? 2006 california micro devices corp. all rights reserved. 05/08/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 l tel: 408.263.3214 l fax: 408.263.7846 l www.cmd.com 1 cm3205 preliminary features ? 5a continuous current from v ddq ? 1.8v to 2.6v adjustable v ddq output voltage ? 600 - mv typical v ddq dropout voltage at 5a ?v tt tracking at 50% of v ddq ? source and sink up to 2a v tt current ? excellent load and line regulation, low noise ? fast transient response ? meets jedec ddr-i sdram power spec. ? linear regulator design requires no inductors and has low external component count ? integrated power mosfets ? dual purpose adj/shutdown pin ? built-in over-current limit with short-circuit foldback and thermal shutdown for v ddq and v tt ? 5ma quiescent current ? to252 andto263 packages for high performance thermal dissipation and easy pc board layout ? optional rohs compliant lead-free packaging applications ? ddr memory and active termination buses ? desktop computers, servers ? residential and enterprise gateways ? dsl modems ? routers and switchers ? dvd recorders ? 3d agp cards ? lcd tv and stb product description the cm3205 is a dual-outpu t, low noise linear regula- tor designed to meet sstl-2 and sstl-3 specifica- tions for ddr-sdram v ddq supply and termination voltage v tt supply. with integrated power mosfet?s, the cm3205 can source up to 5a of v ddq current, and source or sink up to 2a v tt current. the typical drop- out voltage for v ddq is 600 - mv at 5a load current. the cm3205 provides fast response to transient load changes. load regulation is excellent, less than 1%, from no load to full load. it also has built-in over-current limits and thermal shutdown at 170 c . the cm3205 is packaged in an easy-to-use 5-pin d 2 pak (to263-5) and dpak (to252-5). low thermal resistance (48 c /w) allows it to withstand 1.7w (1) dis- sipation at 85 c ambient. it can operate over the indus- trial ambient temperature range of ?40 c to 85 c . 15 4 3 2 2.50v, 5a dl0 vddq chip set dln ddr memory ref 845 887 vddq rt0 rtn 680u 680u 680u 3.3v 1.25v, 2.5a s/d 1u 1k 4.7u 4.7u 4.7u adjsd gnd vddq vtt vin cm3205 v ref typical application ddr v ddq and termination voltage regulator obsolete product
? 2006 california micro devices corp. all rights reserved. 2 490 n. mccarthy blvd., milpitas, ca 95035-5112 l tel: 408.263.3214 l fax: 408.263.7846 l www.cmd.com 05/08/06 cm3205 preliminary ordering information note 1: parts are shipped in tape & reel form unless otherwise specified. specifications package / pinout diagram note: this drawing is not to scale. 5-lead to-252-5 package 1 2 3 4 5 to p v i e w adjsd v ddq gnd v in v tt CM3205-00TP 5-lead to-263-5 package 1 2 3 4 5 top view adjsd v ddq gnd v in v tt cm3205-00tn part numbering information pins package lead-free finish ordering part number 1 part marking 5 to-263-5 cm3205-00tn 5 to-252-5 CM3205-00TP absolute maxi mum ratings parameter rating units v in to gnd [gnd - 0.3] to +6.0 v pin voltages v ddq ,v tt to gnd adjsd to gnd [gnd - 0.3] to +6.0 [gnd - 0.3] to +6.0 v v storage temperature range -65 to +150 c operating temperature range -40 to +85 c lead temperature (soldering, 10s) 300 c package pinout obsolete product
? 2006 california micro devices corp. all rights reserved. 05/08/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 l tel: 408.263.3214 l fax: 408.263.7846 l www.cmd.com 3 cm3205 preliminary electrical operating characteristics (see note 1) v in = 3.3v, typical values are at t a = 25c (unless otherwise specified) symbol parameter conditions min typ max unit s vin v in supply voltage range 3.15 3.30 3.50 v v uvlo under-voltage lockout all outputs are no load 2.4 2.7 2.9 v uvlo hysterisis 100 mv i q quiescent current v ddq = 0v, v tt = 0v, adjsd = 3.3v (shutdown) 3ma v ddq = 2.5v, v tt = 1.25v, (no load) 5ma v ddq regulator output current limit v out = 2.5v 6.0 8.0 a v ref reference voltage 1.203 1.215 1.227 v i bias input bias current (i adj )vadjsd = v ref 30 200 na v r load load regulation i o = 10 ma to 5a 1 % v r line line regulation v in = 3.15v to 3.5v, i o = 10 ma 0.5 % v dropout dropout voltage v in = 3.15v, i o = 5a 600 mv v tt regulator output current limit (source) v out = 1.25v 2 2.5 a output current limit (sink) v out = 1.25v 2 2.5 a v r vttload load regulation i o = 0a to 2a 1 % i o = 0a to -2a 1 % over temperature protection thermal shutdown temperature 170 c thermal shutdown hysteresis 50 c specifications (cont?d) obsolete product
? 2006 california micro devices corp. all rights reserved. 4 490 n. mccarthy blvd., milpitas, ca 95035-5112 l tel: 408.263.3214 l fax: 408.263.7846 l www.cmd.com 05/08/06 cm3205 preliminary vddq v s. t e mpe rature 2.49 2.495 2.5 2.505 2.51 -40 -20 0 20 40 60 80 100 120 140 temperature o c vddq (v) vddq vs. load current 0 0.5 1 1.5 2 2.5 3 0246810 iddq (a) vddq (v) ta=25 o c vin=3.3v vddq dropout vs. iddq 0 100 200 300 400 500 600 012345 iddq (a) dropout voltage (mv) vtt vs. load current 0.0 0.5 1.0 1.5 2.0 2.5 -4 -2 0 2 4 itt (a) vtt (v) source vt t v s. vddq 0.75 0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65 1.5 1.75 2 2.25 2.5 2.75 3 3.25 vddq (v) vtt (v) sink vin vddq vtt 1ms/div 1v/div uvlo startup into full load vddq=2.5v ta=25 o c typical operating curves obsolete product
? 2006 california micro devices corp. all rights reserved. 05/08/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 l tel: 408.263.3214 l fax: 408.263.7846 l www.cmd.com 5 cm3205 preliminary pin descriptions vddq transient response vtt transient response v in =3.3v i out step: 10ma ~ 3a v tt v ddq i out i out v in =3.3v i out step: -2.5a ~ +2.5a pin descriptions pin(s) name description 1adjsd this pin is for v ddq output voltage adjustment. the v ddq output voltage is set using an external resistor divider connected to adjs d. the output voltage is determined by the following formula: where r1 is the ground-side resistor and r2 is the upper resistor of the divider. connect these resistors to the v ddq output at the point of regulation. in addition, this input functions as a sh utdown pin. apply a voltage higher than v in -1.2v to this pin to simultaneously shutdown both v ddq and v tt outputs. the outputs are restored when the voltage on this pin falls below v in -1.2v. a low-leakage diode in series with the shutdown input signal is recommended to avoid interference with the voltage adjustment setting. 2 v ddq v ddq regulator output voltage pin. 3gnd ground reference pin. the back tab is also ground and serves as the package heatsink. it should be soldered to the circuit board copper to remove excess heat from the ic. 4 v in input voltage pin, typically 3.3v from the power supply. 5 v tt v tt regulator output voltage pin, which is preset to 50% of v ddq . v ddq 1.215v r1 r2 + r1 -------------------- - = typical operating characteristics obsolete product
? 2006 california micro devices corp. all rights reserved. 6 490 n. mccarthy blvd., milpitas, ca 95035-5112 l tel: 408.263.3214 l fax: 408.263.7846 l www.cmd.com 05/08/06 cm3205 preliminary application information powering ddr memory double-data-rate (ddr) memory has provided a huge step in performance for personal computers, servers and graphic systems. as is apparent in its name, ddr operates at double the data rate of earlier ram, with two memory accesses per cycle versus one. ddr sdram's transmit data at bo th the rising falling edges of the memory bus clock. ddr?s use of stub series terminated logic (sstl) topology improves noise immunity and power-supply rejection, while reducing power dissipation. to achieve this performance improvement, ddr requires more complex power management architecture than previ- ous ram technology. unlike the conventional dram technology, ddr sdram uses differential inputs and a reference volt- age for all interface signals. this increases the data bus bandwidth, and lowers the system power con- sumption. power consumption is reduced by lower operating voltage, a lower signal voltage swing associ- ated with stub series terminated logic (sstl_2) and by the use of a termination voltage, v tt . sstl_2 is an industry standard, defined in jedec document jesd8-9. sstl_2 maintains high-speed data bus sig- nal integrity by reducing transmission reflections. jedec further defines the ddr sdram specification in jesd79c. ddr memory requires three tightly regulated voltages: v ddq , v tt , and v ref (see figure 1 ). in a typical sstl_2 receiver, the higher current v ddq supply volt- age is normally 2.5v with a tolerance of 200 - mv. the active bus termination voltage, v tt , is half of v ddq . v ref is a reference voltage that tracks half of v ddq , 1%, and is compared with the v tt terminated signal at the receiver. v tt must be within 40 - mv of v ref . figure 1. typical ddr terminations, class ii 9 , 1 3.3v 9 ' ' 4 1.22v 9 7 7 * 1 ' 2.50v, 5a $ ' - 6 ' 5 5 shut down cm3205 x ) x ) x ) x ) x ) vddq/2, 2.5a
9 ' ' 4
9 ' ' 4 & x u u h q w / l p l w & x u u h q w / l p l w & x u u h q w / l p l w 2 7 3 6 k x w g r z q 8 9 / 2 % d q g j d s x ) transmitter vddq vtt (=vddq/2) vddq receiver rs = 25 line rt = 25 vref (=vddq/2) functional block diagram obsolete product
? 2006 california micro devices corp. all rights reserved. 05/08/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 l tel: 408.263.3214 l fax: 408.263.7846 l www.cmd.com 7 cm3205 preliminary the v tt power requirement is proportional to the num- ber of data lines and the resistance of the termination resistor, but does not vary with memory size. in a typi- cal ddr data bus system ea ch data line termination may momentarily consume 16.2 - ma to achieve the 405 - mv minimum over v tt needed at the receiver: a typical 128 mbyte sstl-2 memory system, with 192 terminated lines, has a worst-case maximum v tt sup- ply current up to 3.11a. however, a ddr memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. these high current peaks can be handled by the v tt external capacitor. in a real memory system, the con- tinuous average v tt current level in normal operation is less than 200 ma. the v ddq power supply, in addition to supplying cur- rent to the memory banks, could also supply current to controllers and other circuitry. the current level typi- cally stays within a range of 2.0a to 3.0a, with peaks up to 4.0a or more, depending on memory size and the computing operations being performed. the tight tracking requirements and the need for v tt to sink, as well as source, current provide unique chal- lenges for powering ddr sdram. cm3205 regulator the cm3205 dual output linear regulator provides all of the power requirements of ddr memory by combining two linear regulators into a single to-263 or to-252 5- lead package. the v ddq regulator can supply up to 5a continuous current, and the two-quadrant v tt termina- tion regulator has current si nk and source capability to 2a. the v ddq linear regulator uses a pmos pass element for a very low dropout voltage, typically 600mv at a 5a output. the output voltage of the v ddq regula- tor can be set by an external voltage divider. the sec- ond output, v tt , is regulated at v ddq /2 by an internal resistor divider. the v tt regulator can source, as well as sink, up to 2a continuous current. the cm3205 is designed for optimal operation from a nominal 3.3vdc bus, but can work with v in as high as 5v. when operat- ing at higher v in voltages, attention must be given to the increased package power dissipation and propor- tionally increased heat generation. v ref is typically routed to inputs with high impedance, such as a comparator, with little current draw. an ade- quate v ref can be created with a simple voltage divider of precision, matched resistors from v ddq to ground. a small ceramic bypass capacitor can also be added for improved noise performance. input and output capacitors the cm3205 requires that at least a 680 f electrolytic capacitor be located near the v in pin for stability and to maintain the input bus voltage during load transients. an additional 4.7 f ceramic capacitor between the v in (pin 4) and the gnd (pin 5), located as close as possi- ble to those pins, is recommended to ensure stability. a minimum of a 680 f electrolytic capacitor is recom- mended for the v ddq output. an additional 4.7 f ceramic capacitor between the v ddq (pin 2) and gnd, located very close to those pins, is recommended. a minimum of a 680 f, electrolytic capacitor is recom- mended for the v tt output. this capacitor should have low esr to achieve best output transient response. sp or oscon capacitors provide low esr at high fre- quency, and thus are a good choice. in addition, place a 4.7 f ceramic capacitor between the v tt pin (pin 5) and gnd, located very close to those pins. the total esr must be low enough to keep the transient within the v tt window of 40 - mv during the transition for source to sink. an av erage current step of 0.5a requires: both outputs will remain stab le and in regulation even during light or no load conditions. adjusting v ddq output voltage the cm3205 internal bandgap reference is set at 1.215v. the v ddq voltage is adjustable by using a resistor divider, r1 and r2: i terminaton 405mv rt 25 () --------------------- - 16.2ma == esr 40mv 1a --------------- < 40m = v out v adj 1 r2 r1 ------ - + ?? ?? = application information (cont?d) obsolete product
? 2006 california micro devices corp. all rights reserved. 8 490 n. mccarthy blvd., milpitas, ca 95035-5112 l tel: 408.263.3214 l fax: 408.263.7846 l www.cmd.com 05/08/06 cm3205 preliminary where v adj = 1.215v ( - 1%). for best regulator stabil- ity, we recommend that r1 and r2 not exceed 10 - k each. shutdown pin 1 (adjsd) also serves as a shutdown pin. when pin 1 is pulled high, > (v in - 1.2v), the v ddq output is turned off and both source and sink mosfet?s of the v tt regulator are set to a high impedance state. during shutdown, the quiescent current is reduced to less than 3ma, independent of output load. it is recommended that a 1n91 4 or equivalent low leak- age diode be placed between pin 1 and an external shutdown signal to prevent interference with the adj pin?s normal operation. when the diode anode is pulled low, or left open, the cm3205 is again enabled . current limit, foldback and over-temperature pro- tection the cm3205 features internal current limiting with ther- mal protection. during normal operation, v ddq limits the output current to approximately 8a and v tt limits the output current to approximately 2a. when v tt is current limiting into a hard short circuit, the output cur- rent folds back to a lower level, about 1.5a, until the over-current condition ends. while current limiting is designed to prevent gross de vice failure, care should be taken not to exceed the power dissipation ratings of the package. if the junction temperature of the device exceeds 170 - c (typical), the thermal protection cir- cuitry triggers and shuts down both outputs. once the junction temperature has cooled to below about 120 - c, the cm3205 returns to normal operation. thermal considerations both the to-252 and the to-263 packages provide a very effective thermal conduc tion path from the silicon junction into the pc board to which it is mounted. see figure 2 below. these surface mount packages have a large metal tab that solders to the pc board, where the ground plane can serve as heatsink. this metal tab connects internally to gnd (pin 3). a top-layer ground plane is the best in terms of convection air-cooling, a bottom-layer ground plane is less effective, and a mid- dle layer ground plane of a multiple-layer pc board is the least effective. we recommend the metal tab of cm3205 be soldered to a minimum of 3 square inches of ground plane on the top side of the pc board. use 20 or more plate- through vias to connect the top layer ground plane to ground planes on other layers. when measured in accordance to jedec jesd51-3, under natural convection without forced airflow, the theta junction-to-air ( ja) resistance is approximately 48 - c/watt for the cm3205-00tn (to-263-5), and 55 - c/watt for the CM3205-00TP (to-252-5). figure 2. thermal layout ground plane vias (0.3mm diameter) (top view) (side view) bottom ground plane via top ground plane power trace via (0.3mm diameter) application information (cont?d) obsolete product
? 2006 california micro devices corp. all rights reserved. 05/08/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 l tel: 408.263.3214 l fax: 408.263.7846 l www.cmd.com 9 cm3205 preliminary to-263-5 mechanical specifications dimensions for cm3205-00tn devices packaged in 5- lead, standard to-263 packages are presented below. * this is an approximate amount which may vary. package dimensions for standard to-263 package dimensions package to-263 pins 5 dimensions millimeters inches min max min max a 4.34 4.60 0.171 0.181 b 0.74 0.89 0.029 0.035 c 0.33 0.43 0.013 0.017 d 8.92 9.17 0.351 0.361 e 10.16 10.67 0.400 0.420 e 1.70 ref 0.067 ref l 14.61 15.88 0.575 0.625 l1 2.29 2.79 0.090 0.110 l2 1.14 1.40 0.045 0.055 m 0.23 0.30 0.009 0.012 p 1.14 1.40 0.045 0.055 s 1.40 1.91 0.055 0.075 # per tape and reel 750 pieces controlling dimension: inches mechanical package diagrams top view 5 4 e d l b a side view e p leadform 123 18-22 l2 s c 7 7 3 l1 m seating plane 0 -8 pin 1 marking mechanical details obsolete product
? 2006 california micro devices corp. all rights reserved. 05/08/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 l tel: 408.263.3214 l fax: 408.263.7846 l www.cmd.com 10 cm3205 preliminary to-252-5 mechanical specifications dimensions for CM3205-00TP devices packaged in 5- pin to-252 packages are presented below. package dimensions for to252-5 package dimensions package to-252 pins 5 dimensions millimeters inches min max min max a 6.40 6.80 0.252 0.268 b 5.20 5.50 0.205 0.217 c 6.80 7.20 0.268 0.283 d 2.20 2.80 0.087 0.110 g 0.40 0.60 0.016 0.024 h 2.20 2.40 0.087 0.094 j 0.45 0.55 0.018 0.022 k 0 0.15 0 0.006 l 0.90 1.50 0.035 0.059 m 5.40 5.80 0.213 0.228 p 1.27 ref 0.05 ref s 0.50 0.80 0.020 0.031 # per tape and reel 750 pieces controlling dimension: inches mechanical package diagrams front view 5 4 p m c g h side view a j leadform 123 l2 c 0 -15 l k seating plane 0 -10 pin 1 marking back view d1 b e1 d s mechanical details (cont?d) obsolete product
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