description avagos ammc-5033 is a mmic power amplifer designed for use in wireless transmitters that operate within 17.7 ghz to 32 ghz range. at 25 ghz, it provides 27 dbm of output power (p-1db) and 20 db of small- signal gain from a small easy-to-use device. the device has input and output matching circuitry for use in 50 environ - ments. the ammc- 5033 also integrates a temperature compensated rf power detection circuit that enables power detection of 0.1 v/w at 22 ghz. for improved reliability and moisture protection, the die is passivated at the active areas. features ? wide frequency range: 17.7 C 32 ghz ? high power: p-1db @ 25 ghz = 27 dbm ? high gain: 20 db ? return loss: input: -13 db, output: C20 db ? integrated rf power detector applications ? designed for use in transmitters that operate in various frequency bands between 17.7 ghz and 32 ghz. ? can be driven by the ammc-5040 (20-40 ghz) or the ammc-5618 (6-20 ghz) mmic amplifers, increasing the power handling capability of transmitters requiring linear operation. note: these devices are esd sensitive. the following precautions are strongly recommended: ensure that an esd approved carrier is used when dice are transported from one destination to another. personal grounding is to be worn at all times when handling these devices. ammc-5033 17.7 - 32 ghz power amplifer data sheet ammc-5033 absolute maximum ratings [1] symbol parameters/conditions units min. max. v d1,2 positive drain voltage v 7 v g1 , v gg gate supply voltage v -3 0.5 det bias applied detector bias v 7 (optional) i d1 first stage drain current ma 320 i d2 second stage drain current ma 640 p in cw input power dbm 23 t ch operating channel temp. c +150 t stg storage case temp. c -65 +150 t max maximum assembly temp. c +300 (60 sec max) note: 1. operation in excess of any one of these conditions may result in permanent damage to this device. chip size: 2730 x 1300 m (108 x 51.6 mils) chip size tolerance: 10 m (0.4 mils) chip thickness: 100 10 m (4 0.4 mils) pad dimensions: 80 x 80 m (2.95 0.4 mils)
2 ammc-5033 dc specifcations/physical properties [1] symbol parameters and test conditions units min. typ. max. i d1 first stage drain supply current ma 280 320 (v d1 = 3.5 v, v g1 = open, v gg set for i d2 typical) i d2 second stage drain supply current v 500 (v d2 = 5 v, v g1 = open, v gg set for i d2 typical) vgg gate supply operating voltage v -0.95 -0.6 -0.4 (i d1(q) + i d2(q) = 780 (ma)) detbias detector bias voltage (optional) v vd2 c1(ch-bs) first stage thermal resistance [2] c/w 31 (backside temperature, tb = 25c) c2(ch-bs) second stage thermal resistance [2, 3] c/w 19 (backside temperature, tb = 25c) notes: 1. backside temperature t b = 25c unless otherwise noted. 2. channel-to-backside thermal resistance ( ch-b) = 42c/w at tchannel (tc) = 150c as measured using infrared microscopy. thermal resis - tance at backside temperature (tb) = 25c calculated from measured data. ammc-5033 rf specifcations [4, 5] tb = 25c, v d1 = 3.5 v, v d2 = 5 v, i d1(q) = 280 ma, i d2(q) = 500 ma, zo = 50 lower band mid band upper band specifcations specifcations specifcations parameters and (17.7 - 21 ghz) (21 - 26.5 ghz) (26.5 - 32 ghz) symbol test condition unit min. typ. max. min. typ. max. min. typ. max. gain small-signal gain [5] db 20 22 17.5 20 16.5 18.5 p -1db output power at 1db gain db 23.5 25 25.5 27 25 26.5 compression [6] p -3db output power at 3db gain db 27 28 27 compression [6] oip 3 output third order intercept dbm 27 29 29 32 29 32 point; [6] ; ff = 2 mhz; pin = +2 dbm rl in input return loss [5] db 11.5 13.5 11 13 11 13 rl out output return loss [5] db 14 20 14 19 15 22 isolation min. reverse isolation db 47 48 46 notes: 4. data measured in wafer form t b = 25c. 5. 100% on-wafer rf test is done at frequency = 17.7, 21, 26.5 and 32 ghz. 6. 100% on-wafer test frequency = 17.7, 26.5 and 32 ghz.
3 ammc-5033 typical performances (t b = 25c, v d1 = 3.5 v, i d1 = 280 ma, v d2 = 5 v, i d2 = 500 ma, z in = z out = 50 ) figure 5. output 3rd order intercept point figure 4. noise fgure figure 3. output power at 1 db and 3 db gain compression figure 2. return loss (input and output) figure 1. gain and reverse isolation frequency (ghz) s21 (db) s12 (db) 17 19 21 23 25 27 29 31 33 40 35 30 25 20 15 10 5 0 0 -20 -40 -60 -80 s21 (db) s12 (db) frequency (ghz) return loss (db) 17 19 21 23 25 27 29 31 33 0 -5 -10 -15 -20 -25 -30 s22 (db) s11 (db) frequency (ghz) p-1 (dbm), p-3 (dbm) 17 19 21 23 25 27 29 31 33 30 28 26 24 22 20 p-1 p-3 frequency (ghz) noise figure (db) 17 19 21 23 25 27 29 31 33 10 8 6 4 2 0 frequency (ghz) ip3 (dbm) 17 19 21 23 25 27 29 31 33 38 36 34 32 30 28 26 24
4 ammc-5033 typical performance curves (over temperature and voltage) figure 6. linear and log detector voltage and output power, freq. = 22 ghz, det_b = 5 v figure 7. gain and v d2 voltage, v d1 = 3.5 v (constant) figure 8. output power at 1 db gain compression and v d2 voltage, v d1 = 3.5 v (constant) figure 9. return-loss with temperature rf output power (dbm) (det_r)-(det_o) (v) (det_r)-(det_o) (v) 05 30 10 15 20 25 0.10 0.08 0.06 0.04 0.02 0.00 0.1 0.01 0.001 frequency (ghz) gain (db) 17 19 21 23 25 27 29 31 33 40 30 20 10 0 5v/0.5a 4v/0.5 3.5v/0.5a frequency (ghz) p-1 (dbm) 17 19 21 23 25 27 29 31 33 30 28 26 24 22 20 5v/0.5a 4v/0.5 3.5v/0.5a frequency (ghz) s11 and s22 (db) 17 19 21 23 25 27 29 31 33 0 -5 -10 -15 -20 -25 -30 s11_85 c s11_25 c s11_-40 c s22_85 c s22_25 c s22_-40 c
5 figure 11. output power, pae, and total drain. current vs. input power at 25 ghz figure 10. output power at 1 db gain compression and temperature figure 12. gain with temperature frequency (ghz) p-1 (dbm) 17 19 21 23 25 27 29 31 33 30 28 26 24 22 20 85 c 25 c -40 c pin (dbm) pout (dbm), pae (%) id (ma) -30 -20 20 -10 0 10 30 25 20 15 10 5 0 1200 1000 800 600 400 200 0 pout pae id frequency (ghz) s21 (db) 17 19 21 23 25 27 29 31 33 50 40 30 20 10 0 -10 -20 -30 85 c 25 c -40 c
6 typical scattering parameters [1] (t b = 25c, v d1 = 3.5 v, i d1 = 280 ma, v d2 = 5 v, i d2 = 500 ma, z in = z out = 50 ) freq s11 s21 s12 s22 [ghz] db mag phase db mag phase db mag phase db mag phase 1 -10.7 0.29 173 -51.1 0.003 -163 -95.1 1.77e-05 128 -0.5 0.95 -26 2 -11.0 0.28 167 -70.1 0 79 -83.1 6.97e-05 76 -0.7 0.92 -51 3 -11.4 0.27 161 -46.6 0.005 -103 -74.5 1.89e-04 81 -1.2 0.87 -76 4 -12.1 0.25 153 -37.3 0.014 72 -74.5 1.88e-04 69 -2.2 0.78 -95 5 -15.3 0.17 140 -22.6 0.074 -31 -80.3 9.66e-05 -47 -2.4 0.76 -112 6 -12.2 0.25 149 -20.4 0.096 144 -80.1 9.90e-05 -126 -2.8 0.73 -130 7 -14.0 0.2 143 -20.5 0.095 79 -80.3 9.68e-05 94 -4.0 0.63 -146 8 -15.3 0.17 139 -25.4 0.053 -3 -74.1 1.97e-04 35 -4.2 0.62 -150 9 -17.6 0.13 138 -33.1 0.022 108 -81.4 8.52e-05 -62 -3.5 0.67 -166 10 -19.4 0.11 145 -18.9 0.113 54 -81.4 8.56e-05 -162 -3.8 0.64 177 11 -18.6 0.12 152 -18.2 0.123 -37 -81.3 8.59e-05 151 -4.4 0.6 161 12 -19.7 0.1 141 -29.0 0.035 -77 -74.6 1.86e-04 178 -5.2 0.55 146 13 -24.5 0.06 134 -15.4 0.169 103 -81.3 8.65e-05 -180 -6.3 0.48 131 14 -27.4 0.04 159 0.9 1.107 61 -81.2 8.70e-05 -20 -7.9 0.41 115 15 -30.6 0.03 -148 12.7 4.316 -8 -74.6 1.86e-04 152 -10.1 0.31 100 16 -24.1 0.06 -121 22.6 13.52 -87 -76.2 1.55e-04 144 -13.3 0.22 86 17 -21.2 0.09 -116 28.8 27.62 174 -74.7 1.84e-04 -164 -20.5 0.09 76 18 -18.0 0.13 -116 28.7 27.25 73 -64.8 5.75e-04 165 -20.0 0.1 133 19 -15.5 0.17 -123 26.4 20.92 3 -64.3 6.08e-04 123 -19.4 0.11 130 20 -14.0 0.2 -133 24.7 17.18 -53 -64.4 6.03e-04 90 -19.1 0.11 135 21 -13.3 0.22 -142 23.4 14.82 -103 -69.7 3.27e-04 76 -18.7 0.12 133 22 -13.0 0.22 -151 22.4 13.2 -151 -58.2 1.23e-03 80 -18.5 0.12 129 23 -12.9 0.23 -157 21.5 11.9 164 -63.3 6.80e-04 92 -19.0 0.11 124 24 -12.9 0.23 -163 20.8 10.97 121 -61.0 8.96e-04 44 -20.7 0.09 119 25 -13.0 0.23 -172 20.3 10.36 79 -66.1 4.97e-04 55 -21.8 0.08 122 26 -13.3 0.22 -178 19.9 9.895 37 -64.3 6.09e-04 53 -22.9 0.07 131 27 -13.9 0.2 174 19.7 9.691 -6 -63.1 7.00e-04 58 -22.9 0.07 135 28 -14.9 0.18 165 19.5 9.457 -49 -60.2 9.75e-04 68 -22.6 0.07 142 29 -15.8 0.16 155 19.4 9.384 -94 -61.9 8.00e-04 38 -22.1 0.08 136 30 -17.0 0.14 140 19.3 9.247 -141 -56.3 1.53e-03 25 -22.4 0.08 125 31 -19.1 0.11 113 19.1 8.972 171 -57.7 1.31e-03 15 -24.9 0.06 117 32 -21.0 0.09 75 18.6 8.519 121 -58.2 1.23e-03 1 -31.9 0.03 126 33 -20.5 0.1 30 18.1 7.989 69 -56.0 1.59e-03 -15 -31.4 0.03 -148 34 -17.0 0.14 -9 17.2 7.281 14 -57.7 1.31e-03 -12 -24.4 0.06 -141 35 -14.9 0.18 -31 16.2 6.44 -43 -59.0 1.12e-03 -36 -20.0 0.1 -145 36 -12.8 0.23 -45 14.6 5.378 -104 -60.8 9.14e-04 -40 -16.2 0.16 -152 37 -10.7 0.29 -58 12.1 4.014 -171 -62.9 7.13e-04 -31 -13.1 0.22 -167 38 -9.8 0.33 -71 7.7 2.42 122 -57.1 1.40e-03 -55 -11.1 0.28 174 39 -9.1 0.35 -77 1.9 1.238 65 -61.0 8.94e-04 -61 -10.1 0.31 154 40 -8.5 0.38 -85 -3.5 0.671 14 -60.9 9.04e-04 -59 -9.8 0.33 134 41 -8.6 0.37 -92 -9.2 0.347 -41 -67.6 4.15e-04 -65 -9.7 0.33 116 42 -8.6 0.37 -92 -16.1 0.157 -90 -59.2 1.09e-03 -82 -10.1 0.31 98 43 -8.0 0.4 -92 -23.2 0.069 -134 -61.0 8.95e-04 -75 -10.6 0.29 80 44 -7.6 0.42 -90 -32.0 0.025 -172 -62.0 7.96e-04 -59 -11.4 0.27 62 45 -6.0 0.5 -87 -31.7 0.026 -148 -64.6 5.91e-04 -123 -12.3 0.24 41 46 -4.4 0.6 -93 -40.7 0.009 -164 -61.1 8.84e-04 -82 -13.2 0.22 21 47 -3.5 0.67 -98 -46.2 0.005 62 -102.4 7.57e-06 -171 -14.2 0.2 0 48 -2.7 0.74 -102 -58.4 0.001 80 -60.1 9.93e-04 176 -14.8 0.18 -27 49 -1.8 0.81 -111 -46.4 0.005 50 -59.2 1.10e-03 -69 -14.7 0.18 -49 50 -1.7 0.83 -118 -44.2 0.006 113 -61.9 8.00e-04 26 -14.9 0.18 -77 note: 1. data obtained from on-wafer measurements.
7 biasing and operation the recommended quiescent dc bias condition for optimum efficiency, performance, and reliability is v d1 = 3.5 volts and v d2 = 5 volts with v gg set for i d1 + i d2 = 780 ma (no connection to v g1 ). this bias ar - rangement results in default quiescent drain currents i d1 = 280 ma, i d2 = 500 ma. a single dc gate supply connected to v gg will bias all gain stages. if operation with both v d1 and v d2 at 5 volts is desired, an additional wire bond connection from the v g1 pad to v gg external bypass chip capacitor (shorting v g1 to v gg ) will balance the current in each gain stage. v gg (= v g1 ) can be adjusted for i d1 + i d2 = 780 ma. muting can be accomplished by setting v g1 and/or v gg to the pinch- of voltage v p . an optional output power detector network is also provided. detector sensitivity can be adjusted by bias - ing the diodes with typically 1 to 5 volts applied to the det- bias terminal. simply connecting det-bias to the v d2 supply is a convenient method of biasing this detector network. the diferential voltage between the det-ref and det-out pads can be correlated with the rf power emerging from the rf output port. the detected volt - age is given by: v = (v ref - v det ) - v ofs where v ref is the voltage at the det_ref port, v det is a voltage at the det_out port, and v ofs is the zero-in - put-power ofset voltage. there are three methods to calculate v ofs : 1. v ofs can be measured before each detector measure - ment (by removing or switching of the power source and measuring v ref - v det ). this method gives an error due to temperature drift of less than 0.0002 db/c. 2. v ofs can be measured at a single reference temperature. the drift error will be less than 0.25 db. 3. v ofs can either be characterized over temperature and stored in a lookup table, or it can be measured at two temperatures and a linear ft used to calculate v ofs at any temperature. this method gives an error close to method #1. with reference to figure 13, the rf input is dc coupled to a shunt 50 resistor but it is dc blocked to the input of the frst stage. the rf output is dc blocked to the output of the second stage, however, it is dc coupled to the detector bias circuit. if the output detector is biased using the on-chip optional det-bias network, an external dc blocking capacitor may be required at the rf output port. no ground wires are needed since ground connections are made with plated through-holes to the backside of the device. assembly techniques the backside of the ammc- 5033 chip is rf ground. for microstripline applications, the chip should be attached directly to the ground plane (e.g., circuit carrier or heat - sink) using electrically conductive epoxy. [1,2] for best performance, the topside of the mmic should be brought up to the same height as the circuit sur - rounding it. this can be accomplished by mounting a gold plated metal shim (same length and width as the mmic) under the chip, which is of the correct thickness to make the chip and adjacent circuit coplanar. the amount of epoxy used for chip and or shim at - tachment should be just enough to provide a thin fllet around the bottom perimeter of the chip or shim. the ground plane should be free of any residue that may jeopardize electrical or mechanical attachment. the location of the rf bond pads is shown in figure 14. note that all the rf input and output ports are in a ground-signal-ground confguration. rf connections should be kept as short as reasonable to minimize performance degradation due to undesirable series inductance. a single bond wire is sufcient for signal connections, however double-bonding with 0.7 mil gold wire or the use of gold mesh is recommended for best performance, especially near the high end of the frequency range. thermosonic wedge bonding is the preferred method for wire attachment to the bond pads. gold mesh can be attached using a 2 mil round tracking tool and a tool force of approximately 22 grams with an ultrasonic power of roughly 55 db for a duration of 76 8 ms. a guided wedge at an ultrasonic power level of 64 db can be used for the 0.7 mil wire. the recommended wire bond stage temperature is 150 2c. caution should be taken to not exceed the absolute maximum rating for assembly temperature and time. the chip is 100 m thick and should be handled with care. this mmic has exposed air bridges on the top surface and should be handled by the edges or with a custom collet (do not pick up die with vacuum on die center.) this mmic is also static sensitive and esd handling precautions should be taken. notes: 1. ablebond 84-1 lm1 silver epoxy is recommended. 2. eutectic attach is not recommended and may jeopardize reliability of the device.
8 figure 13. ammc-5033 schematic figure 14. ammc-5033 bonding pad locations, dimensions are in microns v d1 input rf _ 50 v d2 dq v gg v g1 250 1000 v d2 dq dq gnd gnd g vg g 50 50 50 out rf _ ref_ d 2 out det _ . bias det _ . ref det _ . d 1 gnd gnd
ordering information: ammc-5033-w10 = 10 devices per tray AMMC-5033-W50 = 50 devices per tray for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries. data subject to change. copyright ? 2005-2009 avago technologies limited. all rights reserved. obsoletes 5989-3935en av02-0682en - february 25, 2009 figure 15. ammc-5033 assembly diagram 68 pf 68 pf ammc-5033 rfi v d1 , 280 ma v d2 , 500 ma rfo rfinput rfoutput notes: 1. 1f capacitors on gate and drain lines not shown required. v d1 v gg v ee v d2 v d2
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