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xicor, inc. 1994, 1995, 1996 patents pending 7064 1 0 2/4/98 t0/c0/d0 sh 1 characteristics subject to change without notice 8k X25383/85 1k x 8 bit selectable timeout watchdog & v cc supervisory circuit w/serial e 2 prom features selectable timeout watchdog timer low vcc detection and reset assertion reset signal valid to vcc=1v save critical data with idlock memory idlock first or last page, any 1/4 or lower 1/2 of e 2 prom array long battery life with low power consumption <50 m a max standby current, watchdog on ?1 m a max standby current, watchdog off <3ma max active current during write <400 m a max active current during read 1.8v to 3.6v, 2.7v to 5.5v and 4.5v to 5.5v power supply versions 5mhz clock rate minimize programming time 16 byte page write mode self-timed write cycle 5ms write cycle time (typical) spi modes (0,0 & 1,1) built-in inadvertent write protection power-up/power-down protection circuitry write enable latch write protect pin high reliability available packages 8-lead tssop 8-lead soic description these devices combine three popular functions, watch- dog timer, supply voltage supervision, and serial e 2 prom memory in one package. this combination low- ers system cost, reduces board space requirements, and increases reliability. the watchdog timer provides an independent protection mechanism for microcontrollers. during a system failure, the device will respond with a reset /reset signal after a selectable time-out interval. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the users system is protected from low voltage condi- tions by the devices low vcc detection circuitry. when vcc falls below the minimum vcc trip point, the system is reset. reset /reset is asserted until vcc returns to proper operating levels and stabilizes. the memory portion of the device is a cmos serial e 2 prom array with xicors idlock memory. the array is internally organized as x 8. the device features a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes xicors proprietary direct write tm cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years. block diagram data register command decode & control logic reset control low voltage sense write control x - decode logic status register watchdog page decode logic serial e 2 prom array high voltage control si so sck cs reset /reset v cc wp 7036 frm 01 16 8 timer
X25383/85 2 pin descriptions serial output (so) so is a push/pull ser ial data output pin. dur ing a read cycle , data is shifted out on this pin. data is cloc k ed out b y the f alling edge of the ser ial cloc k. serial input (si) si is a ser ial data input pin. all opcodes , b yte addresses , and data to be wr itten to the memor y are input on this pin. data is latched b y the r ising edge of the ser ial cloc k. serial clock (sck) the ser ial cloc k controls the ser ial b us timing f or data input and output. opcodes , addresses , or data present on the si pin are latched on the r ising edge of the cloc k input, while data on the so pin change after the f alling edge of the cloc k input. chip select ( cs ) when cs is high, the de vice is deselected and the so output pin is at high impedance and unless a non v olatile wr ite cycle is underw a y , the de vice will be in the standb y po w er mode . cs lo w enab les the de vice , placing it in the activ e po w er mode . it should be noted that after po w er-up , a high to lo w tr ansition on cs is required pr ior to the star t of an y oper ation. write protect ( wp ) when wp is lo w , non v olatile wr ites to the de vice are disab led, b ut the par t otherwise functions nor mally . when wp is held high, all functions , including non v olatile wr ites oper ate nor mally . wp going lo w while cs is still lo w will interr upt a wr ite to the de vice . if the inter nal wr ite cycle has already been initiated, wp going lo w will ha v e no aff ect on this wr ite . reset ( reset /reset) reset /reset is an activ e lo w/high, open dr ain out- put which goes activ e whene v er vcc f alls belo w the mini- m um vcc sense le v el v tr ip . it will remain activ e until vcc r ises abo v e the minim um vcc sense le v el f or 200ms . reset /reset will also go activ e if the w atchdog timer is enab led and cs remains either high or lo w longer than the selectab le w atchdog time-out per iod. a f alling edge of cs will reset the w atchdog timer . pin configuration pin names symbol description cs chip select input so serial output si serial input sck serial clock input wp write protect input v ss ground v cc supply voltage reset /reset reset output 8 lead soic X25383/85 cs wp so 1 2 3 4 reset /reset 8 7 6 5 v cc v ss sck si 0.197 0.244 not to scale sck si v ss wp v cc cs so 1 2 3 4 8 7 6 5 8 lead tssop X25383 0.122" 0.252" reset /reset
X25383/85 3 principles of operation the de vice is designed to interf ace directly with the syn- chronous ser ial p er ipher al interf ace (spi) of man y popu- lar microcontroller f amilies . the de vice monitors the b us and asser ts reset /reset output if there is no b us activity within user selctab le time- out per iod or the supply v oltage f alls belo w a preset mini- m um v tr ip . the de vice contains an 8-bit instr uction regis- ter . it is accessed via the si input, with data being cloc k ed in on the r ising edge of sck. cs m ust be lo w dur ing the entire oper ation. all instr uctions ( t ab le 1), addresses and data are tr ans- f erred msb rst. data input on the si line is latched on the rst r ising edge of sck after cs goes lo w . data is out- put on the so line b y the f alling edge of sck. sck is static , allo wing the user to stop the cloc k and then star t it again to resume oper ations where left off . write enable latch the de vice contains a wr ite enab le latch. this latch m ust be set bef ore a wr ite oper ation is initiated. the wren instr uction will set the latch and the wrdi instr uction will reset the latch (figure 3). this latch is automatically reset upon a po w er-up condition and after the completion of a v alid wr ite cycle . status register the rdsr instr uction pro vides access to the status reg- ister . the status register ma y be read at an y time , e v en dur ing a wr ite cycle . the status register is f or matted as f ollo ws: status register/idlock/wdt byte idlock memory xicor s idloc k memor y pro vides a e xib le mechanism to store and loc k system id and par ametr ic inf or mation. there are se v en distinct idloc k memor y areas within the arr a y which v ar y in siz e from one page to as m uch as half of the entire arr a y . these areas and associated address r anges are idloc k ed b y wr iting the appropr iate tw o b yte idloc k instr uction to the de vice as descr ibed in t ab le 1 and figure 7. once an idloc k instr uction has been com- pleted, that idloc k setup is held in the non v olatile status register until the ne xt idloc k instr uction is issued. the sections of the memor y arr a y that are idloc k ed can be read b ut not wr itten until idloc k protection is remo v ed or changed. watchdog timer the w atchdog timer bits , wd0 and wd1, select the w atchdog time-out p er iod. these non v olatile bits are prog r ammed with the wrsr instr uction. read sequence when reading from the e 2 pr om memor y arr a y , cs is rst pulled lo w to select the de vice . the 8-bit read instr uction is tr ansmitted to the de vice , f ollo w ed b y the 16- bit address . after the read opcode and address are sent, the data stored in the memor y at the selected address is shifted out on the so line . the data stored in memor y at the ne xt address can be read sequentially b y contin uing to pro vide cloc k pulses . the address is auto- matically incremented to the ne xt higher address after each b yte of data is shifted out. when the highest address is reached, the address counter rolls o v er to address $0000 allo wing the read cycle to be contin ued inde nitely . the read oper ation is ter minated b y taking cs high. ref er to the read e 2 pr om arr a y sequence (figure 1). t o read the status register , the cs line is rst pulled lo w to select the de vice f ollo w ed b y the 8-bit rdsr instr uc- tion. after the rdsr opcode is sent, the contents of the status register are shifted out on the so line . ref er to the read status register sequence (figure 2). write sequence pr ior to an y attempt to wr ite data into the de vice , the ?r ite enab le latch (wel) m ust rst be set b y issuing the wren instr uction (figure 3). cs is rst tak en lo w , then the wren instr uction is cloc k ed into the de vice . after all eight bits of the instr uction are tr ansmitted, cs m ust then be tak en high. if the user contin ues the wr ite oper ation without taking cs high after issuing the wren instr uction, the wr ite oper ation will be ignored. t o wr ite data to the e 2 pr om memor y arr a y , the user then issues the write instr uction f ollo w ed b y the 16 bit address and then the data to be wr itten. an y un used address bits are speci ed to be ? s? the write oper a- tion minimally tak es 32 cloc ks . cs m ust go lo w and remain lo w f or the dur ation of the oper ation. if the address counter reaches the end of a page and the cloc k contin- 7 6 5 4 3 2 1 0 0 0 0 wd1 wd0 idl2 idl1 idl0 status register bits watchdog time-out (typical) wd1 wd0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled
X25383/85 4 ues , the counter will roll bac k to the rst address of the same page and o v erwr ite an y data that ma y ha v e been pre viously wr itten. f or a wr ite oper ation (b yte or page wr ite) to be com- pleted, cs can only be brought high after bit 0 of the last data b yte to be wr itten is cloc k ed in. if it is brought high at an y other time , the wr ite oper ation will not be com- pleted (figure 4). t o wr ite to the status register , the wrsr instr uction is f ollo w ed b y the data to be wr itten (figure 5). data bits 5, 6 and 7 m ust be ? . read status operation if there is not a non v olatile wr ite in prog ress , the read status instr uction retur ns the id loc k b yte from the status register which contains the id loc k bits idl2-idl0 (fig- ure 1). the id loc k bits de ne the id loc k condition (fig- ure 1/t ab le1). the other bits are reser v ed and will retur n ? when read. see figure 3. if a non v olatile wr ite is in prog ress , the read status instr uction retur ns a high on so . when the non v olatile wr ite cycle is completed, the status register data is read out. cloc king sck is v alid dur ing a non v olatile wr ite in prog ress , b ut is not necessar y . if the sck line is cloc k ed, the pointer to the status register is also cloc k ed, e v en though the so pin sho ws the status of the non v olatile wr ite oper ation (see figure 3). reset /reset operation the reset (X25383) output is designed to go lo w whene v er v cc has dropped belo w the minim um tr ip point and/or the w atchdog timer has reached its prog r ammab le time-out limit. the reset (x25385) output is designed to go high whene v er v cc has dropped belo w the minim um tr ip point and/or the w atchdog timer has reached its prog r ammab le time-out limit. the reset /reset output is an open dr ain output and requires a pull up resistor . operational notes the de vice po w ers-up in the f ollo wing state: the de vice is in the lo w po w er standb y state . a high to lo w tr ansition on cs is required to enter an activ e state and receiv e an instr uction. so pin is high impedance . the wr ite enab le latch is reset. reset signal is activ e f or t purst . data protection the f ollo wing circuitr y has been included to pre v ent inad- v er tent wr ites: a wren instr uction m ust be issued to set the wr ite enab le latch. cs m ust come high at the proper cloc k count in order to star t a non v olatile wr ite cycle . table 1. instruction set and idlock protection byte definition instruction format* instruction name and operation 0000 0110 wren: set the write enable latch (write enable operation) 0000 0100 wrdi: reset the write enable latch (write disable operation) 0000 0001 write status instruction?ollowed by: idlock/wdt byte: (see figure 1) 000w 1 w 2 000 --->no idlock: 00h-00h - - - - - - - >none of the array 000w 1 w 2 001 --->idlock q1: 0000h-00ffh - - - - >lower quadrant (q1) 000w 1 w 2 010 --->idlock q2: 0100h-01ffh - - - - >q2 000w 1 w 2 011 --->idlock q3: 0200h-02ffh - - - - >q3 000w 1 w 2 100 --->idlock q4: 0300h-03ffh - - - - >upper quadrant (q4) 000w 1 w 2 101 --->idlock h1: 0000h-01ffh - - - - >lower half of the array (h1) 000w 1 w 2 110 --->idlock p0: 0000h-000fh - - - - >lower page (p0) 000w 1 w 2 111 --->idlock pn: 03f0h-03ffh - - - - >upper page (pn) 0000 0101 read status: reads status register & provides write in progress status on so pin 0000 0010 write: write operation followed by address and data 0000 0011 read: read operation followed by address w0=wd0bit note: w1=wd1bit
X25383/85 5 figure 2. read operation sequence figure 3. read status operation sequence figure 4. wren/wrdi sequence 0 1 2 3 4 5 6 7 8 9 cs sck si so high imped ance read instr uction (1 byte) byte address (2 byte) d a t a out 15 14 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 cs sck si so nonv ola tile write in pr ogress read st a tus instr uction so high during nonv ola tile write cycle so = st a tus reg bit when no nonv ola tile write cycle ... ... ... i d l 2 i d l 1 i d l 0 w d 0 w d 1 0 1 2 3 4 5 6 7 cs si sck high imped ance so instr uction (1 byte)
X25383/85 6 figure 4. write sequence figure 5. status register write sequence 32 33 34 35 36 37 38 39 sck si cs 0 1 2 3 4 5 6 7 8 9 10 sck si instruction 16 bit address d a t a byte 1 7 6 5 4 3 2 1 0 cs 40 41 42 43 44 45 46 47 d a t a byte 2 7 6 5 4 3 2 1 0 d a t a byte 3 7 6 5 4 3 2 1 0 d a t a byte n 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 cs sck si so high impedance instruction 10 11 12 13 14 15 d a t a byte 6 5 4 3 2 1 0 w d 1 w d 0 i d l 2 i d l 1 i d l 0 w a veform inputs outputs must be steady will be steady ma y change from lo w to high will change from lo w to high ma y change from high to lo w will change from high to lo w don? care: changes allo w ed changing: state not kno wn n/a center line is high impedance symbol table
X25383/85 7 d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) power-up timing capacitance t a = +25 c, f = 1mhz, v cc = 5v. notes: (1) v il min. and v ih max. are f or ref erence only and are not tested. (2) this par ameter is per iodically sampled and not 100% tested. symbol parameter limits units test conditions min. typ. max. i cc1 v cc write current (active) 5 ma sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open i cc2 v cc read current (active) 0.4 ma sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open i sb1 v cc standby current wdt=off 1 m a cs = v cc , v in = v ss or v cc , v cc = 5.5v i sb2 v cc standby current wdt=on 50 m a cs = v cc , v in = v ss or v cc , v cc = 5.5v i sb3 v cc standby current wdt=on 20 m a cs = v cc , v in = v ss or v cc , v cc =3.6v i li input leakage current 0.1 10 m a v in = v ss to v cc i lo output leakage current 0.1 10 m a v out = v ss to v cc v il (1) input low voltage ?.5 v cc x0.3 v v ih (1) input high voltage v cc x0.7 v cc +0.5 v v ol1 output low voltage 0.4 v v cc > 3.3v, i ol = 2.1ma v ol2 output low voltage 0.4 v 2v < v cc 3.3v, i ol = 1ma v ol3 output low voltage 0.4 v v cc 2v, i ol = 0.5ma v oh1 output high voltage v cc ?.8 v v cc > 3.3v, i oh = ?.0ma v oh2 output high voltage v cc ?.4 v 2v < v cc 3.3v, i oh = ?.4ma v oh3 output high voltage v cc ?.2 v v cc 2v, i oh = ?.25ma v olrs reset output low voltage 0.4 v i ol = 1ma symbol parameter min. max. units t pur (2) power-up to read operation 1 ms t puw (2) power-up to write operation 5 ms symbol test max. units conditions c out (2) output capacitance (so, reset , reset) 8 pf v out = 0v c in (2) input capacitance (sck, si, cs , wp ) 6 pf v in = 0v absolute maximum ratings* t emper ature under bias ........................ ?5 c to +135 c stor age t emper ature ............................. ?5 c to +150 c v oltage on an y pin with respect to v ss ....... ?.0v to +7v d .c . output current .................................................... 5ma lead t emper ature (solder ing, 10 seconds) ............ 300 c recommended operating conditions 7036 frm t07 *comment stresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and the functional oper ation of the de vice at these or an y other conditions abo v e those listed in the oper ational sections of this speci cation is not implied. exposure to absolute maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability . temp min. max. commercial 0 c 70 c industrial ?0 c +85 c supply voltage limits X25383/85 ?.8 1.8v-3.6v X25383/85 ?.7 2.7v to 5.5v X25383/85 4.5v-5.5v
X25383/85 8 a.c. characteristics (over recommended operating conditions, unless otherwise specified) data input timing symbol parameter voltage range min. max. units f sck clock frequency 2.7v?.5v 1.8v?.6v 0 5 3.3 mhz t cyc cycle time 2.7v?.5v 1.8v?.6v 200 300 ns t lead cs lead time 2.7v?.5v 1.8v?.6v 100 150 ns t lag cs lag time 2.7v?.5v 1.8v?.6v 100 150 ns t wh clock high time 2.7v?.5v 1.8v?.6v 80 130 ns t wl clock low time 2.7v?.5v 1.8v?.6v 80 130 ns t su data setup time 2.7v?.5v 1.8v?.6v 20 ns t h data hold time 2.7v?.5v 1.8v?.6v 20 ns t ri (3) input rise time 2.7v?.5v 1.8v?.6v 2 m s t fi (3) input fall time 2.7v?.5v 1.8v?.6v 2 m s t cs cs deselect time 2.7v?.5v 1.8v?.6v 100 ns t wc (4) write cycle time 2.7v?.5v 1.8v?.6v 10 ms equivalent a.c. load circuit at 5v v cc a.c. test conditions 5v output 100pf 5v 3.3k w reset/reset 30pf 1.64k w 1.64k w input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x0.5
X25383/85 9 data output timing notes: (3) this par ameter is per iodically sampled and not 100% tested. (4) t wc is the time from the r ising edge of cs after a v alid wr ite sequence has been sent to the end of the self-timed inter nal non v olatile wr ite cycle . symbol parameter voltage range min. max. units f sck clock frequency 2.7v?.5v 1.8v?.6v 0 5 3.3 mhz t dis output disable time 2.7v?.5v 1.8v?.6v 100,150 ns t v output valid from clock low 2.7v?.5v 1.8v?.6v 80 130 ns t ho output hold time 2.7v?.5v 1.8v?.6v 0 ns t ro (3) output rise time 2.7v?.5v 1.8v?.6v 50 ns t fo (3) output fall time 2.7v?.5v 1.8v?.6v 50 ns
X25383/85 10 serial output timing serial input timing sck cs so si msb out msb? out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance
X25383/85 11 power-up and power-down timing reset output timing notes: (5) this par ameter is per iodically sampled and not 100% tested. cs vs. reset/reset timing reset /reset output timing symbol parameter min. typ. max. units v trip reset trip point voltage, 5v device reset trip point voltage, 2.7v device reset trip point voltage, 1.8v device 4.25 2.55 1.7 4.5 2.7 1.8 v v v t purst power-up reset timeout 100 200 280 ms t rpd (5) v cc detect to reset/output 500 ns t f (5) v cc fall time 0.1 ns t r (5) v cc rise time 0.1 ns v rvalid reset valid v cc 1 v symbol parameter min. typ. max. units t wdo watchdog timeout period, wd1 = 1, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 0, wd0 = 0 100 450 1 200 600 1.4 300 800 2 ms ms sec t cst cs pulse width to reset the watchdog 400 ns t rst reset timeout 100 200 300 ms vcc t purst t purst t r t f t rpd reset (x25643) 0 v olts v trip v trip reset (x25645) cs t cst reset t wdo t rst reset t wdo t rst
X25383/85 12 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 8-lead plastic small outline gull wing p ackage type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
X25383/85 13 note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop , package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .01 18 (.30) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
X25383/85 14 ordering information part mark convention device X25383/85 p t temperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c package limited w arranty de vices sold b y xicor , inc. are co v ered b y the w arr anty and patent indemni cation pro visions appear ing in its t er ms of sale only . xicor , inc. mak es no w arr anty , e xpress , statutor y , implied, or b y descr iption regarding the inf or mation set f or th herein or regarding the freedom of the descr ibed de vices from patent infr ingement. xicor , inc. mak es no w arr anty of merchantability or tness f or an y pur pose . xicor , inc. reser v es the r ight to discontin ue production and change speci cations and pr ices at an y time and without notice . xicor , inc. assumes no responsibility f or the use of an y circuitr y other than circuitr y embodied in a xicor , inc. product. no other circuits , patents , licenses are implied. u .s. p a tents xicor products are co v ered b y one or more of the f ollo wing u .s . p atents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. f oreign patents and additional patents pending. life rela ted policy in situations where semiconductor component f ailure ma y endanger lif e , system designers using this product should design the system with appropr iate error detection and correction, redundancy and bac k-up f eatures to pre v ent such an occurence . xicor's products are not author iz ed f or use in cr itical components in lif e suppor t de vices or systems . 1. lif e suppor t de vices or systems are de vices or systems which, (a) are intended f or surgical implant into the body , or (b) suppor t or sustain lif e , and whose f ailure to perf or m, when proper ly used in accordance with instr uctions f or use pro vided in the labeling, can be reasonab ly e xpected to result in a signi cant injur y to the user . 2. a cr itical component is an y component of a lif e suppor t de vice or system whose f ailure to perf or m can be reasonab ly e xpected to cause the f ailure of the lif e suppor t de vice or system, or to aff ect its saf ety or eff ectiv eness . v8 = 8-lead tssop s8 = 8-lead soic v v cc limits blank = 4.5v to 5.5v 2.7 = 2.7v to 5.5v 1.8 = 1.8v to 3.6v 8-lead tssop ag = 1.8 to 3.6v, 0 to +70 c eyww 5383/85xx ah = 1.8 to 3.6v, -40 to +85 c f = 2.7 to 5.5v, 0 to +70 c g = 2.7 to 5.5v, -40 to +85 c blank = 4.5 to 5.5v, 0 to +70 c i = 4.5 to 5.5v, -40 to +85 c 8-lead soic X25383/85 x xx blank = 8-lead soic ag = 1.8 to 3.6v, 0 to +70 c ah = 1.8 to 3.6v, -40 to +85 c f = 2.7 to 5.5v, 0 to +70 c g = 2.7 to 5.5v, -40 to +85 c blank = 4.5 to 5.5v, 0 to +70 c i = 4.5 to 5.5v, -40 to +85 c
u.s. sales offices corporate of ce xicor inc. 1511 buc k e y e dr iv e milpitas , ca 95035 phone: 408/432-8888 f ax: 408/432-0640 e-mail: inf o@smtpgate .xicor .com nor theast region xicor inc. 1344 main street w altham, ma 02154 phone: 617/899-5510 f ax: 617/899-6808 e-mail: xicor-ne@smtpgate .xicor .com southeast region xicor inc. 100 e. sybelia a v e . suite 355 maitland, fl 32751 phone: 407/740-8282 f ax: 407/740-8602 e-mail: xicor-se@smtpgate .xicor .com mid-atlantic region xicor inc. 50 nor th street danb ur y , ct 06810 phone: 203/743-1701 f ax: 203/794-9501 e-mail: xicor-ma@smtpgate .xicor .com nor th central region xicor inc. 810 south bar tlett road suite 103 streamw ood, il 60107 phone: 630/372-3200 f ax: 630/372-3210 e-mail: xicor-nc@smtpgate .xicor .com south central region xicor inc. 11884 green ville a v e . suite 102 dallas , tx 75243 phone: 972/669-2022 f ax: 972/644-5835 e-mail: xicor-sc@smtpgate .xicor .com southwest region xicor inc. 4100 ne wpor t place dr iv e suite 710 ne wpor t beach, ca 92660 phone: 714/752-8700 f ax: 714/752-8634 e-mail: xicor-s w@smtpgate .xicor .com nor thwest region xicor inc. 3333 bo w ers a v e . suite 238 santa clar a, ca 95054 phone: 408/492-1966 f ax: 408/980-9478 e-mail: xicor-nw@smtpgate .xicor .com international sales offices eur ope nor thern eur ope xicor ltd. gr ant thor nton house witan w a y witne y oxf ord o x8 6fe uk phone: (44) 1933.700544 f ax: (44) 1933.700533 e-mail: xicor-uk@smtpgate .xicor .com central eur ope xicor gmbh t echnopar k neuk ef er loh bretonischer ring 15 85630 gr asbr unn bei muenchen ger man y phone: (49) 8946.10080 f ax: (49) 8946.05472 e-mail: xicor-gm@smtpgate .xicor .com asia/p a cific japan xicor j apan k.k. suzuki building, 4th floor 1-6-8 shinjuku, shinjuku-ku t oky o 160, j apan phone: (81) 3322.52004 f ax: (81) 3322.52319 e-mail: xicor-jp@smtpgate .xicor .com mainland china t aiwan/hong k ong xicor inc. 4100 ne wpor t place dr iv e suite 710 ne wpor t beach, ca 92660 phone: 714/752-8700 f ax: 714/752-8634 e-mail: xicor-s w@smtpgate .xicor .com singapore/mala ysia/india xicor inc. 3333 bo w ers a v e . suite 238 santa clar a, ca 95054 phone: 408/492-1966 f ax: 408/980-9478 e-mail: xicor-nw@smtpgate .xicor .com k orea xicor k orea, ltd. 27th fl., k orea w or ld t r ade ctr . 159, samsung-dong kangnam k u seoul 135-729 k orea phone: (82) 2.551.2750 f ax: (82) 2.551.2710 e-mail: xicor-ka@smtpgate .xicor .com ( ) = countr y code xicor , inc., mar k eting dept. 1511 buc k e y e dr iv e , milpitas , calif or nia 95035-7493 tel 408/432-8888 f ax 408/432-0640 xicor product information is available at: www.xicor.com X25383/85

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