View UPD70F3726GB-8EU-A_6817501.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

v850es/ke2 32-bit single-chip microcontroller hardware printed in japan document no. u17705ej2v0ud00 (2nd edition) date published december 2006 n cp(k) user?s manual pd70f3726 2005
user?s manual u17705ej2v0ud 2 [memo]
user?s manual u17705ej2v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
user?s manual u17705ej2v0ud 4 caution: pd70f3726 uses superflash ? technology licensed from silicon storage technology, inc. iecube is a registered trademark of nec el ectronics corporation in japan and germany. minicube is a trademark of nec electronics corporat ion germany or a trademark in the united states. eeprom is a trademark of nec electronics corporation windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. superflash is a registered trademark of silicon st orage technology, inc. in several countries including the united states and japan. pc/at is a trademark of internati onal business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. tron is an abbreviation of the r ealtime operating system nucleus. itron is an abbreviati on of industrial tron.
user?s manual u17705ej2v0ud 5 the information in this document is current as of may, 2006. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporat e sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1
user?s manual u17705ej2v0ud 6 preface readers this manual is intended for users who wish to understand the functions of the v850es/ke2 and design applicati on systems using the v850es/ke2. purpose this manual is intended to give users an under standing of the hardw are functions of the v850es/ke2 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? cpu function ? on-chip peripheral functions ? flash memory programming ? electrical specifications ? data types ? register set ? instruction format and instruction set ? interrupts and exceptions ? pipeline operation how to read this manual it is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to understand the overall f unctions of the v850es/ke2 read this manual according to the contents . to find the details of a register where the name is known refer to appendix c register index . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. to understand the details of an instruction function refer to the v850es architecture user?s manual . to know the electrical spec ifications of the v850es/ke2 refer to chapter 23 electrical specifications . the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that even if ?xxx.yyy? is descri bed as is in a program, however, the compiler/assembler cannot recognize it correctly. the mark shows major revised points. the revised points can be easily searched by copying an ?? in the pdf file and spec ifying it in the ?find what:? field.
user?s manual u17705ej2v0ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3
user?s manual u17705ej2v0ud 8 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/ke2 document name document no. v850es architecture user?s manual u15943e v850es/ke2 hardware user?s manual this manual documents related to developm ent tools (user?s manuals) document name document no. qb-v850esx1h in-circuit emulator u17214e qb-v850mini on-chip debug emulator u17638e qb-mini2 on-chip debug emulator with flash programming function to be prepared operation u17293e c language u17291e assembly language u17292e ca850 ver. 3.00 c compiler package link directives u17294e pm+ ver. 6.20 project manager u17990e id850qb ver. 3.20 integrated debugger operation u17964e sm850 ver. 2.50 system simulator operation u16218e sm850 ver. 2.00 or later system simulator external part user open interface specification u14873e basics u13430e installation u17419e technical u13431e rx850 ver. 3.20 real-time os task debugger u17420e basics u13773e installation u17421e technical u13772e rx850 pro ver. 3.20 real-time os task debugger u17422e az850 ver. 3.30 system performance analyzer u17423e pg-fp4 flash memory programmer u15260e
user?s manual u17705ej2v0ud 9 contents chapter 1 introduction ...................................................................................................... ...........17 1.1 v850es/kx2 product lineup....................................... ........................................................... ... 17 1.2 features ................................................................................................................... ................... 18 1.3 applications............................................................................................................... ................. 19 1.4 ordering information ....................................................................................................... .......... 19 1.5 pin configuration (top view).................................... ........................................................... ..... 20 1.6 function block configuration .................................... ........................................................... ... 22 1.7 overview of functions ...................................................................................................... ........ 25 chapter 2 pin functions .................................................................................................... ............26 2.1 list of pin functions ...................................................................................................... ........... 26 2.2 pin i/o circuits and recommende d connection of unused pins......................................... 30 2.3 pin i/o circuits ........................................................................................................... ................ 32 chapter 3 cpu functions .................................................................................................... ..........34 3.1 features ................................................................................................................... ................... 34 3.2 cpu register set ........................................................................................................... ............ 35 3.2.1 program re gister set ..................................................................................................... ..................36 3.2.2 system r egister set...................................................................................................... ...................37 3.3 operating modes............................................................................................................ ............ 43 3.4 address space .............................................................................................................. ............. 44 3.4.1 cpu addr ess s pace........................................................................................................ ................44 3.4.2 wraparound of cpu address space .......................................................................................... .....45 3.4.3 memo ry map............................................................................................................... ....................46 3.4.4 areas .................................................................................................................... ..........................48 3.4.5 recommended us e of addres s space ......................................................................................... ...50 3.4.6 peripheral i/o registers................................................................................................. ..................52 3.4.7 special registers ........................................................................................................ .....................58 3.4.8 c autio ns ................................................................................................................. ........................61 chapter 4 port functions ................................................................................................... .........65 4.1 features ................................................................................................................... ................... 65 4.2 basic port configuration................................................................................................... ........ 65 4.3 port configuratio n ......................................................................................................... ............ 66 4.3.1 port 0................................................................................................................... ...........................72 4.3.2 port 3................................................................................................................... ...........................74 4.3.3 port 4................................................................................................................... ...........................80 4.3.4 port 5................................................................................................................... ...........................82 4.3.5 port 7................................................................................................................... ...........................85 4.3.6 port 9................................................................................................................... ...........................86 4.3.7 po rt cm .................................................................................................................. ........................92 4.3.8 po rt dl .................................................................................................................. .........................94 4.4 block diagrams ............................................................................................................. ............. 96
user?s manual u17705ej2v0ud 10 4.5 port register setting when al ternate function is used...................................................... 114 4.6 cautions ................................................................................................................... ................. 118 4.6.1 cautions on bit manipulation inst ruction for port n register (pn) .................................................. 118 4.6.2 hysteresis characteri stics ............................................................................................... ............. 119 chapter 5 clock generation function............................................................................... 120 5.1 overview ................................................................................................................... ................ 120 5.2 configuration.............................................................................................................. .............. 121 5.3 registers .................................................................................................................. ................. 123 5.4 operation .................................................................................................................. ................ 127 5.4.1 operation of each clock .................................................................................................. ............. 127 5.4.2 clock output function .................................................................................................... ............... 127 5.4.3 external clo ck input f unction ............................................................................................ ............ 127 5.5 pll function ............................................................................................................... ............. 128 5.5.1 ov ervi ew................................................................................................................. ..................... 128 5.5.2 r egist er ................................................................................................................. ...................... 128 5.5.3 usage .................................................................................................................... ...................... 129 chapter 6 16-bit timer/event counter p (tmp)................................................................. 130 6.1 overview ................................................................................................................... ................ 130 6.2 functions .................................................................................................................. ................ 130 6.3 configuration.............................................................................................................. .............. 131 6.4 registers .................................................................................................................. ................. 133 6.5 operation .................................................................................................................. ................ 144 6.5.1 interval timer mode (tp0 md2 to tp0md0 bits = 000) ................................................................. 145 6.5.2 external event count mode (t p0md2 to tp0md0 bits = 001) ..................................................... 155 6.5.3 external trigger pulse output mode (tp0md2 to tp0m d0 bits = 010) ......................................... 163 6.5.4 one-shot pulse output mode (t p0md2 to tp0md0 bits = 011) .................................................. 175 6.5.5 pwm output mode (tp0md2 to tp0md0 bi ts = 100) .................................................................. 182 6.5.6 free-running timer mode (tp0 md2 to tp0md0 bits = 101) ........................................................ 191 6.5.7 pulse width measurement mode (tp0md2 to tp0md0 bits = 110) ............................................. 208 6.5.8 timer output operations .................................................................................................. ............. 214 6.6 eliminating noise on capture tr igger input pin (tip0a) ...................................................... 215 6.7 cautions ................................................................................................................... ................. 217 chapter 7 16-bit timer/event counter 0 ............................................................................. 218 7.1 functions .................................................................................................................. ................ 218 7.2 configuration.............................................................................................................. .............. 219 7.3 registers .................................................................................................................. ................. 224 7.4 operation .................................................................................................................. ................ 231 7.4.1 interval ti mer operation ................................................................................................. ............... 231 7.4.2 square wave output oper ation ............................................................................................. ........ 234 7.4.3 external event counter o peration ......................................................................................... ........ 237 7.4.4 operation in clear & start mode entered by ti010 pin va lid edge in put ....................................... 240 7.4.5 free-running timer oper ation ............................................................................................. .......... 256 7.4.6 ppg output operation ..................................................................................................... ............. 265 7.4.7 one-shot puls e output op eration.......................................................................................... ........ 268
user?s manual u17705ej2v0ud 11 7.4.8 pulse width me asurement operati on ........................................................................................ ....273 7.5 special use of tm01 ........................................................................................................ ........ 281 7.5.1 rewriting cr0 11 register during tm01 operat ion.........................................................................28 1 7.5.2 setting lvs0 1 and lvr 01 bits ............................................................................................. ........281 7.6 cautions................................................................................................................... ................. 283 chapter 8 8-bit timer/event counter 5................................................................................287 8.1 functions .................................................................................................................. ................ 287 8.2 configuration.............................................................................................................. .............. 288 8.3 registers.................................................................................................................. ................. 291 8.4 operation .................................................................................................................. ................ 294 8.4.1 operation as interval timer .............................................................................................. .............294 8.4.2 operation as ex ternal event count er...................................................................................... .......296 8.4.3 square-wave output oper ation............................................................................................. .........297 8.4.4 8-bit pwm output oper ation ............................................................................................... ...........299 8.4.5 operation as inte rval timer (16 bits).................................................................................... ..........302 8.4.6 operation as external event counter (16 bits)............................................................................ ...304 8.4.7 square-wave output oper ation (16-bit resolu tion)......................................................................... 305 8.4.8 c autio ns ................................................................................................................. ......................306 chapter 9 8-bit timer h ................................................................................................... .............307 9.1 functions .................................................................................................................. ................ 307 9.2 configuration.............................................................................................................. .............. 307 9.3 registers.................................................................................................................. ................. 310 9.4 operation .................................................................................................................. ................ 314 9.4.1 operation as interval timer/square wave output ........................................................................... 314 9.4.2 pwm output mode oper ation ................................................................................................ ........317 9.4.3 carrier generat or mode o peratio n ......................................................................................... .......323 chapter 10 interval timer, watch timer ............................................................................330 10.1 interval timer brg ........................................................................................................ .......... 330 10.1.1 f uncti ons ............................................................................................................... .......................330 10.1.2 config uration ........................................................................................................... .....................330 10.1.3 regi sters ............................................................................................................... .......................332 10.1.4 oper ation............................................................................................................... .......................334 10.2 watch timer............................................................................................................... ............... 335 10.2.1 f uncti ons ............................................................................................................... .......................335 10.2.2 config uration ........................................................................................................... .....................335 10.2.3 regi sters ............................................................................................................... .......................336 10.2.4 oper ation............................................................................................................... .......................338 10.3 cautions.................................................................................................................. .................. 339 chapter 11 watchdog timer functions ...............................................................................341 11.1 watchdog timer 1.......................................................................................................... .......... 341 11.1.1 f uncti ons ............................................................................................................... .......................341 11.1.2 config uration ........................................................................................................... .....................343
user?s manual u17705ej2v0ud 12 11.1.3 regi sters............................................................................................................... ....................... 343 11.1.4 oper ation ............................................................................................................... ...................... 345 11.2 watchdog timer 2 .......................................................................................................... .......... 347 11.2.1 f uncti ons ............................................................................................................... ...................... 347 11.2.2 config uration ........................................................................................................... .................... 348 11.2.3 regi sters............................................................................................................... ....................... 348 11.2.4 oper ation ............................................................................................................... ...................... 350 chapter 12 real-time output function (rto) ................................................................... 351 12.1 function .................................................................................................................. .................. 351 12.2 configuration............................................................................................................. ............... 352 12.3 registers ................................................................................................................. .................. 353 12.4 operation ................................................................................................................. ................. 355 12.5 usage..................................................................................................................... .................... 356 12.6 cautions .................................................................................................................. .................. 356 12.7 security function ......................................................................................................... ............ 357 chapter 13 a/d converter ................................................................................................... ...... 359 13.1 overview .................................................................................................................. ................. 359 13.2 functions ................................................................................................................. ................. 359 13.3 configuration............................................................................................................. ............... 360 13.4 registers ................................................................................................................. .................. 362 13.5 operation ................................................................................................................. ................. 370 13.5.1 basic operation ......................................................................................................... ................... 370 13.5.2 trigger modes........................................................................................................... ................... 371 13.5.3 operat ion mo des ......................................................................................................... ................ 372 13.5.4 power fail det ection f unction ........................................................................................... ............. 375 13.5.5 setti ng meth od.......................................................................................................... ................... 376 13.6 cautions .................................................................................................................. .................. 377 13.7 how to read a/d converter char acteristics table............................................................... 383 chapter 14 asynchronous serial interface (uart)..................................................... 387 14.1 features .................................................................................................................. .................. 387 14.2 configuration............................................................................................................. ............... 388 14.3 registers ................................................................................................................. .................. 390 14.4 interrupt requests ........................................................................................................ ........... 396 14.5 operation ................................................................................................................. ................. 397 14.5.1 data format ............................................................................................................. ..................... 397 14.5.2 transmi t operat ion...................................................................................................... ................. 398 14.5.3 continuous trans mission op eration....................................................................................... ....... 400 14.5.4 receive operat ion....................................................................................................... ................. 404 14.5.5 recept ion error ......................................................................................................... ................... 405 14.5.6 parity types and corresponding operatio n................................................................................ .... 407 14.5.7 receive dat a noise filter............................................................................................... ................ 408 14.6 dedicated baud rate generator n (brgn) .................. .......................................................... 409 14.6.1 baud rate generator n (brgn) conf igurat ion .............................................................................. . 409 14.6.2 serial cl ock gener ation................................................................................................. ................ 410
user?s manual u17705ej2v0ud 13 14.6.3 baud rate setting ex ample ............................................................................................... .............413 14.6.4 allowable baud rate range during reception .............................................................................. ...414 14.6.5 transfer rate during continuous transmi ssion............................................................................ ...416 14.7 cautions.................................................................................................................. .................. 416 chapter 15 clocked serial interface 0 (csi0).................................................................417 15.1 features .................................................................................................................. .................. 417 15.2 configuration............................................................................................................. ............... 418 15.3 registers................................................................................................................. .................. 421 15.4 operation ................................................................................................................. ................. 430 15.4.1 transmission/reception completion in terrupt request si gnal (intcs i0n) ......................................430 15.4.2 single tr ansfer mode .................................................................................................... ................432 15.4.3 continuous transfe r mode ................................................................................................ ............435 15.5 output pins............................................................................................................... ................ 443 chapter 16 i 2 c bus......................................................................................................................... ..444 16.1 features .................................................................................................................. .................. 444 16.2 configuration............................................................................................................. ............... 447 16.3 registers................................................................................................................. .................. 449 16.4 functions ................................................................................................................. ................. 463 16.4.1 pin conf iguration....................................................................................................... ....................463 16.5 i 2 c bus definitions and control methods..................... ......................................................... 464 16.5.1 start conditi on......................................................................................................... ......................464 16.5.2 addr esses ............................................................................................................... .....................465 16.5.3 transfer direct ion specif ication ........................................................................................ .............466 16.5.4 ack ..................................................................................................................... .........................467 16.5.5 stop c onditio n.......................................................................................................... .....................468 16.5.6 wait state .............................................................................................................. .......................469 16.5.7 wait state c ancellation method.......................................................................................... ...........471 16.6 i 2 c interrupt request signals (intiic0)...................... ............................................................ 472 16.6.1 master dev ice operat ion ................................................................................................. ..............473 16.6.2 slave device operation (when receiv ing slave address data (address ma tch)) ............................476 16.6.3 slave device operation (w hen receiving ex tension code) .............................................................480 16.6.4 operation with out communi cation ......................................................................................... .......484 16.6.5 arbitration loss oper ation (operation as slave after arbitrat ion lo ss) .............................................485 16.6.6 operation when arbitrat ion loss occurs (no communicati on after arbitr ation loss)........................487 16.7 interrupt request signal (intiic 0) generation timing and wait c ontrol .......................... 494 16.8 address match detection method ....... ................................................................................... 49 5 16.9 error detection ........................................................................................................... .............. 495 16.10 extension code ........................................................................................................... ............. 496 16.11 arbitration.............................................................................................................. ................... 497 16.12 wakeup function .......................................................................................................... ........... 498 16.13 communication reservation ................................................................................................ .. 499 16.13.1 when communication reservation functi on is enabled (iicf0 .iicrsv0 bi t = 0)............................499 16.13.2 when communication reservation function is disabled (iicf0 .iicrsv0 bi t = 1) ...........................502 16.14 cautions................................................................................................................. ................... 503 16.15 communication operations................................................................................................. ... 504
user?s manual u17705ej2v0ud 14 16.15.1 master operation in single mast er system............................................................................... ..... 505 16.15.2 master operation in multimas ter system ................................................................................. ..... 506 16.15.3 slave operation........................................................................................................ .................... 509 16.16 timing of data communication ............................................................................................. . 512 chapter 17 interrupt/exception processing function............................................... 519 17.1 overview .................................................................................................................. ................. 519 17.1.1 f eatur es................................................................................................................ ....................... 519 17.2 non-maskable interrupts ................................................................................................... ...... 522 17.2.1 oper ation ............................................................................................................... ...................... 525 17.2.2 re store ................................................................................................................. ....................... 526 17.2.3 np flag ................................................................................................................. ........................ 527 17.3 maskable interrupts ....................................................................................................... .......... 528 17.3.1 oper ation ............................................................................................................... ...................... 528 17.3.2 re store ................................................................................................................. ....................... 530 17.3.3 priorities of maskable in terrupts....................................................................................... ............ 531 17.3.4 interrupt contro l register (xxlcn) ...................................................................................... ............ 535 17.3.5 interrupt mask registers 0, 1, 3 (imr0, imr1, im r3) ................................................................... 53 7 17.3.6 in-service priori ty register (ispr)..................................................................................... ............ 538 17.3.7 id flag ................................................................................................................. ......................... 539 17.3.8 watchdog timer mode r egister 1 (w dtm1) ................................................................................. 5 40 17.4 external interrupt re quest input pins (nmi, intp0 to intp7) .............................................. 541 17.4.1 noise e liminat ion ....................................................................................................... .................. 541 17.4.2 edge de tection.......................................................................................................... ................... 543 17.5 software exceptions ....................................................................................................... ......... 547 17.5.1 oper ation ............................................................................................................... ...................... 547 17.5.2 re store ................................................................................................................. ....................... 548 17.5.3 ep flag ................................................................................................................. ........................ 549 17.6 exception trap ............................................................................................................ ............. 550 17.6.1 ill egal opc ode.......................................................................................................... ..................... 550 17.6.2 debu g tr ap .............................................................................................................. ..................... 552 17.7 multiple interrupt servicing control...................................................................................... . 554 17.8 interrupt response time ................................................................................................... ...... 556 17.9 periods in which interrupts are not acknowledge d by cpu.............................................. 557 17.10 cautions ................................................................................................................. ................... 557 chapter 18 key interrupt function ..................................................................................... 558 18.1 function .................................................................................................................. .................. 558 18.2 register .................................................................................................................. ................... 559 chapter 19 standby function ................................................................................................ .. 560 19.1 overview .................................................................................................................. ................. 560 19.2 registers ................................................................................................................. .................. 563 19.3 halt mode ................................................................................................................. .............. 566 19.3.1 setting and op eration status ............................................................................................ ............ 566 19.3.2 releasin g halt mode ..................................................................................................... ............ 566 19.4 idle mode................................................................................................................. ................ 568
user?s manual u17705ej2v0ud 15 19.4.1 setting and op eration status ............................................................................................ .............568 19.4.2 releasin g idle mode ..................................................................................................... ..............569 19.5 stop mode ................................................................................................................. .............. 571 19.5.1 setting and op eration status ............................................................................................ .............571 19.5.2 releasin g stop mode ..................................................................................................... ............572 19.5.3 securing oscillation stabilizati on time when stop m ode is rel eased ...........................................574 19.6 subclock operation mode................................................................................................... .... 575 19.6.1 setting and op eration status ............................................................................................ .............575 19.6.2 releasing subc lock operat ion mode....................................................................................... ......575 19.7 sub-idle mode............................................................................................................. ............ 577 19.7.1 setting and op eration status ............................................................................................ .............577 19.7.2 releasing sub-idle mode................................................................................................. ...........578 chapter 20 reset function .................................................................................................. ......580 20.1 overview .................................................................................................................. ................. 580 20.2 configuration............................................................................................................. ............... 580 20.3 operation ................................................................................................................. ................. 581 chapter 21 flash memory.................................................................................................... .......585 21.1 features .................................................................................................................. .................. 585 21.2 memory configuratio n...................................................................................................... ....... 586 21.3 functional outline ........................................................................................................ ........... 587 21.4 rewriting by dedicated flash programmer ............ .............................................................. 591 21.4.1 programmi ng environ ment ................................................................................................. ..........591 21.4.2 communica tion mode...................................................................................................... .............592 21.4.3 flash memo ry control .................................................................................................... ...............597 21.4.4 selection of communicati on mode......................................................................................... .......598 21.4.5 communicati on commands .................................................................................................. ........599 21.4.6 pin co nnection .......................................................................................................... ....................600 21.5 rewriting by self programming ............................................................................................. 605 21.5.1 ov ervi ew ................................................................................................................ ......................605 21.5.2 f eatur es ................................................................................................................ .......................606 21.5.3 standard self programmi ng flow .......................................................................................... .........607 21.5.4 flash functi ons ......................................................................................................... ....................608 21.5.5 pin pr ocessing .......................................................................................................... ....................608 21.5.6 internal resource s used ................................................................................................. ...............609 chapter 22 on-chip debug function ......................................................................................610 22.1 debugging without using dcu ..................................... ......................................................... 6 11 22.1.1 circuit con nection ex amples............................................................................................. ............611 22.1.2 maskabl e func tions...................................................................................................... .................612 22.1.3 securing of user resources.............................................................................................. .............613 22.1.4 c autio ns ................................................................................................................ .......................618 22.2 rom security function ..................................................................................................... ...... 619 22.2.1 secu rity id ............................................................................................................. .......................619 22.2.2 se tting ................................................................................................................. .........................620
user?s manual u17705ej2v0ud 16 chapter 23 electrical specifications ................................................................................. 622 chapter 24 package drawing................................................................................................. .. 644 chapter 25 recommended soldering conditions........................................................... 645 appendix a development tools............................................................................................... 646 a.1 software package............................................................................................................... ...... 648 a.2 language processing software........... ................................................................................... 648 a.3 control software ............................................................................................................... ....... 648 a.4 debugging tools (hardware) ................................................ .................................................. 649 a.4.1 when using iecube qb-v850 eskx1h ...................................................................................... 649 a.4.2 when using minicu be qb-v850m ini ........................................................................................ 651 a.4.3 when using minicu be2 qb-mi ni2 ............................................................................................ 653 a.5 debugging tools (software) ................................................................................................... 65 4 a.6 embedded software.............................................................................................................. ... 655 a.7 flash memory writing tools ................................................................................................... 65 5 appendix b instruction set list ........................................................................................... .. 656 b.1 conventions................................................................................................................ .............. 656 b.2 instruction set (in alphabetical order) .................... .............................................................. 65 9 appendix c register index .................................................................................................. ....... 666 appendix d list of cautions ............................................................................................... ...... 672 appendix e revision history................................................................................................ ...... 699 e.1 major revisions in this edition............................................................................................ .. 699
user?s manual u17705ej2v0ud 17 chapter 1 introduction 1.1 v850es/kx2 product lineup product name v850es/ke2 v850 es/kf2 v850es/kg2 v850es/kj2 number of pins 64 pins 80 pins 100 pins 144 pins flash memory 128 128 256 128 256 128 256 internal memory (kb) ram 4 6 12 6 16 6 16 supply voltage 2.7 to 5.5 v minimum instruction execution time 50 ns @20 mhz x1 input 2 to 10 mhz clock subclock 32.768 khz cmos input 8 8 8 16 cmos i/o 41 (4) note 57 (6) note 72 (8) note 106 (12) note port n-ch open-drain i/o 2 2 4 6 16-bit (tmp) 1 ch 1 ch 1 ch 1 ch 16-bit (tm0) 1 ch 2 ch 4 ch 6 ch 8-bit (tm5) 2 ch 2 ch 2 ch 2 ch 8-bit (tmh) 2 ch 2 ch 2 ch 2 ch interval timer 1 ch 1 ch 1 ch 1 ch watch 1 ch 1 ch 1 ch 1 ch wdt1 1 ch 1 ch 1 ch 1 ch timer wdt2 1 ch 1 ch 1 ch 1 ch rto 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch csi 2 ch 2 ch 2 ch 3 ch automatic transmit/ receive 3-wire csi ? 1 ch 2 ch 2 ch uart 2 ch 2 ch 3 ch 3 ch serial interface i 2 c 1 ch 1 ch 1 ch 2 ch address space ? 128 kb 3 mb 15 mb address bus ? 16 bits 22 bits 24 bits external bus mode ? multiplex only multiplex/separate dma controller ? ? 4 ch 4 ch 10-bit a/d converter 8 ch 8 ch 8 ch 16 ch 8-bit d/a converter ? ? 2 ch 2 ch external 9 9 9 9 interrupt internal 26 29 41 47 key return input 8 ch 8 ch 8 ch 8 ch reset pin provided wdt1 provided reset wdt2 provided regulator none provided standby function halt/idle/stop/sub-idle mode operating ambient temperature ta = ? 40 to +85 c note figures in parentheses indicate the number of pins fo r which the n-ch open-drain output can be selected.
chapter 1 introduction user?s manual u17705ej2v0ud 18 1.2 features { minimum instruction execution time: 50 ns (operation at main clock (f xx ) = 20 mhz) { general-purpose registers: 32 bits 32 registers { cpu features: signed multiplication (16 16 32): 1 to 2 clocks (instructions without creating register haza rds can be continuously executed in parallel) saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space ? internal memory pd70f3726 (single-power flash memory: 128 kb/ram: 4 kb) { interrupts and exceptions non-maskable interrupts: 3 sources maskable interrupts: 32 sources software exceptions: 32 sources exception trap: 1 source { i/o lines: total: 51 { key interrupt function { timer function 16-bit timer/event counter p: 1 channel 16-bit timer/event counter 0: 1 channel 8-bit timer/event counter 5: 2 channels 8-bit timer h: 2 channels 8-bit interval timer brg: 1 channel watch timer/interval timer: 1 channel watchdog timers watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel watchdog timer 2: 1 channel { serial interface asynchronous serial interface (uart): 2 channels 3-wire serial i/o (csi0): 2 channels i 2 c bus interface (i 2 c): 1 channel { a/d converter: 10-bit resolution 8 channels { real-time output port: 6 bits 1 channel { standby functions: halt/idle/stop modes, subclock/sub-idle modes { clock generator main clock oscillation (f x )/subclock oscillation (f xt ) cpu clock (f cpu ) 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable { reset ? reset by reset pin ? reset by overflow of watchdog timer 1 (wdtres1) ? reset by overflow of watchdog timer 2 (wdtres2) { package: 64-pin plastic lqfp (fine pitch) (10 10)
chapter 1 introduction user?s manual u17705ej2v0ud 19 1.3 applications { home audio { av equipment { pc peripheral devices (keyboards, etc.) { household appliances ? outdoor units of air conditioners ? microwave ovens, rice cookers { industrial devices ? pumps ? vending machines ? fa 1.4 ordering information part number package pd70f3726gb-8eu-a 64-pin plasti c lqfp (fine pitch) (10 10) remark products with -a at the end of the part number are lead-free products.
chapter 1 introduction user?s manual u17705ej2v0ud 20 1.5 pin configuration (top view) 64-pin plastic lqfp (fine pitch) (10 10) pd70f3726gb-8eu-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p39/scl0 p38/sda0 pdl7 pdl6 pdl5/flmd1 pdl4 pdl3 pdl2 p05/intp2 p06/intp3 p40/si00 p41/so00 p42/sck00 p30/txd0 p31/rxd0/intp7 p32/asck0/adtrg/to01 p33/tip00/top00 p34/tip01/top01 p35/ti010/to01 p50/kr0/ti011/rtp00 p51/kr1/ti50/rtp01 p52/kr2/to50/rtp02 p53/kr3/rtp03 ev ss pdl1 pdl0 pcm1/clkout pcm0 p915/intp6 p914/intp5 p913/intp4 p99/sck01 p98/so01 p97/si01 p96/ti51/to51 p91/kr7/rxd1 p90/kr6/txd1 p55/kr5/rtp05 p54/kr4/rtp04 ev dd av ref0 av ss flmd0 note 1 v dd nc note 2 v ss x1 x2 reset xt1 xt2 p00/toh0 p01/toh1 p02/nmi p03/intp0 p04/intp1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 notes 1. connect to v ss in normal operation mode. 2. leave the nc pin open. caution make ev dd the same potential as v dd .
chapter 1 introduction user?s manual u17705ej2v0ud 21 pin identification adtrg: a/d trigger input ani0 to ani7: analog input asck0: asynchronous serial clock av ref0 : analog reference voltage av ss : ground for analog clkout: clock output ev dd : power supply for port ev ss : ground for port flmd0, flmd1: flash programming mode intp0 to intp7: external interrupt input kr0 to kr7: key return nc: non-connection nmi: non-maskable interrupt request p00 to p06: port 0 p30 to p35, p38, p39: port 3 p40 to p42: port 4 p50 to p55: port 5 p70 to p77: port 7 p90, p91, p96 to p99, p913 to p915: port 9 pcm0, pcm1: port cm pdl0 to pdl7: port dl reset: reset rtp00 to rtp05: real-time output port rxd0, rxd1: receive data sck00, sck01: serial clock scl0: serial clock sda0: serial data si00, si01: serial input so00, so01: serial output ti010, ti011, ti50, ti51, tip00, tip01: timer input to01, to50, to51, toh0, toh1, top00, top01: timer output txd0, txd1: transmit data v dd : power supply v ss : ground x1, x2: crystal for main clock xt1, xt2: crystal for subclock
chapter 1 introduction user?s manual u17705ej2v0ud 22 1.6 function block configuration (1) internal block diagram nmi to01 ti010, ti011 so00, so01 si00, si01 sck00, sck01 intp0 to intp7 intc top00, top01 tip00, tip01 to50, to51 ti50, ti51 toh0, toh1 txd0, txd1 rxd0, rxd1 asck0 rtp00 to rtp05 kr0 to kr7 rto: 1 ch sda0 scl0 ram flash memory pc alu cpu pdl0 to pdl7 pcm0, pcm1 p90, p91, p96 to p99, p913 to p915 p70 to p77 p50 to p55 p40 to p42 p30 to p35, p38, p39 p00 to p06 av ref0 av ss ani0 to ani7 adtrg ev dd ev ss flmd0, flmd1 v ss bcu cg clkout x1 x2 xt1 xt2 reset 16-bit timer/event counter 0: 1 ch 16-bit timer/ event counter p: 1 ch 8-bit timer/event counter 5: 2 ch 8-bit timer h: 2 ch 128 kb 4 kb general-purpose registers 32 bits 32 system registers 32-bit barrel shifter multiplier 16 16 32 instruction queue uart : 2 ch i 2 c : 1 ch csi0: 2 ch watchdog timer: 2 ch key interrupt function watch timer port a/d converter
chapter 1 introduction user?s manual u17705ej2v0ud 23 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate complex processing. (b) bus control unit (bcu) the bcu controls the internal bus. (c) rom this consists of a 128 kb flash memory mapped to the address spaces from 0000000h to 001ffffh. rom can be accessed by the cpu in one cl ock cycle during instruction fetch. (d) ram this consists of a 4 kb ram mapped to the address spaces from 3ffe000h to 3ffefffh. ram can be accessed by the cpu in on e clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp7) from on-chip peripheral hardware and external hardware. eight levels of inte rrupt priorities can be spec ified for these interrupt requests, and multiplexed servicing control can be performed. (f) clock generator (cg) a main clock oscillator and subclock oscillator ar e provided and generate the main clock oscillation frequency (f x ) and subclock frequency (f xt ), respectively. there are two modes: in the clock-through mode, f x is used as the main clock frequency (f xx ) as is. in the pll mode, f x is used multiplied by 4. the cpu clock frequency (f cpu ) can be selected from among f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt . (g) timer/counter one 16-bit timer/event counter 0 channel, one 16-bi t timer/event counter p channel, and two 8-bit timer/event counter 5 channels ar e incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. two 8-bit timer/event counter 5 channels can be connec ted in cascade to configure a 16-bit timer. two 8-bit timer h channels enabling programmable pulse output are provided on chip. (h) watch timer this timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 khz) or f brg (32.768 khz) from the clock generator. at t he same time, the watch timer can be used as an interval timer.
chapter 1 introduction user?s manual u17705ej2v0ud 24 (i) watchdog timer two watchdog timer channels are provided on chip to detect program loops and system abnormalities. watchdog timer 1 can be used as an interval timer. when used as a watchdog timer, it generates a non- maskable interrupt request signal (intwdt1) or system reset signal (wdtres1) after an overflow occurs. when used as an interval timer, it generates a mask able interrupt request signal (intwdtm1) after an overflow occurs. watchdog timer 2 operates by default following reset release. it generates a non-maskable interrupt request signal (intwdt2) or system rese t signal (wdtres2) after an overflow occurs. (j) serial interface (sio) the v850es/ke2 includes three kinds of serial interf aces: an asynchronous serial interface (uartn), a clocked serial interface (csi0n), and an i 2 c bus interface (i 2 c0), and can simultaneously use up to five channels. for uartn, data is transferred via the txdn and rxdn pins. for csi0n, data is transferred via the so0n, si0n, and sck0n pins. for i 2 c0, data is transferred via the sda0 and scl0 pins. remark n = 0, 1 (k) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 8 analog input pins. conversion is performed using the successive approximation method. (l) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins. (m) real-time output function this function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare register match signal. a 1-channel 6-bit data real-time out put function is provided on chip. (n) ports as shown below, the following ports have general-p urpose port functions and control pin functions. port i/o alternate function p0 7-bit i/o nmi, external interrupt, timer output p3 8-bit i/o serial interface, timer i/o, external interrupt, a/d converter trigger p4 3-bit i/o serial interface p5 6-bit i/o timer i/o, key interrupt function, real-time output function p7 8-bit input a/d converter analog input p9 9-bit i/o serial interface, timer i/o, external interrupt, key interrupt function pcm 2-bit i/o clock output pdl 8-bit i/o ?
chapter 1 introduction user?s manual u17705ej2v0ud 25 1.7 overview of functions part number pd70f3726 rom 128 kb (single-power flash memory) internal memory high-speed ram 4 kb memory space 64 mb general-purpose registers 32 bits 32 registers ceramic/crystal/external clock when pll not used: 2 to 10 mhz (2.7 to 5.5 v) main clock (oscillation frequency) when pll used: 2 to 5 mhz (4.5 to 5.5 v), 2 to 2.5 mhz (2.7 to 5.5 v) subclock (oscillation frequency) crystal/external clock (32.768 khz) minimum instruction execution time 50 ns (when main clock operated at (f xx ) = 20 mhz) dsp function 32 32 = 64: 200 to 250 ns (at 20 mhz) 32 32 + 32 = 32: 300 ns (at 20 mhz) 16 16 = 32: 50 to 100 ns (at 20 mhz) 16 16 + 32 = 32: 150 ns (at 20 mhz) i/o ports 51 ? input: 8 ? i/o: 43 (n-ch open-drain output selectable : 4, fixed to n-ch open-drain output: 2) timer 16-bit timer/event counter p: 1 channel 16-bit timer/event counter 0: 1 channel 8-bit timer/event counter 5: 2 channels (16-bit timer/event counter: usable as 1 channel) 8-bit timer h: 2 channels watchdog timer: 2 channels watch timer: 1 channel 8-bit interval timer: 1 channel real-time output port 4 bits 1, 2 bits 1, or 6 bits 1 a/d converter 10-bit resolution 8 channels serial interface csi: 2 channels uart: 2 channels i 2 c bus: 1 channel dedicated baud rate generator: 2 channels interrupt sources external: 9 (9) note , internal: 26 power save function stop/idle/halt/sub-idle mode operating supply voltage 4.5 to 5.5 v (at 20 mhz)/2.7 to 5.5 v (at 8 mhz) package 64-pin plastic lq fp (fine pitch) (10 10 mm) note the figure in parentheses indicates the number of external interrupts that can release stop mode.
user?s manual u17705ej2v0ud 26 chapter 2 pin functions the names and functions of the pins of the v850es/ke2 are described below, divided into port pins and non-port pins. the pin i/o buffer power supplies ar e divided into two systems; av ref0 and ev dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref0 port 7 ev dd reset, ports 0, 3 to 5, 9, cm, dl 2.1 list of pin functions (1) port pins (1/2) pin name pin no. i/o pull-up resistor function alternate function p00 12 toh0 p01 13 toh1 p02 14 nmi p03 15 intp0 p04 16 intp1 p05 17 intp2 p06 18 i/o yes port 0 i/o port input/output can be specified in 1-bit units. intp3 p30 22 txd0 p31 23 rxd0/intp7 p32 24 asck0/adtrg/to01 p33 25 tip00/top00 p34 26 tip01/top01 p35 27 yes ti010/to01 p38 55 sda0 p39 56 i/o no port 3 i/o port input/output can be specified in 1-bit units. p38 and p39 are fixed to n-ch open-drain output. scl0 p40 19 si00 p41 20 so00 p42 21 i/o yes port 4 i/o port input/output can be specified in 1-bit units. p41 and p42 can be specified as n-ch open- drain output in 1-bit units. sck00
chapter 2 pin functions user?s manual u17705ej2v0ud 27 (2/2) pin name pin no. i/o pull-up resistor function alternate function p50 28 ti011/rtp00/kr0 p51 29 ti50/rtp01/kr1 p52 30 to50/rtp02/kr2 p53 31 rtp03/kr3 p54 34 rtp04/kr4 p55 35 i/o yes port 5 i/o port input/output can be specified in 1-bit units. rtp05/kr5 p70 64 ani0 p71 63 ani1 p72 62 ani2 p73 61 ani3 p74 60 ani4 p75 59 ani5 p76 58 ani6 p77 57 input no port 7 input port ani7 p90 36 txd1/kr6 p91 37 rxd1/kr7 p96 38 ti51/to51 p97 39 si01 p98 40 so01 p99 41 sck01 p913 42 intp4 p914 43 intp5 p915 44 i/o yes port 9 i/o port input/output can be specified in 1-bit units. p98 and p99 can be specified as n-ch open- drain output in 1-bit units. intp6 pcm0 45 ? pcm1 46 i/o yes port cm i/o port input/output can be specified in 1-bit units. clkout pdl0 47 ? pdl1 48 ? pdl2 49 ? pdl3 50 ? pdl4 51 ? pdl5 52 flmd1 pdl6 53 ? pdl7 54 i/o yes port dl i/o port input/output can be specified in 1-bit units. ?
chapter 2 pin functions user?s manual u17705ej2v0ud 28 (2) non-port pins (1/2) pin name pin no. i/o pull-up resistor function alternate function adtrg 24 input yes a/d converter external trigger input p32/asck0/to01 ani0 64 p70 ani1 63 p71 ani2 62 p72 ani3 61 p73 ani4 60 p74 ani5 59 p75 ani6 58 p76 ani7 57 input no analog voltage input for a/d converter p77 asck0 24 input yes uart0 serial clock input p32/adtrg/to01 av ref0 1 ? ? reference voltage for a/d converter and positive power supply for alternate-function ports ? av ss 2 ? ? ground potential for a/d converter and alternate-function ports ? clkout 46 output no internal system clock output pcm1 ev dd 33 ? ? positive power supply for external ? ev ss 32 ? ? ground potential for external ? flmd0 3 no ? flmd1 52 input yes flash programming mode setting pin pdl5 intp0 15 p03 intp1 16 p04 intp2 17 external interrupt request input (maskable, analog noise elimination) p05 intp3 18 external interrupt request input (maskable, digital + anal og noise elimination) p06 intp4 42 p913 intp5 43 p914 intp6 44 p915 intp7 23 input yes external interrupt request input (maskable, analog noise elimination) p31/rxd0 kr0 28 p50/ti011/rtp00 kr1 29 p51/ti50/rtp01 kr2 30 p52/to50/rtp02 kr3 31 p53/rtp03 kr4 34 p54/rtp04 kr5 35 p55/rtp05 kr6 36 p90/txd1 kr7 37 input yes key return input p91/rxd1 nc 5 ? ? not internally connected. leave open. ? nmi 14 input yes external interrupt input (non-maskable, analog noise elimination) p02 reset 9 input ? system reset input ?
chapter 2 pin functions user?s manual u17705ej2v0ud 29 (2/2) pin name pin no. i/o pull-up resistor function alternate function rtp00 28 p50/ti011/kr0 rtp01 29 p51/ti50/kr1 rtp02 30 p52/to50/kr2 rtp03 31 p53/kr3 rtp04 34 p54/kr4 rtp05 35 output yes real-time output port p55/kr5 rxd0 23 serial receive data input for uart0 p31/intp7 rxd1 37 input yes serial receive data input for uart1 p91/kr7 sck00 21 p42 sck01 41 i/o yes serial clock i/o for csi00 and csi01 n-ch open-drain output can be specified in 1- bit units. p99 scl0 56 i/o no serial clock i/o for i 2 c0 fixed to n-ch open-drain output p39 sda0 55 i/o no serial transmit/receive data i/o for i 2 c0 fixed to n-ch open-drain output p38 si00 19 serial receive data input for csi00 p40 si01 39 input yes serial receive data input for csi01 p97 so00 20 p41 so01 40 output yes serial transmit data output for csi00 and csi01 n-ch open-drain output can be specified in 1-bit units. p98 ti010 27 capture trigger input/external event input for tm01 p35/to01 ti011 28 capture trigger input for tm01 p50/rtp00/kr0 ti50 29 external event input for tm50 p51/rtp01/kr1 ti51 38 external event input for tm51 p96/to51 tip00 25 capture trigger input/external event input for tmp0 p33/top00 tip01 26 input yes capture trigger input for tmp0 p34/top01 24 p32/asck0/adtrg to01 27 timer output for tm01 p35/ti010 to50 30 timer output for tm50 p52/rtp02/kr2 to51 38 timer output for tm51 p96/ti51 toh0 12 timer output for tmh0 p00 toh1 13 timer output for tmh1 p01 top00 25 p33/tip00 top01 26 output yes timer output for tmp0 p34/tip01 txd0 22 serial transmit data output for uart0 p30 txd1 36 output yes serial transmit data output for uart1 p90/kr6 v dd 4 ? ? positive power s upply pin for internal ? v ss 6 ? ? ground potential for internal ? x1 7 input no ? x2 8 ? no connecting resonator for main clock ? xt1 10 input no ? xt2 11 ? no connecting resonator for subclock ?
chapter 2 pin functions user?s manual u17705ej2v0ud 30 2.2 pin i/o circuits and recommend ed connection of unused pins (1/2) pin alternate function pin no. i/o circuit type recommended connection p00 toh0 12 p01 toh1 13 5-a p02 nmi 14 p03 to p06 intp0 to intp3 15 to 18 5-w p30 txd0 22 5-a p31 rxd0/intp7 23 p32 asck0/adtrg 24 p33 tip00/top00 25 p34 tip01/top01 26 p35 ti010/to01 27 5-w p38 sda0 55 p39 scl0 56 13-ad p40 si00 19 5-w p41 so00 20 10-e p42 sck00 21 10-f p50 ti011/rtp00/kr0 28 p51 ti50/rtp01/kr1 29 p52 to50/rtp02/kr2 30 p53 rtp03/kr3 31 p54 rtp04/kr4 34 p55 rtp05/kr5 35 8-a input: independently connect to ev dd or ev ss via a resistor. output: leave open. p70 to p77 ani0 to ani7 64 to 57 9-c connect to av ref0 or av ss . p90 txd1/kr6 36 p91 rxd1/kr7 37 p96 ti51/to51 38 8-a p97 si01 39 5-w p98 so01 40 10-e p99 sck01 41 10-f p913 to p915 intp4 to intp6 42 to 44 5-w pcm0 ? 45 pcm1 clkout 46 pdl0 to pdl4 ? 47 to 51 pdl5 flmd1 52 pdl6, pdl7 ? 53, 54 5-a input: independently connect to ev dd or ev ss via a resistor. output: leave open. av ref0 ? 1 ? directly connect to v dd . av ss ? 2 ? ? ev dd ? 33 ? ? ev ss ? 32 ? ?
chapter 2 pin functions user?s manual u17705ej2v0ud 31 (2/2) pin alternate function pin no. i/o circuit type recommended connection nc ? 5 ? leave open. reset ? 9 2 ? flmd0 ? 3 ? directly connect to ev ss or v ss or pull down with a 10 k resistor. v dd ? 4 ? ? v ss ? 6 ? ? x1 ? 7 ? ? x2 ? 8 ? ? xt1 ? 10 16 directly connect to v ss note . xt2 ? 11 16 leave open. note be sure to set the psmr.xtstp bit to 1 when this pin is not used.
chapter 2 pin functions user?s manual u17705ej2v0ud 32 2.3 pin i/o circuits (1/2) type 2 type 8-a type 9-c type 5-a type 5-w type 10-e schmitt-triggered input with hysteresis characteristics in data output disable p-ch in/out v dd n-ch input enable p-ch v dd pull-up enable in comparator + ? av ref0 (threshold voltage) p-ch n-ch input enable pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch data output disable v dd p-ch in/out n-ch open drain input enable pull-up enable v dd p-ch v ss av ss v ss v ss v ss type 10-f data output disable v dd p-ch in/out n-ch open drain input enable pull-up enable v dd p-ch v ss
chapter 2 pin functions user?s manual u17705ej2v0ud 33 (2/2) type 13-ad type 16 p-ch feedback cut-off xt1 xt2 data output disable input enable in/out n -ch v ss remark read v dd as ev dd . also, read v ss as ev ss .
user?s manual u17705ej2v0ud 34 chapter 3 cpu functions the cpu of the v850es/ke2 is based on th e risc architecture and executes mo st instructions in one clock cycle by using 5-stage pipeline control. 3.1 features { number of instructions: 83 { minimum instruction execution time: 50.0 ns (@ 20 mhz operation: 4.5 to 5.5 v) 100 ns (@ 10 mhz operation: 2.7 to 5.5 v) { memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear { general-purpose registers: 32 bits 32 { internal 32-bit architecture { 5-stage pipeline control { multiply/divide instructions { saturated operation instructions { 32-bit shift instruction: 1 clock { load/store instruction with long/short format { four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1
chapter 3 cpu functions user?s manual u17705ej2v0ud 35 3.2 cpu register set the cpu registers of the v850es/ke2 can be classified in to two categories: a general-purpose program register set and a dedicated system register set. all the registers have 32-bit width. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register)
chapter 3 cpu functions user?s manual u17705ej2v0ud 36 3.2.1 program register set the program register set includes general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are available. all of these registers c an be used as a data variable or address variable. however, r0 and r30 are implicitly us ed by instructions and care must be ex ercised when using these registers. r0 always holds 0 and is used for operations that use 0 and offset 0 addressing. r30 is used as a base pointer when performing memory access with the sld and sst instructions. also, r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. t herefore, before using these registers, their contents mu st be saved so that they are not lost, and they must be restor ed to the registers after the registers have been used. there are cases when r2 is used by the real-time os. if r2 is not used by the real-time os, r2 can be used as a variable register. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved regist er working register for generating 32-bit immediate r2 address/data variable register (when r2 is not used by the real-time os to be used) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (area for placing program code) r6 to r29 address/data variable register r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution (2) program counter (pc) this register holds the address of the in struction under execution. the lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occu rs from bit 25 to bit 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address under execution 0 after reset 00000000h
chapter 3 cpu functions user?s manual u17705ej2v0ud 37 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. read from and write to system regist ers are performed by setting the system register numbers shown below with the system register load/st ore instructions (ldsr, stsr instructions). table 3-2. system register numbers operand specification enabled system register no. system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 yes yes 1 interrupt status saving register (eipsw) note 1 yes yes 2 nmi status saving register (fepc) note 1 yes yes 3 nmi status saving register (fepsw) note 1 yes yes 4 interrupt source register (ecr) no yes 5 program status word (psw) yes yes 6 to 15 reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no 16 callt execution status saving register (ctpc) yes yes 17 callt execution status saving register (ctpsw) yes yes 18 exception/debug trap status saving register (dbpc) yes note 2 yes note 2 19 exception/debug trap status saving register (dbpsw) yes note 2 yes note 2 20 callt base pointer (ctbp) yes yes 21 to 31 reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no notes 1. since only one set of these registers is available, the contents of this register must be saved by the program when multiple interrupt servicing is enabled. 2. these registers can be accessed only during the interval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. caution even if bit 0 of eipc, fepc, or ctpc is set (1) by the ldsr instruction, bit 0 is ignored during return with the reti instruction following interrupt servicing (because bit 0 of pc is fixed to 0). when setting a value to eipc, fepc, and ctpc, set an even number (bit 0 = 0).
chapter 3 cpu functions user?s manual u17705ej2v0ud 38 (1) interrupt status saving registers (eipc, eipsw) there are two interrupt status sa ving registers, eipc and eipsw. upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (pc) are saved to eipc and the contents of the program status word (psw) are saved to eipsw (upon occurrence of a non-maskable interrupt (nmi), t he contents are saved to the nmi status saving registers (fepc, fepsw)). the address of the next instruction fo llowing the instruction executed when a software exception or maskable interrupt occurs is saved to eipc, e xcept for some instructions (refer to 17.9 period in which interrupts are not acknowledged by cpu ). the current psw contents are saved to eipsw. since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are rese rved (fixed to 0) for future function expansion. when the reti instruction is execut ed, the values in eipc and eipsw are restored to the pc and psw, respectively. 31 0 eipc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
chapter 3 cpu functions user?s manual u17705ej2v0ud 39 (2) nmi status saving registers (fepc, fepsw) there are two nmi status saving registers, fepc and fepsw. upon occurrence of a non-maskable interrupt (nmi), the contents of the program co unter (pc) are saved to fepc and the contents of the program status word (psw) are saved to fepsw. the address of the next instruction fo llowing the instruction executed when a non-maskable interrupt occurs is saved to fepc, except fo r some instructions. the current psw contents are saved to fepsw. since there is only one set of nmi stat us saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is performed. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served (fixed to 0) for future function expansion. when the reti instruction is exec uted, the values in fepc and fepsw are restored to the pc and psw, respectively. 31 0 fepc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (3) interrupt source register (ecr) upon occurrence of an interrupt or an exception, the inte rrupt source register (ecr) holds the source of an interrupt or an exception. the value held by ecr is the exception code c oded for each interrupt source. this register is a read-only register, and thus data cannot be written to it using the ldsr instruction. 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name description 31 to 16 fecc non-maskable interrupt (nmi) exception code 15 to 0 eicc exception, maskable interrupt exception code
chapter 3 cpu functions user?s manual u17705ej2v0ud 40 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the program status (instruction execution result) and the cpu status. when the contents of this register are changed using the ldsr instruct ion, the new contents become valid immediately following completion of ldsr instruction execution. interrupt request acknowledgment is held pending while a write to the psw is being executed by the ldsr instruction. bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name description 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that non-maskable interrupt (nmi) servici ng is in progress. this flag is set to 1 when an nmi request is acknowledged, and disables multiple interrupts. 0: nmi servicing not in progress 1: nmi servicing in progress 6 ep indicates that exception processing is in prog ress. this flag is set to 1 when an exception occurs. moreover, interrupt requests can be acknowledged even when this bit is set. 0: exception processing not in progress 1: exception processing in progress 5 id indicates whether maskable interrupt r equest acknowledgment is enabled. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do no t become saturated. this flag is neither set nor cleared when arithmetic operation instructions are executed. 0: not saturated 1: saturated 3 cy indicates whether carry or borrow occu rred as the result of an operation. 0: no carry or borrow occurred 1: carry or borrow occurred 2 ov note indicates whether overflow o ccurred during an operation. 0: no overflow occurred 1: overflow occurred. 1 s note indicates whether the result of an operation is negative. 0: operation result is positive or 0. 1: operation result is negative. 0 z indicates whether operation result is 0. 0: operation result is not 0. 1: operation result is 0. remark note is explained on the following page.
chapter 3 cpu functions user?s manual u17705ej2v0ud 41 (2/2) note during saturated operation, the saturated operation results are dete rmined by the contents of the ov flag and s flag. the sat flag is set (to 1) only when the ov flag is set (to 1) during saturated operation. flag status operation result status sat ov s saturated operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (maximum value not exceeded) 0 negative (maximum value not exceeded) holds value before operation 0 1 actual operation result (5) callt execution status saving registers (ctpc, ctpsw) there are two callt execut ion status saving registers, ctpc and ctpsw. when the callt instruction is execut ed, the contents of the program count er (pc) are saved to ctpc, and the program status word (psw) contents are saved to ctpsw. the contents saved to ctpc consist of the address of the next instructi on after the callt instruction. the current psw contents are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are re served (fixed to 0) for future function expansion. 31 0 ctpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
chapter 3 cpu functions user?s manual u17705ej2v0ud 42 (6) exception/debug trap status saving registers (dbpc, dbpsw) there are two exception/de bug trap status saving registers, dbpc and dbpsw. upon occurrence of an exception trap or debug trap, the contents of the program counter (pc) are saved to dbpc, and the program status word (psw) contents are saved to dbpsw. the contents saved to dbpc consist of the address of the next instructi on after the instruction executed when an exception trap or debug trap occurs. the current psw contents are saved to dbpsw. these registers can be read or wr itten only during the interval betw een the execution of the dbtrap instruction or illegal opcode and the dbret instruction. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are re served (fixed to 0) for future function expansion. when the dbret instruction is exec uted, the values in dbpc and dbps w are restored to the pc and psw, respectively. 31 0 dbpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify table addresses and generate target addresses (bit 0 is fixed to 0). bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 0 ctbp (base address) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0
chapter 3 cpu functions user?s manual u17705ej2v0ud 43 3.3 operating modes the v850es/ke2 has the foll owing operating modes. (1) normal operating mode after the system has been released from the reset state, t he pins related to the bus in terface are set to the port mode, execution branches to the reset entry address of the internal rom, and instruction processing is started. (2) flash memory programming mode when this mode is specified, the internal flash me mory can be programmed by using a flash programmer. (a) specifying operating mode the operating mode is specified acco rding to the status (input leve l) of the flmd0 and flmd1 pins. in the normal operating mode, input a low level to the flmd0 pin during the reset period. a high level is input to the flmd0 pin by the flash programmer in the flash memory programming mode if a flash programmer is connected. in the self-programming mode, input a high level to this pin from an external circuit. fix the specification of these pins in the application system and do not change the setting of these pins during operation. flmd0 flmd1 operating mode l normal operating mode h l flash memory programming mode h h setting prohibited remark h: high level l: low level : don?t care
chapter 3 cpu functions user?s manual u17705ej2v0ud 44 3.4 address space 3.4.1 cpu address space for instruction addressing, an internal rom area of up to 1 mb, and an internal ram area are supported in a linear address space (program space) of up to 64 mb. for op erand addressing (data access), up to 4 gb of a linear address space (data space) is supported. the 4 gb address space, however, is viewed as 64 images of a 64 mb physical address space. this means that the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. address space image program space internal ram area access-prohibited area reserved area internal rom area data space image 63 image 1 image 0 on-chip peripheral i/o area internal ram area access-prohibited area external memory area internal rom area (external memory) 1 mb 4 gb 64 mb ? ? ? 64 mb
chapter 3 cpu functions user?s manual u17705ej2v0ud 45 3.4.2 wraparound of cpu address space (1) program space of the 32 bits of the program counter (p c), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calc ulation, the higher 6 bits ignore this and remain 0. therefore, the lower-limit address of the program space, 0000 0000h, and the upper-limit address, 03ffffffh, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. caution no instructions can be fetched from the 4 kb area of 03fff000h to 03ffffffh because this area is an on-chip peripheral i/o area. the refore, do not execute any branch operation instructions in which the destination addres s will reside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction (?) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit addre ss of the data space, address 0000 0000h, and the upper-limit address, ffffffffh, are contiguous addresses, and the data space is wrapped around at t he boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction (?) direction
chapter 3 cpu functions user?s manual u17705ej2v0ud 46 3.4.3 memory map the v850es/ke2 has reserved areas as shown below. figure 3-2. data memory map (physical addresses) 3ffffffh 3fec000h 3febfffh 00fffffh 0000000h 3fff000h 3ffefffh 3fff000h 3ffefffh 3ffffffh 3fec000h (80 kb) use-prohibited area internal ram area (60 kb) on-chip peripheral i/o area (4 kb) use-prohibited area internal rom area (1 mb)
chapter 3 cpu functions user?s manual u17705ej2v0ud 47 figure 3-3. program memory map 03ff0000h 03feffffh 03fff000h 03ffefffh 03ffffffh 00100000h 000fffffh 00000000h internal ram area (60 kb) use-prohibited area (program fetch disabled area) use-prohibited area (program fetch disabled area) internal rom area (1 mb)
chapter 3 cpu functions user?s manual u17705ej2v0ud 48 3.4.4 areas (1) internal rom area an area of 1 mb from 0000000h to 00fffffh is reserved for the internal rom area. (a) internal rom (128 kb) a 128 kb area from 0000000h to 001ffffh is provided in the pd70f3726. addresses 0020000h to 00fffffh are an access-prohibited area. figure 3-4. internal rom area (128 kb) 00fffffh 0020000h 001ffffh 0000000h access-prohibited area internal rom area (128 kb) (2) internal ram area an area of 60 kb maximum from 3ff0000h to 3ffef ffh is reserved for the internal ram area. a 4 kb area from 3ffe000h to 3ffefffh is provided as physical internal ram. addresses 3ff0000h to 3ffdfffh is an access-prohibited area. figure 3-5. internal ram area (4 kb) access-prohibited area 3ffefffh 3ffe000h 3ffdfffh 3ff0000h fffefffh fffe000h fffdfffh fff0000h physical address space logical address space internal ram area (4 kb)
chapter 3 cpu functions user?s manual u17705ej2v0ud 49 (3) on-chip peripheral i/o area a 4 kb area from 3fff000h to 3ffffffh is rese rved as the on-chip peripheral i/o area. figure 3-6. on-chip peripheral i/o area 3ffffffh 3fff000h on-chip peripheral i/o area (4 kb) fffffffh ffff000h physical address space logical address space peripheral i/o registers assigned with functions such as on-chip peripheral i/o operation mode specification and state monitoring are mapped to the on-chip peripheral i/o area. program fetches are not allowed in this area. cautions 1. if word access of a register is atte mpted, halfword access to th e word area is performed twice, first for the lower bits , then for the higher bits, ignoring the lower 2 address bits. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined if the access is a read operation. if a write access is performed, only the data in the lower 8 bits is written to the register. 3. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. (4) number of clocks for access the following table shows the number of base clocks required for accessing each resource. area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) on-chip peripheral i/o (16 bits) instruction fetch (normal access) 1 1 note 1 ? instruction fetch (branch) 2 2 note 1 ? operand data access 3 1 3 note 2 notes 1. if the access conflicts with a data access, th e number of clock is incremented by 1. 2. this value varies depending on the setting of the vswc register. remark unit: clocks/access
chapter 3 cpu functions user?s manual u17705ej2v0ud 50 3.4.5 recommended use of address space the architecture of the v850es/ke2 r equires that a register that serves as a pointer be secured for address generation when operand data in t he data space is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. be cause the number of general-pur pose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose regist ers as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program count er), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, theref ore, a 64 mb space of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the program s pace, access address 3ffe 000h to 3ffefffh (4 kb). (2) data space with the v850es/ke2, it seems that there are sixty-four 64 mb addres s spaces on the 4 gb cpu address space. therefore, the least signific ant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st disp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by har dware, and practically elimin ates the need for registers dedicated to pointers. internal rom area on-chip peripheral i/o area access-prohibited area 3 2 kb 4 kb 24 kb (r = ) 0001ffffh 00007fffh 00000000h fffff000h ffffefffh ffff8000h internal ram area ffffe000h ffffdfffh 4 kb
chapter 3 cpu functions user?s manual u17705ej2v0ud 51 figure 3-7. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom use prohibited use prohibited internal ram use prohibited program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh fffec000h fffebfffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ffe000h 03ffdfffh 03fec000h 03febfffh 00020000h 0001ffffh 00100000h 000fffffh 00000000h xfffffffh xffff000h xfffefffh xfffe000h xfffdfffh xffec000h xffebfffh x0100000h x00fffffh x0000000h remark indicates the recommended area.
chapter 3 cpu functions user?s manual u17705ej2v0ud 52 3.4.6 peripheral i/o registers (1/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff004h port dl register pdl r/w 00h note fffff00ch port cm register pcm r/w 00h note fffff024h port dl mode register pmdl r/w ffh fffff02ch port cm mode register pmcm r/w ffh fffff04ch port cm mode control register pmccm r/w 00h fffff06eh system wait control register vswc r/w 77h fffff100h interrupt mask register 0 imr0 r/w ffffh fffff100h interrupt mask register 0l imr0l r/w ffh fffff101h interrupt mask register 0h imr0h r/w ffh fffff102h interrupt mask register 1 imr1 r/w ffffh fffff102h interrupt mask register 1l imr1l r/w ffh fffff103h interrupt mask register 1h imr1h r/w ffh fffff106h interrupt mask register 3 imr3 r/w ffffh fffff106h interrupt mask register 3l imr3l r/w ffh fffff110h interrupt control register wdt1ic r/w 47h fffff112h interrupt control register pic0 r/w 47h fffff114h interrupt control register pic1 r/w 47h fffff116h interrupt control register pic2 r/w 47h fffff118h interrupt control register pic3 r/w 47h fffff11ah interrupt control register pic4 r/w 47h fffff11ch interrupt control register pic5 r/w 47h fffff11eh interrupt control register pic6 r/w 47h fffff124h interrupt control register tm0ic10 r/w 47h fffff126h interrupt control register tm0ic11 r/w 47h fffff128h interrupt control register tm5ic0 r/w 47h fffff12ah interrupt control register tm5ic1 r/w 47h fffff12ch interrupt control register csi0ic0 r/w 47h fffff12eh interrupt control register csi0ic1 r/w 47h fffff130h interrupt control register sreic0 r/w 47h fffff132h interrupt control register sric0 r/w 47h fffff134h interrupt control register stic0 r/w 47h fffff136h interrupt control register sreic1 r/w 47h fffff138h interrupt control register sric1 r/w 47h fffff13ah interrupt control register stic1 r/w 47h fffff13ch interrupt control register tmhic0 r/w 47h fffff13eh interrupt control register tmhic1 r/w 47h fffff142h interrupt control register iicic0 r/w 47h fffff144h interrupt control register adic r/w 47h fffff146h interrupt control register kric r/w 47h note the output latch is 00h. when input, the pin status is read.
chapter 3 cpu functions user?s manual u17705ej2v0ud 53 (2/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff148h interrupt control register wtiic r/w 47h fffff14ah interrupt control register wtic r/w 47h fffff14ch interrupt control register brgic r/w 47h fffff172h interrupt control register pic7 r/w 47h fffff174h interrupt control register tp0ovic r/w 47h fffff176h interrupt control register tp0ccic0 r/w 47h fffff178h interrupt control register tp0ccic1 r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc r/w 00h fffff200h a/d converter mode register adm r/w 00h fffff201h analog input channel specification register ads r/w 00h fffff202h power fail comparison mode register pfm r/w 00h fffff203h power fail comparison threshold register pft r/w 00h fffff204h a/d conversion result register adcr r undefined fffff205h a/d conversion result register h adcrh r undefined fffff300h key return mode register krm r/w 00h fffff30ah selector operation control register 1 selcnt1 r/w 00h fffff318h digital noise elimination control register nfc r/w 00h fffff400h port 0 register p0 r/w 00h note fffff406h port 3 register p3 r/w 0000h note fffff406h port 3 register l p3l r/w 00h note fffff407h port 3 register h p3h r/w 00h note fffff408h port 4 register p4 r/w 00h note fffff40ah port 5 register p5 r/w 00h note fffff40eh port 7 register p7 r undefined fffff412h port 9 register p9 r/w 0000h note fffff412h port 9 register l p9l r/w 00h note fffff413h port 9 register h p9h r/w 00h note fffff420h port 0 mode register pm0 r/w ffh fffff426h port 3 mode register pm3 r/w ffffh fffff426h port 3 mode register l pm3l r/w ffh fffff427h port 3 mode register h pm3h r/w ffh fffff428h port 4 mode register pm4 r/w ffh fffff42ah port 5 mode register pm5 r/w ffh fffff432h port 9 mode register pm9 r/w ffffh fffff432h port 9 mode register l pm9l r/w ffh fffff433h port 9 mode register h pm9h r/w ffh fffff440h port 0 mode control register pmc0 r/w 00h note the output latch is 00h or 0000h. when input, the pin status is read.
chapter 3 cpu functions user?s manual u17705ej2v0ud 54 (3/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff446h port 3 mode control register pmc3 r/w 0000h fffff446h port 3 mode control register l pmc3l r/w 00h fffff447h port 3 mode control register h pmc3h r/w 00h fffff448h port 4 mode control register pmc4 r/w 00h fffff44ah port 5 mode control register pmc5 r/w 00h fffff452h port 9 mode control register pmc9 r/w 0000h fffff452h port 9 mode control register l pmc9l r/w 00h fffff453h port 9 mode control register h pmc9h r/w 00h fffff466h port 3 function control register pfc3 r/w 00h fffff46ah port 5 function control register pfc5 r/w 00h fffff472h port 9 function control register pfc9 r/w 0000h fffff472h port 9 function control register l pfc9l r/w 00h fffff473h port 9 function control register h pfc9h r/w 00h fffff580h 8-bit timer h mode register 0 tmhmd0 r/w 00h fffff581h 8-bit timer h carrier control register 0 tmcyc0 r/w 00h fffff582h 8-bit timer h compare register 00 cmp00 r/w 00h fffff583h 8-bit timer h compare register 01 cmp01 r/w 00h fffff590h 8-bit timer h mode register 1 tmhmd1 r/w 00h fffff591h 8-bit timer h carrier control register 1 tmcyc1 r/w 00h fffff592h 8-bit timer h compare register 10 cmp10 r/w 00h fffff593h 8-bit timer h compare register 11 cmp11 r/w 00h fffff5a0h tmp0 control register 0 tp0ctl0 r/w 00h fffff5a1h tmp0 control register 1 tp0ctl1 r/w 00h fffff5a2h tmp0 i/o control register 0 tp0ioc0 r/w 00h fffff5a3h tmp0 i/o control register 1 tp0ioc1 r/w 00h fffff5a4h tmp0 i/o control register 2 tp0ioc2 r/w 00h fffff5a5h tmp0 option register 0 tp0opt0 r/w 00h fffff5a6h tmp0 capture/compare register 0 tp0ccr0 r/w 0000h fffff5a8h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff5aah tmp0 counter read buffer register tp0cnt r 0000h fffff5c0h 16-bit timer counter 5 tm5 r 0000h fffff5c0h 8-bit timer counter 50 tm50 r 00h fffff5c1h 8-bit timer counter 51 tm51 r 00h fffff5c2h 16-bit timer compare register 5 cr5 r/w 0000h fffff5c2h 8-bit timer compare register 50 cr50 r/w 00h fffff5c3h 8-bit timer compare register 51 cr51 r/w 00h fffff5c4h timer clock selection register 5 tcl5 r/w 0000h fffff5c4h timer clock selection register 50 tcl50 r/w 00h fffff5c5h timer clock selection register 51 tcl51 r/w 00h
chapter 3 cpu functions user?s manual u17705ej2v0ud 55 (4/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffff5c6h 16-bit timer mode control register 5 tmc5 r/w 0000h fffff5c6h 8-bit timer mode control register 50 tmc50 r/w 00h fffff5c7h 8-bit timer mode control register 51 tmc51 r/w 00h fffff610h 16-bit timer counter 01 tm01 r 0000h fffff612h 16-bit timer capture/compare register 010 cr010 r/w 0000h fffff614h 16-bit timer capture/compare register 011 cr011 r/w 0000h fffff616h 16-bit timer mode control register 01 tmc01 r/w 00h fffff617h prescaler mode register 01 prm01 r/w 00h fffff618h capture/compare control register 01 crc01 r/w 00h fffff619h 16-bit timer output control register 01 toc01 r/w 00h fffff680h watch timer operation mode register wtm r/w 00h fffff6c0h oscillation stabilization time selection register osts r/w 01h fffff6c1h watchdog timer clock sele ction register wdcs r/w 00h fffff6c2h watchdog timer mode register 1 wdtm1 r/w 00h fffff6d0h watchdog timer mode register 2 wdtm2 r/w 67h fffff6d1h watchdog timer enable register wdte r/w 9ah fffff6e0h real-time output buffer register l0 rtbl0 r/w 00h fffff6e2h real-time output buffer register h0 rtbh0 r/w 00h fffff6e4h real-time output port mode register 0 rtpm0 r/w 00h fffff6e5h real-time output port control register 0 rtpc0 r/w 00h fffff706h port 3 function control expansion register pfce3 r/w 00h fffff802h system status register sys r/w 00h fffff806h pll control register pllctl r/w 01h fffff820h power save mode register psmr r/w 00h fffff828h processor clock control register pcc r/w 03h fffff8b0h interval timer brg mode register prsm r/w 00h fffff8b1h interval timer brg compare register prscm r/w 00h fffffa00h asynchronous serial interface mode register 0 asim0 r/w 01h fffffa02h receive buffer register 0 rxb0 r ffh fffffa03h asynchronous serial interfac e status register 0 asis0 r 00h fffffa04h transmit buffer register 0 txb0 r/w ffh fffffa05h asynchronous serial interface transmit status register 0 asif0 r 00h fffffa06h clock select register 0 cksr0 r/w 00h fffffa07h baud rate generator control register 0 brgc0 r/w ffh fffffa10h asynchronous serial interface mode register 1 asim1 r/w 01h fffffa12h receive buffer register 1 rxb1 r ffh fffffa13h asynchronous serial interf ace status register 1 asis1 r 00h fffffa14h transmit buffer register 1 txb1 r/w ffh fffffa15h asynchronous serial interface transmit status register 1 asif1 r 00h fffffa16h clock select register 1 cksr1 r/w 00h fffffa17h baud rate generator control register 1 brgc1 r/w ffh
chapter 3 cpu functions user?s manual u17705ej2v0ud 56 (5/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffb00h tip00 noise elimination control register p0nfc r/w 00h fffffb04h tip01 noise elimination control register p1nfc r/w 00h fffffc00h external interrupt falling edge specification register 0 intf0 r/w 00h fffffc06h external interrupt falling edge specification register 3 intf3 r/w 00h fffffc13h external interrupt falling edge specification register 9h intf9h r/w 00h fffffc20h external interrupt rising edge specification register 0 intr0 r/w 00h fffffc26h external interrupt rising edge specification register 3 intr3 r/w 00h fffffc33h external interrupt rising edge specification register 9h intr9h r/w 00h fffffc40h pull-up resistor option register 0 pu0 r/w 00h fffffc46h pull-up resistor option register 3 pu3 r/w 00h fffffc48h pull-up resistor option register 4 pu4 r/w 00h fffffc4ah pull-up resistor option register 5 pu5 r/w 00h fffffc52h pull-up resistor option register 9 pu9 r/w 0000h fffffc52h pull-up resistor option register 9l pu9l r/w 00h fffffc53h pull-up resistor option register 9h pu9h r/w 00h fffffc67h port 3 function register h pf3h r/w 00h fffffc68h port 4 function register pf4 r/w 00h fffffc73h port 9 function register h pf9h r/w 00h fffffd00h clocked serial interf ace mode register 00 csim00 r/w 00h fffffd01h clocked serial interface clock selection register 0 csic0 r/w 00h fffffd02h clocked serial interface re ceive buffer register 0 sirb0 r 0000h fffffd02h clocked serial interface receive buffer register 0l sirb0l r 00h fffffd04h clocked serial interface tran smit buffer register 0 sotb0 r/w 0000h fffffd04h clocked serial interface tr ansmit buffer register 0l sotb0l r/w 00h fffffd06h clocked serial interface read-onl y receive buffer register 0 sirbe0 r 0000h fffffd06h clocked serial interface read- only receive buffer register 0l sirbe0l r 00h fffffd08h clocked serial interface initial transmit buffer register 0 sotbf0 r/w 0000h fffffd08h clocked serial interface initia l transmit buffer register 0l sotbf0l r/w 00h fffffd0ah serial i/o shift register 0 sio00 r/w 00h fffffd0ah serial i/o shift register 0l sio00l r/w 0000h fffffd10h clocked serial interf ace mode register 01 csim01 r/w 00h fffffd11h clocked serial interface clock selection register 1 csic1 r/w 00h fffffd12h clocked serial interface re ceive buffer register 1 sirb1 r 0000h fffffd12h clocked serial interface receive buffer register 1l sirb1l r 00h fffffd14h clocked serial interface tran smit buffer register 1 sotb1 r/w 0000h fffffd14h clocked serial interface tr ansmit buffer register 1l sotb1l r/w 00h fffffd16h clocked serial interface read-onl y receive buffer register 1 sirbe1 r 0000h fffffd16h clocked serial interface read- only receive buffer register 1l sirbe1l r 00h fffffd18h clocked serial interface initial transmit buffer register 1 sotbf1 r/w 0000h fffffd18h clocked serial interface initia l transmit buffer register 1l sotbf1l r/w 00h
chapter 3 cpu functions user?s manual u17705ej2v0ud 57 (6/6) operable bit unit address function register name symbol r/w 1 8 16 after reset fffffd1ah serial i/o shift register 1 sio01 r/w 00h fffffd1ah serial i/o shift register 1l sio01l r/w 0000h fffffd80h iic shift register 0 iic0 r/w 00h fffffd82h iic control register 0 iicc0 r/w 00h fffffd83h slave address register 0 sva0 r/w 00h fffffd84h iic clock selection register 0 iiccl0 r/w 00h fffffd85h iic function expansion register 0 iicx0 r/w 00h fffffd86h iic status register 0 iics0 r 00h fffffd8ah iic flag register 0 iicf0 r/w 00h ffffff44h pull-up resistor option register dl pudl r/w 00h ffffff4ch pull-up resistor option register cm pucm r/w 00h
chapter 3 cpu functions user?s manual u17705ej2v0ud 58 3.4.7 special registers special registers are registers that prevent invalid da ta from being written when an inadvertent program loop occurs. the v850es/ke2 has the follo wing three special registers. ? power save control register (psc) ? processor clock control register (pcc) ? watchdog timer mode register (wdtm1) moreover, there is also the prcmd r egister, which is a protection register for write operations to the special registers that prevents the application system from unexpectedly stopping due to an inadvertent program loop. write access to the special registers is performed with a specia l sequence and illegal store oper ations are notified to the sys register. (1) setting data to special registers setting data to a special registers is done in the following sequence. <1> prepare the data to be set to the specia l register in a general-purpose register. <2> write the data prepared in st ep <1> to the prcmd register. <3> write the setting data to the special regi ster (using following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <4> to <8> insert nop inst ructions (5 instructions) note . [description example] when using psc register (standby mode setting) st.b r11,psmr[r0] ; psmr register setting (idle, stop mode setting) <1> mov 0x02,r10 <2> st.b r10,prcmd[r0] ; prcmd register write <3> st.b r10,psc[r0] ; psc register setting <4> nop note ; dummy instruction <5> nop note ; dummy instruction <6> nop note ; dummy instruction <7> nop note ; dummy instruction <8> nop note ; dummy instruction (next instruction) no special sequence is required to read special registers. note when switching to the idle mode or the stop m ode (psc.stp bit = 1), 5 nop instructions must be inserted immediately after switching is performed. cautions 1. interrupts are not acknowledged for the store instruction for the prcmd register. this is because continuous execution of store instructi ons by the program in steps <2> and <3> above is assumed. if another instruction is placed between step <2> and <3>, the above sequence may not be realized when an interrupt is acknowle dged for that instruction, which may cause malfunction. 2. the data written to the prcmd register is dummy data, but use the same register as the general-purpose register used for setting data to the special register (step <3>) when writing to the prcmd register (step <2>). the same applies to when using a general- purpose register for addressing.
chapter 3 cpu functions user?s manual u17705ej2v0ud 59 (2) command register (prcmd) the prcmd register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop, when an inadvertent program loop occurs. only the first write operat ion to the special register following the execution of a previously executed writ e operation to the prcmd register, is valid. as a result, register values can be overwritten onl y using a preset sequence, preventing invalid write operations. this register can only be written in 8-bit units (if it is read, an undefined value is returned). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch (3) system status register (sys) this register is allocated with status flags showing the operat ing state of the entire system. this register can be read or writt en in 8-bit or 1-bit units. 0 protection error has not occurred protection error has occurred prerr 0 1 detection of protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < >
chapter 3 cpu functions user?s manual u17705ej2v0ud 60 the operation conditions of the prerr flag are described below. (a) set conditions (prerr = 1) (i) when a write operation to the s pecial register takes place without write operation being performed to the prcmd register (when step <3> is performed without performing step <2> as described in 3.4.7 (1) setting data to special registers ). (ii) when a write operation (including bit manipulation instruction) to an on-chip peripheral i/o register other than a special register is performed follo wing write to the prcmd register (when <3> in 3.4.7 (1) setting data to special registers is not a special register). remark regarding the special registers other than the wdtm register (pcc and psc registers), even if on-chip peripheral i/o register read (except bit ma nipulation instruction) (internal ram access, etc.) is performed in between wr ite to the prcmd register and wr ite to a special register, the prerr flag is not set and setting data can be written to the special register. (b) clear conditions (prerr = 0) (i) when 0 is written to the prerr flag (ii) when system reset is performed cautions 1. if 0 is written to the prerr bit of the sys register that is not a special register immediately following write to the prcmd re gister, the prerr bi t becomes 0 (write priority). 2. if data is written to the prcmd register that is not a special register immediately following write to the prcmd regist er, the prerr bit becomes 1.
chapter 3 cpu functions user?s manual u17705ej2v0ud 61 3.4.8 cautions (1) registers to be set first be sure to set the following registers first when using the v850es/ke2. ? system wait control register (vswc) ? watchdog timer mode register 2 (wdtm2) after setting the vswc and wdtm2 registers, set the other registers as necessary. when using the external bus, set each pin to the alternate-function bus control pin mode by using the port- related registers after setting the above registers. (a) system wait control register (vswc) the vswc register controls the bus access wait ti me for the on-chip perip heral i/o registers. access to the on-chip peripheral i/o register lasts 3 cl ocks (during no wait), but in the v850es/ke2, waits are required according to the internal system clo ck frequency. set the values shown below to the vswc register according to the internal system clock frequency that is used. this register can be read or written in 8-bit units (address: fffff06eh, after reset: 77h). operation conditions internal system clock frequency (f clk ) vswc register setting number of waits 32 khz f clk < 16.6 mhz 00h 0 (no waits) 4.5 v v dd 5.5 v 16.6 mhz f clk 20 mhz 01h 1 4.0 v v dd < 4.5 v 32 khz f clk 16 mhz 00h 0 (no waits) 32 khz f clk < 8.3 mhz 00h 0 (no waits) 2.7 v v dd < 4.0 v 8.3 mhz f clk 10 mhz 01h 1 (b) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time a nd the operation clock of watchdog timer 2. watchdog timer 2 automatically starts in the reset mode after reset is released. write the wdtm2 register to activate this operation. for details, refer to chapter 11 watchdog timer functions .
chapter 3 cpu functions user?s manual u17705ej2v0ud 62 (2) access to special on-chip peripheral i/o register this product has two types of internal system buses. one type is for the cpu bus and the ot her is for the peripheral bus to interface with low-speed peripheral hardware. since the cpu bus clock and peripheral bus clock are asynchronous, if a conflict occurs during access between the cpu and peripheral hardware, illegal dat a may be passed unexpectedly. therefore, when accessing peripheral hardware that may cause a conflic t, the number of access cycles is changed so that the data is received/passed correctly in the cpu. as a result, the cpu does not shift to the next instruction processing and enters the wait status. when this wait status occurs, the number of execution clocks of the instruction is increased by the number of wait clocks. note this with caution when performing real-time processing. when accessing a special on-chip peri pheral i/o register, additional waits ma y be required further to the waits set by the vswc register. the access conditions at that time and the method to calc ulate the number of waits to be inserted (number of cpu clocks) are shown below. number of waits to be inserted = (2 + m) k (clocks) number of accesses to specific on-chip peripheral i/o register = 3 + m + (2 + m) k (clocks)
chapter 3 cpu functions user?s manual u17705ej2v0ud 63 peripheral function register name access k wdtm1 write 1 to 5 watchdog timer 1 (wdt1) k = {(1/f x ) 2/((2 + m)/f cpu )} + 1 f x : main clock oscillation frequency watchdog timer 2 (wdt2) wdtm2 write 3 (fixed) tp0ccr0, tp0ccr1, tp0cnt read 1 k = {(1/f xx )/((2 + m)/f cpu )} + 1 tp0ccr0, tp0ccr1 write 0 to 2 16-bit timer/event counter p0 (tmp0) k = {(1/f xx ) 5/((2 + m)/f cpu )} a wait occurs when performing co ntinuous write to same register 16-bit timer/event counter 01 (tm01) tmc01 read-modify-write 1 (fixed) a wait occurs during write i 2 c0 iics0 read 1 (fixed) asynchronous serial interfaces 0 and 1 (uart0, uart1) asis0, asis1 read 1 (fixed) real-time output function 0 (rto0) rtbl0, rtbh0 write (when rtpc0.rtpoe0 bit = 0) 1 adm, ads, pfm, pft write 1 or 2 adcr, adcrh read 1 or 2 a/d converter {(1/f xx ) 2/[(2 + m)/f cpu ]} + 1 note in the calculation of number of waits, the fractional part of its result must be multiplied by (1/f cpu ) and rounded down if (1/f cpu )/(2 + m) or lower, and rounded up if (1/f cpu )/(2 + m) is exceeded. cautions 1. if fetched from the internal rom or internal ram, the number of waits is as shown above. if fetched from the external memory, the number of waits may be decreased below these. the effect of the external memory access cycles varies depending on the wait settings and the like. however, the number of waits show n above is the maximum value, so no higher value is generated. 2. when the cpu operates on the subclock and no clock is input to the x1 pin, do not access a register in which a wait occurs. if a wait occurs, it can only be released by a reset. remark in the calculation for the number of waits: f cpu : cpu clock frequency f xx : main clock frequency m: set value of bits 2 to 0 of the vswc register when the vswc register = 00h: m = 0 when the vswc register = 01h: m = 1
chapter 3 cpu functions user?s manual u17705ej2v0ud 64 (3) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the dec ode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of t he instruction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 ld.w [r11], r10 if the decode operation of the mo v instruction immediately before the sld instruction and an interrupt request conflict before exec ution of the ld instruction is complete, the executi on result of instruction may not be stored in a register. mov r10, r28 sld.w 0x28, r10 (b) countermeasure <1> when compiler (ca850) is used use ca850 ver. 2.61 or later because generati on of the corresponding instruction sequence can be automatically suppressed. <2> countermeasure by assembler when executing the sld instruction immediately afte r instruction , avoid the above operation using either of the following methods. ? insert a nop instruction immediat ely before the sld instruction. ? do not use the same register as the sld instructi on destination register in the above instruction executed immediately befor e the sld instruction. ? ? ?
user?s manual u17705ej2v0ud 65 chapter 4 port functions 4.1 features { input-only ports: 8 pins { i/o ports: 43 pins ? fixed to n-ch open-drain output: 2 ? switchable to n-ch open-drain output: 6 { input/output can be specified in 1-bit units 4.2 basic port configuration the v850es/ke2 incorporates a total of 51 i/o port pins consis ting of ports 0, 3 to 5, 7, 9, cm, and dl (including 8 input-only port pins). the port configuration is shown below. p00 p06 port 0 p90 p91 p96 p99 p913 p915 port 9 pcm0 pcm1 port cm pdl0 pdl7 port dl p30 p35 p38 p39 port 3 p40 p42 port 4 p50 p55 port 5 p70 p77 port 7 table 4-1. pin i/o buffer power supplies of v850es/ke2 power supply corresponding pins av ref0 port 7 ev dd reset, ports 0, 3 to 5, 9, cm, dl
chapter 4 port functions user?s manual u17705ej2v0ud 66 4.3 port configuration table 4-2. port configuration item configuration control registers port n register (pn: n = 0, 3 to 5, 7, 9, cm, dl) port n mode register (pmn: n = 0, 3 to 5, 9, cm, dl) port n mode control register (pmcn: n = 0, 3 to 5, 9, cm) port n function control register (pfcn: n = 3, 5, 9) port n function register (pfn: n = 3, 4, 9) port 3 function control expansion register (pfce3) pull-up resistor option register (pun: n = 0, 3 to 5, 9, cm, dl) ports input only: 8 i/o: 43 pull-up resistors software control: 41 (1) port n register (pn) data i/o with external devices is performed by writing to and reading from the pn regist er. the pn register is configured of a port latch that re tains the output data and a circ uit that reads the pin status. each bit of the pn register corresponds to one pin of port n and can be read or written in 1-bit units. pn7 0 is output 1 is output pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h note (output latch) r/w note input-only port pins are undefined. writing to and reading from the pn register are executed as follows depending on the setting of each register.
chapter 4 port functions user?s manual u17705ej2v0ud 67 table 4-3. reading to/writing from pn register setting of pmcn register setting of pmn register wr iting to pn register reading from pn register output mode (pmnm bit = 0) write to the output latch note . the contents of the output latch are output from the pin. the value of the output latch is read. port mode (pmcnm bit = 0) input mode (pmnm bit = 1) write to the output latch note . the status of the pin is not affected. the pin status is read. output mode (pmnm bit = 0) write to the output latch note . the status of the pin is not affected. the pin operates as an alternate-function pin. ? when alternate function is output the output status of the alternate function is read. ? when alternate function is input the output latch value is read. alternate-function mode (pmcnm bit = 1) input mode (pmnm bit = 1) write to the output latch note . the status of the pin is not affected. the pin operates as an alternate-function pin. the pin status is read. note the value written to the output latch is retained until a new value is written to the output latch. (2) port n mode register (pmn) pmn specifies the input m ode/output mode of the port. each bit of the pmn register corresponds to one pin of port n and can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of i/o mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w
chapter 4 port functions user?s manual u17705ej2v0ud 68 (3) port n mode control register (pmcn) pmcn specifies the port mode/alternate function. each bit of the pmcn register corresponds to one pin of port n and can be specified in 1-bit units. port mode alternate function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w (4) port n function control register (pfcn) pfcn is a register that specifies the alternate function to be us ed when one pin has two or more alternate functions. each bit of the pfcn register corresponds to one pin of port n and can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function
chapter 4 port functions user?s manual u17705ej2v0ud 69 (5) port n function control expansion register (pfcen) pfcen is a register that specifies t he alternate function to be used when one pin has three or more alternate functions. each bit of the pfcen register corresponds to one pin of port n and can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 (6) port n function register (pfn) pfn is a register that specifies normal output/n-ch open-drain output. each bit of the pfn register corresponds to one pin of port n and can be specified in 1-bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 control of normal output/n-ch open-drain output pfn after reset: 00h r/w note the pfnm bit is valid only when the pmn.pmnm bit is 0 (output mode) regardl ess of the setting of the pmcn register. when the pmnm bit is 1 (input mode) , the set value in the pfn register is invalid. example <1> when the value of t he pfn register is valid pfnm bit = 1 ? n-ch open-drain output is specified. pmnm bit = 0 ? output mode is specified. pmcnm bit = 0 or 1 <2> when the value of the pfn register is invalid pfnm bit = 0 ? n-ch open-drain output is specified. pmnm bit = 1 ? input mode is specified. pmcnm bit = 0 or 1
chapter 4 port functions user?s manual u17705ej2v0ud 70 (7) pull-up resistor option register (pun) pun is a register that specifies the c onnection of an on-chip pull-up resistor. each bit of the pun register corresponds to one pin of port n and can be specified in 1-bit units. pun7 pun6 pun5 pun4 pun3 pun2 pun1 pun0 pun after reset: 00h r/w not connected connected punm 0 1 control of on-chip pull-up resistor connection
chapter 4 port functions user?s manual u17705ej2v0ud 71 (8) port settings set the ports as follows. figure 4-1. register settings and pin functions pmcn register output mode input mode pmn register ? 0 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark switch to the alternate functi on using the following procedure. <1> set the pfcn and pfcen registers. <2> set the pmcn register. <3> set the intrn or intfn register (t o specify an external interrupt pin). if the pmcn register is set first, an unintende d function may be set while the pfcn and pfcen registers are being set.
chapter 4 port functions user?s manual u17705ej2v0ud 72 4.3.1 port 0 port 0 is a 7-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port 0 includes the following alternate functions. table 4-4. alternate-function pins of port 0 pin no. pin name alternate function i/o pull note remark block type 12 p00 toh0 output d0-u 13 p01 toh1 output ? d0-u 14 p02 nmi input d1-suil 15 p03 intp0 input d1-suil 16 p04 intp1 input d1-suil 17 p05 intp2 input analog noise elimination d1-suil 18 p06 intp3 input yes analog/digital noise elimination d1-suil note software pull-up function caution p02 to p06 have hysteresis characteristics when the alternate f unction is input, but not in the port mode. (1) port 0 register (p0) 0 0 is output 1 is output p0n 0 1 control of output data (in output mode) (n = 0 to 6) p0 p06 p05 p04 p03 p02 p01 p00 after reset: 00h (output latch) r/w address: fffff400h (2) port 0 mode register (pm0) 1 output mode input mode pm0n 0 1 control of i/o mode (n = 0 to 6) pm0 pm06 pm05 pm04 pm03 pm02 pm01 pm00 after reset: ffh r/w address: fffff420h
chapter 4 port functions user?s manual u17705ej2v0ud 73 (3) port 0 mode control register (pmc0) 0 pmc0 pmc06 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 i/o port intp3 input pmc06 0 1 specification of p06 pin operation mode i/o port intp2 input pmc05 0 1 specification of p05 pin operation mode i/o port intp1 input pmc04 0 1 specification of p04 pin operation mode i/o port intp0 input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode i/o port toh1 output pmc01 0 1 specification of p01 pin operation mode i/o port toh0 output pmc00 0 1 specification of p00 pin operation mode after reset: 00h r/w address: fffff440h (4) pull-up resistor option register 0 (pu0) 0 not connected connected pu0n 0 1 control of on-chip pull-up resistor connection (n = 0 to 6) pu0 pu06 pu05 pu04 pu03 pu02 pu01 pu00 after reset: 00h r/w address: fffffc40h
chapter 4 port functions user?s manual u17705ej2v0ud 74 4.3.2 port 3 port 3 is an 8-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port 3 includes the following alternate functions. table 4-5. alternate-function pins of port 3 pin no. pin name alternate function i/o pull note remark block type 22 p30 txd0 output d-u 23 p31 rxd0/intp7 input d1-suihl 24 p32 asck0/adtrg/to01 i/o e10-sul 25 p33 tip00/top00 i/o gxx10-sul 26 p34 tip01/top01 i/o gxx10-sul 27 p35 ti010/to01 i/o yes ? e10-sul 55 p38 sda0 i/o d2-snfh 56 p39 scl0 i/o no n-ch open-drain output d2-snfh note software pull-up function caution p31 to p35, p38, and p39 have hysteresis characteristics when th e alternate function is input, but not in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 75 (1) port 3 register (p3) 0 is output 1 is output p3n 0 1 control of output data (in output mode) (n = 0 to 5, 8, 9) p3 (p3h note ) after reset: 00h (output latch) r/w address: p3 fffff406h, p3l fffff406h, p3h fffff407h 0 0 p35 p34 p33 p32 p31 p30 0 0 0 0 0 0 p39 p38 8 9 10 11 12 13 14 15 (p3l) note when reading from or writing to bits 8 to 15 of the p3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p3h register. remark the p3 register can be read or written in 16-bit units. however, when the higher 8 bits and the lowe r 8 bits of the p3 register are used as the p3h register and as the p3l register, re spectively, this register can be read or written in 8-bit or 1-bit units. (2) port 3 mode register (pm3) 1 output mode input mode pm3n 0 1 control of i/o mode (n = 0 to 5, 8, 9) 1 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: pm3 fffff426h, pm3l fffff426h, pm3h fffff427h 1 pm3 (pm3h note ) 1 1 1 1 1 pm39 pm38 8 9 10 11 12 13 14 15 (pm3l) note when reading from or writing to bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm3h register. remark the pm3 register can be read or written in 16-bit units. when the higher 8 bits and the lower 8 bits of the pm3 register are used as the pm3h register and as the pm3l register, respective ly, this register can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u17705ej2v0ud 76 (3) port 3 mode control register (pmc3) pmc3 (pmc3h note 1 ) i/o port scl0 i/o pmc39 0 1 specification of p39 pin operation mode i/o port sda0 i/o pmc38 0 1 specification of p38 pin operation mode i/o port ti010 input/to01 output pmc35 0 1 specification of p35 pin operation mode i/o port tip01 input/top01 output pmc34 0 1 specification of p34 pin operation mode i/o port tip00 input/top00 output pmc33 0 1 specification of p33 pin operation mode i/o port asck0 input/adtrg input/to01 output pmc32 0 1 specification of p32 pin operation mode i/o port rxd0 input/intp7 input note 2 pmc31 0 1 specification of p31 pin operation mode i/o port txd0 output pmc30 0 1 specification of p30 pin operation mode after reset: 0000h r/w address: pmc3 fffff446h, pmc3l fffff446h, pmc3h fffff447h 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 (pmc3l) notes 1. when reading from or writing to bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc3h register. 2. the intp7 and rxd0 pins are alternate-f unction pins. when using the pin as the rxd0 pin, disable edge detection of the alternate-function intp7 pin (clear the intf3.intf31 and intr3.intr31 bits to 0). when using the pin as the intp7 pin, stop the uart0 receive operation (clear the asim0.rxe0 bit to 0). remark the pmc3 register can be read or written in 16-bit units. when the higher 8 bits and the lower 8 bi ts of the pmc3 register are used as the pmc3h register and as the pmc3l register, re spectively, this register can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u17705ej2v0ud 77 (4) port 3 function register h (pf3h) 0 when used as normal port (n-ch open-drain output) when used as alternate-function (n-ch open-drain output) pf3n 0 1 specification of normal port/alternate function (n = 8, 9) pf3h 0 0 0 0 0 pf39 pf38 after reset: 00h r/w address: fffffc67h caution when using p38 and p39 as n-ch open-drai n-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p3n bit = 1 pf3n bit = 1 pmc3n bit = 1 (5) port 3 function control register (pfc3) pfc3 after reset: 00h r/w address: fffff466h 0 0 pfc35 pfc34 pfc33 pfc32 0 0 remark for details of specification of alternate-function pins, refer to 4.3.2 (7) specifying alternate-function pins of port 3 . (6) port 3 function contro l expansion register (pfce3) pfce3 after reset: 00h r/w address: fffff706h 0 0 0 pfce34 pfce33 0 0 0 remark for details of specification of alternate-function pins, refer to 4.3.2 (7) specifying alternate-function pins of port 3 .
chapter 4 port functions user?s manual u17705ej2v0ud 78 (7) specifying alternate-function pins of port 3 pfc35 specification of alter nate-function pin of p35 pin 0 ti010 input 1 to01 output pfce34 pfc34 specification of alte rnate-function pin of p34 pin 0 0 setting prohibited 0 1 setting prohibited 1 0 tip01 input 1 1 top01 output pfce33 pfc33 specification of alte rnate-function pin of p33 pin 0 0 setting prohibited 0 1 setting prohibited 1 0 tip00 input 1 1 top00 output pfc32 specification of alter nate-function pin of p32 pin 0 asck0/adtrg note input 1 to01 output note the asck0 and adtrg pins are alternate-function pins . when using the pin as the asck0 pin, disable the trigger input of the alternate-function adtrg pin (clear the ads.trg bit to 0 or set the ads.adtmd bit to 1). when using the pin as the adtrg pin, do not set the uart0 operation clock to external input (set the cksr0.tps03 to cksr0.tps00 bits to other than 1011). caution when the p3n pin is speci fied as an alternate function by the pmc3.pmc3n bit with the pfc3n and pfce3n bits maintaining the initial value (0), output becomes unde fined. therefore, to specify the p3n pin as an alternate function, set the pfc3n and pfce3n bits to 1 first and then set the pmc3n bit to 1 (n = 3, 4).
chapter 4 port functions user?s manual u17705ej2v0ud 79 (8) pull-up resistor option register 3 (pu3) 0 not connected connected pu3n 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) pu3 0 pu35 pu34 pu33 pu32 pu31 pu30 after reset: 00h r/w address: fffffc46h
chapter 4 port functions user?s manual u17705ej2v0ud 80 4.3.3 port 4 port 4 is a 3-bit i/o port for which i/o se ttings can be controll ed in 1-bit units. port 4 includes the following alternate functions. table 4-6. alternate-function pins of port 4 pin no. pin name alternate function i/o pull note remark block type 19 p40 si00 input ? d1-sul 20 p41 so00 output d0-uf 21 p42 sck00 i/o yes n-ch open-drain output can be selected. d2-sufl note software pull-up function caution p40 and p42 have hysteresis characteristics when th e alternate function is input, but not in the port mode. (1) port 4 register (p4) 0 0 is output 1 is output p4n 0 1 control of output data (in output mode) (n = 0 to 2) p4 0 0 0 0 p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h (2) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 control of i/o mode (n = 0 to 2) pm4 1 1 1 1 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h
chapter 4 port functions user?s manual u17705ej2v0ud 81 (3) port 4 mode control register (pmc4) 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 i/o port sck00 i/o pmc42 0 1 specification of p42 pin operation mode i/o port so00 output pmc41 0 1 specification of p41 pin operation mode i/o port si00 input pmc40 0 1 specification of p40 pin operation mode after reset: 00h r/w address: fffff448h (4) port 4 function register (pf4) 0 normal output n-ch open-drain output pf4n 0 1 control of normal output/n-ch open-drain output (n = 1, 2) pf4 0 0 0 0 pf42 pf41 0 after reset: 00h r/w address: fffffc68h caution when using p41 and p42 as n-ch open- drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p4n bit = 1 pf4n bit = 1 pmc4n bit = 1 (5) pull-up resistor option register 4 (pu4) 0 not connected connected pu4n 0 1 control of on-chip pull-up resistor connection (n = 0 to 2) pu4 0 0 0 0 pu42 pu41 pu40 after reset: 00h r/w address: fffffc48h
chapter 4 port functions user?s manual u17705ej2v0ud 82 4.3.4 port 5 port 5 is a 6-bit i/o port for which i/o se ttings can be controll ed in 1-bit units. port 5 includes the following alternate functions. table 4-7. alternate-function pins of port 5 pin no. pin name alternate function i/o pull note remark block type 28 p50 ti011/rtp00/kr0 i/o e10-sult 29 p51 ti50/rtp01/kr1 i/o e10-sult 30 p52 to50/rtp02/kr2 i/o e00-sut 31 p53 rtp03/kr3 i/o ex0-sut 34 p54 rtp04/kr4 i/o ex0-sut 35 p55 rtp05/kr5 i/o yes ? ex0-sut note software pull-up function (1) port 5 register (p5) 0 is output 1 is output p5n 0 1 control of output data (in output mode) (n = 0 to 5) p5 after reset: 00h (output latch) r/w address: fffff40ah 0 0 p55 p54 p53 p52 p51 p50 (2) port 5 mode register (pm5) 1 output mode input mode pm5n 0 1 control of i/o mode (n = 0 to 5) 1 pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah pm5
chapter 4 port functions user?s manual u17705ej2v0ud 83 (3) port 5 mode control register (pmc5) i/o port/kr5 input rtp05 output pmc55 0 1 specification of p55 pin operation mode i/o port/kr4 input rtp04 output pmc54 0 1 specification of p54 pin operation mode 0 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 after reset: 00h r/w address: fffff44ah pmc5 i/o port/kr3 input rtp03 output pmc53 0 1 specification of p53 pin operation mode i/o port/kr2 input to50 output/rtp02 output pmc52 0 1 specification of p52 pin operation mode i/o port/kr1 input ti50 input/rtp01 output pmc51 0 1 specification of p51 pin operation mode i/o port/kr0 input ti011 input/rtp00 output pmc50 0 1 specification of p50 pin operation mode
chapter 4 port functions user?s manual u17705ej2v0ud 84 (4) port 5 function control register (pfc5) caution when the p5n pin is sp ecified as an alternate function by the pmc5.pmc5n bit with the pfc5n bit maintaining the initial value (0), out put becomes undefined. therefore, to specify the p5n pin as alternate function 2, set the pfc5 n bit to 1 first and then set the pmc5n bit to 1 (n = 3 to 5). pfc5 rtp05 output pfc55 1 specification of alternate-function pin of p55 pin rtp03 output pfc53 1 specification of alternate-function pin of p53 pin rtp04 output pfc54 1 specification of alternate-function pin of p54 pin after reset: 00h r/w address: fffff46ah 0 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 to50 output rtp02 output pfc52 0 1 specification of alternate-function pin of p52 pin ti50 input rtp01 output pfc51 0 1 specification of alternate-function pin of p51 pin ti011 input rtp00 output pfc50 0 1 specification of alternate-function pin of p50 pin (5) pull-up resistor option register 5 (pu5) 0 not connected connected pu5n 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) 0 pu55 pu54 pu53 pu52 pu51 pu50 after reset: 00h r/w address: fffffc4ah pu5
chapter 4 port functions user?s manual u17705ej2v0ud 85 4.3.5 port 7 port 7 is an 8-bit input-only port for which all the pins are fixed to input. port 7 includes the following alternate functions. table 4-8. alternate-function pins of port 7 pin no. pin name alternate function i/o pull note remark block type 64 p70 ani0 input a-a 63 p71 ani1 input a-a 62 p72 ani2 input a-a 61 p73 ani3 input a-a 60 p74 ani4 input a-a 59 p75 ani5 input a-a 58 p76 ani6 input a-a 57 p77 ani7 input no ? a-a note software pull-up function (1) port 7 register (p7) input low level input high level p7n 0 1 input data read (n = 0 to 7) after reset: undefined r address: fffff40eh p77 p76 p75 p74 p73 p72 p71 p70 p7
chapter 4 port functions user?s manual u17705ej2v0ud 86 4.3.6 port 9 port 9 is a 9-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port 9 includes the following alternate functions. table 4-9. alternate-function pins of port 9 pin no. pin name alternate function i/o pull note remark block type 36 p90 txd1/kr6 i/o ex0-sut 37 p91 rxd1/kr7 input ex1-suht 38 p96 ti51/to51 i/o ex0-sut 39 p97 si01 input ? ex1-sul 40 p98 so01 output ex0-uf 41 p99 sck01 i/o n-ch open-drain output can be specified. ex2-sufl 42 p913 intp4 input ex1-suilz 43 p914 intp5 input ex1-suilz 44 p915 intp6 input yes analog noise elimination ex1-suilz note software pull-up function caution p97, p99, and p913 to p915 have hysteresis characteristics when the alternate function is input, but not in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 87 (1) port 9 register (p9) 0 is output 1 is output p9n 0 1 control of output data (in output mode) (n = 0, 1, 6 to 9, 13 to 15) after reset: 00h (output latch) r/w address: p9 fffff412h, p9l fffff412h, p9h fffff413h p915 p9 (p9h note ) p914 p913 0 0 0 p99 p98 p97 p96 0 0 0 0 p91 p90 8 9 10 11 12 13 14 15 (p9l) note when reading from or writing to bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p9h register. remark the p9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lower 8 bits of the p9 register are used as the p9h register and as the p9l register, re spectively, these registers can be read or written in 8-bit or 1-bit units. (2) port 9 mode register (pm9) pm97 output mode input mode pm9n 0 1 control of i/o mode (n = 0, 1, 6 to 9, 13 to 15) pm96 1 1 1 1 pm91 pm90 after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h pm915 pm9 (pm9h note ) pm914 pm913 1 1 1 pm99 pm98 8 9 10 11 12 13 14 15 (pm9l) note when reading from or writing to bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm9h register. remark the pm9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pm9 register are used as the pm9h register and as the pm9l register, re spectively, this register can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u17705ej2v0ud 88 (3) port 9 mode control register (pmc9) i/o port intp6 input pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 0 0 0 0 pmc91 pmc90 after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pmc915 pmc9 (pmc9h note ) pmc914 pmc913 0 0 0 pmc99 pmc98 8 9 10 11 12 13 14 15 i/o port intp5 input pmc914 0 1 specification of p914 pin operation mode i/o port sck01 i/o pmc99 0 1 specification of p99 pin operation mode i/o port intp4 input pmc913 0 1 specification of p913 pin operation mode i/o port so01 output pmc98 0 1 specification of p98 pin operation mode (pmc9l) i/o port si01 input pmc97 0 1 specification of p97 pin operation mode i/o port/ti51 input to51 output pmc96 0 1 specification of p96 pin operation mode i/o port/kr7 input rxd1 input pmc91 0 1 specification of p91 pin operation mode i/o port/kr6 input txd1 output pmc90 0 1 specification of p90 pin operation mode note when reading from or writing to bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc9h register. remark the pmc9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pmc9 register are used as the pmc9h register and as the pmc9l r egister, respectively, these registers can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u17705ej2v0ud 89 (4) port 9 function register h (pf9h) 0 normal output n-ch open-drain output pf9n 0 1 control of normal output/n-ch open-drain output (n = 8, 9) pf9h 0 0 0 0 0 pf99 pf98 after reset: 00h r/w address: fffffc73h caution when using p98 and p99 as n-ch open-drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 be fore setting the pin to n-ch open-drain output. p9n bit = 1 pfc9n bit = 0/1 pf9n bit = 1 pmc9n bit = 1
chapter 4 port functions user?s manual u17705ej2v0ud 90 (5) port 9 function control register (pfc9) caution when port 9 is sp ecified as an alternate function by the pmc9.pmc9n bit with the pfc9n bit maintaining the initial value (0), output becom es undefined. therefore, to specify port 9 as alternate function 2, set the pfc9 n bit to 1 first and then set the pmc9n bit to 1 (n = 0, 1, 6 to 9, 13 to 15). pfc9 (pfc9h note ) intp6 input pfc915 1 specification of alternate-function pin of p915 pin intp5 input pfc914 1 specification of alternate-function pin of p914 pin intp4 input pfc913 1 specification of alternate-function pin of p913 pin after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc97 pfc96 0 0 0 0 pfc91 pfc90 pfc915 pfc914 pfc913 0 0 0 pfc99 pfc98 8 9 10 11 12 13 14 15 sck01 i/o pfc99 1 specification of alternate-function pin of p99 pin so01 output pfc98 1 specification of alternate-function pin of p98 pin (pfc9l) si01 input pfc97 1 specification of alternate-function pin of p97 pin to51 output pfc96 1 specification of alternate-function pin of p96 pin rxd1 input pfc91 1 specification of alternate-function pin of p91 pin txd1 output pfc90 1 specification of alternate-function pin of p90 pin note when reading from or writing to bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc9h register. remark the pfc9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pfc9 register are used as the pfc9h register and as t he pfc9l register, respective ly, these registers can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u17705ej2v0ud 91 (6) pull-up resistor option register 9 (pu9) not connected connected pu9n 0 1 control of on-chip pull-up resistor connection (n = 0, 1, 6 to 9, 13 to 15) pu9 (pu9h note ) after reset: 0000h r/w address: pu9 fffffc52h, pu9l fffffc52h, pu9h fffffc53h pu97 pu96 0 0 0 0 pu91 pu90 pu915 pu914 pu913 0 0 0 pu99 pu98 8 9 10 11 12 13 14 15 (pu9l) note when reading from or writing to bits 8 to 15 of the pu9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pu9h register. remark the pu9 register can be read or written in 16-bit units. however, when the higher 8 bits and the lo wer 8 bits of the pu9 register are used as the pu9h register and as the pu9l register, respectively, these registers can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u17705ej2v0ud 92 4.3.7 port cm port cm is a 2-bit i/o port for which i/o se ttings can be controlled in 1-bit units. port cm includes the following alternate functions. table 4-10. alternate-function pins of port cm pin no. pin name alternate function i/o pull note remark block type 45 pcm0 ? ? c-u 46 pcm1 clkout output yes ? d0-u note software pull-up function (1) port cm register (pcm) 0 is output 1 is output pcmn 0 1 control of output data (in output mode) (n = 0, 1) after reset: 00h (output latch) r/w address: fffff00ch 0 pcm 0 0 0 0 0 pcm1 pcm0 (2) port cm mode register (pmcm) output mode input mode pmcmn 0 1 control of i/o mode (n = 0, 1) after reset: ffh r/w address: fffff02ch 1 pmcm 1 1 1 1 1 pmcm1 pmcm0 (3) port cm mode control register (pmccm) 0 pmccm 0 0 0 0 0 pmccm1 0 i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode after reset: 00h r/w address: fffff04ch
chapter 4 port functions user?s manual u17705ej2v0ud 93 (4) pull-up resistor option register cm (pucm) not connected connected pucmn 0 1 control of on-chip pull-up resistor connection (n = 0, 1) after reset: 00h r/w address: ffffff4ch 0 pucm 0 0 0 0 0 pucm1 pucm0
chapter 4 port functions user?s manual u17705ej2v0ud 94 4.3.8 port dl port dl is an 8-bit i/o port for which i/o setti ngs can be controlled in 1-bit units. port dl includes the following alternate functions. table 4-11. alternate-function pins of port dl pin no. pin name alternate function i/o pull note remark block type 47 pdl0 ? ? c-u 48 pdl1 ? ? c-u 49 pdl2 ? ? c-u 50 pdl3 ? ? c-u 51 pdl4 ? ? c-u 52 pdl5 ? ? c-u 53 pdl6 ? ? c-u 54 pdl7 ? ? yes ? c-u note software pull-up function
chapter 4 port functions user?s manual u17705ej2v0ud 95 (1) port dl register (pdl) 0 is output 1 is output pdln 0 1 control of output data (in output mode) (n = 0 to 7) after reset: 00h (output latch) r/w address: fffff004h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 pdl (2) port dl mode register (pmdl) pmdl7 output mode input mode pmdln 0 1 control of i/o mode (n = 0 to 7) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffh r/w address: fffff024h pmdl (3) pull-up resistor option register dl (pudl) not connected connected pudln 0 1 control of on-chip pull-up resistor connection (n = 0 to 7) pudl7 pudl6 pudl5 pudl4 pudl3 pudl2 pudl1 pudl0 after reset: 00h r/w address: ffffff44h pudl
chapter 4 port functions user?s manual u17705ej2v0ud 96 4.4 block diagrams figure 4-2. block diagram of type a-a internal bus rd a/d input signal pmn p-ch n-ch figure 4-3. block diagram of type c-u wr pm rd wr port pmn pmmn wr pu ev dd pumn p-ch address output latch (pmn) internal bus selector selector
chapter 4 port functions user?s manual u17705ej2v0ud 97 figure 4-4. block diagram of type d0-u wr pmc rd address output signal of alternate function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch output latch (pmn) internal bus selector selector selector
chapter 4 port functions user?s manual u17705ej2v0ud 98 figure 4-5. block diagram of type d0-uf wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch address output latch (pmn) internal bus selector selector selector output signal of alternate function 1
chapter 4 port functions user?s manual u17705ej2v0ud 99 figure 4-6. block diagram of type d1-suil wr pmc rd address input signal of alternate function 1 wr port pmn note 2 pmcmn wr intf intfmn note 1 wr pu pumn wr pm pmmn noise elimination edge detection wr intr intrmn note 1 ev dd p-ch output latch (pmn) internal bus selector selector notes 1. refer to 17.4 external interrupt request input pins (nmi, intp0 to intp7) . 2. there are no hysteresis characteristics in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 100 figure 4-7. block diagram of type d1-suihl wr pmc rd address wr port pmn pmcmn wr pu pumn wr pm pmmn wr intf intfmn note 1 wr intr intrmn note 1 ev dd p-ch input signal of alternate function 1-2 input signal of alternate function 1-1 noise elimination edge detection output latch (pmn) note 2 internal bus selector selector notes 1. refer to 17.4 external interrupt request input pins (nmi, intp0 to intp7) . 2. there are no hysteresis characteristics in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 101 figure 4-8. block diagram of type d1-sul wr pmc rd wr port address pmn pmcmn wr pu pumn wr pm pmmn ev dd p-ch note output latch (pmn) internal bus selector selector input signal of alternate function 1 note there are no hysteresis characteristics in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 102 figure 4-9. block diagram of type d2-snfh wr pmc rd address output signal of alternate function 1 input signal of alternate function 1 wr port pmcmn wr pf pfmn wr pm pmmn pmn ev ss note n-ch output latch (pmn) internal bus selector selector selector note there are no hysteresis characteristics in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 103 figure 4-10. block diagram of type d2-sufl wr pmc rd note wr port pmn pmcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch address output latch (pmn) internal bus selector selector selector input signal of alternate function 1 output signal of alternate function 1 output enable signal of alternate function 1 note there are no hysteresis characteristics in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 104 figure 4-11. block diagram of type e00-sut wr pmc rd address alternate-function input signal in port mode output signal of alternate function 2 output signal of alternate function 1 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector selector
chapter 4 port functions user?s manual u17705ej2v0ud 105 figure 4-12. block diagram of type e10-sul wr pmc rd address input signal of alternate function 1 output signal of alternate function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector note note there are no hysteresis characteristics in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 106 figure 4-13. block diagram of type e10-sult wr pmc rd address alternate-function input signal in port mode input signal of alternate function 1 output signal of alternate function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector
chapter 4 port functions user?s manual u17705ej2v0ud 107 figure 4-14. block diagram of type ex0-sut wr pmc rd address alternate-function input signal in port mode output signal of alternate function 2 wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) internal bus selector selector selector
chapter 4 port functions user?s manual u17705ej2v0ud 108 figure 4-15. block diag ram of type ex0-uf wr pmc rd address output signal of alternate function 2 wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) internal bus selector selector selector
chapter 4 port functions user?s manual u17705ej2v0ud 109 figure 4-16. block diag ram of type ex1-suht wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) address input signal of alternate function 2 alternate-function input signal in port mode internal bus selector selector
chapter 4 port functions user?s manual u17705ej2v0ud 110 figure 4-17. block diag ram of type ex1-suil wr pmc rd wr port pmn pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr intf intfmn note 1 wr intr intrmn note 1 ev dd p-ch output latch (pmn) note 2 address input signal of alternate function 2 noise elimination edge detection internal bus selector selector notes 1. refer to 17.4 external interrupt request input pins (nmi, intp0 to intp7) . 2. there are no hysteresis characteristics in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 111 figure 4-18. block diagram of type ex1-sul wr pmc rd wr port pmn pmcmn wr pu pumn wr pm pmmn wr pfc pfcmn ev dd p-ch output latch (pmn) address input signal of alternate function 2 internal bus selector selector
chapter 4 port functions user?s manual u17705ej2v0ud 112 figure 4-19. block diagram of type ex2-sufl wr pmc rd address input signal of alternate function 2 output signal of alternate function 2 wr port pmn note pmcmn wr pfc pfcmn wr pu pumn wr pm pmmn wr pf pfmn ev dd p-ch ev dd ev ss p-ch n-ch output latch (pmn) output enable signal of alternate function 2 internal bus selector selector selector note there are no hysteresis characteristics in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 113 figure 4-20. block diagram of type gxx10-sul p-ch wr pmc rd wr port pmn note pmcmn wr pfce pfcemn wr pm pmmn wr pfc pfcmn wr pu pumn ev dd address input signal of alternate function 3 output signal of alternate function 4 output latch (pmn) internal bus selector selector selector note there are no hysteresis characteristics in the port mode.
chapter 4 port functions user?s manual u17705ej2v0ud 114 4.5 port register setting when alternate function is used table 4-12 shows the port register settings when each port is used for an alternate function. when using a port pin as an alternate-functi on pin, refer to description of each pin.
chapter 4 port functions user?s manual u17705ej2v0ud 115 other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pfcnx bit of pfcn register ? ? ? pfc03 = 0 ? ? ? pfc30 = 0 note 1 , pfc31 = 0 note 1 , pfc31 = 0 note 2 , pfc32 = 0 note 2 , pfc32 = 0 pfc32 = 1 pfc33 = 0 pfc33 = 1 pfc34 = 0 pfc34 = 1 pfc35 = 0 pfc35 = 1 pfcenx bit of pfcen register ? ? ? ? ? ? ? ? ? ? ? ? ? pfce33 = 1 pfce33 = 1 pfce34 = 1 pfce34 = 1 ? ? pmcnx bit of pmcn register pmc00 = 1 pmc01 = 1 pmc02 = 1 pmc03 = 1 pmc04 = 1 pmc05 = 1 pmc06 = 1 pmc30 = 1 pmc31 = 1 pmc31 = 1 pmc32 = 1 pmc32 = 1 pmc32 = 1 pmc33 = 1 pmc33 = 1 pmc34 = 1 pmc34 = 1 pmc35 = 1 pmc35 = 1 pmnx bit of pmn register pm00 = setting not required pm01 = setting not required pm02 = setting not required pm03 = setting not required pm04 = setting not required pm05 = setting not required pm06 = setting not required pm30 = setting not required pm31 = setting not required pm31 = setting not required pm32 = setting not required pm32 = setting not required pm32 = setting not required pm33 = setting not required pm33 = setting not required pm34 = setting not required pm34 = setting not required pm35 = setting not required pm35 = setting not required pnx bit of pn register p00 = setting not required p01 = setting not required p02 = setting not required p03 = setting not required p04 = setting not required p05 = setting not required p06 = setting not required p30 = setting not required p31 = setting not required p31 = setting not required p32 = setting not required p32 = setting not required p32 = setting not required p33 = setting not required p33 = setting not required p34 = setting not required p34 = setting not required p35 = setting not required p35 = setting not required i/o output output input input input input input output input input input input output input output input output input output alternate function function name toh0 toh1 nmi intp0 intp1 intp2 intp3 txd0 rxd0 intp7 asck0 adtrg to01 tip00 top00 tip10 top10 ti010 to01 table 4-12. settings when port pins are used for alternate functions (1/3) pin name p00 p01 p02 p03 p04 p05 p06 p30 p31 p32 p33 p34 p35 notes 1. the intp7 and rxd0 pins are alternate-func tion pins. when using the pin as the rxd0 pin, disable edge detection of the altern ate-function intp7 pin (clear the intf3.intf31 and intr3.intr31 bits to 0). when using the pin as the intp7 pin, stop the uart 0 receive operation (clear the asim0.rxe0 bit to 0). 2. the asck0 and adtrg pins are alternate-function pins. when usi ng the pin as the asck0 pin, dis able the trigger input of the a lternate-function adtrg pin (clear the ads.trg bit to 0 or set the ad s.adtmd bit to 1). when using the pin as the adtrg pin, do not set the uart0 operatio n clock to external input (set the cksr0.tps03 to cksr0. tps00 bits to other than 1011).
chapter 4 port functions user?s manual u17705ej2v0ud 116 table 4-12. settings when port pins are used for alternate functions (2/3) other bits (registers) ? ? ? ? ? krm0 (krm) = 1 ? ? krm1 (krm) = 1 ? ? krm2 (krm) = 1 ? krm3 (krm) = 1 krm4 (krm) = 1 krm5 (krm) = 1 pfcnx bit of pfcn register pfc50 = 0 pfc50 = 1 pfc50 = setting not required pfc51 = 0 pfc51 = 1 pfc51 = setting not required pfc52 = 0 pfc52 = 1 pfc52 = setting not required pfc53 = 1 pfc53 = setting not required pfc54 = 1 pfc54 = setting not required pfc55 = 1 pfc55 = setting not required pmcnx bit of pmcn register pmc50 = 1 pmc50 = 1 pmc50 = 0 pmc51 = 1 pmc51 = 1 pmc51 = 0 pmc52 = 1 pmc52 = 1 pmc52 = 0 pmc53 = 1 pmc53 = 0 pmc54 = 1 pmc54 = 0 pmc55 = 1 pmc55 = 0 pmnx bit of pmn register pm50 = setting not required pm50 = setting not required pm50 = 1 pm51 = setting not required pm51 = setting not required pm51 = 1 pm52 = setting not required pm52 = setting not required pm52 = 1 pm53 = setting not required pm53 = 1 pm54 = setting not required pm54 = 1 pm55 = setting not required pm55 = 1 pnx bit of pn register p50 = setting not required p50 = setting not required p50 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p53 = setting not required p53 = setting not required p54 = setting not required p54 = setting not required p55 = setting not required p55 = setting not required i/o input output input input output input output output input output input output input output input alternate function function name ti011 rtp00 kr0 ti50 rtp01 kr1 to50 rtp02 kr2 rtp03 kr3 rtp04 kr4 rtp05 kr5 pin name p50 p51 p52 p53 p54 p55 ? pmc38 = 1 pmc39 = 1 pmc42 = 1 pm38 = setting not required pm39 = setting not required pm42 = setting not required p38 = setting not required p39 = setting not required p42 = setting not required i/o i/o i/o sda0 scl0 sck00 p38 p39 pmc40 = 1 pmc41 = 1 pm40 = setting not required pm41 = setting not required p40 = setting not required p41 = setting not required input output si00 so00 p40 p41 p42 pf41 (pf4) = don ? t care pf42 (pf4) = don ? t care pf38 (pf3h) = 1 pf39 (pf3h) = 1 ? ?
chapter 4 port functions user?s manual u17705ej2v0ud 117 table 4-12. settings when port pins are used for alternate functions (3/3) krm6 (krm) = 1 krm7 (krm) = 1 pf98 (pf9) = don?t care pf99 (pf9) = don?t care pfc90 = 1 pfc90 = setting not required pfc91 = 1 pfc91 = setting not required pfc96 = setting not required pfc96 = 1 pfc97 = 1 pfc98 = 1 pfc99 = 1 pmc90 = 1 pmc90 = 0 pmc91 = 1 pmc91 = 0 pmc96 = 0 pmc96 = 1 pmc97 = 1 pmc98 = 1 pmc99 = 1 pm90 = setting not required pm90 = 1 pm91 = setting not required pm91 = 1 pm96 = 1 pm96 = setting not required pm97 = setting not required pm98 = setting not required pm99 = setting not required p90 = setting not required p90 = setting not required p91 = setting not required p91 = setting not required p96 = setting not required p96 = setting not required p97 = setting not required p98 = setting not required p99 = setting not required i/o output input input input input output input output i/o alternate function function name txd1 kr6 rxd1 kr7 ti51 to51 si01 so01 sck01 pin name p90 p91 p96 p97 p98 p99 pfc913 = 1 pmc913 = 1 pm913 = setting not required p913 = setting not required input intp4 p913 pfc914 = 1 pmc914 = 1 pm914 = setting not required p914 = setting not required input intp5 p914 pfc915 = 1 pmc915 = 1 pm915 = setting not required p915 = setting not required input intp6 p915 pmccm1 = 1 pmcm1 = setting not required pcm1 = setting not required output clkout pcm1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p70 = setting not required p71 = setting not required p72 = setting not required p73 = setting not required p74 = setting not required p75 = setting not required p76 = setting not required p77 = setting not required input input input input input input input input ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 p70 p71 p72 p73 p74 p75 p76 p77 other bits (registers) pfcnx bit of pfcn register pmcnx bit of pmcn register pmnx bit of pmn register pnx bit of pn register
chapter 4 port functions user?s manual u17705ej2v0ud 118 4.6 cautions 4.6.1 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. when pdl0 is an output port, pdl1 to pdl7 are input ports (all pin statuses are high level), and the value of the port latch is 00h, if the output of output port pdl0 is changed from low level to high level via a bit manipulation instruction, the value of the port latch is ffh. explanation: the targets of writ ing to and reading from the pn regi ster of a port whose pmnm bit is 1 are the output latch and pin status, respectively. a bit manipulation instruction is executed in the following order in the v850es/ke2. <1> the pn register is read in 8-bit units. <2> the targeted one bit is manipulated. <3> the pn register is written in 8-bit units. in step <1>, the value of the out put latch (0) of pdl0, which is an output port, is read, while the pin statuses of pdl1 to pdl7, which ar e input ports, are read. if the pin statuses of pdl1 to pdl7 are high level at this time, the read value is feh. the value is changed to ffh by the manipulation in <2>. ffh is written to the output la tch by the manipulation in <3>. figure 4-21. bit manipula tion instruction (pdl0) low-level output bit manipulation instruction (set1 0, pdl[r0]) is executed for pdl0 bit. pin status: high level pdl0 pdl1 to pdl7 port dl latch 00000000 low-level output pin status: high level pdl0 pdl1 to pdl7 port dl latch 11111111 bit manipulation instruction for pdl0 bit <1> the pdl register is read in 8-bit units. ? in the case of pdl0, an output port, the value of the port latch (0) is read. ? in the case of pdl1 to pdl7, input ports, the pin status (1) is read. <2> set pdl0 bit to 1. <3> write the results of <2> to the output latch of the pdl register in 8-bit units.
chapter 4 port functions user?s manual u17705ej2v0ud 119 4.6.2 hysteresis characteristics in port mode, the following ports do not have hysteresis characteristics. p02 to p06 p31 to p35, p38, p39 p40, p42 p97, p99, p913 to p915
user?s manual u17705ej2v0ud 120 chapter 5 clock generation function 5.1 overview the following clock generation functions are available. { main clock oscillator ? f x = 2 to 5 mhz (f xx = 8 to 20 mhz: 4.5 v v dd 5.5 v) ? f x = 2 to 4 mhz (f xx = 8 to 16 mhz: 4.0 v v dd 5.5 v) ? f x = 2 to 2.5 mhz (f xx = 8 to 10 mhz: 2.7 v v dd 5.5 v) ? f x = 2 to 10 mhz (f xx = 2 to 10 mhz: 2.7 v v dd 5.5 v) { subclock oscillator ? f xt = 32.768 khz { multiplication ( 4) function by pll (phase locked loop) ? clock-through mode/pll mode selectable ? usable voltage: v dd = 2.7 to 5.5 v { internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) { peripheral clock generation { clock output function remark f x : main clock oscillation frequency f xx : main clock frequency f xt : subclock frequency
chapter 5 clock generation function user?s manual u17705ej2v0ud 121 5.2 configuration figure 5-1. clock generator frc bit mck bit ck2 to ck0 bits selpll bit pllon bit cls bit, ck3 bit stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock watch timer clock watch timer clock, watchdog timer clock peripheral clock, watchdog timer 2 clock watchdog timer 1 clock internal system clock interval timer brg main clock oscillator main clock oscillator stop control xt1 xt2 clkout x1 x2 idle mode idle control idle mode selector pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1024 f brg = f x /2 to f x /2 12 f xt f xt f xx f x f xw idle control idle mode selector selector mfrc bit remark f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f brg : watch timer clock frequency f xw : watchdog timer 1 clock frequency
chapter 5 clock generation function user?s manual u17705ej2v0ud 122 (1) main clock oscillator the main clock oscillator oscillates the following frequencies (f x ): ? f x = 2 to 5 mhz (v dd = 4.5 to 5.5 v, in pll mode) ? f x = 2 to 4 mhz (v dd = 4.0 to 5.5 v, in pll mode) ? f x = 2 to 2.5 mhz (v dd = 2.7 to 5.5 v, in pll mode) ? f x = 2 to 10 mhz (v dd = 2.7 to 5.5 v, in clock through mode) (2) subclock oscillator the subclock oscillator oscillat es a frequency of 32.768 khz (f xt ). (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscill ator is stopped in the st op mode or when the pcc.mck bit = 1 (valid only when the pcc.cls bit = 1). (4) prescaler 1 this prescaler generates the clock (f xx to f xx /1024) to be supplied to the following on-chip peripheral functions: tmp0, tm01, tm50, tm51, tmh0, tmh1, csi00, csi01, uart0, uart1, i 2 c0, adc, and wdt2 (5) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, rom, and ram blocks, and can be output from the clkout pin. (6) interval timer brg this circuit divides the clock (f x ) generated by the main clock oscillator to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. for details, refer to chapter 10 interval timer, watch timer . (7) pll this circuit multiplies the clock (f x ) generated by the main clock oscillator. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be sele cted by using the pllctl.selpll bit. operation of the pll c an be started or stopped by the pllctl.pllon bit.
chapter 5 clock generation function user?s manual u17705ej2v0ud 123 5.3 registers (1) processor clock control register (pcc) the pcc register is a special register. data can be wr itten to this register only in combination of specific sequences (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 03h. (1/2) frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 control of main clock oscillator used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w after reset: fffff828h main clock operation subclock operation cls note 0 1 status of cpu clock (f cpu ) even if the mck bit is set to 1 while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. when the main clock is stopped and the device is operating on the subclock, clear the mck bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. ? ? < > < > < > note the cls bit is a read-only bit.
chapter 5 clock generation function user?s manual u17705ej2v0ud 124 (2/2) f xx f xx /2 f xx /4 f xx /8 (default value) f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 cautions 1. do not change the cpu clock (by using the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation instruction to ma nipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. 3. when the cpu operates on the subclock and no clock is input to the x1 pin, do not access a register in which a wait occurs (ref er to 3.4.8 (2) acces s to special on-chip peripheral i/o register for details of the access methods). if a wait occurs, it can only be released by a reset. remark : don?t care
chapter 5 clock generation function user?s manual u17705ej2v0ud 125 (a) example of setting main clock operation subclock operation <1> ck3 bit 1: use of a bit manipulation instructi on is recommended. do not change the ck2 to ck0 bits. <2> subclock operation: read the cls bit to check if subclock operation has started. it takes the following time after the ck3 bit is se t until subclock operation is started. max.: 1/f xt (1/subclock frequency) <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. cautions 1. when stopping th e main clock, stop the pll. 2. if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied, then change to the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 remark internal system clock (f clk ): clock generated from the main clock (f xx ) by setting bits ck2 to ck0 [description example] <1> _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit 1 <2> _check_cls : tst1 4, pcc[r0] -- wait until subclock operation starts. bz _check_cls <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit 1, main clock is stopped remark the above description is an exampl e. note with caution that t he cls bit is read in a closed loop in <2>.
chapter 5 clock generation function user?s manual u17705ej2v0ud 126 (b) example of setting subclock operation main clock operation <1> mck bit 0: main clock starts oscillating <2> insert waits by the program and wait until the oscillation stabilizat ion time of the main clock elapses. <3> ck3 bit 0: use of a bit manipulation instruct ion is recommended. do not change the ck2 to ck0 bits. <4> main clock operation: it takes the following time after the ck3 bit is set until main clock operation is started. max.: 1/f xt (1/subclock frequency) therefore, insert one nop instructi on immediately after setting the ck3 bit to 0 or read the cls bit to check if main clock operation has started. [description example] <1> _start_main_osc : st.b r0, prcmd[r0] -- release of protection of special registers clr1 6, pcc[r0] -- main clock starts oscillating <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time _wait_ost : nop nop nop addi -1, r11, r11 mp r0, r11 bne _program_wait <3> st.b r0, prcmd[r0] clr1 3, pcc[r0] -- ck3 0 <4> _check_cls : tst1 4, pcc[r0] -- wait until main clock operation starts bnz _check_cls remark the above description is an exampl e. note with caution that t he cls bit is read in a closed loop in <4>.
chapter 5 clock generation function user?s manual u17705ej2v0ud 127 5.4 operation 5.4.1 operation of each clock the following table shows the oper ation status of each clock. table 5-1. operation status of each clock pcc register cls bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 register setting and operation status target clock during reset during oscillation stabilization time count halt mode idle mode stop mode subclock mode sub-idle mode subclock mode sub-idle mode main clock oscillator (f x ) { { { { { subclock oscillator (f xt ) { { { { { { { { { cpu clock (f cpu ) { { internal system clock (f clk ) { { { peripheral clock (f xx to f xx /1024) { { wt clock (main) { { { { { wt clock (sub) { { { { { { { { { wdt1 clock (f xw ) { { { { { wdt2 clock (main) { { wdt2 clock (sub) { { { { { { { { { remark o: operable : stopped 5.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the pcc.ck3 to pcc.ck0 bits. the clkout pin functions alte rnately as the pcm1 pin and functions as a clock output pin if so specified by the control register of port cm. the status of the clko ut pin is the same as the in ternal system clock in table 5-1 and the pin can output the clock when it is in the operable status. it outputs a low level in the stopped status. however, the port mode (pcm1: input mode) is selected until the clkout pin output is set after reset. cons equently, the clkout pin goes into a high-impedance state. 5.4.3 external clock input function an external clock can be direct ly input to the oscillator. input the clock to the x1 pin and its inverse signal to the x2 pin. set the pcc.mfrc bit to 1 (on-chip feedback resistor not used). note, however, that oscillation stabilization time is inserted even in the external clock mode.
chapter 5 clock generation function user?s manual u17705ej2v0ud 128 5.5 pll function 5.5.1 overview the pll function is used to output t he operating clock of the cpu and on-chip peripheral function at a frequency 4 times higher than the oscillation frequen cy, and select the clock-through mode. when pll function is used: input clock = 2 to 5 mhz (f xx : 8 to 20 mhz) clock-through mode: input clock = 2 to 10 mhz (f xx : 2 to 10 mhz) 5.5.2 register (1) pll control register (pllctl) the pllctl register is an 8-bit register that controls the security function of pll and rto. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. 0 pllctl 0 0 0 0 rtost0 note selpll pllon pll stopped pll operating pllon 0 1 pll operation control clock-through operation pll operation selpll 0 1 pll clock selection after reset: 01h r/w address: fffff806h < > < > < > note for the rtost0 bit, refer to chapter 12 real-time output function (rto) . caution be sure to clear bits 3 to 7 to ?0?. changing bit 3 does not affect the operation.
chapter 5 clock generation function user?s manual u17705ej2v0ud 129 5.5.3 usage (1) when pll is used ? after reset has been released, the pll operates (pll ctl.pllon bit = 1), but because the default mode is the clock-through mode (pllctl.selpll bit = 0), select the pll mode (selpll bit = 1). ? to set the stop mode in which the main clock is stoppe d, or to set the idle mode, first select the clock- through mode and then stop the pll. to return from the idle or stop mode, first enable pll operation (pllon bit = 1), and then select the pll mode (selpll bit = 1). ? to enable the pll operation, first se t the pllon bit to 1, wait for 200 s, and then set the selpll bit to 1. to stop the pll, first select the clock-through mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0). (2) when pll is not used ? the clock-through mode (selpll bit = 0) is select ed after reset has been released, but the pll is operating (pllon bit = 1) and must t herefore be stopped (pllon bit = 0). remark the pll is operable in the idle mode. to realiz e low power consumption, stop the pll. be sure to stop the pll when shifting to the stop mode.
user?s manual u17705ej2v0ud 130 chapter 6 16-bit timer/event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. 6.1 overview an outline of tmp0 is shown below. ? clock selection: 8 ways ? capture trigger input pins: 2 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? timer output pins: 2 6.2 functions tmp0 has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 131 6.3 configuration tmp0 includes the following hardware. table 6-1. configuration of tmp0 item configuration timer register 16-bit counter registers tmp0 capture/compare registers 0, 1 (tp0ccr0, tp0ccr1) tmp0 counter read buffer register (tp0cnt) ccr0, ccr1 buffer registers timer inputs 2 (tip00 note , tip01 pins) timer outputs 2 (top00, top01 pins) control registers tmp0 control registers 0, 1 (tp0ctl0, tp0ctl1) tmp0 i/o control registers 0 to 2 (tp0ioc0 to tp0ioc2) tmp0 option register 0 (tp0opt0) note the tip00 pin functions alternat ely as a capture trigger input signal, external event count input signal, and external trigger input signal. figure 6-1. block diagram of tmp0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 selector internal bus internal bus top00 top01 tip00 tip01 selector ccr0 buffer register ccr1 buffer register tp0ccr0 tp0ccr1 16-bit counter tp0cnt inttp0ov inttp0cc0 inttp0cc1 output controller clear edge detector edge detector digital noise eliminator remark f xx : main clock frequency
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 132 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tp0cnt register. when the tp0ctl0.tp0ce bit = 0, the va lue of the 16-bit counter is ffffh. if the tp0cnt register is read at this time, 0000h is read. reset sets the tp0ce bit to 0. therefor e, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tp0ccr0 register is used as a compare regist er, the value written to the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttp0cc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tp0ccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tp0ccr1 register is used as a compare regist er, the value written to the tp0ccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttp0cc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tp0ccr1 register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the tip00 and tip01 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tp0ioc1 and tp0ioc2 registers. (5) output controller this circuit controls the output of the top00 and top0 1 pins. the output contro ller is controlled by the tp0ioc0 register. (6) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock. (7) digital noise eliminator this circuit is valid only when the tip0a pi n is used as a capture trigger input pin. this circuit is controlled by the tip0a noise elimination register (panfc). remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 133 6.4 registers (1) tmp0 control re gister 0 (tp0ctl0) the tp0ctl0 register is an 8-bit register that controls the operation of tmp0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tp0ctl0 register by software. tp0ce tmp0 operation disabled (tmp0 reset asynchronously note ). tmp0 operation enabled. tmp0 operation started. tp0ce 0 1 tmp0 operation control tp0ctl0 0 0 0 0 tp0cks2 tp0cks1 tp0cks0 654321 after reset: 00h r/w address: fffff5a0h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tp0cks2 0 0 0 0 1 1 1 1 internal count clock selection tp0cks1 0 0 1 1 0 0 1 1 tp0cks0 0 1 0 1 0 1 0 1 note tp0opt0.tp0ovf bit, 16-bit counter , timer output (top00, top01 pins) cautions 1. set the tp0cks2 to tp0 cks0 bits when the tp0ce bit = 0. when the value of the tp0ce bi t is changed from 0 to 1, the tp0cks2 to tp0cks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 134 (2) tmp0 control re gister 1 (tp0ctl1) the tp0ctl1 register is an 8-bit register that controls the operation of tmp0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tp0est 0 1 software trigger control tp0ctl1 tp0est tp0eee 0 0 tp0md2 tp0md1 tp0md0 <6> <5> 4 3 2 1 after reset: 00h r/w address: fffff5a1h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tp0est bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tp0est bit as the trigger. disable operation with external event count input. (perform counting with the count clock selected by the tp0ctl0.tp0ck0 to tp0ctl0.tp0ck2 bits.) tp0eee 0 1 count clock selection the tp0eee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tp0md2 0 0 0 0 1 1 1 1 timer mode selection tp0md1 0 0 1 1 0 0 1 1 tp0md0 0 1 0 1 0 1 0 1 enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) ? cautions 1. the tp0est bit is valid only in the external trigger pulse output mode or one-shot pulse output mode . in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tp0eee bit. 3. set the tp0eee and tp0md2 to tp0md0 bits when the tp0ctl0.tp0ce bit = 0. (the sam e value can be written when the tp0ce bit = 1.) the operation is not guaranteed when rewriting is performed with the tp0ce bit = 1. if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 4. be sure to clear bits 3, 4, and 7 to ?0?.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 135 (3) tmp0 i/o control register 0 (tp0ioc0) the tp0ioc0 register is an 8-bit register that controls the timer output (top00, top01 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tp0ol1 0 1 top01 pin output level setting note top01 pin high-level start top01 pin low-level start tp0ioc0 0 0 0 tp0ol1 tp0oe1 tp0ol0 tp0oe0 6543<2>1 after reset: 00h r/w address: fffff5a2h tp0oe1 0 1 top01 pin output setting timer output disabled ? when tp0ol1 bit = 0: low level is output from the top01 pin ? when tp0ol1 bit = 1: high level is output from the top01 pin tp0ol0 0 1 top00 pin output level setting note top00 pin high-level start top00 pin low-level start tp0oe0 0 1 top00 pin output setting timer output disabled ? when tp0ol0 bit = 0: low level is output from the top00 pin ? when tp0ol0 bit = 1: high level is output from the top00 pin 7 <0> timer output enabled (a square wave is output from the top01 pin). timer output enabled (a square wave is output from the top00 pin). note the output level of the timer out put pin (top0n) specified by the tp0oln bit is shown below (n = 0, 1). tp0ce bit top0n pin output 16-bit counter ? when tp0oln bit = 0 tp0ce bit top0n pin output 16-bit counter ? when tp0oln bit = 1 cautions 1. rewrite the tp0ol1, tp0oe1, tp0ol0, and tp0oe0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. even if the tp0ola bit is manipulated when the tp0ce and tp0oea bits are 0, the top0a pin output level varies (a = 0, 1).
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 136 (4) tmp0 i/o control register 1 (tp0ioc1) the tp0ioc1 register is an 8-bit regist er that controls the valid edge of the capture trig ger input signals (tip00, tip01 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tp0is3 0 0 1 1 tp0is2 0 1 0 1 capture trigger input signal (tip01 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tp0ioc1 0 0 0 tp0is3 tp0is2 tp0is1 tp0is0 654321 after reset: 00h r/w address: fffff5a3h tp0is1 0 0 1 1 tp0is0 0 1 0 1 capture trigger input signal (tip00 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tp0is3 to tp0is0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. the tp0is3 to tp0is0 bi ts are valid only in the free- running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 137 (5) tmp0 i/o control register 2 (tp0ioc2) the tp0ioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tip00 pin) and external trigger input signal (tip00 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tp0ees1 0 0 1 1 tp0ees0 0 1 0 1 external event count input signal (tip00 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tp0ioc2 0 0 0 tp0ees1 tp0ees0 tp0ets1 tp0ets0 654321 after reset: 00h r/w address: fffff5a4h tp0ets1 0 0 1 1 tp0ets0 0 1 0 1 external trigger input signal (tip00 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tp0ees1, tp0ees0, tp0ets1, and tp0ets0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. the tp0ees1 and tp0ees0 bi ts are valid only when the tp0ctl1.tp0eee bit = 1 or when the external event count mode (tp0ctl1.tp0md2 to tp0ctl1.tp0md0 bits = 001) has been set. 3. the tp0ets1 and tp0ets0 bi ts are valid only when the external trigger pulse output mode (tp0md2 to tp0md0 bits = 010) or the one-shot pu lse output mode (tp0md2 to tp0md0 bits = 011) is set.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 138 (6) tmp0 option register 0 (tp0opt0) the tp0opt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tp0ccs1 0 1 tp0ccr1 register capture/compare selection the tp0ccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tp0opt0 0 tp0ccs1 tp0ccs0 0 0 0 tp0ovf 654321 after reset: 00h r/w address: fffff5a5h tp0ccs0 0 1 tp0ccr0 register capture/compare selection the tp0ccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected tp0ovf set (1) reset (0) tmp0 overflow detection flag ? the tp0ovf bit is set when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an interrupt request signal (inttp0ov) is generated at the same time that the tp0ovf bit is set to 1. the inttp0ov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tp0ovf bit is not cleared even when the tp0ovf bit or the tp0opt0 register are read when the tp0ovf bit = 1. ? the tp0ovf bit can be both read and written, but the tp0ovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmp0. overflow occurred tp0ovf bit 0 written or tp0ctl0.tp0ce bit = 0 7 <0> cautions 1. rewrite the tp0ccs1 and tp0ccs0 bits when the tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mi stakenly performed, clear the tp0ce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3, 6, and 7 to ?0?.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 139 (7) tmp0 capture/compare register 0 (tp0ccr0) the tp0ccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tp0opt0.tp0ccs0 bit. in the pulse width measurement mode, the tp0ccr0 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tp0ccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tp0ccr0 register is disable d during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). tp0ccr0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff5a6h 14 0 13 11 9 7 5 3 15 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 140 (a) function as compare register the tp0ccr0 register can be rewritten even when the tp0ctl0.tp0ce bit = 1. the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttp0cc0) is generated. if top00 pin output is ena bled at this time, the output of the top00 pin is inverted. when the tp0ccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. (b) function as capture register when the tp0ccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tp0ccr0 register if the valid ed ge of the capture trigger input pin (tip00 pin) is detected. in the pulse width measur ement mode, the count value of the 16-bit counter is stored in the tp0ccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tip00 pin) is detected. even if the capture operation and reading the tp0 ccr0 register conflict, the correct value of the tp0ccr0 register can be read. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 6-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ?
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 141 (8) tmp0 capture/compare register 1 (tp0ccr1) the tp0ccr1 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tp0opt0.tp0ccs1 bit. in the pulse width measurement mode, the tp0ccr1 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tp0ccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tp0ccr1 register is disable d during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). tp0ccr1 12 10 8 6 4 2 after reset: 0000h r/w address: fffff5a8h 14 0 13 11 9 7 5 3 15 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 142 (a) function as compare register the tp0ccr1 register can be rewritten even when the tp0ctl0.tp0ce bit = 1. the set value of the tp0ccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttp0cc1) is generated. if top01 pin output is ena bled at this time, the output of the top01 pin is inverted. (b) function as capture register when the tp0ccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tp0ccr1 register if the valid ed ge of the capture trigger input pin (tip01 pin) is detected. in the pulse width measur ement mode, the count value of the 16-bit counter is stored in the tp0ccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tip01 pin) is detected. even if the capture operation and reading the tp0 ccr1 register conflict, the correct value of the tp0ccr1 register can be read. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 6-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ?
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 143 (9) tmp0 counter read buffer register (tp0cnt) the tp0cnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tp0ctl0.tp0ce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tp0cnt register is cleared to 0000h wh en the tp0ce bit = 0. if t he tp0cnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tp0cnt register is cleared to 000 0h after reset, as the tp0ce bit is cleared to 0. caution accessing the tp0cnt register is disabl ed during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). tp0cnt 12 10 8 6 4 2 after reset: 0000h r address: fffff5aah 14 0 13 11 9 7 5 3 15 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 144 6.5 operation tmp0 can perform the following operations. operation tp0ctl1.tp0est bit (software trigger bit) tip00 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count mode, specify that t he valid edge of the tip00 pin capture trigger input is not detected (by clearing the tp0ioc1.tp0i s1 and tp0ioc1.tp0is0 bits to ?00?). 2. when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tp0ctl1.tp0eee bit to 0).
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 145 6.5.1 interval timer mode (t p0md2 to tp0md0 bits = 000) in the interval timer mode, an interrupt request signal (inttp0cc0) is generated at t he specified interval if the tp0ctl0.tp0ce bit is set to 1. a square wave whose hal f cycle is equal to the interval can be output from the top00 pin. usually, the tp0ccr1 register is not used in the interval timer mode. figure 6-2. configuration of interval timer 16-bit counter output controller ccr0 buffer register tp0ce bit tp0ccr0 register count clock selection clear match signal top00 pin inttp0cc0 signal figure 6-3. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1)
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 146 when the tp0ce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the out put of the top00 pin is inverted. additionally, the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the top00 pin is in verted, and a compare match interrupt request signal (inttp0cc0) is generated. the interval can be calculated by the following expression. interval = (set value of tp0ccr0 register + 1) count clock cycle figure 6-4. register setting for in terval timer mode operation (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 note 00 tp0ctl1 0, 0, 0: interval timer mode 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count with external event count input signal 000 tp0md2 tp0md1 tp0md0 tp0eee tp0est (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level with operation of top00 pin disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output setting of output level with operation of top01 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 note this bit can be set to 1 only when the interrupt request signals (inttp0cc0 and inttp0cc1) are masked by the interrupt mask flags (tp0ccmk0 and tp0ccmk1) and timer output (top01) is performed at the same time. however, set the tp0ccr0 and tp0ccr1 registers to the same value (refer to 6.5.1 (2) (d) operation of tp0ccr1 register ).
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 147 figure 6-4. register setting for in terval timer mode operation (2/2) (d) tmp0 counter read buffer register (tp0cnt) by reading the tp0cnt register, the count va lue of the 16-bit counter can be read. (e) tmp0 capture/compare register 0 (tp0ccr0) if the tp0ccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tmp0 capture/compare register 1 (tp0ccr1) usually, the tp0ccr1 register is not used in the inte rval timer mode. however, the set value of the tp0ccr1 register is transferred to the ccr1 buffer register. a compare match interrupt request signal (inttp0cc1) is generated when the count value of th e 16-bit counter matches the value of the ccr1 buffer register. therefore, mask the interrupt request by using the corresponding interrupt mask flag (tp0ccmk1). remark tmp0 i/o control register 1 (tp0ioc1), tm p0 i/o control register 2 (tp0ioc2), and tmp0 option register 0 (tp0opt0) are usually not used in the interval timer mode. however, set the tp0ioc2 register to use the external event count input.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 148 (1) interval timer mode operation flow figure 6-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tp0ce bit = 1 tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ccr0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 149 (2) interval timer mode operation timing (a) operation if tp0ccr0 register is cleared to 0000h if the tp0ccr0 register is cleared to 0000h, the inttp 0cc0 signal is generated at each count clock, and the output of the top00 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 150 (b) operation if tp0ccr0 register is set to ffffh if the tp0ccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. t he counter is cleared to 0000h in synchronization with the next count-up timing. the inttp0cc0 signal is generated and the output of the top00 pin is inverted. at this time, an overflow interrupt request signal (inttp0ov) is not generated, nor is the overflow flag (tp0opt0.tp0ovf bit) set to 1. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 151 (c) notes on rewriting tp0ccr0 register to change the value of the tp0ccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tp0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register tp0ol0 bit top00 pin output inttp0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remark interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle if the value of the tp0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tp0ccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttp0cc0 signal is generated and the output of the top00 pin is inverted. therefore, the inttp0cc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 152 (d) operation of tp0ccr1 register figure 6-6. configuration of tp0ccr1 register ccr0 buffer register tp0ccr0 register tp0ccr1 register ccr1 buffer register top00 pin inttp0cc0 signal top01 pin inttp0cc1 signal 16-bit counter output controller tp0ce bit count clock selection clear match signal output controller match signal
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 153 if the set value of the tp0ccr1 register is less than the set value of the tp0ccr0 register, the inttp0cc1 signal is generated once per cycle. at the same time, the output of t he top01 pin is inverted. the top01 pin outputs a square wave with the sa me cycle as that output by the top00 pin. figure 6-7. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal tp0ccr1 register top01 pin output inttp0cc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 154 if the set value of the tp0ccr1 register is greater than the set value of the tp0ccr0 register, the count value of the 16-bit counter does not match the va lue of the tp0ccr1 register. consequently, the inttp0cc1 signal is not generated, nor is the output of the top01 pin changed. figure 6-8. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register top00 pin output inttp0cc0 signal tp0ccr1 register top01 pin output inttp0cc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 155 6.5.2 external event count mode (tp0md2 to tp0md0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tp0ctl0.tp0ce bit is set to 1, and an interrupt request si gnal (inttp0cc0) is generated each time the specified number of edges have been counted. the time r output (top00, top01 pins) cannot be used. usually, the tp0ccr1 register is not us ed in the external event count mode. figure 6-9. configuration in external event count mode 16-bit counter ccr0 buffer register tp0ce bit tp0ccr0 register edge detector clear match signal inttp0cc0 signal tip00 pin (external event count input) figure 6-10. basic timing in external event count mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 0 d 0 d 0 d 0 16-bit counter tp0ccr0 register inttp0cc0 signal external event count input (tip00 pin input) d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) remark this figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 156 when the tp0ce bit is set to 1, the value of the 16-bit counter is clea red from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the tp0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttp0cc0) is generated. the inttp0cc0 signal is generated each time the valid e dge of the external event count input has been detected (set value of tp0ccr0 register + 1) times. figure 6-11. register setting for operati on in external event count mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 0: stop counting 1: enable counting 000 tp0cks2 tp0cks1 tp0cks0 tp0ce (b) tmp0 control register 1 (tp0ctl1) 00000 tp0ctl1 0, 0, 1: external event count mode 001 tp0md2 tp0md1 tp0md0 tp0eee tp0est (c) tmp0 i/o control register 0 (tp0ioc0) 00000 tp0ioc0 0: disable top00 pin output 0: disable top01 pin output 000 tp0oe1 tp0ol0 tp0oe0 tp0ol1 (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 157 figure 6-11. register setting for operati on in external event count mode (2/2) (e) tmp0 counter read buffer register (tp0cnt) the count value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register 0 (tp0ccr0) if d 0 is set to the tp0ccr0 register, the counter is cleared and a compare match interrupt request signal (inttp0cc0) is generated when the nu mber of external event counts reaches (d 0 + 1). (g) tmp0 capture/compare register 1 (tp0ccr1) usually, the tp0ccr1 register is not used in the exte rnal event count mode. however, the set value of the tp0ccr1 register is transferred to the ccr1 buff er register. when the count value of the 16-bit counter matches the value of the ccr1 buffer re gister, a compare match interrupt request signal (inttp0cc1) is generated. therefore, mask the interrupt signal by using the interrupt mask flag (tp0ccmk1). remark tmp0 i/o control register 1 (tp0ioc1) and tmp0 option register 0 (tp0opt0) are not used in the external event count mode.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 158 (1) external event count mode operation flow figure 6-12. flow of software processing in external event count mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tp0ce bit = 1 tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 159 (2) operation timing in external event count mode cautions 1. in the external even t count mode, do not set the tp0 ccr0 and tp0ccr1 registers to 0000h. 2. in the external event count mode, use of the timer output is disabled. if performing timer output using external event co unt input, set the interval timer mode, and select the operation enabled by the external even t count input for the count clock (tp0ctl1.tp0md2 to tp0ctl1.tp0md0 bits = 000, tp0ctl1.tp0eee bit = 1). (a) operation if tp0ccr0 register is set to ffffh if the tp0ccr0 register is set to ffffh, the 16-bit co unter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the inttp0cc0 signal is generated. at this time, the tp0opt0.tp0ovf bit is not set. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 160 (b) notes on rewriting the tp0ccr0 register to change the value of the tp0ccr0 register to a smaller value, stop counting once and then change the set value. if the value of the tp0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) if the value of the tp0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tp0ccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttp0cc0 signal is generated. therefore, the inttp0cc0 signal may not be generated at the va lid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 161 (c) operation of tp0ccr1 register figure 6-13. configuration of tp0ccr1 register ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal inttp0cc1 signal edge detector tip00 pin if the set value of the tp0ccr1 register is smalle r than the set value of the tp0ccr0 register, the inttp0cc1 signal is generated once per cycle. figure 6-14. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 162 if the set value of the tp0ccr1 register is greater than the set value of the tp0ccr0 register, the inttp0cc1 signal is not generated because the count va lue of the 16-bit counte r and the value of the tp0ccr1 register do not match. figure 6-15. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 163 6.5.3 external trigger pulse output mode (tp0md2 to tp0md0 bits = 010) in the external trigger pulse output mode, 16-bit timer/event counter p waits for a trigger when the tp0ctl0.tp0ce bit is set to 1. when the valid edge of an ex ternal trigger input signal is detected, 16-bit timer/event counter p starts counting, and outputs a pwm waveform from the top01 pin. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the top00 pin. figure 6-16. configuration in external trigger pulse output mode ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) output controller top01 pin inttp0cc1 signal top00 pin count clock selection count start control edge detector software trigger generation tip00 pin transfer transfer s r
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 164 figure 6-17. basic timing in exte rnal trigger pulse output mode external trigger input (tip00 pin input) top00 pin output (software trigger) d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output 16-bit timer/event counter p waits for a trigger when the tp0c e bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing at the same time, and out puts a pwm waveform from the top01 pin. if the trigger is generated again while the counter is operating, the counter is cleared to 0000h and restarted. (the output of th e top00 pin is inverted. the top01 pin outputs a high leve l regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tp0ccr1 register) count clock cycle cycle = (set value of tp0ccr0 register + 1) count clock cycle duty factor = (set value of tp0ccr1 regist er)/(set value of tp0ccr0 register + 1) the compare match interrupt request signal inttp0cc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttp0cc1 is gener ated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tp0ccra register is transferred to t he ccra buffer register when the count value of the 16-bit counter matches the value of the ccra buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal, or setti ng the software trigger (tp0ctl1.tp0est bit) to 1 is used as the trigger. remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 165 figure 6-18. setting of registers in exte rnal trigger pulse output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0/1 0/1 0 0 tp0ctl1 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count with external event input signal generate software trigger when 1 is written 010 tp0md2 tp0md1 tp0md0 tp0eee tp0est 0, 1, 0: external trigger pulse output mode (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output settings of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? when tp0ol1 bit = 0 top01 pin output 16-bit counter ? when tp0ol1 bit = 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 166 figure 6-18. setting of registers in exte rnal trigger pulse output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remark tmp0 i/o control register 1 (tp0ioc1) and tm p0 option register 0 (tp0opt0) are not used in the external trigger pulse output mode.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 167 (1) operation flow in extern al trigger pulse output mode figure 6-19. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) top00 pin output (software trigger) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5>
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 168 figure 6-19. software processing flow in ex ternal trigger pulse output mode (2/2) tp0ce bit = 1 setting of tp0ccr0 register register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting is enabled (tp0ce bit = 1). trigger wait status tp0ccr1 register write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. start setting of tp0ccr1 register <1> count operation start flow <2> tp0ccr0 and tp0ccr1 register setting change flow setting of tp0ccr0 register when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. setting of tp0ccr1 register <4> tp0ccr0, tp0ccr1 register setting change flow only writing of the tp0ccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. setting of tp0ccr1 register <3> tp0ccr0, tp0ccr1 register setting change flow tp0ce bit = 0 counting is stopped. stop <5> count operation stop flow remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 169 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tp0ccr1 register last. rewrite the tp0ccra register after writing the tp0ccr1 register after the inttp0cc0 signal is detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) top00 pin output (software trigger) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 170 in order to transfer data from the tp0ccra register to the ccra buffer register, the tp0ccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tp0ccr0 register and then set the active level width to the tp0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tp0ccr0 register, and then write the same value to the tp0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tp0ccr1 register has to be set. after data is written to the tp0ccr1 register, the val ue written to the tp0ccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tp0ccr0 or tp0ccr1 register again after writing the tp0ccr1 register once, do so after the inttp0cc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the tp0ccra register to the ccra buffer register conflicts with writing the tp0ccra register. remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 171 (b) 0%/100% output of pwm waveform to output a 0% waveform, clear the tp0ccr1 register to 0000h. if the set value of the tp0ccr0 register is ffffh, the inttp0cc1 signal is generated periodically. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 to output a 100% waveform, set a value of (set value of tp0ccr0 register + 1) to the tp0ccr1 register. if the set value of the tp0ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 172 (c) conflict between trigger detecti on and match with tp0ccr1 register if the trigger is detected immediately after the inttp 0cc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the top01 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened if the trigger is detected immediately before the inttp 0cc1 signal is generated, the inttp0cc1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. t he output signal of the top01 pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 173 (d) conflict between trigger detecti on and match with tp0ccr0 register if the trigger is detected immediately after the inttp 0cc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the top01 pin is extended by time from generation of the inttp0cc0 signal to trigger detection. 16-bit counter tp0ccr0 register inttp0cc0 signal top01 pin output external trigger input (tip00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended if the trigger is detected immediately before the inttp 0cc0 signal is generated, the inttp0cc0 signal is not generated. the 16-bit counter is cleared to 0000h, the top01 pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter tp0ccr0 register inttp0cc0 signal top01 pin output external trigger input (tip00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 174 (e) generation timing of compare match interrupt request signal (inttp0cc1) the timing of generation of the inttp0cc1 signal in the external trigger pulse output mode differs from the timing of other inttp0cc1 signals; the inttp0cc1 signal is generated when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? 1d 1 ? 1d 1 d 1 + 1 d 1 + 2 usually, the inttp0cc1 signal is generated in synch ronization with the next count up, after the count value of the 16-bit counter matches the value of the tp0ccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the top01 pin.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 175 6.5.4 one-shot pulse output mode (tp0md2 to tp0md0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter p waits for a trigger when the tp0ctl0.tp0ce bit is set to 1. when the valid edge of an external trigger input is detected, 16-bit timer/event co unter p starts counting, and outputs a one-shot pulse from the top01 pin. instead of the external trigger, a software trigger can also be generated to output the pulse. when the software trigger is used, the top00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 6-20. configuration in one-shot pulse output mode ccr0 buffer register tp0ce bit tp0ccr0 register tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) top01 pin inttp0cc1 signal top00 pin count clock selection count start control edge detector software trigger generation tip00 pin transfer transfer s r output controller (rs-ff) s r 16-bit counter
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 176 figure 6-21. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) top00 pin output (software trigger) when the tp0ce bit is set to 1, 16-bit timer/event counter p waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counti ng, and outputs a one-shot pul se from the top01 pin. after the one-shot pulse is output, the 16-bit counter is set to ffffh, stops counting, and waits for a trigger. if a trigger is generated again while the one-s hot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tp0ccr1 register) count clock cycle active level width = (set value of tp0ccr0 register ? set value of tp0ccr1 register + 1) count clock cycle the compare match interrupt request signal inttp0cc0 is generated when the 16-bit counter counts after its count value matches the value of the ccr0 buffer regist er. the compare match interrupt request signal inttp0cc1 is generated when the count value of the 16-bit counter matches the va lue of the ccr1 buffer register. the valid edge of an external trigger input or setting the so ftware trigger (tp0ctl1.tp0est bit) to 1 is used as the trigger.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 177 figure 6-22. setting of registers in one-shot pulse output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0/1 0/1 0 0 tp0ctl1 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count external event input signal generate software trigger when 1 is written 011 tp0md2 tp0md1 tp0md0 tp0eee tp0est 0, 1, 1: one-shot pulse output mode (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? when tp0ol1 bit = 0 top01 pin output 16-bit counter ? when tp0ol1 bit = 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 178 figure 6-22. setting of registers in one-shot pulse output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external trigger input select valid edge of external event count input 0/1 0/1 0/1 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 0 ? d 1 + 1) count clock cycle output delay period = d 1 count clock cycle caution one-shot pulses are not output in the one -shot pulse output mode if the value set for the tp0ccr1 register is greater th an that for the tp0ccr0 register. remark tmp0 i/o control register 1 (tp0ioc1) and tm p0 option register 0 (tp0opt0) are not used in the one-shot pulse output mode.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 179 (1) operation flow in one-shot pulse output mode figure 6-23. software processing flow in one-shot pulse output mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) <1> <3> tp0ce bit = 1 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). trigger wait status start <1> count operation start flow tp0ce bit = 0 count operation is stopped stop <3> count operation stop flow d 10 d 00 d 11 d 01 d 00 d 10 d 11 <2> d 01 setting of tp0ccr0, tp0ccr1 registers as rewriting the tp0ccrm register immediately forwards to the ccrm buffer register, rewriting immediately after the generation of the inttp0ccr0 signal is recommended. <2> tp0ccr0, tp0ccr1 register setting change flow remark m = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 180 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tp0ccra register to change the set value of the tp0ccra register to a smaller value, stop counting once, and then change the set value. if the value of the tp0ccra register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal tp0ccr1 register inttp0cc1 signal top01 pin output external trigger input (tip00 pin input) d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) top00 pin output (software trigger) when the tp0ccr0 register is rewritten from d 00 to d 01 and the tp0ccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the tp0ccr1 register is rewritten when the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the tp0ccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter count s up to ffffh and then counts up again from 0000h. when the count value matches d 11 , the counter generates the inttp0cc1 signal and asserts the top01 pin. when the count value matches d 01 , the counter generates the in ttp0cc0 signal, deasserts the top01 pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 181 (b) generation timing of compare match interrupt request signal (inttp0cc1) the generation timing of the inttp0cc1 signal in the on e-shot pulse output mode is different from other inttp0cc1 signals; the inttp0cc1 signal is genera ted when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 usually, the inttp0cc1 signal is generated when the 16- bit counter counts up next time after its count value matches the value of the tp0ccr1 register. in the one-shot pulse output mode, howe ver, it is generated one clock earlier. this is because the timing is changed to match the change timing of the top01 pin.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 182 6.5.5 pwm output mode (tp0md2 to tp0md0 bits = 100) in the pwm output mode, a pwm waveform is output from the top01 pin when the tp0ctl0.tp0ce bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the top00 pin. figure 6-24. configuration in pwm output mode ccr0 buffer register tp0ce bit tp0ccr0 register 16-bit counter tp0ccr1 register ccr1 buffer register clear match signal match signal inttp0cc0 signal output controller (rs-ff) output controller top01 pin inttp0cc1 signal top00 pin count clock selection count start control transfer transfer s r
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 183 figure 6-25. basic timing in pwm output mode ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal top00 pin output tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 ? d 10 + 1) when the tp0ce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts count ing, and outputs a pwm waveform from the top01 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tp0ccr1 register ) count clock cycle cycle = (set value of tp0ccr0 register + 1) count clock cycle duty factor = (set value of tp0ccr1 regist er)/(set value of tp0ccr0 register + 1) the pwm waveform can be changed by rewriting the tp0ccra register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttp0cc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttp0cc1 is gener ated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tp0ccra register is transferred to t he ccra buffer register when the count value of the 16-bit counter matches the value of the ccra buffer regi ster and the 16-bit counter is cleared to 0000h. remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 184 figure 6-26. register setting in pwm output mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 0 0 tp0ctl1 100 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 0, 0: pwm output mode 0: operate on count clock selected by tp0cks0 to tp0cks2 bits 1: count with external event count input signal (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level while operation of top00 pin is disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output specifies active level of top01 pin output 0: active-high 1: active-low 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1 top01 pin output 16-bit counter ? when tp0ol1 bit = 0 top01 pin output 16-bit counter ? when tp0ol1 bit = 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 185 figure 6-26. register setting in pwm output mode (2/2) (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input. 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (e) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (f) tmp0 capture/compare register s 0 and 1 (tp0ccr0 and tp0ccr1) if d 0 is set to the tp0ccr0 register and d 1 to the tp0ccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remark tmp0 i/o control register 1 (tp0ioc1) and tm p0 option register 0 (tp0opt0) are not used in the pwm output mode.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 186 (1) operation flow in pwm output mode figure 6-27. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register inttp0cc0 signal top00 pin output tp0ccr1 register ccr1 buffer register inttp0cc1 signal top01 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <2> <3> <4> <5> <1>
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 187 figure 6-27. software processing flow in pwm output mode (2/2) tp0ce bit = 1 setting of tp0ccr0 register register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting is enabled (tp0ce bit = 1). tp0ccr1 write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tp0ccra register is transferred to the ccra buffer register. start setting of tp0ccr1 register <1> count operation start flow <2> tp0ccr0, tp0ccr1 register setting change flow setting of tp0ccr0 register when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of tp0ccr1 register <4> tp0ccr0, tp0ccr1 register setting change flow only writing of the tp0ccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of tp0ccr1 register <3> tp0ccr0, tp0ccr1 register setting change flow tp0ce bit = 0 counting is stopped. stop <5> count operation stop flow remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 188 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tp0ccr1 register last. rewrite the tp0ccra register after writing the tp0ccr1 register after the inttp0cc1 signal is detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register ccr0 buffer register tp0ccr1 register ccr1 buffer register top01 pin output inttp0cc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the tp0ccra register to the ccra buffer register, the tp0ccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tp0ccr0 register and then set the active level to the tp0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tp0ccr0 register, and then write the same value to the tp0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tp0ccr1 register has to be set. after data is written to the tp0ccr1 register, the val ue written to the tp0ccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tp0ccr0 or tp0ccr1 register again after writing the tp0ccr1 register once, do so after the inttp0cc0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the tp0ccra register to the ccra buffer register conflicts with writing the tp0ccra register. remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 189 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tp0ccr1 register to 0000h. if the set value of the tp0ccr0 register is ffffh, the inttp0cc1 signal is generated periodically. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 to output a 100% waveform, set a value of (set value of tp0ccr0 register + 1) to the tp0ccr1 register. if the set value of the tp0ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tp0ce bit tp0ccr0 register tp0ccr1 register inttp0cc0 signal inttp0cc1 signal top01 pin output d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 190 (c) generation timing of compare match interrupt request signal (inttp0cc1) the timing of generation of the inttp0cc1 signal in the pwm output mode differs from the timing of other inttp0cc1 signals; the inttp0cc1 signal is genera ted when the count value of the 16-bit counter matches the value of the tp0ccr1 register. count clock 16-bit counter tp0ccr1 register top01 pin output inttp0cc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 usually, the inttp0cc1 signal is generated in synch ronization with the next counting up after the count value of the 16-bit counter matches the value of the tp0ccr1 register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the top01 pin.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 191 6.5.6 free-running timer mode (tp0md2 to tp0md0 bits = 101) in the free-running timer mode, 16-bit timer/event counter p starts counting when the tp 0ctl0.tp0ce bit is set to 1. at this time, the tp0ccra register can be used as a compare register or a c apture register, depending on the setting of the tp0opt0.tp0ccs 0 and tp0opt0.tp0ccs1 bits. figure 6-28. configuration in free-running timer mode tp0ccr0 register (capture) tp0ce bit tp0ccr1 register (capture) 16-bit counter tp0ccr1 register (compare) tp0ccr0 register (compare) output controller tp0ccs0, tp0ccs1 bits (capture/compare selection) top00 pin output output controller top01 pin output edge detector count clock selection digital noise eliminator digital noise eliminator tip00 pin (external event count input/ capture trigger input) tip01 pin (capture trigger input) internal count clock 0 1 0 1 inttp0ov signal inttp0cc1 signal inttp0cc0 signal edge detector edge detector remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 192 when the tp0ce bit is set to 1, 16-bit timer/event counter p starts counting, and the ou tput signals of the top00 and top01 pins are inverted. when the count value of the 16-bit counter later matches the set value of the tp0ccra register, a compare match interrupt request signal (inttp0 cca) is generated, and the out put signal of the top0a pin is inverted. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttp0ov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tp0opt0.tp0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the tp0ccra register can be rewritten whil e the counter is operating. if it is re written, the new value is reflected at that time, and compared with the count value. figure 6-29. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 193 when the tp0ce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tip0a pin is detected, the count value of the 16-bit counter is stored in the tp0ccra register, and a capture interrupt request signal (inttp0cca) is generated. the 16-bit counter continues counting in synchronization with t he count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttp0ov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tp0opt0.tp0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. figure 6-30. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 194 figure 6-31. register setting in free-running timer mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note the setting is invalid when the tp0ctl1.tp0eee bit = 1 (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 0 0 tp0ctl1 101 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 0, 1: free-running mode 0: operate with count clock selected by tp0cks0 to tp0cks2 bits 1: count on external event count input signal (c) tmp0 i/o control register 0 (tp0ioc0) 0 0 0 0 0/1 tp0ioc0 0: disable top00 pin output 1: enable top00 pin output setting of output level with operation of top00 pin disabled 0: low level 1: high level 0: disable top01 pin output 1: enable top01 pin output setting of output level with operation of top01 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tp0oe1 tp0ol0 tp0oe0 tp0ol1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 195 figure 6-31. register setting in free-running timer mode (2/2) (d) tmp0 i/o control register 1 (tp0ioc1) 0 0 0 0 0/1 tp0ioc1 select valid edge of tip00 pin input select valid edge of tip01 pin input 0/1 0/1 0/1 tp0is2 tp0is1 tp0is0 tp0is3 (e) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1 (f) tmp0 option register 0 (tp0opt0) 0 0 0/1 0/1 0 tp0opt0 overflow flag specifies if tp0ccr0 register functions as capture or compare register specifies if tp0ccr1 register functions as capture or compare register 0 0 0/1 tp0ccs0 tp0ovf tp0ccs1 (g) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (h) tmp0 capture/compare regist ers 0 and 1 (tp0ccr0 and tp0ccr1) these registers function as captur e registers or compare registers depending on the setting of the tp0opt0.tp0ccsa bit. when the registers function as captur e registers, they store the count value of the 16-bit counter when the valid edge input to t he tip0a pin is detected. when the registers function as compare registers and when d a is set to the tp0ccra register, the inttp0cca signal is generated when the counter reaches (d a + 1), and the output signal of the top0a pin is inverted. remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 196 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 6-32. software processing flow in fr ee-running timer mode (c ompare function) (1/2) ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3>
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 197 figure 6-32. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tp0ce bit = 1 read tp0opt0 register (check overflow flag). register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc0 register, tp0ioc2 register, tp0opt0 register, tp0ccr0 register, tp0ccr1 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). start execute instruction to clear tp0ovf bit (clr tp0ovf). <1> count operation start flow <2> overflow flag clear flow tp0ce bit = 0 counter is initialized and counting is stopped by clearing tp0ce bit to 0. stop <3> count operation stop flow tp0ovf bit = 1 no yes
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 198 (b) when using capture/compare register as capture register figure 6-33. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2>
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 199 figure 6-33. software processing flow in fr ee-running timer mode (c apture function) (2/2) tp0ce bit = 1 read tp0opt0 register (check overflow flag). register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits) tp0ctl1 register, tp0ioc1 register, tp0opt0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). start execute instruction to clear tp0ovf bit (clr tp0ovf). <1> count operation start flow <2> overflow flag clear flow tp0ce bit = 0 counter is initialized and counting is stopped by clearing tp0ce bit to 0. stop <3> count operation stop flow tp0ovf bit = 1 no yes
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 200 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter p is used as an interval timer with the tp0ccra register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttp0cca signal has been detected. ffffh 16-bit counter 0000h tp0ce bit tp0ccr0 register inttp0cc0 signal top00 pin output tp0ccr1 register inttp0cc1 signal top01 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the corresponding tp0ccra register must be re-set in the interrupt servicing that is executed when the inttp0cca signal is detected. the set value for re-setting the tp0ccra register can be calculated by the following expression, where ?d a ? is the interval period. compare register default value: d a ? 1 value set to compare register second and subsequent time: previous set value + d a (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 201 (b) pulse width measurement with capture register when pulse width measurement is performed with the tp0ccra register used as a capture register, software processing is necessary for reading the capt ure register each time the inttp0cca signal has been detected and for calculating an interval. ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal tip01 pin input tp0ccr1 register inttp0cc1 signal inttp0ov signal tp0ovf bit 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 pulse interval (d 00 ) pulse interval (10000h + d 01 ? d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the fr ee-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calcul ated by reading the value of the tp0ccra register in synchronization with the inttp0cca signal, and calculating the difference between the read value and the previously read value. remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 202 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register tip01 pin input tp0ccr1 register inttp0ov signal tp0ovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> read the tp0ccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tp0ccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 203 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tp0ce bit inttp0ov signal tp0ovf bit tp0ovf0 flag note tip00 pin input tp0ccr0 register tp0ovf1 flag note tip01 pin input tp0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tp0ovf0 and tp0ovf1 flags are set on the internal ram by software. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> an overflow occurs. set the tp0ovf0 and tp0ovf 1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tp0ccr0 register. read the tp0ovf0 flag. if the tp0ovf0 flag is 1, clear it to 0. because the tp0ovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tp0ccr1 register. read the tp0ovf1 flag. if the tp0ovf1 flag is 1, clear it to 0 (the tp0ovf0 flag is cleared in <4>, and the tp0ovf1 flag remains 1). because the tp0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 204 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tp0ce bit inttp0ov signal tp0ovf bit tp0ovf0 flag note tip00 pin input tp0ccr0 register tp0ovf1 flag note tip01 pin input tp0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tp0ovf0 and tp0ovf1 flags are set on the internal ram by software. <1> read the tp0ccr0 register (setting of t he default value of the tip00 pin input). <2> read the tp0ccr1 register (setting of t he default value of the tip01 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tp0ccr0 register. read the overflow flag. if the overflow flag is 1, set only the tp0ovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tp0ccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tp0ovf1 flag. if the tp0ovf1 flag is 1, clear it to 0. because the tp0ovf1 flag is 1, the pul se width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 205 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16- bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0ov signal tp0ovf bit d a0 d a1 d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the tp0ccra register (setting of t he default value of the tip0a pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tp0ccra register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d a1 ? d a0 ) (incorrect). actually, the pulse width must be (20000h + d a1 ? d a0 ) because an overflow occurs twice. if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 206 example when capture trigger interval is long ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0ov signal tp0ovf bit overflow counter note d a0 d a1 1h 0h 2h 0h d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tp0ccra register (setting of t he default value of the tip0a pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tp0ccra register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d a1 ? d a0 ). in this example, the pulse width is (20000h + d a1 ? d a0 ) because an overflow occurs twice. clear the overflow counter (0h).
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 207 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tp0ovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tp0opt0 regist er. to accurately detect an overflow, read the tp0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tp0ovf bit) overflow flag (tp0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 208 6.5.7 pulse width measurement mode (tp0md2 to tp0md0 bits = 110) in the pulse width measurement mode, 16-bit timer/event counter p starts counting when the tp0ctl0.tp0ce bit is set to 1. each time the valid edge input to the tip0a pi n has been detected, the count va lue of the 16-bit counter is stored in the tp0ccra register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by readin g the tp0ccra register after a capture interrupt request signal (inttp0cca) occurs. select either the tip00 or tip01 pin as the capture trigger input pin. specify ?no edge detected? by using the tp0ioc1 register for the unused pins. when an external clock is used as the count clock, measur e the pulse width of the tip01 pin because the external clock is fixed to the tip00 pin. at this time, clear the tp0ioc1.tp0is1 and tp0ioc1.tp0is0 bits to 00 (capture trigger input (tip00 pin): no edge detected). figure 6-34. configuration in pulse width measurement mode tp0ccr0 register (capture) tp0ce bit tp0ccr1 register (capture) edge detector count clock selection edge detector edge detector tip00 pin (external event count input/capture trigger input) tip01 pin (capture trigger input) internal count clock clear inttp0ov signal inttp0cc0 signal inttp0cc1 signal 16-bit counter digital noise eliminator digital noise eliminator remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 209 figure 6-35. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tp0ce bit tip0a pin input tp0ccra register inttp0cca signal inttp0ov signal tp0ovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark a = 0, 1 when the tp0ce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tip0a pin is later detected, the count value of the 16-bit counter is stored in the tp0ccra register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttp0cca) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tip0a pin even wh en the 16-bit counter counted up to ffffh, an overflow interrupt request signal (inttp0ov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tp0opt0.t p0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tp0ovf bit set (1) count + captured value) count clock cycle remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 210 figure 6-36. register setting in pu lse width measurement mode (1/2) (a) tmp0 control re gister 0 (tp0ctl0) 0/1 0 0 0 0 tp0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tp0cks2 tp0cks1 tp0cks0 tp0ce note setting is invalid when the tp0eee bit = 1. (b) tmp0 control register 1 (tp0ctl1) 0 0 0/1 0 0 tp0ctl1 110 tp0md2 tp0md1 tp0md0 tp0eee tp0est 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tp0cks0 to tp0cks2 bits 1: count external event count input signal (c) tmp0 i/o control register 1 (tp0ioc1) 0 0 0 0 0/1 tp0ioc1 select valid edge of tip00 pin input select valid edge of tip01 pin input 0/1 0/1 0/1 tp0is2 tp0is1 tp0is0 tp0is3 (d) tmp0 i/o control register 2 (tp0ioc2) 0 0 0 0 0/1 tp0ioc2 select valid edge of external event count input 0/1 0 0 tp0ees0 tp0ets1 tp0ets0 tp0ees1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 211 figure 6-36. register setting in pu lse width measurement mode (2/2) (e) tmp0 option register 0 (tp0opt0) 00000 tp0opt0 overflow flag 0 0 0/1 tp0ccs0 tp0ovf tp0ccs1 (f) tmp0 counter read buffer register (tp0cnt) the value of the 16-bit counter can be read by reading the tp0cnt register. (g) tmp0 capture/compare regist ers 0 and 1 (tp0ccr0 and tp0ccr1) these registers store the count valu e of the 16-bit counter when the valid edge input to the tip0a pin is detected. remarks 1. tmp0 i/o control register 0 (tp0ioc0) is not used in the pulse wid th measurement mode. 2. a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 212 (1) operation flow in pul se width measurement mode figure 6-37. software processing flow in pulse width measurement mode <1> <2> set tp0ctl0 register (tp0ce bit = 1) tp0ce bit = 0 register initial setting tp0ctl0 register (tp0cks0 to tp0cks2 bits), tp0ctl1 register, tp0ioc1 register, tp0ioc2 register, tp0opt0 register initial setting of these registers is performed before setting the tp0ce bit to 1. the tp0cks0 to tp0cks2 bits can be set at the same time when counting has been started (tp0ce bit = 1). the counter is initialized and counting is stopped by clearing the tp0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tp0ce bit tip00 pin input tp0ccr0 register inttp0cc0 signal d 0 0000h 0000h d 1 d 2
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 213 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tp0ovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tp0opt0 regist er. to accurately detect an overflow, read the tp0ovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tp0ovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tp0ovf bit) overflow flag (tp0ovf bit) l h l to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag wit hout checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conflicts with occurrence of an over flow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clear instruction.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 214 6.5.8 timer output operations the following table shows the operations and out put levels of the top00 and top01 pins. table 6-4. timer output control in each mode operation mode top01 pin top00 pin interval timer mode square wave output external event count mode square wave output ? external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output square wave output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? table 6-5. truth table of top00 and top01 pins under control of timer output control bits tp0ioc0.tp0ola bit tp0ioc0.tp0oea bit tp0ctl0.tp0ce bit level of top0a pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark a = 0, 1
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 215 6.6 eliminating noise on capture trigger input pin (tip0a) the tip0a pin has a digital noise eliminator. however, this circuit is valid only when the pin is used as a capture trigger input pin; it is invalid when the pin is used as an external event count input pin or external trigger input pin. digital noise can be eliminated by specifying the alter nate function of the tip0a pi n using the pmc3, pfc3, and pfce3 registers. the number of times of sampling can be selected from three or two by using the panfc.panfsts bit. the sampling clock can be selected from f xx , f xx /2, f xx /4, f xx /16, f xx /32, or f xx /64, by using the panfc.panfc2 to panfc.panfc0 bits. (1) tip0a noise elimination control register (panfc) this register is used to select the sampling clock and t he number of times of sampling for eliminating digital noise. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 panfc (a = 0, 1) panfsts 0 0 0 panfc2 panfc1 panfc0 number of times of sampling = 3 number of times of sampling = 2 panfsts 0 1 setting of number of times of sampling for eliminating digital noise after reset: 00h r/w address: p0nfc fffffb00h, p1nfc fffffb04h f xx f xx /2 f xx /4 f xx /16 f xx /32 f xx /64 panfc2 0 0 0 0 1 1 panfc1 0 0 1 1 0 0 panfc0 0 1 0 1 0 1 sampling clock selection setting prohibited other than above cautions 1. enable starting the 16-bit counter of tmp0 (tp0ctl.tp0ce bit = 1) after the lapse of the sampling clock period number of times of sampling. 2. be sure to clear bits 7, 5 to 3 to ?0?.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 216 <1> select the number of times of sampling a nd the sampling clock by using the panfc register. <2> select the alternate function (of the tip0a pin) by using the pmc3, pfc3, and pfce3 registers. <3> set the operating mode of tmp0 (such as the capt ure mode or the valid edge of the capture trigger). <4> enable the tmp0 count operation. the digital noise elimination width (t wtipa ) is as follows, where t is the sampling clock period and m is the number of times of sampling. ? t wtipa < (m ? 1)t: accurately eliminated as noise ? (m ? 1)t t wtipa < mt: eliminated as noise or detected as valid edge ? t wtipa mt: accurately detected as valid edge therefore, a pulse width of mt or lon ger must be input so that the valid ed ge of the capture trigger input can be accurately detected.
chapter 6 16-bit timer/event counter p (tmp) user?s manual u17705ej2v0ud 217 6.7 cautions (1) capture operation when the capture operation is used and f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, or the external event counter (tp0clt1.tp0eee bit = 1) is selected as the count clock, ffffh, not 0000h, may be captured in the tp0ccrn register if the capture trigger is input immediately after the tp0ce bit is set to 1. (a) free-running timer mode count clock 0000h ffffh tp0ce bit tp0ccr0 register ffffh 0001h 0000h tip00 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tp0ce bit tp0ccr0 register tip00 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input
user?s manual u17705ej2v0ud 218 chapter 7 16-bit timer/event counter 0 in the v850es/ke2, one channel of 16-bit timer/event counter 0 is provided. 7.1 functions 16-bit timer/event counter 01 has the following functions. (1) interval timer 16-bit timer/event counter 01 generates an inte rrupt request at the preset time interval. (2) square-wave output 16-bit timer/event counter 01 can output a square wave with any selected frequency. (3) external event counter 16-bit timer/event counter 01 c an measure the number of pulses of an externally input signal. (4) one-shot pulse output 16-bit timer/event counter 01 can output a one-shot pulse whose output pulse width can be set freely. (5) ppg output 16-bit timer/event counter 01 can output a rectangular wa ve whose frequency and output pulse width can be set freely. (6) pulse width measurement 16-bit timer/event counter 01 can measure the pulse width of an externally input signal.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 219 7.2 configuration 16-bit timer/event counter 01 includes the following hardware. table 7-1. configuration of 16-bit timer/event counter 01 item configuration time/counter 16-bit timer counter 01 (tm01) register 16-bit timer capture/ compare registers: 16-bit 2 (cr010, cr011) timer input 2 (ti010, ti011 pins) timer output 1 (to01 pin), output controller control registers note 16-bit timer mode control register 01 (tmc01) capture/compare control register 01 (crc01) 16-bit timer output control register 01 (toc01) prescaler mode register 01 (prm01) selector operation control register 1 (selcnt1) note to use the ti010, ti011, and to01 pin functions, refer to table 4-12 settings when port pins are used for alternate functions . the block diagram is shown below. figure 7-1. block diagram of 16-bit timer/event counter 01 inttm010 to01 inttm011 tl011 f xx /4 tl010 3 crc012 crc011 crc010 tmc013 tmc012 tmc011 ovf01 ospt01 ospe01 toc014 lvs01 lvr01 toc011 toe01 match clear noise eliminator noise eliminator 16-bit timer capture/compare register 010 (cr010) 16-bit timer capture/compare register 011 (cr011) 16-bit timer counter 01 (tm01) match internal bus count clock capture/compare control register 01 (crc01) output controller selector timer output control register 01 (toc01) noise eliminator 16-bit timer mode control register 01 (tmc01) selector selector internal bus selector prescaler mode register 01 (prm01) selector operation control register 1 (selcnt1) prm011 isel11 prm010 remark f xx : main clock frequency
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 220 (1) 16-bit timer counter 01 (tm01) the tm01 register is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the count clock. tm01 12 10 8 6 4 2 after reset: 0000h r address: fffff610h 14 0 13 11 9 7 5 3 15 1 the count value of the tm01 regist er can be read by reading the tm01 register when the values of the tmc01.tmc013 and tmc01.tmc012 bits are other than 00. t he value of the tm01 register is 0000h if it is read when the tmc013 and tmc012 bits are 00. the count value is reset to 0000h in the following cases. ? at reset signal generation ? if the tmc013 and tmc012 bits are cleared to 00 ? if the valid edge of the ti010 pin is input in the mode in which the clear & start occurs when inputting the valid edge to the ti010 pin ? if the tm01 register and the cr010 register match in the mode in which the clear & start occurs when the tm01 register and the cr010 register match ? the toc01.ospt01 bit is set to 1 in one-shot pulse out put mode or the valid edge is input to the ti010 pin (2) 16-bit timer capture/compare regi ster 010 (cr010), 16-bit timer cap ture/compare register 011 (cr011) the cr010 and cr011 registers are 16-bi t registers that are used with a capt ure function or comparison function selected by using the crc01 register. change of the value of the cr010 register while th e timer is operating (tmc01.tmc013 and tmc01.tmc012 bits = other than 00) is prohibited. the value of the cr011 register can be changed during operat ion if the value has been set in a specific way. for details, see 7.5.1 rewriting cr011 re gister during tm01 operation . these registers can be read or written in 16-bit units. reset sets these registers to 0000h. (a) 16-bit timer capture/comp are register 010 (cr010) cr010 12108642 after reset: 0000h r/w address: fffff612h 14 0 13 11 9 7 5 3 15 1
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 221 (i) when the cr010 register is used as a compare register the value set in the cr010 register is constantly compar ed with the tm01 register count value, and an interrupt request signal (inttm010) is generated if they match. the va lue is held until the cr010 register is rewritten. (ii) when the cr010 register is used as a capture register the count value of the tm01 register is captured to the cr010 register when a capture trigger is input. as the capture trigger, an edge of a phase reverse to that of the ti010 pin or the valid edge of the ti011 pin can be selected by using the crc01 or prm01 register. (b) 16-bit timer capture/comp are register 011 (cr011) cr011 12 10 8 6 4 2 after reset: 0000h r/w address: fffff614h 14 0 13 11 9 7 5 3 15 1 (i) when using the cr011 register as a compare register the value set to the cr011 register and the count value of the tm01 re gister are always compared and when these values match, an interrupt re quest signal (inttm011) is generated. (ii) when using the cr011 regi ster as a capture register the tm01 register count value is captured to the cr011 register by inputting a capture trigger. the valid edge of the ti010 pin can be selected as t he capture trigger. the valid edge of the ti010 pin is set with the prm01 register. cautions 1. when the p35 pin is used as the valid edge of ti010 a nd the timer output function is used, set the p32 pin as the timer output pin (to01). 2. if clearing of the tmc013 and tmc012 bits to 00 and input of the capture trigger conflict, then the captured data is undefined. 3. to change the mode from the capture mode to the comparison mode, first clear the tmc013 and tmc012 bits to 00, and then change the setting. a value that has been on ce captured remains stored in the cr010 and cr011 registers unless the device is reset. if the mode has b een changed to the comparison mode, be sure to set a comparison value.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 222 (c) setting range when u sed as compare register when the cr010 or cr011 register is used as a compare register, set it as shown below. operation cr010 register cr011 register ? operation as interval timer ? operation as square-wave output ? operation as external event counter 0000h < n ffffh 0000h note m ffffh normally, this setting is not used. mask the match interrupt signal (inttm011). ? operation in the clear & start mode entered by ti010 pin valid edge input ? operation as free-running timer 0000h note n ffffh 0000h note m ffffh ? operation as ppg output m < n ffffh 0000h note m < n ? operation as one-shot pulse output 0000h note n ffffh (n m) 0000h note m ffffh (m n) note when 0000h is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the first match timing is as follows . a match interrupt occurs at the timing when the timer counter (tm01 register) is changed from 0000h to 0001h. ? when the timer counter is cleared due to overflow ? when the timer counter is cleared due to ti010 pin valid edge (when clear & start mode is entered by ti010 pin valid edge input) ? when the timer counter is cleared due to compare ma tch (when clear & start mode is entered by match between tm01 and cr010 (cr010 = other than 0000h, cr011 = 0000h)) operation enabled (other than 00) tm01 register timer counter clear interrupt signal is not generated interrupt signal is generated timer operation enable bit interrupt request signal compare register set value (0000h) operation disabled (00) remarks 1. n: cr010 register set value m: cr011 register set value 2. for details of operation enable bits (tmc 01.tmc013, tmc01.tmc012 bits), refer to 7.3 (1) 16-bit timer mode control register 01 (tmc01) .
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 223 table 7-2. capture operation of cr010 and cr011 registers external input signal capture operation ti010 pin input ti011 pin input set values of es101 and es100 position of edge to be captured set values of es111 and es110 position of edge to be captured 01: rising 01: rising 00: falling 00: falling crc011 bit = 1 ti010 pin input (reverse phase) 11: both edges (cannot be captured) crc011 bit = 0 ti011 pin input 11: both edges capture operation of cr010 register interrupt signal inttm010 signal is not generated even if value is captured. interrupt signal inttm010 signal is generated each time value is captured. set values of es101 and es100 position of edge to be captured 01: rising 00: falling ti010 pin input note 11: both edges capture operation of cr011 register interrupt signal inttm011 signal is generated each time value is captured. note the capture operation of the cr011 register is not affected by the setting of the crc011 bit. caution to capture the count value of the tm01 regi ster to the cr010 register by using the phase reverse to that input to the ti 010 pin, the interrupt request si gnal (inttm010) is not generated after the value has been captured. if the valid edge is de tected on the ti011 pin during this operation, the capture operation is not performed but the inttm 010 signal is generated as an external interrupt signal. to not use th e external interrupt, mask the inttm010 signal. remark crc011: see 7.3 (2) capture/compare control register 01 (crc01) . es111, es110, es101, es100: see 7.3 (4) prescaler mode register 01 (prm01) .
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 224 7.3 registers registers used to control 16-bit time r/event counter 01 are shown below. ? 16-bit timer mode control register 01 (tmc01) ? capture/compare contro l register 01 (crc01) ? 16-bit timer output control register 01 (toc01) ? prescaler mode register 01 (prm01) ? selector operation control register 1 (selcnt1) remark to use the ti010, ti011, and to01 pin functions, refer to table 4-12 settings when port pins are used for alternate functions . (1) 16-bit timer mode control register 01 (tmc01) tmc01 is an 8-bit register that sets the 16-bit time r/event counter 01 operation mo de, the tm01 register clear mode, and output timing, and detects an overflow. rewriting tmc01 is prohibited during operation (when the tmc013 and tmc012 bits = other than 00). however, it can be changed when the tmc013 and tmc012 bits are cleared to 00 (stopping operation) and when the ovf01 bit is cleared to 0. this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. cautions 1. 16-bit timer/event c ounter 01 starts operation at the mo ment tmc012 and tmc013 are set to values other than 00 (operation stop mode), resp ectively. set tmc012 and tmc013 to 00 to stop the operation. 2. do not access the tmc01 re gister when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2).
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 225 after reset: 00h r/w address: fffff616h 7 6 5 4 3 2 1 <0> tmc01 0 0 0 0 tmc013 tmc012 tmc011 ovf01 tmc013 tmc012 enable operation of 16-bit timer/event counter 01 0 0 disables tm01 operation. stops suppl ying operating clock. clears 16-bit timer counter (tm01). 0 1 free-running timer mode 1 0 clear & start mode entered by ti010 pin valid edge input note 1 1 1 clear & start mode entered upon a match between tm01 and cr010 tmc011 note 2 condition to reverse timer output (to01) 0 ? match between tm01 and cr010 or match between tm01 and cr011 1 ? match between tm01 and cr010 or match between tm01 and cr011 ? trigger input of ti010 pin valid edge ovf01 tm01 register overflow flag clear (0) clears ovf01 to 0 or tmc01.tmc013 and tmc01.tmc012 = 00 set (1) overflow occurs. ovf01 is set to 1 when the value of tm01 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti010 pin valid edge input, and clear & start mode entered upon a match between tm01 and cr010). it can also be set to 1 by writing 1 to the ovf01 bit. notes 1. the ti010 pin valid edge is set by the prm01 register. 2. be sure to clear the tmc011 bit to 0 when the to01 pin and ti010 pin are used alternately.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 226 (2) capture/compare control register 01 (crc01) the crc01 register is the register that controls the operation of the cr010 and cr011 registers. changing the value of the crc01 register is prohib ited during operation (when the tmc01.tmc013 and tmc01.tmc012 bits = other than 00). this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: crc01 fffff618h 7 6 5 4 3 2 1 0 crc01 0 0 0 0 0 crc012 crc011 crc010 crc012 cr011 register operating mode selection 0 operates as compare register 1 operates as capture register crc011 cr010 register capt ure trigger selection 0 captures on valid edge of ti011 pin 1 captures on valid edge of ti010 pin by reverse phase note the valid edge of the ti011 and ti010 pin is set by the prm01 register. if prm01.es101 and prm01.es100 are set to 11 (both edges) when crc011 is 1, the valid edge of the ti010 pin cannot be detected. crc010 cr010 register operating mode selection 0 operates as compare register 1 operates as capture register if tmc013 and tmc012 are set to 11 (clear & start mode entered upon a match between tm01 and cr010), be sure to set the crc010 bit to 0. note when the valid edge is detected from the ti011 pin, the capture oper ation is not performed but the inttm010 signal is generated as an external interrupt signal. caution to ensure that the capture operation is pe rformed properly, the cap ture trigger requires a pulse two cycles longer than th e count clock selected by th e prm01 or selcnt1 register.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 227 (3) 16-bit timer output control register 01 (toc01) the toc01 register is an 8-bit register that controls the to01 pin output. the toc01 register can be rewritt en while only the ospt01 bit is oper ating (when the tmc01.tmc013 and tmc01.tmc012 bits = other than 00). rewriting t he other bits is prohibited during operation. however, toc014 can be rewritten during timer operati on as a means to rewrite the cr011 register (see 7.5.1 rewriting cr011 register during tm01 operation ). this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. caution be sure to set the toc01 regi ster using the following procedure. <1> set the toc014 and toc011 bits to 1. <2> set only the toe01 bit to 1. <3> set either the lvs01 bi t or the lvr01 bit to 1. (1/2) after reset: 00h r/w address: fffff619h 7 <6> <5> 4 <3> <2> 1 <0> toc01 0 ospt01 ospe01 toc014 lvs01 lvr01 toc011 toe01 ospt01 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always ?0? when it is read. if it is set to 1, tm01 is cleared and started. ospe01 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output if it is set to 1, tm01 is cleared and started. one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti010 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between the tm01 and cr010 registers. toc014 to01 pin output control on match between cr011 and tm01 registers 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm011) is generated even when the toc014 bit = 0.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 228 (2/2) lvs01 lvr01 setting of to01 pin output status 0 0 no change 0 1 initial value of to01 pin output is low level (to01 pin output is cleared to 0). 1 0 initial value of to01 pin output is high level (to01 pin output is set to 1). 1 1 setting prohibited ? the lvs01 and lvr01 bits can be used to set the initial value of the output level of the to01 pin. if the initial value does not have to be set, leave the lvs01 and lvr01 bits as 001. ? be sure to set the lvs01 and lvr01 bits when toe01 = 1. the lvs01, lvr01, and toe01 bits being simultaneously set to 1 is prohibited. ? the lvs01 and lvr01 bits are trigger bits. by sett ing these bits to 1, the initial value of the output level of the to01 pin can be set. even if these bits are cleared to 0, output of the to01 pin is not affected. ? the values of the lvs01 and lvr01 bits are always 0 when they are read. ? for how to set the lvs01 and lvr01 bits, see 7.5.2 setting lvs01 and lvr01 bits . toc011 to01 pin output control on match between cr010 and tm01 registers 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm010) is generated even when the toc011 bit = 0. toe01 to01 pin output control 0 disables output (to01 pin output fixed to low level) 1 enables output
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 229 (4) prescaler mode register 01 (prm01) the prm01 register is the register that sets the tm01 register count clock and ti010 and ti011 pin input valid edges. the prm011 and prm010 bits are set in combination with the selcnt1.isel11 bit. refer to 7.3 (6) count clock setting for 16-bit timer/event counter 01 for details. rewriting the prm01 register is pr ohibited during operation (when the tm c01.tmc013 and tmc01.tmc012 bits = other than 00). this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. cautions 1. do not apply the following setting when setting the prm011 and prm010 bits to 11 (to specify the valid edge of th e ti010 pin as a count clock). ? clear & start mode entered by the ti010 pin valid edge ? setting the ti010 pin as a capture trigger 2. if the operation of 16-bit timer/event counter 01 is enabled when the ti010 or ti011 pin is at high level and when the valid edge of the ti 010 or ti011 pin is specifi ed to be the rising edge or both edges, th e high level of the ti010 or ti011 pi n is detected as a rising edge. note this when the ti010 or ti011 pin is pulled up. however, the rising edge is not detected when the timer operation has been once stopped and is then enabled again. 3. when the p35 pin is used as the valid edge of ti010 and th e timer output function is used, set the p32 pin as the timer output pin (to01). es111 es110 ti011 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es101 es100 ti010 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges remark to set the prm011 and prm010 bits, refer to 7.3 (6) count clock setti ng for 16-bit timer/event counter 01 . after reset: 00h r/w address: fffff617h 7 6 5 4 3 2 1 0 prm01 es111 es110 es101 es100 0 0 prm011 prm010
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 230 (5) selector operation control register 1 (selcnt1) the selcnt1 register sets the count cl ock of 16-bit timer/event counter 01. the selcnt1 register is set in combination with th e prm01.prm101 and prm01.prm100 bits. refer to 7.3 (6) count clock setting for 16-bit timer/event counter 01 for details. this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. 0 selcnt1 0 0 0 0 0 isel11 0 after reset: 00h r/w address: fffff30ah 76 54 32 1 0 (6) count clock setting for 16-bit timer/event counter 01 the count clock for 16-bit timer/event counter 01 is set by using the prm01.pr m011, prm01.prm010, and selcnt1.isel11 bits in combination. selcnt1 register prm01 register selection of count clock note 1 isel11 bit prm011 bit prm010 bit count clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 f xx setting prohibited setting prohibited 100 ns 0 0 1 f xx /4 200 ns 250 ns 400 ns 0 1 0 intwt ? ? ? 0 1 1 valid edge of ti0101 ote 2 ? ? ? 1 0 0 f xx /2 100 ns 125 ns 200 ns 1 0 1 f xx /8 400 ns 500 ns 800 ns 1 1 0 f xx /16 800 ns 1.0 s 1.6 s 1 1 1 setting prohibited notes 1. when the internal clock is selected, set so as to satisfy the following conditions: v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse lon ger than two cycles of the internal clock (f xx /4).
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 231 7.4 operation 7.4.1 interval timer operation if the tmc01.tmc013 and tmc01.tmc012 bits are set to 11 (clear & start mode entered upon a match between the tm01 register and the cr010 register), the count operation is started in synchronization with the count clock. when the value of the tm01 register late r matches the value of the cr010 regist er, the tm01 register is cleared to 0000h and a match interrupt signal (inttm010) is generat ed. this inttm010 signal enables the tm01 register to operate as an interval timer. remarks 1. for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for enabling the inttm010 interrupt, refer to chapter 17 interrupt/exception processing function . figure 7-2. block diagram of interval timer operation 16-bit counter (tm01) cr010 register operable bits tmc013, tmc012 count clock clear match signal inttm010 signal figure 7-3. basic timing exampl e of interval timer operation tm01 register 0000h operable bits (tmc013, tmc012) compare register (cr010) compare match interrupt (inttm010) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1)
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 232 figure 7-4. example of register se ttings for interval timer operation (a) 16-bit timer mode control register 01 (tmc01) 00001100 tmc013 tmc012 tmc011 ovf01 clears and starts on match between tm01 and cr010. (b) capture/compare cont rol register 01 (crc01) 00000000 crc012 crc011 crc010 cr010 used as compare register (c) 16-bit timer output control register 01 (toc01) 00000 lvr01 lvs01 toc014 ospe01 ospt01 toc011 toe01 000 (d) prescaler mode register 01 (prm01), sel ector operation control register 1 (selcnt1) 0 prm01 0 0 0 0 prm011 prm010 selcnt1 es111 es110 es101 es100 selects count clock. 0 0/1 0/1 isel11 0/1 (e) 16-bit timer counter 01 (tm01) by reading the tm01 register, the count value can be read. (f) 16-bit capture/compare register 010 (cr010) if m is set to the cr010 register, the interval time is as follows. ? interval time = (m + 1) count clock cycle setting the cr010 register to 0000h is prohibited. (g) 16-bit capture/compare register 011 (cr011) usually, the cr011 register is not used for the interval timer function. however, a compare match interrupt (inttm011) is generated when the set value of the cr011 register matches the value of the tm01 register. therefore, mask the interrupt request by using the interrupt mask flag (tm0mk11).
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 233 figure 7-5. example of software pr ocessing for interval timer function tm01 register 0000h operable bits (tmc013, tmc012) compare register (cr010) compare match interrupt (inttm010) n 11 00 00 n n n <1> <2> tmc013, tmc012 bits = 11 tmc013, tmc012 bits = 00 register initial setting prm01 register, selcnt1 register, crc01 register, cr010 register, port setting initial setting of these registers is performed before setting the tmc013 and tmc012 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc013 and tmc012 bits to 00. start stop <1> count operation start flow <2> count operation stop flow
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 234 7.4.2 square wave output operation when 16-bit timer/event counter 01 operates as an interval timer (see 7.4.1 ), a square wave can be output from the to01 pin by setting the toc01 register to 03h. when the tmc01.tmc013 and tmc01.tmc012 bits are set to 11 (count clear & start mode entered upon a match between the tm01 register and the cr010 register), the c ounting operation is started in synchronization with the count clock. when the value of the tm01 register late r matches the value of the cr010 regist er, the tm01 register is cleared to 0000h, an interrupt signal (inttm010) is generated, and output of the to01 pin is invert ed. this to01 pin output that is inverted at fixed interval s enables to01 to output a square wave. remarks 1. for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for enabling the inttm010 interrupt, refer to chapter 17 interrupt/exception processing function . figure 7-6. block diagram of square wave output operation 16-bit counter (tm01) cr010 register operable bits tmc013, tmc012 count clock clear match signal inttm010 signal output controller to01 pin figure 7-7. basic timing example of square wave output operation tm01 register 0000h operable bits (tmc013, tmc012) compare register (cr010) to01 pin output compare match interrupt (inttm010) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1)
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 235 figure 7-8. example of register setti ngs for square wave output operation (a) 16-bit timer mode control register 01 (tmc01) 00001100 tmc013 tmc012 tmc011 ovf01 clears and starts on match between tm01 and cr010. (b) capture/compare cont rol register 01 (crc01) 00000000 crc012 crc011 crc010 cr010 used as compare register (c) 16-bit timer output control register 01 (toc01) 0 0 0 0 0/1 lvr01 lvs01 toc014 ospe01 ospt01 toc011 toe01 enables to01 pin output. inverts to01 pin output on match between tm01 and cr010. specifies the initial value of to01 output f/f. 0/1 1 1 (d) prescaler mode register 01 (prm01), sel ector operation control register 1 (selcnt1) 0 prm01 0 0 0 0 prm011 prm010 selcnt1 es111 es110 es101 es100 selects count clock. 0 0/1 0/1 isel11 0/1 (e) 16-bit timer counter 01 (tm01) by reading the tm01 register, the count value can be read. (f) 16-bit capture/compare register 010 (cr010) if m is set to the cr010 register, the square wave frequency is as follows. 1 / [2 (m + 1) count clock cycle] setting the cr010 register to 0000h is prohibited. (g) 16-bit capture/compare register 011 (cr011) usually, the cr011 register is not used for the square wave output func tion. however, a compare match interrupt (inttm011) is generated when the set val ue of the cr011 register ma tches the value of the tm01 register. therefore, mask the interrupt request by using the interrupt mask flag (tm0mk11).
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 236 figure 7-9. example of software proc essing for square wave output function tm01 register 0000h operable bits (tmc013, tmc012) compare register (cr010) to01 pin output compare match interrupt (inttm010) to01 output control bit (toc011, toe01) n 11 00 00 n n n <1> <2> tmc013, tmc012 bits = 11 tmc013, tmc012 bits = 00 register initial setting prm01 register, selcnt1 register, crc01 register, toc01 register note , cr010 register, port setting initial setting of these registers is performed before setting the tmc013 and tmc012 bits to 11. starts count operation. the counter is initialized and counting is stopped by clearing the tmc013 and tmc012 bits to 00. start stop <1> count operation start flow <2> count operation stop flow note care must be exercised when setting the toc01 register. for details, see 7.3 (3) 16-bit timer output control register 01 (toc01) .
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 237 7.4.3 external event counter operation when the prm01.prm011 and prm01.prm010 bits are set to 11 (for counting up with the valid edge of the ti010 pin) and the tmc01.tmc013 and tmc01.tm c012 bits are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matc hing between the tm01 register and the cr010 register (inttm010) is generated. to input the external event, the ti010 pin is used. th erefore, the timer/event co unter cannot be used as an external event counter in the clear & start mode entered by the ti010 pin va lid edge input (when the tmc013 and tmc012 bits = 10). the inttm010 signal is generated with the following timing. ? timing of generation of inttm010 signal (second time or later) = number of times of detection of valid edge of external event (set value of the cr010 register + 1) however, the first match interrupt immediately after the timer/event counter has start ed operating is generated with the following timing. ? number of times of detection of valid edge of external event input (set value of the cr010 register + 2) to detect the valid edge, the signal input to t he ti010 pin is sampled during the clock cycle of f prs . the valid edge is not detected until it is detected two times in a row. t herefore, a noise with a short pul se width can be eliminated. remarks 1. for the alternate-function pin (ti010) settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for enabling the inttm010 interrupt, refer to chapter 17 interrupt/exception processing function . figure 7-10. block diagram of ex ternal event counter operation 16-bit counter (tm01) cr010 register operable bits tmc013, tmc012 clear match signal inttm010 signal f xx /4 edge detection ti010 pin output controller to01 pin
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 238 figure 7-11. example of register setti ngs in external event counter mode (a) 16-bit timer mode control register 01 (tmc01) 00001100 tmc013 tmc012 tmc011 ovf01 clears and starts on match between tm01 and cr010. (b) capture/compare cont rol register 01 (crc01) 00000000 crc012 crc011 crc010 cr010 used as compare register (c) 16-bit timer output control register 01 (toc01) 0 0 0 0/1 0/1 lvr01 lvs01 toc014 ospe01 ospt01 toc011 toe01 0: disables to01 output. 1: enables to01 output. 00: does not invert to01 output on match between tm01 and cr010/cr011. 01: inverts to01 output on match between tm01 and cr010. 10: inverts to01 output on match between tm01 and cr011. 11: inverts to01 output on match between tm01 and cr010/cr011. specifies initial value of to01 output f/f. 0/1 0/1 0/1 (d) prescaler mode register 01 (prm01), sel ector operation control register 1 (selcnt1) 0 prm01 0 0/1 0/1 0 prm011 prm010 isel11 es111 es110 es101 es100 selects count clock (specifies valid edge of ti010). 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 00 1 1 selcnt1 (e) 16-bit timer counter 01 (tm01) by reading the tm01 register, the count value can be read. (f) 16-bit capture/compare register 010 (cr010) if m is set to the cr010 register, the interrupt signal (inttm010) is generated when the number of external events reaches (m + 1). setting the cr010 register to 0000h is prohibited. (g) 16-bit capture/compare register 011 (cr011) when this register?s value matches the count value of the tm01 register, an interrupt signal (inttm011) is generated. the count value of t he tm01 register is not cleared.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 239 figure 7-12. example of software proce ssing in external event counter mode compare register (cr010) operable bits (tmc013, tmc012) 0000h tm01 register to01 pin output compare match interrupt (inttm010) to01 output control bit (toc014, toc011, toe01) tmc013, tmc012 bits = 11 tmc013, tmc012 bits = 00 register initial setting prm01 register, selcnt1 register, crc01 register, toc01 register note , cr010 register, port setting initial setting of these registers is performed before setting the tmc013 and tmc012 bits to 11. starts count operation. the counter is initialized and counting is stopped by clearing the tmc013 and tmc012 bits to 00. start stop <1> count operation start flow <2> count operation stop flow 11 00 n n n n 00 <1> <2> note care must be exercised when setting the toc01 register. for details, see 7.3 (3) 16-bit timer output control register 01 (toc01) .
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 240 7.4.4 operation in clear & start mode entered by ti010 pin valid edge input when the tmc01.tmc013 and tmc01.tmc012 bits are set to 10 (clear & start mode entered by the ti010 pin valid edge input) and the count clock (set by the prm01, selcnt1 registers) is supplied to the timer/event counter, the tm01 register starts counting up. when the valid edge of the ti010 pin is detected du ring the counting operation, the tm01 register is cleared to 0000h and starts counting up again. if the valid edge of the ti010 pin is not detected, the tm01 register overflow s and continues counting. the valid edge of the ti010 pin is a cause to clear th e tm01 register. starting t he counter is not controlled immediately after the st art of the operation. the cr010 and cr011 registers are used as compare registers and capture registers. (a) when the cr010 and cr011 register s are used as compare registers signals inttm010 and inttm011 are generated when the va lue of the tm01 register matches the value of the cr010 and cr011 registers. (b) when the cr010 and cr011 register s are used as capture registers the count value of the tm01 register is captur ed to the cr010 register and the inttm010 signal is generated when the valid edge is input to the ti011 pin (or when the pha se reverse to that of the valid edge is input to the ti010 pin). when the valid edge is input to the ti010 pin, the count va lue of the tm01 register is captured to the cr011 register and the inttm011 signal is generated. as s oon as the count value has been captured, the counter is cleared to 0000h. caution do not set the count clock as the va lid edge of the ti010 pin (rpm01.prm011 and rpm01.prm010 bits = 11). when the prm011 a nd prm010 bits = 11, the tm01 register is cleared. remarks 1. for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for enabling the inttm010 interrupt, refer to chapter 17 interrupt/exception processing function .
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 241 (1) operation in clear & start mode en tered by ti010 pin valid edge input (cr010 register: compare register , cr011 register: compare register) figure 7-13. block diagram of clear & start mode entered by ti010 pin valid edge input (cr010 register: compare register , cr011 register: compare register) 16-bit counter (tm01) clear output controller edge detection compare register (cr011) match signal to01 pin match signal interrupt signal (inttm010) interrupt signal (inttm011) ti010 pin compare register (cr010) operable bits tmc013, tmc012 count clock
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 242 figure 7-14. timing example of clear & star t mode entered by ti010 pin valid edge input (cr010 register: compare regist er, cr011 register: compare register) (a) toc01 = 13h, prm01 = 10h, crc01 = 00h, tmc01 = 08h tm01 register 0000h operable bits (tmc013, tmc012) count clear input (ti010 pin input) compare register (cr010) compare match interrupt (inttm010) compare register (cr011) compare match interrupt (inttm011) to01 pin output m 10 m nn nn mmm 00 n (b) toc01 = 13h, prm01 = 10h, crc01, = 00h, tmc01 = 0ah tm01 register 0000h operable bits (tmc013, tmc012) count clear input (ti010 pin input) compare register (cr010) compare match interrupt (inttm010) compare register (cr011) compare match interrupt (inttm011) to01 pin output m 10 m nn nn mmm 00 n (a) and (b) differ as follows depending on the setting of the tmc01 register (tmc011 bit). (a) the output level of the to01 pi n is inverted when the tm01 register matches a compare register. (b) the output level of the to01 pin is inverted w hen the tm01 register matches a compare register or when the valid edge of the ti010 pin is detected.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 243 (2) operation in clear & start mode en tered by ti010 pin valid edge input (cr010 register: compare register , cr011 register: capture register) figure 7-15. block diagram of clear & start mode entered by ti010 pin valid edge input (cr010 register: compare register , cr011 register: capture register) 16-bit counter (tm01) clear output controller edge detector capture register (cr011) capture signal to01 pin match signal interrupt signal (inttm010) interrupt signal (inttm011) ti010 pin compare register (cr010) operable bits tmc013, tmc012 count clock
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 244 figure 7-16. timing example of clear & star t mode entered by ti010 pin valid edge input (cr010 register: compare register, cr011 register: capture register) (1/2) (a) toc01 = 13h, prm01 = 10h, crc01, = 04h, tmc01 = 08h, cr010 = 0000h tm01 register 0000h operable bits (tmc013, tmc012) capture & count clear input (ti010 pin input) compare register (cr010) compare match interrupt (inttm010) capture register (cr011) capture interrupt (inttm011) to01 pin output 0000h 10 q p n m s 00 0000h m n s p q this is an application example where the output level of t he to01 pin is inverted when the count value has been captured & cleared. the count value is captured to the cr011 register and the tm01 regist er is cleared (to 0000h) when the valid edge of the ti010 pin is det ected. when the count va lue of the tm01 register is 0000h, a compare match interrupt signal (inttm010) is generated, and t he output level of the to01 pin is inverted.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 245 figure 7-16. timing example of clear & star t mode entered by ti010 pin valid edge input (cr010 register: compare register, cr011 register: capture register) (2/2) (b) toc01 = 13h, prm01 = 10h, crc01 = 04h, tmc01 = 0ah, cr010 = 0003h tm01 register 0000h operable bits (tmc013, tmc012) capture & count clear input (ti010 pin input) compare register (cr010) compare match interrupt (inttm010) capture register (cr011) capture interrupt (inttm011) to01 pin output 0003h 0003h 10 q p n m s 00 0000h m 4444 ns pq this is an application exampl e where the width set to the cr010 register (4 clocks in this example) is to be output from the to01 pin when the count value has been captured & cleared. the count value is captured to t he cr011 register, a capture interrupt signal (inttm011) is generated, the tm01 register is cleared (to 0000h), and the output level of the to01 pin is inverted when the valid edge of the ti010 pin is detected. when the count value of the tm01 register is 0003h (four clocks have been counted), a compare match interrupt signal (inttm010) is generat ed and the output level of the to01 pin is inverted.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 246 (3) operation in clear & start mode en tered by ti010 pin valid edge input (cr010 register: capture register , cr011 register: compare register) figure 7-17. block diagram of clear & start mode entered by ti010 pin valid edge input (cr010 register: capture register, cr011 register: compare register) 16-bit counter (tm01) clear output controller edge detection capture register (cr010) capture signal to01 pin match signal interrupt signal (inttm011) interrupt signal (inttm010) ti010 pin compare register (cr011) operable bits tmc013, tmc012 count clock
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 247 figure 7-18. timing example of clear & start mode entered by ti010 pin valid edge input (cr010 register: capture register, cr011 register: compare register) (1/2) (a) toc01 = 13h, prm01 = 10h, crc01 = 03h, tmc01 = 08h, cr011 = 0000h 10 p n m s 00 l 0000h 0000h mns p tm01 register 0000h operable bits (tmc013, tmc012) capture & count clear input (ti010 pin input) capture register (cr010) capture interrupt (inttm010) compare register (cr011) compare match interrupt (inttm011) to01 pin output this is an application example where the output level of the to01 pin is to be inverted when the count value has been captured & cleared. the tm01 register is cleared at the rising edge detecti on of the ti010 pin and it is captured to the cr010 register at the falling edge detection of the ti010 pin. when the crc01.crc011 bit is set to 1, the count valu e of the tm01 register is captured to cr010 in the phase reverse to that of the signal input to the ti010 pi n, but the capture interrupt signal (inttm010) is not generated. however, the inttm010 signal is generated when the valid edge of the ti011 pin is detected. mask the inttm010 signal when it is not used.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 248 figure 7-18. timing example of clear & star t mode entered by ti010 pin valid edge input (cr010 register: capture register, cr011 register: compare register) (2/2) (b) toc01 = 13h, prm01 = 10h, crc01 = 03h, tmc01 = 0ah, cr011 = 0003h tm01 register 0000h operable bits (tmc013, tmc012) capture & count clear input (ti010 pin input) compare register (cr010) compare match interrupt (inttm010) capture register (cr011) capture interrupt (inttm011) to01 pin output 0003h 0003h 10 p n m s 00 4444 l 0000h m n s p this is an application exampl e where the width set to the cr011 register (4 clocks in this example) is to be output from the to01 pin when the count value has been captured & cleared. the tm01 register is cleared (to 0000h) at the rising edge detection of the ti 010 pin and captured to the cr010 register at the falling edge detec tion of the ti010 pin. the output level of the to01 pin is inverted when the tm01 register is cleared (to 0000h) because the rising edge of the ti 010 pin has been detected or when the value of the tm01 register matches that of a compare register (cr011). when the crc01.crc011 bit is 1, the count value of the tm01 register is captured to the cr010 register in the phase reverse to that of the input signal of the ti010 pin, but the captur e interrupt signal (inttm010) is not generated. however, the inttm010 inte rrupt is generated when the valid edg e of the ti011 pin is detected. mask the inttm010 signal when it is not used.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 249 (4) operation in clear & start mode en tered by ti010 pin valid edge input (cr010 register: capture register , cr011 register: capture register) figure 7-19. block diagram of clear & start mode entered by ti010 pin valid edge input (cr010 register: capture register, cr011 register: capture register) 16-bit counter (tm01) clear output controller capture register (cr010) capture signal capture signal to01 pin interrupt signal (inttm011) interrupt signal (inttm010) capture register (cr011) operable bits tmc013, tmc012 count clock edge detection ti010 pin edge detection ti011 pin selector
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 250 figure 7-20. timing example of clear & start mode entered by ti010 pin valid edge input (cr010 register: capture register, cr011 register: capture register) (1/3) (a) toc01 = 13h, prm01 = 30h, crc01 = 05h, tmc01 = 0ah tm01 register 0000h operable bits (tmc013, tmc012) capture & count clear input (ti010 pin input) capture register (cr010) capture interrupt (inttm010) capture register (cr011) capture interrupt (inttm011) to01 pin output 10 r s t o l m n p q 00 l 0000h 0000h lm nopqrst this is an application example where t he count value is captured to the cr0 11 register, the tm01 register is cleared, and the to01 pin output is inverted when the rising or falling edge of t he ti010 pin is detected. when the edge of the ti011 pin is det ected, an interrupt signal (inttm 010) is generated. mask the inttm010 signal when it is not used.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 251 figure 7-20. timing example of clear & start mode entered by ti010 pin valid edge input (cr010 register: capture register, cr011 register: capture register) (2/3) (b) toc01 = 13h, prm01 = c0h, crc01 = 05h, tmc01 = 0ah tm01 register 0000h operable bits (tmc013, tmc012) capture trigger input (ti011 pin input) capture register (cr010) capture interrupt (inttm010) capture & count clear input (ti010) capture register (cr011) capture interrupt (inttm011) to01 pin output 10 r s t o l m n p q 00 ffffh l l l 0000h 0000h lmn o pq r s t this is a timing example where an edge is not input to t he ti010 pin, in an application where the count value is captured to the cr010 register when the rising or falling edge of the ti011 pin is detected. because the to010 pin does not detect any edges, the to01 pin output is not inverted and remains low level.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 252 figure 7-20. timing example of clear & start mode entered by ti010 pin valid edge input (cr010 register: capture register, cr011 register: capture register) (3/3) (c) toc01 = 13h, prm01 = 00h, crc01 = 07h, tmc01 = 0ah tm01 register 0000h operable bits (tmc013, tmc012) capture & count clear input (ti010 pin input) capture register (cr010) capture register (cr011) capture interrupt (inttm011) to01 pin output capture input (ti011) capture interrupt (inttm010) 0000h 10 p o m q r t s w n l 00 l l ln r pt 0000h moq sw this is an application example where the pulse width of the signal input to the ti010 pin is measured. by setting the crc01 register, the count value can be ca ptured to the cr010 register in the phase reverse to the falling edge of the ti010 pin (i.e., rising edge) and to the cr011 register at the falling edge of the ti010 pin. the high- and low-level widths of the input pulse can be calculated by the following expressions. ? high-level width = [cr011 register value] ? [cr010 register value] [count clock cycle] ? low-level width = [cr010 register value] [count clock cycle] if the reverse phase of the ti010 pin is selected as a trigger to capture the count value to the cr010 register, the inttm010 signal is not generated. read the val ues of the cr010 and cr011 registers to measure the pulse width immediately after the inttm011 signal is generated. however, if the valid edge specifi ed by the prm01.es111 and prm01.es110 bi ts is input to the ti011 pin, the count value is not captured but the inttm010 signal is ge nerated. to measure the pulse width of the ti010 pin, mask the inttm010 signal when it is not used.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 253 figure 7-21. example of register settings in clear & st art mode entered by ti010 pin valid edge input (1/2) (a) 16-bit timer mode control register 01 (tmc01) 0000100/10 tmc013 tmc012 tmc011 ovf01 clears and starts at valid edge input of ti010 pin. 0: inverts to01 output on match between cr010 and cr011. 1: inverts to01 output on match between cr010 and cr011 and valid edge of ti010 pin. (b) capture/compare cont rol register 01 (crc01) 000000/10/10/1 crc012 crc011 crc010 0: cr010 used as compare register 1: cr010 used as capture register 0: cr011 used as compare register 1: cr011 used as capture register 0: ti011 pin is used as capture trigger of cr010. 1: reverse phase of ti010 pin is used as capture trigger of cr010. (c) 16-bit timer output control register 01 (toc01) 0 0 0 0/1 0/1 lvr01 lvs01 toc014 ospe01 ospt01 toc011 toe01 0: disables to01 output 1: enables to01 output 00: does not invert to01 output on match between tm01 and cr010/cr011. 01: inverts to01 output on match between tm01 and cr010. 10: inverts to01 output on match between tm01 and cr011. 11: inverts to01 output on match between tm01 and cr010/cr011. specifies initial value of to01 output f/f 0/1 0/1 0/1
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 254 figure 7-21. example of register settings in clear & st art mode entered by ti010 pin valid edge input (2/2) (d) prescaler mode register 01 (prm01), sel ector operation control register 1 (selcnt1) 0/1 prm01 0/1 0/1 0/1 0 prm011 prm010 es111 es110 es101 es100 count clock selection (setting ti010 valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc011 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 selcnt1 isel11 0/1 (e) 16-bit timer counter 01 (tm01) by reading the tm01 register, the count value can be read. (f) 16-bit capture/compare register 010 (cr010) when this register is used as a co mpare register and when its value ma tches the count value of the tm01 register, an interrupt signal (inttm010) is generated. the count value of the tm01 register is not cleared. to use this register as a capture register, select eit her the ti010 or ti011 pin input as a capture trigger. when the valid edge of the capt ure trigger is detected, t he count value of the tm01 r egister is stored in the cr010 register. (g) 16-bit capture/compare register 011 (cr011) when this register is used as a co mpare register and when its value ma tches the count value of the tm01 register, an interrupt signal (inttm011) is generated. the count value of the tm01 register is not cleared. when this register is used as a capt ure register, the ti010 pin input is us ed as a capture trigger. when the valid edge of the capture trigger is detected, the count value of the tm01 register is stored in the cr011 register.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 255 figure 7-22. example of software processing in clear & start mode entered by ti010 pin valid edge input tm01 register 0000h operable bits (tmc013, tmc012) count clear input (ti010 pin input) compare register (cr010) compare match interrupt (inttm010) compare register (cr011) compare match interrupt (inttm011) to01 pin output m 10 m n n n n mmm 00 <1> <2> <2> <2> <3> <2> 00 n tmc013, tmc012 bits = 10 edge input to ti010 pin register initial setting prm01 register, selcnt1 register, crc01 register, toc01 register note , cr010, cr011 registers, tmc01.tmc011 bit, port setting initial setting of these registers is performed before setting the tmc013 and tmc012 bits to 10. starts count operation when the valid edge is input to the ti010 pin, the value of the tm01 register is cleared. start <1> count operation start flow <2> tm01 register clear & start flow tmc013, tmc012 bits = 00 the counter is initialized and counting is stopped by clearing the tmc013 and tmc012 bits to 00. stop <3> count operation stop flow note care must be exercised when setting the toc01 register. for details, see 7.3 (3) 16-bit timer output control register 01 (toc01) .
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 256 7.4.5 free-running timer operation when the tmc01.tmc013 and tmc01.tmc012 bits are set to 01 (free-running timer mode), 16-bit timer/event counter 01 continues counting up in synchronization with t he count clock. when it has counted up to ffffh, the overflow flag (tmc01.ovf01 bit) is set to 1 at the nex t clock, and the tm01 register is cleared (to 0000h) and continues counting. clear the ovf01 bit to 0 by executing the clr instruction via software. the following three types of free-runn ing timer operations are available. ? both the cr010 and cr011 register s are used as compare registers. ? either the cr010 register or cr011 register is used as a compare register and the other is used as a capture register. ? both the cr010 and cr011 register s are used as capture registers. remarks 1. for the alternate-function pin (to01) settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for enabling the inttm010 and inttm011 interrupts, refer to chapter 17 interrupt/exception processing function . (1) free-running timer mode operation (cr010 register: compare register , cr011 register: compare register) figure 7-23. block diagram of free-running timer mode (cr010 register: compare register , cr011 register: compare register) 16-bit counter (tm01) output controller compare register (cr011) match signal to01 pin match signal interrupt signal (inttm010) interrupt signal (inttm011) compare register (cr010) operable bits tmc013, tmc012 count clock
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 257 figure 7-24. timing example of free-running timer mode (cr010 register: compare register , cr011 register: compare register) ? toc01 = 13h, prm01 = 00h, crc01 = 00h, tmc01 = 04h ffffh tm01 register 0000h operable bits (tmc013, tmc012) compare register (cr010) compare match interrupt (inttm010) compare register (cr011) compare match interrupt (inttm011) to01 pin output overflow flag (ovf01) 01 m n m n m n m n 00 00 n 0 write clear 0 write clear 0 write clear 0 write clear m this is an application example where two compare registers are used in the free-running timer mode. the output level of the to01 pin is reversed each time the count value of the tm01 register matches the set values of the cr010 and cr011 register s. when the count value matches t he register value, the inttm010 or inttm011 signal is generated. (2) free-running timer mode operation (cr010 register: compare register , cr011 register: capture register) figure 7-25. block diagram of free-running timer mode (cr010 register: compare register , cr011 register: capture register) 16-bit counter (tm01) output controller edge detection capture register (cr011) capture signal to01 pin match signal interrupt signal (inttm010) interrupt signal (inttm011) ti010 pin compare register (cr010) operable bits tmc013, tmc012 count clock
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 258 figure 7-26. timing example of free-running timer mode (cr010 register: compare register , cr011 register: capture register) ? toc01 = 13h, prm01 = 10h, crc01 = 04h, tmc01 = 04h 01 m n s p q 00 0000h 0000h mn s p q ffffh tm01 register 0000h operable bits (tmc013, tmc012) capture trigger input (ti010) compare register (cr010) compare match interrupt (inttm010) compare register (cr011) capture interrupt (inttm011) to01 pin output overflow flag (ovf01) 0 write clear 0 write clear 0 write clear 0 write clear this is an application example where a compare register a nd a capture register are used at the same time in the free-running timer mode. in this example, the inttm010 signal is generated and th e output level of the to01 pin is reversed each time the count value of the tm01 register matches the set value of the cr010 register (compare register). in addition, the inttm011 signal is generated and the count va lue of the tm01 register is captured to the cr011 register each time the valid ed ge of the ti010 pin is detected.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 259 (3) free-running timer mode operation (cr010 register: capture register , cr011 register: capture register) figure 7-27. block diagram of free-running timer mode (cr010 register: capture register, cr011 register: capture register) 16-bit counter (tm01) capture register (cr010) capture signal capture signal interrupt signal (inttm011) interrupt signal (inttm010) capture register (cr011) operable bits tmc013, tmc012 count clock edge detection ti010 pin edge detection ti011 pin selector remark if both the cr010 and cr011 registers are used as c apture registers in the free-running timer mode, the output level of the to 01 pin is not inverted. however, it can be inverted each time the va lid edge of the ti010 pin is detected if the tmc01.tmc011 bit is set to 1.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 260 figure 7-28. timing example of free-running timer mode (cr010 register: capture register, cr 011 register: capture register) (1/2) (a) toc01 = 13h, prm01 = 0 to 50h, crc01 = 05h, tmc01 = 04h 01 m a b c de n s p q 00 0000h abc d e 0000h mn s p q ffffh tm01 register 0000h operable bits (tmc013, tmc012) capture trigger input (ti010) capture register (cr011) capture interrupt (inttm011) capture trigger input (ti011) capture register (cr010) capture interrupt (inttm010) overflow flag (ovf01) 0 write clear 0 write clear 0 write clear 0 write clear this is an application example where the count values that have been captured at t he valid edges of separate capture trigger signals are stor ed in separate capture registers in the free-running timer mode. the count value is captured to the cr011 register when the valid ed ge of the ti010 pin input is detected and to the cr010 register when the valid edge of the ti011 pin input is detected.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 261 figure 7-28. timing example of free-running timer mode (cr010 register: capture register, cr 011 register: capture register) (2/2) (b) toc01 = 13h, prm01 = c0h, crc01 = 05h, tmc01 = 04h ffffh tm01 register 0000h operable bits (tmc013, tmc012) capture trigger input (ti011) capture register (cr010) capture interrupt (inttm010) capture trigger input (ti010) capture register (cr011) capture interrupt (inttm011) 01 l m p s n o r q t 00 0000h 0000h lmn o pq r s t l l this is an application example where both the edges of the ti011 pin are detect ed and the count value is captured to the cr010 register in the free-running timer mode. when both the cr010 and cr011 registers are used as capt ure registers and when the valid edge of only the ti011 pin is to be detected, the count val ue cannot be captured to the cr011 register.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 262 figure 7-29. example of register setti ngs in free-running timer mode (1/2) (a) 16-bit timer mode control register 01 (tmc01) 0000010/10 tmc013 tmc012 tmc011 ovf01 free-running timer mode 0: inverts to01 pin output on match between cr010 and cr011. 1: inverts to01 pin output on match between cr010 and cr011 and valid edge of ti010 pin. (b) capture/compare cont rol register 01 (crc01) 000000/10/10/1 crc012 crc011 crc010 0: cr010 used as compare register 1: cr010 used as capture register 0: cr011 used as compare register 1: cr011 used as capture register 0: ti011 pin is used as capture trigger of cr010. 1: reverse phase of ti010 pin is used as capture trigger of cr010. (c) 16-bit timer output control register 01 (toc01) 0 0 0 0/1 0/1 lvr01 lvs01 toc014 ospe01 ospt01 toc011 toe01 0: disables to01 output 1: enables to01 output 00: does not invert to01 output on match between tm01 and cr010/cr011. 01: inverts to01 output on match between tm01 and cr010. 10: inverts to01 output on match between tm01 and cr011. 11: inverts to01 output on match between tm01 and cr010/cr011. specifies initial value of to01 output f/f 0/1 0/1 0/1
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 263 figure 7-29. example of register setti ngs in free-running timer mode (2/2) (d) prescaler mode register 01 (prm01), sel ector operation control register 1 (selcnt1) 0/1 prm01 0/1 0/1 0/1 0 prm011 prm010 es111 es110 es101 es100 count clock selection (setting ti010 valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc011 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0 0/1 0/1 selcnt1 isel11 0/1 (e) 16-bit timer counter 01 (tm01) by reading the tm01 register, the count value can be read. (f) 16-bit capture/compare register 010 (cr010) when this register is used as a co mpare register and when its value ma tches the count value of the tm01 register, an interrupt signal (inttm010) is generated. the count value of the tm01 register is not cleared. to use this register as a capture register, select eit her the ti010 or ti011 pin input as a capture trigger. when the valid edge of the capt ure trigger is detected, t he count value of the tm01 r egister is stored in the cr010 register. (g) 16-bit capture/compare register 011 (cr011) when this register is used as a co mpare register and when its value ma tches the count value of the tm01 register, an interrupt signal (inttm011) is generated. the count value of the tm01 register is not cleared. when this register is used as a capt ure register, the ti010 pin input is us ed as a capture trigger. when the valid edge of the capture trigger is detected, the count value of the tm01 register is stored in the cr011 register.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 264 figure 7-30. example of software pr ocessing in free-running timer mode ffffh tm01 register 0000h operable bits (tmc013, tmc012) compare register (cr010) compare match interrupt (inttm010) compare register (cr011) compare match interrupt (inttm011) timer output control bits (toe01, toc014, toc011) to01 pin output m 01 n n n n m m m 00 <1> <2> 00 n tmc013, tmc012 bits = 0, 1 register initial setting prm01 register, selcnt1 register, crc01 register, toc01 register note , cr010/cr011 register, tmc01.tmc011 bit, port setting initial setting of these registers is performed before setting the tmc013 and tmc012 bits to 01. starts count operation start <1> count operation start flow tmc013, tmc012 bits = 0, 0 the counter is initialized and counting is stopped by clearing the tmc013 and tmc012 bits to 00. stop <2> count operation stop flow note care must be exercised when setting the toc01 register. for details, see 7.3 (3) 16-bit timer output control register 01 (toc01) .
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 265 7.4.6 ppg output operation a rectangular wave having a pulse width set in advance by the cr011 register is out put from the to01 pin as a ppg (programmable pulse generator) signal during a cycle set by the cr010 register when the tmc01.tmc013 and tmc01.tmc012 bits are set to 11 (clear & start upon a ma tch between the tm01 register and the cr010 register). the pulse cycle and duty factor of the pulse generated as the ppg output are as follows. ? pulse cycle = (set value of the cr010 register + 1) count clock cycle ? duty = (set value of the cr011 register + 1)/(set value of the cr010 register + 1) caution to change the duty factor (value of the cr0 11 register) during operation, see 7.5.1 rewriting cr011 register during tm01 operation. remarks 1. for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for enabling the inttm010 and inttm011 interrupts, refer to chapter 17 interrupt/ exception processing function . figure 7-31. block diagram of ppg output operation 16-bit counter (tm01) clear output controller compare register (cr011) match signal to01 pin match signal interrupt signal (inttm010) interrupt signal (inttm011) compare register (cr010) operable bits tmc013, tmc012 count clock
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 266 figure 7-32. example of register settings for ppg output operation (a) 16-bit timer mode control register 01 (tmc01) 00001100 tmc013 tmc012 tmc011 ovf01 clears and starts on match between tm01 and cr010. (b) capture/compare cont rol register 01 (crc01) 00000000 crc012 crc011 crc010 cr010 used as compare register cr011 used as compare register (c) 16-bit timer output control register 01 (toc01) 0 0 0 1 0/1 lvr01 lvs01 toc014 ospe01 ospt01 toc011 toe01 enables to01 output 11: inverts to01 output on match between tm01 and cr010/cr011. 00: disables one-shot pulse output specifies initial value of to01 output f/f 0/1 1 1 (d) prescaler mode register 01 (prm01), sel ector operation control register 1 (selcnt1) 0 prm01 0 0 0 0 prm011 prm010 isel11 es111 es110 es101 es100 selects count clock 0 0/1 0/1 0/1 selcnt1 (e) 16-bit timer counter 01 (tm01) by reading the tm01 register, the count value can be read. (f) 16-bit capture/compare register 010 (cr010) an interrupt signal (inttm010) is generated when the valu e of this register matches the count value of the tm01 register. (g) 16-bit capture/compare register 011 (cr011) an interrupt signal (inttm011) is generated when the valu e of this register matches the count value of the tm01 register. caution set values to the cr010 and cr011 registers such that the condition 0000h cr011 < cr010 ffffh is satisfied.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 267 figure 7-33. example of software pr ocessing for ppg output operation tm01 register 0000h operable bits (tmc013, tmc012) compare register (cr010) compare match interrupt (inttm010) compare register (cr011) compare match interrupt (inttm011) timer output control bits (toe01, toc014, toc011) to01 pin output m 11 m m m n n n 00 <1> n + 1 <2> 00 n tmc013, tmc012 bits = 11 register initial setting prm01 register, selcnt1 register, crc01 register, toc01 register note , cr010, cr011 registers, port setting initial setting of these registers is performed before setting the tmc013 and tmc012 bits. starts count operation start <1> count operation start flow tmc013, tmc012 bits = 00 the counter is initialized and counting is stopped by clearing the tmc013 and tmc012 bits to 00. stop <2> count operation stop flow n + 1 n + 1 m + 1 m + 1 m + 1 note care must be exercised when setting the toc01 register. for details, see 7.3 (3) 16-bit timer output control register 01 (toc01) . remark ppg pulse cycle = (m + 1) count clock cycle ppg duty = (n + 1)/(m + 1)
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 268 7.4.7 one-shot pulse output operation a one-shot pulse can be output by setting the tmc01.tm c013 and tmc01.tmc012 bits to 01 (free-running timer mode) or to 10 (clear & start mode entered by the ti010 pin valid edge) and setting the toc01.ospe01 bit to 1. when the toc01.ospt01 is set to 1 or when the valid edge is input to the ti010 pin during timer operation, clearing & starting of the tm01 register is triggered, and a pulse of the di fference between the values of the cr010 and cr011 registers is output onl y once from the to01 pin. caution do not input the trigger agai n (setting ospt01 to 1 or detecti ng the valid edge of the ti010 pin) while the one-shot pulse is output. to output th e one-shot pulse again, gene rate the trigger after the current one-shot pulse output has completed. remarks 1. for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for enabling the inttm010 and inttm011 interrupts, refer to chapter 17 interrupt/ exception processing function . figure 7-34. block diagram of on e-shot pulse output operation 16-bit counter (tm01) output controller compare register (cr011) match signal to01 pin match signal interrupt signal (inttm010) interrupt signal (inttm011) compare register (cr010) operable bits tmc013, tmc012 count clock ti010 edge detection ospt01 bit ospe01 bit clear
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 269 figure 7-35. example of register settings for one-shot pulse output operation (1/2) (a) 16-bit timer mode control register 01 (tmc01) 00000/10/100 tmc013 tmc012 tmc011 ovf01 01: free running timer mode 10: clear and start mode by valid edge of ti010 pin. (b) capture/compare cont rol register 01 (crc01) 00000000 crc012 crc011 crc010 cr010 used as compare register cr011 used as compare register (c) 16-bit timer output control register 01 (toc01) 0 0/1 1 1 0/1 lvr01 lvs01 toc014 ospe01 ospt01 toc011 toe01 enables to01 pin output inverts to01 output on match between tm01 and cr010/cr011. specifies initial value of to01 pin output enables one-shot pulse output software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it). 0/1 1 1 (d) prescaler mode register 01 (prm01), sel ector operation control register 1 (selcnt1) 0 prm01 0 0 0 0 prm011 prm010 isel11 es111 es110 es101 es100 selects count clock 0 0/1 0/1 0/1 selcnt1
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 270 figure 7-35. example of register settings for one-shot pulse output operation (2/2) (e) 16-bit timer counter 01 (tm01) by reading the tm01 register, the count value can be read. (f) 16-bit capture/compare register 010 (cr010) this register is used as a compare register when a one-shot pulse is output. when the value of the tm01 register matches that of the cr0 10 register, an interrupt signal (i nttm010) is generated and the output level of the to01 pin is inverted. (g) 16-bit capture/compare register 011 (cr011) this register is used as a compare register when a one-shot pulse is output. when the value of the tm01 register matches that of the cr0 11 register, an interrupt signal (i nttm011) is generated and the output level of the to01 pin is inverted.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 271 figure 7-36. example of software processing for one-shot pulse output operation (1/2) ffffh tm01 register 0000h operable bits (tmc013, tmc012) one-shot pulse enable bit (ospe1) one-shot pulse trigger bit (ospt1) one-shot pulse trigger input (ti010 pin) overflow plug (ovf01) compare register (cr010) compare match interrupt (inttm010) compare register (cr011) compare match interrupt (inttm011) to01 pin output to01 output control bits (toe01, toc014, toc011) n m n ? m n ? m 01 or 10 00 00 n n n m m m m + 1 m + 1 <1> <2> <2> <3> to01 output level is not inverted because no one- shot trigger is input. ? time from when the one-shot pulse trigger is input until the one-shot pulse is output = (m + 1) count clock cycle ? one-shot pulse output active level width = (n ? m) count clock cycle
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 272 figure 7-36. example of software processing for one-shot pulse output operation (2/2) tmc013, tmc012 bits = 01 or 10 register initial setting prm01 register, selcnt1 register, crc01 register, toc01 register note , cr010, cr011 registers, port setting initial setting of these registers is performed before setting the tmc013 and tmc012 bits. starts count operation start <1> count operation start flow <2> one-shot trigger input flow tmc013, tmc012 bits = 00 the counter is initialized and counting is stopped by clearing the tmc013 and tmc012 bits to 00. stop <3> count operation stop flow toc01.ospt01 bit = 1 or edge input to ti010 pin write the same value to the bits other than the ospt01 bit. note care must be exercised when setting the toc01 register. for details, see 7.3 (3) 16-bit timer output control register 01 (toc01) .
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 273 7.4.8 pulse width measurement operation the tm01 register can be used to m easure the pulse width of the signal input to the ti010 and ti011 pins. measurement can be accomplished by operating the 16-bit ti mer/event counter 01 in the free-running timer mode or by restarting the timer in synchronizati on with the signal input to the ti010 pin. when an interrupt is generated, read the value of the valid capture register and measure the pulse width. check the tmc01.ovf01 flag. if it is set (to 1), clear it to 0 by software. figure 7-37. block di agram of pulse width measureme nt (free-running timer mode) 16-bit counter (tm01) capture register (cr010) capture signal capture signal interrupt signal (inttm011) interrupt signal (inttm010) capture register (cr011) operable bits tmc013, tmc012 count clock edge detection ti010 pin edge detection ti011 pin selector figure 7-38. block diagram of pulse width measurement (clear & start mode entered by ti010 pin valid edge input) 16-bit counter (tm01) capture register (cr010) capture signal capture signal interrupt signal (inttm011) interrupt signal (inttm010) capture register (cr011) operable bits tmc013, tmc012 count clock edge detection ti010 pin edge detection ti011 pin clear selector
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 274 a pulse width can be measured in the following three ways. ? measuring the pulse width by using two input signals of the ti010 and ti011 pins (free-running timer mode) ? measuring the pulse width by using one input signal of the ti010 pin (free-running timer mode) ? measuring the pulse width by using one input signal of the ti010 pin (clear & start mode entered by the ti010 pin valid edge input) (1) measuring the pulse width by using two input si gnals of the ti010 and ti011 pins (free-running timer mode) set the free-running timer mode (the tmc01.tmc013 an d tmc01.tmc012 bits = 01). when the valid edge of the ti010 pin is detected, the count valu e of the tm01 register is captured to the cr011 register. when the valid edge of the ti011 pin is detected, the count value of the tm 01 register is captured to the cr010 register. specify detection of both the edges of the ti010 and ti011 pins. by this measurement method, the prev ious count value is subt racted from the count valu e captured by the edge of each input signal. therefore, sa ve the previously captured value to a separate register in advance. if an overflow occurs, the value becomes negative if the pr eviously captured value is si mply subtracted from the current captured value and, therefore, a borrow occurs (the psw.cy bit is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear the tmc01.ovf01 bit to 0. figure 7-39. timing example of pulse width measurement (1) ? tmc01 = 04h, prm01 = f0h, crc01 = 05h ffffh tm01 register 0000h operable bits (tmc013, tmc012) capture trigger input (ti010) capture register (cr011) capture interrupt (inttm011) capture trigger input (ti011) capture register (cr010) capture interrupt (inttm010) overflow flag (ovf01) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 275 (2) measuring the pulse width by using one input signal of the ti010 pin (free-running timer mode) set the free-running timer mode (the tmc01.tmc013 and tmc01.tmc012 bits = 01). the count value of the tm01 register is captured to the cr010 r egister in the phase reverse to the valid edge detected on the ti010 pin. when the valid edge of the ti010 pin is detected, the count value of the tm01 register is captured to the cr011 register. by this measurement method, values are stored in se parate capture registers when a width from one edge to another is measured. theref ore, the capture values do not have to be saved. by subtracting the value of one capture register from that of a nother, a high-level width, low-level width, and cycle are calculated. if an overflow occurs, the value becomes negative if one c aptured value is simply subtracted from another and, therefore, a borrow occurs (the psw.cy bit is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear the tmc01.ovf01 bit to 0. figure 7-40. timing example of pulse width measurement (2) ? tmc01 = 04h, prm01 = 10h, crc01 = 07h ffffh tm01 register 0000h operable bits (tmc013, tmc012) capture trigger input (ti010) capture register (cr010) capture register (cr011) capture interrupt (inttm011) overflow flag (ovf01) capture trigger input (ti011) capture interrupt (inttm010) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h l l abc d e 0000h mn s p q
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 276 (3) measuring the pulse width by using one input signal of the ti010 pin (clear & start mode entered by the ti010 pin valid edge input) set the clear & start mode entered by the ti010 pin va lid edge (the tmc01.tmc013 and tmc01.tmc012 bits = 10). the count value of the tm01 regist er is captured to the cr010 register in the phase reverse to the valid edge of the ti010 pin, and the count value of the tm01 regi ster is captured to the cr011 register and the tm01 register is cleared (0000h) when the valid edge of the ti010 pin is detected. ther efore, a cycle is stored in the cr011 register if the tm01 register does not overflow. if an overflow occurs, take the value that results from addi ng 10000h to the value stored in the cr011 register as a cycle. clear the tmc01.ovf01 bit to 0. figure 7-41. timing example of pulse width measurement (3) ? tmc01 = 08h, prm01 = 10h, crc01 = 07h ffffh tm01 register 0000h operable bits (tmc013, tmc012) capture & count clear input (ti010) capture register (cr010) capture register (cr011) capture interrupt (inttm011) overflow flag (ovf01) capture trigger input (ti011) capture interrupt (inttm010) 10 <1> <2> <3> <3> <3> <3> <2> <2> <2> <1> <1> <1> m a b cd n s p q 00 00 0 write clear 0000h l l abc d 0000h mn s p q <1> pulse cycle = (10000h number of times ovf01 bit is set to 1 + captured value of the cr011 register) count clock cycle <2> high-level pulse width = (10000h number of times ovf01 bit is set to 1 + captured value of the cr010 register) count clock cycle <3> low-level pulse width = (pulse cycle ? high-level pulse width)
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 277 figure 7-42. example of register setti ngs for pulse width measurement (1/2) (a) 16-bit timer mode control register 01 (tmc01) 00000/10/100 tmc013 tmc012 tmc011 ovf01 01: free running timer mode 10: clear and start mode entered by valid edge of ti010 pin. (b) capture/compare cont rol register 01 (crc01) 0000010/11 crc012 crc011 crc010 1: cr010 used as capture register 1: cr011 used as capture register 0: ti011 pin is used as capture trigger of cr010. 1: reverse phase of ti010 pin is used as capture trigger of cr010. (c) 16-bit timer output control register 01 (toc01) 00000 lvr01 lvs01 toc014 ospe01 ospt01 toc011 toe01 000 (d) prescaler mode register 01 (prm01), sel ector operation control register 1 (selcnt1) selects count clock (setting valid edge of ti010 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting when crc011 = 1 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0/1 prm01 0/1 0/1 0/1 0 prm011 prm010 es111 es110 es101 es100 0 0/1 0/1 selcnt1 isel11 0/1
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 278 figure 7-42. example of register setti ngs for pulse width measurement (2/2) (e) 16-bit timer counter 01 (tm01) by reading the tm01 register, the count value can be read. (f) 16-bit capture/compare register 010 (cr010) this register is used as a capture register. either t he ti010 or ti011 pin is select ed as a capture trigger. when a specified edge of the capture trigger is detected, the count value of the tm 01 register is stored in the cr010 register. (g) 16-bit capture/compare register 011 (cr011) this register is used as a capture register. the signal input to the ti 010 pin is used as a capture trigger. when the capture trigger is detected, the count value of the tm01 register is stored in the cr011 register.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 279 figure 7-43. example of software proce ssing for pulse width measurement (1/2) (a) example of free-running timer mode ffffh tm01 register 0000h operable bits (tmc013, tmc012) capture trigger input (ti010) capture register (cr011) capture interrupt (inttm011) capture trigger input (ti011) capture register (cr010) capture interrupt (inttm010) 01 d 00 d 00 d 01 d 01 d 02 d 02 d 03 d 03 d 04 d 04 d 10 d 10 d 11 d 11 d 12 d 12 d 13 d 13 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <2> <3> (b) example of clear & start mode entered by ti010 pin valid edge ffffh tm01 register 0000h operable bits (tmc013, tmc012) capture & count clear input (ti010) capture register (cr010) capture interrupt (inttm010) capture register (cr011) capture interrupt (inttm011) 10 d 0 l d 0 d 1 d 1 d 2 d 2 d 3 d 3 d 4 d 4 d 5 d 5 d 6 d 6 d 7 d 7 d 8 d 8 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <3> <2>
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 280 figure 7-43. example of software proce ssing for pulse width measurement (2/2) <2> capture trigger input flow edge detection of ti010, ti011 pins calculated pulse width from capture value stores count value to cr010, cr011 registers. generates capture interrupt note . tmc013, tmc012 bits = 01 or 10 register initial setting prm01 register, selcnt1 register, crc01 register, port setting initial setting of these registers is performed before setting the tmc013 and tmc012 bits. starts count operation start <1> count operation start flow tmc013, tmc012 bits = 00 the counter is initialized and counting is stopped by clearing the tmc013 and tmc012 bits to 00. stop <3> count operation stop flow note the capture interrupt signal (i nttm010) is not generated when the re verse-phase edge of the ti010 pin input is selected to the valid edge of the cr010 register.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 281 7.5 special use of tm01 7.5.1 rewriting cr011 regi ster during tm01 operation in principle, rewriting the cr010 and cr011 registers of the v850es/ke2 when they are used as compare registers is prohibited while the tm 01 register is operating (tmc01.tmc013 and tmc01.tm c012 bits = other than 00). however, the value of the cr011 register can be changed, even while the tm01 register is operating, using the following procedure if the cr011 register is used for ppg output and the duty fa ctor is changed (change the value of the cr011 register immediately after its value matches th e value of the tm01 register. if the value of the cr011 register is changed immediately before its value matc hes the tm01 register, an une xpected operation may be performed). procedure for changing value of the cr011 register <1> disable interrupt inttm011 (tm0ic10.tm0mk11 bit = 1). <2> disable reversal of the timer output when the value of the tm01 register matches that of the cr011 register (toc01.toc014 bit = 0). <3> change the value of the cr011 register. <4> wait for one cycle of the count clock of the tm01 register. <5> enable reversal of the timer output when the value of the tm01 register matches that of the cr011 register (toc01.toc014 bit = 1). <6> clear the interrupt flag of inttm011 to 0 (tm0ic10.tm0if11 bit = 0). <7> enable interrupt inttm011 (tm0ic10.tm0mk11 bit = 0). remark for the tm0ic10 register, see chapter 17 interrupt/exception processing function . 7.5.2 setting lvs01 and lvr01 bits (1) usage of the lvs01 and lvr01 bits the toc01.lvs01 and toc01.lvr01 bits are used to set the default value of the to01 pin output and to invert the timer output without enabling the ti mer operation (tmc01.tmc013 and tmc 01.tmc012 bits = 00). clear the lvs01 and lvr01 bits to 00 (default value: low- level output) when software control is unnecessary. lvs01 bit lvr01 bit timer output status 0 0 not changed (low-level output) 0 1 cleared (low-level output) 1 0 set (high-level output) 1 1 setting prohibited
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 282 (2) setting the lvs01 and lvr01 bits set the lvs01 and lvr01 bits using the following procedure. figure 7-44. example of flow for setting lvs01 and lvr01 bits setting toc01.ospe01, toc014, toc011 bits setting toc01.toe01 bit setting toc01.lvs01, lvr01 bits setting tmc01.tmc013, tmc012 bits <3> enabling timer operation <2> setting of timer output f/f <1> setting of timer output operation caution be sure to set the lvs01 and lvr01 bits following steps <1>, <2>, and <3> above. step <2> can be performed after <1> and before <3>. figure 7-45. timing example of lvr01 and lvs01 bits toc01.lvs01 bit toc01.lvr01 bit operable bits (tmc013, tmc012) to01 pin output inttm010 signal <1> 00 <2> <1> <3> <4> <4> <4> 01, 10, or 11 <1> the to01 pin output goes high wh en the lvs01 and lvr01 bits = 10. <2> the to01 pin output goes low when the lvs01 and lvr01 bits = 01 (the pin output remains unchanged from the high level even if the lvs01 and lvr01 bits are cleared to 00). <3> the timer starts operating when the tmc013 and tm c012 bits are set to 01, 10, or 11. because the lvs01 and lvr01 bits were set to 10 before the operat ion was started, the to01 pin output starts from the high level. after the timer st arts operating, setting the lvs01 and lvr01 bits is prohibited until the tmc013 and tmc012 bits = 00 (disabling the timer operation). <4> the output level of the to01 pi n is inverted each time an interrupt signal (inttm010) is generated.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 283 7.6 cautions (1) alternate functions of ti010/to01 pins channel pin alternate function remarks ti010 p35/to01 shares the pin with to01. ti011 p50/kr0/rtp00 ? p32/asck0/adtrg tm01 to01 p35/ti010 assigned to two pins, p32 and p35. ? to perform the one-shot pulse out put with detecting the valid edge of t he ti010 pin as a trigger, use the output of the to01 pin that fu nctions alternately as p32. when using the output of the to01 pin that functions alternately as p35, t he ti010 pin that functions alternately as p35 cannot be used. when using only a software trigger (setting (1) toc 01.ospt01 bit ) as the start trigger for the one-shot pulse output, either of the p32 and p35 pi ns can be used as the to01 pin output. ? to perform the to01 pin output inversion operation by detecting the valid edge of the ti010 pin input, use the output of the to01 pin that functions alternately as p32. when using the output of the to01 pin that functions alternately as p35, t he ti010 pin that functions alternately as p35 cannot be used. therefore, the to01 pin output inversion operation by detecting the valid edge of the ti010 pin input cannot be performed. when usin g the to01 pin that functions alternately as p35, clear the tmc01.tmc011 bit to 0. (2) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the count of the tm01 register is st arted asynchronously to the count pulse. figure 7-46. count start timing of tm01 register 0000h timer start 0001h 0002h 0003h 0004h count pulse tm01 count value (3) setting cr010 and cr011 registers (in the mode in which clear & start occurs upon match between tm01 register and cr010 register) set the cr010 and cr011 registers to a value other than 0000h (when using these registers as external event counters, one-pulse count operation is not possible).
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 284 (4) data hold timing of capture register (a) if the valid edge of the ti011/ti 010 pin is input while the cr010/cr011 register is read, the cr010/cr011 register performs capture oper ation, but the read value at this time is not guaranteed. howe ver, the interrupt request signal (inttm010/inttm011) is generated as a result of detection of the valid edge. figure 7-47. data hold timing of capture register n n + 1 n + 2 x n + 1 m m + 1 m + 2 count pulse tm01 count value edge input inttm011 value captured to cr011 capture read signal capture operation is performed but read value is not guaranteed. capture operation (b) the values of the cr010 and cr011 registers are no t guaranteed after 16-bit timer/event counter 01 has stopped. (5) setting valid edge set the valid edge of the ti010 pin while the timer operation is stopped (tmc 01.tmc013 and tmc01.tmc012 bits = 00). set the valid edge by us ing the prm01.es100 and prm01.es101 bits. (6) re-triggering one-shot pulse make sure that the trigger is not generated while an active level is being output in t he one-shot pulse output mode. be sure to input the next trigger afte r the current active level is output.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 285 (7) operation of ovf01 flag (a) setting of ovf01 flag the tmc01.ovf01 flag is set to 1 in the following case in addition to when the tm01 register overflows. select the mode in which clear & start occurs upon match between the tm01 r egister and the cr010 register. set the cr010 register to ffffh when the tm01 register is cleared from ffffh to 0000h upon match with the cr010 register figure 7-48. operation timing of ovf01 flag fffeh ffffh ffffh 0000h 0001h count pulse tm01 inttm010 ovf01 cr010 (b) clearing of ovf01 flag after the tm01 register overflows, cl earing ovf01 flag is invalid and set (1) again even if the ovf01 flag is cleared (0) before the next count clock is count ed (before tm01 register becomes 0001h). (8) one-shot pulse output one-shot pulse output operates normally in either the free-running timer mode or the mode in which clear & start occurs on the valid edge of the ti010 pin. in the mo de in which clear & start occurs upon match between the tm01 register and the cr010 register, one-s hot pulse output is not possible.
chapter 7 16-bit timer/event counter 0 user?s manual u17705ej2v0ud 286 (9) capture operation (a) if valid edge of ti010 pin is specified for count clock if the valid edge of the ti010 pin is spec ified for the count clock, the captur e register that s pecified the ti010 pin as the trigger does not operate normally. (b) to ensure that signals input from ti011 and ti010 pins are correctly captured to accurately capture the count value, the pulse input to the ti010 and ti011 pins as a capture trigger must be wider than two count clocks selected by the prm01 and selcnt1 registers. (c) interrupt signal generation although a capture operation is performed at the falling ed ge of the count clock, an interrupt request signal (inttm010, inttm011) is generated at the ri sing edge of the next count clock. (d) note when crc01.crc011 bit is set to 1 when the count value of the tm01 regist er is captured to the cr010 regi ster in the phase reverse to the signal input to the ti010 pin, the interrupt signal (i nttm010) is not generated after the count value is captured. if the valid edge is detect ed on the ti011 pin during this operat ion, the capture operation is not performed but the inttm010 signal is generated as an ex ternal interrupt signal. mask the inttm010 signal when the external interrupt is not used. (10) edge detection (a) specifying valid edge after reset if the operation of the 16-bit timer/ev ent counter 01 is enabled after reset and while the ti010 or ti011 pin is at high level and when the rising edge or both the edges are specified as the vali d edge of the ti010 or ti011 pin, then the high level of the ti010 or ti011 pin is detected as the rising edge. note this when the ti010 or ti011 pin is pulled up. however, t he rising edge is not detected when the operation is once stopped and then enabled again. (b) sampling clock for noise elimination the sampling clock for noise elimination differs depending on whether the valid edge of ti010 is used for the count clock or as a capture trigger. in the former case, sampling is performed using f xx /4, and in the latter case, sampling is performed using the count clo ck selected by the prm01 and selcnt1 registers. when the signal input to the ti010 pin is sampled and the valid level is detected two times in a row, the valid edge is detected. therefore, noise having a short pulse width can be eliminated. remark f xx : main clock frequency
user?s manual u17705ej2v0ud 287 chapter 8 8-bit timer/event counter 5 in the v850es/ke2, two channels of 8-bi t timer/event counter 5 are provided. 8.1 functions 8-bit timer/event counter 5n has the following two modes (n = 0, 1). ? mode using 8-bit timer/event counter alone (individual mode) ? mode using cascade connection (16-bit resolution: cascade connection mode) these two modes are described below. (1) mode using 8-bit timer/event counter alone (i ndividual mode) 8-bit timer/event counter 5n operates as an 8-bit timer/event counter. the following functions can be used. ? interval timer ? external event counter ? square-wave output ? pwm output (2) mode using cascade connection (16-bi t resolution: cascade connection mode) 8-bit timer/event counter 5n operates as a 16-bit time r/event counter by connecti ng the tm5n register in cascade. the following functions can be used. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square-wave output with 16-bit resolution the block diagram of 8-bit timer/event counter 5n is shown next.
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 288 figure 8-1. block diagram of 8-bit timer/event counter 5n ovf ti5n 3 tcl5n2 tcl5n1 tcl5n0 tce5n tmc5n6 tmc5n4 lvs5n lvr5n tmc5n1 toe5n to5n inttm5n s r q inv s r q match clear count clock note selector internal bus internal bus 8-bit timer mode control register 5n (tmc5n) 8-bit timer compare register 5n (cr5n) 8-bit timer counter 5n (tm5n) selector invert level mask circuit timer clock selection register 5n (tcl5n) selector selector csi0 serial clock note the count clock is set by the tcl5n register. remark n = 0, 1 8.2 configuration 8-bit timer/event counter 5n includes the following hardware. table 8-1. configuration of 8-bit timer/event counter 5n item configuration timer registers 8-bit timer counter 5n (tm5n) 16-bit timer counter 5 (tm5): on ly when using cascade connection registers 8-bit timer compare register 5n (cr5n) 16-bit timer compare register 5 (cr5 ): only when using cascade connection timer output 1 (to5n pin) control registers note timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) 16-bit timer mode control register 5 (t mc5): only when using cascade connection note when using the functions of the ti5n and to5n pins, refer to table 4-12 settings when port pins are used for alternate functions . remark n = 0, 1
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 289 (1) 8-bit timer counter 5n (tm5n) the tm5n register is an 8-bit read-only re gister that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. through cascade connection, the tm5n registers can be used as a 16-bit timer. when using the tm50 register and the tm51 register in ca scade as a 16-bit timer, these registers can be read only in 16-bit units. therefore, r ead these registers twice and compare t he values, taking into consideration that the reading occurs during a count change. tm5n (n = 0, 1) 642 after reset: 00h r address: tm50 fffff5c0h, tm51 fffff5c1h 0 753 1 the count value is reset to 00h in the following cases. <1> reset <2> when the tmc5n.tce5n bit is cleared (0) <3> the tm5n register and cr5n register match in t he mode in which clear & start occurs on a match between the tm5n register and the cr5n register caution when connected in cascade, these registers become 0000h ev en when the tce50 bit in the lowest timer (tm50) is cleared. remark n = 0, 1
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 290 (2) 8-bit timer compare register 5n (cr5n) the cr5n register can be read and written in 8-bit units. in a mode other than the pwm mode, the value set to the cr5n register is always compared to the count value of the tm5n register, and if the two values match, an interrupt request signal (inttm5n) is generated. in the pwm mode, tm5n register overfl ow causes the to5n pin output to chan ge to the active level, and when the values of the tm5n register and the cr5n register match, the to5n pi n output changes to the inactive level. the value of the cr5n register can be set in the range of 00h to ffh. when using the tm50 register and tm51 register in ca scade as a 16-bit timer, the cr50 register and cr51 register operate as 16-bit timer compare register 5 (cr5 ). the counter value and register value are compared in 16-bit lengths, and if they match, an inte rrupt request signal (inttm50) is generated. cr5n (n = 0, 1) 642 after reset: 00h r/w address: cr50 fffff5c2h, cr51 fffff5c3h 0 753 1 cautions 1. in the mode in which clear & start occurs upon a match of the tm5n register and cr5n register (tmc5n.tmc5n6 bit = 0), do not writ e a different value to the cr5n register during the count operation. 2. in the pwm mode, set the cr5n register re write interval to thr ee or more count clocks (clock selected with the tcl5n register). 3. before changing the value of the cr5n re gister when using a cascade connection, be sure to stop the timer operation. remark n = 0, 1
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 291 8.3 registers the following two registers are used to co ntrol 8-bit timer/event counter 5n. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) remark to use the functions of the ti5n and to5n pins, refer to table 4-12 settings when port pins are used for alternate functions . (1) timer clock selection register 5n (tcl5n) the tcl5n register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the ti5n pin input. the tcl5n register can be read or written in 8-bit units. reset sets this register to 00h. falling edge of ti5n rising edge of ti5n f xx f xx /2 f xx /4 f xx /64 f xx /256 inttm010 count clock selection note tcl5n2 0 0 0 0 1 1 1 1 tcl5n1 0 0 1 1 0 0 1 1 tcl5n0 0 1 0 1 0 1 0 1 20 mhz 10 mhz ? ? setting prohibited 100 ns 200 ns 3.2 s 12.8 s ? ? ? 100 ns 200 ns 0.4 s 6.4 s 25.6 s ? clock f xx 0 tcl5n (n = 0, 1) 0 0 0 0 tcl5n2 tcl5n1 tcl5n0 after reset: 00h r/w address: tcl50 fffff5c4h, tcl51 fffff5c5h 76 54 32 1 0 note when the internal clock is selected, set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz caution before overwriting the tcl5n register with different data, stop the timer operation. remark when the tm5n register is connected in casc ade, the tcl51 register settings are invalid.
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 292 (2) 8-bit timer mode control register 5n (tmc5n) the tmc5n register performs the following six settings. ? controls counting by the tm5n register ? selects the operation m ode of the tm5n register ? selects the individual mode or cascade connection mode ? sets the status of t he timer output flip-flop ? controls the timer output flip-flop or selects the active level in the pwm (free-running timer) mode ? controls timer output the tmc5n register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h.
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 293 tce5n counting is disabled after the counter is cleared to 0 (counter disabled) start count operation tce5n 0 1 control of count operation of 8-bit timer/event counter 5n tmc5n (n = 0, 1) tmc5n6 0 tmc514 note lvs5n lvr5n tmc5n1 toe5n mode in which clear & start occurs on match between tm5n register and cr5n register pwm (free-running timer) mode tmc5n6 0 1 selection of operation mode of 8-bit timer/event counter 5n individual mode cascade connection mode (connected with 8-bit timer/event counter 50) tmc514 0 1 selection of individual mode or cascade connection mode for 8-bit timer/event counter 51 unchanged reset timer output f/f to 0 set timer output f/f to 1 setting prohibited lvs5n 0 0 1 1 setting of status of timer output f/f lvr5n 0 1 0 1 after reset: 00h r/w address: tmc50 fffff5c6h, tmc51 fffff5c7h disable inversion operation enable inversion operation high active low active tmc5n1 0 1 other than pwm (free-running timer) mode (tmc5n6 bit = 0) controls timer f/f pwm (free-running timer) mode (tmc5n6 bit = 1) selects active level disable output (to5n pin is low level) enable output toe5n 0 1 timer output control <7> 6 5 4 <3> <2> 1 <0> note bit 4 of the tmc50 register is fixed to 0. cautions 1. because to51 and ti51 ar e alternate functions of the sam e pin, only one can be used at one time. 2. the lvs5n and lvr5n bit settings are val id in modes other than the pwm mode. 3. do not set <1> to <4> below at the same time. set as follows. <1> set the tmc5n1 , tmc5n6, and tmc514 note bits: setting of operation mode <2> set the toe5n bit for timer output enable: timer output enable <3> set the lvs5n and lvr5n bits (caution 2): setting of timer output f/f <4> set the tce5n bit remarks 1. in the pwm mode, the pwm output is set to the inactive level by the tce5n bit = 0. 2. when the lvs5n and lvr5n bits are read, 0 is read. 3. the values of the tmc5n6, l vs5n, lvr5n, tmc5n1, and toe 5n bits are reflected to the to5n output regardless of the tce5n bit value.
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 294 8.4 operation 8.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval timer t hat repeatedly generates interrupt s at the interval of the count value preset in the cr 5n register. if the count value in the tm5n register matches the value set in the cr5n register, the value of the tm5n register is cleared to 00h and counting is continued, and at the same time, an interrupt request signal (inttm5n) is generated. setting method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation and selects t he mode in which clear & start occurs on a match between the tm5n register and cr5n regist er (tmc5n register = 0000xx00b, : don?t care). <2> when the tmc5n.tce5n bit is set to 1, the count operation starts. <3> when the values of the tm5n regi ster and cr5n register match, the inttm5n signal is generated (tm5n register is cleared to 00h). <4> then, the inttm5n signal is repe atedly generated at the same interval . to stop counting, set the tce5n bit = 0. interval time = (n + 1) t: n = 00h to ffh caution during interval timer operation, do not rewrite the value of the cr5n register. remark n = 0, 1 figure 8-2. timing of interval timer operation (1/2) basic operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm5n count value cr5n tce5n inttm5n count start remark n = 0, 1
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 295 figure 8-2. timing of interval timer operation (2/2) when cr5n register = 00h t interval time 00h 00h 00h 00h 00h count clock tm5n count value cr5n tce5n inttm5n remark n = 0, 1 when cr5n register = ffh t 01h 00h feh ffh 00h feh ffh 00h ffh ffh ffh count clock tm5n count value cr5n tce5n inttm5n interval time interrupt acknowledgment interrupt acknowledgment remark n = 0, 1
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 296 8.4.2 operation as external event counter the external event counter c ounts the number of clock pulses input to the ti5n pin from an external source by using the tm5n register. each time the valid edge specified by the tcl5n register is input to the ti5n pin, the tm5n register is incremented. either the rising edge or the falling e dge can be specified as the valid edge. when the count value of the tm5n regist er matches the value of the cr5n regi ster, the tm5n register is cleared to 00h and an interrupt request signal (inttm5n) is generated. setting method <1> set each register. ? tcl5n register: selects the ti5n pin input edge. falling edge of ti5n pin tlc5n register = 00h rising edge of ti5n pin tcl5n register = 01h ? cr5n register: compare value (n) ? tmc5n register: stops count operation, selects t he mode in which clear & start occurs on a match between the tm5n register and cr5n register , disables timer output f/f inversion operation, and disables timer output. (tmc5n register = 0000xx00b, : don?t care) ? for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions. <2> when the tmc5n.tce5n bit is set to 1, the counter co unts the number of pulses in put from the ti5n pin. <3> when the values of the tm5n regi ster and cr5n register match, the inttm5n signal is generated (tm5n register is cleared to 00h). <4> then, the inttm5n signal is generat ed each time the values of t he tm5n register and cr5n register match. inttm5n signal is generated when the valid edge of ti5n pin is input n + 1 times: n = 00h to ffh caution during external event counter operation, do not rewrite the value of the cr5n register. remark n = 0, 1 figure 8-3. timing of external event coun ter operation (with rising edge specified) 00h 01h 02h 03h 04h 05h n ? 1n n 00h 01h 02h 03h ti5n cr5n inttm5n tce5n tm5n count value count start remark n = 0, 1
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 297 8.4.3 square-wave output operation a square wave with any frequency can be output at an interval determined by the value preset in the cr5n register. by setting the tmc5n.toe5n bit to 1, the output status of the to5n pin is inverted at an interval determined by the count value preset in the cr 5n register. in this way, a square wave of any frequency can be output (duty = 50%) (n = 0, 1). setting method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation, selects t he mode in which clear & start occurs on a match between the tm5n register and cr5n register, sets initial value of timer output, enables timer output f/f inversion operation, and enables timer output. (tmc5n register = 00001011b or 00000111b) ? for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions. <2> when the tmc5n.tce5n bit is set to 1, counting starts. <3> when the values of the tm5n register and cr5n regi ster match, the timer output f/f is inverted. moreover, the inttm5n signal is generated and the tm5n register is cleared to 00h. <4> then, the timer output f/f is inve rted during the same interval and a s quare wave is output from the to5n pin. frequency = 1/2t(n + 1): n = 00h to ffh caution do not rewrite the value of the cr5n register during square-wave output.
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 298 figure 8-4. timing of square-wave output operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm5n count value cr5n to5n note tce5n inttm5n count start note the initial value of the to5n pin output can be set using the tmc5n.lvs5n and tmc5n.lvr5n bits. remark n = 0, 1
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 299 8.4.4 8-bit pwm output operation by setting the tmc5n.tmc5n6 bit to 1, 8-bit ti mer/event counter 5n performs pwm output. pulses with a duty factor determined by the value set in the cr5n register are out put from the to5n pin. set the width of the active level of the pwm pulse in t he cr5n register. the active level can be selected using the tmc5n.tmc5n1 bit. the count clock can be select ed using the tcl5n register. pwm output can be enabled/disabled by the tmc5n.toe5n bit. caution the cr5n register rewrite interval must be three or more operation clocks (set by the tcl5n register). use method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation, se lects pwm mode, and leave timer output f/f unchanged, sets active level, and enables timer output. (tmc5n register = 01000001b or 01000011b) ? for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions. <2> when the tmc5n.tce5n bit is set to 1, counting starts. pwm output operation <1> when counting starts, pwm output (output from the to5n pin) outputs the inactive level until an overflow occurs. <2> when an overflow occurs, the active level set by setting method <1> is output. the active level is output until the value of the cr5n register and the count value of the tm5n register match. an interrupt request signal (inttm5n) is generated. <3> when the value of the cr5n register and the count value of the tm5n register match, the inactive level is output and continues to be output until an overflow occurs again. <4> then, steps <2> and <3> are repeat ed until counting is stopped. <5> when counting is stopped by clearing tce5n bit to 0, pwm output becomes inactive. cycle = 256t, active level width = nt, duty = n/256: n = 00h to ffh remarks 1. n = 0, 1 2. for the detailed timing, refer to figure 8-5 timing of pwm output operation and figure 8-6 timing of operation b ased on cr5n register transitions .
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 300 (a) basic operation of pwm output figure 8-5. timing of pwm output operation basic operation (active level = h) 00h n + 1 n n 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h active level inactive level active level count clock tm5n count value cr5n tce5n inttm5n to5n t when cr5n register = 00h 00h n + 1 n + 2 n 00h 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level count clock tm5n count value cr5n tce5n inttm5n to5n t when cr5n register = ffh 00h n + 1 n + 2 n ffh 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level inactive level active level active level count clock tm5n count value cr5n tce5n inttm5n to5n t remark n = 0, 1
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 301 (b) operation based on cr5n register transitions figure 8-6. timing of operation b ased on cr5n register transitions when the value of the cr5n register changes from n to m before the rising edge of the ffh clock the value of the cr5n register is transferred at the overflow that occurs immediately after. n n + 1 n + 2 m n <1> cr5n transition (n m) m m + 1 m + 2 m m + 1 m + 2 ffh 02h 00h 01h ffh 02h 00h 01h count clock tm5n count value cr5n tce5n h inttm5n to5n <2> t when the value of the cr5n register changes from n to m after the rising edge of the ffh clock the value of the cr5n register is transferred at the second overflow. n n + 1 n + 2 n nn <1> cr5n transition (n m) m n + 1 n + 2 m m + 1 m + 2 ffh 03h 02h 00h 01h ffh 02h 00h 01h count clock tm5n count value cr5n tce5n h inttm5n to5n <2> t caution in the case of reload from the cr5n register between <1> and <2>, the value that is actually used differs (read value: m; actu al value of cr5n register: n). remark n = 0, 1
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 302 8.4.5 operation as inter val timer (16 bits) the 16-bit resolution timer/event counter mode is se lected by setting the tmc51.tmc514 bit to 1. 8-bit timer/event counter 5n operates as an interval time r by repeatedly generating inte rrupts using the count value preset in 16-bit timer compare register 5 (cr5) as the interval. setting method <1> set each register. ? tcl50 register: selects the count clock (t) (the tcl51 register does not need to be set in cascade connection) ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tmc51 register: selects the mode in wh ich clear & start occurs on a match between tm5 register and cr5 register ( : don?t care) tmc50 register = 0000xx00b tmc51 register = 0001xx00b <2> set the tmc51.tce51 bit to 1. then set the tmc 50.tce50 bit to 1 to start the count operation. <3> when the values of the tm5 r egister and cr5 register connected in cascade match, the inttm50 signal is generated (the tm5 register is cleared to 0000h). <4> the inttm50 signal is then generated repeatedly at the same interval. interval time = (n + 1) t: n = 0000h to ffffh cautions 1. to write using 8-bit access during cascade connection, set th e tce51 bit to 1 at operation start and then set the tce50 bit to 1. when operation is stopped, clear the tce50 bit to 0 and then clear the tce51 bit to 0. 2. during cascade connection, ti50 input, to50 output, and the inttm50 signal are used. do not use ti51 input, to51 out put, and the inttm51 signal; mask them instead (for details, refer to chapte r 17 interrupt/exception processing function). clear the lvs51, lvr51, tmc511, and toe51 bits to 0. 3. do not change the value of the cr5 register during timer operation.
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 303 figure 8-7 shows a timing example of the cascade connection mode with 16-bit resolution. figure 8-7. cascade connection mode with 16-bit resolution 00h n + 1 01h 00h ffh 00h 01h ffh 00h ffh m ? 1 01h 00h 00h na 01h 00h 02h m 00h 00h b n n m interval time operation enabled, count start interrupt occurrence, counter cleared operation stopped count clock tm50 count value tm51 count value tce51 inttm50 cr51 tce50 cr50 t
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 304 8.4.6 operation as external event counter (16 bits) the 16-bit resolution timer/event counter mode is selected by setting the tmc51.tmc514 bit to 1. the external event counter counts the number of clock pulse s input to the ti50 pin from an external source using 16-bit timer counter 5 (tm5). setting method <1> set each register. ? tcl50 register: selects the ti50 pin input edge. (the tcl51 register does not have to be set during cascade connection.) falling edge of ti50 pin tcl50 register = 00h rising edge of ti50 pin tcl50 register = 01h ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tmc51 registers: stops count operation, selects the clear & stop mode entered on a match between the tm5 register and cr5 regi ster, disables timer output f/f inversion, and disables timer output. ( : don?t care) tmc50 register = 0000xx00b tmc51 register = 0001xx00b ? for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions. <2> set the tmc51.tce51 bit to 1. then set the tmc 50.tce50 bit to 1 and count the number of pulses input from the ti50 pin. <3> when the values of the tm5 r egister and cr5 register connected in cascade match, the inttm50 signal is generated (the tm5 register is cleared to 0000h). <4> the inttm50 signal is then generated each time the va lues of the tm5 register and cr5 register match. inttm50 signal is generated when t he valid edge of ti50 pin is input n + 1 times: n = 0000h to ffffh cautions 1. during external event counter opera tion, do not rewrite the value of the cr5n register. 2. to write using 8-bit access during cascade connection, set the tce51 bit to 1 and then set the tce50 bit to 1. when operation is stopped, clear the tce50 bit to 0 and then clear the tce51 bit to 0 (n = 0, 1). 3. during cascade connection, ti50 input and the inttm50 si gnal are used. do not use ti51 input, to51 output, and the inttm51 signal; mask them instead (for details, refer to chapter 17 interrupt/except ion processing function). clear the lvs51, lvr51, tmc511, and toe51 bits to 0. 4. do not change the value of the cr5 regi ster during external event counter operation.
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 305 8.4.7 square-wave output operat ion (16-bit resolution) the 16-bit resolution timer/event counter mode is se lected by setting the tmc51.tmc514 bit to 1. 8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer compare register 5 (cr5). setting method <1> set each register. ? tcl50 register: selects the count clock (t) (the tcl51 register does not have to be set in cascade connection) ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tcm51 registers: stops count operation, se lects the mode in which clear & start occurs on a match between the tm5 register and cr5 register. lvs50 lvr50 timer output f/f status settings 1 0 high-level output 0 1 low-level output enables timer output f/f inversion, and enables timer output. tmc50 register = 00001011b or 00000111b tmc51 register = 00010000b ? for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions. <2> set the tmc51.tce51 bit to 1. then set the tmc 50.tce50 bit to 1 to start the count operation. <3> when the values of the tm5 regi ster and the cr5 register connected in cascade match, the to50 timer output f/f is inverted. moreover, the inttm50 sign al is generated and the tm 5 register is cleared to 0000h. <4> then, the timer output f/f is inve rted during the same interval and a s quare wave is output from the to50 pin. frequency = 1/2t (n + 1): n = 0000h to ffffh caution do not write a different value to the cr5 register during operation.
chapter 8 8-bit timer/event counter 5 user?s manual u17705ej2v0ud 306 8.4.8 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because the tm5n register is started a synchronously to the count pulse. figure 8-8. count start timing of tm5n register 00h timer start 01h 02h 03h 04h count pulse tm5n count value remark n = 0, 1
user?s manual u17705ej2v0ud 307 chapter 9 8-bit timer h in the v850es/ke2, two channels of 8-bit timer h are provided. 9.1 functions 8-bit timer hn has the following functions (n = 0, 1). ? interval timer ? square ware output ? pwm output ? carrier generator 9.2 configuration 8-bit timer hn includes the following hardware. table 9-1. configuration of 8-bit timer hn item configuration timer registers 8-bit ti mer counter hn: 1 each register 8-bit timer h compare register n0 (cmpn0): 1 each 8-bit timer h compare register n1 (cmpn1): 1 each timer outputs tohn, output controller control registers note 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register n (tmcycn) note to use the tohn pin function, refer to table 4-12 settings when port pins are used for alternate functions . remark n = 0, 1
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 308 the block diagram is shown below. figure 9-1. block diag ram of 8-bit timer hn match selector internal bus tmhen ckshn2 ckshn1 ckshn0 tmmdn1tmmdn0 tolevn toenn decoder 8-bit timer h compare register n0 (cmpn0) reload/ interrupt control tohn inttmhn inttm5n selector rmc n nrzb n f xx f xx /2 f xx /2 2 f xx /2 4 f xx /2 6 note interrupt generator output controller level inversion nrz n 1 0 f/f r 8-bit timer counter hn carrier generator mode signal pwm mode signal timer h enable signal clear 3 2 8-bit timer h compare register n1 (cmpn1) 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register n (tmcycn) note f xx /2 10 when n = 0, f xt when n = 1 remark n = 0, 1 (1) 8-bit timer h compare register n0 (cmpn0) this register can be read or written in 8-bit units. this register is used in all of the timer operation modes. this register constantly compares the value set to the cmpn0 register with the count value of 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttmhn) and inverts the output level of the tohn pin. rewrite the value of the cmpn0 register while the timer is stopped (tmhmdn.tmhen bit = 0). reset sets this register to 00h. cmpn0 (n = 0, 1) after reset: 00h r/w address: cmp00 fffff582h, cmp10 fffff592h 76 54 32 1 0 caution rewriting the cmpn0 register during timer count operation is prohibited.
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 309 (2) 8-bit timer h compare register n1 (cmpn1) this register can be read or written in 8-bit units. this register is used in the pwm out put mode and carrier generator mode. in the pwm output mode, this register constantly compares the value set to the cmpn1 register with the count value of 8-bit timer counter hn and, when the two values match, inverts the output leve l of the tohn pin. no interrupt request signal is generated. in the carrier generator mode, the cm pn1 register always compares the value set to the cmpn1 register with the count value of 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttmhn). at the same time, the count value is cleared. the cmpn1 register can be rewri tten during timer count operation. if the value of the cmpn1 register is rewritten while the timer is operat ing, the new value is latched and transferred to the cmpn1 register when the count valu e of the timer matches the old value of the cmpn1 register, and then the value of the cmp n1 register is changed to the new val ue. if matching of the count value and the cmpn1 register value and writing a value to the cmpn1 register conflict, the value of the cmpn1 register is not changed. reset sets this register to 00h. cmpn1 (n = 0, 1) after reset: 00h r/w address: cmp01 fffff583h, cmp11 fffff593h 76 54 32 1 0 the cmpn1 register can be rewritt en during timer count operation. in the carrier generator mode, after the cmpn1 register is set, if the count value of 8-bit timer counter hn and the set value of the cmpn1 register match, an interrupt request signal (in ttmhn) is generated. at the same time, the value of 8-bit timer counter hn is cleared to 00h. if the set value of the cmpn1 register is rewritten dur ing timer operation, the reload timing is when the count value of 8-bit timer counter hn and the set value of the cmpn1 register match. if the transfer timing and write to the cmpn1 register from the cpu conflict, transfer is not performed. caution in the pwm output mode a nd carrier generator mode, be su re to set the cmpn1 register when starting the timer count operation (t mhmdn.tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the same value to the cmpn1 register).
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 310 9.3 registers the registers that control 8-bit timer hn are as follows. ? 8-bit timer h mode register n (tmhmdn) ? 8-bit timer h carrier control register n (tmcycn) remarks 1. to use the tohn pin function, refer to table 4-12 settings when port pins are used for alternate functions . 2. n = 0, 1 (1) 8-bit timer h mode register n (tmhmdn) the tmhmdn register controls the mode of 8-bit timer hn. tmhmdn register can be read or written in 8-bit or 1-bit units. reset sets tmhmdn to 00h. remark n = 0, 1
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 311 (a) 8-bit timer h mode register 0 (tmhmd0) tmhe0 stop timer count operation (8-bit timer counter h0 = 00h) enable timer count operation (counting starts when clock is input) tmhe0 0 1 8-bit timer h0 operation enable tmhmd0 cksh02 cksh01 cksh00 tmmd01 tmmd00 tolev0 toen0 after reset: 00h r/w address: fffff580h f xx f xx /2 f xx /4 f xx /16 f xx /64 f xx /1024 cksh02 0 0 0 0 1 1 cksh01 0 0 1 1 0 0 cksh00 0 1 0 1 0 1 setting prohibited 125 ns 250 ns 1 s 4 s 64 s selection of count clock count clock note interval timer mode carrier generator mode pwm output mode setting prohibited tmmd01 0 0 1 1 tmmd00 0 1 0 1 8-bit timer h0 operation mode other than above low level high level tolev0 0 1 timer output level control (default) disable output enable output toen0 0 1 timer output control f xx = 16.0 mhz <7> 6 5 4 3 2 <1> <0> setting prohibited f xx = 10.0 mhz setting prohibited 100 ns 200 ns 800 ns 3.2 s 51.2 s f xx = 20 mhz 100 ns 200 ns 400 ns 1.6 s 6.4 s 102.4 s note set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz cautions 1. when the tmhe0 bit = 1, setting bits other than those of the tmhmd0 register is prohibited. 2. in the pwm output mode and carrier generator mode, be sure to set the cmp01 register when starting the timer count ope ration (tmhe0 bit = 1) after the timer count operation was stopped (tmhe0 bit = 0) (be sure to set again even if setting the same value to th e cmp01 register). 3. when using the carrier generator mode , set 8-bit timer h0 count clock frequency to six times 8-bit timer/event counter 50 count clock frequency or higher.
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 312 (b) 8-bit timer h mode register 1 (tmhmd1) tmhe1 stop timer count operation (8-bit timer counter h1 = 00h) enable timer count operation (counting starts when clock is input) tmhe1 0 1 8-bit timer h1 operation enable tmhmd1 cksh12 cksh11 cksh10 tmmd11 tmmd10 tolev1 toen1 after reset: 00h r/w address: fffff590h f xx f xx /2 f xx /4 f xx /16 f xx /64 cksh12 0 0 0 0 1 1 cksh11 0 0 1 1 0 0 cksh10 0 1 0 1 0 1 setting prohibited 125 ns 250 ns 1 s 4 s selection of count clock count clock note interval timer mode carrier generator mode pwm output mode setting prohibited tmmd11 0 0 1 1 tmmd10 0 1 0 1 8-bit timer h1 operation mode f xt (subclock) setting prohibited other than above low level high level tolev1 0 1 timer output level control (default) disable output enable output toen1 0 1 timer output control f xx = 16.0 mhz <7> 6 5 4 3 2 <1> <0> setting prohibited 100 ns 200 ns 800 ns 3.2 s f xx = 20.0 mhz f xx = 10.0 mhz 100 ns 200 ns 400 ns 1.6 s 6.4 s note set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz cautions 1. when the tmhe1 bit = 1, setting bits other than those of the tmhmd1 register is prohibited. 2. in the pwm output mode and carrier generator mode, be sure to set the cmp11 register when starting the timer count ope ration (tmhe1 bit = 1) after the timer count operation was stopped (tmhe1 bit = 0) (be sure to set again even if setting the same value to th e cmp11 register). 3. when using the carrier generator mode , set 8-bit timer h1 count clock frequency to six times the 8-bit ti mer/event counter 51 count cl ock frequency or higher.
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 313 (2) 8-bit timer h carrier cont rol register n (tmcycn) this register controls the 8-bit timer hn remote control output and carrier pulse output status. tmcycn register can be read or written in 8-bit or 1-bit units. the nrzn bit is a read-only bit. reset sets tmcycn to 00h. remark n = 0, 1 0 tmcycn (n = 0, 1) 0 0 0 0 rmcn nrzbn nrzn after reset: 00h r/w address: tmcyc0 fffff581h, tmcyc1 fffff591h low-level output high-level output low-level output carrier pulse output rmcn 0 0 1 1 nrzbn 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enable status nrzn 0 1 carrier pulse output status flag 76 54 32 1<0>
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 314 9.4 operation 9.4.1 operation as interval timer/square wave output when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. the cmpn1 register cannot be used in the interval timer mode. even if the cmpn1 register is set, this has no effect on the timer output because matches between 8-bit timer counter hn and the cmpn1 regi ster are not detected. a square wave of the desired frequency (duty = 50%) is out put from the tohn pin, by setting the tmhmdn.toenn bit to 1. remarks 1. for the alternate-function pin (tohn) settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for inttmhn interrupt enable, refer to chapter 17 interrupt/exception processing function . setting <1> set each register. figure 9-2. register settings in interval timer mode (i) 8-bit timer h mode register n (tmhmdn) settings 0 0/1 0/1 0/1 0 sets timer output sets timer output default level sets interval timer mode selects count clock (f cnt ) stops count operation 0 0/1 0/1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 (ii) cmpn0 register settings the interval time is as follows if n is set as a comparison value. ? interval time = (n + 1)/f cnt <2> when the tmhen bit is set to 1, counting starts. <3> when the count value of 8-bit timer counter hn an d the set value of the cmpn0 register match, the inttmhn signal is generated and 8-bit timer counter hn is cleared to 00h. <4> then, the inttmhn signal is generated in the same in terval. to stop the count operation, clear the tmhen bit to 0.
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 315 figure 9-3. timing of interval timer/ square wave output operation (1/2) basic operation (operation when 01h cmpn0 feh) 00h count clock count start 8-bit timer counter hn count value cmpn0 tmhen inttmhn tohn 01h n clear clear n 00h 01h n 00h 01h 00h <1> <2> level inversion, match interrupt occurrence, 8-bit timer counter clear <2> level inversion, match interrupt occurrence, 8-bit timer counter clear <3> interval time <1> when the tmhen bit is set to 1, the count operation is enabled. the count clock starts counting no more than one clock after operation has been enabled. <2> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 r egister match, the value of 8-bit timer counter hn is cleared, the tohn outpu t level is inverted, and the inttmhn signal is output at the rising edge of the count clock. <3> the inttmhn signal and tohn output are set to t he default level when the tmhen bit is cleared to 0 during 8-bit timer hn operation. if the level is alre ady at the default level bef ore the tmhmdn.tmhen bit is cleared to 0, that level is maintained. remarks 1. n = 0, 1 2. 01h n feh
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 316 figure 9-3. timing of interval timer/ square wave output operation (2/2) operation when cmpn0 = ffh 00h count clock count start cmpn0 tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time 8-bit timer counter hn count value operation when cmpn0 = 00h count clock count start cmpn0 tmhen inttmhn note tohn 00h 00h 8-bit timer counter hn count value note an inttmhn interrupt is generated only once. remark n = 0, 1
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 317 9.4.2 pwm output mode operation in the pwm output mode, a pulse of any duty and cycle can be output. the cmpn0 register controls the time r output (tohn) cycle. rewriting the cmpn0 register during timer operation is prohibited. the cmpn1 register controls the time r output (tohn) duty. the cmpn1 r egister can be rewritten during timer operation. the operation in the pwm out put mode is as follows. after timer counting starts, when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, the tohn output level is invert ed and 8-bit timer counter hn is cleared to 00h. when the count value of 8-bit timer counter hn and the set value of the cmpn1 regi ster match, the tohn output level is inverted. remarks 1. for the alternate-function pin (tohn) settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for inttmhn interrupt enable, refer to chapter 17 interrupt/exception processing function . setting <1> set each register. figure 9-4. register settings in pwm output mode (i) 8-bit timer h mode register n (tmhmdn) settings 0 0/1 0/1 0/1 1 enables timer output sets timer output default level selects pwm output mode selects count clock (f cnt ) stops count operation 0 0/1 1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 (ii) cmpn0 register setting ? compare value (n): sets cycle (ii) cmpn1 register setting ? compare value (m): sets duty remarks 1. n = 0, 1 2. 00h cmpn1 (m) < cmpn0 (n) ffh <2> when the tmhen bit is set to 1, counting starts.
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 318 <3> after the count operation is enabled, the first com pare register to be compared is the cmpn0 register. when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match , 8-bit timer counter hn is cleared, an interrupt request signal (in ttmhn) is generated, and the tohn output level is inverted. at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. <4> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 re gister match, the tohn output level is inverted, and at the same time the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> a pulse of any duty can be obtained throug h the repetition of steps <3> and <4> above. <6> to stop the count operation, clear the tmhen bit to 0. designating the set value of the cmpn0 register as (n), the set value of th e cmpn1 register as (m), and the count clock frequency as f cnt , the pwm pulse output cycle and duty are as follows. pwm pulse output cycle = (n + 1)/f cnt duty = inactive width: active width = (m + 1) : (n + 1) cautions 1. the set value of the cmpn1 register ca n be changed while the time r counter is operating. however, this takes a duration of at least three operating clocks (signal selected by the ckshn2 to ckshn0 bits of the tmhmdn regi ster) from when the value of the cmpn1 register is changed until the value is transferred to the register. 2. be sure to set the cmpn1 register when starting the timer count operation (tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the same value to the cmpn1 register). 3. make sure that the cmpn1 register set value (m) and cmpn 0 register set value (n) are within the following range. 00h cmpn1 (m) < cmpn0 (n) ffh
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 319 figure 9-5. operation timing in pwm output mode (1/4) basic operation count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h <1> <3> <2> cmpn1 <4> a5h 01h 8-bit timer counter hn count value <1> when the tmhen bit is set to 1, counting starts. at this time tohn output remains the default level. <2> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 r egister match, the tohn output level is inverted, 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 r egister match, the tohn output level is inverted. at this time, the value of 8-bit timer counter hn is not cleared and the inttmhn signal is not output. <4> when the tmhen bit is cleared to 0 during 8-bit timer hn operation, the inttmhn signal and tohn output are set to the default level. remark n = 0, 1
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 320 figure 9-5. operation timing in pwm output mode (2/4) operation when cmpn0 register = ffh, cmpn1 register = 00h count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmpn1 ffh 00h 8-bit timer counter hn count value operation when cmpn0 register = ffh, cmpn1 register = feh count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmpn1 ffh feh 8-bit timer counter hn count value remark n = 0, 1
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 321 figure 9-5. operation timing in pwm output mode (3/4) operation when cmpn0 register = 01h, cmpn1 register = 00h count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmpn1 00h 8-bit timer counter hn count value remark n = 0, 1
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 322 figure 9-5. operation timing in pwm output mode (4/4) operation by changing cmpn1 r egister (cmpn1 register = 02h 03h, cmpn0 register = a5h) count clock 8-bit timer counter hn cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h <1> <4> <3> <2> cmpn1 <6> <5> 02h a5h 03h 02h (03h) <2>? 80h <1> when the tmhen bit is set to 1, counting starts. at this time, the tohn output remains the default level. <2> the set value of the cmpn1 register can be changed during count operati on. this operation is asynchronous to the count clock. <3> when the count value of 8-bit timer counter hn and t he set value of the cmpn0 register match, 8-bit timer counter hn is cleared, the tohn output level is in verted, and the inttmhn signal is generated. <4> even if the value of the cmpn1 register is chang ed, that value is latched and not transferred to the register. when the count value of 8-bit timer counter hn and the set value of the cmpn1 register prior to the change match, the changed value is transferred to the cmpn1 register and the value of the cmpn1 register is changed (<2>?). however, three or more count clocks are required fr om the time the value of the cmpn1 register is changed until it is transferred to the register. even if a match signal is generated within three count clocks, the changed valu e cannot be transferred to the register. <5> when the count value of 8-bit timer counter hn ma tches the changed set value of the cmpn1 register, the tohn output level is inverted. 8-bit timer count er hn is not cleared and the inttmhn signal is not generated. <6> when the tmhen bit is cleared to 0 during 8-bit timer hn operation, the inttmhn signal and tohn output are set to the default level.
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 323 9.4.3 carrier genera tor mode operation the carrier clock generated by 8-bit timer hn is output using the cycle set with 8-bit timer/event counter 5n. in the carrier generator mode, 8-bit timer/ event counter 5n is used to control the extent to wh ich the carrier pulse of 8-bit timer hn is output, and the carrier pulse is output from the tohn output. remarks 1. for the alternate-function pin (tohn) settings, refer to table 4-12 settings when port pins are used for alternate functions . 2. for inttmhn interr upt enable, refer to chapter 17 interrupt/exception processing function . (1) carrier generation in the carrier generator mode, the cmpn0 register gener ates a waveform with the low-level width of the carrier pulse and the cmpn1 register generates a waveform with the high-level width of the carrier pulse. during 8-bit timer hn operation, the cmpn1 register can be rewritten, but rewriting of the cmpn0 register is prohibited. (2) carrier output control carrier output control is performed wit h the interrupt request signal (inttm 5n) of 8-bit timer/event counter 5n and the tmcycn.nrzbn and tmcycn.rmcn bits. t he output relationships are as follows. rmcn bit nrzbn bit output 0 0 low level output 0 1 high level output 1 0 low level output 1 1 carrier pulse output remark n = 0, 1
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 324 to control carrier pulse output during count operati on, the tmcycn.nrzn and tm cycn.nrzbn bits have a master and slave bit configuration. the nrzn bit is read-only while the nrzbn bit can be read and written. the inttm5n signal is synchronized with the 8-bit timer hn clock and output as the inttm5hn signal. the inttm5hn signal becomes the data transfer signal of the nrzn bit and the value of the nrzbn bit is transferred to the nrzn bit. the transfer timing from the nrzbn bit to the nrzn bit is as follows. figure 9-6. transfer timing 8-bit timer hn count clock tmhen inttm5n inttm5hn nrzn nrzbn rmcn 1 1 1 0 00 <1> <2> <3> <1> the inttm5n signal is synchronized with the count clock of 8-bit timer hn and is output as the inttm5hn signal. <2> the value of the nrzbn bit is transferred to the nrzn bit at the second clock from the rising edge of the inttm5hn signal. <3> write the next value to the nrzbn bit in the inte rrupt servicing programming that has been started by the inttm5hn interrupt or after timing has been chec ked by polling the interrupt request flag. write data to count the next time to the cr5n register. cautions 1. do not rewrite the nrzbn bit again until at least the second cl ock after it has been rewritten, or else transfer from the nrzbn bit to the nrzn bit is not guaranteed. 2. when using 8-bit timer/event counter 5n in the carrier generator mode, an interrupt occurs at the timing of <1>. an interrupt o ccurs at a different timing when it is used in other than the carrier generator mode. remark n = 0, 1
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 325 setting <1> set each register. figure 9-7. register settings in carrier generator mode ? 8-bit timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 enables timer output sets timer output default level selects carrier generator mode selects count clock (f cnt ) stops count operation 1 0/1 1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 ? cmpn0 register: compare value ? cmpn1 register: compare value ? tmcycn register: rmcn = 1 ... re mote control output enable bit nrzbn = 0/1 ... carrier output enable bit ? tcl5n, tmc5n registers: refer to 9.3 registers . remark n = 0, 1 <2> when the tmhen bit is set to 1, 8-bit timer hn count operation starts. <3> when the tmc5n.tce5n bit is set to 1, 8-bi t timer/event counter 5n count operation starts. <4> after the count operation is enabled, the first compar e register to be compared is the cmpn0 register. when the count value of 8-bit timer counter hn and the set value of the cmpn0 register match, the inttmhn signal is generated, 8-bit timer counter hn is cleared, and at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. <5> when the count value of 8-bit timer counter hn an d the set value of the cmpn1 register match, the inttmhn signal is generated, 8-bit timer counter hn is cleared, and at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. <6> the carrier clock is obtained through t he repetition of steps <4> and <5> above. <7> the inttm5n signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. this signal becomes the data transfer signal of the nrzbn bit and the value of the nrzbn bit is transferred to the nrzn bit. <8> write the next value to the nrzbn bit in the interru pt servicing programming th at has been started by the inttm5hn interrupt or after timing has been checked by polling the interrupt request flag. write data to count the next time to the cr5n register. <9> when the nrzn bit becomes high level, the carri er clock is output from the tohn pin. <10> any carrier clock can be obtained through the repetiti on of the above steps. to stop the count operation, clear the tmhen bit to 0.
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 326 designating the set value of the cmpn0 register as (n ), the set value of the cm pn1 register as (m), and the count clock frequency as f cnt , the carrier clock output cycle and duty are as follows. carrier clock output cycle = (n + m + 2)/f cnt duty = high level width: carrier clock output width = (m + 1) : (n + m + 2) cautions 1. be sure to set the cmpn1 register when starting the timer count operation (tmhen bit = 1) after the timer count operation was stopped (tmh en bit = 0) (be sure to set again even if setting the same value to the cmpn1 register). 2. set the values of the cmpn0 and cmpn1 registers in the range of 01h to ffh. 3. in the carrier generator mode, thr ee operating clocks (signal selected by the tmhmdn.ckshn0 to tmhmdn.cks hn2 bits) are required for actual transfer of the new value to the register after the cmpn 1 register has been rewritten. 4. be sure to perform the tmcycn.rmcn bit se tting before the start of the count operation. 5. when using the carrier generator mode, set the 8-bit timer hn count clock frequency to six times the 8-bit timer/even t counter 5n count clo ck frequency or higher.
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 327 figure 9-8. carrier ge nerator mode (1/3) operation when the cmpn0 register = n, the cmpn1 register = n is set cmpn0 cmpn1 tmhen inttmhn carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 5n count clock tm5n count value tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5hn <1> <2> <3> <4> <5> <6> klm n <6> <7> 8-bit timer hn count clock 8-bit timer counter hn count value cr5n <1> when the tmhen bit = 0 and the tce5n bit = 0, the operation of 8-bit timer hn is stopped. <2> when the tmhen bit is set to 1, 8-bit timer hn starts counting. the carrier clock remains the default level. <3> when the count value of 8-bit timer counter hn and th e set value of the cmpn0 r egister match, the first inttmhn signal is generated, the carrier clock signal is inverted, and the register t hat is compared with 8-bit timer counter hn changes from the cm pn0 register to the cmpn1 register. 8-bit timer counter hn is cleared to 00h. <4> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 register match, the inttmhn signal is generated, the carrier clock signal is invert ed, and the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. 8-bit timer counter hn is cleared to 00h. a carrier clock with a duty of 50% is generated through the repetition of steps <3> and <4>. <5> the inttm5n signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. <6> the inttm5hn signal becomes the data transfer signal of the nrzbn bit, and the va lue of the nrzbn bit is transferred to the nrzn bit. <7> the tohn output is made low leve l by clearing the nrzn bit = 0. remark n = 0, 1
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 328 figure 9-8. carrier ge nerator mode (2/3) operation when the cmpn0 register = n, the cmpn1 register = m is set n cmpn0 cmpn1 tmhen inttmhn carrier clock tm5n count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5hn klmn nrzbn <1> <2> <3> <4> <5> <6> <7> 8-bit timer 5n count clock 8-bit timer hn count clock 8-bit timer counter hn count value <1> when the tmhen bit = 0 and the tce5n bit = 0, the operation of 8-bit timer hn is stopped. <2> when the tmhen bit is set to 1, 8-bit timer hn starts counting. the carrier clock remains the default level at this time. <3> when the count value of 8-bit timer counter hn and th e set value of the cmpn0 r egister match, the first inttmhn signal is generated, the carrier clock signal is inverted, and the register t hat is compared with 8-bit timer counter hn changes from the cm pn0 register to the cmpn1 register. 8-bit timer counter hn is cleared to 00h. <4> when the count value of 8-bit timer counter hn and t he set value of the cmpn1 register match, the inttmhn signal is generated, the carrier clock signal is invert ed, and the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. 8-bit timer counter hn is cleared to 00h. a carrier clock with a fixed duty (other than 50%) is generated through the repetiti on of steps <3> and <4>. <5> the inttm5n signal is generated. this signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. <6> the carrier is output from the rising edge of t he first carrier clock by setting the nrzn bit = 1. <7> by setting the nrzn bit = 0, the tohn output is also main tained high level while the carrier clock is high level, and does not change to low level (the high level width of the carrier waveform is guaranteed through steps <6> and <7>). remark n = 0, 1
chapter 9 8-bit timer h user?s manual u17705ej2v0ud 329 figure 9-8. carrier ge nerator mode (3/3) operation based on the cmp n1 register transitions 8-bit timer hn count clock cmpn0 tmhen inttmhn carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>' <4> <3> <2> cmpn1 <5> m n l m (l) 8-bit timer counter hn count value <1> when the tmhen bit is set to 1, counting starts. the carrier clock remains the default level at this time. <2> when the count value of the 8-bit timer counter hn matches the value of the cmpn0 register, the inttmhn signal is output, the carrier signal is inverted, and the 8-bi t timer counter is cleared to 00h. at the same time, the compare register whose value is to be compared with that of the 8-bit timer counter hn is changed from the cmpn0 register to the cmpn1 register. <3> the cmpn1 register is asynchronous to the count clock, and its value c an be changed while the 8-bit timer hn is operating. the new value (l) to which the value of t he register is to be changed is latched. when the count value of the 8-bit timer counter hn matches the val ue (m) of the cmpn1 register before the change, the cmpn1 register is changed (<3>?). however, it takes three count clo cks or more since the value of the cmpn1 register has been changed until the value is transferred to the register. even if a matc h signal is generated before the duration of three count clocks elapses, the new value is not transferred to the register. <4> when the count value of 8-bit timer counter hn and the value (m) of the cmpn1 re gister match, the inttmhn signal is output, the carrier signal is inverted, and 8-bit ti mer counter hn is cleared to 00h. at the same time, the compare register whose value is to be compared with that of the 8-bit timer counter hn is changed from the cmpn1 register to the cmpn0 register. <5> the timing at which the count value of 8-bit timer counter hn and the value of the cmpn1 register match again is the changed value (l). remark n = 0, 1
user?s manual u17705ej2v0ud 330 chapter 10 interval timer, watch timer the v850es/ke2 includes interval timer brg and a watch ti mer. interval timer brg can also be used as the source clock of the watch timer. the watch timer can also be used as interval timer wt. two interval timer channels and one watch timer channel can be used at the same time. 10.1 interval timer brg 10.1.1 functions interval timer brg has the following functions. ? interval timer brg: an interrupt request si gnal (intbrg) is generated at a specified interval. ? generation of count clock for watch timer: when the main clock is used as the count clock for the watch timer, a count clock (f brg ) is generated. 10.1.2 configuration the following shows the block diagram of interval timer brg. figure 10-1. block diagra m of interval timer brg f x f x /8 f x /4 f x /2 f x bgcs0 bgcs1 todis bgce 3-bit prescaler 8-bit counter clear match f bgcs count clock for watch timer intbrg 1/2 prsm register prscm register 2 internal bus f brg clock control output control selector remark f x : main clock oscillation frequency f bgcs : interval timer brg count clock frequency f brg : watch timer count clock frequency intbrg: interval timer brg interrupt request signal
chapter 10 interval timer, watch timer user?s manual u17705ej2v0ud 331 (1) clock control the clock control controls supply/stop of the operation clock of interval timer brg. (2) 3-bit prescaler the 3-bit prescaler divides f x to generate f x /2, f x /4, and f x /8. (3) selector the selector selects the count clock (f bgcs ) for interval timer brg from f x , f x /2, f x /4, and f x /8. (4) 8-bit counter the 8-bit counter counts the count clock (f bgcs ). (5) output control the output control controls supply of the count clock (f brg ) for the watch timer. (6) prscm register the prscm register is an 8-bit compare re gister that sets the interval time. (7) prsm register the prsm register controls the oper ation of interval timer brg, the selector, and clock supply to the watch timer.
chapter 10 interval timer, watch timer user?s manual u17705ej2v0ud 332 10.1.3 registers interval timer brg includes the following registers. (1) interval timer brg mode register (prsm) prsm controls the operation of interval timer brg, se lection of count clock, and clock supply to the watch timer. this register can be read or written in 8-bit or 1-bit units. reset sets prsm to 00h. 0 prsm 0 0 bgce 0 todis bgcs1 bgcs0 operation stopped, 8-bit counter cleared to 01h operate bgce 0 1 control of interval timer operation f x f x /2 f x /4 f x /8 5 mhz 200 ns 400 ns 800 ns 1.6 s 4 mhz 250 ns 500 ns 1 s 2 s bgcs1 0 0 1 1 bgcs0 0 1 0 1 selection of input clock (f bgcs ) note after reset: 00h r/w address: fffff8b0h clock for watch timer supplied clock for watch timer not supplied todis 0 1 control of clock supply for watch timer 10 mhz 100 ns 200 ns 400 ns 800 ns < > note set these bits so that the fo llowing conditions are satisfied. v dd = 4.0 to 5.5 v: f bgcs 10 mhz v dd = 2.7 to 4.0 v: f bgcs 5 mhz cautions 1. do not change the values of the todi s, bgcs1, and bgcs0 bits while interval timer brg is operating (bgce bit = 1). set the todis, bgcs1, and bgcs0 bits before setting (1) the bgce bit. 2. when the bgce bit is clea red (to 0), the 8-bit counter is cleared.
chapter 10 interval timer, watch timer user?s manual u17705ej2v0ud 333 (2) interval timer brg compare register (prscm) prscm is an 8-bit compare register. this register can be read or written in 8-bit units. reset sets prscm to 00h. prscm7 prscm prscm6 prscm5 prscm4 prscm3 prscm2 prscm1 prscm0 after reset: 00h r/w address: fffff8b1h caution do not rewrite the prscm regi ster while interval timer brg is operating (prsm.bgce bit = 1). set the prscm register before setting (1) the bgce bit.
chapter 10 interval timer, watch timer user?s manual u17705ej2v0ud 334 10.1.4 operation (1) operation of interval timer brg set the count clock by using the bg cs1 and bgcs0 bits of prsm and the 8-bit compare value by using the prscm register. when the prsm.bgce bit is set (1), interval timer brg starts operating. each time the count value of the 8-bit counter and the set value in the prscm register match, an interrupt request signal (intbrg) is generated. at the same time, the 8-bit counter is cleared to 01h and counting is continued. the interval time can be obtained from the following equation. interval time = 2 m n/f x remark m: division value (set values of bgcs1 and bgcs0 bits) = 0 to 3 n: set value in prscm register note = 1 to 256 (when the set value in the prscm register is 00h, n = 256) f x : main clock oscillation frequency note when the prscm register = 01h, an intb rg interrupt is generated only once. (2) count clock supply for watch timer set the count clock by using the bg cs1 and bgcs0 bits of prsm and the 8-bit compare value by using the prscm register, so that the count clock frequency (f brg ) of the watch timer is 32.768 khz. clear (0) the prsm.todis bit at the same time. when the prsm.bgce bit is set (1), f brg is supplied to the watch timer. f brg is obtained from the following equation. f brg = f x /(2 m+ 1 n) to set f brg to 32.768 khz, perform the following calculat ion to set the bgcs1 and bgcs0 bits and the prscm register. <1> set n = f x /65,536 (round off the decimal) to set m = 0. <2> if n is even, n = n/2 and m = m + 1 <3> repeat step <2> until n is even or m = 3 <4> set n to the prscm register and m to the bgcs1 and bgcs0 bits. example: when f x = 4.00 mhz <1> n = 4,000,000/65,536 = 61 (r ound off the decimal), m = 0 <2>, <3> since n is odd, the values remain as n = 61, m = 0 <4> the set value in the prscm register: 3 dh (61), the set values in the bgcs1 and bgcs0 bits: 00 remark m: divided value (set value in the bgcs1 and bgcs0 bits) = 0 to 3 n: set value in prscm register = 1 to 256 (when the set value in the prscm register is 00h, n = 256) f x : main clock oscillation frequency
chapter 10 interval timer, watch timer user?s manual u17705ej2v0ud 335 10.2 watch timer 10.2.1 functions the watch timer has the following functions. ? watch timer: an interrupt request signal (intwt) is generated at time intervals of 0.5 or 0.25 seconds by using the main clock or subclock. ? interval timer: an interrupt request signal (i ntwti) is generated at the preset time interval. the watch timer and interval timer functions can be used at the same time. 10.2.2 configuration the following shows the block di agram of the watch timer. figure 10-2. block diagram of watch timer internal bus watch timer operation mode register (wtm) f brg f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 selector selector selector selector remark f brg : frequency of count clock from interval timer brg f xt : subclock frequency f w : watch timer clock frequency intwt: watch timer interrupt request signal intwti: interval timer interrupt request signal
chapter 10 interval timer, watch timer user?s manual u17705ej2v0ud 336 (1) 11-bit prescaler the 11-bit prescaler generates a clock of f w /2 4 to f w /2 11 by dividing f w . (2) 5-bit counter the 5-bit counter generates the watch timer interru pt request signal (intwt) at intervals of 2 4 /f w , 2 5 /f w , 2 13 /f w , or 2 14 /f w by counting f w or f w /2 9 . (3) selectors the watch timer has the following four selectors. ? selector that selects the main clo ck (the clock from interval timer brg (f brg )) or the subclock (f xt ) as the clock for the watch timer. ? selector that selects f w or f w /2 9 as the count clock frequency of the 5-bit counter ? selector that selects 2 4 /f w or 2 13 /f w , or 2 5 /f w or 2 14 /f w as the intwt signal generation time interval. ? selector that selects the generation time interval of the interval timer wt inte rrupt request signal (intwti) from 2 4 /f w to 2 11 /f w . (4) 8-bit counter the 8-bit counter counts the count clock (f bgcs ). (5) wtm register the wtm register is an 8-bit register that controls the operation of the watch timer/interval timer wt and sets the interval of interrupt request signal generation. 10.2.3 registers the watch timer includes the following register. (1) watch timer operation mode register (wtm) this register enables or disables the count clock and operation of the watch ti mer, sets the interval time of the 11-bit prescaler, controls the operation of the 5-bit counter, and sets the timer of watch timer interrupt request signal (intwt) generation. the wtm register can be read or written in 8-bit or 1-bit units. reset sets wtm to 00h.
chapter 10 interval timer, watch timer user?s manual u17705ej2v0ud 337 wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.91 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.3 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of interval timer interrupt (intwti) time wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h < > < > 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of watch timer interrupt (intwt) time clear after operation stops start wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stop operation (clear both prescaler and 5-bit counter) enable operation wtm0 0 1 watch timer operation enable caution rewrite the wtm2 to wtm7 bits wh ile both the wtm0 and wtm1 bits are 0. remarks 1. f w : watch timer clock frequency 2. values in parentheses apply when f w = 32.768 khz
chapter 10 interval timer, watch timer user?s manual u17705ej2v0ud 338 10.2.4 operation (1) operation as watch timer the watch timer generates an interrupt request at fixed time intervals. the watch timer operates using time intervals of 0.25 or 0.5 second s with the subclock (32.768 khz). the count operation starts when the wtm.wtm0 and wtm. wtm1 bits are set to 11. when these bits are cleared to 00, the 10-bit prescaler and 5-bit count er are cleared and the count operation stops. the 5-bit counter can be cleared to synchronize the time by clearing the wtm1 bit to 0 when the watch timer and interval timer wt operate simultaneously. at this ti me, an error of up to 15.6 ms may occur in the watch timer, but interval timer wt is not affected. (2) operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (intwti) at intervals specified by a count value set in advance. the interval time can be selected by the wtm.wtm4 to wtm.wtm7 bits. table 10-1. interval ti me of interval timer wtm7 wtm6 wtm5 wtm4 interval time 0 0 0 0 2 4 1/f w 488 s (operating at f w = f xt = 32.768 khz) 0 0 0 1 2 5 1/f w 977 s (operating at f w = f xt = 32.768 khz) 0 0 1 0 2 6 1/f w 1.95 ms (operating at f w = f xt = 32.768 khz) 0 0 1 1 2 7 1/f w 3.91 ms (operating at f w = f xt = 32.768 khz) 0 1 0 0 2 8 1/f w 7.81 ms (operating at f w = f xt = 32.768 khz) 0 1 0 1 2 9 1/f w 15.6 ms (operating at f w = f xt = 32.768 khz) 0 1 1 0 2 10 1/f w 31.3 ms (operating at f w = f xt = 32.768 khz) 0 1 1 1 2 11 1/f w 62.5 ms (operating at f w = f xt = 32.768 khz) 1 0 0 0 2 4 1/f w 488 s (operating at f w = f brg = 32.768 khz) 1 0 0 1 2 5 1/f w 977 s (operating at f w = f brg = 32.768 khz) 1 0 1 0 2 6 1/f w 1.95 ms (operating at f w = f brg = 32.768 khz) 1 0 1 1 2 7 1/f w 3.91 ms (operating at f w = f brg = 32.768 khz) 1 1 0 0 2 8 1/f w 7.81 ms (operating at f w = f brg = 32.768 khz) 1 1 0 1 2 9 1/f w 15.6 ms (operating at f w = f brg = 32.768 khz) 1 1 1 0 2 10 1/f w 31.3 ms (operating at f w = f brg = 32.768 khz) 1 1 1 1 2 11 1/f w 62.5 ms (operating at f w = f brg = 32.768 khz) remark f w : watch timer clock frequency
chapter 10 interval timer, watch timer user?s manual u17705ej2v0ud 339 figure 10-3. operation timing of watch timer/interval timer start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti remarks 1. assuming that the interrupt time of the watch timer is set to 0.5 seconds. 2. f w : watch timer clock frequency values in parentheses apply when count clock f w = 32.768 khz. n: number of interval timer wt operations 10.3 cautions (1) operation as watch timer some time is required before the first watch timer in terrupt request (intwt) is generated after operation is enabled (wtm.wtm1 and wtm.wtm0 bits = 11). figure 10-4. example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s) it takes 0.515625 (max.) seconds for the first intwt to be generated (2 9 1/32768 = 0.015625 (max.) seconds longer). intwt is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt
chapter 10 interval timer, watch timer user?s manual u17705ej2v0ud 340 (2) when watch timer and interval timer brg operate simultaneously when using the subclock as the count clock for the watch ti mer, the interval time of interval timer brg can be set to any value. changing the interval time does not a ffect the watch timer (before changing the interval time, stop operation). when using the main clock as the count clock for the watch timer, set the interval time of interval timer brg to approximately 65.536 khz. do not change this value. (3) when interval timer brg and inter val timer wt operate simultaneously when using the subclock as the count clock for interval ti mer wt, the interval times of interval timers brg and wt can be set to any values. they can also be cha nged later (before changing the value, stop operation). when using the main clock as the count clock for interval timer wt, the interval time of interval timer brg can be set to any value, but cannot be changed later (it can be changed only when interval timer wt stops operation). the interval time of interval timer wt can be set to 2 5 to 2 12 of the set value of interval timer brg. it can also be changed later. (4) when watch timer and interval timer wt operate simultaneously the interval time of interval timer wt can be set to a value between 488 s and 62.5 ms. it cannot be changed later. do not stop interval timer wt (clear (0) the wtm.wtm0 bit) while the watch timer is operating. if the wtm0 bit is set (1) after it had been cleared (0), the watch timer will have a discrepancy of up to 0.5 or 0.25 seconds. (5) when watch timer, interval timer brg, and interval time r wt operate simultaneously when using the subclock as the count clock for the watch timer, the interval times of interval timers brg and wt can be set to any values. the interval time of interval timer brg can be changed later (before changing the value, stop operation). when using the main clock as the count clock for the watch timer, set the interval time of interval timer brg to approximately 65.536 khz. it cannot be c hanged later. the interval time of interval timer wt can be set to a value between 488 s and 62.5 ms. it cannot be changed later. do not stop interval timer brg (clear (0) the prsm.bgce bit) or interval timer wt (clear (0) the wtm.wtm0 bit) while the watch timer is operating.
user?s manual u17705ej2v0ud 341 chapter 11 watchdog timer functions 11.1 watchdog timer 1 11.1.1 functions watchdog timer 1 has the following operation modes. ? watchdog timer ? interval timer the following functions are realized fr om the above-listed operation modes. ? generation of non-maskable interrupt request si gnal (intwdt1) upon overflow of watchdog timer 1 note ? generation of system reset signal (wdtres1 ) upon overflow of watchdog timer 1 ? generation of maskable interrupt request signal (intwdtm1) upon overflow of interval timer note for non-maskable interrupt servicing due to non-mask able interrupt request signal (intwdt1, intwdt2), refer to 17.10 cautions . remark select whether to use watchdog timer 1 in the watchdog timer 1 mode or the interval timer mode with the wdtm1 register.
chapter 11 watchdog timer functions user?s manual u17705ej2v0ud 342 figure 11-1. block diagra m of watchdog timer 1 wdtm14 wdtm13 run1 2 intwdtm1 wdtres1 3 wdcs1 wdcs0 wdcs2 f xw /2 21 f xw /2 15 f xw /2 16 f xw /2 17 f xw /2 18 f xw /2 19 f xw /2 14 f xw /2 13 intwdt1 f xw internal bus watchdog timer mode register 1 (wdtm1) watchdog timer clock selection register (wdcs) output controller prescaler clear selector remark intwdtm1: request signal for maskable interrupt through watchdog timer 1 overflow intwdt1: request signal for non-maskable inte rrupt through watchdog timer 1 overflow wdtres1: reset signal through watchdog timer 1 overflow f xw = f x : watchdog timer 1 clock frequency
chapter 11 watchdog timer functions user?s manual u17705ej2v0ud 343 11.1.2 configuration watchdog timer 1 includes the following hardware. table 11-1. configuration of watchdog timer 1 item configuration control register watchdog timer clock select ion register (wdcs) watchdog timer mode register 1 (wdtm1) 11.1.3 registers the registers that control watchdo g timer 1 are as follows. ? watchdog timer clock selection register (wdcs) ? watchdog timer mode register 1 (wdtm1) (1) watchdog timer clock selection register (wdcs) this register sets the overflow time of watchdog timer 1 and the interval timer. the wdcs register can be read or wri tten in 8-bit or 1-bit units. reset sets wdcs to 00h. 0 wdcs 0 0 0 0 wdcs2 wdcs1 wdcs0 2 13 /f xw 2 14 /f xw 2 15 /f xw 2 16 /f xw 2 17 /f xw 2 18 /f xw 2 19 /f xw 2 21 /f xw wdcs2 0 0 0 0 1 1 1 1 overflow time of watchdog timer 1/interval timer wdcs1 0 0 1 1 0 0 1 1 wdcs0 0 1 0 1 0 1 0 1 4 mhz 10 mhz 5 mhz 2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.2 ms 52.43 ms 209.7 ms f xw after reset: 00h r/w address: fffff6c1h remark f xw = f x : watchdog timer 1 clock frequency
chapter 11 watchdog timer functions user?s manual u17705ej2v0ud 344 (2) watchdog timer mode register 1 (wdtm1) this register sets the watchdog timer 1 operati on mode and enables/disables count operations. this register is a special register that c an be written only in a special sequence (refer to 3.4.7 special registers ). the wdtm1 register can be read or written in 8-bit or 1-bit units. reset sets wdtm1 to 00h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm1 register. for details, refer to 3.4.8 (2). run1 stop counting clear counter and start counting run1 0 1 selection of operation mode of watchdog timer 1 note 1 wdtm1 0 0 wdtm14 wdtm13 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (upon overflow, maskable interrupt intwdtm1 is generated.) watchdog timer mode 1 note 3 (upon overflow, non-maskable interrupt intwdt1 is generated.) watchdog timer mode 2 (upon overflow, reset operation wdtres1 is started.) wdtm14 0 0 1 1 wdtm13 0 1 0 1 selection of operation mode of watchdog timer 1 note 2 < > notes 1. once the run1 bit is set (to 1), it c annot be cleared (to 0) by software. therefore, when counting is start ed, it cannot be stopped except reset. 2. once the wdtm13 and wdtm14 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only by reset. 3. for non-maskable interrupt servicing due to non -maskable interrupt request signal (intwdt1), refer to 17.10 cautions .
chapter 11 watchdog timer functions user?s manual u17705ej2v0ud 345 11.1.4 operation (1) operation as watchdog timer 1 watchdog timer 1 operation to detect a program loop is selected by setting the wdtm1.wdtm14 bit to 1. the count clock (program loop detection time interv al) of watchdog timer 1 can be selected using the wdcs.wdcs0 to wdcs.wdcs2 bits. the count operation is started by setting the wdtm1.run1 bit to 1. when, after the count operation is st arted, the run1 bit is again set to 1 within the set program loop detection time interval, watchdog timer 1 is cleared and the count operation starts again. if the program loop detection time is exceeded without run1 bit being set to 1, reset signal (wdtres1) through the value of the wdtm1.wdtm13 bit or a non-maskable interrupt request signal (intwdt1) is generated. the count operation of watchdog timer 1 stops in t he stop mode and idle mode. set the run1 bit to 1 before the stop mode or idle mode is entered in order to clear watchdog timer 1. because watchdog timer 1 operates in the halt mode, make sure that an overflow will not occur during halt. cautions 1. when the subclock is selected for the cpu cl ock, the count operation of watchdog timer 1 is stopped (the value of watc hdog timer 1 is maintained). 2. for non-maskable interrupt servicing due to the intwdt1 signal, refer to 17.10 cautions. table 11-2. program loop detect ion time of watchdog timer 1 program loop detection time clock f xw = 4 mhz f xw = 5 mhz f xw = 10 mhz 2 13 /f xw 2.048 ms 1.638 ms 0.819 ms 2 14 /f xw 4.096 ms 3.277 ms 1.683 ms 2 15 /f xw 8.192 ms 6.554 ms 3.277 ms 2 16 /f xw 16.38 ms 13.11 ms 6.554 ms 2 17 /f xw 32.77 ms 26.21 ms 13.11 ms 2 18 /f xw 65.54 ms 52.43 ms 26.21 ms 2 19 /f xw 131.1 ms 104.9 ms 52.43 ms 2 21 /f xw 524.3 ms 419.4 ms 209.7 ms remark f xw = f x : watchdog timer 1 clock frequency
chapter 11 watchdog timer functions user?s manual u17705ej2v0ud 346 (2) operation as interval timer watchdog timer 1 can be made to operate as an interval ti mer that repeatedly generates interrupts using the count value set in advance as the interval, by clearing the wdtm1.wdtm14 bit to 0. when watchdog timer 1 operates as an interval time r, the interrupt mask flag (wdtmk) and priority specification flags (wdtpr0 to wdtpr2) of the wdti c register are valid and maskable interrupt request signals (intwdtm1) can be generated. the default priority of the intwdtm1 signal is set to the highest level among the maskable interrupt request signals. the interval timer continues to operate in the halt mode, but it stops operating in the stop mode and the idle mode. cautions 1. once the wdtm14 bit is set to 1 (thereby selecting the watc hdog timer 1 mode), the interval timer mode is not entered as long as reset is not performed. 2. when the subclock is sel ected for the cpu clock, the count operation of the watchdog timer 1 stops (the value of the wa tchdog timer is maintained). table 11-3. interval ti me of interval timer interval time clock f xw = 4 mhz f xw = 5 mhz f xw = 10 mhz 2 13 /f xw 2.048 ms 1.638 ms 0.819 ms 2 14 /f xw 4.096 ms 3.277 ms 1.638 ms 2 15 /f xw 8.192 ms 6.554 ms 3.277 ms 2 16 /f xw 16.38 ms 13.11 ms 6.554 ms 2 17 /f xw 32.77 ms 26.21 ms 13.11 ms 2 18 /f xw 65.54 ms 52.43 ms 26.21 ms 2 19 /f xw 131.1 ms 104.9 ms 52.43 ms 2 21 /f xw 524.3 ms 419.4 ms 209.7 ms remark f xw = f x : watchdog timer 1 clock frequency
chapter 11 watchdog timer functions user?s manual u17705ej2v0ud 347 11.2 watchdog timer 2 11.2.1 functions watchdog timer 2 has the following functions. ? default start watchdog timer note 1 reset mode: reset operation upon overflow of watchdog timer 2 (generation of wdtres2 signal) non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2 signal) note 2 ? input selectable from main clock and subclock as the source clock notes 1. watchdog timer 2 automatically starts in t he reset mode following reset release. when watchdog timer 2 is not used, either stop its operation before reset is executed through this function, or clear once watchdog timer 2 and stop it within the next interval time. also, write to the wdtm2 register for verifi cation purposes only once, even if the default settings (reset mode, interval time: f xx /2 25 ) need not be changed. 2. for non-maskable interrupt servicing due to a non -maskable interrupt request signal (intwdt2), refer to 17.10 cautions . figure 11-2. block diagra m of watchdog timer 2 f xx /2 9 clock input controller output controller wdtres2 (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 f xt wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f xx /2 18 to f xx /2 25 or f xt /2 9 to f xt /2 16 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 3 2 clear remark f xx : main clock frequency f xt : subclock frequency intwdt2: non-maskable interrupt request signal through watchdog timer 2 wdtres2: watchdog timer 2 reset signal
chapter 11 watchdog timer functions user?s manual u17705ej2v0ud 348 11.2.2 configuration watchdog timer 2 includes the following hardware. table 11-4. configuration of watchdog timer 2 item configuration control register watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) 11.2.3 registers (1) watchdog timer mode register 2 (wdtm2) this register sets the overflow time and operation clock of watchdog timer 2. the wdtm2 register can be read or writt en in 8-bit units. this register c an be read any number of times, but it can be written only once following reset release. reset sets wdtm2 to 67h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm2 register. for details, refer to 3.4.8 (2). 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2) reset mode (generation of wdtres2) wdm21 0 0 1 wdm20 0 1 ? selection of operation mode of watchdog timer 2 cautions 1. to stop the operation of watchdog ti mer 2, write ?1fh? to the wdtm2 register. 2. for details about bits wdcs0 to wdcs4, refer to table 11-5 watchdog timer 2 clock selection. 3. if the wdtm2 register is written twice afte r a reset, an overflow signal is forcibly output. 4. to intentionally generate an overflow signa l, write data to the wdtm2 register only twice, or write a value other than ?ach? to the wdte register only once. however, when watchdog timer 2 is set to stop operation, an overflow signal is not generated even if data is written to the wdtm2 register only twice, or a value other than ?ach? is written to the wdte register only once.
chapter 11 watchdog timer functions user?s manual u17705ej2v0ud 349 table 11-5. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 selected clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 0 0 0 0 0 2 18 /f xx 13.1 ms 16.4 ms 26.2 ms 0 0 0 0 1 2 19 /f xx 26.2 ms 32.8 ms 52.4 ms 0 0 0 1 0 2 20 /f xx 52.4 ms 65.5 ms 104.9 ms 0 0 0 1 1 2 21 /f xx 104.9 ms 131.1 ms 209.7 ms 0 0 1 0 0 2 22 /f xx 209.7 ms 262.1 ms 419.4 ms 0 0 1 0 1 2 23 /f xx 419.4 ms 524.3 ms 838.9 ms 0 0 1 1 0 2 24 /f xx 838.9 ms 1048.6 ms 1677.7 ms 0 0 1 1 1 2 25 /f xx 1677.7 ms 2097.2 ms 3355.4 ms 0 1 0 0 0 2 9 /f xt 15.625 ms (f xt = 32.768 khz) 0 1 0 0 1 2 10 /f xt 31.25 ms (f xt = 32.768 khz) 0 1 0 1 0 2 11 /f xt 62.5 ms (f xt = 32.768 khz) 0 1 0 1 1 2 12 /f xt 125 ms (f xt = 32.768 khz) 0 1 1 0 0 2 13 /f xt 250 ms (f xt = 32.768 khz) 0 1 1 0 1 2 14 /f xt 500 ms (f xt = 32.768 khz) 0 1 1 1 0 2 15 /f xt 1000 ms (f xt = 32.768 khz) 0 1 1 1 1 2 16 /f xt 2000 ms (f xt = 32.768 khz) 1 operation stopped (2) watchdog timer enable register (wdte) the counter of watchdog timer 2 is cl eared and counting restarted by writin g ?ach? to the wdte register. the wdte register can be read or written in 8-bit units. reset sets wdte to 9ah. wdte after reset: 9ah r/w address: fffff6d1h cautions 1. when a value other th an ?ach? is written to the wdte register, an overflow signal is forcibly output. 2. when a 1-bit memory manipulation instru ction is executed for the wdte register, an overflow signal is forcibly output. 3. the read value of the wdte register is a lways ?9ah? (value that differs from written value ?ach?). 4. to intentionally generate an overflow signal, write a value other than ?ach? to the wdte register only once, or write data to the wdtm2 register only twice. however, when watchdog timer 2 is set to stop operation, an overflow signal is not generated even if data is written to the wdtm2 register only twice, or a value other than ?ach? is written to the wdte register only once.
chapter 11 watchdog timer functions user?s manual u17705ej2v0ud 350 11.2.4 operation watchdog timer 2 automatically starts in t he reset mode following reset release. the wdtm2 register can be written to only once following reset through byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm 2 register using 8-bit memory manipulation instructions. after this is done, the operation of watchdog timer 2 cannot be stopped. the watchdog timer 2 program loop detection time in terval can be selected by the wdtm2.wdcs24 to wdtm2.wdcs20 bits. writing ach to the wdte register clears the counter of watchdog timer 2 and starts the count operation again. after the count operat ion starts, write ach to the wdte r egister within the set program loop detection time interval. if the program loop detection time is exceeded without a ch being written to the wdte register, a reset signal (wdtres2) or non-maskable interrupt request signal (i ntwdt2) is generated depending on the set value of the wdtm2.wdm21 and wdtm2.wdm20 bits. to not use watchdog timer 2, writ e 1fh to the wdtm2 register. for non-maskable interrupt servicing when the non -maskable interrupt request mode is set, refer to 17.10 cautions . if the main clock is selected as the source clock of wa tchdog timer 2, the watchdog timer stops operation in the idle/stop mode. therefore, clear wa tchdog timer 2 by writing ach to the wdte register before the idle/stop mode is set. because watchdog timer 2 operates in the halt mode or w hen the subclock is selected as its source clock in the idle/stop mode, exercise care that the ti mer does not overflow in the halt mode.
user?s manual u17705ej2v0ud 351 chapter 12 real-time output function (rto) 12.1 function the real-time output function (rto) transfers preset data to the rtbl0 and rtbh0 registers, and then transfers this data with hardware to an external device via the r eal-time output latches, upon occurr ence of a timer interrupt. the pins through which the data is output to an external device constitute a port called a real-time output port. because rto can output signal without jitter, it is suitable for controlling a stepping motor. in the v850es/ke2, a 6-bit real-time output port channel is provided. the real-time output port can be se t in the port mode or real-time output port mode in 1-bit units. the block diagram of rto is shown below. figure 12-1. block diagram of rto real-time buffer register 0h (rtbh0) real-time output latch 0h selector inttm50 inttm51 real-time output latch 0l rtpoe0 rtpeg0 byte0 extr0 real-time output port control register 0 (rtpc0) transfer trigger (h) transfer trigger (l) rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 real-time output port mode register 0 (rtpm0) 4 2 2 4 internal bus real-time buffer register 0l (rtbl0) rtpout04, rtpout05 rtpout00 to rtpout03
chapter 12 real-time output function (rto) user?s manual u17705ej2v0ud 352 12.2 configuration rto includes the following hardware. table 12-1. configuration of rto item configuration registers real-time output buffe r register 0 (rtbl0, rtbh0) control registers real-time output port mode register 0 (rtpm0) real-time output port control register 0 (rtpc0) (1) real-time output buffer register 0 (rtbl0, rtbh0) rtbl0 and rtbh0 are 4-bit registers t hat hold output data in advance. these registers are mapped to independent addresses in the peripheral i/o register area. they can be read or written in 8-bit or 1-bit units. if an operation mode of 4 bits 1 channel or 2 bits 1 channel is specified (rtpc0.byte0 bit = 0), data can be individually set to the rtbl0 and rtbh0 registers. the data of both these r egisters can be read at once by specifying the address of ei ther of these registers. if an operation mode of 6 bits 1 channel is specified (byte0 bit = 1), 8-bit data can be set to both the rtbl0 and rtbh0 registers by writing the da ta to either of these registers. moreover, the data of both these registers can be read at once by specifying t he address of either of these registers. table 12-2 shows the operation when the rt bl0 and rtbh0 register s are manipulated. 0 rtbl0 rtbh0 0 rtbh05 rtbh04 rtbl03 rtbl02 rtbl01 rtbl00 after reset: 00h r/w address: rtbl0 fffff6e0h, rtbh0 fffff6e2h cautions 1. when writing to bits 6 and 7 of the rtbh0 register, always write 0. 2. when the main clock is stopped and the cpu is operating on the subclock, do not access the rtbl0 and rtbh0 registers. for details, refer to 3.4.8 (2). table 12-2. operation during manipul ation of rtbl0 and rtbh0 registers read write note operation mode register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl0 rtbh0 rtbl0 invalid rtbl0 4 bits 1 channel, 2 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 invalid rtbl0 rtbh0 rtbl0 rtbh0 rtbl0 6 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 rtbl0 note after setting the real-time output port, set output data to the rtbl0 and rtbh0 registers by the time a real- time output trigger is generated.
chapter 12 real-time output function (rto) user?s manual u17705ej2v0ud 353 12.3 registers rto is controlled using the foll owing two types of registers. ? real-time output port mode register 0 (rtpm0) ? real-time output port control register 0 (rtpc0) (1) real-time output port mode register 0 (rtpm0) this register selects the real-time output port mode or port mode in 1-bit units. the rtpm0 register can be read or written in 8-bit or 1-bit units. reset sets rtpm0 to 00h. 0 rtpm0m 0 1 real-time output disabled real-time output enabled control of real-time output port (m = 0 to 5) rtpm0 0 rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 after reset: 00h r/w address: fffff6e4h cautions 1. to reflect real-time output signa ls (rtpout00 to rtpout05) to the pins (rtp00 to rtp05), set them to the r eal-time output port with the pmc5 and pfc5 registers. 2. by enabling real-time output operation (rtpc0.rtpoe0 bit = 1), the bits specified as real-time outpu t enabled perform real-time output, and the bits specified as real-time out put disabled output 0. 3. if real-time output is disabled (r tpoe0 bit = 0), real-time output signals (rtpout00 to rtpout05) all output 0, regardless of the rtpm0 register setting.
chapter 12 real-time output function (rto) user?s manual u17705ej2v0ud 354 (2) real-time output port control register 0 (rtpc0) this register sets the operation mode and ou tput trigger of the real-time output port. the relationship between the operation mo de and output trigger of the real -time output port is as shown in table 12-3. the rtpc0 register can be read or written in 8-bit or 1-bit units. reset sets rtpc0 to 00h. rtpoe0 disables operation note 3 enables operation rtpoe0 0 1 control of real-time output operation rtpc0 rtpeg0 note 1 byte0 extr0 note 2 00 0 0 4 bits 1 channel, 2 bits 1 channel 6 bits 1 channel byte0 0 1 specification of channel configuration for real-time output after reset: 00h r/w address: fffff6e5h < > notes 1. the value of the rtpeg0 bit does not affect the operation. 2. for the extr0 bit, refer to table 12-3 . 3. when real-time output operation is dis abled (rtpoe0 bit = 0), real-time output signals (rtpout00 to rtpout05) all output 0. caution perform the settings for the byte0 an d extr0 bits only when the rtpoe0 bit = 0. table 12-3. operation modes and output triggers of real-time output port byte0 extr0 operation mode rtbh0 (rtp 04, rtp05) rtbl0 (rtp00 to rtp03) 0 inttm51 inttm50 0 1 4 bits 1 channel, 2 bits 1 channel inttm50 no trigger 0 inttm50 1 1 6 bits 1 channel setting prohibited
chapter 12 real-time output function (rto) user?s manual u17705ej2v0ud 355 12.4 operation if the real-time output operation is enabled by setting the rtpc0.rtpoe0 bi t to 1, the data of the rtbh0 and rtbl0 registers is transferred to the real-time output latch in synchronizati on with the generation of the selected transfer trigger (set by the rtpc0.extr0 and rtpc0.byte0 bits). of the trans ferred data, only the data of the bits specified as real-time output enabled by the rtpm0 register is output from bi ts rtpout00 to rtpo ut05. the bits specified as real-time output disabled by the rtpm0 register output 0. if the real-time output operatio n is disabled by clearing the rtpoe0 bi t to 0, the rtpout00 to rtpout05 signals output 0 regardless of the setti ng of the rtpm0 register. figure 12-2. example of operation timing of rto0 (when extr0 and byte0 bits = 00) abababab d01 d02 d03 d04 d11 d12 d13 d14 d11 d12 d13 d14 d01 d02 d03 d04 inttm51 (internal) inttm50 (internal) cpu operation rtbh0 rtbl0 rt output latch 0 (h) rt output latch 0 (l) a: software processing by inttm51 interrupt request signal (write to rtbh0 register) b: software processing by inttm50 interrupt request signal (write to rtbl0 register) remark for the operation during standby, refer to chapter 19 standby function .
chapter 12 real-time output function (rto) user?s manual u17705ej2v0ud 356 12.5 usage (1) disable real-time output. clear the rtpc0.rtpoe0 bit to 0. (2) perform initializa tion as follows. ? specify the real-time output port m ode or port mode in 1-bit units. set the rtpm0 register. ? channel configuration: select the trigger and valid edge. set the rtpc0.extr0, rtpc0.byt e0, and rtpc0.rtpeg0 bits. ? set the initial values to the rtbh0 and rtbl0 registers note 1 . (3) enable real-time output. set the rtpoe0 bit to 1. (4) set the next output value to the rtbh0 and rtbl0 registers by the time the selected transfer trigger is generated note 2 . (5) set the next real-time output value to the rtbh0 and rtbl0 regi sters through interrupt servicing corresponding to the selected trigger. notes 1. if write to the rtbh0 and rtbl0 registers is per formed when the rtpoe0 bit = 0, that value is transferred to real-time output latches 0h and 0l, respectively. 2. even if write is performed to t he rtbh0 and rtbl0 registers when th e rtpoe0 bit = 1, data transfer to real-time output latches 0h and 0l is not performed. caution to reflect the real-time out put signals (rtpout00 to rtpout05) to the pi ns, set the real-time output ports (rtp00 to rtp05) with the pmc5 and pfc5 registers. 12.6 cautions (1) prevent the following conflicts by software. ? conflict between real-time output disable/enable s witching (rtpoe0 bit) and selected real-time output trigger ? conflict between write to the rtbh0 and rtbl0 regist ers in the real-time output enabled status and the selected real-time output trigger. (2) before performing initialization, disable real-time output (rtpoe0 bit = 0). (3) once real-time output has been disabled (rtpoe0 bit = 0), be sure to initialize the rtbh0 and rtbl0 registers before enabling real-time output again (rtpoe0 bit = 0 1).
chapter 12 real-time output function (rto) user?s manual u17705ej2v0ud 357 12.7 security function a circuit that sets the pin outputs to high impedance as a security functi on for when malfunctions of a stepping motor controlled by rto occur is provided on chip. it fo rcibly resets the pins allocated to rtp00 to rtp05 via external interrupt intp0 pin edge detection, placing them in t he high-impedance state. the ports (p50 to p55 pins) placed in high impedance by intp0 note 1 pin are initialized note 2 , so settings for these ports must be performed again. notes 1. regardless of the port settings, p50 to p55 pins are all placed in high impedance via the intp0 pin. 2. the bits that are initialized are a ll the bits corresponding to p50 to p 55 pins of the following registers. ? p5 register ? pm5 register ? pmc5 register ? pu5 register ? pfc5 register the block diagram of the security function is shown below. figure 12-3. block diagra m of security function edge detection intc intp0 rtost0 rtpout00 to rtpout05 rtp00 to rtp05 ev dd r 6 this function is set with the pllctl.rtost0 bit.
chapter 12 real-time output function (rto) user?s manual u17705ej2v0ud 358 (1) pll control register (pllctl) the pllctl register is an 8-bit register that controls the rto security function and pll. this register can be read or writt en in 8-bit or 1-bit units. reset sets pllctl to 01h. 0 pllctl 0 0 0 0 rtost0 selpll note pllon note intp0 pin is not used as trigger for security function intp0 pin is used as trigger for security function rtost0 0 1 control of rtp00 to rtp05 security function after reset: 01h r/w address: fffff806h < > < > < > note for details on the selpll and pllon bits, refer to chapter 5 clock generation function . cautions 1. before outputting a value to the real-time output po rts (rtp00 to rtp05), select the intp0 pin interrupt edge det ection and then set the rtost0 bit. 2. to set again the ports (p50 to p 55 pins) as real-time output ports after placing them in high impedance via th e intp0 pin, first cancel the security function. [procedure to set ports again] <1> cancel the security function and enable port setting by clearing the rtost0 bit to 0. <2> set the rtost0 bit to 1 (only if required). <3> set again as real-time output port. 3. be sure to clear bits 4 to 7 to ?0?. changing bit 3 does not affect the operation.
user?s manual u17705ej2v0ud 359 chapter 13 a/d converter 13.1 overview the a/d converter converts analog input signals into digital values and has an 8-channel (ani0 to ani7) configuration. the a/d converter has the following functions. operating voltage (av ref0 ): 2.7 to 5.5 v successive approximation method 10-bit a/d converter analog input pin: 8 trigger mode: ? software trigger mode ? timer trigger mode (inttm010) ? external trigger mode (adtrg pin) operation mode ? select mode ? scan mode a/d conversion time: ? normal mode: 14 to 100 s @ 4.0 v av ref0 5.5 v 17 to 100 s @ 2.7 v av ref0 < 4.0 v ? high-speed mode: 3 to 100 s @ 4.5 v av ref0 5.5 v 4.8 to 100 s @ 4.0 v av ref0 < 4.5 v 6 to 100 s @ 2.85 v av ref0 < 4.0 v 14 to 100 s @ 2.7 v av ref0 < 2.85 v power fail detection function caution when using the a/d converter, operate with av ref0 at the same potential as v dd and ev dd . 13.2 functions (1) 10-bit resolution a/d conversion 1 analog input channel is selected from the ani0 to ani7 pins, and an a/d conversion operation with resolution of 10 bits is repeatedly executed. every ti me a/d conversion is completed, an interrupt request signal (intad) is generated. (2) power fail detection function this is a function to detect low voltage in a battery. the results of a/d conversi on (the value in the adcrh register) and the pft register are compared, and in tad signal is generated only when the comparison conditions match.
chapter 13 a/d converter user?s manual u17705ej2v0ud 360 13.3 configuration the a/d converter includes the following hardware. figure 13-1. block diag ram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 av ref0 av ss intad adcs bit 3 ads2 ads1 ads0 ega1 ega0 trg adtmd fr0 adhs1 adhs0 adcs2 adcs admd fr2 fr1 sample & hold circuit av ss voltage comparator controller edge detector adtrg inttm010 adcr/adcrh register pft register ads register adm register pfen pfcm pfm register internal bus sar register comparator tap selector selector selector table 13-1. registers of a/ d converter used by software item configuration registers a/d conversion result register (adcr) a/d conversion result register h (adcrh): only higher 8 bits can be read power fail comparison threshold register (pft) a/d converter mode register (adm) analog input channel specification register (ads) power fail comparison mode register (pfm)
chapter 13 a/d converter user?s manual u17705ej2v0ud 361 (1) ani0 to ani7 pins these are analog input pins for the 8 channels of the a/ d converter. they are used to input analog signals to be converted into digital signals. pins other than thos e selected as analog input by the ads register can be used as input ports. (2) sample & hold circuit the sample & hold circuit samples the analog input si gnals selected by the input circuit and sends the sampled data to the voltage comparator. this ci rcuit holds the sampled analog input voltage during a/d conversion. (3) series resistor string the series resistor string is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (4) voltage comparator the voltage comparator com pares the value that is sampled and hel d with the output voltage of the series resistor string. (5) successive approximation register (sar) this register compares the sampled analog voltage value with the voltage value from the series resistor string, and converts the comparison result starti ng from the most significant bit (msb). when the least significant bit (lsb) has been converted to a digital value (end of a/d conversion), the contents of the sar register are transfe rred to the adcr register. the sar register cannot be read or written directly. (6) a/d conversion result register (adcr) , a/d conversion result register h (adcrh) each time a/d conversion ends, the conversion results are loaded from the successive approximation register and the results of a/d conversion are held in the higher 10 bits of this regist er (the lower 6 bits are fixed to 0). (7) controller the controller compares the a/d c onversion results (the value of the adcrh register) with the value of the pft register when a/d conversion ends or the power fail detection function is used. it generates intad signal only when the comparison conditions match. (8) av ref0 pin this is the analog power supply pin/reference voltage input pin of the a/d converter. always use the same potential as the v dd pin even when not using the a/d converter. the signals input to the ani0 to ani7 pins are conv erted into digital signals based on the voltage applied across av ref0 and av ss . (9) av ss pin this is the ground potential pin of the a/d converter. always use the same potential as the v ss pin even when not using the a/d converter.
chapter 13 a/d converter user?s manual u17705ej2v0ud 362 (10) a/d converter mode register (adm) this register sets the conversion time of the analog input to be converted to a digital signal and the conversion operation start/stop. (11) analog input channel sp ecification register (ads) this register specifies the input port for the analog voltage to be converted to a digital signal. (12) power fail comparis on mode register (pfm) this register sets the power fail detection mode. (13) power fail comparison threshold register (pft) this register sets the threshold to be compared with the adcr register. 13.4 registers the a/d converter is controlle d by the following registers. ? a/d converter mode register (adm) ? analog input channel specification register (ads) ? power fail comparison mode register (pfm) ? power fail comparison threshold register (pft) ? a/d conversion result register, a/d c onversion result register h (adcr, adcrh) (1) a/d converter mode register (adm) this register sets the conversion time of the analog input signal to be convert ed into a digital signal as well as conversion start and stop. the adm register can be read or wr itten in 8-bit or 1-bit units. reset sets this register to 00h.
chapter 13 a/d converter user?s manual u17705ej2v0ud 363 adcs adcs 0 1 conversion operation stopped conversion operation enabled control of a/d conversion operation adm admd fr2 note 1 fr1 note 1 fr0 note 1 adhs1 note 1 adhs0 note 1 adcs2 admd 0 1 select mode scan mode control of operation mode adhs1 0 1 normal mode high-speed mode (valid only when av ref0 4.5 v) selection of 5 v a/d conversion time mode (av ref0 4.5 v) adhs0 0 1 normal mode high-speed mode (valid only when av ref0 2.7 or 2.85 v) selection of 3 v a/d conversion time mode (av ref0 2.7 or 2.85 v) after reset: 00h r/w address: fffff200h adcs2 0 1 reference voltage generator operation stopped reference voltage generator operation enabled control of reference voltage generator for boosting note 2 < > < > notes 1. for details of the fr2 to fr0 bits and the a/d conversion, refer to table 13-2 a/d conversion time . 2. the operation of the reference vo ltage generator for boosting is controlled by the adcs bit and it takes 1 s (high-speed mode) or 14 s (normal mode) after operation is started until it is stabilized. therefore, the adcs2 bit is set to 1 (a /d conversion is started) at least 1 s (high-speed mode) or 14 s (normal mode) after if the adcs2 bit was set to 1 (reference voltage generator for boosting is on), the first conversion result is valid. cautions 1. writing to the adm register is proh ibited during a/d conversi on operation (adcs bit = 1) in normal mode (adhs1, adhs0 bits = 00). if the same value is written to the adm re gister during a/d conversion operation in high- speed mode (adhs1, adhs0 bits = 10 or 01) , conversion is aborte d and started again from the beginning. writing to the fr2 to fr0, adhs1, and adhs0 bits is prohibited during the a/d conversion operation. 2. setting adhs1 and adhs0 bits to 11 is prohibited. 3. do not access the adm regi ster when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2) access to special on-chip peripheral i/o register.
chapter 13 a/d converter user?s manual u17705ej2v0ud 364 table 13-2. a/d conversion time a/d conversion time ( s) adhs1 adhs0 fr2 fr1 fr0 20 mhz@ av ref0 4.5 v 16 mhz@ av ref0 4.0 v 8 mhz@ av ref0 2.85 v 8 mhz@ av ref0 2.7 v conversion time mode 0 0 0 0 0 288/f xx 14.4 18.0 36.0 36.0 0 0 0 0 1 240/f xx setting prohibited 15.0 30.0 30.0 0 0 0 1 0 192/f xx setting prohibited setting prohibited 24.0 24.0 normal mode av ref0 2.7 v 0 0 0 1 1 setting prohibited 0 0 1 0 0 144/f xx setting prohibited setting prohibited 18.0 18.0 0 0 1 0 1 120/f xx setting prohibited setting prohibited setting prohibited setting prohibited 0 0 1 1 0 96/f xx setting prohibited setting prohibited setting prohibited setting prohibited normal mode av ref0 2.7 v 0 0 1 1 1 setting prohibited 0 1 0 0 0 96/f xx 4.8 6.0 12.0 setting prohibited 0 1 0 0 1 72/f xx setting prohibited setting prohibited 9.0 setting prohibited 0 1 0 1 0 48/f xx setting prohibited setting prohibited 6.0 setting prohibited 0 1 0 1 1 24/f xx setting prohibited setting prohibited setting prohibited setting prohibited high-speed mode av ref0 2.85 v 0 1 1 0 0 224/f xx 11.2 14.0 28.0 28.0 0 1 1 0 1 168/f xx setting prohibited 10.5 21.0 21.0 0 1 1 1 0 112/f xx setting prohibited setting prohibited setting prohibited setting prohibited 0 1 1 1 1 56/f xx setting prohibited setting prohibited setting prohibited setting prohibited high-speed mode av ref0 2.7 v 1 0 0 0 0 72/f xx 3.6 setting prohibited setting prohibited setting prohibited 1 0 0 0 1 54/f xx setting prohibited setting prohibited setting prohibited setting prohibited 1 0 0 1 0 36/f xx setting prohibited setting prohibited setting prohibited setting prohibited 1 0 0 1 1 18/f xx setting prohibited setting prohibited setting prohibited setting prohibited high-speed mode av ref0 4.5 v 1 0 1 setting prohibited 1 1 setting prohibited
chapter 13 a/d converter user?s manual u17705ej2v0ud 365 (a) controlling reference volt age generator for boosting when the adcs2 bit = 0, power to the a/d converter drops. the converter requires a setup time of 1 s (high-speed mode) or 14 s (normal mode) or more after the adcs2 bit has been set to 1. therefore, the result of a/ d conversion becomes valid from the first result by setting the adcs bit to 1 at least 1 s (high-speed mode) or 14 s (normal mode) after the adcs2 bit has been set to 1. table 13-3. setting of adcs bit and adcs2 bit adcs adcs2 a/d co nversion operation 0 0 stopped status (dc power consumption path does not exist) 0 1 conversion standby mode (only the refer ence voltage generator for boosting consumes power) 1 0 conversion mode (reference voltage generator stops operation note 1 ) 1 1 conversion mode (reference voltage generator is operating note 2 ) notes 1. if the adcs and adcs2 bits are changed from 00b to 10b, the reference voltage generator for boosting automatically turns on. if the adcs bit is cleared to 0 while the adcs2 bit is 0, the voltage generator automatically turns off. in the software trigger mode (ads.trg bit = 0), use of the first a/d conversion result is prohibited. in the hardware trigger mode (trg bit = 1), use t he a/d conversion result on ly if a/d conversion is started after the lapse of the o scillation stabilization time of t he reference voltage generator for boosting. 2. if the adcs and adcs2 bits are changed from 00b to 11b, the reference voltage generator for boosting automatically turns on. if the adcs bit is cleared to 0 while the adcs2 bit is 1, the voltage generator stays on. in the software trigger mode (trg bit = 0), use of the first a/d conversion result is prohibited. in the hardware trigger mode (trg bit = 1), use t he a/d conversion result on ly if a/d conversion is started after the lapse of the o scillation stabilization time of t he reference voltage generator for boosting. figure 13-2. operation sequence comparator control conversion operation conversion standby conversion operation conversion stop adcs adcs2 note reference voltage generator for boosting: operating note 1 s (high-speed mode) or 14 s (normal mode) or more are required for the operation of the reference voltage generator for boosting between when the adcs2 bit is set (1) and when the adcs bit is set (1).
chapter 13 a/d converter user?s manual u17705ej2v0ud 366 (2) analog input channel specification register (ads) this register specifies the analog vo ltage input port for a/d conversion. the ads register can be read or wr itten in 8-bit or 1-bit units. reset sets ads to 00h. ega1 note 1 ads ega0 note 1 trg adtmd note 2 0 ads2 ads1 ads0 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani0 ani0, ani1 ani0 to ani2 ani0 to ani3 ani0 to ani4 ani0 to ani5 ani0 to ani6 ani0 to ani7 ads2 0 0 0 0 1 1 1 1 ads1 0 0 1 1 0 0 1 1 ads0 0 1 0 1 0 1 0 1 specification of analog input channel select mode scan mode no edge detection falling edge rising edge both rising and falling edges ega1 note 1 0 0 1 1 ega0 note 1 0 1 0 1 specification of external trigger signal (adtrg) edge after reset: 00h r/w address: fffff201h trg 0 1 software trigger mode hardware trigger mode trigger mode selection adtmd note 2 0 1 external trigger (adtrg pin input) timer trigger (inttm010 signal generated) specification of hardware trigger mode notes 1. the ega1 and ega0 bits are valid only when t he hardware trigger mode (trg bit = 1) and external trigger mode (adtrg pin input: adtmd bit = 1) are selected. 2. the adtmd bit is valid only when the hardware trigger mode (trg bit = 1) is selected. cautions 1. writing to the ads register is pr ohibited during a/d conversion operation (adm.adcs bit = 1) in normal mode (adm.adhs1, adm.adhs0 bits = 00). 2. inputting software/hardware triggers redundantly is prohibited during a/d conversion operation (adcs bit = 1) in normal mode (adhs1, adhs0 bits = 00). 3. do not access the ads regi ster when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2) access to special on-chip peripheral i/o register. 4. be sure to clear bit 3 to ?0?.
chapter 13 a/d converter user?s manual u17705ej2v0ud 367 (3) a/d conversion result register, a/d conversion result register h (adcr, adcrh) the adcr and adcrh registers stor e the a/d conversion results. these registers are read-only in 16-bit or 8-bit units. however, specify the adcr register for 16-bit access, and the adcrh register for 8-bit access. in the adcr r egister, the 10 bits of conversion results are read in the higher 10 bits and 0 is read in the lower 6 bits. in the adcrh register, the higher 8 bits of the conversion results are read. reset makes these registers undefined. after reset: undefined r address: fffff204h adcr ad9 ad8 ad7 ad6 ad0 0 0 0 0 0 0 ad1 ad2 ad3 ad4 ad5 ad9 adcrh ad8 ad7 ad6 ad5 ad4 ad3 ad2 76 54 32 1 0 after reset: undefined r address: fffff205h caution do not access the adcr and adcrh registers when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2 ) access to special on-chip peripheral i/o register.
chapter 13 a/d converter user?s manual u17705ej2v0ud 368 the following shows the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and a/d conversion results (adcr register). sar = int ( 1024 + 0.5) adcr note = sar 64 or, (sar ? 0.5) v in < (sar + 0.5) int ( ): function that returns the in teger part of the value in parentheses v in : analog input voltage av ref0 : voltage of av ref0 pin adcr: value in the adcr register note the lower 6 bits of the a dcr register are fixed to 0. the following shows the relationship between the ana log input voltage and a/ d conversion results. figure 13-3. relationship between analog input voltage and a/d conversion results 1023 1022 1021 ffc0h ff80h ff40h 3 2 1 0 00c0h 0080h 0040h 0000h input voltage/av ref0 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 a/d conversion results sar adcr v in av ref0 av ref0 1024 av ref0 1024
chapter 13 a/d converter user?s manual u17705ej2v0ud 369 (4) power fail comparison mode register (pfm) this register sets the power fail detection mode. the pfm register compares the value in the p ft register with the val ue of the adcrh register. the pfm register can be read or wr itten in 8-bit or 1-bit units. reset sets this register to 00h. pfen pfen 0 1 power fail comparison disabled power fail comparison enabled selection of power fail comparison enable/disable pfm pfcm 0 0 0 0 0 0 pfcm 0 1 interrupt request signal (intad) generated when adcr pft interrupt request signal (intad) generated when adcr < pft selection of power fail comparison mode after reset: 00h r/w address: fffff202h < > < > cautions 1. writing to the pfm register is prohibited during a/d conversion operation (adm.adcs bit = 1) in normal mode (adm.adhs1, adm.adhs0 bits = 00). 2. do not access the pfm register when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2) access to special on- chip peripheral i/o register. (5) power fail comparison th reshold register (pft) the pft register sets the comparison value in the power fail detection mode. the 8-bit data set in the pft register is co mpared with the value of the adcrh register. the pft register can be read or written in 8-bit units. reset sets this register to 00h. pft after reset: 00h r/w address: fffff203h 76 54 321 0 cautions 1. writing to the pft register is prohibited during a/d conversion operation (adm.adcs bit = 1) in normal mode (adm.adhs1, adm.adhs0 bits = 00). 2 do not access the pft register when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2) access to special on- chip peripheral i/o register.
chapter 13 a/d converter user?s manual u17705ej2v0ud 370 13.5 operation 13.5.1 basic operation <1> select the channel whose analog signal is to be c onverted into a digital signal using the ads register. set the adm.adhs1 or adm.adhs0 bit. <2> set the adm.adcs2 bit to 1 and wait 1 s (high-speed mode) or 14 s (normal mode) or longer. <3> set the adm.adcs bit to 1 to start a/d conversion. (steps <4> to <10> are executed by hardware.) <4> the sample & hold circuit samples the voltage input to the selected analog input channel. <5> after sampling for a specific time, the sample & hold circuit enters the hold stat us and holds the input analog voltage until it has been converted into a digital signal. <6> set bit 9 of the successive approximation register (sar) to 1. the tap selector sets the voltage tap of the series resistor string to (1/2) av ref0 . <7> the voltage comparator compares t he voltage difference between the voltage tap of the series resistor string and the analog input voltage. if the ana log input voltage is greater than (1/2) av ref0 , the msb of the sar register remains set to 1. if the analog input voltage is less than (1/2) av ref0 , the msb is cleared to 0. <8> next, bit 8 of the sar register is automatically se t to 1 and the next comparison starts. depending on the previously determined value of bit 9, the voltage tap of the series resistor string is selected as follows. ? bit 9 = 1: (3/4) av ref0 ? bit 9 = 0: (1/4) av ref0 the analog input voltage is compared with one of th ese voltage taps and bit 8 of the sar register is manipulated as follows depending on the result of the comparison. analog input voltage voltage tap: bit 8 = 1 analog input voltage voltage tap: bit 8 = 0 <9> the above steps are repeated until bit 0 of the sar register has been manipulated. <10> when comparison of all 10 bits of the sar register ha s been completed, the valid digital value remains in the sar register, and the value of the sar register is transferred and latched to the adcr register. at the same time, an a/d conversion end interrupt request signal (intad) is generated. <11> repeat steps <4> to <10> until the adcs bit is cleared to 0. for another a/d conversion, start at <3>. however, when operating the a/d converter with the adcs2 bit cleared to 0, start at <2>.
chapter 13 a/d converter user?s manual u17705ej2v0ud 371 13.5.2 trigger modes the v850es/ke2 has the following three trigger modes that set the a/d conver sion start timing. these trigger modes are set by the ads register. ? software trigger mode ? external trigger mode (hardware trigger mode) ? timer trigger mode (hardware trigger mode) (1) software trigger mode this mode is used to start a/d conversion by setting t he adm.adcs bit to 1 while the ads.trg bit is 0. conversion is repeatedly performed as long as the a dcs bit is not cleared to 0 after completion of a/d conversion. if the adm, ads, pfm, or pft register is writt en during conversion in high-speed mode (adm.adhs1, adm.adhs0 bits = 01 or 10), a/d conv ersion is aborted and started again fr om the beginning. writing to the adm, ads, pfm, or pft register is prohibited duri ng conversion in normal mode (adhs1, adhs0 bits = 00). (2) external trigger mode (hardware trigger mode) use this mode by setting to high-speed mode (adhs1, adhs 0 bits = 10 or 01). inputting a valid edge to the adtrg pin is prohibited during a/d conversion in normal mode (adhs1, adhs0 bits = 00). this mode is used to start a/d conver sion by detecting an external trig ger (adtrg) after the adcs bit has been set to 1 with the trg and ads.adtmd bits set to 1 and 0 respectively. the a/d converter waits for the external trigge r (adtrg) after the adcs bit is set to 1. the valid edge of the signal input to the adtrg pin is specified by using the ads. ega1 and ads.ega0 bits. when the specified valid edge is det ected, a/d conversion is started. when a/d conversion is completed, the a/d converte r waits for the external trigger (adtrg) again. if a valid edge is input to the adtrg pin during a/d conversion in high-speed mode (adhs1, adhs0 bits = 01 or 10), a/d conversion is aborted a nd started again from the beginning. if the adm, ads, pfm, or pft regist er is written during conversion in high-speed mode (adhs1, adhs0 bits = 01 or 10), a/d conversion is aborted and the a/d c onverter waits for an external trigger (adtrg). (3) timer trigger mode (hardware trigger mode) use this mode by setting to high-speed mode (adhs1, adhs 0 bits = 10 or 01). inputting a valid edge to the adtrg pin is prohibited during a/d conversion in normal mode (adhs1, adhs0 bits = 00). this mode is used to start a/d conversion by detecti ng a timer trigger (inttm010) after the adcs bit has been set to 1 with the trg and adtmd bits both set to 1. the a/d converter waits for the timer trigger (inttm010) after the adcs bit is set to 1. when the inttm010 signal is generated, a/d conversion is started. when a/d conversion is completed, the a/d converte r waits for the timer trigger (inttm010) again. if the inttm010 signal is generated during a/d conversion in high-speed mode (adhs1, adhs0 bits = 01 or 10), a/d conversion is aborted and st arted again from the beginning. if the adm, ads, pfm, or pft regist er is written during conversion in high-speed mode (adhs1, adhs0 bits = 01 or 10), a/d conversion is aborted and the a/d converter waits for a timer trigger (inttm010).
chapter 13 a/d converter user?s manual u17705ej2v0ud 372 13.5.3 operation modes the following two operation modes are available. t hese operation modes are set by the adm register. ? select mode ? scan mode (1) select mode one input analog signal specified by the ads register while the adm.ad md bit = 0 is converted. when conversion is complete, the result of c onversion is stored in the adcr register. at the same time, the a/d conversion end interrupt r equest signal (intad) is generat ed. however, the intad signal may or may not be generated depending on setting of the pfm and pft registers. for details, refer to 13.5.4 power fail detection function . in the high-speed mode (adm.adhs1, ad m.adhs0 bits = 01 or 10), if any va lue is written to the adm, ads, pfm, and pft registers during conver sion, a/d conversion is aborted. in the software trigger mode, a/d conversion is started from the beginning again. in t he hardware trigger mode, the a/d converter waits for a trigger. in the normal mode (adhs1, adhs0 bits = 00), wr iting to the adm, ads, pfm, or pft register is prohibited during conversion. in the high-speed mode (adhs1, adhs0 bits = 01 or 10) , if the trigger is detec ted during conversion in hardware trigger mode, a/d conversi on is aborted and started again from the beginning. in the normal mode (adhs1, adhs0 bits = 00), inputting the trigger again is prohibited during a/d conversion. figure 13-4. example of select mode operat ion timing (ads.ads2 to ads.ads0 bits = 001b) ani1 a/d conversion data 1 (ani1) data 2 (ani1) data 1 data 2 data 1 (ani1) data 2 (ani1) adcr intad conversion start set adcs bit = 1 conversion start set adcs bit = 1 conversion end conversion end
chapter 13 a/d converter user?s manual u17705ej2v0ud 373 (2) scan mode in this mode, the analog signals specified by the ad s register and input from the ani0 pin while the adm.admd bit = 1 are sequentially selected and converted. when conversion of one analog input signal is complete, t he conversion result is st ored in the adcr register and, at the same time, the a/d conversion end interrupt request signal (intad) is generated. the a/d conversion results of all t he analog input signals are stored in t he adcr register. it is therefore recommended to save the contents of the adcr regist er to ram once a/d conversion of one analog input signal has been completed. in the hardware trigger mode (ads.trg bit = 1), the a/d converter waits for a trigger after it has completed in the high-speed mode (adm.adhs1, ad m.adhs0 bits = 01 or 10), if any va lue is written to the adm, ads, pfm, and pft registers during conver sion, a/d conversion is aborted. in the software trigger mode, a/d conversion is started from the beginning again. in t he hardware trigger mode, the a/d converter waits for a trigger. conversion starts again from the ani0 pin. in the normal mode (adhs1, adhs0 bits = 00), inputting a valid edge to the adtrg pin is prohibited during a/d conversion. in the high-speed mode (adhs1, adhs0 bits = 01 or 10) , if the trigger is detec ted during conversion in hardware trigger mode, a/d conversion is aborted and started again from t he beginning (ani0 pin). in the normal mode (adhs1, adhs0 bits = 00), writing to the ad m, ads, pfm, or pft register is prohibited during conversion.
chapter 13 a/d converter user?s manual u17705ej2v0ud 374 figure 13-5. example of scan mode operati on timing (ads.ads2 to ads.ads0 bits = 011b) (a) timing example adcr intad ani3 ani0 ani1 ani2 a/d conversion data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) conversion start set adcs bit = 1 conversion end set adcs bit = 0 data 1 data 2 data 3 data 4 (b) block diagram a/d converter adcr register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr
chapter 13 a/d converter user?s manual u17705ej2v0ud 375 13.5.4 power fail detection function the conversion end interrupt request si gnal (intad) can be controlled as fo llows using the pfm and pft registers. ? if the pfm.pfen bit = 0, the intad signal is generated each time conversion ends. ? if the pfen bit = 1 and the pfm.pfcm bi t = 0, the conversion result (adcrh register) and the value of the pft register are compared when conversion ends, and the intad signal is generated only if adcrh pft. ? if the pfen and pfcm bits = 1, the conversion result and the value of t he pft register are compared when conversion ends, and the intad signal is generated only if adcrh < pft. ? because, when the pfen bit = 1, the conversion result is overwritt en after the intad signal has been generated, unless the conversion result is read by the time the next conversion ends, in some cases it may appear as if the actual operation differs from the operation described above (refer to figure 13-6 ). figure 13-6. power fail detection function (pfcm bit = 0) conversion operation adcrh pft intad ani0 80h 80h 7fh 80h ani0 ani0 ani0 note note if reading is not performed during this interval, the conv ersion result changes to the next conversion result.
chapter 13 a/d converter user?s manual u17705ej2v0ud 376 13.5.5 setting method the following describes how to set registers. (1) when using the a/d converter for a/d conversion <1> set (1) the adm.adcs2 bit. <2> select the channel and conversion time by setting the ads.ads2 to ads.ads0 bits and the adm.adhs1, adm.adhs0, and adm.fr2 to adm.fr0 bits. <3> set (1) the adm.adcs bit. <4> transfer the a/d conversion data to the adcr register. <5> an interrupt request signal (intad) is generated. <6> change the channel by setting the ads2 to ads0 bits. <7> transfer the a/d conversion data to the adcr register. <8> the intad signal is generated. <9> clear (0) the adcs bit. <10> clear (0) the adcs2 bit. cautions 1. the time taken from <1> to <3> must be 1 s (high-speed mode) or 14 s (normal mode) or longer. 2. steps <1> and <2> may be reversed. 3. step <1> may be omitted. however, if om itted, do not use the first conversion result after <3>. 4. the time taken from <4> to <7> is differe nt from the conversion time set by the adhs1, adhs0, and fr2 to fr0 bits. the time taken for <6> and <7> is the c onversion time set by the adhs1, adhs0, and fr2 to fr0 bits. (2) when using the a/d converter for the power fail detection function <1> set (1) the pfm.pfen bit. <2> set the power fail comparison conditions by using the pfm.pfcm bit. <3> set (1) the adm.adcs2 bit. <4> select the channel and conversion time by setting the ads.ads2 to ads.ads0 bits and the adm.adhs1, adm.adhs0, and adm.fr2 to adm.fr0 bits. <5> set the threshold value in the pft register. <6> set (1) the adm.adcs bit. <7> transfer the a/d conversion data to the adcr register. <8> compare the adcrh register with the pft register. an interrupt request signal (intad) is generated when the conditions match. <9> change the channel by setting the ads2 to ads0 bits. <10> transfer the a/d conversion data to the adcr register. <11> the adcrh register is compared with the pft regi ster. when the conditions match, an intad signal is generated. <12> clear (0) the adcs bit. <13> clear (0) the adcs2 bit. remark if the operation of the power fail detection function is enabled, all the a/ d conversion results are compared, regardless of whether the select mode or scan mode is set.
chapter 13 a/d converter user?s manual u17705ej2v0ud 377 13.6 cautions (1) power consumpti on in standby mode the operation of the a/d converter st ops in the standby mode. at this time, the power consumption can be reduced by stopping the conversion op eration (the adm.adcs bit = 0) and stopping the reference voltage generator (the adm.adcs2 bit = 0). figure 13-7 shows an example of how to reduce the power consumpti on in the standby mode. figure 13-7. example of how to redu ce power consumption in standby mode adcs adcs2 series resistor string av ref0 p-ch av ss reference voltage generator (2) input range of ani0 to ani7 pins use the a/d converter with the ani0 to ani7 pin input voltages within the specified range. if a voltage of av ref0 or higher or av ss or lower (even if within the absolute maxi mum ratings) is input to these pins, the conversion value of the channel is undefined. also, this may affect the conversion value of other channels. (3) conflicting operations (a) conflict between writing to t he adcr register and reading from adcr register upon the end of conversion reading the adcr register takes precedence. after the register has been read, a new conversion result is written to the adcr register. (b) conflict between writing to the adcr register and writing to the adm register or writing to the ads register upon the end of conversion writing to the adm register or ads register takes precedence. the adcr regist er is not written, and neither is the conversion end interr upt request signal (intad) generated.
chapter 13 a/d converter user?s manual u17705ej2v0ud 378 (4) measures against noise to keep a resolution of 10 bits, be aware of noise on the av ref0 and ani0 to ani7 pins. the higher the output impedance of the analog input source, the greater the effect of noise. therefore, it is recommended to connect external capacitors as shown in figure 13-8 to reduce noise. figure 13-8. handling of analog input pins av ref0 ani0 to ani7 av ss v ss if noise of av ref0 or higher or av ss or lower could be generated, clamp with a diode with a small v f (0.3 v or lower). reference voltage input c 0.1 f (5) ani0/p70 to ani7/p77 pins the analog input pins (ani0 to ani7) function alternately as input port pins (p70 to p77). when performing a/d conversion by selecting any of th e ani0 to ani7 pins, do not execute an input instruction to port 7 during conversion. th is may decrease the conversion resolution. if digital pulses are applied to the pin adjacent to the pin subject to a/d conversi on, the value of the a/d conversion may differ from the expected value because of coupling noise. therefore, do not apply pulses to the pin adjacent to the pin subject to a/d conversion. (6) input impedance of av ref0 pin a series resistor string of tens of k is connected between the av ref0 pin and av ss pin. therefore, if the output im pedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the av ref0 pin and av ss pin, resulting in a large reference voltage error.
chapter 13 a/d converter user?s manual u17705ej2v0ud 379 (7) interrupt request flag (adic.adif bit) even when the ads register is changed, the adif bit is not cleared (0). therefore, if the analog input pin is changed during a/d conversion, the adif bit may be set (1) because a/d conversion of the previous analog input pin ends immediately before the ads register is rewritten. in a such case, note that if the adif bit is r ead immediately after the ads register ha s been rewritten, the adif bit is set (1) even though a/d conversion of the analog in put pin after the change has not been completed. when stopping a/d conversion once and resuming it, clea r the adif bit (0) before resuming a/d conversion. figure 13-9. a/d conversion end in terrupt request occurrence timing anin anin anin anim anim anin anim anim a/d conversion adcr intad ads rewrite (anin conversion start) ads rewrite (anim conversion start) anim conversion is not complete even though adif is set. remark n = 0 to 7 m = 0 to 7 (8) conversion results immediat ely after a/d conversion start if the adm.adcs bit is set to 1 within 1 s (high-speed mode) or 14 s (normal mode) after the adm.adcs2 bit has been set to 1, or if the adcs bit is set to 1 with the adcs2 bit cleared to 0, the converted value immediately after the a/d conversion operation has st arted may not satisfy the rating. take appropriate measures such as polling the a/d conversion end inte rrupt request signal (intad) and discarding the first conversion result. (9) reading a/d conversion result register (adcr) when the adm or ads register has been written, the contents of the adcr register may become undefined. when the conversion operation is complete, read the co nversion results before writing to the adm or ads register. a correct conversion result may not be able to be read at a timing other than the above. accessing the adcr and adcrh registers is prohibit ed when the cpu operates with the subclock and the main clock oscillation (f x ) is stopped. for details, refer to 3.4.8 (2) access to special on-chip peripheral i/o register .
chapter 13 a/d converter user?s manual u17705ej2v0ud 380 (10) a/d converter sampling time a nd a/d conversion start delay time the a/d converter sampling time differs depending on the se t value of the adm register. a delay time exists until actual sampling is started after a/d converter operation is enabled. when using a set in which the a/d conversion time must be strictly observed, care is required for the contents shown in figure 13-10 and table 13-4. figure 13-10. timing of a/d converter sampling and a/d conversion start delay adcs wait period conversion time conversion time register write response time/trigger response time sampling time sampling timing intad adcs bit 1 or ads register rewrite sampling time
chapter 13 a/d converter user?s manual u17705ej2v0ud 381 table 13-4. a/d converter conversion time register write response time note trigger response time note adhs1 adhs0 fr2 fr1 fr0 conversion time sampling time min. max. min. max. 0 0 0 0 0 288/f xx 176/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 0 0 0 1 240/f xx 176/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 0 0 1 0 192/f xx 132/f xx 10/f xx 11/f xx 6/f xx 7/f xx 0 0 1 0 0 144/f xx 88/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 0 1 0 1 120/f xx 88/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 0 1 1 0 96/f xx 48/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 1 0 0 0 96/f xx 48/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 1 0 0 1 72/f xx 36/f xx 10/f xx 11/f xx 6/f xx 7/f xx 0 1 0 1 0 48/f xx 24/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 1 0 1 1 24/f xx 12/f xx 8/f xx 9/f xx 4/f xx 5/f xx 0 1 1 0 0 224/f xx 176/f xx 11/f xx 12/f xx 7/f xx 8/f xx 0 1 1 0 1 168/f xx 132/f xx 10/f xx 11/f xx 6/f xx 7/f xx 0 1 1 1 0 112/f xx 88/f xx 9/f xx 10/f xx 5/f xx 6/f xx 0 1 1 1 1 56/f xx 44/f xx 8/f xx 9/f xx 4/f xx 5/f xx 1 0 0 0 0 72/f xx 24/f xx 11/f xx 12/f xx 7/f xx 8/f xx 1 0 0 0 1 54/f xx 18/f xx 10/f xx 11/f xx 6/f xx 7/f xx 1 0 0 1 0 36/f xx 12/f xx 9/f xx 10/f xx 5/f xx 6/f xx 1 0 0 1 1 18/f xx 6/f xx 8/f xx 9/f xx 4/f xx 5/f xx other than above setting prohibited ? ? ? ? ? note each response time is the time after the wait period. for the wait function, refer to 3.4.8 (2) access to special on-chip peripheral i/o register . remark f xx : main clock frequency
chapter 13 a/d converter user?s manual u17705ej2v0ud 382 (11) internal equivalent circuit the following shows the equivalent circuit of the analog input block. figure 13-11. internal equi valent circuit of anin pin anin c out c in r in av ref0 r in c out c in 4.5 v 3 k 8 pf 15 pf 2.7 v 60 k 8 pf 15 pf remarks 1. the above values are reference values. 2. n = 0 to 7 (12) variation of a/d conversion results the results of the a/d conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. to reduce the variation, take coun teractive measures with the program such as averaging the a/d conversion results. (13) a/d conversion result hysteresis characteristics the successive approximation type a/d co nverter holds the analog input voltage in the internal sample & hold capacitor and then performs a/d conversion. after t he a/d conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur. ? when the same channel is used for a/d conversions, if th e voltage is higher or lo wer than the previous a/d conversion, then hysteresis characteristics may appear where the conversion resu lt is affected by the previous value. thus, even if t he conversion is performed at the same potential, the result may vary. ? when switching the analog input cha nnel, hysteresis characteristics may appear where the conversion result is affected by the previous channel value. this is because one a/d converter is used for the a/d conversions. thus, even if the conversion is perfo rmed at the same potential, the result may vary. therefore, to obtain more accurate conversion result, perform a/d conversion twice successively for the same channel, and discard the first conversion result. (14) a/d conversion operation in normal mode ? in software trigger mode: writing to the adm, ads, pfm, or pft regist er is prohibited during conversion in normal mode (adm.adhs1, adm.adhs0 bits = 00). ? in hardware trigger (external trigger/timer trigger) mode: this mode cannot be used in normal mode (adhs1, adhs0 bits = 00). use it in high-speed mode (adhs1, adhs0 bits = 10 or 01).
chapter 13 a/d converter user?s manual u17705ej2v0ud 383 13.7 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltag e that can be identified. that is , the percentage of the analog input voltage per bit of digital output is called 1 lsb (least si gnificant bit). the percent age of 1 lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a percentage, and is always r epresented by the following formula regardless of the resolution. 1 %fsr = (max. value of analog in put voltage that can be converted ? min. value of analog input voltage that can be converted)/100 = (av ref0 ? 0)/100 = av ref0 /100 1 lsb is as follows when the resolution is 10 bits. 1 lsb = 1/2 10 = 1/1024 = 0.098 %fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, linearity error and erro rs that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. figure 13-12. overall error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref0 0
chapter 13 a/d converter user?s manual u17705ej2v0ud 384 (3) quantization error when analog values are converted to digital values, a 1/2 lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2 lsb is converted to the same digital code, so a quantization error cannot be avoided. note that the quantization error is not included in the over all error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 13-13. quan tization error 0 ?? 0 1 ?? 1 digital output quantization error 1/2 lsb 1/2 lsb analog input 0 av ref0 (4) zero-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (1/2 lsb) when the digital output changes from 0??000 to 0??001. figure 13-14. zero-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref0 digital output (lower 3 bits) analog input (lsb) -1 100
chapter 13 a/d converter user?s manual u17705ej2v0ud 385 (5) full-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (full scale ? 3/2 lsb) when the digital output changes from 1??110 to 1??111. figure 13-15. full-scale error 100 011 010 000 0 av ref0 av ref0 ?1 av ref0 ?2 av ref0 ?3 digital output (lower 3 bits) analog input (lsb) full-scale error 111 (6) differential linearity error while the ideal width of code output is 1 lsb, this indicates the difference between the actual measurement value and the ideal value. this indicates the basic characteristics of the a/d conversion when the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from av ss to av ref0 . when the input voltage is increased or decreased, or when two or more channels are used, refer to 13.7 (2) overall error . figure 13-16. differential linearity error 0 av ref0 digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1 lsb width
chapter 13 a/d converter user?s manual u17705ej2v0ud 386 (7) integral linearity error this shows the degree to which the conversion characterist ics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measur ement value and the ideal straight line when the zero-scale error and full-scale error are 0. figure 13-17. integral linearity error 0 av ref0 digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 (8) conversion time this expresses the time from when the analog input vo ltage was applied to the time when the digital output was obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. figure 13-18. sampling time sampling time conversion time
user?s manual u17705ej2v0ud 387 chapter 14 asynchronous serial interface (uart) in the v850es/ke2, two channels of asynchronous serial interface (uart) are provided. 14.1 features ? maximum transfer speed: 312.5 kbps ? full-duplex communications on-chip rxbn register on-chip txbn register ? two-pin configuration note txdn: transmit data output pin rxdn: receive data input pin ? reception error detection functions ? parity error ? framing error ? overrun error ? interrupt sources: 3 types ? reception error interrupt request signal (intsren): interrupt is generated according to the logical or of the three types of reception errors ? reception completion interrupt request signal (int srn): interrupt is generated when receive data is transferred from the receive shift register to the rxbn register after serial transfer is completed during a reception enabled state ? transmission completion interrupt request signal (intstn): interrupt is generated when the serial transmission of transmit data (8 or 7 bits) from the transmit shift register is completed ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? on-chip dedicated baud rate generator note the asck0 pin (external clock i nput) is available only for uart0.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 388 14.2 configuration table 14-1. configuration of uartn item configuration registers receive buffer register n (rxbn) transmit buffer register n (txbn) receive shift register transmit shift register asynchronous serial interface mode register n (asimm) asynchronous serial interface status register n (asisn) asynchronous serial interface tran smit status register n (asifn) other reception control parity check addition of transmissi on control parity remark n = 0, 1 figure 14-1 shows the configuration of uartn. (1) asynchronous serial interfa ce mode register n (asimn) the asimn register is an 8-bit register for specifying the operation of uartn. (2) asynchronous serial interfa ce status register n (asisn) the asisn register consists of a set of flags that indicate the erro r contents when a reception error occurs. the various reception error flags are set (1) when a reception error occurs and are cleared (0) when the asisn register is read. (3) asynchronous serial interface tran smit status register n (asifn) the asifn register is an 8-bit regist er that indicates the status when a transmit operation is performed. this register consists of a transmit buffer data flag, which indicates the hol d status of the t xbn register data, and the transmit shift register data flag, which indicates whether transmission is in progress. (4) reception control parity check the receive operation is controlled according to the c ontents set in the asimn register. a check for parity errors is also performed during a re ceive operation, and if an error is detected, a value corresponding to the error contents is set in the asisn register. (5) receive shift register this is a shift register that converts the serial data t hat was input to the rxdn pin to parallel data. one byte of data is received, and if a stop bi t is detected, the receive data is transferred to the rxbn register. this register cannot be directly manipulated. (6) receive buffer register n (rxbn) the rxbn register is an 8-bit buffer register for holdi ng receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, re ceive data is transferred from the re ceive shift register to the rxbn register, synchronized with the end of t he shift-in processing of one frame. also, the reception completion interrupt request signal (intsrn) is generated by t he transfer of data to the rxbn register.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 389 (7) transmit shift register this is a shift register that converts the parallel data that was transferred from the txbn register to serial data. when one byte of data is transferred fr om the txbn register, the shift regi ster data is output from the txdn pin. the transmission completion interrupt request signal (int stn) is generated synchronized with the completion of transmission of one frame. this register cannot be directly manipulated. (8) transmit buffer register n (txbn) the txbn register is an 8-bit buffer for transmit data. a transmit operation is star ted by writing transmit data to the txbn register. (9) addition of transmission control parity a transmit operation is controlled by adding a start bit, par ity bit, or stop bit to the data that is written to the txbn register, according to the contents that were set in the asimn register. figure 14-1. block diagram of uartn parity framing overrun internal bus asynchronous serial interface mode register n (asimn) receive buffer register n (rxbn) receive shift register reception control parity check transmit buffer register n (txbn) transmit shift register addition of transmission control parity baud rate generator n intsren intsrn intstn rxdn txdn remark for the configuration of the baud rate generator, refer to figure 14-12 .
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 390 14.3 registers (1) asynchronous serial interfa ce mode register n (asimn) the asimn register is an 8-bit register t hat controls the uartn transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. cautions 1. when using uartn, be sure to set th e external pins related to uartn functions to the control made before setting the cksrn and brgcn registers, and then set the uarten bit to 1. then set the other bits. 2. set the uarten and rxen bits to 1 while a high level is input to the rxdn pin. if these bits are set to 1 while a low level is input to the rxdn pin, reception will be started. (1/2) <7> uarten asimn (n = 0, 1) <6> txen <5> rxen 4 psn1 3 psn0 2 cln 1 sln 0 isrmn after reset: 01h r/w address: asim0 fffffa00h, asim1 fffffa10h uarten control of operating clock 0 stop clock supply to uartn. 1 supply clock to uartn. ? if the uarten bit is cleared to 0, uartn is asynchronously reset note . ? if the uarten bit = 0, uartn is reset. to operate uartn, first set the uarten bit to 1. ? if the uarten bit is cleared from 1 to 0, all the register s of uartn are initialized. to set the uarten bit to 1 again, be sure to re-set the registers of uartn. the output of the txdn pin goes high when transmission is disabled, regardless of the setting of the uarten bit. txen transmission enable/disable 0 disable transmission 1 enable transmission ? set the txen bit to 1 after setting the uarten bit to 1 at startup. clear the uarten bit to 0 after clearing the txen bit to 0 to stop. ? to initialize the transmission unit, clear (0) the txen bi t, and after letting 2 clock cycles (base clock) elapse, set (1) the txen bit again. if the txen bit is not set again, initialization may not be successful. (for details about the base clock, refer to 14.6.1 (1) base clock .) note the asisn, asifn, and rxbn registers are reset.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 391 (2/2) rxen reception enable/disable 0 disable reception note 1 enable reception ? set the rxen bit to 1 after setting the uarten bit to 1 at startup. clear the uarten bit to 0 after clearing the rxen bit to 0 to stop. ? to initialize the reception unit status, clear (0) the r xen bit, and after letting 2 clock cycles (base clock) elapse, set (1) the rxen bit again. if the rxen bit is not set agai n, initialization may not be successful. (for details about the base clock, refer to 14.6.1 (1) base clock .) psn1 psn0 transmit operation receive operation 0 0 don?t output parity bit receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity ? to overwrite the psn1 and psn0 bits, fi rst clear (0) the txen and rxen bits. ? if ?0 parity? is selected for reception, no parity judgment is performed. therefore, no error interrupt is generated because the asisn.pen bit is not set. cln specification of character length of 1 frame of transmit/receive data 0 7 bits 1 8 bits ? to overwrite the cln bit, first clear (0) the txen and rxen bits. sln specification of stop bit length of transmit data 0 1 bit 1 2 bits ? to overwrite the sln bit, first clear (0) the txen bit. ? since reception is always done with a stop bit length of 1, the sln bit setting does not affect receive operations. isrmn enable/disable of generation of reception completi on interrupt request signals when an error occurs 0 generate a reception error interrupt request signal (intsren) as an interrupt when an error occurs. in this case, no reception completion interr upt request signal (intsrn) is generated. 1 generate a reception completion interrupt request si gnal (intsrn) as an interrupt when an error occurs. in this case, no reception error interrupt request signal (intsren) is generated. ? to overwrite the isrmn bit, first clear (0) the rxen bit. note when reception is disabled, the receive shift r egister does not detect a start bit. no shift-in processing or transfer processing to the rxbn regist er is performed, and t he contents of the rxbn register are retained. when reception is enabled, the receive shift operat ion starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the receive shift register are transferred to the rxbn register. a reception completion interrupt request signal (intsrn) is also generated in synchronizati on with the transfer to the rxbn register.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 392 (2) asynchronous serial interfa ce status register n (asisn) the asisn register, which consists of 3 error flag bits (pen, fen and oven), indicates the error status when uartn reception is complete. the asisn register is cleared to 00h by a read operation. when a recept ion error occurs, the rxbn register should be read and the error flag should be cl eared after the asisn register is read. this register is read-only in 8-bit units. reset sets this register to 00h. cautions 1. when the asimn.uarten bit or asimn. rxen bit is cleared to 0, or when the asisn register is read, the pen, fen, and oven bits are cleared (0). 2. operation using a bit manipula tion instruction is prohibited. 3. when the main clock is stopped and th e cpu is operating on the subclock, do not access the asisn register. for details, refer to 3.4.8 (2). 7 0 asisn (n = 0, 1) 6 0 5 0 4 0 3 0 2 pen 1 fen 0 oven after reset: 00h r address: asis0 fffffa03h, asis1 fffffa13h pen status flag indicating a parity error 0 when the uarten or rxen bit is cleared to 0, or after the asisn register has been read 1 when reception was completed, the receive data parity did not match the parity bit ? the operation of the pen bit differs according to the settings of the asimn.psn1 and asimn.psn0 bits. fen status flag indicating framing error 0 when the uarten or rxen bit is cleared to 0, or after the asisn register has been read 1 when reception was completed, no stop bit was detected ? for receive data stop bits, only the first bit is checked regardless of the stop bit length. oven status flag indicating an overrun error 0 when the uarten or rxen bit is cleared to 0, or after the asisn register has been read. 1 uartn completed the next receive operation bef ore reading receive data of the rxbn register. ? when an overrun error occurs, the next receive data value is not written to the rxbn register and the data is discarded.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 393 (3) asynchronous serial interface tran smit status register n (asifn) the asifn register, which consists of 2 status flag bits, indicates the status during transmission. by writing the next data to the txbn register after data is transferred from the txbn register to the transmit shift register, transmit operations can be performed conti nuously without suspension even during an interrupt interval. when transmission is performed continuously, data should be written afte r referencing the txbfn bit to prevent writing to the txbn register by mistake. this register is read-only in 8-bit or 1-bit units. reset sets this register to 00h. 7 0 asifn (n = 0, 1) 6 0 5 0 4 0 3 0 2 0 <1> txbfn <0> txsfn after reset: 00h r address: asif0 fffffa05h, asif1 fffffa15h txbfn transmission buffer data flag 0 data to be transferred next to txbn register does not exist (when the asimn.uarten or asimn.txen bit is cleared to 0, or when data has been transf erred to the transmis sion shift register) 1 data to be transferred next exists in txbn register (d ata exists in txbn register when the txbn register has been written to) ? when transmission is performed continuousl y, data should be written to the txbn register after confirming that this flag is 0. if writing to txbn register is performed when this flag is 1, transmit data cannot be guaranteed. txsfn transmit shift register data flag (indi cates the transmission status of uartn) 0 initial status or a waiting transmi ssion (when the uarten or txen bit is cleared to 0, or when following transmission completion, the next data transfer fr om the txbn register is not performed) 1 transmission in progress (when data has been transferred from the txbn register) ? when the transmission unit is initializ ed, initialization should be executed a fter confirming that this flag is 0 following the occurrence of a transmission completion inte rrupt request signal (intstn). if initialization is performed when this flag is 1, transmit data cannot be guaranteed.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 394 (4) receive buffer register n (rxbn) the rxbn register is an 8-bit buffer register for stor ing parallel data that had been converted by the receive shift register. when reception is enabled (asimn.rxen bit = 1), receive da ta is transferred from the receive shift register to the rxbn register, synchronized with the completion of th e shift-in processing of one frame. also, a reception completion interrupt request signal (intsrn) is gener ated by the transfer to the rxbn register. for information about the timing for generat ing this interrupt request, refer to 14.5.4 receive operation . if reception is disabled (asimn.rxen bit = 0), the contents of the rxbn register are retained, and no processing is performed for transferring data to the r xbn register even when the shift-in processing of one frame is completed. also, the intsrn signal is not generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxbn register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overrun error (asisn.oven bit = 1) occurs, the receive data at that time is not trans ferred to the rxbn register. the rxbn register becomes ffh when a reset is input or asimn.uarten bit = 0. this register is read-only in 8-bit units. 7 rxbn7 rxbn (n = 0, 1) 6 rxbn6 5 rxbn5 4 rxbn4 3 rxbn3 2 rxbn2 1 rxbn1 0 rxbn0 after reset: ffh r address: rxb0 fffffa02h, rxb1 fffffa12h
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 395 (5) transmit buffer register n (txbn) the txbn register is an 8-bit buffe r register for setting transmit data. when transmission is enabled (asimn.txen bit = 1), the tr ansmit operation is started by writing data to txbn register. when transmission is disabled (txen bit = 0), even if dat a is written to txbn register, the value is ignored. the txbn register data is transferr ed to the transmit shift register, and a transmission completion interrupt request signal (intstn) is generated, synchronized wit h the completion of the transmission of one frame from the transmit shift register. for information about t he timing for generating this interrupt request, refer to 14.5.2 transmit operation . when asifn.txbfn bit = 1, writing must not be performed to txbn register. this register can be read or written in 8-bit units. reset sets this register to ffh. 7 txbn7 txbn (n = 0, 1) 6 txbn6 5 txbn5 4 txbn4 3 txbn3 2 txbn2 1 txbn1 0 txbn0 after reset: ffh r/w address: txb0 fffffa04h, txb1 fffffa14h
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 396 14.4 interrupt requests the following three types of interrupt re quest signals are generated from uartn. ? reception error interrupt request signal (intsren) ? reception completion interrupt request signal (intsrn) ? transmission completion interrupt request signal (intstn) the default priorities among these three types of interrupt request signals are, from high to low, reception error interrupt, reception completion interrup t, and transmission completion interrupt. table 14-2. generated interrupt re quest signals and default priorities interrupt request signal priority reception error interrupt request signal (intsren) 1 reception completion interrupt request signal (intsrn) 2 transmission completion interrupt request signal (intstn) 3 (1) reception error interrupt request signal (intsren) when reception is enabled, the intsren signal is generated according to the logical or of the three types of reception errors explained for the asisn register. whether the intsren signal or the intsrn signal is generated when an error occurs can be specified according to the asimn.isrmn bit. when reception is disabled, the intsren signal is not generated. (2) reception completion interr upt request signal (intsrn) when reception is enabled, the intsrn signal is generated when data is shifted in to the receive shift register and transferred to the rxbn register. the intsrn signal can be generated in place of the intsren signal according to the asimn.isrmn bit even when a reception error has occurred. when reception is disabled, the intsrn signal is not generated. (3) transmission completion inte rrupt request signal (intstn) the intstn signal is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmit shift register.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 397 14.5 operation 14.5.1 data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consists of one data fr ame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 14-2. the character bit length within one data frame, the type of parity, and the stop bit length are specified according to the asimn register. also, data is transferred lsb first. figure 14-2. format of uartn transmit/receive data 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 398 14.5.2 transmit operation when the asimn.uarten bit is set to 1, a hi gh level is output from the txdn pin. then, when the asimn.txen bit is set to 1, transmission is enabled, and the transmit operat ion is started by writing transmit data to the txbn register. (1) transmission enabled state this state is set by the txen bit. ? txen bit = 1: transmission enabled state ? txen bit = 0: transmission disabled state since uartn does not have a cts (tr ansmission enabled signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (2) starting a transmit operation in the transmission enabled state, a trans mit operation is started by writing tr ansmit data to the txbn register. when a transmit operation is star ted, the data in the txbn register is tr ansferred to the transmit shift register. then, the transmit shift register out puts data to the txdn pin (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically. (3) transmission interrupt when the transmit shift register bec omes empty, a transmission completion interrupt request signal (intstn) is generated. the timing for generating the intstn signa l differs according to the specification of the stop bit length. the intstn signal is generated at the same time that the last stop bit is output. if the data to be transmitted next has not been written to the txbn register, the transmit operation is suspended. caution normally, when the transmit shift register becomes empty, the intstn signal is generated. however, the intstn signal is not generated if the transmit shift register becomes empty due to reset.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 399 figure 14-3. uartn transmission completion interrupt timing start stop d0 d1 d2 d6 d7 parity parity txdn (output) intstn (output) start d0 d1 d2 d6 d7 txdn (output) intstn (output) (a) stop bit length: 1 (b) stop bit length: 2 stop
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 400 14.5.3 continuous transmission operation uartn can write the next transmit data to the txbn register at the timing t hat the transmit shift register starts the shift operation. this enables an efficient transmission rate to be realized by continuously transmitting data even during the transmission completion interrupt service after th e transmission of one data frame. in addition, reading the asifn.txsfn bit after the occurrence of a transmission co mpletion interrupt request si gnal (intstn) enables the txbn register to be efficiently written twice (2 byte s) without waiting for the tr ansmission of 1 data frame. when continuous transmission is perform ed, data should be written after referenc ing the asifn register to confirm the transmission status and whether or not da ta can be written to the txbn register. caution the values of the asif.txbfn and asif .txsfn bits change 10 11 01 in continuous transmission. therefore, do not confirm the status based on the combination of the txbfn and txsfn bits. read only the txbfn bit during continuous transmission. txbfn whether or not writing to txbn register is enabled 0 writing is enabled 1 writing is not enabled caution when transmission is perfo rmed continuously, write the first tr ansmit data (first byte) to the txbn register and confirm that the txbfn bit is 0, and then write the next transmit data (second byte) to the txbn register. if writing to the txbn register is performed when the txbfn bit is 1, transmit data cannot be guaranteed. the communication status can be confir med by referring to the txsfn bit. txsfn transmission status 0 transmission is completed. 1 under transmission. cautions 1. when initializing the transmission unit wh en continuous transmissi on is completed, confirm that the txsfn bit is 0 afte r the occurrence of the transmission completion interrupt, and then execute initialization. if in itialization is performed when the txsfn bit is 1, transmit data cannot be guaranteed. 2. while transmission is being performed contin uously, an overrun error may occur if the next transmission is completed befo re the intstn interrupt servicing following the transmission of 1 data frame is executed. an overrun error can be detected by embedding a program that can count the number of transmit data and referenc ing txsfn bit.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 401 figure 14-4. continuous transmission processing flow set registers interrupt occurrence wait for interrupt required number of transfers performed? write transmit data to txbn register write second byte transmit data to txbn register write transmit data to txbn register when reading asifn register, txbfn = 0? when reading asifn register, txsfn = 1? when reading asifn register, txsfn = 0? no no no no yes yes yes yes end of transmission processing
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 402 (1) starting procedure the procedure to start continuous transmission is shown below. figure 14-5. continuous tr ansmission starting procedure txdn (output) data (1) data (2) <5> <1> <2> <4> intstn (output) txbn register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asifn register (txbfn, txsfn bits) 00 11 note 11 01 01 11 01 11 txsn register start bit stop bit stop bit start bit 10 note refer to 14.7 cautions (2) . asifn register transmission starting procedure internal operation txbfn txsfn ? set transmission mode <1> start transmission unit 0 0 ? write data (1) 1 0 <2> generate start bit ? read asifn register (confirm that txbfn bit = 0) start data (1) transmission 1 0 0 0 1 note 1 1 1 ? write data (2) <> 1 1 <3> intstn interrupt occurs ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (3) <4> generate start bit start data (2) transmission <> 1 1 <5> intstn interrupt occurs ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (4) 1 1 note refer to 14.7 cautions (2) .
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 403 (2) ending procedure the procedure for ending continuous transmission is shown below. figure 14-6. continuous transmission end procedure txdn (output) data (m ? 1) data (m) <11> <7> <6> <8> <10> intstn (output) txbn register data (m ? 1) data (m ? 1) data (m) ffh data (m) <9> asifn register (txbfn, txsfn bits) uarten bit or txen bit 11 01 11 01 00 txsn register start bit start bit stop bit stop bit asifn register transmission end procedure internal operation txbfn txsfn <6> transmission of data (m ? 2) is in progress 1 1 <7> intstn interrupt occurs ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (m) <8> generate start bit start data (m ? 1) transmission <> 1 1 <9> intstn interrupt occurs ? read asifn register (confirm that txsfn bit = 1) there is no write data <10> generate start bit start data (m) transmission <> 0 0 1 1 <11> generate intstn interrupt ? read asifn register (confirm that txsfn bit = 0) ? clear (0) the uarten bit or txen bit initialize internal circuits 0 0 0 0
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 404 14.5.4 receive operation the awaiting reception state is set by setting the asimn.uar ten bit to 1 and then setting the asimn.rxen bit to 1. to start the receive operatio n, start sampling at the fallin g edge when the falling of the rxdn pin is detected. if the rxdn pin is low level at a start bit sampling point, the st art bit is recognized. when the receive operation begins, serial data is stored sequentially in the receive shift regi ster according to the baud rate that was set. a reception completion interrupt request signal (intsrn) is generated each time the reception of one frame of data is completed. normally, the receive data is transferred from the rxbn register to memory by th is interrupt servicing. (1) reception enabled state the receive operation is set to the reception enabled state by setting the rxen bit to 1. ? rxen bit = 1: reception enabled state ? rxen bit = 0: reception disabled state in receive disabled state, the reception hardware stands by in the initial stat e. at this time, the contents of the rxbn register are retained, and no reception completion interrupt or reception error interrupt is generated. (2) starting a receive operation a receive operation is started by the detection of a start bit. the rxdn pin is sampled using the serial clock from baud rate generator n (brgn). (3) reception completion interrupt when the rxen bit = 1 and the reception of one frame of data is completed (the stop bit is detected), the intsrn signal is generated and the receive data within t he receive shift register is transferred to the rxbn register at the same time. also, if an overrun error (asisn.oven bit = 1) occurs, t he receive data at that time is not transferred to the rxbn register, and either the intsrn signal or a re ception error interrupt request signal (intsren) is generated according to the asimn.isrmn bit setting. even if a parity error (asisn.pen bit = 1) or framing error (asisn.fen bit = 1) occurs during a reception operation, the receive operation contin ues until stop bit is received, and after reception is completed, either the intsrn signal or the intsren signal is generated according to the isrmn bit setting (the receive data within the receive shift register is transferred to the rxbn register). if the rxen bit is cleared (0) during a receive operation, the receive operation is immediately stopped. the contents of the rxbn register and the asisn register at this time do not change, and the intsrn signal or the intsren signal is not generated. the intsrn signal or the intsren signal is not gener ated when the rxen bit = 0 (reception is disabled).
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 405 figure 14-7. uartn reception completion inte rrupt timing start d0 d1 d2 d6 d7 rxdn (input) intsrn (output) rxbn register parity stop cautions 1. be sure to read th e rxbn register even when a recept ion error occurs. if the rxbn register is not read, an overrun error wil l occur at the next data reception and the reception error status will continue infinitely. 2. reception is always performed assuming a stop bit length of 1. a second stop bit is ignored. 14.5.5 reception error the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. as a result of data reception, the various flags of the asisn register ar e set (1), and a reception error interrupt request signal (intsren) or a reception completion interrupt request signal (intsrn) is generated at the same time. the asimn.isrmn bit specifies whether the intsren signal or the intsrn signal is generated. the type of error that occurred during reception can be de tected by reading the conten ts of the asisn register during the intsren or intsrn interrupt servicing. the contents of the asisn r egister are cleared (0) by reading the asisn register. table 14-3. reception error causes error flag reception error cause pen parity error the parity specificat ion during transmission did not match the parity of the reception data fen framing error no stop bit was detected oven overrun error the reception of the next data was completed before data was read from the rxbn register
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 406 (1) separation of reception e rror interrupt request signal a reception error interrupt request signal can be separ ated from the intsrn signal and generated as the intsren signal by clearing the isrmn bit to 0. figure 14-8. when reception error inte rrupt request signal is separated from intsrn signal (isrmn bit = 0) (a) no error occurs during reception (b) an e rror occurs during reception intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn does not occur figure 14-9. when reception error in terrupt request signal is included in intsrn signal (isrmn bit = 1) (a) no error occurs during reception (b) an erro r occurs during reception intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsrn signal (reception completion interrupt) intsren signal (reception error interrupt) intsren does not occur
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 407 14.5.6 parity types and corresponding operation a parity bit is used to detect a bit error in communication da ta. normally, the same type of parity bit is used on the transmission and reception sides. (1) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the valu e ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 (ii) during reception the number of bits with the value ?1? within the receive data includi ng the parity bit is counted, and a parity error is generated if this number is odd. (2) odd parity (i) during transmission in contrast to even parity, the parity bit is controlled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 (ii) during reception the number of bits with the value ?1? within the receive data includi ng the parity bit is counted, and a parity error is generated if this number is even. (3) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (4) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no par ity bit. since there is no parity bit, no parity error is generated.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 408 14.5.7 receive data noise filter the rxdn signal is sampled at the risi ng edge of the prescaler output base clock (f uclk ). if the same sampling value is obtained twice, the ma tch detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (refer to figure 14-11 ). refer to 14.6.1 (1) base clock regarding the base clock. also, since the circuit is configured as shown in figure 14-10, internal processing during a receive operation is delayed by up to 2 clocks accordin g to the external signal status. figure 14-10. noise filter circuit rxdn q base clock in ld_en q in internal signal a internal signal b match detector f uclk figure 14-11. timing of rx dn signal judg ed as noise internal signal a base clock rxdn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 409 14.6 dedicated baud rate generator n (brgn) a dedicated baud rate generator, which consists of a s ource clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by uartn. the dedicated baud ra te generator output can be selected as the serial clock for each channel. separate 8-bit counters exist fo r transmission and for reception. 14.6.1 baud rate generator n (brgn) configuration figure 14-12. configuration of baud rate generator n (brgn) f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 asck0 note 2 f uclk note 1 selector uarten 8-bit counter match detector baud rate brgcn: mdln7 to mdln0 1/2 uarten and txen bits (or rxen bit) cksrn: tpsn3 to tpsn0 f xx notes 1. set f uclk so as to satisfy the following conditions. ? v dd = 4.5 to 5.5 v: f uclk 12 mhz ? v dd = 2.7 to 4.5 v: f uclk 6 mhz 2. asck0 pin input can be used only by uart0. remark f xx : main clock frequency f uclk : base clock (1) base clock when the asimn.uarten bit = 1, the clock selected a ccording to the cksrn.tpsn3 to cksrn.tpsn0 bits is supplied to the transmission/reception uni t. this clock is called the base clock (f uclk ). when the uarten bit = 0, f uclk is fixed to low level.
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 410 14.6.2 serial clock generation a serial clock can be generated according to the settings of the cksrn and brgcn registers. the base clock to the 8-bit counter is select ed by the cksrn.tpsn3 to cksrn.tpsn0 bits. the 8-bit counter divisor value can be set by the brgcn.mdln7 to brgcn.mdln0 bits. (1) clock select register n (cksrn) the cksrn register is an 8-bit regist er for selecting the basic block us ing the tpsn3 to tpsn0 bits. the clock selected by the tpsn3 to t psn0 bits becomes the base clock (f uclk ) of the transmission/reception module. this register can be read or written in 8-bit units. reset sets this register to 00h. caution clear the asimn.uarten bit to 0 before rewriti ng the tpsn3 to tpsn0 bits. 7 0 cksrn (n = 0, 1) 6 0 5 0 4 0 3 tpsn3 2 tpsn2 1 tpsn1 0 tpsn0 after reset: 00h r/w address: cksr0 fffffa06h, cksr1 fffffa16h tpsn3 tpsn2 tpsn1 tpsn0 base clock (f uclk ) note 1 0 0 0 0 f xx 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1,024 1 0 1 1 external clock note 2 (asck0 pin) other than above setting prohibited notes 1. set f uclk so as to satisfy the following conditions. ? v dd = 4.5 to 5.5 v: f uclk 12 mhz ? v dd = 2.7 to 4.5 v: f uclk 6 mhz 2. asck0 pin input clock can be used only by uart0. setting of uart1 and uart2 is prohibited. remark f xx : main clock frequency
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 411 (2) baud rate generator c ontrol register n (brgcn) the brgcn register is an 8-bit regist er that controls the baud rate (serial transfer speed) of uartn. this register can be read or written in 8-bit units. reset sets this register to ffh. caution if the mdln7 to mdln0 bits are to be o verwritten, the asimn.txen and asimn.rxen bits should be cleared to 0 first. 7 mdln7 brgcn (n = 0, 1) 6 mdln6 5 mdln5 4 mdln4 3 mdln3 2 mdln2 1 mdln1 0 mdln0 after reset: ffh r/w address: brgc0 fffffa07h, brgc1 fffffa17h mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 set value (k) serial clock 0 0 0 0 0 ? setting prohibited 0 0 0 0 1 0 0 0 8 f uclk /8 0 0 0 0 1 0 0 1 9 f uclk /9 0 0 0 0 1 0 1 0 10 f uclk /10 1 1 1 1 1 0 1 0 250 f uclk /250 1 1 1 1 1 0 1 1 251 f uclk /251 1 1 1 1 1 1 0 0 252 f uclk /252 1 1 1 1 1 1 0 1 253 f uclk /253 1 1 1 1 1 1 1 0 254 f uclk /254 1 1 1 1 1 1 1 1 255 f uclk /255 remarks 1. f uclk : frequency [hz] of base clock selected by cksr0.tpsn3 to cksr0.tpsn0 bits 2. k: value set by mdln7 to mdln0 bits (k = 8, 9, 10, ..., 255) 3. the baud rate is the output clock fo r the 8-bit counter divided by 2. 4. : don?t care
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 412 (3) baud rate the baud rate is the value obtained by the following formula. baud rate [bps] = f uclk = frequency [hz] of base clock selected by cksrn.tpsn3 to cksrn.tpsn0 bits. k = value set by brgcn.mdln7 to brgcn. mdln0 bits (k = 8, 9, 10, ..., 255) (4) baud rate error the baud rate error is obtained by the following formula. error (%) = ? 1 100 [%] cautions 1. make sure that the baud rate erro r during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error durin g reception is within the allowable baud rate range during reception, which is described in 14.6.4 allowable baud rate range during reception. example: base clock frequency = 10 mhz = 10,000,000 hz setting of brgcn.mdln7 to brgcn.mdln0 bits = 00100001b (k = 33) target baud rate = 153,600 bps baud rate = 10,000,000/(2 33) = 151,515 [bps] error = (151,515/153,600 ? 1) 100 = ? 1.357 [%] f uclk 2 k actual baud rate (baud rate with error) target baud rate (normal baud rate)
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 413 14.6.3 baud rate setting example table 14-4. baud rate generator setting data f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz baud rate (bps) f uclk k err f uclk k err f uclk k err 300 f xx /512 41h (65) 0.16 f xx /1024 1ah (26) 0.16 f xx /256 41h (65) 0.16 600 f xx /256 41h (65) 0.16 f xx /1024 0dh (13) 0.16 f xx /128 41h (65) 0.16 1200 f xx /128 41h (65) 0.16 f xx /512 0dh (13) 0.16 f xx /64 41h (65) 0.16 2400 f xx /64 41h (65) 0.16 f xx /256 0dh (13) 0.16 f xx /32 41h (65) 0.16 4800 f xx /32 41h (65) 0.16 f xx /128 0dh (13) 0.16 f xx /16 41h (65) 0.16 9600 f xx /16 41h (65) 0.16 f xx /64 0dh (13) 0.16 f xx /8 41h (65) 0.16 10400 f xx /64 0fh (15) 0.16 f xx /64 0ch (12) 0.16 f xx /32 0fh (15) 0.16 19200 f xx /8 41h (65) 0.16 f xx /32 0dh (13) 0.16 f xx /4 41h (65) 0.16 24000 f xx /32 0dh (13) 0.16 f xx /2 a7h (167) ? 0.20 f xx /16 0dh (13) 0.16 31250 f xx /32 0ah (10) 0.00 f xx /32 08h (8) 0.00 f xx /16 0ah (10) 0 33600 f xx /2 95h (149) ? 0.13 f xx /2 77h (119) 0.04 f xx 95h (149) ? 0.13 38400 f xx /4 41h (65) 0.16 f xx /16 0dh (13) 0.16 f xx /2 41h (65) 0.16 48000 f xx /16 0dh (13) 0.16 f xx /2 53h (83) 0.40 f xx /8 0dh (13) 0.16 56000 f xx /2 59h (89) 0.32 f xx /2 47h (71) 0.60 f xx 59h (89) 0.32 62500 f xx /16 0ah (10) 0.00 f xx /16 08h (8) 0.00 f xx /8 0ah (10) 0.00 76800 f xx /2 41h (65) 0.16 f xx /8 0dh (13) 0.16 f xx 41h (65) 0.16 115200 f xx /2 2bh (43) 0.94 f xx /2 23h (35) ? 0.79 f xx 2bh (43) 0.94 153600 f xx /2 21h (33) ? 1.36 f xx /4 0dh (13) 0.16 f xx 21h (33) ? 1.36 312500 f xx /4 08h (8) 0 f xx /2 0dh (13) ? 1.54 f xx /2 08h (8) 0.00 caution the allowable fre quency of the base clock (f uclk ) is as follows. ? v dd = 4.5 to 5.5 v: f uclk 12 mhz ? v dd = 2.7 to 4.5 v: f uclk 6 mhz remark f xx : main clock frequency f uclk : base clock frequency k: set values of brgcn.mdln7 to brgcn.mdln0 bits err: baud rate error [%] n = 0 to 2
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 414 14.6.4 allowable baud ra te range during reception the degree to which a discrepancy from the transmission des tination?s baud rate is allowed during reception is shown below. caution the equations described belo w should be used to set the ba ud rate error during reception so that it always is within the allowable error range. figure 14-13. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartn transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 14-13, after the start bit is detect ed, the receive data latch timing is determined according to the counter that was set by the brgc n register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. if this is applied to 11-bit reception, the following is theoretically true. fl = (brate) ?1 brate: uartn baud rate k: brgcn register set value fl: 1-bit data length when the latch timing margin is 2 base clocks, the minimum allowable transfer rate (flmin) is as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 min fl + = ? ? =
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 415 therefore, the transfer destination?s maximum re ceivable baud rate (brmax) is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum allowable transfer rate (flmax) can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 max fl 11 10 ? = + ? = 11 fl k 20 2 k 21 max fl ? = therefore, the transfer destination?s minimum receivable baud rate (brmin) is as follows. brmin = (flmax/11) ? 1 = brate the allowable baud rate error of uartn and the trans fer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 14-5. maximum and mini mum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ?3.61% 20 +4.26% ?4.31% 50 +4.56% ?4.58% 100 +4.66% ?4.67% 255 +4.72% ?4.73% remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: brgcn register set value 22k 21k + 2 20k 21k ? 2
chapter 14 asynchronous serial interface (uart) user?s manual u17705ej2v0ud 416 14.6.5 transfer rate duri ng continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock longer than normal. however, on the reception si de, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 14-14. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the base clock frequency by f uclk yields the following equation. flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows (when the stop bit length = 1). transfer rate = 11 fl + (2/f uclk ) 14.7 cautions cautions to be observed when using uartn are shown below. (1) when the supply of clocks to uart n is stopped (for example, in idle or stop mode), operation stops with each register retaining the value it had immediately before t he supply of clocks was st opped. the txdn pin output also holds and outputs the value it had imm ediately before the supply of clocks was stopped. however, operation is not gua ranteed after the supply of clocks is rest arted. therefore, after the supply of clocks is restarted, the circuits should be initialized by clearing the asimn.uarten, asimn.rxen, and asimn.txen bits to 000. (2) uartn has a 2-stage buffer configurat ion consisting of the txbn regist er and the transmission shift register, and has status flags (asifn.txbfn and as ifn.txsfn bits) that indicate t he status of each buffer. if the txbfn and txsfn bits are read in contin uous transmission, the value changes 10 11 01. for the timing to write the next data to the txbn register, read only the txbfn bit durin g continuous transmission.
user?s manual u17705ej2v0ud 417 chapter 15 clocked serial interface 0 (csi0) in the v850es/ke2, two channels of clocked serial interface 0 (csi0) are provided. 15.1 features ? maximum transfer speed: 5 mbps ? master mode/slave mode selectable ? transmission data length: 8 bits or 16 bits can be set ? msb/lsb-first selectable for transfer data ? eight clock signals can be selected (7 master clocks and 1 slave clock) ? 3-wire type so0n: serial transmit data output si0n: serial receive data input sck0n: serial clock i/o ? interrupt sources: 1 type ? transmission/reception completion inte rrupt request signal (intcsi0n) ? transmission/reception mode or reception-only mode selectable ? two transmission buffer registers (sotbfn/sotbfln, sotbn/sotbln) and two reception buffer registers (sirbn/sirbln, sirben/sirbeln) are provided on chip ? single transfer mode/continuous transfer mode selectable remark n = 0, 1
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 418 15.2 configuration csi0n is controlled via the csim0n register. (1) clocked serial interface mode register 0n (csim0n) the csim0n register is an 8-bit register t hat specifies the operation of csi0n. (2) clocked serial interface clock selection register n (csicn) the csicn register is an 8-bit register that co ntrols the csi0n serial transfer operation. (3) serial i/o shift register 0n (sio0n) the sio0n register is a 16-bit shift register th at converts parallel data into serial data. the sio0n register is used for bot h transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations ar e started up by accessing the buffer register. (4) serial i/o shift register 0nl (sio0nl) the sio0nl register is an 8-bit shift register that converts parallel data into serial data. the sio0nl register is used for both transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations ar e started up by access of the buffer register . (5) clocked serial interface recei ve buffer register n (sirbn) the sirbn register is a 16-bit buffer r egister that stores receive data. (6) clocked serial interface recei ve buffer register nl (sirbnl) the sirbnl register is an 8-bit buffer r egister that stores receive data. (7) clocked serial interface read-only r eceive buffer register n (sirben) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. (8) clocked serial interface read-only r eceive buffer register nl (sirbenl) the sirbenl register is an 8-bit buffer register that stores receive data. the sirbenl register is the same as the sirbnl register. it is used to read the contents of the sirbnl register. (9) clocked serial interface transm it buffer register n (sotbn) the sotbn register is a 16-bit buffer r egister that stores transmit data. (10) clocked serial interface transm it buffer register nl (sotblnl) the sotbnl register is an 8-bit buffer register that stores transmit data. (11) clocked serial interface initial tr ansmit buffer register n (sotbfn) the sotbfn register is a 16-bit buffer register that st ores the initial transmit data in the continuous transfer mode.
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 419 (12) clocked serial interface initial tran smit buffer register nl (sotbfnl) the sotbfnl register is an 8-bit buffe r register that stores initial tran smit data in the continuous transfer mode. (13) selector the selector selects the serial clock to be used. (14) serial clock controller controls the serial clock supply to the shift register. also controls the clock out put to the sck0n pin when the internal clock is used. (15) serial clock counter counts the serial clock output or i nput during transmission/reception, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) interrupt controller controls the interrupt request timing. remark n = 0, 1
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 420 figure 15-1. block diagram of clocked serial interface selector transmission control so selection so latch transmit buffer register (sotbn/sotbnl) receive buffer register (sirbn/sirbnl) shift register (sion/sio0nl) initial transmit buffer register (sotbfn/sotbfnl) interrupt controller clock start/stop control & clock phase control serial clock controller sck0n intcsi0n so0n si0n control signal transmission data control f xx /2 6 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 f xx /2 to50, to51 sck0n remarks 1. n = 0, 1 2. f xx : main clock
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 421 15.3 registers (1) clocked serial interface mode register 0n (csim0n) the csim0n register controls the csi0n operation. this register can be read or written in 8-bit or 1-bit units (however, csotn bit is read-only). reset sets csim0n to 00h. caution overwriting the csim0n.trmdn, csim 0n.ccln, csim0n.dirn, csim0n.csitn, and csim0n.auton bits can be done only when the cs otn bit = 0. if these bits are overwritten at any other time, the operation cannot be guaranteed.
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 422 <7> csi0en csim0n (n = 0, 1) <6> trmdn 5 ccln <4> dirn 3 csitn 2 auton 1 0 <0> csotn after reset: 00h r/w address: csim00 fffffd00h, csim01 fffffd10h csi0en csi0n operation enable/disable 0 disable csi0n operation. 1 enable csi0n operation. the internal csi0n circuit can be reset note asynchronously by clearing the csi0en bit to 0. for the sck0n and so0n pin output status when the csi0en bit = 0, refer to 15.5 output pins . trmdn specification of transmission/reception mode 0 receive-only mode 1 transmission/reception mode when the trmdn bit = 0, reception is performed and the so0n pi n outputs a low level. data reception is started by reading the sirbn register. when the trmdn bit = 1, transmissi on/reception is started by writing data to the sotbn register. ccln specification of data length 0 8 bits 1 16 bits dirn specification of transfer direction mode (msb/lsb) 0 first bit of transfer data is msb 1 first bit of transfer data is lsb csitn control of delay of interrupt request signal 0 no delay 1 delay mode (interrupt request signal is delay ed 1/2 cycle compared to the serial clock) the delay mode (csitn bit = 1) is valid only in the master mode (csicn.cks0n2 to csicn.csk0n0 bits are not 111b). in the slave mode (cks0n2 to cks0n0 bits are 111b), do not set the delay mode. auton specification of single trans fer mode or continuous transfer mode 0 single transfer mode 1 continuous transfer mode csotn communication status flag 0 communication stopped 1 communication in progress the csotn bit is cleared (0) by writing 0 to the csi0en bit. note the csotn bit and the sirbn, sirbnl, sirbe, sirbenl, sion , and sionl registers are reset.
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 423 (2) clocked serial interface clock selection register n (csicn) the csicn register is an 8-bit register t hat controls the csi0n transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets csicn to 00h. caution the csicn register can be overwri tten only when the csim0n.csi0en bit = 0. 7 0 csicn (n = 0, 1) 6 0 5 0 4 ckpn 3 dapn 2 cks0n2 1 cks0n1 0 cks0n0 after reset: 00h r/w address: csic0 fffffd01h, csic1 fffffd11h ckpn dapn specification of timing of transmitting/receiving data to/from sck0n 0 0 (type 1) do7 do6 do5 do4 do3 do2 do1 do0 di7 so0n (output) sck0n (i/o) si0n (input) di6 di5 di4 di3 di2 di1 di0 0 1 (type 2) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) 1 0 (type 3) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) 1 1 (type 4) do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) cks0n2 cks0n1 cks0n0 serial clock note mode 0 0 0 f xx /2 master mode 0 0 1 f xx /2 2 master mode 0 1 0 f xx /2 3 master mode 0 1 1 f xx /2 4 master mode 1 0 0 f xx /2 5 master mode 1 0 1 f xx /2 6 master mode 1 1 0 clock generated by to5n master mode 1 1 1 external clock (sck0n pin) slave mode note set the serial clock so as to satisfy the following conditions. ? v dd = 4.0 to 5.5 v: serial clock 5 mhz ? v dd = 2.7 to 4.0 v: serial clock 2.5 mhz remark f xx : main clock frequency
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 424 (3) clocked serial interface receive buffe r registers n, nl (sirbn, sirbnl) the sirbn register is a 16-bit buffer r egister that stores receive data. when the receive-only mode is set (csim0n.trmdn bit = 0), the reception operati on is started by reading data from the sirbn register. this register is read-only in 16-bit units. when the lowe r 8 bits are used as the sirbnl register, this register is read-only in 8-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csim0n.csi0en bit. cautions 1. read the sirbn regist er only when a 16-bit data length has been set (csim0n.ccln bit = 1). read the sirbnl register only when an 8-bi t data length has been set (ccln bit = 0). 2. when the single transfer mode has been set (csim0n.aut on bit = 0), perform a read operation only in the idle state (csim0n.csotn bit = 0). if the sirbn or sirbnl register is read during data transfer, th e data cannot be guaranteed. (a) sirbn register 14 sirbn 14 13 sirbn 13 12 sirbn 12 2 sirbn 2 3 sirbn 3 4 sirbn 4 5 sirbn 5 6 sirbn 6 7 sirbn 7 8 sirbn 8 9 sirbn 9 10 sirbn 10 11 sirbn 11 15 sirbn 15 1 sirbn 1 0 sirbn 0 sirbn (n = 0, 1) after reset: 0000h r address: sirb0 fffffd02h, sirb1 fffffd12h (b) sirbnl register 7 sirbn7 sirbnl (n = 0, 1) 6 sirbn6 5 sirbn5 4 sirbn4 3 sirbn3 2 sirbn2 1 sirbn1 0 sirbn0 after reset: 00h r address: sirb0l fffffd02h, sirb1l fffffd12h
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 425 (4) clocked serial interface read-only receive buffer registers n, nl (sirben, sirbenl) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. even if the sirben register is read, the next operation will not start. the sirben register is used to read the conten ts of the sirbn register when the serial reception is not continued. this register is read-only in 16-bit units. however, when the lower 8 bits are used as the sirbenl register, the register is read-only in 8-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csim0n.csi0en bit. cautions 1. the receive operation is not started even if data is read from the sirben and sirbenl registers. 2. read the sirben register only when a 16-bit data length has been set (csim0n.ccln bit = 1). read the sirbenl register only when an 8-bi t data length has been set (ccln bit = 0). (a) sirben register 14 sirben 14 13 sirben 13 12 sirben 12 2 sirben 2 3 sirben 3 4 sirben 4 5 sirben 5 6 sirben 6 7 sirben 7 8 sirben 8 9 sirben 9 10 sirben 10 11 sirben 11 15 sirben 15 1 sirben 1 0 sirben 0 sirben (n = 0, 1) after reset: 0000h r address: sirbe0 fffffd06h, sirbe1 fffffd16h (b) sirbenl register 7 sirben7 sirbenl (n = 0, 1) 6 sirben6 5 sirben5 4 sirben4 3 sirben3 2 sirben2 1 sirben1 0 sirben0 after reset: 00h r address: sirbe0l fffffd06h, sirbe1l fffffd16h
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 426 (5) clocked serial interface transmit bu ffer registers n, nl (sotbn, sotbnl) the sotbn register is a 16-bit buffer r egister that stores transmit data. when the transmission/reception mode is set (csim0n.trmd n bit = 1), the transmission operation is started by writing data to the sotbn register. this register can be read or written in 16-bit units. however, when the lower 8 bi ts are used as the sotbnl register, the register is read-only in 8-bit units. after reset, this regi ster is initialized. cautions 1. access the sotbn register only when a 16-bit data length has been set (csim0n.ccln bit = 1). access the sotbnl register only when an 8-bi t data length has been set (ccln bit = 0). 2. when the single transfer mode is set (csim0n.auton bit = 0) , perform access only in the idle state (csim0n.csotn bit = 0). if the sotbn and sotbnl registers are accessed during data transfer, the da ta cannot be guaranteed. (a) sotbn register 14 sotbn 14 13 sotbn 13 12 sotbn 12 2 sotbn 2 3 sotbn 3 4 sotbn 4 5 sotbn 5 6 sotbn 6 7 sotbn 7 8 sotbn 8 9 sotbn 9 10 sotbn 10 11 sotbn 11 15 sotbn 15 1 sotbn 1 0 sotbn 0 sotbn (n = 0, 1) after reset: 0000h r/w address: sotb0 fffffd04h, sotb1 fffffd14h (b) sotbnl register 7 sotbn7 sotbnl (n = 0, 1) 6 sotbn6 5 sotbn5 4 sotbn4 3 sotbn3 2 sotbn2 1 sotbn1 0 sotbn0 after reset: 00h r/w address: sotb0l fffffd04h, sotb1l fffffd14h
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 427 (6) clocked serial interface initial transmit buffer registers n, nl (sotbfn, sotbfnl) the sotbfn register is a 16-bit buffer register that st ores initial transmission data in the continuous transfer mode. the transmission operation is not started even if data is writt en to the sotbfn register. this register can be read or written in 16-bit units. however, when the lower 8 bits are used as the sotbfnl register, the register can be read or written in 8-bit units. after reset, this regi ster is initialized. caution access the sotbfn register and sotbfnl regi ster only when a 16-bit data length has been set (csim0n.ccln bit = 1), and only when an 8- bit data length has been set (ccln bit = 0), respectively, and only in the idle state (csim0n.csotn bit = 0). if the sotbfn and sotbfnl registers are accessed during data transfer, the data cannot be guaranteed. (a) sotbfn register 14 sotbfn 14 13 sotbfn 13 12 sotbfn 12 2 sotbfn 2 3 sotbfn 3 4 sotbfn 4 5 sotbfn 5 6 sotbfn 6 7 sotbfn 7 8 sotbfn 8 9 sotbfn 9 10 sotbfn 10 11 sotbfn 11 15 sotbfn 15 1 sotbfn 1 0 sotbfn 0 sotbfn (n = 0, 1) after reset: 0000h r/w address: sotbf0 fffffd08h, sotbf1 fffffd18h (b) sotbfnl register 7 sotbfn7 sotbfnl (n = 0, 1) 6 sotbfn6 5 sotbfn5 4 sotbfn4 3 sotbfn3 2 sotbfn2 1 sotbfn1 0 sotbfn0 after reset: 00h r/w address: sotbf0l fffffd08h, sotbf1l fffffd18h
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 428 (7) serial i/o shift registers n, nl (sio0n, sio0nl) the sio0n register is a 16-bit shift register th at converts parallel data into serial data. the transfer operation is not started even if the s io0n register is read. this register is read-only in 16-bit units. however, when the lower 8 bi ts are used as the sio0nl register, the register is read-only in 8-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csim0n.csi0en bit. caution read the sio0n register and sio0nl re gister only when a 16-bi t data length has been set (csim0n.ccln bit = 1), and only when an 8-bit data length has been set (ccln bit = 0), respectively, and only in the idle state (csim0n.csotn bit = 0). if the sio0n and sio0nl registers are read during data tran sfer, the data cannot be guaranteed. (a) sio0n register 14 sion14 13 sion13 12 sion12 2 sion2 3 sion3 4 sion4 5 sion5 6 sion6 7 sion7 8 sion8 9 sion9 10 sion10 11 sion11 15 sion15 1 sion1 0 sion0 sio0n (n = 0, 1) after reset: 0000h r address: sio00 fffffd0ah, sio01 fffffd1ah (b) sio0nl register 7 sion7 sio0nl (n = 0, 1) 6 sion6 5 sion5 4 sion4 3 sion3 2 sion2 1 sion1 0 sion0 after reset: 00h r address: sio00l fffffd0ah, sio01l fffffd1ah
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 429 receive-only mode ? reading starts reception ? storing up to the (n ? 2)th data (other than the last two) when reception is complete, read the received data from this register. repeat this operation until the (n ? 2)th data has been received. (supplement) do not read the (n ? 1)th data from this register. if read, a reception operation starts and continuous transfer cannot be completed. storing the (n ? 1)th received data note 2 read the (n ? 1)th received data from this register when the (n ? 1)th or nth (last) data has been received. storing the nth (last) received data note 2 when the nth (last) data has been received, read the nth (last) data. ? not used ? not used continuous transfer note 1 transmission/reception mode storing up to the (n ? 1)th received data (other than the last) note 2 when reception is complete, read the received data from this register. repeat this operation until the (n ? 1)th data has been received. ? not used storing the nth (last) received data note 2 when the nth (last) transmission/reception is complete, read the nth (last) data. ? starting transmission/reception when written ? storing the data to be transmitted second and subsequently when transmission/reception is complete, write the data to be transmitted next to this register to start the next transmission/reception. storing the data to be transmitted first note 2 before starting transmission/reception (writing to sotbn), write the data to be transmitted first. receive-only mode ? reading starts reception ? storing received data ? first, read dummy data and start transfer. ? to perform reception of the next data after reception is complete, read the received data from this register. storing the data received last note 2 if reception of the next data will not be performed after reception is complete, read the received data from this register. ? not used ? not used ? not used single transfer transmission/reception mode storing received data note 2 when transmission and reception are complete, read the received data from this register. ? not used. ? not used. ? starting transmission/reception when written ? storing the data to be transmitted ? when transmission/reception is complete, write the data to be transmitted next. ? not used function use method function use method function use method function use method function use method r/w read read read write write table 15-1. use of each buffer register register name sirbn (sirbnl) sirben (sirbenl) sio0n (sio0nl) sotbn (sotbnl) sotbfn (sotbfnl) notes 1. it is assumed that the number of data to be transmitted is n. 2. neither reading nor writing will start communication. remark in the 16-bit mode, the registers not enclose d in parentheses are used; in the 8-bit mode, the registers in parentheses are us ed.
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 430 15.4 operation 15.4.1 transmission/reception completion interrupt request signal (intcsi0n) the intcsi0n signal is set (1) upon comple tion of data transmission/reception. writing to the csim0n register clears (0) the intcsi0n signal. caution the delay mode (csim0n.csi tn bit = 1) is valid only in th e master mode (csicn.cks0n2 to csicn.cks0n0 bits are not 111b). the delay m ode cannot be set when the slave mode is set (cks0n2 to cks0n0 bits = 111b).
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 431 figure 15-2. timing chart of intcsi0n signal output in delay mode (a) transmit/receive type 1 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n signal csotn bit delay (b) transmit/receive type 4 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n signal csotn bit delay remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0, 1
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 432 15.4.2 single transfer mode (1) usage in the receive-only mode (csim0n.trmdn bit = 0), co mmunication is started by reading the sirbn/sirbnl register. in the transmission/reception mode (trmdn bit = 1) , communication is started by writing to the sotbn/sotbnl register. in the slave mode, the operation must be en abled beforehand (csim0n.csi0en bit = 1). when communication is started, t he value of the csim0n.csotn bit becomes 1 (transmission execution status). upon communication completion, the transmission/recepti on completion interrupt request signal (intcsi0n) is generated, and the csotn bit is cleared (0). t he next data communication request is then waited for. caution when the csotn bit = 1, do not manipulate the csi0n register. remark n = 0, 1
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 433 figure 15-3. timing chart in single transfer mode (1/2) (a) in transmission/recepti on mode, data length: 8 bits , transfer direction: msb first, no interrupt delay, single transfer mode, when aah is received and 55h is transmitted, transmit/receive type 1 01010101 10101010 (55h) (aah) aah aah abh 56h adh 5ah b5h 6ah d5h sck0n (i/o) so0n (output) si0n (input) reg_r/w sotbnl register sio0nl register sirbnl register csotn bit intcsi0n signal 55h (transmit data) write 55h to sotbnl register remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. for the transmit/receive types, refer to 15.3 (2) clocked serial interface clock selection register n (csicn) . 3. n = 0, 1
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 434 figure 15-3. timing chart in single transfer mode (2/2) (b) in transmission/reception mode, da ta length: 8 bits, transfer directi on: msb first, no interrupt delay, single transfer mode, when aah is received and 55h is transmitted, transmit/receive type 2 01010101 10101010 aah aah abh 56h adh 5ah b5h 6ah d5h sck0n (i/o) so0n (output) si0n (input) reg_r/w sotbnl register sio0nl register sirbnl register csotn bit intcsi0n signal (55h) (aah) 55h (transmit data) write 55h to sotbnl register remarks 1. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. for the transmit/receive types, refer to 15.3 (2) clocked serial interface clock selection register n (csicn) . 3. n = 0, 1
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 435 15.4.3 continuous transfer mode (1) usage (receive-only: 8-bit data length) <1> set the continuous transfer mode (csim0n. auton bit = 1) and the receive-only mode (csim0n.trmdn bit = 0). <2> read the sirbnl register (start transfer with dummy read). <3> when the transmission/reception completion interr upt request signal (intcs i0n) has been generated, read the sirbnl register note (reserve next transfer). <4> repeat step <3> (n ? 2) times. (n: number of transfer data) ignore the interrupt trigger ed by reception of the (n ? 1)th data (at this time, the sirbenl register can be read). <5> following generation of the last intcsi0n sign al, read the sirbenl r egister and the sio0nl register note . note when transferring n number of data, receive data is loaded by reading the sirbnl register from the first data to the (n ? 2)th data. the (n ? 1)th data is loaded by readi ng the sirbenl register, and the nth (last) data is loaded by readi ng the sio0nl register (refer to table 15-1 use of each buffer register ).
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 436 figure 15-4. continuous transf er (receive-only) timing chart ? transmit/receive type 1, 8-bit data length din-1 sck0n (i/o) si0n (input) so0n (output) l sio0nl register sirbnl register reg-rd csotn bit intcsi0n signal rq_clr trans_rq din-2 din-1 sirbn (dummy) sirbn (1) sirbn (d2) sirbn (d3) sirben (d4) sio0n (d5) <3> <5> <3> <3> <4> period during which next transfer can be reserved <2> <1> din-2 din-3 din-4 din-5 din-5 din-3 din-4 remarks 1. reg_rd: internal signal. this signal indica tes that the sirbnl register has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. 2. n = 0, 1 in the case of the continuous transfer mode, two transfer requests are set at the star t of the first transfer. following the intcsi0n signal, transfer is continued if the sirbnl register can be read within the next transfer reservation period. if the sirbnl register cannot be read, transfer ends and the sirbnl register does not receive the new value of the sio0nl register. the last data can be obtained by reading the sio0nl register following completion of the transfer.
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 437 (2) usage (transmission/reception: 8-bit data length) <1> set the continuous transfer mode (csim0n.au ton bit = 1) and the transmission/reception mode (csim0n.trmdn bit = 1). <2> write the first data to the sotbfnl register. <3> write the 2nd data to the sotb nl register (start transfer). <4> when the transmission/reception completion interr upt request signal (intcs i0n) has been generated, write the next data to the sotbnl regi ster (reserve next transfer). re ad the sirbnl register to load the receive data. <5> repeat step <4> as long as data to be sent remains. <6> when the intcsi0n signal is generated, r ead the sirbnl register to load the (n ? 1)th receive data (n: number of transfer data). <7> following the last intcsi0n signal, read the sio0nl register to load the nth (last) receive data.
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 438 figure 15-5. continuous transfer (transmission/reception) timing chart ? transmit/receive type 1, 8-bit data length dout-1 dout-1 sck0n (i/o) so0n (output) si0n (input) sotbfnl register sotbnl register sio0nl register sirbnl register reg_wr reg_rd csotn bit intcsi0n signal rq_clr trans_rq dout-2 dout-3 dout-4 dout-5 dout-2 dout-3 dout-4 dout-5 din-1 din-1 sotbfn (d1) sotbn (d2) sotbn (d3) sotbn (d4) sotbn (d5) sirbn (d1) sirbn (d2) < 5 >< 7 >< 8 > < 4 > < 5 > < 4 > < 6 > period during which next transfer can be reserved < 5 > < 4 > < 3 > < 2 > < 1 > sirbn (d3) sirbn (d4) sion (d5) din-2 din-3 din-4 din-5 din-2 din-3 din-4 din-5 remarks 1. reg_wr: internal signal. this signal indicate s that the sotbnl regist er has been written. reg_rd: internal signal. this signal indica tes that the sirbnl register has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. 2. n = 0, 1 in the case of the continuous transfe r mode, two transfer requests are set at the start of the first transfer. following the intcsi0n signal, transfer is continued if the sotbnl register can be written within the next transfer reservation period. if the sotbnl register cannot be written, transfer ends and the sirbnl register does not receive the new value of the sio0nl register. the last receive data can be obtained by reading the sio0nl register follo wing completion of the transfer.
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 439 (3) next transfer reservation period in the continuous transfer mode, the next transfer mu st be prepared with the period shown in figure 15-6. figure 15-6. timing chart of next transfer reservation period (1/2) (a) when data length: 8 bits, transmit/receive type 1 sck0n (i/o) intcsi0n signal reservation period: 7 sck0n cycles (b) when data length: 16 bi ts, transmit/receive type 1 sck0n (i/o) intcsi0n signal reservation period: 15 sck0n cycles remark n = 0, 1
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 440 figure 15-6. timing chart of next transfer reservation period (2/2) (c) when data length: 8 bi ts, transmit/receive type 2 sck0n (i/o) intcsi0n signal reservation period: 6.5 sck0n cycles (d) when data length: 16 bi ts, transmit/receive type 2 sck0n (i/o) intcsi0n signal reservation period: 14.5 sck0n cycles remark n = 0, 1
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 441 (4) cautions to continue continuous transfers, it is necessary to either read the sirb n register or write to the sotbn register during the transfer reservation period. if access is performed to the sirbn register or the so tbn register when the transfer reservation period is over, the following occurs. (i) in case of conflict between transfer request clear and register access since transfer request clear has higher priority, the nex t transfer request is ignored. therefore, transfer is interrupted, and normal data transfer cannot be performed. figure 15-7. transfer request clear and register access conflict sck0n (i/o) intcsi0n signal rq_clr reg_r/w transfer reservation period remarks 1. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0, 1
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 442 (ii) in case of conflict between tr ansmission/reception completion inte rrupt request sign al (intcsi0n) generation and register access since continuous transfer has stopped once, ex ecuted as a new continuous transfer. in the slave mode, a bit phase erro r transfer error results (refer to figure 15-8 ). in the transmission/reception mode, the value of the so tbfn register is retransmitted, and illegal data is sent. figure 15-8. interrupt request and register ac cess conflict sck0n (i/o) intcsi0n signal rq_clr reg_r/w transfer reservation period 01 234 remarks 1. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indica tes that the sirbn/sirb nl register read or the sotbn/sotbnl register write was performed. 2. n = 0, 1
chapter 15 clocked serial interface 0 (csi0) user?s manual u17705ej2v0ud 443 15.5 output pins the following describes the output pins. for the setting of each pin, refer to table 4-12 settings when port pins are used for alternate functions . (1) sck0n pin when the csi0n operation is disabled (csim0n.csi0en bi t = 0), the sck0n pin output status is as follows. table 15-2. sck0n pin output status ckpn cks0n2 cks0n1 cks0n0 sck0n pin output 0 don?t care don?t care don?t care fixed to high level 1 1 1 high impedance 1 other than above fixed to low level remark n = 0, 1 (2) so0n pin when the csi0n operation is disabled (csi0en bit = 0), the so0n pin output status is as follows. table 15-3. so0n pin output status trmdn dapn auton ccln dirn so0n pin output 0 don?t care don?t care don?t care don?t care fixed to low level 0 don?t care don?t care don?t care so latch value (low level) 0 sotbn7 bit value 0 1 sotbn0 bit value 0 sotbn15 bit value 0 1 1 sotbn0 bit value 0 sotbfn7 bit value 0 1 sotbfn0 bit value 0 sotbfn15 bit value 1 1 1 1 1 sotbfn0 bit value remark n = 0, 1
444 user?s manual u17705ej2v0ud chapter 16 i 2 c bus to use the i 2 c bus function, use the p38/sda0 and p39/scl0 pins as the serial transmit/receive data i/o pin (sda0) and the serial clock i/o pin (scl0), respec tively, and set them to n-ch open-drain output. in the v850es/ke2, one channel of i 2 c bus is provided. 16.1 features the i 2 c0 has the following two modes. ? operation stop mode ? i 2 c (inter ic) bus mode (multimaster supported) (1) operation stop mode this mode is used when serial transfers are not per formed. it can therefor e be used to reduce power consumption. (2) i 2 c bus mode (multi master supported) this mode is used for 8-bit data transfers with several dev ices via two lines: a serial clock (scl0) line and a serial data bus (sda0) line. this mode complies with the i 2 c bus format and the master device can generate ?start condition?, ?address?, ?transfer direction specification?, ? data?, and ?stop condition? data to the sl ave device, via the serial data bus. the slave device automatically detects these received st ate and data by hardware. this function can simplify the part of application progr am that controls the i 2 c bus. since the scl0 and sda0 pins are used for n-ch open drain outputs, i 2 c0 requires pull-up resistors for the serial clock line and the serial data bus line.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 445 figure 16-1. block diagram of i 2 c0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) so latch iice0 dq cl01, cl00 trc0 dfc0 dfc0 sda0 scl0 output control intiic0 iic shift register 0 (iic0) iicc0.stt0, spt0 iics0.msts0, exc0, coi0 iics0.msts0, exc0, coi0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 internal bus cld0 dad0 smc0 dfc0 cl01 cl00 clx0 iic clock select register 0 (iiccl0) stcf0 iicbsy0 stcen0 iicrsv0 iic flag register 0 (iicf0) iic function expansion register 0 (iicx0) fxx clear slave address register 0 (sva0) match signal set noise eliminator iic shift register 0 (iic0) data retention time correction circuit n-ch open-drain output ack detector ack generator start condition detector stop condition detector serial clock counter serial clock controller noise eliminator n-ch open-drain output start condition generator stop condition generator wakeup controller interrupt request signal generator serial clock wait controller bus status detector prescaler
chapter 16 i 2 c bus 446 user?s manual u17705ej2v0ud a serial bus configuration example is shown below. figure 16-2. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 447 16.2 configuration i 2 c0 includes the following hardware. table 16-1. configuration of i 2 c0 item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers iic control register 0 (iicc0) iic status register 0 (iics0) iic flag register 0 (iicf0) iic clock selection register 0 (iiccl0) iic function expansion register 0 (iicx0) (1) iic shift register 0 (iic0) the iic0 register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8- bit serial data. the iic0 register can be used for both transmission and reception. write and read operations to the iic0 r egister are used to control the act ual transmit and receive operations. the iic0 register can be read or written in 8-bit units. reset sets iic0 to 00h. (2) slave address register 0 (sva0) the sva0 register sets local addresses when in slave mode. the sva0 register can be read or written in 8-bit units. reset sets sva0 to 00h. (3) so latch the so latch is used to retain the sda0 pin?s output level. (4) wakeup controller this circuit generates an interrupt r equest signal (intiic0) when the address re ceived by this register matches the address value set to the sva0 register or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks t hat are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic0). an i 2 c interrupt is generated followi ng either of two triggers. ? falling of the eighth or ninth clock of t he serial clock (set by iicc0.wtim0 bit) ? interrupt request generated when a stop condition is detected (set by iicc0.spie0 bit)
chapter 16 i 2 c bus 448 user?s manual u17705ej2v0ud (8) serial clock controller in master mode, this circuit generates the clo ck output via the scl0 pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack generator, stop condition detector, start condition detector, and ack detector these circuits are used to gener ate and detect various statuses. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (12) start condition generator this circuit generates a start condition when the iicc0.stt0 bit is set. however, in the communication reservation disabled st atus (iicf0.iicrsv0 bit = 1), when the bus is not released (iicf0.iicbsy0 bit = 1), start condition requests are ignored and the iicf0.stcf0 bit is set to 1. (13) stop condition generator a stop condition is generated when t he iic0.spt0 bit is set (1). (14) bus status detector this circuit detects whether or not the bus is rel eased by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediatel y following operation, the init ial status is set by the iicf0.stcen0 bit.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 449 16.3 registers i 2 c0 is controlled by the following registers. ? iic control register 0 (iicc0) ? iic status register 0 (iics0) ? iic flag register 0 (iicf0) ? iic clock selection register 0 (iiccl0) ? iic function expansion register 0 (iicx0) the following registers are also used. ? iic shift register 0 (iic0) ? slave address register 0 (sva0) remark for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions . (1) iic control register 0 (iicc0) the iicc0 register is used to enable/stop i 2 c0 operations, set wait timing, and set other i 2 c operations. the iicc0 register can be r ead or written in 8-bit or 1-bit units. however, set the spie0, wtim0, and acke0 bits when the iice0 bit is 0 or during the wait period. when setting the iice0 bit from ?0? to ?1?, these bits can also be set at the same time. reset sets this register to 00h.
chapter 16 i 2 c bus 450 user?s manual u17705ej2v0ud (1/4) after reset: 00h r/w address: iicc0 fffffd82h <7> <6> <5> <4> <3> <2> <1> <0> iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c0 operation enable/dis able specification 0 stop operation. reset the iics0 register note 1 . stop internal operation. 1 enable operation. be sure to set this bit to 1 when the scl0 and sda0 lines are high level. condition for clearing (iice0 bit = 0) condition for setting (iice0 bit = 1) ? cleared by instruction ? reset ? set by instruction lrel0 note 2 exit from communications 0 normal operation 1 this exits from the current communications and sets standby mode. this setting is automatically cleared to 0 after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines are set to high impedance. the stt0, spt0, iics0.msts0, iics0.exc0, iics0.coi 0, iics0.trc0, iics0.ackd0, and iics0.std0 bits are cleared to 0. the standby mode following exit from communications remains in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rec eption occurs after the start condition. condition for clearing (lrel0 bit = 0) condition for setting (lrel0 bit = 1) ? automatically cleared after execution ? reset ? set by instruction wrel0 note 2 wait cancellation control 0 do not cancel wait 1 cancel wait. this setting is automatica lly cleared to 0 after wait is canceled. condition for clearing (wrel0 bit = 0) condition for setting (wrel0 bit = 1) ? automatically cleared after execution ? reset ? set by instruction notes 1. the iics0 register, and the iicf0.stcf0, iicf0 .iicbsy0, iiccl0.cld0, and iiccl0.dad0 bits are reset. 2. this flag?s signal is invalid when the iice0 bit = 0. caution if the i 2 c0 operation is enabled (iice0 bit = 1) when the scl0 line is high level and the sda0 line is low level, the start condition is detected immediately. to avoid this, after enabling the i 2 c0 operation, immediately set the lrel0 bit to 1 with a bit manipulation instruction.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 451 (2/4) spie0 note enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spie0 bit = 0) condition for setting (spie0 bit = 1) ? cleared by instruction ? reset ? set by instruction wtim0 note control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clocks, the clock is set to low level and wait is set for master device. an interrupt is generated at the falling of the 9th clock during address transfer independently of the setting of this bit. the setting of this bit is valid when the address transfer is co mpleted. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after ack is issued. however, when t he slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim0 bit = 0) condition for setting (wtim0 bit = 1) ? cleared by instruction ? reset ? set by instruction acke0 note acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during t he ninth clock period, the sda0 line is set to low level. the acke0 bit setting is invalid for address reception. in this case, ack is generated when the addresses match. however, the acke0 bit setting is valid for address reception of the extension code. condition for clearing (acke0 bit = 0) condition for setting (acke0 bit = 1) ? cleared by instruction ? reset ? set by instruction note this flag?s signal is invalid when the iice0 bit = 0.
chapter 16 i 2 c bus 452 user?s manual u17705ej2v0ud (3/4) stt0 start condition trigger 0 do not generate a start condition. 1 when bus is released (in stop mode): generate a start condition (for starting as master). the sda0 line is changed from high level to low level while the scl0 line is high level and then the start c ondition is generated. next, after the rated amount of time has elapsed, the scl0 line is changed to low level (wait status). when a third party is communicating ? when communication reservation functi on is enabled (iicf0.iicrsv0 bit = 0) functions as the start condition reservation flag. when set to 1, automatically generates a start condition after the bus is released. ? when communication reservation functi on is disabled (iicrsv0 bit = 1) the iicf0.stcf0 bit is set to 1 and the informati on set (1) to the stt0 bit is cleared. no start condition is generated. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acke0 bit has been cleared to 0 and slave has been notified of final reception. for master transmission: a start condition may not be generat ed normally during the ack period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the spt0 bit. ? when the stt0 bit is set to 1, setting the stt0 bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (stt0 bit = 0) condition for setting (stt0 bit = 1) ? when the stt0 bit is set to 1 in the communication reservation disabled status ? cleared by loss in arbitration ? cleared when start conditi on is generated by master device ? when the lrel0 bit = 1 (e xit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? set by instruction remark the stt0 bit is 0 if it is read after data setting.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 453 (4/4) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda0 line goes to low level, either set the scl0 line to high level or wait until the scl0 pin goes to high level. next, after the rated amount of time has elapsed, the sda0 line is changed from low level to high level and a stop condition is generated. cautions concerning setting timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acke0 bit has been cleared to 0 and during the wait period after slave has been notified of final reception. for master transmission: a stop condition may not be generated normally during the ack period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the stt0 bit. ? the spt0 bit can be set to 1 only when in master mode note . ? when the wtim0 bit has been cleared to 0, if the spt0 bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generat ed during the high-level period of the ninth clock. the wtim0 bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the spt0 bit should be set to 1 during the wait peri od that follows output of the ninth clock. ? when the spt0 bit is set to 1, setting the spt0 bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (spt0 bit = 0) condition for setting (spt0 bit = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when the lrel0 bit = 1 (e xit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? set by instruction note set the spt0 bit to 1 only in master mode. however, the spt0 bit must be set to 1 and a stop condition generated before the first stop condition is detected follo wing the switch to operation enable status. for details, refer to 16.14 cautions . caution when the iics0.trc0 bit is set to 1, th e wrel0 bit is set to 1 during the ninth clock and wait is canceled, after which the trc0 bi t is cleared to 0 and the sda0 line is set to high impedance. remark the spt0 bit is 0 if it is read after data setting.
chapter 16 i 2 c bus 454 user?s manual u17705ej2v0ud (2) iic status register 0 (iics0) the iics0 register indica tes the status of the i 2 c0 bus. the iics0 register is read-only, in 8-bit or 1-bit units. however, the iics0 register can only be read when t he iicc0.stt0 bit is 1 or during the wait period. reset sets this register to 00h. caution when the main clock is stopped and the cpu is operating on the subclock, do not access the iics0 register. for de tails, refer to 3.4.8 (2). (1/3) after reset: 00h r address: iics0 fffffd86h <7> <6> <5> <4> <3> <2> <1> <0> iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 bit = 0) condition for setting (msts0 bit = 1) ? when a stop condition is detected ? when the ald0 bit = 1 (arbitration loss) ? cleared by the iicc0.lrel0 bit = 1 (exit from communications) ? when the iicc0.iice0 bit changes from 1 to 0 (operation stop) ? reset ? when a start condition is generated ald0 detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. the msts0 bit is cleared to 0. condition for clearing (ald0 bit = 0) condition for setting (ald0 bit = 1) ? automatically cleared after the iics0 register is read note ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when the arbitration result is a ?loss?. note the ald0 bit is also cleared when a bit manipulation instruction is executed fo r another bit in the iics0 register.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 455 (2/3) exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 bit = 0) condition for setting (exc0 bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when the higher four bits of the received address data is either ?0000? or ?1111? (s et at the rising edge of the eighth clock). coi0 detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi0 bit = 0) condition for setting (coi0 bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 ? reset ? when the received address matches the local address (sva0 register) (set at the rising edge of the eighth clock). trc0 detection of transmit/receive status 0 receive status (other than transmit status ). the sda0 line is set for high impedance. 1 transmit status. the value in the so latch is enabled for output to the sda0 line (valid starting at the rising edge of the first byte?s ninth clock). condition for clearing (trc0 bit = 0) condition for setting (trc0 bit = 1) ? when a stop condition is detected ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? cleared by the iicc0.wrel0 bit = 1 note (wait release) ? when the ald0 bit changes from 0 to 1 (arbitration loss) ? reset master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated ? when ?0? is output to the first byte?s lsb (transfer direction specification bit) slave ? when ?1? is input in the first byte?s lsb (transfer direction specification bit) note the iics0.trc0 bit is cleared to 0 and the sda0 line become high impedance when the iicc0.wrel0 bit is set to 1 and wait state is rel eased at the ninth clock with the trc0 bit = 1.
chapter 16 i 2 c bus 456 user?s manual u17705ej2v0ud (3/3) ackd0 detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackd0 bit = 0) condition for setting (ackd0 bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? after the sda0 pin is set to low level at the rising edge of the scl0 pin?s ninth clock std0 detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (std0 bit = 0) condition for setting (std0 bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by the lrel0 bit = 1 (exit from communications) ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when a start condition is detected spd0 detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device?s communication is terminated and the bus is released. condition for clearing (spd0 bit = 0) condition for setting (spd0 bit = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when a stop condition is detected
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 457 (3) iic flag register 0 (iicf0) iicf0 is a register that set the operation mode of i 2 c0 and indicate the status of the i 2 c bus. these registers can be read or writt en in 8-bit or 1-bit units. howeve r, the stcf0 and iicbsy0 bits are read- only. the iicrsv0 bit can be used to enable/disable t he communication reservation function (refer to 16.13 communication reservation ). the stcen0 bit can be used to set the in itial value of the iicbsy0 bit (refer to 16.14 cautions ). the iicrsv0 and stcen0 bits can be written only when the operation of i 2 c0 is disabled (iicc0.iice0 bit = 0). when operation is enabled, the iic f0 register can be read. reset sets this register to 00h.
chapter 16 i 2 c bus 458 user?s manual u17705ej2v0ud <7> stcf0 condition for clearing (stcf0 bit = 0) ? clearing by setting the stt0 bit = 1 ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset condition for setting (stcf0 bit = 1) ? generating start condition unsuccessful and the stt0 bit cleared to 0 when communication reservation is disabled (iicrsv0 bit = 1). stcf0 0 1 generate start condition start condition generation unsuccessful: clear stt0 flag iicc0.stt0 clear flag iicf0 <6> iicbsy0 5 0 4 0 3 0 2 0 <1> stcen0 <0> iicrsv0 after reset: 00h r/w note address: iicf0 fffffd8ah condition for clearing (iicbsy0 bit = 0) ? detection of stop condition ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset condition for setting (iicbsy0 bit = 1) ? detection of start condition ? setting of the iice0 bit when the stcen0 bit = 0 iicbsy0 0 1 bus release status (initial communication status when stcen0 bit = 1) bus communication status (initial communication status when stcen0 bit = 0) i 2 c0 bus status flag condition for clearing (stcen0 bit = 0) ? detection of start condition ? reset condition for setting (stcen0 bit = 1) ? setting by instruction stcen0 0 1 after operation is enabled (iice0 bit = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iice0 bit = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsv0 bit = 0) ? clearing by instruction ? reset condition for setting (iicrsv0 bit = 1) ? setting by instruction iicrsv0 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only bits. cautions 1. write to the stcen0 bit only wh en the operation is stopped (iice0 bit = 0). 2. as the bus release status (iicbsy0 bit = 0) is recognized regardless of the actual bus status when the stcen0 bit = 1, when gene rating the first start condition (stt0 bit = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. write to the iicrsv0 bit only when the operation is stopped (iice0 bit = 0).
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 459 (4) iic clock selection register 0 (iiccl0) the iiccl0 register is used to set the transfer clock for the i 2 c0 bus. the iiccl0 register can be r ead or written in 8-bit or 1-bit units. however, the cld0 and dad0 bits are read- only. the smc0, cl01 and cl00 bits are set in combination with the iicx0.clx0 bit (refer to 16.3 (6) i 2 c0 transfer clock setting method ). set the iiccl0 register when the iicc0.iice0 bit = 0. reset sets this register to 00h. after reset: 00h r/w note address: iiccl0 fffffd84h 7 6 <5> <4> 3 2 1 0 iiccl0 0 0 cld0 dad0 smc0 dfc0 cl01 cl00 cld0 detection of scl0 pin level (valid only when iicc0.iice0 bit = 1) 0 the scl0 pin was detected at low level. 1 the scl0 pin was detected at high level. condition for clearing (cld0 bit = 0) condition for setting (cld0 bit = 1) ? when the scl0 pin is at low level ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when the scl0 pin is at high level dad0 detection of sda0 pin level (valid only when iice0 bit = 1) 0 the sda0 pin was detected at low level. 1 the sda0 pin was detected at high level. condition for clearing (dad0 bit = 0) condition for setting (dad0 bit = 1) ? when the sda0 pin is at low level ? when the iice0 bit changes from 1 to 0 (operation stop) ? reset ? when the sda0 pin is at high level smc0 operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfc0 digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of dfc0 bit set/clear. the digital filter is used for noi se elimination in high-speed mode. note bits 4 and 5 are read-only bits.
chapter 16 i 2 c bus 460 user?s manual u17705ej2v0ud (5) iic function expansion register 0 (iicx0) these registers set the function expansion of i 2 c0 (valid only in high-speed mode). these registers can be read or written in 8-bit or 1-bit units. the clx0 bit is set in combination with the iiccl0.smc0, iiccl0.cl01, and iiccl0.cl00 bits (refer to 16.3 (6) i 2 c0 transfer clock setting method ). set the iicx0 register when the iicc0.iice0 bit = 0. reset sets this register to 00h. after reset: 00h r/w address: iicx0 fffffd85h 7 6 5 4 3 2 1 <0> iicx0 0 0 0 0 0 0 0 clx0 (6) i 2 c0 transfer clock setting method the i 2 c0 transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m t + t r + t f ) m = 12, 24, 48, 54, 86, 88, 172, 198 (refer to table 16-2 selection clock setting .) t: 1/f xx t r : scl0 rise time t f : scl0 fall time for example, the i 2 c0 transfer clock frequency (f scl ) when f xx = 20 mhz, m = 54, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(54 50 ns + 200 ns + 50 ns) ? 339 khz m t + t r + t f m/2 t t f t r m/2 t scl0 scl0 inversion scl0 inversion scl0 inversion the selection clock is set using a combination of the iiccl0.smc0, iiccl0.cl01, and iiccl0.cl00 bits and the iicx0.clx0 bit.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 461 table 16-2. selection clock setting iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 selection clock transfer clock (f xx /m) settable internal system clock frequency (f xx ) range operation mode 0 0 0 0 f xx /2 f xx /88 4.0 mhz to 8.38 mhz 0 0 0 1 f xx /2 f xx /172 8.38 mhz to 16.76 mhz 0 0 1 0 f xx f xx /86 4.19 mhz to 8.38 mhz 0 0 1 1 f xx /3 f xx /198 16.0 mhz to 19.8 mhz normal mode (smc0 bit = 0) 0 1 0 x f xx /2 f xx /48 8 mhz to 16.76 mhz 0 1 1 0 f xx f xx /24 4 mhz to 8.38 mhz 0 1 1 1 f xx/ 3 f xx /54 16 mhz to 20 mhz high-speed mode (smc0 bit = 1) 1 0 x x setting prohibited 1 1 0 x f xx /2 f xx /24 8.00 mhz to 8.38 mhz 1 1 1 0 f xx f xx /12 4.00 mhz to 4.19 mhz high-speed mode (smc0 bit = 1) 1 1 1 1 setting prohibited remark x: don?t care
chapter 16 i 2 c bus 462 user?s manual u17705ej2v0ud (7) iic shift register 0 (iic0) the iic0 shift register is used for serial transmission/re ception (shift operations) that is synchronized with the serial clock. the iic0 shift register can be read or written in 8-bit units, but data s hould not be written to the iic0 shift register during a data transfer. access (read/write) the iic0 shift regist er only during the wait period. acce ssing this register in communication states other than the wa it period is prohibited. howe ver, for the master device, the iic0 shift register can be written once only after the transmission trigger bit (iicc0.stt0 bit) has been set to 1. when the iic0 shift register is written during wait, the wait is cancelled and data transfer is started. reset sets this register to 00h. after reset: 00h r/w address: iic0 fffffd80h 7 6 5 4 3 2 1 0 iic0 (8) slave address register 0 (sva0) the sva0 register holds the i 2 c bus?s slave addresses. however, rewriting this register is prohibited when the iics0.std0 bit = 1 (start condition detection). the sva0 register can be read or written in 8-bit units, but bit 0 is fixed to 0. reset sets this register to 00h. after reset: 00h r/w address: sva0 fffffd83h 7 6 5 4 3 2 1 0 sva0 0
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 463 16.4 functions 16.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. scl0 .............. this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. sda0 .............. this pi n is used for serial data input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. since outputs from the serial clock line and the serial dat a bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 16-3. pin configuration diagram v dd scl0 sda0 scl0 sda0 v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
chapter 16 i 2 c bus 464 user?s manual u17705ej2v0ud 16.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication fo rmat and the status generated by the i 2 c bus. the transfer timing for the ?start condition?, ?addre ss?, ?transfer direction spec ification?, ?data?, and ?stop condition? generated via the i 2 c bus?s serial data bus is shown below. figure 16-4. i 2 c bus?s serial data transfer timing 1 to 7 8 9 1 to 8 9 1 to 8 9 scl0 sda0 start condition address r/w ack data data stop condition ack ack the master device generates the start condition, slave address, and stop condition. ack can be generated by either the master or slave device (normally, it is generated by the devic e that receives 8- bit data). the serial clock (scl0) is continuously output by the master devic e. however, in the sl ave device, the scl0?s low- level period can be extended and a wait can be inserted. 16.5.1 start condition a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are generat ed when the master device starts a serial transfer to the slave device. start conditions can be det ected when the device is used as a slave. figure 16-5. start conditions h scl0 sda0 a start condition is generated when the iicc0.stt0 bit is set to 1 after a stop condition has been detected (iics0.spd0 bit = 1). when a start condition is detected, iics0.std0 bit is set to 1.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 465 16.5.2 addresses the 7 bits of data that follow the st art condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via bus lines. t herefore, each slave devic e connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and che cks whether or not the 7-bit address data matches the data values stored in the sva0 register. if the address dat a matches the sva0 values, the slave device is selected and communicates with the master device until t he master device generates a start condition or stop condition. figure 16-6. address address scl0 1 sda0 intiic0 note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (int iic0) is generated if a local addre ss or extension code is received during slave device operation. the slave address and the eighth bit, which specif ies the transfer direction as described in 16.5.3 transfer direction specification below, are together written to the iic0 regi ster and are then output. received addresses are written to the iic0 register. the slave address is assigned to the hi gher 7 bits of the iic0 register.
chapter 16 i 2 c bus 466 user?s manual u17705ej2v0ud 16.5.3 transfer di rection specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfe r direction. when this transfer direction specification bit has a value of 0, it indicates that the mast er device is transmitting data to a slave device. when the transfer direction specif ication bit has a value of 1, it indica tes that the master device is receiving data from a slave device. figure 16-7. transfer direction specification scl0 1 sda0 intiic0 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the interrupt request signal (int iic0) is generated if a local addre ss or extension code is received during slave device operation.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 467 16.5.4 ack ack is used to confirm the serial data stat us of the transmitting and receiving devices. the receiving device returns ack for every 8 bits of data it receives. the transmitting device normally receives ack after transmi tting 8 bits of data. when ack is returned from the receiving device, the reception is j udged as normal and processing continues. t he detection of ack is confirmed with the iics0.ackd0 bit. when the master device is the receivi ng device, after receiving the final dat a, it does not return ack and generates the stop condition. when the slave dev ice is the receiving device and does not return ack, the master device generates either a stop condition or a rest art condition, and then stops the current transmission. failure to return ack may be caused by the following factors. (a) reception was not performed normally. (b) the final data was received. (c) the receiving device (slave) does not exist for the specified address. when the receiving device sets the sda0 line to low level during the ninth clo ck, ack is generated (normal reception). when the iicc0.acke0 bit is set to 1, automatic ac k generation is enabled. trans mission of the eighth bit following the 7 address data bits causes the iics0.trc0 bit to be set. normally, set the acke0 bit to 1 for reception (trc0 bit = 0). when the slave device is receiving (when trc0 bit = 0), if the slave device cannot rece ive data or does not need to receive any more data, clear the acke0 bit to 0 to indi cate to the master that no more data can be received. similarly, when the master device is receiving (when trc0 bit = 0) and the subsequent data is not needed, clear the acke0 bit to 0 to prevent ack from being generated. th is notifies the slave device (transmitting device) of the end of the data transmissi on (transmission stopped). figure 16-8. ack scl0 1 sda0 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack when the local address is received, ack is automatically generated regardless of the value of the acke0 bit. no ack is generated if the received addre ss is not a local address (nack). when receiving the extension code, set the acke0 bit to 1 in advance to generate ack. the ack generation method during data rec eption is based on the wait timing setti ng, as described by the following. ? when 8-clock wait is selected (iicc0.wtim0 bit = 0): ack is generated at the falling edge of t he scl0n pin?s eighth clock if the acke0 bit is set to 1 before the wait state cancellation. ? when 9-clock wait is selected (iicc0.wtim0 bit = 1): ack is generated if the acke0 bit is set to 1 in advance.
chapter 16 i 2 c bus 468 user?s manual u17705ej2v0ud 16.5.5 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is generated when serial transfer from the master device to the slave device has been completed. stop conditions can be detected when the device is used as a slave. figure 16-9. stop condition h scl0 sda0 a stop condition is generated when the ii cc0.spt0 bit is set to 1. when the stop condition is detected, the iics0.spd0 bit is set to 1 and the interrupt request signal (i ntiic0) is generated when the iicc0 .spie0 bit is set to 1.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 469 16.5.6 wait state the wait state is used to not ify the communication partner t hat a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave dev ices, the next data transfer can begin. figure 16-10. wait state (1/2) (a) when master device has a nine-clock wa it and slave device has an eight-clock wait (master: transmission, slave: r eception, and iicc0.acke0 bit = 1) scl0 6 sda0 78 9 123 scl0 iic0 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iic0 data write (cancel wait) slave wait after output of eighth clock. ffh is written to iic0 register or iicc0.wrel0 bit is set to 1. transfer lines wait state from slave wait state from master
chapter 16 i 2 c bus 470 user?s manual u17705ej2v0ud figure 16-10. wait state (2/2) (b) when master and slave d evices both have a nine-clock wait (master: transmission, slave: reception, and acke0 = 1) scl0 6 sda0 789 123 scl0 iic0 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic0 scl0 acke0 master master and slave both wait after output of ninth clock. iic0 data write (cancel wait) slave ffh is written to iic0 register or wrel0 bit is set to 1. generated according to previously set acke0 bit value transfer lines wait state from master and slave wait state from slave a wait state is automatically generated after a start condition is generated. moreover, a wait stat e is automatically generated depending on the setting of the iicc0.wtim0 bit. normally, when the iicc0.wrel0 bit is set to 1 or when ffh is written to the iic0 regi ster, the wait status is canceled and the transmitting side writes data to t he iic0 register to cancel the wait status. the master device can also c ancel the wait status via ei ther of the following methods. ? by setting the iicc0.stt0 bit to 1 ? by setting the iicc0.spt0 bit to 1
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 471 16.5.7 wait state cancellation method in the case of i 2 c0, wait state can be canceled normally in the following ways. ? by writing data to the iic0 register ? by setting the iicc0.wrel0 bit to 1 (wait state cancellation) ? by setting the iicc0.stt0 bit to 1 (start condition generation) note ? by setting the iicc0.spt0 bit to 1 (stop condition generation) note note master only if any of these wait state canc ellation actions is performed, i 2 c0 will cancel wait state and restart communication. when canceling wait state and s ending data (including address), writ e data to the iic0 register. to receive data after canceling wait state, or to complete data transmission, set the wrel0 bit to 1. to generate a restart condition after canceli ng wait state, set the stt0 bit to 1. to generate a stop condition after canceling wait state, set the spt0 bit to 1. execute cancellation only once for each wait state. for example, if data is written to t he iic0 register following wait state canc ellation by setting the wrel0 bit to 1, conflict between the sda0 line change timing and iic0 register write timing may resu lt in the data output to the sda0 line may be incorrect. even in other operations, if communication is stopped halfway, clearing the iicc0.iice0 bit to 0 will stop communication, enabling wait state to be cancelled. if the i 2 c bus dead-locks due to noise, etc., setting the iicc0.lre l0 bit to 1 causes the communication operation to be exited, enabling wait st ate to be cancelled.
chapter 16 i 2 c bus 472 user?s manual u17705ej2v0ud 16.6 i 2 c interrupt request signals (intiic0) the following shows the value of the iic s0 register at the intiic0 interr upt request signal generation timing and at the intiic0 signal timing. remark st: start condition ad6 to ad0: address r/w: transfer direction specification ack: acknowledge d7 to d0: data sp: stop condition
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 473 16.6.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when iicc0.wtim0 bit = 0 iicc0.spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x000b s 3: iics0 register = 1000x000b (wtim0 bit = 1 note ) s 4: iics0 register = 1000xx00b 5: iics0 register = 00000001b note to generate a stop condition, set the wtim0 bit to 1 and change the timing of the generation of the interrupt request signal (intiic0). remark s : always generated : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x100b s 3: iics0 register = 1000xx00b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus 474 user?s manual u17705ej2v0ud (2) start ~ address ~ data ~ star t ~ address ~ data ~ stop (restart) <1> when wtim0 bit = 0 iicc0.stt0 bit = 1 spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 7 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x000b (wtim0 bit = 1 note 1 ) s 3: iics0 register = 1000xx00b (wtim0 bit = 0 note 2 ) s 4: iics0 register = 1000x110b s 5: iics0 register = 1000x000b (wtim0 bit = 1 note 3 ) s 6: iics0 register = 1000xx00b 7: iics0 register = 00000001b notes 1. to generate a start condition, set the wt im0 bit to 1 and change the timing of the generation of the interrupt request signal (intiic0). 2. clear the wtim0 bit to 0 to make the settings original. 3. to generate a stop condition, set the wt im0 bit to 1 and change the timing of the generation of the interrupt request signal (intiic0). remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 stt0 bit = 1 spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000xx00b s 3: iics0 register = 1000x110b s 4: iics0 register = 1000xx00b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 475 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtim0 bit = 0 spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 1010x110b s 2: iics0 register = 1010x000b s 3: iics0 register = 1010x000b (wtim0 bit = 1 note ) s 4: iics0 register = 1010xx00b 5: iics0 register = 00000001b note to generate a stop condition, set the wtim0 bit to 1 and change the timing of the generation of the interrupt request signal (intiic0). remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 1010x110b s 2: iics0 register = 1010x100b s 3: iics0 register = 1010xx00b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus 476 user?s manual u17705ej2v0ud 16.6.2 slave device operation (when recei ving slave address data (address match)) (1) start ~ address ~ data ~ data ~ stop <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001x000b s 3: iics0 register = 0001x000b 4: iics0 register = 00000001b remark s : always generated : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001x100b s 3: iics0 register = 0001xx00b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 477 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001x000b s 3: iics0 register = 0001x110b s 4: iics0 register = 0001x000b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001xx00b s 3: iics0 register = 0001x110b s 4: iics0 register = 0001xx00b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus 478 user?s manual u17705ej2v0ud (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtim0 bit = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001x000b s 3: iics0 register = 0010x010b s 4: iics0 register = 0010x000b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 6 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001xx00b s 3: iics0 register = 0010x010b s 4: iics0 register = 0010x110b s 5: iics0 register = 0010xx00b 6: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 479 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001x000b s 3: iics0 register = 00000110b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0001x110b s 2: iics0 register = 0001xx00b s 3: iics0 register = 00000110b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus 480 user?s manual u17705ej2v0ud 16.6.3 slave device operation (w hen receiving extension code) always under communication when re ceiving the extension code. (1) start ~ code ~ data ~ data ~ stop <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x000b s 3: iics0 register = 0010x000b 4: iics0 register = 00000001b remark s : always generated : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x110b s 3: iics0 register = 0010x100b s 4: iics0 register = 0010xx00b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 481 (2) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x000b s 3: iics0 register = 0001x110b s 4: iics0 register = 0001x000b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 6 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x110b s 3: iics0 register = 0010xx00b s 4: iics0 register = 0001x110b s 5: iics0 register = 0001xx00b 6: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus 482 user?s manual u17705ej2v0ud (3) start ~ code ~ data ~ st art ~ code ~ data ~ stop <1> when wtim0 bit = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x000b s 3: iics0 register = 0010x010b s 4: iics0 register = 0010x000b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 7 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x110b s 3: iics0 register = 0010xx00b s 4: iics0 register = 0010x010b s 5: iics0 register = 0010x110b s 6: iics0 register = 0010xx00b 7: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 483 (4) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtim0 bit = 0 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x000b s 3: iics0 register = 00000110b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 (after restart, address mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0010x010b s 2: iics0 register = 0010x110b s 3: iics0 register = 0010xx00b s 4: iics0 register = 00000110b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus 484 user?s manual u17705ej2v0ud 16.6.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 1: iics0 register = 00000001b remark : generated only when iicc0.spie0 bit = 1
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 485 16.6.5 arbitration loss operation (ope ration as slave after arbitration loss) when used as master in the multi-mast er system, check the arbitration result by reading the iics0.msts0 bit for checking arbitration result by eac h intiic0 interrupt occurrence. (1) when arbitration loss occurs duri ng transmission of slave address data <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0101x110b s 2: iics0 register = 0001x000b s 3: iics0 register = 0001x000b 4: iics0 register = 00000001b remark s : always generated : generated only when iicc0.spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0101x110b s 2: iics0 register = 0001x100b s 3: iics0 register = 0001xx00b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus 486 user?s manual u17705ej2v0ud (2) when arbitration loss occurs dur ing transmission of extension code <1> when wtim0 bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 0110x010b s 2: iics0 register = 0010x000b s 3: iics0 register = 0010x000b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 0110x010b s 2: iics0 register = 0010x110b s 3: iics0 register = 0010x100b s 4: iics0 register = 0010xx00b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 487 16.6.6 operation when arbitr ation loss occurs (no communicat ion after arbitration loss) when used as master in the multi-mast er system, check the arbitration result by reading the iics0.msts0 bit for checking arbitration result by eac h intiic0 interrupt occurrence. (1) when arbitration loss occurs dur ing transmission of slave address data st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 2 s 1: iics0 register = 01000110b 2: iics0 register = 00000001b remark s : always generated : generated only when iicc0.spie0 bit = 1 (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 2 s 1: iics0 register = 0110x010b iicc0.lrel0 bit is set to 1 by software 2: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus 488 user?s manual u17705ej2v0ud (3) when arbitration loss o ccurs during data transfer <1> when iicc0.wtim0 bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 3 s 1: iics0 register = 10001110b s 2: iics0 register = 01000000b 3: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 <2> when wtim0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 3 s 1: iics0 register = 10001110b s 2: iics0 register = 01000100b 3: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 489 (4) when arbitration loss occurs due to restart condition duri ng data transfer <1> not extension code (example: address mismatch) st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iics0 register = 1000x110b s 2: iics0 register = 01000110b 3: iics0 register = 00000001b remarks 1. s : always generated : generated only when spie0 bit = 1 x: don?t care 2. dn = d6 to d0 <2> extension code st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iics0 register = 1000x110b s 2: iics0 register = 0110x010b iicc0.lrel0 bit is set to 1 by software 3: iics0 register = 00000001b remarks 1. s : always generated : generated only when spie0 bit = 1 x: don?t care 2. dn = d6 to d0
chapter 16 i 2 c bus 490 user?s manual u17705ej2v0ud (5) when arbitration loss occurs due to stop condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp s 1 2 s 1: iics0 register = 1000x110b 2: iics0 register = 01000001b remarks 1. s : always generated : generated only when spie0 bit = 1 x: don?t care 2. dn = d6 to d0
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 491 (6) when arbitration loss occurs due to low level of sda0n pin when attempting to generate a restart condition <1> when wtim0 bit = 0 iicc0.stt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x000b (wtim0 bit = 1) s 3: iics0 register = 1000x100b (wtim0 bit = 0) s 4: iics0 register = 01000000b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 iicc0.stt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x100b s 3: iics0 register = 01000100b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus 492 user?s manual u17705ej2v0ud (7) when arbitration loss occurs due to a stop conditi on when attempting to gene rate a restart condition <1> when wtim0 bit = 0 stt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x000b (wtim0 bit = 1) s 3: iics0 register = 1000xx00b 4: iics0 register = 01000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 stt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000xx00b 3: iics0 register = 01000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 493 (8) when arbitration loss occurs due to low level of sda0n pin wh en attempting to generate a stop condition <1> when wtim0 bit = 0 iicc0.spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x000b (wtim0 bit = 1) s 3: iics0 register = 1000x100b (wtim0 bit = 0) s 4: iics0 register = 01000100b 5: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care <2> when wtim0 bit = 1 iicc0.spt0 bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iics0 register = 1000x110b s 2: iics0 register = 1000x100b s 3: iics0 register = 01000100b 4: iics0 register = 00000001b remark s : always generated : generated only when spie0 bit = 1 x: don?t care
chapter 16 i 2 c bus 494 user?s manual u17705ej2v0ud 16.7 interrupt request signal (intiic0) generation timing and wait control the setting of the iicc0.wtim0 bit determines the ti ming by which the intiic 0 signal is generated and the corresponding wait control, as shown below. table 16-3. intiic0 signal gene ration timing and wait control during slave device operation du ring master device operation wtim0 bit address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiic0 signal and wait period o ccurs at the falling edge of the ninth clock only when there is a match with the addre ss set to the sva0 register. at this point, ack is generated regardless of the va lue set to the iicc0.acke0 bit. for a slave device that has received an extension code, the intiic0 signal occurs at t he falling edge of the eighth clock. when the address does not match after restart, the intiic0 signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not ma tch the contents of the sva0 regi ster and extensi on codes have not been received, neither the intiic0 signal nor a wait occurs. remark the numbers in the table indicate the number of the serial clock?s cl ock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined depending on the conditions in notes 1 and 2 above regardless of the wtim0 bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtim0 bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 495 (4) wait cancellation method the four wait cancellation methods are as follows. ? by writing data to the iic0 register ? by setting the iicc0.wrel0 bit (canceling wait state) ? by setting the iicc0.stt0 bit (generating start condition) note ? by setting the iicc0.spt0 bit (generating stop condition) note note master only when an 8-clock wait has been selected (wtim0 bit = 0), whether or not ac k has been generated must be determined prior to wait cancellation. (5) stop condition detection the intiic0 signal is generated w hen a stop condition is detected. 16.8 address match detection method when in i 2 c bus mode, the master device c an select a particular slave device by transmitting the corresponding slave address. address match detection is performed autom atically by hardware. an intiic 0 interrupt request signal occurs when a local address has been set to the sva0 register and when t he address set to the sva0 register matches the slave address sent by the master device, or when an extension code has been received. 16.9 error detection in i 2 c bus mode, the status of the serial data bus (sda0) during data transmission is capt ured by the iic0 register of the transmitting device, so the iic 0 register data prior to transmission can be compared with the transmitted iic0 register data to enable detection of tr ansmission errors. a transmission error is judged as having occurred when the compared data values do not match.
chapter 16 i 2 c bus 496 user?s manual u17705ej2v0ud 16.10 extension code (1) when the higher 4 bits of the receive address are eit her 0000 or 1111, the extension code flag (exc0) is set for extension code reception and an interrupt request signal (intiic0) is issued at the falling edge of the eighth clock. the local address stored in the sva0 register is not affected. (2) if 11110xx0 is set to the sva0 register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that the int iic0 signal occurs at the fa lling edge of the eighth clock. ? higher 4 bits of data match: iics0.exc0 bit = 1 ? 7 bits of data match: iics0.coi0 bit = 1 (3) since the processing after the intiic0 signal occurs diffe rs according to the data that follows the extension code, such processing is performed by software. the slav e that has received an ext ension code is always under communication, even if the addresses mismatch. for example, when operation as a sl ave is not desired after the extension code is received, set the iicc0.lrel0 bit to 1 and the cpu will enter the next communication wait state. table 16-4. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 497 16.11 arbitration when several master devices simultaneous ly generate a start condition (when the iicc0.stt0 bit is set to 1 before the iics0.std0 bit is set to 1), communication among the ma ster devices is performed as the number of clocks is adjusted until the data differs. this ki nd of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (iic s0.ald0 bit) is set (1) via the timing by which the arbitration loss occurr ed, and the scl0 and sda0 lines are both set for high impedance, which releases the bus. the arbitration loss is detec ted based on the timing of the next interrupt request signal (i ntiic0) (the eighth or ninth clock, when a stop condition is detec ted, etc.) and the ald0 bit = 1 se tting that has been made by software. for details of interrupt request timing, refer to 16.6 i 2 c interrupt request signals (intiic0) . figure 16-11. arbitration timing example master 1 master 2 transfer lines scl0 sda0 scl0 sda0 scl0 sda0 master 1 loses arbitration hi-z hi-z
chapter 16 i 2 c bus 498 user?s manual u17705ej2v0ud table 16-5. status during arbitration and interrupt request generation timing status during arbitration inte rrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack transfer period after data reception when restart condition is det ected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected duri ng data transfer when stop condition is generated (when iicc0.spie0 bit = 1) note 2 when the sda0 pin is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate a restart condition when stop condition is generated (when spie0 bit = 1) note 2 when the sda0 pin is at low level while attempting to generate a stop condition when the scl0 pin is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when the iicc0.wtim0 bit = 1, an interrupt request o ccurs at the falling edge of the ninth clock. when the wtim0 bit = 0 and the extension code?s slave addr ess is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set the spie0 bit = 1 for master device operation. 16.12 wakeup function the i 2 c bus slave function is a function t hat generates an interrupt request signal (intiic0) when a local address or extension code has been received. this function makes processing more efficient by prev enting unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wa keup standby mode is set. this wak eup standby mode is in effect while addresses are transmitted due to the possi bility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. however, when a stop condition is detect ed, the iicc0.spie0 bit is set regardl ess of the wake up function, and this determines whether interrupt r equests are enabled or disabled.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 499 16.13 communication reservation 16.13.1 when communication reservation func tion is enabled (iicf0.iicrsv0 bit = 0) to start master device communications when not current ly using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is re leased. there are two modes under which the bus is not used. ? when arbitration results in neit her master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iicc0.lrel0 bit was set to ?1?). if the iicc0.stt0 bit is set (1) while the bus is not used, a start condition is automatic ally generated and wait status is set after the bus is released (after a stop condition is detected). a communication is automatically start ed as the master by setting the iicc0 .spie0 bit to 1, detecting the bus release due to an interrupt request (intiic0) occurrence ( detecting a stop condition), and then writing the address to the iic0 register. before detecting a stop condition, dat a written to the iic0 register is set to invalid. when the stt0 bit has been set (1), the operation mode (as start condition or as communication reservation) is determined according to the bus status. if the bus has been re leased .............................................. a start condition is generated if the bus has not been released (standby mode) .............. comm unication reservation to detect which operation mode has been dete rmined for the stt0 bit, set the stt0 bi t (1), wait for the wait period, then check the iics0.msts0 bit. wait periods, which should be set via software, are listed in table 16-6. these wait periods can be set via the settings for the iicx0.clx0, iiccl0.sm c0, iiccl0.cl01, and iiccl0.cl00 bits. table 16-6. wait periods clx0 smc0 cl01 cl00 selected clock wait period 0 0 0 0 f xx /2 46 clocks 0 0 0 1 f xx /2 86 clocks 0 0 1 0 f xx 43 clocks 0 0 1 1 f xx /3 102 clocks 0 1 0 1/0 f xx /2 30 clocks 0 1 1 0 f xx 15 clocks 0 1 1 1 f xx /3 36 clocks 1 1 0 1/0 f xx /2 18 clocks 1 1 1 0 f xx 9 clocks
chapter 16 i 2 c bus 500 user?s manual u17705ej2v0ud the communication reservation timing is shown below. figure 16-12. communication reservation timing 2 13456 2 13456 789 scl0 sda0 stt0=1 program processing hardware processing write to iic0 set spd0 and intiic0 communication reservation set std0 generated by master with bus access iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are accepted via the following timing. after the iics0.std0 bit is set to 1, a communication reservation can be made by setting the iicc0 .stt0 bit to 1 before a stop condition is detected. figure 16-13. timing for accep ting communication reservations scl0 sda0 std0 spd0 standby mode
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 501 the communication reservation flowchart is illustrated below. figure 16-14. communication reservation flowchart di stt0 = 1 define communication reservation wait cancel communication reservation no yes iic0 h ei msts0 = 0? (communication reservation) note (generate start condition) ; sets stt0 flag (communication reservation). ; gets wait period set by software (refer to table 16-6 ). ; confirmation of communication reservation ; clear user flag. ; iic0 write operation ; defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation oper ation executes a write to the iic0 register when a stop condition interrupt request occurs.
chapter 16 i 2 c bus 502 user?s manual u17705ej2v0ud 16.13.2 when communication reservation func tion is disabled (iicf0.iicrsv0 bit = 1) when the iicc0.stt0 bit is set when the bus is not us ed in a communication during bus communication, this request is rejected and a start condition is not generated. the followi ng two statuses are incl uded in the status where bus is not used. ? when arbitration results in nei ther master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iicc0.lrel0 bit was set to 1) to confirm whether the start conditi on was generated or request was rejected, check the iicf0.stcf0 flag. the time shown in table 16-7 is required until the stcf0 flag is set after setting the s tt0 bit = 1. therefore, secure the time by software. table 16-7. wait periods cl01 cl00 selected clock wait period 0 0 f xx /2 10 clocks 0 1 f xx /2 10 clocks 1 0 f xx 5 clocks 1 1 f xx /3 15 clocks
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 503 16.14 cautions (1) when iicf0.stcen0 bit = 0 immediately after i 2 c0 operation is enabled, the bus communica tion status (iicf0.iicbsy0 bit = 1) is recognized regardless of the actual bus status. to execute master comm unication in the status where a stop condition has not been detect ed, generate a stop condition and then releas e the bus before st arting the master communication. use the following sequence for generating a stop condition. <1> set the iiccl0 register. <2> set the iicc0.iice0 bit. <3> set the iicc0.spt0 bit. (2) when iicf0.stcen0 bit = 1 immediately after i 2 c0 operation is enabled, the bus released status (iicbsy0 bit = 0) is recognized regardless of the actual bus status. to generate the first start condition (iicc0.stt0 bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) when the iicc0.iice0 bit of the v850es/ke2 is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. be sure to set the iicc0.iice0 bit to 1 when the scl0 and sda0 lines are high level. (4) determine the operation clock frequency by the ii ccl0 and iicx0 registers bef ore enabling the operation (iicc0.iice0 bit = 1). to change the operation clo ck frequency, clear the iicc0.iice0 bit to 0 once. (5) after the iicc0.stt0 and iicc0.spt0 bits have been set to 1, they must not be re -set without being cleared to 0 first. (6) if transmission has been reserved, set the iicc0.spie0 bi t to 1 so that an interrupt request is generated by the detection of a stop condition. after an interrupt r equest has been generated, the wait state will be released by writing communication data to i 2 c0, then transferring will begin. if an inte rrupt is not generat ed by the detection of a stop condition, transmission will hal t in the wait state because an in terrupt request was not generated. however, it is not necessary to set the spie0 bit to 1 for the software to detect the iics0.msts0 bit.
chapter 16 i 2 c bus 504 user?s manual u17705ej2v0ud 16.15 communication operations the following shows three operati on procedures with the flowchart. (1) master operation in single master system the flowchart when using the v850es/ke2 as the ma ster in a single master system is shown below. this flowchart is broadly divided into the initial setti ngs and communication processi ng. execute the initial settings at startup. if communica tion with the slave is required, pr epare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 c0 bus multimaster system, whether the bus is released or used cannot be judged by the i 2 c bus specifications when the bus takes part in a communicati on. here, when data and clock are at a high level for a certain period (1 frame), the v850es/ke2 takes par t in a communication with bus released state. this flowchart is broadly divided into the initial setti ngs, communication waiting, and communication processing. the processing when the v850es/ke2 loos es in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. execute the initial setti ngs at startup to take part in a communication. then, wait for the co mmunication request as the master or wait for the spec ification as the slave. the actual communication is performed in the communication proce ssing, and it supports the transmission/reception with the slave and the arbitration wit h other masters. (3) slave operation an example of when the v850es/ke2 is used as the slave of the i 2 c0 bus is shown below. when used as the slave, operation is st arted by an interrupt. execute the in itial settings at st artup, then wait for the intiic0 interrupt occurrence (communication waiting). when the intiic0 interrupt occurs, the communication status is judged and its result is pa ssed as a flag over to the main processing. by checking the flags, necessary communication processing is performed.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 505 16.15.1 master operation in single master system figure 16-15. master operati on in single master system iicx0 0xh iiccl0 xxh iicf0 0xh set stcen0, iicrsv0 = 0 iicc0 xxh acke0 = wtim0 = spie0 = 1 iice0 = 1 set ports initialize i 2 c bus note spt0 = 1 sva0 xxh write iic0 write iic0 spt0 = 1 wrel0 = 1 start end read iic0 acke0 = 0 wtim0 = wrel0 = 1 no no yes no no no yes yes yes yes stcen0 = 1? acke0 = 1 wtim0 = 0 intiic0 interrupt occurred? transfer completed? transfer completed? restarted? trc0 = 1? ackd0 = 1? ackd0 = 1? refer to table 4-12 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting communication start preparation (start condition generation) communication start (address, transfer direction specification) waiting for ack detection waiting for data transmission transmission start communication processing initial settings reception start waiting for data reception no yes intiic0 interrupt occurred? waiting for ack detection communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiic0 interrupt occurred? yes no intiic0 interrupt occurred? yes no yes no yes no intiic0 interrupt occurred? stt0 = 1 note release the i 2 c0 bus (scl0, sda0 pins = high level) in c onformity with the specif ications of the product in communication. for example, when the eeprom tm outputs a low level to the sda0 pi n, set the scl0 pin to the output port and output clock pulses from t hat output port until when the sda0 pin is constantly high level. remark for the transmission and reception formats, confo rm to the specifications of the product in communication.
chapter 16 i 2 c bus 506 user?s manual u17705ej2v0ud 16.15.2 master operation in multimaster system figure 16-16. master operation in multimaster system (1/3) iicx0 0xh iiccl0 xxh iicf0 0xh set stcen0, iicrsv0 = 0 iicc0 xxh acke0 = wtim0 = spie0 = 1 iice0 = 1 set ports spt0 = 1 sva0 xxh spie0 = 1 start slave operation slave operation bus release status for a certain period confirmation of bus status is in progress yes confirm bus status note master operation started? communication reservation enable communication reservation disable spd0 = 1? stcen0 = 1? iicrsv0 = 0? a refer to table 4-12 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting (communication start request issued) (no communication start request) ? waiting for slave specification from another master ? waiting for communication start request (depending on user program) communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiic0 interrupt occurred? intiic0 interrupt occurred? yes no yes no spd0 = 1? yes no slave operation no intiic0 interrupt occurred? yes no 1 b spie0 = 0 yes no waiting for communication request waiting for communication initial settings note confirm that the bus release status (iiccl0.cld0 bit = 1, iiccl0.dad0 bit = 1) has been maintained for a certain period (1 frame, for example). when the sda0 pin is constantly low le vel, determine whether to release the i 2 c0 bus (scl0, sda0 pins = high level) by re ferring to the specificat ions of the product in communication.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 507 figure 16-16. master operation in multimaster system (2/3) stt0 = 1 wait slave operation yes msts0 = 1? exc0 = 1 or coi0 =1? communication start preparation (start condition generation) securing wait time by software (refer to table 16-6 ) waiting for bus release (communication reserved) wait status after stop condition detection and start condition generation by communication reservation function no intiic0 interrupt occurred? yes yes no no a c stt0 = 1 wait slave operation yes iicbsy0 = 0? exc0 = 1 or coi0 =1? communication start preparation (start condition generation) communication reservation disabled communication reservation enabled securing wait time by software (refer to table 16-7 ) waiting for bus release stop condition detection no no intiic0 interrupt occurred? yes yes no yes stcf0 = 0? no b d c d communication processing communication processing
chapter 16 i 2 c bus 508 user?s manual u17705ej2v0ud figure 16-16. master operation in multimaster system (3/3) write iic0 wtim0 = 1 wrel0 = 1 read iic0 acke0 = 1 wtim0 = 0 wtim0 = wrel0 = 1 acke0 = 0 write iic0 yes trc0 = 1? restarted? msts0 = 1? communication start (address, transfer direction specification) transmission start no yes waiting for data transmission reception start yes no intiic0 interrupt occurred? yes no transfer completed? waiting for ack detection yes no intiic0 interrupt occurred? waiting for data transmission not in communication yes no intiic0 interrupt occurred? no yes ackd0 = 1? no yes no c 2 yes msts0 = 1? no yes transfer completed? no yes ackd0 = 1? no 2 yes msts0 = 1? no 2 waiting for ack detection yes no intiic0 interrupt occurred? yes msts0 = 1? no c 2 yes exc0 = 1 or coi0 = 1? no 1 2 spt0 = 1 stt0 = 1 slave operation end communication processing communication processing remarks 1. conform the transmission and reception formats to the specifications of the product in communication. 2. when using the v850es/ke2 as the master in the multimaste r system, read the iics0.msts0 bit for each intiic0 interrupt occurrenc e to confirm the arbitration result. 3. when using the v850es/ke2 as t he slave in the multimaster syst em, confirm the status using the iics0 and iicf0 registers for each intiic 0 interrupt occurrence to determine the next processing.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 509 16.15.3 slave operation the following shows the processing procedure of the slave operation. basically, the operation of the slave device is event-driven. therefore, processing by an intiic0 interrupt (processing requiring a significant change of the operat ion status, such as st op condition detection during communication) is necessary. the following description assumes that data communication does not support extension codes. also, it is assumed that the intiic0 interrupt servicing performs only status change processing and t hat the actual data communication is performed during the main processing. figure 16-17. software out line during slave operation i 2 c intiic0 setting, etc. setting, etc. flag data main processing interrupt servicing therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main pr ocessing instead of the intiic0 signal. (1) communication mode flag this flag indicates the following communication statuses. clear mode: data communication not in progress communication mode: data communication in progre ss (valid address detection stop condition detection, ack from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. th is is the same status as an intiic0 interrupt during normal data transfer. this flag is set in the interr upt processing block and cleared in the main processing block. the ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without clearance processing (the address match is regarded as a request for the next data). (3) communication direction flag this flag indicates the direction of communication and is the same as the value of the iics0.trc0 bit. the following shows the operati on of the main processing bl ock during slave operation. start i 2 c0 and wait for the communication enabled status. when communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). for transmission, repeat the transmission operation until the master device stops returning ack. when the master device stops returning ack, transfer is complete.
chapter 16 i 2 c bus 510 user?s manual u17705ej2v0ud for reception, receive the required number of data and do not return ack for the next data immediately after transfer is complete. after that, the master device generates the stop condition or restart c ondition. this causes exit from communications. figure 16-18. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 1? read iic0 clear ready flag clear ready flag communication direction flag = 1? wrel0 = 1 ackd0 = 1? clear communication mode flag wrel0 = 1 write iic0 iicc0 xxh acke0 = wtim0 = 1 spie0 = 0, iice0 = 1 sva0 xxh local address setting iicx0 0xh iiccl0 xxh set ports transfer clock selection iicf0 0xh set iicrsv0 start condition setting transmission start reception start no yes no communication mode flag = 1? yes no ready flag = 1? refer to table 4-12 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. start initial settings communication processing
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 511 the following shows an example of the pr ocessing of the slave device by an int iic0 interrupt (it is assumed that no extension codes are used here). during an intiic0 interr upt, the status is confirm ed and the following steps are executed. <1> when a stop condition is detect ed, communication is terminated. <2> when a start condition is detected, the address is confirmed. if the address does not match, communication is terminated. if the address matches, the communica tion mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, w hen the ready flag is set, operation retu rns from the interrupt while the i 2 c0 bus remains in the wait status. remark <1> to <3> in the above correspond to <1> to <3> in figure 16-19 slave operation flowchart (2) . figure 16-19. slave operation flowchart (2) yes yes yes no no no intiic0 occurred set ready flag interrupt servicing completed spd0 = 1? std0 = 1? coi0 = 1? clear communication direction flag, ready flag, and communication mode flag <1> <2> <3> communication direction flag trc0 set communication mode flag clear ready flag
chapter 16 i 2 c bus 512 user?s manual u17705ej2v0ud 16.16 timing of data communication when using i 2 c bus mode, the master dev ice generates an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the ma ster device transmits the iics0.trc0 bit that specifies the data transfer direction and then starts serial co mmunication with the slave device. the iic0 register?s shift operation is synchronized with the falling edge of the se rial clock (scl0 pin). the transmit data is transferred to the so latch and is output (msb first) via the sda0 pin. data input via the sda0 pin is captured by the iic0 register at the ri sing edge of the scl0 pin. the data communication timing is shown below.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 513 figure 16-20. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iic0 address iic0 data iic0 ffh transmit start condition receive (when exc0 = 1) note note note to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 16 i 2 c bus 514 user?s manual u17705ej2v0ud figure 16-20. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iic0 ackd0 std0 spd0 wtim0 h h l l l l l l h h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic0 data iic0 ffh note iic0 ffh note iic0 data transmit receive note note ack ack note to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 515 figure 16-20. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic0 data iic0 address iic0 ffh note iic0 ffh note stop condition start condition transmit note note (when spie0 = 1) receive (when spie0 = 1) ack note to cancel slave wait, write ffh to iic0 or set wrel0.
chapter 16 i 2 c bus 516 user?s manual u17705ej2v0ud figure 16-21. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (1/3) (a) start condition ~ address iic0 ackd0 std0 spd0 wtim0 h h l l l h l acke0 msts0 stt0 l l spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iic0 address iic0 ffh note note iic0 data start condition ack note to cancel master wait, writ e ffh to iic0 or set wrel0.
chapter 16 i 2 c bus user?s manual u17705ej2v0ud 517 figure 16-21. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (2/3) (b) data iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l l h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic0 data iic0 data iic0 ffh note iic0 ffh note note to cancel master wait, writ e ffh to iic0 or set wrel0.
chapter 16 i 2 c bus 518 user?s manual u17705ej2v0ud figure 16-21. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (3/3) (c) stop condition iic0 ackd0 std0 spd0 wtim0 h h l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 iic0 address iic0 ffh note note iic0 data stop condition start condition (when spie0 = 1) nack (when spie0 = 1) note to cancel master wait, writ e ffh to iic0 or set wrel0.
user?s manual u17705ej2v0ud 519 chapter 17 interrupt/except ion processing function 17.1 overview the v850es/ke2 is provided with a dedica ted interrupt controller (intc) fo r interrupt servicing and realize an interrupt function that can service interrupt requests from a total of 35 sources. an interrupt is an event that occurs independently of program execution, and an ex ception is an event whose occurrence is dependent on program execution. the v850es/ke2 can process interrupt requests from t he on-chip peripheral hardware and external sources. moreover, exception processing can be star ted by the trap instruction (software exception) or by generation of an exception event (fetching of an illegal opcode) (exception trap). 17.1.1 features interrupt source v850es/ke2 external 1 channel (nmi pin) non-maskable interrupt internal 2 channels (wdt1, wdt2) external 8 channels (all edge detection interrupts) wdt1 1 channel tmp 3 channels tm0 2 channels tmh 2 channels tm5 2 channels wt 2 channels brg 1 channel uart 6 channels csi0 2 channels iic 1 channel kr 1 channel ad 1 channel interrupt function maskable interrupt internal total 24 channels 16 channels (trap00h to trap0fh) software exception 16 channels (trap10h to trap1fh) exception function exception trap 2 channels (ilgop/dbg0) table 17-1 lists the interrupt/exception sources.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 520 table 17-1. interrupt source list (1/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register reset pin input pin reset interrupt ? reset internal reset input from wdt1, wdt2 wdt1 wdt2 0000h 00000000h u ndefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? ? intwdt1 wdt1 overflow (when non- maskable interrupt selected) wdt1 0020h 00000020h note 1 ? non- maskable interrupt ? intwdt2 wdt2 overflow (when non- maskable interrupt selected) wdt2 0030h 00000030h note 1 ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal opcode/dbtrap instruction ? 0060h 00000060h nextpc ? 0 intwdtm1 wdt1 overflow (when interval timer selected) wdt1 0080h 00000080h nextpc wdt1ic 1 intp0 intp0 pin valid edge input pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin valid edge input pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin valid edge input pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin valid edge input pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin valid edge input pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin valid edge input pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin valid edge input pin 00f0h 000000f0h nextpc pic6 10 inttm010 tm01 and cr010 match tm01 0120h 00000120h nextpc tm0ic10 11 inttm011 tm01 and cr011 match tm01 0130h 00000130h nextpc tm0ic11 12 inttm50 tm50 and cr50 match tm50 0140h 00000140h nextpc tm5ic0 13 inttm51 tm51 and cr51 match tm51 0150h 00000150h nextpc tm5ic1 14 intcsi00 csi00 transfer completion csi00 0160h 00000160h nextpc csi0ic0 15 intcsi01 csi01 transfer completion csi01 0170h 00000170h nextpc csi0ic1 16 intsre0 uart0 reception error occurrence uart0 0180h 00000180h nextpc sreic0 17 intsr0 uart0 reception completion uart0 0190h 00000190h nextpc sric0 18 intst0 uart0 transmission completion uart0 01a0h 000001ah nextpc stic0 19 intsre1 uart1 reception error occurrence uart1 01b0h 000001b0h nextpc sreic1 20 intsr1 uart1 reception completion uart1 01c0h 000001c0h nextpc sric1 maskable interrupt 21 intst1 uart1 transmission completion uart1 01d0h 000001d0h nextpc stic1 notes 1. for restoration in the case of intwdt1 and intwdt2, refer to 17.10 cautions . 2. n = 0 to fh
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 521 table 17-1. interrupt source list (2/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register 22 inttmh0 tmh0 and cmp00/cmp01 match tmh0 01e0h 000001e0h nextpc tmhic0 23 inttmh1 tmh1 and cmp10/cmp11 match tmh1 01f0h 000001f0h nextpc tmhic1 25 intiic0 i 2 c0 transfer completion i 2 c0 0210h 00000210h nextpc iicic0 26 intad a/d conversion completion a/d 0220h 00000220h nextpc adic 27 intkr key return interrupt kr 0230h 00000230h nextpc kric 28 intwti watch timer interval wt 0240h 00000240h nextpc wtiic 29 intwt watch timer reference time wt 0250h 00000250h nextpc wtic 30 intbrg 8-bit counter of prescaler 3 and prscm match prescaler 3 0260h 00000260h nextpc brgic 45 intp7 intp7 pin valid edge input pin 0390h 00000390h nextpc pic7 46 inttp0ov tmp0 overflow tmp 03a0h 000003a0h nextpc tp0ovic 47 inttp0cc0 tmp0 capture 0/ compare 0 match tmp 03b0h 000003b0h nextpc tp0ccic0 maskable interrupt 48 inttp0cc1 tmp0 capture 1/ compare 1 match tmp 03c0h 000003c0h nextpc tp0ccic1 remarks 1. default priority: the priority order when two or more maskable interrupt requests with the same priority level are generated at the sa me time. the highest priority is 0. the priority of non-maskable interrupt request is as follows. intwdt2 > intwdt1 > nmi restored pc: the value of the program counter (pc) saved to eipc, fepc, or dbpc when interrupt/exception processing is started. the restored pc when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextpc (when an interrupt is acknowledged during the execution of an instruction, the execution of that in struction is stopped and is resumed following completion of interrupt servicing). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? divide instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only w hen an interrupt occurs before stack pointer update) nextpc: the pc value at which processing is st arted following interrupt/exception processing. 2. the execution address of the illegal opcode when an illegal opcode exception occurs is calculated with (restored pc ? 4).
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 522 17.2 non-maskable interrupts non-maskable interrupt request signals are acknowledged unconditionally, even when interrupts are disabled (di state). non-maskable interrupts (nmi) are not subject to pr iority control and take precedence over all other interrupt request signals. the following three types of non-maskable interrupt request signals are available in the v850es/ke2. ? nmi pin input (nmi) ? non-maskable interrupt request signal (intwdt1) due to overflow of watchdog timer 1 ? non-maskable interrupt request signal (intwdt2) due to overflow of watchdog timer 2 there are four choices for the valid edge of an nmi pin, namely: rising edge, falling edge, both edges, and no edge detection. the non-maskable interrupt request signal (intwdt1) due to overflow of watchdog timer 1 functions by setting the wdtm1.wdtm14 and wdtm1.wdtm13 bits to 10. the non-maskable interrupt request signal (intwdt2) due to overflow of watchdog timer 2 functions by setting the wdtm2.wdm21 and wdtm2.wdm20 bits to 01. when two or more non-maskable interrupts occur simultane ously, they are processed in a sequence determined by the following priority order (the interrupt requ est signals with low priority level are ignored). intwdt2 > intwdt1 > nmi if during nmi processing, an nmi, intwdt1, or intwdt2 r equest signal newly occurs, processing is performed as follows. (1) if an nmi request signal newly occurs during nmi processing the new nmi request signal is held pending regard less of the value of the psw.np bit. the nmi request signal held pending is acknowledged upon completi on of processing of the nm i currently being executed (following reti instruction execution). (2) if an intwdt1 request signal newly occurs during nmi processing if the np bit remains set (to 1) during nmi processing, the new intwdt1 request signal is held pending. the intwdt1 request signal held pending is acknowledged upon completion of processing of the nmi currently being executed (following re ti instruction execution). if the np bit is cleared (to 0) during nmi processing, a newly generated intwdt1 request signal is executed (nmi processing is interrupted). (3) if an intwdt2 request signal newly occurs during nmi processing a newly generated intwdt2 request signal is executed re gardless of the value of the np bit (nmi processing is interrupted). caution for non-maskable interrupt servicing from non-maskable interrupt re quest signals (intwdt1, intwdt2), refer to 17.10 cautions.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 523 figure 17-1. acknowledging non-maskab le interrupt request signals (1/2) (a) if two or more nmi request si gnals are simultan eously generated main routine system reset nmi, intwdt2 request (simultaneously generated) intwdt2 processing nmi and intwdt2 requests simultaneously generated main routine system reset nmi, intwdt1 request (simultaneously generated) intwdt1 processing nmi and intwdt1 requests simultaneously generated main routine system reset nmi, intwdt1, intwdt2 requests (simultaneously generated) intwdt2 processing nmi, intwdt1, and intwdt2 requests simultaneously generated main routine system reset intwdt1, intwdt2 request (simultaneously generated) intwdt2 processing intwdt1 and intwdt2 requests simultaneously generated
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 524 figure 17-1. acknowledging non-maskab le interrupt request signals (2/2) (b) if a new non-maskable interr upt request signal is generated during a non-maskable interrupt servicing non-maskable interrupt currently being serviced non-maskable interrupt request newly generated during non-maskable interrupt servicing nmi intwdt1 intwdt2 nmi generation of nmi request during nmi processing generation of intwdt1 request during nmi processing (np = 1 state prior to intwdt1 request is maintained) generation of intwdt1 request during nmi processing (set np = 0 before intwdt1 request) generation of intwdt1 request during nmi processing (set np = 0 after intwdt1 request) generation of intwdt2 request during nmi processing main routine nmi request nmi processing (held pending) nmi processing nmi request (hold pending) main routine system reset nmi request nmi request nmi processing intwdt1 processing (hold pending) main routine system reset nmi request nmi request nmi processing intwdt1 processing intwdt1 request np = 0 np = 0 main routine system reset intwdt2 request nmi processing intwdt2 processing generation of intwdt2 request during intwdt1 processing main routine system reset intwdt1 request intwdt1 processing intwdt2 processing intwdt2 request main routine system reset nmi processing intwdt1 processing intwdt1 (hold pending) request intwdt1 (invalid) request generation of intwdt1 request during intwdt1 processing main routine system reset intwdt1 processing generation of nmi request during intwdt1 processing intwdt1 intwdt2 main routine system reset intwdt1 request intwdt1 request intwdt1 processing nmi request (invalid) nmi request (invalid) generation of intwdt2 request during intwdt2 processing generation of intwdt1 request during intwdt2 processing main routine system reset intwdt2 processing main routine system reset intwdt2 processing generation of nmi request during intwdt2 processing main routine system reset intwdt2 request intwdt2 request intwdt2 processing intwdt1 (invalid) request intwdt2 (invalid) request intwdt1 request intwdt2 request
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 525 17.2.1 operation upon generation of a non-maskable interrupt request si gnal, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes the exception code (0010h, 0020h, 0030h ) to the higher halfword (fecc) of ecr. <4> sets the psw.np and psw.id bits to 1 and clears the psw.ep bit to 0. <5> loads the handler address (00000010h, 00000020h, 00000030h) of the non-maskable interrupt to the pc and transfers control. figure 17-2 shows the servicing flow for non-maskable interrupts. figure 17-2. non-maskable interrupt servicing nmi input non-maskable interrupt request interrupt servicing interrupt request held pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 handler address intc acknowledged cpu processing psw. np 1 0
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 526 17.2.2 restore execution is restored from non-maskable inte rrupt servicing by the reti instruction. (1) in case of nmi restore from nmi processing is done with the reti instruction. when the reti instruction is executed , the cpu performs the following processing and transfers control to the address of the restored pc. (i) loads the values of the restored pc and psw from fepc and fepsw , respectively, because the psw.ep bit and the psw.np bit are 0 and 1, respectively. (ii) transfers control back to the load ed address of the restored pc and psw. figure 17-3 shows the processing fl ow of the reti instruction. figure 17-3. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep bit and the np bit are changed by the ldsr instruction dur ing non-maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to clear the ep bit back to 0 and set the np bit back to 1 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. (2) in case of intwdt1, intwdt2 signals for non-maskable interrupt servicing by the non-maskabl e interrupt request signals (intwdt1, intwdt2), refer to 17.10 cautions .
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 527 17.2.3 np flag the np flag is a status flag that indicates that non-maskable in terrupt servicing is in progress. this flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt serving in progress np 0 1 nmi servicing status after reset: 00000020h
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 528 17.3 maskable interrupts maskable interrupt request signals can be masked by in terrupt control registers. the v850es/ke2 has 33 maskable interrupt sources (refer to 17.1.1 features ). if two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. in addition to the default pr iority, eight levels of interrupt priorities can be specified by using the interrupt control registers, allowing programmable priority control. when an interrupt request signal has been acknowledged, the interrupt disabled (di) status is set and the acknowledgment of other maskable inte rrupt request signals is disabled. when the ei instruction is executed in an interrupt servicing routine, the interr upt enabled (ei) status is set, which enables acknowledgment of interrupt request signals having a priority higher than that of the interrupt request signal currently in progress. note that only interrupt request signals with a higher priority have this capability; interrupt request signals with the same priority level cannot be nested. to use multiple interrupts, it is neces sary to save eipc and eipsw to memory or a register befor e executing the ei instruction, and restore eipc and eipsw to the original values by executing the di instruction before the reti instruction. when the wdtm1.wdtm14 bit is cleared to 0, the watchdog timer 1 overflow interrupt functions as a maskable interrupt (intwdtm1). 17.3.1 operation if a maskable interrupt request signal is generated, t he cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to t he lower halfword of ecr (eicc). <4> sets the psw.id bit to 1 and clears the psw.ep bit to 0. <5> loads the corresponding handler addr ess to the pc and transfers control. the maskable interrupt request signal masked by intc and the maskable interrupt request signal that occurs while another interrupt is being serviced (when psw.np bit = 1 or id bit = 1) are held pending internally. when the interrupts are unmasked, or when the np bit = 0 and the id bit = 0 by using the reti and ldsr instructions, a new maskable interrupt servicing is started in accordance with th e priority of the pending maskable interrupt request signal. figure 17-4 shows the servicing flow for maskable interrupts.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 529 figure 17-4. maskable interrupt servicing maskable interrupt request interrupt servicing eipc eipsw ecr. eicc psw. ep psw. id ispr. corresponding- bit note pc intc acknowledged cpu processing interrupt mask released? priority higher than that of interrupt currently being serviced? interrupt request pending psw. np psw. id interrupt request pending no no no no 1 0 1 0 int input yes yes yes yes priority higher than that of other interrupt requests? highest default priority of interrupt requests with the same priority? restored pc psw exception code 0 1 1 handler address note for the ispr register, refer to 17.3.6 in-service prio rity register (ispr) .
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 530 17.3.2 restore execution is restored from maskable interrupt servicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing and transfers control to the address of the restored pc. (1) loads the values of the restored pc and psw fr om eipc and eipsw because the psw.ep bit and the psw.np bit are both 0. (2) transfers control back to the load ed address of the restored pc and psw. figure 17-5 shows the processing fl ow of the reti instruction. figure 17-5. reti instruction processing reti instruction original processing restored pc psw ispr. corresponding -bit note eipc eipsw 0 psw. ep 1 0 1 0 pc psw fepc fepsw psw. np note for the ispr register, refer to 17.3.6 in-service prio rity register (ispr) . caution when the ep bit and the np bit are ch anged by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to clear the ep bit back to 0 and the np bit back to 0 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 531 17.3.3 priorities of maskable interrupts intc provides a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority leve l control: control based on the default pr iority levels, and control based on the programmable priority levels specified by the interrupt priority level specificat ion bit (xxicn.xxprn bit). when two or more interrupts having the same priority level specifi ed by xxprn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request (default priority level) beforehand. for more information, refer to table 17-1 interrupt source list . programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request signal is acknowledged , the psw.id flag is automatically set (1). therefore, when multiple interrupts are to be used, clear (0) the id flag bef orehand (for example, by plac ing the ei instruction into the interrupt service program) to enable interrupts. remark xx: identifying name of eac h peripheral unit (refer to table 17-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 17-2 interrupt control registers (xxicn) )
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 532 figure 17-6. example of interrupt nesting (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b interrupt request b (level 2) servicing of c interrupt request c (level 3) interrupt request d (level 2) servicing of d servicing of e ei interrupt request e (level 2) interrupt request f (level 3) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. caution the values of eipc and eipsw must be saved before executing multiple interrupts. remarks 1. a to u in the figure are the names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates the re lative priority between two interrupt request signals.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 533 figure 17-6. example of interrupt nesting (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after processing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. notes 1. lower default priority 2. higher default priority
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 534 figure 17-7. example of servicing simultan eously generated inte rrupt request signals main routine ei interrupt request a (level 2) interrupt request b (level 1) note 1 interrupt request c (level 1) note 2 servicing of interrupt request b servicing of interrupt request c servicing of interrupt request a interrupt requests b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority. notes 1. higher default priority 2. lower default priority
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 535 17.3.4 interrupt control register (xxlcn) an interrupt control register is assigned to each maska ble interrupt and sets the control conditions for each maskable interrupt request. the interrupt control regist ers can be read or written in 8-bit or 1-bit units. reset sets xxicn to 47h. caution be sure to read the xxicn. xxifn bit while interrupts are disabled (d i). if the xxifn bit is read while interrupts are enabled (e i), an incorrect value may be read if there is a conflict between acknowledgment of the interrupt and reading of the bit. xxifn interrupt request not generated interrupt request generated xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 enables interrupt servicing disables interrupt servicing (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest) specifies level 1 specifies level 2 specifies level 3 specifies level 4 specifies level 5 specifies level 6 specifies level 7 (lowest) xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff168h < > < > note automatically reset by hardware when interrupt request is acknowledged. remark xx: identifying name of eac h peripheral unit (refer to table 17-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 17-2 interrupt control registers (xxicn) ) following tables list the addresses and bits of the interrupt control registers.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 536 table 17-2. interrupt c ontrol registers (xxlcn) bits address register <7> <6> 5 4 3 2 1 0 fffff110h wdt1ic wdt1if wdt1mk 0 0 0 wdt1pr2 wdt1pr1 wdt1pr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff124h tm0ic10 tm0if10 tm0mk10 0 0 0 tm0pr102 tm0pr101 tm0pr100 fffff126h tm0ic11 tm0if11 tm0mk11 0 0 0 tm0pr112 tm0pr111 tm0pr110 fffff128h tm5ic0 tm5if0 tm5mk0 0 0 0 tm5pr02 tm5pr01 tm5pr00 fffff12ah tm5ic1 tm5if1 tm5mk1 0 0 0 tm5pr12 tm5pr11 tm5pr10 fffff12ch csi0ic0 csi0if0 csi0mk0 0 0 0 csi0pr02 csi0pr01 csi0pr00 fffff12eh csi0ic1 csi0if1 csi0mk1 0 0 0 csi0pr12 csi0pr11 csi0pr10 fffff130h sreic0 sreif0 sremk0 0 0 0 srepr02 srepr01 srepr00 fffff132h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff134h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff136h sreic1 sreif1 sremk1 0 0 0 srepr12 srepr11 srepr10 fffff138h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff13ah stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff13ch tmhic0 tmhif0 tmhmk0 0 0 0 tmhpr02 tmhpr01 tmhpr00 fffff13eh tmhic1 tmhif1 tmhmk1 0 0 0 tmhpr12 tmhpr11 tmhpr10 fffff142h iicic0 iicif0 iicmk0 0 0 0 iicpr02 iicpr01 iicpr00 fffff144h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff146h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff148h wtiic wtiif wtimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff14ah wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0 fffff14ch brgic brgif brgmk 0 0 0 brgpr2 brgpr1 brgpr0 fffff172h pic7 pif7 pmk7 0 0 0 ppr72 ppr71 ppr70 fffff174h tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff176h tp0ccic0 tp0ccif0 tp0ccmk0 0 0 0 tp0ccpr02 tp0ccpr01 tp0ccpr00 fffff178h tp0ccic1 tp0ccif1 tp0ccmk1 0 0 0 tp0ccpr12 tp0ccpr11 tp0ccpr10
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 537 17.3.5 interrupt mask registers 0, 1, 3 (imr0, imr1, imr3) these registers set the interrupt mask status for maskable interrupts. the xxmkn bit of the imr0, imr1, and imr3 registers and the xxmkn bit of the xxlcn register are respectively linked. the imrm register can be read or wri tten in 16-bit units (m = 0, 1, 3). when the higher 8 bits of the imrk r egister are treated as the imrkh register and the lower 8 bits of the imrk register as the imrkl register, they can be read or written in 8-bit or 1-bit units (k = 0, 1). caution in the device file, th e xxmkn bit of the xxicn register is de fined as a reserved word. therefore, if bit manipulation is performed using the name xxm kn, the xxicn register, not the imrm register, is rewritten (as a result, the imrm register is also rewritten). csi0mk1 pmk6 imr0 (imr0h note ) (imr0l) csi0mk0 pmk5 tm5mk1 pmk4 tm5mk0 pmk3 tm0mk11 pmk2 tm0mk10 pmk1 1 pmk0 1 wdt1mk after reset: ffffh r/w address: imr0 fffff100h, imr0l fffff100h, imr0h fffff101h after reset: ffffh r/w address: imr1 fffff102h, imr1l fffff102h, imr1h fffff103h 1 tmhmk1 imr1 (imr1h note ) (imr1l) brgmk tmhmk0 wtmk stmk1 wtimk srmk1 krmk sremk1 admk stmk0 iicmk0 srmk0 1 sremk0 xxmkn 0 1 enables interrupt servicing disables interrupt servicing 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 interrupt mask flag setting after reset: ffffh r/w address: imr3, imr3l fffff106h 1 1 imr3 (imr3l) 1 1 1 1 1 tp0ccmk1 1 tp0ccmk0 1 tp0ovmk 1 pmk7 1 1 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 note when reading from or writing to bits 8 to 15 of the imr0 and imr1 registers in 8-bit or 1- bit units, specify these bits as bits 0 to 7 of the imr0h and imr1h registers. caution set bits 9 and 8 of the imr0 register, bits 15 and 8 of the imr1 register, and bits 15 to 5 and 0 of the imr3 regi ster to 1. the operation is not guaranteed if their value is changed. remark xx: identifying name of eac h peripheral unit (refer to table 17-2 interrupt control registers (xxicn) ) n: peripheral unit number (refer to table 17-2 interrupt control registers (xxicn) )
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 538 17.3.6 in-service priority register (ispr) this register holds the priority level of the maskable in terrupt currently being ackno wledged. when the interrupt request signal is acknowledged, the bit of this register corres ponding to the priority level of that interrupt request signal is set (1) and remains set while the interrupt is being serviced. when the reti instruction is executed, t he bit among those that are set (1) in t he ispr register that corresponds to the interrupt request signal having the highest priority is aut omatically cleared (0) by hardw are. however, it is not cleared (0) when execution is returned from non-maskab le interrupt servicing or exception processing. this register is read-only in 8-bit or 1-bit units. reset sets ispr to 00h. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after th e bits of the register have been set to 1 by acknowledging the interrupt may be read. to accura tely read the value of the ispr register before an interrupt is acknowledge d, read the register while inte rrupts are disabled (di status). ispr7 interrupt request with priority n is not acknowledged interrupt request with priority n is being acknowledged isprn 0 1 priority of interrupt currently being acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah < > < > < > < > < > < > < > < > remark n = 0 to 7 (priority level)
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 539 17.3.7 id flag the interrupt disable flag (id) is allocated to the psw and controls the maskable inte rrupt?s operating state, and stores control information regarding enabling/disa bling reception of interrupt request signals. reset sets this flag to 00000020h. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled id 0 1 maskable interrupt servicing specification note after reset: 00000020h note interrupt disable flag (id) function id is set (1) by the di instruction and cleared (0) by the ei instruction. its value is also modified by the reti instruction or ld sr instruction when referencing the psw. non-maskable interrupt request signals and e xceptions are acknowledged regardless of this flag. when a maskable interrupt reques t signal is acknowledged, the id flag is automatically set (1) by hardware. an interrupt request signal generated during t he acknowledgment disabled period (id flag = 1) can be acknowledged when the xxicn.xxifn bit is set (1), and the id flag is cleared (0).
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 540 17.3.8 watchdog timer mode register 1 (wdtm1) this register is a special register that can be written to only in a s pecial sequence. to generate a maskable interrupt (intwdt1), clear the wdtm14 bit to 0. this register can be read or written in 8- bit or 1-bit units (for details, refer to chapter 11 watchdog timer functions ). run1 stop count operation clear counter and start count operation run1 0 1 watchdog timer operation mode selection note 1 wdtm1 0 0 wdtm14 wdtm13 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (generate maskable interrupt intwdtm1 when overflow occurs) watchdog timer mode 1 note 3 (generate non-maskable interrupt intwdt1 when overflow occurs) watchdog timer mode 2 (start wdtres2 reset operation when overflow occurs) wdtm14 0 0 1 1 wdtm13 0 1 0 1 watchdog timer operation mode selection note 2 < > notes 1. once the run1 bit has been set (1), it cannot be cleared (0) by software. therefore, once counting starts, it cannot be stopped except by reset. 2. once the wdtm14 and wdtm13 bits have bee n set (1), they cannot be cleared (0) by software. reset is the only way to clear these bits. 3. for non-maskable interrupt servicing due to a non-maskable interrupt request signal (intwdt1), refer to 17.10 cautions .
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 541 17.4 external interrupt request i nput pins (nmi, intp0 to intp7) 17.4.1 noise elimination (1) noise elimination for nmi pin the nmi pin includes a noise eliminator that operates using analog delay. therefore, a signal input to the nmi pin is not detected as an edge unless it maintains its input level for a cert ain period. the edge is detected only after a certain period has elapsed. the nmi pin is used for releasing the stop mode. in the stop mode, noise elim ination using the system clock is not performed because the internal system clock is stopped. (2) noise elimination for intp0 to intp2 and intp4 to intp7 pins the intp0 to intp2 and intp4 to intp7 pins include a noise eliminator that operat es using analog delay. therefore, a signal input to each pin is not detected as an edge unless it ma intains its input level for a certain period. the edge is detected only after a certain period has elapsed. (3) noise elimination for intp3 pin the intp3 pin has a digital/analog noise eliminat or that can be selected by the nfc.nfen bit. the number of times the digital noise eliminator samp les signals can be selected by the nfc.nfsts bit from three or two. the sampling clock can be selected by the nfc.nfc2 to nfc.nfc0 bits from f xx /64, f xx /128, f xx /256, f xx /512, f xx /1024, and f xt . if the sampling clock is set to f xx /64, f xx /128, f xx /256, f xx /512, or f xx /1024, the sampling clock stops in the idle/stop mode. it c annot therefore be used to release the standby mode. to release the standby mode, select f xt as the sampling clock or select the analog noise eliminator.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 542 (a) digital noise eliminat ion control register (nfc) the nfc register controls elimination of noise on the intp3 pin. if f xt is used as the noise elimination clock, the external interrupt function of the in tp3 pin can be used even in the idle/stop mode. this register can be read or written in 8-bit or 1-bit units. reset sets nfc to 00h. nfen analog noise elimination digital noise elimination nfen 0 1 setting of intp3 pin noise elimination nfc nfsts 0 0 0 nfc2 nfc1 nfc0 number of samplings = 3 times number of samplings = 2 times nfsts 0 1 setting of number of samplings of digital noise elimination after reset: 00h r/w address: fffff318h f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 f xt nfc2 0 0 0 0 1 1 nfc1 0 0 1 1 0 0 nfc0 0 1 0 1 0 1 selection of sampling clock setting prohibited other than above remark f xx : main clock frequency f xt : subclock frequency
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 543 the digital noise elimination width (t wit3 ) is as follows, where t is the sampling clock period and m is the number of samplings. ? t wit3 < (m ? 1)t: accurately eliminated as noise ? (m ? 1)t t wit3 < mt: may be eliminated as noise or detected as valid edge ? t wit3 mt: accurately detected as valid edge to detect the valid edge input to the intp3 pin accura tely, therefore, a pulse wider than mt must be input. minimum elimination noise width nfsts nfc2 nfc1 nfc0 sampling clock f xx = 20 mhz f xx = 10 mhz f xx = 8 mhz 0 0 0 0 f xx /64 6.4 s 12.8 s 16 s 0 0 0 1 f xx /128 12.8 s 25.6 s 32 s 0 0 1 0 f xx /256 25.6 s 51.2 s 64 s 0 0 1 1 f xx /512 51.2 s 102.4 s 128 s 0 1 0 0 f xx /1024 102.4 s 204.8 s 256 s 0 1 0 1 f xt (32.768 khz) 61.04 s 1 0 0 0 f xx /64 3.2 s 6.4 s 8 s 1 0 0 1 f xx /128 6.4 s 12.8 s 16 s 1 0 1 0 f xx /256 12.8 s 25.6 s 32 s 1 0 1 1 f xx /512 25.6 s 51.2 s 64 s 1 1 0 0 f xx /1024 51.2 s 102.4 s 128 s 1 1 0 1 f xt (32.768 khz) 30.52 s other than above setting prohibited 17.4.2 edge detection the valid edges of the nmi and intp0 to intp7 pins can be selected from the following four types for each pin. ? rising edge ? falling edge ? both edges ? no edge detection after reset, the edge detection for the nmi pin is set to ? no edge detection?. therefore, interrupt requests cannot be acknowledged (the nmi pin functions as a normal port) unless a valid edge is specified by the intr0 and intf0 registers. when using the p02 pin as an output port, set the nmi pin valid edge to ?no edge detection?.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 544 (1) external interrupt rising and falling e dge specification registers 0 (intr0, intf0) these are 8-bit registers t hat specify detection of the rising and fa lling edges of the nmi and intp0 to intp3 pins. these registers can be read or wri tten in 8-bit or 1-bit units. reset sets these registers to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf0n and intr0n bits = 00. 0 intr0 intr06 intr05 intr04 intr03 intr02 intp2 intp1 intp0 nmi 00 after reset: 00h r/w address: intr0 fffffc20h, intf0 fffffc00h intp2 intp1 intp0 nmi intp3 intp3 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 remark for specification of the valid edge, refer to table 17-3 . table 17-3. nmi and intp0 to in tp3 pins valid edge specification intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 2: control of nmi pin n = 3 to 6: control of intp0 to intp3 pins
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 545 (2) external interrupt rising and falling e dge specification registers 3 (intr3, intf3) these are 8-bit registers that s pecify detection of the rising and fall ing edges of the intp7 pin. these registers can be read or wri tten in 8-bit or 1-bit units. reset sets these registers to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf31 and intr31 bits = 00. 0 intr3 0 0 0 0 0 intr31 0 after reset: 00h r/w address: intr3 fffffc26h, intf3 fffffc06h intp7 intp7 0 intf3 0 0 0 0 0 intf31 0 remark for specification of the valid edge, refer to table 17-4 . table 17-4. intp7 pin valid edge specification intf31 intr31 valid edge specification 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 546 (3) external interrupt rising and falling edge specification registers 9h (intr9h, intf9h) these are 8-bit registers that s pecify detection of the rising edge of the intp4 to intp6 pins. these registers can be read or wri tten in 8-bit or 1-bit units. reset sets these registers to 00h. caution when switching to the port function from th e external interrupt functi on (alternate function), edge detection may be performe d. therefore, set the port m ode after setting the intf9n and intr9n bits = 00. intr915 intr9h intr914 intr913 0 0 0 0 0 after reset: 00h r/w address: intr9h fffffc33h, intf9h fffffc13h intp5 intp4 intp6 intp5 intp4 intp6 intf915 intf9h intf914 intf913 0 0 0 0 0 remark for specification of the valid edge, refer to table 17-5 . table 17-5. intp4 to intp6 pins valid edge specification intf9n intr9n valid edge specification (n = 13 to 15) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 13 to 15: control of intp4 to intp6 pins
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 547 17.5 software exceptions a software exception is generated when the cpu executes the trap instruction. software exceptions can always be acknowledged. 17.5.1 operation if a software exception occurs, the cpu performs the fo llowing processing and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits to 1. <5> loads the handler address (00000040h or 00000050h) for the software exception routine to the pc and transfers control. figure 17-8 shows the software exception processing flow. figure 17-8. software exception processing trap instruction note eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note trap instruction format: trap vector (however, vector = 00h to 1fh) the handler address is determined by the operand (vector) of the trap instructio n. if the vector is 00h to 1fh, the handler address is 00000040h, and if the vector is 10h to 1fh, the handler address is 00000050h.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 548 17.5.2 restore execution is restored from software exceptio n processing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the restored pc and psw from ei pc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. figure 17-9 shows the processing fl ow of the reti instruction. figure 17-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep bit and the np bit are ch anged by the ldsr instruction during software exception processing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessa ry to set the psw.ep bit back to 1 using the ldsr instruction immediately before th e reti instruction. remark the solid line shows the cpu processing flow.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 549 17.5.3 ep flag the ep flag, which is bit 6 of the psw, is a status flag that indicate s that exception processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress exception processing in progress ep 0 1 exception processing status after reset: 00000020h
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 550 17.6 exception trap the exception trap is an interrupt that is requested when t he illegal execution of an instruction takes place. in the v850es/ke2, an illegal opcode trap (ilgop) is considered as an exception trap. 17.6.1 illegal opcode an illegal opcode is defined as an instruction with instru ction opcode (bits 10 to 5) = 111111b, sub-opcode (bits 26 to 23) = 0111b to 1111b, and sub-opcode (bit 16) = 0b. when such an instruction is ex ecuted, an exception trap is generated. 15 16 23 22 xxxxxx0 x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 x: don?t care caution it is recommended not to use an illegal opcode because instru ctions may newly be assigned in the future. (1) operation upon generation of an exception trap, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits. <4> loads the handler address (00000060h) for the except ion trap routine to the pc and transfers control. figure 17-10 shows the exception trap processing flow.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 551 figure 17-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore execution is restored from exception trap processing by the dbret instruction. when the dbret instruction is executed, the cpu performs the fo llowing processing and transfers cont rol to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. caution dbpc and dbpsw can be accessed only durin g the interval between the execution of an illegal opcode and the dbret instruction. figure 17-11 shows the processing flow for re store from exception trap processing. figure 17-11. processing flow fo r restore from exception trap dbret instruction pc psw dbpc dbpsw jump to restored pc address
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 552 17.6.2 debug trap a debug trap is an exception that occurs upon execution of the dbtrap inst ruction and that can be acknowledged at all times. when a debug trap occurs, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets the handler address (00000060h) for the debug trap routine to the pc and transfers control. figure 17-12 shows the debug trap processing flow. figure 17-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h debug monitor routine processing cpu processing
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 553 (2) restore execution is restored from debug trap pr ocessing by the dbret instruction. when the dbret instruction is executed, the cpu performs the following processing and tr ansfers control to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. caution dbpc and dbpsw can be accessed only duri ng the interval between the execution of the dbtrap instruction and the dbret instruction. figure 17-13 shows the processing flow fo r restore from debug trap processing. figure 17-13. processing flow for restore from debug trap dbret instruction pc psw dbpc dbpsw jump to restored pc address
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 554 17.7 multiple interru pt servicing control multiple interrupt servicing control is a function that st ops an interrupt service routine currently in progress if a higher priority interrupt request signal is generated, and processes the acknowledgm ent operation of the higher priority interrupt request signal. if an interrupt request signal with a lower or equal priority is generated and a service routi ne is currently in progress, the later interrupt request signal will be held pending. multiple interrupt servicing control is performed when inte rrupts are enabled (psw.id bit = 0). even in an interrupt servicing routine, multiple interrupt control must be performed while interrupts are enabled (id bit = 0). if a maskable interrupt or software exception is generated in a maskable interrupt or software exception service program, eipc and eipsw must be saved. the following example illustrates the procedure. (1) to acknowledge maskable interrupt re quest signals in service program service program for maskable interrupt or exception ? ? ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (enables interrupt acknowledgment) ? ? acknowledges maskable interrupt ? ? ? di instruction (disables interrupt acknowledgment) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 555 (2) to generate exception in service program service program for maskable interrupt or exception ? ? ? eipc saved to memory or register ? eipsw saved to memory or register ? ? trap instruction acknowledges exceptions su ch as trap instruction. ? ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction priorities 0 to 7 (0 is the highest) can be set for each maskable interrupt request in multiple interrupt servicing control by software. to set a priority level, wr ite values to the xxicn.xxp rn0 to xxicn.xxprn2 bits corresponding to each maskable interrupt request. after reset, interrupt requests are masked by the xxicn.xxmkn bit, and the priority is set to level 7 by the xxprn0 to xxprn2 bits. priorities of maskable interrupts are as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been suspend ed as a result of multiple interrupt servicing control is resumed after the interrupt servicing of the higher priority has been completed and the reti inst ruction has been executed. a pending interrupt request signal is acknowledged a fter the current interrupt servicing has been completed and the reti instruction has been executed. caution in a non-maskable interrupt servicing rout ine (in the time until the reti instruction is executed), maskable interrupts are not acknowledged and held pending.
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 556 17.8 interrupt response time except in the following cases, the cpu interrupt response ti me is a minimum of 4 clocks. if inputting consecutive interrupt request signals, at least 4 clocks must be placed between each interrupt request signal. ? idle/stop mode ? external bus access ? consecutive interrupt request non- sample instruction (refer to 17.9 periods in which interrupts are not acknowledged by cpu ) ? access to interrupt control register ? access to peripheral i/o register figure 17-14. pipeline operati on during interrupt request si gnal acknowledgment (outline) (1) minimum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem wb ifx idx int1 int2 int3 int4 4 system clocks (2) maximum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem mem mem wb ifx idx int1 int2 int3 int3 int3 int4 6 system clocks remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt response time (internal system clock) internal interrupt external interrupt condition min. 4 4 + analog delay max. 6 6 + analog delay the following cases are excluded. ? idle/stop mode ? external bus access ? consecutive interrupt request non-sample instruction ? access to interrupt control register ? access to peripheral i/o register
chapter 17 interrupt/exception processing function user?s manual u17705ej2v0ud 557 17.9 periods in which interrupts are not acknowledged by cpu interrupts are acknowledged by the cpu while an instru ction is being executed. however, no interrupt is acknowledged between an interrupt request non-sample instru ction and the next instru ction (interrupts are held pending). the following instructions are interrupt request non-sample instructions. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instructions (vs. psw) ? store instruction for the prcmd register ? store instruction and set1, not1, and clr1 instructions for the following registers ? interrupt-related registers: interrupt control register (xxlcn), interrupt mask registers 0, 1, 3 (imr0, imr1, imr3) ? power save control register (psc) 17.10 cautions design the system so that restoring by the reti instructi on is as follows after a non-maskable interrupt triggered by a non-maskable interrupt request signal (intwdt1/intwdt2) is serviced. figure 17-15. restoring by reti instruction generation of intwdt1/intwdt2 intwdt1/intwdt2 servicing routine software reset processing routine fepc software reset processing address fepsw value to set np bit = 1, ep bit = 1 reti ten reti instructions (fepc and fepsw note must be set) psw initial set value of psw initialization processing note fepsw value to set np bit = 1, ep bit = 0
user?s manual u17705ej2v0ud 558 chapter 18 key interrupt function 18.1 function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7) by setting the krm register. caution if any of the kr0 to kr7 pins is at low l evel, the intkr signal is not generated even if a falling edge is input to another pin. table 18-1. assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units figure 18-1. key re turn block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0
chapter 18 key interrupt function user?s manual u17705ej2v0ud 559 18.2 register (1) key return mode register (krm) the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. krm7 does not detect key return signal detects key return signal krmn 0 1 key return mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 after reset: 00h r/w address: fffff300h caution if the krm register is changed, an interrupt request signal (intkr) may be generated. to prevent this, change th e krm register after disabling interrupts (di), and then enable interrupts (ei) a fter clearing the interrupt request flag (kric.krif bit) to 0. remark for the alternate-function pin settings, refer to table 4-12 settings when port pins are used for alternate functions .
user?s manual u17705ej2v0ud 560 chapter 19 standby function 19.1 overview the power consumption of the system can be effectively reduced by using t he standby modes in combination and selecting the appropriate mode for the application. the available standby modes are listed in table 19-1. table 19-1. standby modes mode functional outline halt mode mode to stop only the operating clock of the cpu idle mode mode to stop all the operations of the internal circuits except the oscillator note 1 stop mode mode to stop all the operations of the internal circuits except the subclock oscillator note 2 subclock operation mode mode to use the subclock as the internal system clock sub-idle mode mode to stop all the operations of the internal circuits, except the oscillator, in the subclock operation mode notes 1. the pll does not stop. to realize low power consum ption, stop the pll and then shift to the idle mode. 2. change to the clock-through mode, stop the pll, t hen shift to the stop mode. for details, refer to chapter 5 clock generation function .
chapter 19 standby function user?s manual u17705ej2v0ud 561 figure 19-1. status transition (1/2) normal operation mode (operation with main clock) wait for stabilization of oscillation wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count end of oscillation stabilization time count end of oscillation stabilization time count setting of halt mode interrupt request note 3 setting of stop mode idle mode halt mode stop mode reset note 5 interrupt request note 2 setting of idle mode interrupt request note 4 reset note 1 reset note 5 notes 1. reset by reset pin input, watchdog timer 1 overflow (wdtres1), or watchdog timer 2 overflow (wdtres2). 2. non-maskable interrupt request signal (nmi, intw dt1, intwdt2) or unmasked maskable interrupt request signal. 3. non-maskable interrupt request signal (nmi pin input, intwdt2 (when the cpu is operating on the subclock)), unmasked external interrupt request si gnal (intp0 to intp7 pin input), or unmasked internal interrupt request signal from peripheral functions operable in idle mode. 4. non-maskable interrupt request signal (nmi pin input, intwdt2 (when the cpu is operating on the subclock)), unmasked external interrupt request si gnal (intp0 to intp7 pin input), or unmasked internal interrupt request signal from peripheral functions operable in stop mode. 5. reset by reset pin input or watchdog timer 2 (when the cpu is operating on the subclock) overflow (wdtres2).
chapter 19 standby function user?s manual u17705ej2v0ud 562 figure 19-1. status transition (2/2) normal operation mode (operation with main clock) subclock operation mode (operation with subclock) wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count setting of subclock operation mode setting of normal operation mode end of oscillation stabilization time count sub-idle mode reset note 1 interrupt request note 2 setting of idle mode reset note 1 notes 1. reset by reset pin input or watchdog timer 2 overflow (wdtres2). 2. non-maskable interrupt request signal (nmi pin input, intwdt2 (when the cpu is operating on the subclock)), unmasked external interrupt request si gnal (intp0 to intp7 pin input), or unmasked internal interrupt request signal from peripheral functions operable in sub-idle mode.
chapter 19 standby function user?s manual u17705ej2v0ud 563 19.2 registers (1) power save control register (psc) this is an 8-bit register that controls the standby function. the stp bit of this register is used to specify the standby mode. the psc register is a special register that can be written to only in a special sequence (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets psc to 00h. nmi2m psc 0 nmi0m intm 0 0 stp 0 releasing standby mode note by intwdt2 signal enabled releasing standby mode note by intwdt2 signal disabled nmi2m 0 1 control of releasing standby mode note by intwdt2 signal releasing standby mode note by nmi pin input enabled releasing standby mode note by nmi pin input disabled nmi0m 0 1 control of releasing standby mode note by nmi pin input releasing standby mode note by maskable interrupt request signals enabled releasing standby mode note by maskable interrupt request signals disabled intm 0 1 control of releasing standby mode note by maskable interrupt request signals normal mode standby mode note stp 0 1 standby mode note setting after reset: 00h r/w address: fffff1feh < > < > < > < > note in this case, standby mode means the idle/s top mode; it does not in clude the halt mode. cautions 1. if the nmi2m, nmi0m, or intm bit is set to 1 at the same time the stp bit is set to 1, the setting of nmi2m, nmi0m, or intm bit becom es invalid. if there is an unmasked interrupt request signal being held pending when th e idle/stop mode is set, set the bit corresponding to the interrupt request signal (n mi2m, nmi0m, or intm) to 1, and then set the stp bit to 1. 2. when the idle/stop mode is set, set the psmr.psm bit and then set the stp bit.
chapter 19 standby function user?s manual u17705ej2v0ud 564 (2) power save mode register (psmr) this is an 8-bit register that cont rols the operation status in the st andby mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. reset sets psmr to 00h. xtstp subclock oscillator used subclock oscillator not used xtstp 0 1 specification of subclock oscillator use psmr 0 0 0 0 0 0 psm idle mode stop mode psm 0 1 specification of operation in standby mode after reset: 00h r/w after reset: fffff820h < > cautions 1. be sure to clear the xtstp bi t to 0 during subclock resonator connection. 2. be sure to clear bits 1 to 6 of the psmr register to 0. 3. the psm bit is valid only when the psc.stp bit is 1.
chapter 19 standby function user?s manual u17705ej2v0ud 565 (3) oscillation stabilization time selection register (osts) the wait time until the oscill ation stabilizes after the stop mode is releas ed is controlled by the osts register. the osts register can be read or written in 8-bit units. reset sets osts to 01h. 0 osts 0 0 0 0 osts2 osts1 osts0 2 13 /f x 2 15 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 19 /f x 2 20 /f x 2 21 /f x osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 5 mhz 10 mhz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 4 mhz 2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms f x after reset: 01h r/w address: fffff6c0h cautions 1. the wait time following release of the stop mode does not include the time until the clock oscillation starts (?a? in the figure below) following release of the stop mode, regardless of whether the stop mode is released by re set or the occurrence of an interrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to clear bits 3 to 7 to ?0?. 3. the oscillation stabilization ti me following reset release is 2 15 /f x (because the initial value of the osts register = 01h). 4. the oscillation stabilization time is also inserted during external clock input. remark f x : main clock oscillation frequency
chapter 19 standby function user?s manual u17705ej2v0ud 566 19.3 halt mode 19.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock oscillator continues operating. only clock s upply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the inte rnal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 19-3 shows the operation status in the halt mode. the average power consumption of the system can be reduc ed by using the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed with an unmasked interrupt request signal held pending, the system shift to the halt mode, but the ha lt mode is immediately released by the pending interrupt request signal. 19.3.2 releasing halt mode the halt mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt1, intwdt2 signal), an unmasked maskable interrupt request signal, and reset signal (reset pin input, wdtres1, wdtres2 signal). after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interr upt request signal or an unmasked maskable interrupt request signal, regardless of the prio rity of the interrupt request. if the halt mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the halt mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request with a priority higher than that of the interrupt request signal currently being serviced is issued (including a non-maskable interrupt request signal), the halt mode is released and that interrupt request signal is acknowledged. table 19-2. operation after releasing halt mode by interr upt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing halt mode by reset the same operation as the normal reset operation is performed.
chapter 19 standby function user?s manual u17705ej2v0ud 567 table 19-3. operation status in halt mode when cpu is operating with main clock setting of halt mode item when subclock is not used when subclock is used cpu stops operation main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled interrupt controller operable timer p (tmp0) operable 16-bit timer (tm01) operable 8-bit timers (tm50, tm51) operable timer h (tmh0, tmh1) operable watch timer operable when main clock output is selected as count clock operable watchdog timer 1 operable watchdog timer 2 operable when main clock is selected as count clock operable csi00, csi01 operable i 2 c0 operable serial interface uart0, uart1 operable key interrupt function operable a/d converter operable real-time output operable port function retains status before halt mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set.
chapter 19 standby function user?s manual u17705ej2v0ud 568 19.4 idle mode 19.4.1 setting and operation status the idle mode is set by clearing the psmr.psm bit to 0 and setting the psc.stp bit to 1 in the normal operation mode. in the idle mode, the clock oscillator continues operati on but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle mode was set are retained. the cpu and other on-chip peripheral functions st op operating. however, the on -chip peripheral functions that can operate with the subclock or an external clock continue operating. table 19-5 shows the operation status in the idle mode. the idle mode can reduce the power consumption more than the halt m ode because it stops the operation of the on-chip peripheral functions. the main clock oscill ator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization ti me after the idle mode has been released, in the same manner as when the halt mode is released. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the idle mode.
chapter 19 standby function user?s manual u17705ej2v0ud 569 19.4.2 releasing idle mode the idle mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal (when the cpu is operating on the subclock)), unmasked external inte rrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral function s operable in the idle mode, or reset (reset pin input, wdtres2 signal (when the cpu is operating on the subclock)). after the idle mode has been released, th e normal operation mode is restored. (1) releasing idle mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the idle mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interr upt request. if the idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the idle mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the idle mode is released and that interrupt request signal is acknowledged. table 19-4. operation after releasing id le mode by interr upt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed caution the interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (interrupt disabled) become s invalid and the idle mode is not released. (2) releasing idle mode by reset the same operation as the normal reset operation is performed.
chapter 19 standby function user?s manual u17705ej2v0ud 570 table 19-5. operation status in idle mode when cpu is operating with main clock setting of idle mode item when subclock is not used when subclock is used cpu stops operation main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled interrupt controller stops operation timer p (tmp0) stops operation 16-bit timer (tm01) operable when intwt is selected as count clock and f brg is selected as count clock of wt operable when intwt is selected as count clock 8-bit timers (tm50, tm51) ? operable when ti5m is selected as count clock ? operable when inttm010 is selected as count clock and tm01 is enabled in idle mode timer h (tmh0) stops operation timer h (tmh1) stops operation operable when f xt is selected as count clock watch timer operable when main clock is selected as count clock operable watchdog timer 1 stops operation watchdog timer 2 stops operation operable when f xt is selected as count clock csi00, csi01 operable when sck0m input clock is selected as operation clock i 2 c0 stops operation uart0 operable when asck0 is selected as count clock serial interface uart1 stops operation key interrupt function operable a/d converter stops operation note regulator operation continues real-time output operable when inttm5m is selected as real-t ime output trigger and tm5m is enabled in idle mode. however, the rtbh0 and rtbl0 registers cannot be updated because the cpu is stopped. port function retains status before idle mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle mode was set. note set the adm.adcs and adm.adcs2 bits to 00b. remark m = 0, 1
chapter 19 standby function user?s manual u17705ej2v0ud 571 19.5 stop mode 19.5.1 setting and operation status the stop mode is set when the psmr.psm bit is set to 1 and the psc.stp bit is set to 1 in the normal operation mode. in the stop mode, the subclock oscillat or continues operating but the main cl ock oscillator stops. clock supply to the cpu and the on-chip peri pheral functions is stopped. as a result, program execution is st opped, and the contents of the inter nal ram before the stop mode was set are retained. the on-chip peripheral f unctions that operate with the clock oscilla ted by the subclock oscillator or an external clock continue operating. table 19-7 shows the operation status in the stop mode. because the stop stops operati on of the main clock oscillator, it reduces the power consumption to a level lower than the idle mode. if the subclock o scillator and external clock are not used, the power consumption can be minimized with only leakage current flowing. caution insert five or more nop instru ctions after the instruction that st ores data in the psc register to set the stop mode.
chapter 19 standby function user?s manual u17705ej2v0ud 572 19.5.2 releasing stop mode the stop mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal (when the cpu is operating on the subclock)), unmasked external inte rrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the stop mode, or reset (reset pin input, wdtres2 signal (when the cpu is operating on the subclock)). after the stop mode has been released, the normal operat ion mode is restored after the oscillation stabilization time has been secured. (1) releasing stop mode by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the stop mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the prio rity of the interrupt request. if the software stop mode is set in an interrupt servicing routine, however, an interrupt r equest that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the stop mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the stop mode is released and that interrupt request signal is acknowledged. table 19-6. operation after releasing st op mode by interrupt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed caution the interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (interrupt disabled) become s invalid and the stop mode is not released. (2) releasing stop mode by reset the same operation as the normal reset operation is performed.
chapter 19 standby function user?s manual u17705ej2v0ud 573 table 19-7. operation status in stop mode when cpu is operating with main clock setting of stop mode item when subclock is not used when subclock is used cpu stops operation main clock oscillator oscillation stops subclock oscillator ? oscillation enabled interrupt controller stops operation timer p (tmp0) stops operation 16-bit timer (tm01) stops operation operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) operable when ti5m is selected as count clock operable when ti5m is selected as count clock or when inttm010 is selected as count clock and tm01 is enabled in stop mode timer h (tmh0) stops operation timer h (tmh1) stops operation operable when f xt is selected as count clock watch timer stops operation operable when f xt is selected as count clock watchdog timer 1 stops operation watchdog timer 2 stops operation operable when f xt is selected as count clock csi00, csi01 operable when sck0m input clock is selected as operation clock i 2 c0 stops operation uart0 operable when asck0 is selected as count clock serial interface uart1 stops operation key interrupt function operable a/d converter stops operation note real-time output operable when inttm5m is selected as real-t ime output trigger and tm5m is enabled in stop mode. however, the rtbh0 and rtbl0 registers cannot be updated because the cpu is stopped. port function retains status before stop mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the stop mode was set. note set the adm.adcs and adm.adcs2 bits to 00b. remark m = 0, 1
chapter 19 standby function user?s manual u17705ej2v0ud 574 19.5.3 securing oscillation stabilization time when stop mode is released when the stop mode is released, only the oscillation stabilization time set by the osts register elapses. if the stop mode has been released by reset, however, the reset value of the osts register, 2 15 /f x (8.192 ms at f x = 4 mhz) elapses. the operation performed when the stop mode is releas ed by an interrupt request signal is shown below. figure 19-2. oscillation stabilization time oscillated waveform main clock oscillator stops oscillation stabilization time count main clock stop mode status interrupt request remark for details of the osts register, refer to 19.2 (3) oscillation stabilization time selection register (osts) .
chapter 19 standby function user?s manual u17705ej2v0ud 575 19.6 subclock operation mode 19.6.1 setting and operation status the subclock operation mode is set when the pcc.ck3 bit is set to 1 in the normal operation mode. when the subclock operation mode is set, t he internal system clock is changed from the main clock to the subclock. when the pcc.mck bit is set to 1, the op eration of the main clock oscillator is stopped. as a result, the system operates only with the subclock. table 19-8 shows the operation stat us in subclock operation mode. in the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. in addition, the power consumption can be further reduced to the level of the stop mode by st opping the operation of t he main clock oscillator. cautions 1. when manipulating the ck3 bit, do no t change the set values of the pcc.ck2 to pcc.ck0 bits (using a bit manipulation instruction to ma nipulate the bit is recommended). for details, refer to 5.3 (1) processor cl ock control register (pcc). 2. if the following conditions are not satisfied, change the ck2 to ck0 bits so that the conditions are satisfied and set the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 remark internal system clock (f clk ): clock generated from the main clock (f xx ) by setting bits ck2 to ck0 19.6.2 releasing subclock operation mode the subclock operation mode is released when the ck3 bit is cleared to 0 or by reset (reset pin input, wdtres1, wdtres2 signal). if the main clock is stopped (mc k bit = 1), set the mck bit to 1, secure the oscillation stabilization time of the main clock by software, and clear the ck3 bit to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for deta ils, refer to 5.3 (1) processor clock control register (pcc).
chapter 19 standby function user?s manual u17705ej2v0ud 576 table 19-8. operation status in subclock operation mode operation status setting of subclock operation item mode when main clock is oscillati ng when main clock is stopped cpu operable subclock oscillator oscillation enabled interrupt controller operable timer p (tmp0) operable stops operation 16-bit timer (tm01) operable operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) operable ? operable when ti5m is selected as count clock ? operable when inttm010 is selected as count clock and when tm01 is enabled in subclock operation mode timer h (tmh0) operable stops operation timer h (tmh1) operable operable when f xt is selected as count clock watch timer operable operable when f xt is selected as count clock watchdog timer 1 stops operation watchdog timer 2 operable operable when f xt is selected as count clock csi00, csi01 operable operable when sck0m input clock is selected as operation clock i 2 c0 operable stops operation uart0 operable operable when asck0 is selected as count clock serial interface uart1 operable stops operation key interrupt function operable a/d converter operable stops operation real-time output operable operable when inttm5m is selected as real-time output trigger and ti5m is selected as count clock of tm5m port function settable internal data settable remark m = 0, 1
chapter 19 standby function user?s manual u17705ej2v0ud 577 19.7 sub-idle mode 19.7.1 setting and operation status the sub-idle mode is set when the psmr.psm bit is cleared to 0 and the psc.stp bit is set to 1 in the subclock operation mode. in this mode, the clock oscillator continues operation bu t clock supply to the cpu and the other on-chip peripheral functions is stopped. as a result, program execution is st opped and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and t he other on-chip peripheral functions are st opped. however, the on-chip peripheral functions that can operate with the subclock or an extern al clock continue operating. table 19-10 shows the operation status in the sub-idle mode. because the sub-idle mode stops oper ation of the cpu and other on-chip per ipheral functions, it can reduce the power consumption more than the subc lock operation mode. if the sub-idle mode is set after the main clock has been stopped, the power consumption can be reduced to a level as lo w as that in the stop mode. caution following the store instruction to the psc re gister for setting the sub-idle mode, insert five or more nop instructions.
chapter 19 standby function user?s manual u17705ej2v0ud 578 19.7.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal (when the cpu is operating on the subclock)), unmasked external interrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peri pheral functions operable in the sub-idle mode, or reset (reset pin input, wdtres2 signal (when t he cpu is operating on the subclock)). when the sub-idle mode is released by an interrupt requ est signal, the subclock operation mode is set. if it is released by reset, the normal operation mode is restored. (1) releasing sub-idle m ode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the sub-idle mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of t he interrupt request. if the sub-idle mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an that of the interrupt r equest currently being serviced is issued, only the sub-idle mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the sub-idle mode is released and that interrupt request signal is acknowledged. table 19-9. operation after releasing sub- idle mode by interrupt request signal release source interrupt enabled (ei) st atus interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed caution the interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (interrupt disabled) beco mes invalid and the sub-idle mode is not released. (2) releasing sub-id le mode by reset the same operation as the normal reset operation is performed.
chapter 19 standby function user?s manual u17705ej2v0ud 579 table 19-10. operation status in sub-idle mode operation status setting of sub-idle item mode when main clock is oscillati ng when main clock is stopped cpu stops operation subclock oscillator oscillation enabled interrupt controller stops operation timer p (tmp0) stops operation 16-bit timer (tm01) operable when intwt is selected as count clock operable when intwt is selected as count clock and f xt is selected as count clock of wt 8-bit timers (tm50, tm51) ? operable when ti5m is selected as count clock ? operable when inttm010 is selected as count clock and when tm01 is enabled in sub-idle mode timer h (tmh0) stops operation timer h (tmh1) operable when f xt is selected as count clock watch timer operable operable when f xt is selected as count clock watchdog timer 1 stops operation watchdog timer 2 operable when f xt is selected as count clock csi00, csi01 operable when sck0m input clock is selected as operation clock i 2 c0 stops operation uart0 operable when asck0 is selected as count clock serial interface uart1 stops operation key interrupt function operable a/d converter stops operation note real-time output operable when inttm5m is selected as real-tim e output trigger and tm5m is set to the operable conditions of the sub-idle mode port function retains status before sub-idle mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the sub-idle mode was set. note set the adm.adcs and adm.adcs2 bits to 00b. remark m = 0, 1
user?s manual u17705ej2v0ud 580 chapter 20 reset function 20.1 overview the following reset functions are available. ? reset function by reset pin input ? reset function by overflow of watchdog timer 1 (wdtres1) ? reset function by overflow of watchdog timer 2 (wdtres2) if the reset pin goes high, the reset stat us is released, and the cpu starts ex ecuting the program. initialize the contents of each register in the program as necessary. the reset pin has a noise e liminator that operat es by analog delay to prevent malfunction caused by noise. 20.2 configuration figure 20-1. reset block diagram reset count clock count clock analog delay circuit reset controller watchdog timer 1 watchdog timer 2 wdtres1 issued due to overflow reset signal to cpu reset signal to cg reset signal to other peripheral macros wdtres2 issued due to overflow
chapter 20 reset function user?s manual u17705ej2v0ud 581 20.3 operation the system is reset, initializing each hardware unit, when a lo w level is input to the reset pin or if watchdog timer 1 or watchdog timer 2 overflows (wdtres1 or wdtres2). while a low level is being input to the reset pin, the ma in clock oscillator stops. t herefore, the overall power consumption of the system can be reduced. if the reset pin goes high or if the wdtres1 or wdtres2 signal is received, the reset status is released. if the reset status is released by reset pin input or the wdtres2 signal, the oscillation stabilization time elapses (reset value of osts register: 2 15 /f xx ) and then the cpu starts program execution. if the reset status is released by the wdtres1 signal, t he oscillation stabilization ti me is not inserted because the main system clock oscill ator does not stop.
chapter 20 reset function user?s manual u17705ej2v0ud 582 table 20-1. hardware status on reset pi n input or occurrence of wdtres2 signal item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues peripheral clock (f xx to f xx /1024) operation stops operation starts after securing oscillation stabilization time internal system clock (f clk ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) watchdog timer 1 clock (f xw ) operation stops operation starts cpu initialized program execution starts after securing oscillation stabilization time internal ram undefined if power-on reset or writing data to ram (by cpu) and reset input conflict (data is damaged). otherwise value imm ediately before reset input is retained. i/o lines high impedance on-chip peripheral i/o registers initialized to specified status watchdog timer 2 operation stops operation starts after securing oscillation stabilization time other on-chip peripheral fu nctions operation stops operation can be started after securing oscillation stabilization time table 20-2. hardware status on occurrence of wdtres1 signal item during reset after reset main clock oscillator (f x ) oscillation continues subclock oscillator (f xt ) oscillation continues peripheral clock (f xx to f xx /1024) operation stops operation starts internal system clock (f clk ) oscillation continues (initialized to f xx /8) cpu clock (f cpu ) oscillation continues (initialized to f xx /8) watchdog timer 1 clock (f xw ) operation continues internal ram undefined if writing data to ram (by cpu) and reset input conflict (data is damaged). otherwise value imm ediately before reset input is retained. i/o lines high impedance on-chip peripheral i/o registers initialized to specified status watchdog timer 2 operation stops operation starts other on-chip peripheral fu nctions operation stops o peration can be started
chapter 20 reset function user?s manual u17705ej2v0ud 583 figure 20-2. hardware status on reset input figure 20-3. operation on power application oscillation stabilization time count initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal analog delay reset f x v dd f clk oscillation stabilization time count initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay
chapter 20 reset function user?s manual u17705ej2v0ud 584 figure 20-4. timing of reset operation by watchdog timer 1 initialized to f xx /8 operation f clk : 12-clock width internal system reset signal (active low) wdtres1 signal (active low) f x f clk figure 20-5. timing of reset operation by watchdog timer 2 oscillation stabilization time count initialized to f xx /8 operation overflow of oscillation stabilization time counter internal system reset signal (active low) wdtres2 signal (active low) f x f clk analog delay
user?s manual u17705ej2v0ud 585 chapter 21 flash memory caution for the electrical specifications related to the flash memory rewriting, refer to chapter 23 electrical specifications. flash memory versions are commonly used in the following development environments and mass production applications. { for altering software after the v850es/ ke2 is soldered onto the target system. { for data adjustment when starting mass production. { for differentiating software according to the specif ication in small scale production of various models. { for facilitating inventory management. { for updating software after shipment. 21.1 features { 4-byte/1-clock access (when instruction is fetched) { capacity: 128 kb { write voltage: erase/write with a single power supply { rewriting method ? rewriting by communication with dedicated flash pr ogrammer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) { flash memory write prohibit f unction supported (security function) { safe rewriting of entire flash memory area by self programming using boot swap function { interrupts can be acknowledged during self programming.
chapter 21 flash memory user?s manual u17705ej2v0ud 586 21.2 memory configuration the 128 kb internal flash memory area is divided into 64 blocks and can be programmed/erased in block units. all the blocks can also be erased at once. when the boot swap function is used, the physical memory (blocks 0 to 3) located at the addresses of boot area 0 is replaced by the physical memory (blocks 4 to 7) locate d at the addresses of boot area 1. for details of the boot swap function, refer to 21.5 rewriting by self programming . figure 21-1. flash memory mapping block 0 (2 kb) block 1 (2 kb) block 2 (2 kb) block 3 (2 kb) block 5 (2 kb) block 6 (2 kb) block 7 (2 kb) block 8 (2 kb) block 4 (2 kb) block 63 (2 kb) 00007ffh 0000800h 0000fffh 0001000h 00027ffh 0002800h 0002fffh 0003000h 00037ffh 0003800h 0003fffh 0004000h 00047ffh 0004800h 001ffffh 001f7ffh 001f800h 00017ffh 0001800h 0001fffh 0002000h 0000000h 3ffffffh 3ff0000h 3feffffh 3fec000h 3febfffh 0020000h 001ffffh 0000000h use prohibited internal flash memory area (128 kb) boot area 0 note (8 kb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) boot area 1 note (8 kb) 128 kb note boot area 0 (blocks 0 to 3): boot area boot area 1 (blocks 4 to 7): area to be replac ed with the boot area by the boot swap function
chapter 21 flash memory user?s manual u17705ej2v0ud 587 21.3 functional outline the internal flash memory of the v850es/ke2 can be rewrit ten by using the rewrite f unction of the dedicated flash programmer, regardless of whether the v850es/ke2 has already been mounted on the target system or not (on- board/off-board programming). in addition, a security function that prohi bits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. the rewrite function using the user program (self programmi ng) is ideal for an application where it is assumed that the program is changed after production/sh ipment of the target syst em. a boot swap function t hat rewrites the entire flash memory area safely is also supported. in addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten und er various conditions, such as while communicating with an external device. table 21-1. rewrite method rewrite method functional outline operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of on-board/off- board programming. (during self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. therefore, the rewrite program must be transferred to the internal ram or external memory in advance). normal operation mode remark the fa series is a product of na ito densei machida mfg. co., ltd.
chapter 21 flash memory user?s manual u17705ej2v0ud 588 table 21-2. basic functions support ( { : supported, : not supported) function functional outline on-board/off-board programming self programming block erasure the contents of specified memory blocks are erased. { { chip erasure the contents of the entire memory area are erased all at once. { write writing to specified addresses, and a verify check to see if write level is secured are performed. { { verify/checksum data read from the flash memory is compared with data transferred from the flash programmer. { (can be read by user program) blank check the erasure status of the entire memory is checked. { { security setting use of the block erase command, chip erase command, program command, and read command and rewriting of the boot area can be prohibited. { (supported only when setting is changed from enable to disable) the following table lists the security functions. the bl ock erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting via on-board/off-board programming. each security function can be used in combination with the others at the same time. table 21-3. security functions function function outline block erase command prohibit execution of a block erase co mmand on all blocks is prohibited. setting of prohibition can be initialized by execution of a chip erase command. chip erase command prohibit execution of block erase and chip erase commands on all the blocks is prohibited. once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. program command prohibit execution of program and block er ase commands on all the blocks is prohibited. setting of prohibition can be initialized by execution of the chip erase command. read command prohibit execution of read command on all t he blocks is prohibited. setting of prohibition can be initialized by execution of the chip erase command. boot area rewrite prohibit boot areas from block 0 to the specified last block can be protected. the protected boot area cannot be rewritten (erased and written). setting of prohibition cannot be initialized by execution of the chip erase command.
chapter 21 flash memory user?s manual u17705ej2v0ud 589 table 21-4. security setting erase, write, read operations when each security is set ( : executable, : not executable, ? : not supported) notes on security setting function on-board/ off-board programming self programming on-board/ off-board programming self programming block erase command prohibit block erase command: chip erase command: program command: read command: block erasure (flashblockerase): chip erasure: ? write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. chip erase command prohibit block erase command: chip erase command: program command: note 1 read command: block erasure (flashblockerase): chip erasure: ? write (flashwordwrite): read (flashwordread): setting of prohibition cannot be initialized. program command prohibit block erase command: chip erase command: program command: read command: block erasure (flashblockerase): chip erasure: ? write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. read command prohibit block erase command: chip erase command: program command: read command: block erasure (flashblockerase): chip erasure: ? write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. boot area rewrite prohibit block erase command: note 2 chip erase command: program command: note 2 read command: block erasure (flashblockerase): chip erasure: ? write (flashwordwrite): read (flashwordread): setting of prohibition cannot be initialized. supported only when setting is changed from enable to prohibit notes 1. in this case, since the erase command is invalid, dat a different from the data al ready written in the flash memory cannot be written. 2. the boot area for which rewriti ng is prohibited is invalid.
chapter 21 flash memory user?s manual u17705ej2v0ud 590 (1) security setting by pg-fp4 (security flag settings) when disabling the read command (disable read), to raise the security level, it is recommended to also disable the block erase command (disable block erase) and program command (disable program). furthermore, when rewriting program is not necessary si milarly to the mask rom versions, additionally disable the chip erase command (disable chip erase). notes 1. set ?supply voltage?, ?program download/upload?, and ?command options? in broken lines in accordance with the use conditions. 2. to disable rewriting the boot area (boot block clus ter setting), select ?disable boot block cluster reprogramming? in ?security flag settings? and select the last block of the boot area for which rewriting is to be disabled. note 1 note 2
chapter 21 flash memory user?s manual u17705ej2v0ud 591 21.4 rewriting by dedicated flash programmer the flash memory can be rewritten by using a dedicat ed flash programmer after the v850es/ke2 is mounted on the target system (on-board pr ogramming). the flash memory can also be re written before the device is mounted on the target system (off-board progr amming) by using a dedicated program adapter (fa series). 21.4.1 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850es/ke2. figure 21-2. environment required for writing programs to flash memory host machine rs-232c dedicated flash programmer v850es/ke2 flmd1 v dd v ss reset uart0/csi00 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy s tat v e flmd0 usb a host machine is required for controlling the dedicated flash programmer. uart0 or csi00 is used for the interface between the dedicated flash programmer and the v850es/ke2 to perform writing, erasing, etc. a dedicated program adapter (fa series) is required for off-board writing. ? fa-70f3726gb-8eu-mx (already wired) ? fa-64gb-8eu-a (not wired: wiring required) remark the fa series is a product of naito densei machida mfg. co., ltd.
chapter 21 flash memory user?s manual u17705ej2v0ud 592 21.4.2 communication mode communication between the dedicated flash program mer and the v850es/ke2 is performed by serial communication using the uart0 or csi 00 interfaces of the v850es/ke2. (1) uart0 transfer rate: 9,600, 19,200, 31,250, 38,400, 76,800, 153,600 bps (setting of 57,600, 115,200, or 128,000 bps is not supported.) figure 21-3. communication with dedicated flash programmer (uart0) dedicated flash programmer v850es/ke2 v dd v ss reset txd0 rxd0 flmd1 flmd1 flmd0 flmd0 v dd gnd reset rxd txd x1 x2 clk pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve (2) csi00 serial clock: 2.4 khz to 2.5 mhz (msb first) figure 21-4. communication with de dicated flash programmer (csi00) dedicated flash programmer v850es/ke2 flmd1 v dd v ss reset so00 si00 sck00 flmd1 flmd0 flmd0 v dd gnd reset si so sck pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx y yy x x x x x x x x x x x x x x x x xxx y y yy statve x1 x2 clk
chapter 21 flash memory user?s manual u17705ej2v0ud 593 (3) csi00 + hs serial clock: 2.4 khz to 2.5 mhz (msb first) figure 21-5. communication with dedi cated flash programmer (csi00 + hs) dedicated flash programmer v850es/ke2 v dd v ss reset so00 si00 sck00 pcm0 v dd flmd1 flmd1 flmd0 flmd0 gnd reset si so sck hs pg-fp4 (flash p ro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve x1 x2 clk the dedicated flash programmer outputs the transfer clock, and the v850es/ke2 operates as a slave. when the pg-fp4 is used as the d edicated flash programmer, it gener ates the following signals to the v850es/ke2. for details, refer to the pg-fp4 user?s manual (u15260e) . table 21-5. signal connections of dedicated flash programmer (pg-fp4) pg-fp4 v850es/ke2 processing for connection signal name i/o pin function pin name uart0 csi00 csi00 + hs flmd0 output write enable/disable flmd0 flmd1 output write enable/disable flmd1 note 1 note 1 note 1 vdd ? v dd voltage generation/voltage monitor v dd gnd ? ground v ss clk output clock output to v850es/ke2 x1, x2 note 2 note 2 note 2 reset output reset signal reset si/rxd input receive signal so00 so/txd output transmit signal si00 sck output transfer clock sck00 hs input handshake signal for csi00 + hs communication pcm0 notes 1. wire the pin as shown in figure 21-6, or connect it to gnd on board via a pull-down resistor. 2. connect these pins to supply a clock from the pg -fp4 (wire as shown in figure 21-6, or create an oscillator on board and supply the clock). remark : must be connected. : does not have to be connected.
chapter 21 flash memory user?s manual u17705ej2v0ud 594 table 21-6. wiring between v850es/ke2 and pg-fp4 pin configuration of flash programmer (pg-fp 4) with csi00-hs with csi00 with uart0 signal name i/o pin function pin name on fa board pin name pin no. pin name pin no. pin name pin no. si/r x d input receive signal si p41/ so00 20 p41/so00 20 p30/txd0 22 so/t x d output transmit signal so p40/si00 19 p40/si00 19 p31/rxd0/ intp7 23 sck output transfer clock sck p42/sck00 21 p42/sck00 21 not needed not needed x1 x1 7 x1 7 x1 7 clk output clock to v850es/ke2 x2 x2 note 8 x2 note 8 x2 note 8 /reset output reset signal /r eset reset 9 reset 9 reset 9 flmd0 output write voltage flmd0 flmd0 3 flmd0 3 flmd0 3 flmd1 output write voltage flmd1 pdl5/ flmd1 52 pdl5/ flmd1 52 pdl5/ flmd1 52 hs input handshake signal for csi00 + hs communication reserve /hs pcm0 45 not needed not needed not needed not needed v dd 4 v dd 4 v dd 4 ev dd 33 ev dd 33 ev dd 33 vdd ? v dd voltage generation/voltage monitor vdd av ref0 1 av ref0 1 av ref0 1 v ss 6 v ss 6 v ss 6 av ss 2 av ss 2 av ss 2 gnd ? ground gnd ev ss 32 ev ss 32 ev ss 32 note when using the clock output of the flash programmer, connect clk of the programmer to x1, and connect its inverse signal to x2.
chapter 21 flash memory user?s manual u17705ej2v0ud 595 figure 21-6. wiring example of v850es/ke2 flash writing adapter (fa-64gb-8eu-a) (1/2) pd70f3726 vdd gnd gnd vdd gnd vdd vdd gnd 32 1 7 6 2 33 45 52 note 1 19 20 21 23 22 89 4 3 j1 vdd2 vdd so sck si /reset v pp reserve/hs clkout so sck si x1 x2 /reset clkin vpp reserve/hs rfu-3 rfu-2 rfu-1 flmd1 flmd0 vde note 2 note 3 connect to vdd. connect to gnd.
chapter 21 flash memory user?s manual u17705ej2v0ud 596 figure 21-6. wiring example of v850es/ke2 flash writing adapter (fa-64gb-8eu-a) (2/2) notes 1. wire the flmd1 pin as shown in the figure, or c onnect it to gnd on board via a pull-down resistor. 2. the above figure shows an example of wiring when the clock is supplied from the pg-fp4. be sure to set and connect as follows when the clock is supplied from the pg-fp4. ? set j1 of the flash adapter (fa) to the vdd side. ? connect clkout of fa to clkin of fa. ? connect x1 of fa to x1 of the device. ? connect x2 of fa to x2 of the device. if an oscillator is created on the flash adapter and a clock is supplied, the above setting and connections will not necessary. the following shows a circuit example. x1 x2 3. corresponding pin when using uart0 remarks 1. handle the pins not described above in accord ance with the specified handling of unused pins (refer to 2.2 pin i/o circuits and recomme nded connection of unused pins). when connecting to v dd via a resistor, use of a resistor of 1 k to 10 k is recommended. 2. this adapter is for a 64-pin plastic lqfp (fine pitch) package. 3. this diagram shows the wiring when using a handshake-supporting csi.
chapter 21 flash memory user?s manual u17705ej2v0ud 597 21.4.3 flash memory control the following shows the procedure for manipulating the flash memory. figure 21-7. procedure for manipulating flash memory start select communication system manipulate flash memory end? yes supplies flmd0 pulse no end switch to flash memory programming mode
chapter 21 flash memory user?s manual u17705ej2v0ud 598 21.4.4 selection of communication mode in the v850es/ke2, the communication mode is selected by inputting pulses (11 pulses max.) to the flmd0 pin after switching to the flash memory programming mode. the flmd0 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. figure 21-8. selection of communication mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxd0 (input) txd0 (output) v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset released note the number of clocks is as follows depending on the communication mode. flmd0 pulse communication mode remarks 0 uart0 communication rate: 9600 bps (after reset), lsb first 8 csi00 v850es/ke2 performs slave operation, msb first 11 csi00 + hs v850es/ke2 performs slave operation, msb first other rfu setting prohibited caution when uart0 is selected, the receive clock is calculate d based on the reset command sent from the dedicated flash programme r after receiving the flmd0 pulse.
chapter 21 flash memory user?s manual u17705ej2v0ud 599 21.4.5 communication commands the v850es/ke2 communicates with the dedicated flash programmer by means of commands. the signals sent from the dedicated flash programmer to the v850es/ke2 are called ?commands?. the response signals sent from the v850es/ke2 to the dedicated flash programmer are called ?response commands?. figure 21-9. communication commands dedicated flash programmer v850es/ke2 command response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve the following shows the commands for flash memory cont rol in the v850es/ke2. all of these commands are issued from the dedicated flash programmer, and the v850es/ke2 performs the processing corresponding to the commands. table 21-7. flash memory control commands support classification command name csi00 csi00 + hs uart0 function blank check block blank check command { { { checks if the contents of the memory in the specified block have been correctly erased. chip erase command { { { erases the contents of the entire memory. erase block erase command { { { erases the contents of the memory of the specified block. write program command { { { writes the specified address range, and executes a contents verify check. verify command { { { compares the contents of memory in the specified address range with data transferred from the flash programmer. verify checksum command { { { reads the checksum in the specified address range. silicon signature command { { { reads silicon signature information. system setting, control security setting command { { { prohibits the use of the chip erase command, block erase command, program command, read command, and rewriting of the boot area.
chapter 21 flash memory user?s manual u17705ej2v0ud 600 21.4.6 pin connection when performing on-board writing, mount a connector on t he target system to conne ct to the dedicated flash programmer. also, incorporate a function on-board to s witch from the normal operation mode to the flash memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after rese t. therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) flmd0 pin in the normal operation mode, input a voltage of v ss level to the flmd0 pin. in the flash memory programming mode, supply a write voltage of v dd level to the flmd0 pin. because the flmd0 pin serves as a write protection pin in the self programming mode, a voltage of v dd level must be supplied to the flmd0 pin via port control, etc., before writing to the flash memory. for details, refer to 21.5.5 (1) flmd0 pin . figure 21-10. flmd0 pin connection example v850es/ke2 flmd0 dedicated flash programmer connection pin pull-down resistor (r flmd0 )
chapter 21 flash memory user?s manual u17705ej2v0ud 601 (2) flmd1 pin when 0 v is input to the flmd0 pin, t he flmd1 pin does not function. when v dd is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v must be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. figure 21-11. flmd1 pin connection example flmd1 pull-down resistor (r flmd1 ) other device v850es/ke2 caution if the v dd signal is input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal. table 21-8. relationship between flmd0 and flmd1 pi ns and operation mode wh en reset is released flmd0 flmd1 operation mode 0 don?t care normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited
chapter 21 flash memory user?s manual u17705ej2v0ud 602 (3) serial interface pin the following shows the pins used by each serial interface. table 21-9. pins used by serial interfaces serial interface pins used uart0 txd0, rxd0 csi00 so00, si00, sck00 csi00 + hs so00, si00, sck00, pcm0 when connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) conflict of signals when the dedicated flash programmer (output) is connec ted to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. figure 21-12. conflict of signals (serial interface input pin) v850es/ke2 input pin conflict of signals dedicated flash programmer connection pins other device output pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side.
chapter 21 flash memory user?s manual u17705ej2v0ud 603 (b) malfunction of other device when the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device. figure 21-13. malfunction of other device v850es/ke2 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the v850es/ke2 outputs affects the other device, isolate the signal on the other device side. v850es/ke2 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side.
chapter 21 flash memory user?s manual u17705ej2v0ud 604 (4) reset pin when the reset signals of the dedicated flash programmer are connected to the reset pin that is connected to the reset signal generator on-board, a conflict of signal s occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 21-14. conflict of signals (reset pin) v850es/ke2 reset dedicated flash programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. (5) port pins (including nmi) when the system shifts to the flash memory programmi ng mode, all the pins that are not used for flash memory programming are in the same st atus as that immediately after rese t. if the external device connected to each port does not recognize the st atus of the port immediately after reset, pins require appropriate processing, such as connecting to v dd via a resistor or connecting to v ss via a resistor. (6) other signal pins connect x1, x2, xt1, and xt2 in the same st atus as that in the normal operation mode. (7) power supply supply the same power (v dd , v ss , ev dd , ev ss , av ss , av ref0 ) as in normal operation mode.
chapter 21 flash memory user?s manual u17705ej2v0ud 605 21.5 rewriting by self programming 21.5.1 overview the v850es/ke2 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. by using this interface and a self programming library that is used to rewrit e the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal ram or external memory. consequently, the user program c an be upgraded and constant data can be rewritten in the field. figure 21-15. concept of self programming application program self programming library flash macro service flash memory flash function execution flash information erase, write
chapter 21 flash memory user?s manual u17705ej2v0ud 606 21.5.2 features (1) secure self programming (boot swap function) the v850es/ke2 supports a boot swap function that ca n exchange the physical memory (blocks 0 to 3) of boot area 0 with the physical memory (blocks 4 to 7) of boot area 1. by writi ng the start program to be rewritten to boot area 1 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriti ng because the correct user program always exists in boot area 0. figure 21-16. rewriting entire memory area (boot swap) block n block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 block 63 block 63 boot swap rewriting boot areas 0 and 1 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 block 8 block 7 block 6 block 5 block 4 block 3 block 2 block 1 block 0 (2) interrupt support instructions cannot be fetched from the flash memory during self programming. c onventionally, therefore, a user handler written to the flash me mory could not be used even if an inte rrupt occurred. therefore, in the v850es/ke2, to use an interrupt dur ing self programming, processing tr ansits to the specific address note in the internal ram. allocate the jump instru ction that transits processi ng to the user interrupt se rvicing at the specific address note in the internal ram. note nmi interrupt: start address of internal ram maskable interrupt: start address of internal ram + 4 addresses
chapter 21 flash memory user?s manual u17705ej2v0ud 607 21.5.3 standard self programming flow the entire processing to rewrite the flash memory by flash self programming is illustrated below. figure 21-17. standard self programming flow (a) rewriting at once (b) rewriting in block units flash environment initialization processing erase processing write processing flash information setting processing note 1 internal verify processing boot area swapping processing note 2 flash environment end processing flash memory manipulation end of processing flash environment initialization processing erase processing write processing flash information setting processing note 1 internal verify processing boot area swapping processing note 2 flash environment end processing flash memory manipulation end of processing all blocks end? yes no ? disable accessing flash area ? disable setting of stop mode ? disable stopping clock ? disable accessing flash area ? disable setting of stop mode ? disable stopping clock notes 1. if a security setting is not performed, flash in formation setting processing does not have to be executed. 2. if boot swap is not used, flash information setting processing and boot area swap processing do not have to be executed.
chapter 21 flash memory user?s manual u17705ej2v0ud 608 21.5.4 flash functions table 21-10. main flash function list function name outline support flashenv initialization of flash control macro flashblockerase erasure of only specified one block flashwordwrite writing from specified address flashblockiverify internal verification of specified block flashblockblankcheck blank check of specified block flashflmdcheck check of flmd pin flashgetinfo reading of flash information flashsetinfo setting of flash information flashbootswap swapping of boot area flashwordread reading data from specified address remark for details, refer to the v850 series flash memory self programming (single power supply flash memory) user?s manual . contact an nec electronics sales representative for the above manual. 21.5.5 pin processing (1) flmd0 pin the flmd0 pin is used to set the operation mode when re set is released and to protect the flash memory from being written during self rewriting. it is therefore necessary to keep the voltage applied to the flmd0 pin at 0 v when reset is released and a normal operation is exec uted. it is also necessary to apply a voltage of v dd level to the flmd0 pin during the self programming m ode period via port control before the memory is rewritten. when self programming has been completed, the volt age on the flmd0 pin must be returned to 0 v. figure 21-18. mode change timing reset signal flmd0 pin v dd 0 v v dd 0 v self programming mode normal operation mode normal operation mode caution make sure that the flmd0 pin is at 0 v when reset is released.
chapter 21 flash memory user?s manual u17705ej2v0ud 609 21.5.6 internal resources used the following table lists the internal resources used for se lf programming. these internal resources can also be used freely for purposes ot her than self programming. table 21-11. internal resources used resource name description entry ram area (internal ram/external ram size: 136 bytes) routines and parameters used for the flash macr o service are located in this area. the entry program and default parameters are copied by calling a library initialization function. stack area (stack size: 600 bytes) an extension of the stack us ed by the user is used by the library (can be used in both the internal ram and external ram). library code (code size: approx. 1600 bytes) program entity of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as user application. calls flash functions. maskable interrupt can be used in user application execut ion status or self programming status. to use this interrupt in the self-programming status, sinc e the processing transits to the address of the internal ram start address + 4 addresses (3ffe004h), allocate the jump instruction that transits the processing to the user inte rrupt servicing at the address of the internal ram start address + 4 addresses (3ffe004h) in advance. nmi interrupt can be used in user application execution status or self programming status. to use this interrupt in the self-programming status, sinc e the processing transits to the address of the internal ram start address (3ffe000h), allocate the jump instruction that transits the processing to the user interrupt serv icing at the internal ram start address (3ffe000h) in advance. tm50, tm51 because tm50 and tm51 are used in the flash macro service, do not use them in the self programming status. when using tm50 and tm51 after self programming, set them again. remark for details, refer to the v850 series flash memory self pr ogramming (single power supply flash memory) user?s manual . contact an nec electronics sales representative for the above manual.
user?s manual u17705ej2v0ud 610 chapter 22 on-chip debug function the v850es/ke2 utilizes user resources to impl ement an on-chip debug function by minicube2. the v850es/ke2 is not provi ded with a dcu (debug control unit). howe ver, it can be used as a simplified in- circuit emulator by using the on-chip debug emulator (minicube ? ) and debug adapt er (qb-v850eskx1h-da). for the connection, refer to appendix a development tools . remark the dcu (debug control unit) is a circuit that im plements the on-chip debu g function by using the drst, dck, dms, ddi, and ddo pins as debug interface pins. the following table shows the features of the two on-chip debug functions. table 22-1. on-chip debug function features debugging using dcu debugging without using dcu debug interface pins not supported. ? when uart0 is used rxd0, txd0 ? when csi00 is used si00, so00, sck00, hs (pcm0) securing of user resources not supported. required hardware break function not supported. not supported. internal rom area not supported. 4 points software break function ram area not supported. 2000 points real-time ram monitor function note 1 not supported. available dynamic memory modification (dmm) function note 2 not supported. available mask function not supported. reset pin rom security function not supported. 10-byte id code authentication hardware used not supported. ninicube2, etc. trace function not supported. not supported. debug interrupt interface function (dbint) not supported. not supported. notes 1. this is a function which reads out memo ry contents during program execution. 2. this is a function which rewrites ra m contents during program execution.
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 611 22.1 debugging without using dcu the following describes how to implement an on-chip debug function using mini cube2 with the uart0 pins (rxd0, txd0) or csi00 pins (si00, so00, sck00, hs (pmc0)) as debug interfaces, without using the dcu. 22.1.1 circuit connection examples figure 22-1. circuit connection example when uart0/csi00 is used for communication interface qb-mini2 v850es/ke2 gnd v dd v dd reset_out rxd/si note 1 vdd txd/so note 1 sck hs clk note 2 flmd1 note 3 flmd0 note 3 reset_in note 4 v ss txd0/so00 v dd rxd0/si00 sck00 flmd1 reset circuit flmd0 port x 100 10 k 1 to 10 k 1 k reset signal 10 k 1 to 10 k 1 to 10 k 3 to 10 k 1 to 10 k v dd note 5 v dd v dd hs reset m inic ube2 m inicube2 notes 1. connect txd0/so00 (transmit side) of the v850 es/ke2 to rxd/si (receive side) of the target connector, and txd/so (transmit side) of the tar get connector to rxd0/si00 (receive side) of the v850es/ke2. 2. this pin may be used to supply a clock from minicube2 during flash memory programming. for details, refer to chapter 21 flash memory . 3. the v850es/ke2-side pin connected to this pin (f lmd0, flmd1) can be used as an alternate- function pin other than while the memory is rewri tten during a break in debugging, because this pin is in hi-z state. 4. this connection is designed assuming that the reset signal is output from the n-ch open-drain buffer (output resistance: 100 or less). 5. the circuit enclosed by the broken lines is designe d for flash self programming, which controls the flmd0 pin via ports. use the port for inputting or outputting the high level. when flash self programming is not performed, a pull-down resistanc e for the flmd0 pin can be within 1 to 10 k . remark refer to table 22-2 for pins used when uart0 or csi00 is used for communication interface.
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 612 table 22-2. wiring between v850es/ke2 and minicube2 pin configuration of minicube2 (qb- mini2) with csi00-hs with uart0 signal name i/o pin function pin name pin no. pin name pin no. si/rxd input pin to receive commands and data from v850es/ke2 p41/so00 20 p30/txd0 22 so/txd output pin to transmit commands and data to v850es/ke2 p40/si00 19 p31/rxd0 23 sck output clock output pin for 3-wire serial communication p42/sck00 21 not needed not needed not needed note not needed note not needed note not needed note clk note output clock output pin to v850es/ke2 not needed note not needed note not needed note not needed note reset_out output reset output pin to v850es/ke2 reset 9 reset 9 flmd0 output output pin to set v850es/ke2 to debug mode or programming mode flmd0 3 flmd0 3 flmd1 output output pin to set programming mode pdl5/flmd1 52 pdl5/flmd1 52 hs input handshake signal for csi00 + hs communication pcm0 45 not needed not needed v dd 4 v dd 4 ev dd 33 bv dd 33 vdd ? v dd voltage generation av ref0 1 av ref0 1 v ss 6 v ss 6 av ss 2 av ss 2 gnd ? ground ev ss 32 ev ss 32 reset_in input reset input pin on the target system note it is used as the clock output of the flash pr ogrammer for minicube2. for details, refer to chapter 21 flash memory . 22.1.2 maskable functions only reset signals can be masked. the maskable functions with the debugg er (id850qb) and the corresponding v850es/ke2 functions are listed below. table 22-3. maskable functions maskable functions with id850qb corresponding v850es/ke2 functions nmi0 ? nmi1 ? nmi2 ? stop ? hold ? reset reset signal generation by reset pin input wait ?
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 613 22.1.3 securing of user resources the user must prepare the following to perform communi cation between minicube2 and the target device and implement each debug function. these it ems need to be set in the user program or using the compiler options. (1) securement of memory space the shaded portions in figure 22-2 are the areas rese rved for placing the debug monitor program, so user programs and data cannot be allocated in these spaces. these spaces must be secured so as not to be used by the user program. figure 22-2. memory spaces where de bug monitor programs are allocated csi/uart receive interrupt vector (4 bytes) reset vector (4 bytes) interrupt vector for debugging (4 bytes) (2 kb) security id area (10 bytes) : debugging area 00fffffh 0000060h 0000160h note 0000070h 0000000h access-prohibited area internal rom (16 bytes) 3ffe000h access-prohibited area internal ram internal rom area internal ram area 001ffffh 001f800h 3ffefffh 3ffeff0h note this is the address when csi00 is used. it starts at 0000190h when uart0 is used. ? security id setting the id code must be embedded in the area between 0000070h and 0000079h in figure 22-2, to prevent the memory from being read by an unauthorized person. for details, refer to 22.2 rom security function .
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 614 (2) reset vector a reset vector includes the jump in struction for the debug monitor program. [how to secure areas] it is not necessary to secure this area intentionally. when downloading a program, however, the debugger rewrites the reset vector in accordance with the followin g cases. if the rewritt en pattern does not match the following cases, the debugger generates an error (f0c34 when using the id850qb). (a) when two nop instructions ar e placed in succession from address 0 before rewriting after rewriting 0x0 nop jumps to debug monitor program at 0x0 0x2 nop 0x4 xxxx 0x4 xxxx (b) when two 0xffff are successi vely placed from address 0 (already era sed device) before rewriting after rewriting 0x0 0xffff jumps to debug monitor program at 0x0 0x2 0xffff 0x4 xxxx 0x4 xxxx (c) the jr instruction is placed at address 0 (when using ca850) before rewriting after rewriting 0x0 jr disp22 jumps to debug monitor program at 0x0 0x4 jr disp22 - 4 (d) mov32 and jmp are placed in succession from address 0 (when using iar compiler iccv850) before rewriting after rewriting 0x0 mov imm32,reg1 jumps to debug monitor program at 0x0 0x6 jmp [reg1] 0x4 mov imm32,reg1 0xa jmp [reg1] (e) the jump instruction for the debug monitor program is placed at address 0 before rewriting after rewriting jumps to debug monitor program at 0x0 no change
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 615 (3) securement of area for debug monitor program the shaded portions in figure 22-2 are the areas where the debug monitor program is allocated. the monitor program performs initialization processing for debug commu nication interface and run or break processing for the cpu. the internal rom area mu st be filled with 0xff. this area mu st not be rewritten by the user program. [how to secure areas] it is not necessarily required to secure this area if the user program does not use this area. to avoid problems that may occur during the debugger st artup, however, it is recommended to secure this area in advance, using the compiler. the following shows examples for securing the area, using the nec electronics compiler ca850. add the assemble source file and link directive code, as shown below. ? assemble source (add the following code as an assemble source file.) -- secures 2 kb space for monitor rom section .section "monitorrom", const .space 0x800, 0xff -- secures interrupt vector for debugging .section "dbg0" .space 4, 0xff -- secures interrupt vector for serial communication -- change the section name according to the serial communication mode used .section "intcsi00" .space 4, 0xff -- secures 16-byte space for monitor ram section .section "monitorram", bss .lcomm monitorramsym, 16, 4 -- defines symbol monitorramsym ? link directive (add the following code to the link directive file.) the following shows an example when the intern al rom has 128 kb (end address is 003ffffh) and internal ram has 4 kb (end address is 1ffefffh). mromseg : !load ?r v0x01f800{ monitorrom = $progbits ?a monitorrom; }; mramseg : !load ?rw v0x03ffeff0{ monitorram = $nobits ?aw monitorram; };
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 616 (4) securement of communication serial interface uart0 or csi00 is used for communication between mi nicube2 and the target system. the settings related to the serial interface modes are performed by the debu g monitor program, but if the setting is changed by the user program, a communication error may occur. to prevent such a problem from occurring, communica tion serial interface must be secured in the user program. [how to secure communica tion serial interface] ? serial interface registers do not set the registers related to uart0 and csi00 in the user program. ? interrupt mask register when uart0 is used, do not mask the receive end inte rrupt (intsr0). when csi00 is used, do not mask the transmit end interrupt (intcsi00). (a) when csi00 is used csi0ic0 0 6543210 7 (b) when uart0 is used sric0 0 6543210 7 remark : don?t care
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 617 ? port registers when uart0 is used when uart0 is used, port registers are set to make the txd0 and rxd0 pins valid by the debug monitor program. do not change the following register setti ngs with the user program during debugging. (the same value can be overwritten.) pmc3l 11 6543210 7 remark : don?t care ? port registers when csi00 is used when csi00 is used, port registers are set to make t he si00, so00, sck00, and hs (pmc0) pins valid by the debug monitor program. do not change the following register setti ngs with the user program during debugging. (the same value can be overwritten.) (a) si00, so00, and sck00 settings pmc4 111 6543210 7 (b) hs (pmc0 pin) settings pmcm 0 6543210 7 pcm note 6543210 7 note writing to this bit is prohibited. the port values corresponding to the hs pin ar e changed by the monitor program according to the debugger status. to perform port register settings in 8-bit units, the user program can usually use read-modify-write. if an interrupt for debugging occurs before writing, however, an unexpected operation may be performed. remark : don?t care
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 618 22.1.4 cautions (1) handling of device that was used for debugging do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewritten during debugging and the number of rewr ites of the flash memory cannot be guaranteed. moreover, do not embed the debug monitor program into mass-produced products. (2) when breaks cannot be executed forced breaks cannot be executed if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial interface, whic h is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby releas e by a maskable interrupt is prohibited ? mode for communication between mini cube2 and the target device is ua rt0, and the main clock has been stopped (3) when pseudo real-ti me ram monitor (rrm) function and dmm function do not operate the pseudo rrm function and dmm function do not operat e if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial interface, whic h is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby releas e by a maskable interrupt is prohibited ? mode for communication between mini cube2 and the target device is ua rt0, and the main clock has been stopped ? mode for communication between minicube2 and the tar get device is uart0, and a clock different from the one specified in the debugger is used for communication (4) standby release with pseudo rrm and dmm functions enabled the standby mode is released by the pseudo rrm function and dmm function if one of the following conditions is satisfied. ? mode for communication between minicube2 and the target device is csi00 ? mode for communication between mini cube2 and the target device is ua rt0, and the main clock has been supplied. (5) writing to peripheral i/o re gisters that requires a specifi c sequence, using dmm function peripheral i/o registers that re quires a specific sequence cannot be written with the dmm function. (6) flash self programming if a space where the debug monitor program is allocated is rewritten by flash self programming, the debugger can no longer operate normally.
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 619 22.2 rom security function 22.2.1 security id the flash memory versions of the v850es/ke2 perform aut hentication using a 10-byte id code to prevent the contents of the flash memory from being read by an unaut horized person during on-chip debugging by the on-chip debug emulator. set the id code in the 10-byte on-chip flash memory area from 0000070h to 0000079h to allow the debugger perform id authentication. if the ids match, the security is released and reading fl ash memory and using the on-chip debug emulator are enabled. ? set the 10-byte id code to 0000070h to 0000079h. ? bit 7 of 0000079h is the on-chip debug emulator enable flag. (0: disable, 1: enable) ? when the on-chip debug emulator is started, the debugger requests id input. when the id code input on the debugger and the id code set in 0000070h to 0000079h match, the debugger starts. ? debugging cannot be performed if the on-chip debug emul ator enable flag is 0, even if the id codes match. figure 22-3. security id area 0000079h 0000070h 0000000h security id (10 bytes) caution after the flash memory is erased , 1 is written to the entire area.
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 620 22.2.2 setting the following shows how to set the id code as shown in table 22-4. when the id code is set as shown in table 22-4, the id code input in the configuration dialog box of the id850qb is ?123456789abcdef123d4? (the id code is case-insensitive). table 22-4. id code address value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9a 0x75 0xbc 0x76 0xde 0x77 0xf1 0x78 0x23 0x79 0xd4 the id code can be specified for the device file that suppor ts ca850 ver. 3.10 or later and the security id using the pm+ compiler common option setting.
chapter 22 on-chip debug function user?s manual u17705ej2v0ud 621 [program example (when usi ng ca850 ver. 3.10 or later)] #-------------------------------------- # securityid #-------------------------------------- .section "security_id" --interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xf1debc9a --4-7 byte code .hword 0xd423 --8-9 byte code remark add the above program exam ple to the startup files.
user?s manual u17705ej2v0ud 622 chapter 23 electrical specifications absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd v dd = ev dd = av ref0 ? 0.3 to +6.5 v av ref0 v dd = ev dd = av ref0 ? 0.3 to +6.5 v ev dd v dd = ev dd = av ref0 ? 0.3 to +6.5 v v ss v ss = ev ss = av ss ? 0.3 to +0.3 v av ss v ss = ev ss = av ss ? 0.3 to +0.3 v supply voltage ev ss v ss = ev ss = av ss ? 0.3 to +0.3 v v i1 p00 to p06, p30 to p35, p38, p39, p40 to p42, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7, reset, flmd0 ? 0.3 to ev dd + 0.3 note v input voltage v i2 x1, x2, xt1, xt2 ? 0.3 to v dd + 0.3 note v analog input voltage v ian p70 to p77 ? 0.3 to av ref0 + 0.3 note v note be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-c ollector pins, however, can be dir ectly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance stat e and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that th e absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. remark unless otherwise specified, the characte ristics of alternate-function pins are the same as those of port pins.
chapter 23 electrical specifications user?s manual u17705ej2v0ud 623 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit note 20 ma p38, p39 per pin 30 ma p00 to p06, p30 to p35, p38, p39, p40 to p42 35 ma output current, low i ol p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 total of all pins: 70 ma 35 ma note per pin ? 10 ma p00 to p06, p30 to p35, p40 to p42 ? 30 ma output current, high i oh p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 total of all pins: ? 60 ma ? 30 ma normal operation mode ? 40 to +85 c operating ambient temperature t a flash memory programming mode ? 40 to +85 c storage temperature t stg ? 40 to +125 c note p00 to p06, p30 to p35, p40 to p 42, p50 to p55, p90, p91, p96 to p 99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-c ollector pins, however, can be dir ectly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance stat e and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that th e absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. remark unless otherwise specified, the characte ristics of alternate-function pins are the same as those of port pins. capacitance (t a = 25 c, v dd = ev dd = av ref0 = v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i p70 to p77 15 pf note 15 pf i/o capacitance c io f x = 1 mhz unmeasured pins returned to 0 v p38, p39 20 pf note p00 to p06, p30 to p35, p40 to p 42, p50 to p55, p90, p91, p96 to p 99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 remark f x : main clock oscillation frequency
chapter 23 electrical specifications user?s manual u17705ej2v0ud 624 pll characteristics (t a = ? 40 to + 85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input frequency f x 2 5 mhz output frequency f xx 8 20 mhz lock time t pll after v dd reaches 2.7 v (min.) 200 s operating conditions (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v dd = 4.5 to 5.5 v 0.25 20 mhz v dd = 4.0 to 5.5 v 0.25 16 mhz in pll mode v dd = 2.7 to 5.5 v 0.25 10 mhz in clock-through mode v dd = 2.7 to 5.5 v 0.0625 10 mhz internal system clock frequency f clk operating with subclock note 32.768 khz note v dd = 2.7 to 5.5 v internal system clock fr equency vs. supply voltage 1.0 0.1 0.032 0.01 supply voltage v dd [v] internal system clock frequency f clk [mhz] 2.0 2.5 2.7 10.0 16.0 20.0 100 3.0 3.5 4.0 4.5 5.0 5.5 6.0
chapter 23 electrical specifications user?s manual u17705ej2v0ud 625 operating conditions for eeprom emulation (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v dd = 4.5 to 5.5 v 0.25 16 mhz v dd = 4.0 to 5.5 v 0.25 12 mhz in pll mode v dd = 2.7 to 5.5 v 0.25 6 mhz v dd = 4.0 to 5.5 v 0.0625 10 mhz in clock-through mode v dd = 2.7 to 5.5 v 0.0625 6 mhz internal system clock frequency f clk operating with subclock notes 1, 2 32.768 khz notes 1. v dd = 2.7 to 5.5 v 2. do not stop the main clock. internal system clock fr equency vs. supply voltage 1.0 0.1 0.032 0.01 supply voltage v dd [v] internal system clock frequency f clk [mhz] 2.0 2.5 2.7 3.5 10.0 6.0 20.0 16.0 100 3.0 4.0 5.0 5.5 4.5 6.0
chapter 23 electrical specifications user?s manual u17705ej2v0ud 626 main clock oscilla tor characteristics (1) crystal resonator, ceramic resonator (t a = ? 40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit v dd = 4.5 to 5.5 v 2 5 mhz v dd = 4.0 to 5.5 v 2 4 mhz in pll mode v dd = 2.7 to 5.5 v 2 2.5 mhz oscillation frequency (f x ) note 1 in clock through mode v dd = 2.7 to 5.5 v 2 10 mhz after reset is released osts0 = 1 2 15 /f x s x2 x1 oscillation stabilization time note 2 after stop mode is released note 3 s notes 1. indicates only oscillator characteristics. 2. time required to stabilize the resonator after reset or stop mode is released. 3. the value differs depending on the osts register settings. (2) external clock (t a = ? 40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit v dd = 4.5 to 5.5 v 2 5 mhz v dd = 4.0 to 5.5 v 2 4 mhz in pll mode v dd = 2.7 to 5.5 v 2 2.5 mhz x2 x1 external clock x1, x2 input frequency (f x ) note in clock through mode v dd = 2.7 to 5.5 v 2 10 mhz note the duty ratio of the input waveform must be within 50% 5%. cautions 1. when using the main cl ock oscillator, wire as follows in the area enclosed by th e broken lines in the above figures to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main clock is stopped and the devi ce is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock.
chapter 23 electrical specifications user?s manual u17705ej2v0ud 627 subclock oscillato r characteristics (1) crystal resonator (t a = ? 40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz xt2 xt1 oscillation stabilization time note 2 10 s notes 1. indicates only oscillator characteristics. 2. time required from when v dd reaches oscillation voltage range (2 .7 v (min.)) to when the crystal resonator stabilizes. (2) external clock (t a = ? 40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) recommended circuit parameter conditions min. typ. max. unit xt2 xt1 external clock input frequency (f xt ) note v dd = 2.7 to 5.5 v 32 35 khz note the duty ratio of the input waveform must be within 50% 5%. cautions 1. when using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subclock oscillator is designed as a low-am plitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillato r. particular care is therefore required with the wiring me thod when the subclock is used.
chapter 23 electrical specifications user?s manual u17705ej2v0ud 628 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) (1/3) parameter symbol conditions min. typ. max. unit per pin for p00 to p06, p30 to p35, p40 to p42, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 ? 5.0 ma ev dd = 4.0 to 5.5 v ? 30 ma total of p00 to p06, p30 to p35, p40 to p42 ev dd = 2.7 to 5.5 v ? 15 ma ev dd = 4.0 to 5.5 v ? 30 ma output current, high i oh1 total of p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 ev dd = 2.7 to 5.5 v ? 15 ma per pin for p00 to p06, p30 to p35, p40 to p42, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 10 ma ev dd = 4.0 to 5.5 v 15 ma per pin for p38, p39 ev dd = 2.7 to 5.5 v 8 ma total of p00 to p06, p30 to p35, p40 to p42 30 ma output current, low i ol1 total of p38, p39, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 30 ma v ih1 note 1 0.7ev dd ev dd v v ih2 note 2 0.8ev dd ev dd v v ih3 p70 to p77 0.7av ref0 av ref0 v input voltage, high v ih4 note 3 x1, x2, xt1, xt2 v dd ? 0.5 v dd v v il1 note 1 ev ss 0.3ev dd v v il2 note 2 ev ss 0.2ev dd v v il3 p70 to p77 av ss 0.3av ref0 v input voltage, low v ih4 note 3 x1, x2, xt1, xt2 v ss 0.4 v notes 1. p00, p01, p30, p41, p98, pcm0, pcm1, pd l0 to pdl7 and their alternate-function pins. 2. reset, flmd0, p02 to p06, p31 to p35, p38, p39, p40, p42, p50 to p55, p 90, p91, p96, p97, p99, p913 to p915 and their alternate-function pins. 3. when an external clock is used. remark unless otherwise specified, the characte ristics of alternate-function pins are the same as those of port pins.
chapter 23 electrical specifications user?s manual u17705ej2v0ud 629 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) (2/3) parameter symbol conditions min. typ. max. unit note 1 i oh = ? 2.0 ma, ev dd = 4.0 to 5.5 v ev dd ? 1.0 ev dd v output voltage, high v oh1 note 2 i oh = ? 0.1 ma, ev dd = 2.7 to 5.5 v ev dd ? 0.5 ev dd v v ol1 note 3 i ol = 2.0 ma note 4 0 0.8 v i ol = 15 ma, ev dd = 4.0 to 5.5 v 0 2.0 v i ol = 8 ma, ev dd = 3.0 to 5.5 v 0 1.0 v output voltage, low v ol2 p38, p39 i ol = 5 ma, ev dd = 2.7 to 5.5 v 0 1.0 v input leakage current, high i lih v in = v dd 3.0 a input leakage current, low i lil v in = 0 v ? 3.0 a output leakage current, high i loh v o = v dd 3.0 a output leakage current, low i lol v o = 0 v ? 3.0 a pull-up resistor r l v in = 0 v 10 30 100 k notes 1. total of p00 to p06, p30 to p35, p40 to p42 and their alternate-function pins: i oh = ? 30 ma, total of p50 to p55, p90, p 91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 and their alternate-function pins: i oh = ? 30 ma. 2. total of p00 to p06, p30 to p35, p40 to p42 and their alternate-function pins: i oh = ? 15 ma, total of p50 to p55, p90, p 91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 and their alternate-function pins: i oh = ? 15 ma. 3. total of p00 to p06, p30 to p35, p40 to p42 and their alternate-function pins: i ol = 30 ma, total of p38, p39, p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0, pcm1, pdl0 to pdl7 and their alternate-function pins: i ol = 30 ma. 4. refer to i ol1 for i ol of p38 and p39.
chapter 23 electrical specifications user?s manual u17705ej2v0ud 630 dc characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) (3/3) parameter symbol conditions min. typ. note 2 max. unit normal operation mode (all peripheral functions operating) f xx = 20 mhz (f x = 5 mhz) (in pll mode) v dd = 5 v 10% 51 70 ma i dd1 f xx = 10 mhz (in clock-through mode) v dd = 3 v 10% 17 34 ma halt mode (all peripheral functions operating) f xx = 20 mhz (f x = 5 mhz) (in pll mode) v dd = 5 v 10% 25 38 ma i dd2 f xx = 10 mhz (in clock-through mode) v dd = 3 v 10% 9 15 ma idle mode (watch timer operating) f x = 5 mhz (when pll mode off) v dd = 5 v 10% 1.8 2.9 ma i dd3 f x = 10 mhz (in clock-through mode) v dd = 3 v 10% 1.4 2.4 ma i dd4 subclock operation mode (f xt = 32.768 khz) main oscillation stopped 240 400 a i dd5 sub-idle mode (f xt = 32.768 khz) watch timer operating, main oscillation stopped 20 75 a stop mode subclock oscillating 15 60 a i dd6 subclock stopped (xt1 = v ss , psmr.xtstp bit = 1) 0.1 30 a flash memory erase/write (t a = ? 40 to +85 c) f xx = 20 mhz (f x = 5 mhz) (in pll mode) v dd = 5 v 10% 51 70 ma supply current note 1 i dd7 f xx = 10 mhz (in clock-through mode) v dd = 3 v 10% 17 34 ma notes 1. total current of v dd and ev dd (all ports stopped). av ref0 is not included. 2. typ. value of v dd is as follows. v dd = 5.0 v when v dd = 5 v 10% v dd = 3.0 v when v dd = 3 v 10% remark f xx : main clock frequency f x : main clock oscillation frequency f xt : subclock frequency
chapter 23 electrical specifications user?s manual u17705ej2v0ud 631 data retention characteristics stop mode (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 2.0 5.5 v stop release signal input time t drel 0 s caution shifting to stop mode and restoring from stop mode mu st be performed within the rated operating range. t drel stop release signal input stop mode setting v dddr v dd reset (input) stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) operating voltage lower limit
chapter 23 electrical specifications user?s manual u17705ej2v0ud 632 ac characteristics ac test input measurement points (v dd , av ref0 , ev dd ) ac test output measurement points load conditions v oh v ol v oh v ol measurement points dut (device under measurement) c l = 50 pf caution if the load capaci tance exceeds 50 pf due to the circ uit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. v dd 0 v v ih v il v ih v il measurement points
chapter 23 electrical specifications user?s manual u17705ej2v0ud 633 clkout output timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output cycle t cyk <1> 50 ns 30.6 s v dd = 4.0 to 5.5 v t cyk /2 ? 17 ns high-level width t wkh <2> v dd = 2.7 to 5.5 v t cyk /2 ? 26 ns v dd = 4.0 to 5.5 v t cyk /2 ? 17 ns low-level width t wkl <3> v dd = 2.7 to 5.5 v t cyk /2 ? 26 ns v dd = 4.0 to 5.5 v 17 ns rise time t kr <4> v dd = 2.7 to 5.5 v 26 ns v dd = 4.0 to 5.5 v 17 ns fall time t kf <5> v dd = 2.7 to 5.5 v 26 ns clock timing clkout (output) <1> <2> <3> <4> <5>
chapter 23 electrical specifications user?s manual u17705ej2v0ud 634 basic operation (1) reset/external interrupt timing ( t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf ) parameter symbol conditions min. max. unit t wrsl1 <87> reset in power-on status 2 s reset low-level width t wrsl2 <88> power-on reset 2 s nmi high-level width t wnih <89> analog noise elimination 1 s nmi low-level width t wnil <90> analog noise elimination 1 s n = 0 to 7 (analog noise elimination) 600 ns intpn high-level width t with <91> n = 3 (when digital noise elimination selected) ni t ismp + 200 ns n = 0 to 7 (analog noise elimination) 600 ns intpn low-level width t witl <92> n = 3 (when digital noise elimination selected) ni t ismp + 200 ns v dd = 4.0 to 5.5 v t + 50 ns adtrg high-level width t wadh <93> v dd = 2.7 to 5.5 v t + 100 ns v dd = 4.0 to 5.5 v t + 50 ns adtrg low-level width t wadl <94> v dd = 2.7 to 5.5 v t + 100 ns remarks 1. ni: number of samplings set with the nfc.nfsts bit t ismp : digital noise elimination sa mpling clock cycle of intp3 pin t: a/d base clock cycle (f ad ) 2. the above specification shows the pulse width that is accurately detected as a valid edge. if a pulse narrower than the above specification is input, theref ore, it may also be detected as a valid edge.
chapter 23 electrical specifications user?s manual u17705ej2v0ud 635 reset/interrupt <88> <87> v dd reset (input) nmi (input) intpn (input) adtrg (input) <89>/<91>/<93> <90>/<92>/<94> remark n = 0 to 7
chapter 23 electrical specifications user?s manual u17705ej2v0ud 636 timer timing ( t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf ) parameter symbol conditions min. max. unit v dd = 4.5 to 5.5 v 2t smp0 + 100 note 1 ns ti01 high-level width t ti0h <95> v dd = 2.7 to 5.5 v 2t smp0 + 200 note 1 ns v dd = 4.5 to 5.5 v 2t smp0 + 100 note 1 ns ti01 low-level width t ti0l <96> v dd = 2.7 to 5.5 v 2t smp0 + 200 note 1 ns v dd = 4.5 to 5.5 v 50 ns ti5m high-level width t ti5h <97> v dd = 2.7 to 5.5 v 100 ns v dd = 4.5 to 5.5 v 50 ns ti5m low-level width t ti5l <98> v dd = 2.7 to 5.5 v 100 ns v dd = 4.5 to 5.5 v np t smpp + 100 note 2 ns tip0m high-level width t tiph <99> v dd = 2.7 to 5.5 v np t smpp + 200 note 2 ns v dd = 4.5 to 5.5 v np t smpp + 100 note 2 ns tip0m low-level width t tipl <100> v dd = 2.7 to 5.5 v np t smpp + 200 note 2 ns notes 1. t smp0 : timer 0 count clock cycle however, t smp0 = 4/f xx when ti0n is used as an external event count input. 2. np: number of sampling clocks set by the pmnfc.pmnfsts bit t smpp : digital noise elimination sa mpling clock cycle of tip0m pin if tip00 is used as an external event count input or an external trigger input, however, t smpp = 0 (digital noise is not eliminated). remarks 1. m = 0, 1 2. the above specification shows the pul se width that is accurately detected as a valid edge. if a pulse narrower than the above specification is input, theref ore, it may also be detected as a valid edge. timer input timing ti01 (input) ti5m (input) tip0m (input) <95>/<97>/<99> <96>/<98>/<100> remark m = 0, 1
chapter 23 electrical specifications user?s manual u17705ej2v0ud 637 uart timing (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate 312.5 kbps v dd = 4.5 to 5.5 v 12 mhz asck0 frequency v dd = 2.7 to 5.5 v 6 mhz
chapter 23 electrical specifications user?s manual u17705ej2v0ud 638 csi0 timing (1) master mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit v dd = 4.0 to 5.5 v 200 ns sck0n cycle time t kcy1 <101> v dd = 2.7 to 5.5 v 400 ns sck0n high-/low-level width t kh1 , t kl1 <102> t kcy1 /2 ? 30 ns v dd = 4.0 to 5.5 v 30 ns si0n setup time (to sck0n) t sik1 <103> v dd = 2.7 to 5.5 v 50 ns v dd = 4.0 to 5.5 v 30 ns si0n hold time (from sck0n) t ksi1 <104> v dd = 2.7 to 5.5 v 50 ns v dd = 4.0 to 5.5 v 30 ns delay time from sck0n to so0n output t kso1 <105> v dd = 2.7 to 5.5 v 60 ns remark n = 0, 1 (2) slave mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit v dd = 4.0 to 5.5 v 200 ns sck0n cycle time t kcy2 <101> v dd = 2.7 to 5.5 v 400 ns v dd = 4.0 to 5.5 v 45 ns sck0n high-/low-level width t kh2 , t kl2 <102> v dd = 2.7 to 5.5 v 90 ns v dd = 4.0 to 5.5 v 30 ns si0n setup time (to sck0n) t sik2 <103> v dd = 2.7 to 5.5 v 60 ns v dd = 4.0 to 5.5 v 30 ns si0n hold time (from sck0n) t ksi2 <104> v dd = 2.7 to 5.5 v 60 ns v dd = 4.0 to 5.5 v 50 ns delay time from sck0n to so0n output t kso2 <105> v dd = 2.7 to 5.5 v 100 ns remark n = 0, 1
chapter 23 electrical specifications user?s manual u17705ej2v0ud 639 (a) csicn.ckpn, dapn bits = 00 or 11 so0n (output) input data output data si0n (input) sck0n (i/o) <101> <102> <102> <103> <104> <105> hi-z hi-z (b) csicn.ckpn, dapn bits = 01 or 10 so0n (output) input data output data si0n (input) sck0n (i/o) <101> <102> <102> <103> <104> <105> hi-z hi-z remark n = 0, 1
chapter 23 electrical specifications user?s manual u17705ej2v0ud 640 i 2 c bus mode (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) normal mode high-speed mode parameter symbol min. max. min. max. unit scl0 clock frequency f clk 0 100 0 400 khz bus free time (between start and stop conditions) t buf <111> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <112> 4.0 ? 0.6 ? s scl0 clock low-level width t low <113> 4.7 ? 1.3 ? s scl0 clock high-level width t high <114> 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta <115> 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <116> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <117> 250 ? 100 note 4 ? ns sda0 and scl0 signal rise time t r <118> ? 1000 20 + 0.1cb note 5 300 ns sda0 and scl0 signal fall time t f <119> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <120> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <121> ? ? 0 50 ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda0 signal (at v ihmin. of scl0 signal) in order to occupy the undef ined area at the falling edge of scl0. 3. if the system does not extend the scl0 signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high- speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl0 signal?s low state hold time: t su : dat 250 ns ? if the system extends the scl0 signal?s low state hold time: transmit the following data bit to the sda0 line prior to the scl0 line release (t rmax. + t su:dat = 1000 + 250 = 1250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf)
chapter 23 electrical specifications user?s manual u17705ej2v0ud 641 i 2 c bus mode stop condition start condition restart condition stop condition scl0 (i/o) sda0 (i/o) <113> <119> <119> <118> <118> <116> <117> <115> <112> <111> <112> <121> <120> <114>
chapter 23 electrical specifications user?s manual u17705ej2v0ud 642 a/d converter (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 av ref0 5.5 v 0.2 0.4 %fsr overall error note 1 ainl 2.7 av ref0 4.0 v 0.3 0.6 %fsr high-speed mode 3.0 100 s 4.5 av ref0 5.5 v normal mode 14.0 100 s high-speed mode 4.8 100 s 4.0 av ref0 4.5 v normal mode 14.0 100 s high-speed mode 6.0 100 s 2.85 av ref0 4.0 v normal mode 17.0 100 s high-speed mode 14.0 100 s conversion time t conv 2.7 av ref0 2.85 v normal mode 17.0 100 s 4.0 av ref0 5.5 v 0.4 %fsr zero-scale error note 1 ezs 2.7 av ref0 4.0 v 0.6 %fsr 4.0 av ref0 5.5 v 0.4 %fsr full-scale error note 1 efs 2.7 av ref0 4.0 v 0.6 %fsr 4.0 av ref0 5.5 v 2.5 lsb non-linearity error note 2 ile 2.7 av ref0 4.0 v 4.5 lsb 4.0 av ref0 5.5 v 1.5 lsb differential linearity error note 2 dle 2.7 av ref0 4.0 v 2.0 lsb analog input voltage v ian 0 av ref0 v when using a/d converter 1.3 2.5 ma av ref0 current ia ref0 when not using a/d converter note 3 1.0 10 a notes 1. excluding quantization error ( 0.05 %fsr). 2. excluding quantization error ( 0.5 lsb). 3. adm.adcs bit = 0, adm.adcs2 bit = 0 remark lsb: least significant bit fsr: full scale range
chapter 23 electrical specifications user?s manual u17705ej2v0ud 643 flash memory programming characteristics (t a = ? 40 to +85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, v ss = ev ss = av ss = 0 v, c l = 50 pf) (1) basic characteristics parameter symbol conditions min. typ. max. unit v dd = 4.5 to 5.5 v 2 20 mhz v dd = 4.0 to 5.5 v 2 16 mhz programming operation frequency v dd = 2.7 to 5.5 v 2 10 mhz supply voltage v dd 2.7 5.5 v number of rewrites c erwr note 100 times programming temperature t prg ? 40 +85 c note when writing initially to shipped products, it is counted as one rewrite for both ?erase to write? and ?write only?. example (p: write, e: erase) shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit setup time from v dd to flmd0 t dp <122> 10 ms 3 s time from reset to flmd0 pulse input start t rp <123> 66611.2/f x s flmd0 pulse high-/low-level width t pw <124> 10 100 s flmd0 pulse rise time t r <125> 50 ns flmd0 pulse fall time t f <126> 50 ns serial write operation timing v dd flmd0 flmd1 0 v <122> <124> <124> <123> reset <126> <125>
user?s manual u17705ej2v0ud 644 chapter 24 package drawing m 48 32 33 64 1 17 16 49 s n s j detail of lead end r k m i s l t p q g f h 64-pin plastic lqfp (10x10) item millimeters a b d g 12.0 0.2 10.0 0.2 1.25 12.0 0.2 h 0.22 0.05 c 10.0 0.2 f 1.25 i j k 0.08 0.5 (t.p.) 1.0 0.2 l 0.5 p 1.4 q 0.1 0.05 t 0.25 s 1.5 0.10 u 0.6 0.15 s64gb-50-8eu-2 r3 + 4 ? 3 n 0.08 m 0.17 + 0.03 ? 0.07 a b cd u note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition.
user?s manual u17705ej2v0ud 645 chapter 25 recommended soldering conditions the v850es/ke2 should be soldered and mounted under the following recommended conditions. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 25-1. surface mounting type solderi ng conditions pd70f3726gb-8eu-a: 64-pin plastic lqfp (fine pitch) (10 10) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ir60-207-3 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). remarks 1. products with -a at the end of the part number are lead-free products. 2. for soldering methods and conditions other t han those recommended above, please contact an nec electronics sales representative.
user?s manual u17705ej2v0ud 646 appendix a development tools the following development t ools are available for the development of systems that employ the v850es/ke2. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, pr oducts supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computer s, refer to the explanation for ibm pc/at compatibles. ? windows tm unless otherwise specified, ?windows? means the following oss. ? windows 98, 2000 ? windows me ? windows xp ? windows nt tm ver. 4.0
appendix a development tools user?s manual u17705ej2v0ud 647 figure a-1. development tool configuration flash memory write environment debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter note 2 in-circuit emulator (qb-v850eskx1h) note 5 ? project manager (windows only) note 1 software package conversion socket or conversion adapter target system control software embedded software ? real-time os ? network library ? file system on-chip debug emulator (qb-v850mini) note 3 (qb-mini2) note 4 debug adapter note 6 (qb-v850eskx1h-da) flash memory write adapter flash programmer flash memory language processing software ? c compiler package ? device file notes 1. project manager pm+ is included in the c compiler package. pm+ is only used in windows. 2. the qb-v850mini, qb-mini2, and qb-v850 eskx1h support the usb interface only. 3. the qb-v850mini is supplied with the id850qb, usb interface cable, ocd c able, self-check board, kel adapter, and kel connector. all other products are optional. 4. the qb-mini2 is supplied with usb interface cable, 16-pin target cable, 10- pin target cable, and 78k0-ocd board (integrated debugger is not s upplied.) all other products are optional. 5. the qb-v850eskx1h is supplied with the id850qb, flash memory programmer pg-fpl, power supply unit, and usb interface adapter. all other products are optional. 6. required only when minicu be (qb-v850mini) is used.
appendix a development tools user?s manual u17705ej2v0ud 648 a.1 software package development tools (software) commonly used with v850 microcontrollers are included this package. sp850 software package for v850 microcontrollers part number: s sp850 remark in the part number differs depending on the host machine and os used. s sp850 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this compiler converts programs written in c into object codes executable with a microcontroller. this compiler is started from project manager pm+. ca850 c compiler package part number: s ca703000 df703734 device file this file contains information peculiar to the device. this device file should be used in combinat ion with a tool (ca850, sm+ for v850es/kx2, or id850qb). the corresponding os and host machine di ffer depending on the tool to be used. remark in the part number differs depending on the host machine and os used. s ca703000 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) cd-rom a.3 control software pm+ project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from pm+. pm+ is included in c compiler package ca850. it can only be used in windows.
appendix a development tools user?s manual u17705ej2v0ud 649 a.4 debugging tools (hardware) a.4.1 when using iecube ? qb-v850eskx1h the system configuration when conn ecting the qb-v850eskx1h to the host machine (pc-9821 series, pc/at compatible) is shown below. even if optional prod ucts are not prepared, connection is possible. figure a-2. system configuration (when using qb-v850eskx1h) (1/2) <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> <12> <13> : optional products <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> <12> <13> : optional products <1> host machine (pc-9821 series, ibm-pc/at compatibles) <2> debugger, usb driver, manuals, etc. (id850qb disk, accessory disk note 1 ) <3> usb interface cable <4> ac adapter <5> in-circuit emulator (qb-v850eskx1h) <6> coaxial type extension pr obe (qb-144-ep-01s) (optional) <7> flexible type extension probe note 2 (qb-144-ep-02s) (optional) <8> exchange adapter note 3 (qb-64-ea-01s) <9> check pin adapter note 4 (qb-64-ca-01s) (optional) <10> space adapter note 4 (qb-64-sa-01s) (optional) <11> mount adapter (qb- 64gb-ma-01s) (optional) <12> target connector note 3 (qb-64gb-tc-01s) <13> target system
appendix a development tools user?s manual u17705ej2v0ud 650 figure a-2. system configuration (when using qb-v850eskx1h) (2/2) notes 1. download the device file from the nec electronics website. http://www.necel.com/micro/ods/eng/index.html 2. under development 3. supplied with the device depending on the ordering number. ? when qb-v850eskx1h-zzz is ordered the exchange adapter and the ta rget connector are not supplied. ? when qb-v850eskx1h-s64gb is ordered the qb-64gb-ea-01s and qb -64gb-tc-01s are supplied. 4. when using both <9> and <10>, the order between <9> and <10> is not cared. <5> qb-v850eskx1h note in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using the v850es/ke2. it supports integrated debugger id850qb. this emulator should be used in combination with a power supply unit and emulation probe. use the usb interface ca ble to connect this emulator to the host machine. <3> usb interface cable cable to connect the host machine and the qb-v850eskx1h. <4> ac adapter 100 to 240 v can be supported by replacing the ac plug. <8> qb-64-ea-01s exchange adapter adapter to perform pin conversion. <9> qb-64-ca-01s check pin adapter adapter used in waveform monitoring using the oscilloscope, etc. <10> qb-64-sa-01s space adapter adapter to adjust the height. <11> qb-64gb-ma-01s mount adapter adapter to mount the v850es/ke2 with socket. <12> qb-64gb-tc-01s target connector connector to solder on the target system. note the qb-v850eskx1h is supplied with a power supply unit, usb interface cable, and flash memory programmer pg-fpl. it is also supplied with in tegrated debugger id850qb as control software. remark the numbers in the angle brackets correspond to the numbers in figure a-2.
appendix a development tools user?s manual u17705ej2v0ud 651 a.4.2 when using minicube qb-v850mini (1) debug emulation using minicube and qb-v850eskx1h-da the system configuration when connecting minicube and debug adapter qb-v850eskx1h-da to the host machine (pc-9821 series, pc/at compatible) is shown belo w. even if optional products are not prepared, connection is possible. figure a-3. system configuration using qb -v850eskx1h-da (when using optional products) <6> <7> <8> <9> <10> <12> : optional products <12> v850es/ke2 <11> target system <1> <4> <3> <2> s t a t u s t a r g e t p o w e r <5>
appendix a development tools user?s manual u17705ej2v0ud 652 figure a-4. system configuration using qb -v850eskx1h-da (when using optional products) <6> <9> <11> target system <1> <4> <3> <2> s t a t u s t a r g e t p o w e r <5> <1> host machine pc with usb ports <2> cd-rom note contents such as integrated debugger id8 50qb, n-wire checker, device driver, and documents are included in cd-rom. it is supplied with minicube. <3> usb interface cable usb cable to connect the host machine and minicube. it is supplied with minicube. the cable length is approximately 2 m. <4> minicube on-chip debug emulator this on-chip debug emulator serves to debug hardware and software when developing application systems using the v850es/ke2. it supports integrated debugger id850qb. <5> ocd cable cable to connect minicube and the target system. it is supplied with minicube. the cable length is approximately 20 cm. <6> qb-v850eskx1h-da debug adapter this operates as an in-circuit emulator by using in combination with minicube. it is supplied with minicube. <7> qb-64-ca-01s (optional) check pin adapter adapter used in waveform monitoring using the oscilloscope, etc. <8> qb-144-ep-01s (optional) coaxial type extension probe probe to connect the qb-v850eskx1h-da and the exchange adapter. the cable length is approximately 40 cm. <9> qb-64-ea-01s exchange adapter adapter to perform pin conversion. <10> qb-64-sa-01s (optional) space adapter adapter to adjust the height. <11> qb-64gb-tc-01s target connector connector to solder on the target system. <12> qb-64gb-ma-01s (optional) mount adapter adapter to mount the v850es/ke2 with socket. note download the device file from the nec electronics website. http://www.necel.com/micro/ods/eng/index.html remark the numbers in the angle brackets corresp ond to the numbers in figures a-3 and a-4.
appendix a development tools user?s manual u17705ej2v0ud 653 a.4.3 when using minicube2 qb-mini2 the system configuration when con necting minicube2 to the host machine (pc-9821 series, pc/at compatible) is shown below. figure a-5. system configuration of on-chip emulation system <6> <5> target system v850es/ke2 <1> <2> software <4> <3> m in icu be 2 <1> host machine pc with usb ports <2> software the integrated debugger id850qb, device file, etc. download the device file from the nec electronics website. http://www.necel.com/micro/ods/eng/ <3> usb interface cable usb cable to connect the host machine and minicube2. it is supplied with minicube2. the cable length is approximately 2 m. <4> minicube2 on-chip debug emulator this on-chip debug emulator serves to debug hardware and software when developing application systems using the v850es/ke2. it supports integrated debugger id850qb. <5> 16-pin target cable cable to connect minicube2 and the target system. it is supplied with minicube2. the cable length is approximately 15 cm. <6> target connector (sold separat ely) use a 16-pin general-purpose connector with 2.54 mm pitch. remark the numbers in the angular brackets co rrespond to the numbers in figure a-5.
appendix a development tools user?s manual u17705ej2v0ud 654 a.5 debugging tools (software) this simulator is used with v850 microc ontrollers. sm+ for v850es/kx2 is windows- based software. debugging of c source and assembler files is possible during simulation of the target system operation on the host machine. by using sm+ for v850es/kx2, logic veri fication and performance verification of applications can be performed independently fr om hardware development. therefore, development efficiency and software quality can be improved. it should be used in combination with the device file. sm+ for v850es/kx2 system simulator (under development) part number: s sm703734-b this debugger supports the in-circuit emulat ors for v850 microcontrollers. the id850qb is windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memo ry display with the trace result. it should be used in combination with the device file. id850qb integrated debugger part number: s id703000-qb (id850qb) remark in the part number differs depending on the host machine and os used. s id703000-qb host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom
appendix a development tools user?s manual u17705ej2v0ud 655 a.6 embedded software the rx850 and rx850 pro are real-time oss conforming to itron 3.0 specifications. a tool (configurator) for generating multiple information tables is supplied. rx850 pro has more functions than the rx850. rx850, rx850 pro real-time os part number: s rx703000- ??? (rx850) s rx703100- ??? (rx850 pro) applilet note this is a driver configurator that auto matically generates sample programs for the v850es/ke2. rx-fs850 (file system) this is a fat file system function. it is a file system that supports the cd-rom file system function. this file system is used with the real-time os rx850 pro. note for how to obtain applilet, consult an nec electronics sales representative. caution to purchase the rx850 or rx850 pro, first f ill in the purchase application form and sign the license agreement. remark and ??? in the part number differ depending on the host machine and os used. s rx703000- ??? s rx703100- ??? ??? product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k 0.1 million units 001m 1 million units 010m mass-production object 10 million units s01 source program object source program for mass production host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation solaris (rel. 2.5.1) cd-rom a.7 flash memory writing tools flashpro iv (part number: pg-fp4) flash programmer flash programmer dedicated to microcont rollers with on-chip flash memory. qb-mini2 (minicube2) on-chip debug em ulator with programming function. fa-64gb-8eu-a flash memory writing adapter flash memory writing adapter used connected to the flashpro iv, etc. (not wired). fa-70f3726gb-8eu-mx flash memory writing adapter flash memory writing adapter used connected to the flashpro iv, etc. (already wired). remark fa-64gb-8eu-a and fa-70f3726gb-8e u-mx are products of naito de nsei machida mfg. co., ltd. tel: +81-42-750-4172
user?s manual u17705ej2v0ud 656 appendix b instruction set list b.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the re mainders of division result s and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the condition codes sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list
appendix b instruction set list user?s manual u17705ej2v0ud 657 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword halfword (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency).
appendix b instruction set list user?s manual u17705ej2v0ud 658 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition code (cccc) condition formula explanation 0 0 0 0 ov = 1 overflow 1 0 0 0 ov = 0 no overflow 0 0 0 1 cy = 1 carry lower (less than) 1 0 0 1 cy = 0 no carry not lower (greater than or equal) 0 0 1 0 z = 1 zero 1 0 1 0 z = 0 not zero 0 0 1 1 (cy or z) = 1 not higher (less than or equal) 1 0 1 1 (cy or z) = 0 higher (greater than) 0 1 0 0 s = 1 negative 1 1 0 0 s = 0 positive 0 1 0 1 ? always (unconditional) 1 1 0 1 sat = 1 saturated 0 1 1 0 (s xor ov) = 1 less than signed 1 1 1 0 (s xor ov) = 0 greater than or equal signed 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed 1 1 1 1 ((s xor ov) or z) = 0 greater than signed
appendix b instruction set list user?s manual u17705ej2v0ud 659 b.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 r r r r r 0 1 0 010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 4 4 4 bit#3,disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 r r r r r 1 1 1 111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 r r r r r 0 1 0 011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 3 3 3 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 3 3 3 r r r r r
appendix b instruction set list user?s manual u17705ej2v0ud 660 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (restored pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 3 3 3 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 2 2 2 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11
appendix b instruction set list user?s manual u17705ej2v0ud 661 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 r r r r r 0 1 0 000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 4 5 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 r r r r r 0 1 0 111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 4 5 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3
appendix b instruction set list user?s manual u17705ej2v0ud 662 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) sp sp+4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend (imm5) ep sp/imm n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 3 3 3 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5)) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16)) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1
appendix b instruction set list user?s manual u17705ej2v0ud 663 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], halfword) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1
appendix b instruction set list user?s manual u17705ej2v0ud 664 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,halfword)) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 3 3 3 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the total number of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states).
appendix b instruction set list user?s manual u17705ej2v0ud 665 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8.
user?s manual u17705ej2v0ud 666 appendix c register index (1/6) symbol name unit page adcr a/d conversion result register adc 367 adcrh a/d conversion result register h adc 367 adic interrupt control register intc 535 adm a/d converter mode register adc 362 ads analog input channel specification register adc 366 asif0 asynchronous serial interface tr ansmit status register 0 uart 393 asif1 asynchronous serial interface tr ansmit status register 1 uart 393 asim0 asynchronous serial interface mode register 0 uart 390 asim1 asynchronous serial interface mode register 1 uart 390 asis0 asynchronous serial interface status register 0 uart 392 asis1 asynchronous serial interface status register 1 uart 392 brgc0 baud rate generator control register 0 uart 411 brgc1 baud rate generator control register 1 uart 411 brgic interrupt control register intc 535 cksr0 clock select register 0 uart 410 cksr1 clock select register 1 uart 410 cmp00 8-bit timer h compare register 00 tmh 308 cmp01 8-bit timer h compare register 01 tmh 309 cmp10 8-bit timer h compare register 10 tmh 308 cmp11 8-bit timer h compare register 11 tmh 309 cr010 16-bit timer capture/compare register 010 tm0 220 cr011 16-bit timer capture/compare register 011 tm0 221 cr5 16-bit timer compare register 5 tm5 290 cr50 8-bit timer compare register 50 tm5 290 cr51 8-bit timer compare register 51 tm5 290 crc01 capture/compare control register 01 tm0 226 csi0ic0 interrupt control register intc 535 csi0ic1 interrupt control register intc 535 csic0 clocked serial interface cl ock selection register 0 csi0 423 csic1 clocked serial interface cl ock selection register 1 csi0 423 csim00 clocked serial interfac e mode register 00 csi0 421 csim01 clocked serial interfac e mode register 01 csi0 421 ctbp callt base pointer cpu 42 ctpc callt execution status saving register cpu 41 ctpsw callt execution status saving register cpu 41 dbpc exception/debug trap status saving register cpu 42 dbpsw exception/debug trap status saving register cpu 42 ecr interrupt source register cpu 39 eipc interrupt status saving register cpu 38 eipsw interrupt status saving register cpu 38
appendix c register index user?s manual u17705ej2v0ud 667 (2/6) symbol name unit page fepc nmi status saving register cpu 39 fepsw nmi status saving register cpu 39 iic0 iic shift register 0 i 2 c 462 iicc0 iic control register 0 i 2 c 449 iiccl0 iic clock selection register 0 i 2 c 459 iicf0 iic flag register 0 i 2 c 457 iicic0 interrupt control register intc 535 iics0 iic status register 0 i 2 c 454 iicx0 iic function expansion register 0 i 2 c 460 imr0 interrupt mask register 0 intc 537 imr0h interrupt mask register 0h intc 537 imr0l interrupt mask register 0l intc 537 imr1 interrupt mask register 1 intc 537 imr1h interrupt mask register 1h intc 537 imr1l interrupt mask register 1l intc 537 imr3 interrupt mask register 3 intc 537 imr3l interrupt mask register 3l intc 537 intf0 external interrupt falling edge specification register 0 intc 544 intf3 external interrupt falling edge specification register 3 intc 545 intf9h external interrupt falling edge specification register 9h intc 546 intr0 external interrupt rising edge specification register 0 intc 544 intr3 external interrupt rising edge specification register 3 intc 545 intr9h external interrupt rising edge specification register 9h intc 546 ispr in-service priority register intc 538 kric interrupt control register intc 535 krm key return mode register kr 559 nfc digital noise elimination control register intc 542 osts oscillation stabilization time selection register standby 565 p0 port 0 register port 72 p0nfc tip00 noise elimination control register tmp 215 p1nfc tip01 noise elimination control register tmp 215 p3 port 3 register port 75 p3h port 3 register h port 75 p3l port 3 register l port 75 p4 port 4 register port 80 p5 port 5 register port 82 p7 port 7 register port 85 p9 port 9 register port 87 p9h port 9 register h port 87 p9l port 9 register l port 87 pc program counter cpu 36 pcc processor clock control register cg 123 pcm port cm register port 92
appendix c register index user?s manual u17705ej2v0ud 668 (3/6) symbol name unit page pdl port dl register port 95 pf3h port 3 function register h port 77 pf4 port 4 function register port 81 pf9h port 9 function register h port 89 pfc3 port 3 function control register port 77 pfc5 port 5 function control register port 84 pfc9 port 9 function control register port 90 pfc9h port 9 function control register h port 90 pfc9l port 9 function control register l port 90 pfce3 port 3 function control expansion register port 77 pfm power fail comparison mode register adc 369 pft power fail comparison threshold register adc 369 pic0 interrupt control register intc 535 pic1 interrupt control register intc 535 pic2 interrupt control register intc 535 pic3 interrupt control register intc 535 pic4 interrupt control register intc 535 pic5 interrupt control register intc 535 pic6 interrupt control register intc 535 pic7 interrupt control register intc 535 pllctl pll control register cg 128, 358 pm0 port 0 mode register port 72 pm3 port 3 mode register port 75 pm3h port 3 mode register h port 75 pm3l port 3 mode register l port 75 pm4 port 4 mode register port 80 pm5 port 5 mode register port 82 pm9 port 9 mode register port 87 pm9h port 9 mode register h port 87 pm9l port 9 mode register l port 87 pmc0 port 0 mode control register port 73 pmc3 port 3 mode control register port 76 pmc3h port 3 mode control register h port 76 pmc3l port 3 mode control register l port 76 pmc4 port 4 mode control register port 81 pmc5 port 5 mode control register port 83 pmc9 port 9 mode control register port 88 pmc9h port 9 mode control register h port 88 pmc9l port 9 mode control register l port 88 pmccm port cm mode control register port 92 pmcm port cm mode register port 92 pmdl port dl mode register port 95 prcmd command register cpu 59
appendix c register index user?s manual u17705ej2v0ud 669 (4/6) symbol name unit page prm01 prescaler mode register 01 tm0 229 prscm interval timer brg compare register cg 333 prsm interval timer brg mode register cg 332 psc power save control register standby 563 psmr power save mode register standby 564 psw program status word cpu 40 pu0 pull-up resistor option register 0 port 73 pu3 pull-up resistor option register 3 port 79 pu4 pull-up resistor option register 4 port 81 pu5 pull-up resistor option register 5 port 84 pu9 pull-up resistor option register 9 port 91 pu9h pull-up resistor option register 9h port 91 pu9l pull-up resistor option register 9l port 91 pucm pull-up resistor option register cm port 93 pudl pull-up resistor option register dl port 95 r0 to r31 general-purpose registers cpu 36 rtbh0 real-time output buffer register h0 rtp 352 rtbl0 real-time output buffer register l0 rtp 352 rtpc0 real-time output port control register 0 rtp 354 rtpm0 real-time output port mode register 0 rtp 353 rxb0 receive buffer register 0 uart 394 rxb1 receive buffer register 1 uart 394 selcnt1 selector operation control register 1 tm0 230 sio00 serial i/o shift register 0 csi0 428 sio00l serial i/o shift register 0l csi0 428 sio01 serial i/o shift register 1 csi0 428 sio01l serial i/o shift register 1l csi0 428 sirb0 clocked serial interface re ceive buffer register 0 csi0 424 sirb0l clocked serial interface re ceive buffer register 0l csi0 424 sirb1 clocked serial interface re ceive buffer register 1 csi0 424 sirb1l clocked serial interface re ceive buffer register 1l csi0 424 sirbe0 clocked serial interface read- only receive buffer register 0 csi0 425 sirbe0l clocked serial interface read- only receive buffer register 0l csi0 425 sirbe1 clocked serial interface read- only receive buffer register 1 csi0 425 sirbe1l clocked serial interface read- only receive buffer register 1l csi0 425 sotb0 clocked serial interface tr ansmit buffer register 0 csi0 426 sotb0l clocked serial interface tr ansmit buffer register 0l csi0 426 sotb1 clocked serial interface tr ansmit buffer register 1 csi0 426 sotb1l clocked serial interface tr ansmit buffer register 1l csi0 426 sotbf0 clocked serial interface init ial transmit buffer register 0 csi0 427 sotbf0l clocked serial interface init ial transmit buffer register 0l csi0 427 sotbf1 clocked serial interface init ial transmit buffer register 1 csi0 427 sotbf1l clocked serial interface init ial transmit buffer register 1l csi0 427
appendix c register index user?s manual u17705ej2v0ud 670 (5/6) symbol name unit page sreic0 interrupt control register intc 535 sreic1 interrupt control register intc 535 sric0 interrupt control register intc 535 sric1 interrupt control register intc 535 stic0 interrupt control register intc 535 stic1 interrupt control register intc 535 sva0 slave address register 0 i 2 c 462 sys system status register cpu 59 tcl50 timer clock selection register 50 tm5 291 tcl51 timer clock selection register 51 tm5 291 tm01 16-bit timer counter 01 tm0 220 tm0ic10 interrupt control register intc 535 tm0ic11 interrupt control register intc 535 tm5 16-bit timer counter 5 tm5 289 tm50 8-bit timer counter 50 tm5 289 tm51 8-bit timer counter 51 tm5 289 tm5ic0 interrupt control register intc 535 tm5ic1 interrupt control register intc 535 tmc01 16-bit timer mode control register 01 tm0 224 tmc50 8-bit timer mode control register 50 tm5 292 tmc51 8-bit timer mode control register 51 tm5 292 tmcyc0 8-bit timer h carrier control register 0 tmh 313 tmcyc1 8-bit timer h carrier control register 1 tmh 313 tmhic0 interrupt control register intc 535 tmhic1 interrupt control register intc 535 tmhmd0 8-bit timer h mode register 0 tmh 311 tmhmd1 8-bit timer h mode register 1 tmh 312 toc01 16-bit timer output control register 01 tm0 227 tp0ccic0 interrupt control register intc 535 tp0ccic1 interrupt control register intc 535 tp0ccr0 tmp0 capture/compare register 0 tmp 139 tp0ccr1 tmp0 capture/compare register 1 tmp 141 tp0cnt tmp0 counter read buffer register tmp 143 tp0ctl0 tmp0 control register 0 tmp 133 tp0ctl1 tmp0 control register 1 tmp 134 tp0ioc0 tmp0 i/o control register 0 tmp 135 tp0ioc1 tmp0 i/o control register 1 tmp 136 tp0ioc2 tmp0 i/o control register 2 tmp 137 tp0opt0 tmp0 option register 0 tmp 138 tp0ovic interrupt control register intc 535 txb0 transmit buffer register 0 uart 395 txb1 transmit buffer register 1 uart 395 vswc system wait control register cpu 61
appendix c register index user?s manual u17705ej2v0ud 671 (6/6) symbol name unit page wdcs watchdog timer clock se lection register wdt 343 wdt1ic interrupt control register intc 535 wdte watchdog timer enable register wdt 349 wdtm1 watchdog timer mode register 1 wdt 344, 540 wdtm2 watchdog timer mode register 2 wdt 348 wtic interrupt control register intc 535 wtiic interrupt control register intc 535 wtm watch timer operation mode register wt 336
user?s manual u17705ej2v0ud 672 appendix d list of cautions this appendix lists cautions described in this document. ?classification (hard/soft)? in table is as follows. hard: cautions for microcontroller internal/external hardware soft: cautions for software such as register settings or programs (1/27) chapter classification function details of function cautions page flmd0 connect to v ss in normal operation mode. p. 20 nc leave the nc pin open. p. 20 chapter 1 hard pin functions ev dd make ev dd the same potential as v dd . p. 20 chapter 2 hard pin functions xt1 be sure to set the psmr.xtstp bi t to 1 when this pin is not used. p. 31 eipc, eipsw, fepc, fepsw since only one set of these registers is av ailable, the contents of this register must be saved by the program when mult iple interrupt servicing is enabled. p. 37 eipc, fepc, ctpc even if bit 0 of eipc, fepc, or ctpc is se t (1) by the ldsr instruction, bit 0 is ignored during return with the reti in struction following interrupt servicing (because bit 0 of pc is fixed to 0). when setting a value to eipc, fepc, and ctpc, set an even number (bit 0 = 0). p. 37 program space no instructions can be fe tched from the 4 kb area of 03fff000h to 03ffffffh because this area is an on-chip peripheral i/o area. therefore, do not execute any branch operation instruct ions in which the destination address will reside in any part of this area. p. 45 if word access of a register is attempt ed, halfword access to the word area is performed twice, first for the lower bits , then for the higher bits, ignoring the lower 2 address bits. p. 49 if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined if the a ccess is a read operation. if a write access is performed, only the data in the lo wer 8 bits is written to the register. p. 49 on-chip peripheral i/o area addresses that are not defined as register s are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. p. 49 when switching to the idle mode or the stop mode (psc.stp bit = 1), 5 nop instructions must be inserted imm ediately after switching is performed. p. 58 interrupts are not acknowledged for the store instruction for the prcmd register. this is because continuous execution of st ore instructions by the program in steps <2> and <3> above is assumed. if another instruction is placed between steps <2> and <3>, t he above sequence may not be realized when an interrupt is acknowledged for t hat instruction, which may cause malfunction. p. 58 chapter 3 soft cpu functions setting data to special registers the data written to the prcmd register is dummy data, but use the same register as the general-purpose register used for setting data to the special register (step <3>) when writing to t he prcmd register (step <2>). the same applies to when using a general-pur pose register for addressing. p. 58
appendix d list of cautions user?s manual u17705ej2v0ud 673 (2/27) chapter classification function details of function cautions page if 0 is written to the prerr bit of the sys register that is not a special register immediately following write to the prcm d register, the prerr bit becomes 0 (write priority). p. 60 sys register if data is written to the prcmd register t hat is not a special register immediately following write to the prcmd register, the prerr bit becomes 1. p. 60 waits on register access be sure to set the following registers first when using the v850es/ke2. ? system wait control register (vswc) ? watchdog timer mode register 2 (wdtm2) p. 61 vswc register access to the on-chip peripheral i/o register lasts 3 clocks (during no wait), but in the v850es/ke2, waits are required according to the internal system clock frequency. set the values shown below to the vswc register according to the internal system clock frequency that is used. p. 61 if fetched from the internal rom or internal ram, the number of waits is as shown above. if fetched from the external memory, the number of waits may be decreased below these. the effect of the external memory access cycles varies depending on the wait settings and the like. however, the number of waits shown above is the maximum value, so no higher value is generated. p. 63 chapter 3 soft cpu functions access to special on-chip peripheral i/o register when the cpu operates on the subclock and no clock is input to the x1 pin, do not access a register in which a wait occurs. if a wait occurs, it can only be released by a reset. p. 63 pfn register the pfnm bit is valid only when the pmn. pmnm bit is 0 (output mode) regardless of the setting of the pmcn register. w hen the pmnm bit is 1 (input mode), the set value in the pfn register is invalid. p. 69 port 0 p02 to p06 have hyster esis characteristics when the alternate function is input, but not in the port mode. p. 72 hard port 3 p31 to p35, p38, and p39 have hyst eresis characteristics when the alternate function is input, but not in the port mode. p. 74 p3 register when reading from or writing to bits 8 to 15 of the p3 register in 8-bit or 1-bit units, specify these bi ts as bits 0 to 7 of the p3h register. p. 75 pm3 register when reading from or writing to bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm3h register. p. 75 when reading from or writing to bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc3h register. p. 76 pmc3 register the intp7 and rxd0 pins are alternate-f unction pins. when using the pin as the rxd0 pin, disable edge detection of the al ternate-function intp7 pin (clear the intf3.intf31 and intr3.intr31 bits to 0). when using the pin as the intp7 pin, stop the uart0 receive operation (clear the asim0.rxe0 bit to 0). p. 76 soft pf3h register when using p38 and p39 as n-ch open-drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p3n bit = 1 pf3n bit = 1 pmc3n bit = 1 p. 77 chapter 4 hard port functions specifying alternate- function pins of port 3 the asck0 and adtrg pins are alternate- function pins. when using the pin as the asck0 pin, disable the trigger input of the alternate-function adtrg pin (clear the ads.trg bit to 0 or set the ads.adtmd bit to 1). when using the pin as the adtrg pin, do not set the uart0 oper ation clock to external input (set the cksr0.tps03 to cksr0.tps00 bits to other than 1011). p. 78
appendix d list of cautions user?s manual u17705ej2v0ud 674 (3/27) chapter classification function details of function cautions page specifying alternate- function pins of port 3 when the p3n pin is specified as an al ternate function by the pmc3.pmc3n bit with the pfc3n and pfce3n bits maintaini ng the initial value (0), output becomes undefined. therefore, to specify the p3n pin as an alternate function, set the pfc3n and pfce3n bits to 1 first and then set the pmc3n bit to 1 (n = 3, 4). p. 78 port 4 p40 and p42 have hysteres is characteristics when the alternate function is input, but not in the port mode. p. 80 hard pf4 register when using p41 and p42 as n-ch open-drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p4n bit = 1 pf4n bit = 1 pmc4n bit = 1 p. 81 soft pfc5 register when the p5n pin is specified as an alternate function by the pmc5.pmc5n bit with the pfc5n bit maintaining the initial value (0), output becomes undefined. therefore, to specify the p5n pin as alte rnate function 2, set the pfc5n bit to 1 first and then set the pmc5n bit to 1 (n = 3 to 5). p. 84 hard port 9 p97, p99, and p913 to p915 have hyst eresis characteristics when the alternate function is input, but not in the port mode. p. 86 p9 register when reading from or writing to bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify these bi ts as bits 0 to 7 of the p9h register. p. 87 pm9 register when reading from or writing to bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm9h register. p. 87 pmc9 register when reading from or writing to bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc9h register. p. 88 pf9h register when using p98 and p99 as n-ch open-drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p9n bit = 11 pfc9n bit = 0/11 pf9n bit = 11 pmc9n bit = 1 p. 89 when port 9 is specified as an alternate function by the pmc9.pmc9n bit with the pfc9n bit maintaining the initial value (0), output becomes undefined. therefore, to specify port 9 as alternate function 2, set the pfc9n bit to 1 first and then set the pmc9n bit to 1 (n = 0, 1, 6 to 9, 13 to 15). p. 90 pfc9 register when reading from or writing to bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc9h register. p. 90 pu9 register when reading from or writing to bits 8 to 15 of the pu9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pu9h register. p. 91 rxd0, intp7 the intp7 and rxd0 pins are alter nate-function pins. when using the pin as the rxd0 pin, disable edge detection of the al ternate-function intp7 pin (clear the intf3.intf31 and intr3.intr31 bits to 0). when using the pin as the intp7 pin, stop the uart0 receive operation (clear the asim0.rxe0 bit to 0). p. 115 asck0, adtrg the asck0 and adtrg pins are alternate- function pins. when using the pin as the asck0 pin, disable the trigger input of the alternate-function adtrg pin (clear the ads.trg bit to 0 or set the ads.adtmd bit to 1). when using the pin as the adtrg pin, do not set the uart0 operation clock to external input (set the cksr0.tps03 to cksr0.tps00 bits to other than 1011). p. 115 soft cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be wri tten in addition to the targeted bit. therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. p. 118 chapter 4 hard port functions hysteresis characteristics in port mode, the following ports do not have hysteresis characteristics. p02 to p06 p31 to p35, p38, p39 p40, p42 p97, p99, p913 to p915 p. 119
appendix d list of cautions user?s manual u17705ej2v0ud 675 (4/27) chapter classification function details of function cautions page do not change the cpu clock (by using t he ck3 to ck0 bits) while clkout is being output. p. 124 use a bit manipulation instruction to m anipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. p. 124 when the cpu operates on the subclock and no clock is input to the x1 pin, do not access a register in which a wait occu rs (refer to 3.4.8 (2) access to special on-chip peripheral i/o register for details of the access methods). if a wait occurs, it can only be released by a reset. p. 124 when stopping the main clock, stop the pll. p. 125 pcc register if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied, then change to the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 p. 125 chapter 5 soft clock generation function pllctl register be sure to clear bits 3 to 7 to ?0?. changing bit 3 does not affect the operation. p. 128 set the tp0cks2 to tp0cks0 bits when the tp0ce bit = 0. when the value of the tp0ce bit is changed from 0 to 1, the tp0cks2 to tp0cks0 bits can be set simultaneously. p. 133 tp0ctl0 register be sure to clear bits 3 to 6 to ?0?. p. 133 the tp0est bit is valid only in the exte rnal trigger pulse output mode or one-shot pulse output mode. in any other mode, writing 1 to this bit is ignored. p. 134 external event count input is selected in the external event count mode regardless of the value of the tp0eee bit. p. 134 set the tp0eee and tp0md2 to tp0md0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) the operation is not guaranteed when rewriting is performed with the tp0ce bit = 1. if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. p. 134 tp0ctl1 register be sure to clear bits 3, 4, and 7 to ?0?. p. 134 rewrite the tp0ol1, tp0oe1, tp 0ol0, and tp0oe0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. p. 135 tp0ioc0 register even if the tp0ola bit is manipulated w hen the tp0ce and tp0oea bits are 0, the top0a pin output level varies (a = 0, 1). p. 135 rewrite the tp0is3 to tp0is0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bi t = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. p. 136 tp0ioc1 register the tp0is3 to tp0is0 bits are valid only in the free-running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible. p. 136 rewrite the tp0ees1, tp0ees0, tp0ets1, and tp0ets0 bits when the tp0ctl0.tp0ce bit = 0. (the same value can be written when the tp0ce bit = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. p. 137 the tp0ees1 and tp0ees0 bits are valid only when the tp0ctl1.tp0eee bit = 1 or when the external event count mode (tp0ctl1.tp0md2 to tp0ctl1.tp0md0 bits = 001) has been set. p. 137 chapter 6 soft 16-bit timer/ event counter p (tmp) tp0ioc2 register the tp0ets1 and tp0ets0 bits are valid only when the external trigger pulse output mode (tp0md2 to tp0md0 bits = 010) or the one-shot pulse output mode (tp0md2 to tp0md0 bits = 011) is set. p. 137
appendix d list of cautions user?s manual u17705ej2v0ud 676 (5/27) chapter classification function details of function cautions page rewrite the tp0ccs1 and tp0ccs0 bits when the tp0ce bit = 0. (the same value can be written when the tp0ce bi t = 1.) if rewriting was mistakenly performed, clear the tp0ce bit to 0 and then set the bits again. p. 138 tp0opt0 register be sure to clear bits 1 to 3, 6, and 7 to ?0?. p. 138 tp0ccr0 register accessing the tp0ccr0 register is dis abled during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). p. 139 tp0ccr1 register accessing the tp0ccr1 register is dis abled during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). p. 141 tp0cnt register accessing the tp0cnt register is dis abled during subclock operation with the main clock stopped. for details, refer to 3.4.8 (2). p. 143 to use the external event count mode, s pecify that the valid edge of the tip00 pin capture trigger input is not detect ed (by clearing the tp0ioc1.tp0is1 and tp0ioc1.tp0is0 bits to ?00?). p. 144 operation when using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tp0ctl1.tp0eee bit to 0). p. 144 tp0ctl1. tp0eee bit this bit can be set to 1 only when the interrupt request signals (inttp0cc0 and inttp0cc1) are masked by the interrupt mask flags (tp0ccmk0 and tp0ccmk1) and timer output (top01) is performed at the same time. however, set the tp0ccr0 and tp0ccr1 registers to the same value (refer to 6.5.1 (2) (d) operation of tp0ccr1 register). p. 146 in the external event count mode, do not set the tp0ccr0 and tp0ccr1 registers to 0000h. p. 159 operation timing in external event count mode in the external event count mode, use of the timer output is disabled. if performing timer output using external ev ent count input, set the interval timer mode, and select the operation enabled by t he external event count input for the count clock (tp0ctl1.tp0md2 to tp0ctl1.tp0md0 bits = 000, tp0ctl1.tp0eee bit = 1). p. 159 setting of registers in one- shot pulse output mode one-shot pulses are not output in the one-shot pulse output mode if the value set for the tpnccr1 register is greater than that for the tpnccr0 register. p. 178 enable starting the 16-bit counter of tmp0 (tp0ctl.tp0ce bit = 1) after the lapse of the sampling clock period number of times of sampling. p. 215 panfc register be sure to clear bits 7, 5 to 3 to ?0?. p. 215 chapter 6 soft 16-bit timer/ event counter p (tmp) capture operation when the capture operation is used and f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, or the external event counter (tp0clt1.tp0eee bit = 1) is selected as the count clock, ffffh, not 0000h, may be captured in the tp0ccrn register if the capture trigger is input immediately after the tp0ce bit is set to 1. p. 217 when the p35 pin is used as the valid edge of ti010 and the timer output function is used, set the p32 pin as the timer output pin (to01). p. 221 if clearing of the tmc013 and tmc012 bits to 00 and input of the capture trigger conflict, then the captured data is undefined. p. 221 chapter 7 soft 16-bit timer/ event counter 0 cr010 and cr011 registers to change the mode from the capture mode to the comparison mode, first clear the tmc013 and tmc012 bits to 00, and then change the setting. a value that has been once captured remains stored in the cr010 and cr011 registers unless the device is re set. if the mode has been changed to the comparison mode, be sure to set a comparison value. p. 221
appendix d list of cautions user?s manual u17705ej2v0ud 677 (6/27) chapter classification function details of function cautions page capture operation of cr010 and cr011 registers to capture the count value of the tm01 r egister to the cr010 register by using the phase reverse to that input to the ti010 pin, the interrupt request signal (inttm010) is not generated after the value has been captured. if the valid edge is detected on the ti011 pin during this operation, the capture operation is not performed but the inttm010 signal is generat ed as an external interrupt signal. to not use the external interrupt, mask the inttm010 signal. p. 223 16-bit timer/event counter 01 starts operation at the moment tmc012 and tmc013 are set to values other than 00 (operation stop mode), respectively. set tmc012 and tmc013 to 00 to stop the operation. p. 224 do not access the tmc01 register when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2). p. 224 tmc01 register be sure to clear the tmc011 bit to 0 when the to01 pin and ti010 pin are used alternately. p. 225 crc01 register to ensure that the capture operat ion is performed properly , the capture trigger requires a pulse two cycles longer than the count clock selected by the prm01 or selcnt1 register. p. 226 toc01 register caution be sure to set the toc01 register using the following procedure. <1> set the toc014 and toc011 bits to 1. <2> set only the toe01 bit to 1. <3> set either the lvs01 bit or the lvr01 bit to 1. p. 227 do not apply the following setting when setting the prm011 and prm010 bits to 11 (to specify the valid edge of the ti010 pin as a count clock). ? clear & start mode entered by the ti010 pin valid edge ? setting the ti010 pin as a capture trigger p. 229 if the operation of 16-bit timer/event counter 01 is enabled when the ti010 or ti011 pin is at high level and when the valid edge of the ti010 or ti011 pin is specified to be the rising edge or both edges, the high level of the ti010 or ti011 pin is detected as a rising edge. note this when the ti010 or ti011 pin is pulled up. however, the rising edge is not detected when the timer operation has been once stopped and is then enabled again. p. 229 prm01 register when the p35 pin is used as the valid edge of ti010 and the timer output function is used, set the p32 pin as the timer output pin (to01). p. 229 when the internal clock is selected, set so as to satisfy the following conditions: v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz p. 230 count clock setting the external clock requires a pulse longer than two cycles of the internal clock (f xx /4). p. 230 operation in clear & start mode entered by ti010 pin valid edge input do not set the count clock as the valid edge of the ti010 pin (rpm01.prm011 and rpm01.prm010 bits = 11). when the prm011 and prm010 bits = 11, the tm01 register is cleared. p. 240 ppg output operation to change the duty factor (value of t he cr011 register) during operation, see 7.5.1 rewriting cr011 register during tm01 operation. p. 265 register settings for ppg output operation set values to the cr010 and cr011 registers such that the condition 0000h cr011 < cr010 ffffh is satisfied. p. 266 chapter 7 soft 16-bit timer/ event counter 0 one-shot pulse output operation do not input the trigger again (setting o spt01 to 1 or detecting the valid edge of the ti010 pin) while the one-shot pulse is output. to output the one-shot pulse again, generate the trigger after the current one-shot pulse output has completed. p. 268
appendix d list of cautions user?s manual u17705ej2v0ud 678 (7/27) chapter classification function details of function cautions page lvs01 and lvr01 bits be sure to set the lvs01 and lvr01 bits following steps <1>, <2>, and <3> above. step <2> can be performed after <1> and before <3>. p. 282 to perform the one-shot pulse output with detecting the valid edge of the ti010 pin as a trigger, use the output of the to01 pin that functions alternately as p32. when using the output of the to01 pin that functions alternately as p35, the ti010 pin that functions alter nately as p35 cannot be used. when using only a software trigger (setti ng (1) toc01.ospt01 bit ) as the start trigger for the one-shot pulse output, eit her of the p32 and p35 pins can be used as the to01 pin output. p. 283 soft alternate functions of ti010/to01 pins to perform the to01 pin output inversi on operation by detecting the valid edge of the ti010 pin input, use the output of the to01 pin that functions alternately as p32. when using the output of the to01 pin that functions alternately as p35, the ti010 pin that functions alternately as p35 cannot be used. therefore, the to01 pin output inversion operation by detecting the valid edge of the ti010 pin input cannot be performed. when using the to01 pi n that functions alternately as p35, clear the tmc01.tmc011 bit to 0. p. 283 hard error on starting timer an error of up to 1 clock occurs befor e the match signal is generated after the timer has been started. this is because t he count of the tm01 register is started asynchronously to the count pulse. p. 283 soft setting cr0n0 and cr0n1 registers setting cr010 and cr011 registers (in the mode in which clear & start occurs upon match between tm01 register and cr010 register) set the cr010 and cr011 registers to a value other than 0000h (when using these registers as external event c ounters, one-pulse count operation is not possible). p. 283 hard if the valid edge of the ti011/ti010 pin is input while the cr010/cr011 register is read, the cr010/cr011 register performs capture operation, but the read value at this time is not guaranteed. however, the interrupt request signal (inttm010/inttm011) is generated as a result of detection of the valid edge. p. 284 data hold timing of capture register the values of the cr010 and cr011 registers are not guaranteed after 16-bit timer/event counter 01 has stopped. p. 284 setting valid edge set the valid edge of the ti010 pin while the timer operation is stopped (tmc01.tmc013 and tmc01.tmc012 bits = 00). set the valid edge by using the prm01.es100 and prm01.es101 bits. p. 284 re-triggering one-shot pulse make sure that the trigger is not generat ed while an active level is being output in the one-shot pulse output mode. be sure to input the next trigger after the current active level is output. p. 284 the tmc01.ovf01 flag is set to 1 in the following case in addition to when the tm01 register overflows. select the mode in which clear & start occurs upon match between the tm01 register and the cr010 register. set the cr010 register to ffffh when the tm01 register is cleared from ffffh to 0000h upon match with the cr010 register p. 285 soft ovf01 flag after the tm01 register overflows, clear ing ovf01 flag is invalid and set (1) again even if the ovf01 flag is cleared (0) before the next count clock is counted (before tm01 register becomes 0001h). p. 285 chapter 7 hard 16-bit timer/ event counter 0 one-shot pulse output one-shot pulse output operat es normally in either the free-running timer mode or the mode in which clear & start occurs on the valid edge of the ti010 pin. in the mode in which clear & start occurs upon match between the tm01 register and the cr010 register, one-shot pulse output is not possible. p. 285
appendix d list of cautions user?s manual u17705ej2v0ud 679 (8/27) chapter classification function details of function cautions page if the valid edge of the ti010 pin is specif ied for the count clock, the capture register that specified the ti010 pin as the trigger does not operate normally. p. 286 to accurately capture the count value, the pulse input to the ti010 and ti011 pins as a capture trigger must be wider than two count clocks selected by the prm01 and selcnt1 registers. p. 286 hard although a capture operation is performed at the falling edge of the count clock, an interrupt request signal (inttm010, inttm011) is generated at the rising edge of the next count clock. p. 286 soft capture operation when the count value of the tm01 register is captured to the cr010 register in the phase reverse to the signal input to the ti010 pin, the interrupt signal (inttm010) is not generated after the count value is captured. if the valid edge is detected on the ti011 pin during this oper ation, the capture operation is not performed but the inttm010 signal is generat ed as an external interrupt signal. mask the inttm010 signal when the external interrupt is not used. p. 286 if the operation of the 16-bit timer/event counter 01 is enabled after reset and while the ti010 or ti011 pin is at high level and when the rising edge or both the edges are specified as the valid edge of the ti010 or ti011 pin, then the high level of the ti010 or ti011 pin is detected as the rising edge. note this when the ti010 or ti011 pin is pulled up. however, the rising edge is not detected when the operation is once stopped and then enabled again. p. 286 chapter 7 hard 16-bit timer/ event counter 0 edge detection the sampling clock for noise eliminat ion differs depending on whether the valid edge of ti010 is used for the count clock or as a capture trigger. in the former case, sampling is performed using f xx /4, and in the latter case, sampling is performed using the count clock selected by the prm01 and selcnt1 registers. when the signal input to the ti010 pin is sampled and the valid level is detected two times in a row, the valid edge is det ected. therefore, noise having a short pulse width can be eliminated. p. 286 tm5n register when connected in cascade, these registers become 0000h even when the tce50 bit in the lowest timer (tm50) is cleared. p. 289 in the mode in which clear & start occu rs upon a match of the tm5n register and cr5n register (tmc5n.tmc5n6 bit = 0), do not write a different value to the cr5n register during the count operation. p. 290 in the pwm mode, set the cr5n register rewrite interval to three or more count clocks (clock selected with the tcl5n register). p. 290 cr5n register before changing the value of the cr5n register when using a cascade connection, be sure to stop the timer operation. p. 290 when the internal clock is selected, set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz p. 291 soft tcl5n register before overwriting the tcl5n register with different data, stop the timer operation. p. 291 hard because to51 and ti51 are alternate functi ons of the same pin, only one can be used at one time. p. 293 the lvs5n and lvr5n bit settings are valid in modes other than the pwm mode. p. 293 chapter 8 soft 8-bit timer/ event counter 5 tmc5n register do not set <1> to <4> below at the same time. set as follows. <1> set the tmc5n1, tmc5n6, and tmc514 note bits: setting of operation mode <2> set the toe5n bit for timer output enable: timer output enable <3> set the lvs5n and lvr5n bits: setting of timer output f/f <4> set the tce5n bit p. 293
appendix d list of cautions user?s manual u17705ej2v0ud 680 (9/27) chapter classification function details of function cautions page operation as interval timer during interval timer operation, do not rewr ite the value of the cr5n register. p. 294 operation as external event counter during external event counter operation, do not rewrite the value of the cr5n register. p. 296 square-wave output operation do not rewrite the value of the cr5n register during square-wave output. p. 297 8-bit pwm output operation the cr5n register rewrite interval must be three or more operation clocks (set by the tcl5n register). p. 299 operation based on cr5n register transitions in the case of reload from the cr5n register between <1> and <2>, the value that is actually used differs (read value: m; actual value of cr5n register: n). p. 301 to write using 8-bit access during cascade connection, set the tce51 bit to 1 at operation start and then set the tce50 bit to 1. when operation is stopped, clear the tce50 bit to 0 and then clear the tce51 bit to 0. p. 302 during cascade connection, ti50 input, to50 output, and the inttm50 signal are used. do not use ti51 input, to51 output, and the inttm51 signal; mask them instead (for details, refer to chapter 21 interrupt/exception processing function). clear the lvs 51, lvr51, tmc511, and toe51 bits to 0. p. 302 operation as interval timer (16 bits) do not change the value of the cr5 register during timer operation. p. 302 during external event counter operation, do not rewrite the value of the cr5n register. p. 304 to write using 8-bit access during casc ade connection, set the tce51 bit to 1 and then set the tce50 bit to 1. when operat ion is stopped, clear the tce50 bit to 0 and then clear the tce51 bit to 0 (n = 0, 1). p. 304 during cascade connection, ti50 input and t he inttm50 signal are used. do not use ti51 input, to51 output, and the inttm51 signal; mask them instead (for details, refer to chapter 21 interrupt/exception processing function). clear the lvs51, lvr 51, tmc511, and toe51 bits to 0. p. 304 operation as external event counter (16 bits) do not change the value of the cr5 regi ster during external event counter operation. p. 304 square-wave output operation (16-bit resolution) do not write a different value to the cr5 register during operation. p. 305 chapter 8 soft 8-bit timer/ event counter 5 error on starting timer an error of up to 1 clock occurs befor e the match signal is generated after the timer has been started. this is bec ause the tm5n register is started asynchronously to the count pulse. p. 306 cmpn0 register rewriting the cmpn0 register dur ing timer count operation is prohibited. p. 308 cmpn1 register in the pwm output mode and carri er generator mode, be sure to set the cmpn1 register when starting the timer count operation (tmhmdn.tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the same value to the cmpn1 register). p. 309 set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz p. 311 chapter 9 soft 8-bit timer h tmhmd0 register when the tmhe0 bit = 1, setting bits other than those of the tmhmd0 register is prohibited. p. 311
appendix d list of cautions user?s manual u17705ej2v0ud 681 (10/27) chapter classification function details of function cautions page in the pwm output mode and carrier generator mode, be sure to set the cmp01 register when starting the timer count oper ation (tmhe0 bit = 1) after the timer count operation was stopped (tmhe0 bit = 0) (be sure to set again even if setting the same value to the cmp01 register). p. 311 tmhmd0 register when using the carrier generator mode, se t 8-bit timer h0 count clock frequency to six times 8-bit timer/event count er 50 count clock frequency or higher. p. 311 set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz p. 312 when the tmhe1 bit = 1, setting bits other than those of the tmhmd1 register is prohibited. p. 312 in the pwm output mode and carrier generator mode, be sure to set the cmp11 register when starting the timer count oper ation (tmhe1 bit = 1) after the timer count operation was stopped (tmhe1 bit = 0) (be sure to set again even if setting the same value to the cmp11 register). p. 312 tmhmd1 register when using the carrier generator mode, se t 8-bit timer h1 count clock frequency to six times the 8-bit timer/event c ounter 51 count clock frequency or higher. p. 312 the set value of the cmpn1 register can be changed while the timer counter is operating. however, this takes a duration of at least three operating clocks (signal selected by the ckshn2 to ckshn0 bits of the tmhmdn register) from when the value of the cmpn1 register is changed until the value is transferred to the register. p. 318 be sure to set the cmpn1 register when starting the timer count operation (tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the sa me value to the cmpn1 register). p. 318 pwm output mode operation make sure that the cmpn1 register se t value (m) and cmpn0 register set value (n) are within the following range. 00h cmpn1 (m) < cmpn0 (n) ffh p. 318 do not rewrite the nrzbn bit again until at least the second clock after it has been rewritten, or else transfer from the nrz bn bit to the nrzn bit is not guaranteed. p. 324 transfer timing when using 8-bit timer/event counter 5n in the carrier generator mode, an interrupt occurs at the timing of <1>. an interrupt occurs at a different timing when it is used in other than the carrier generator mode. p. 324 be sure to set the cmpn1 register when starting the timer count operation (tmhen bit = 1) after the timer count operation was stopped (tmhen bit = 0) (be sure to set again even if setting the sa me value to the cmpn1 register). p. 326 set the values of the cmpn0 and cmpn1 registers in the range of 01h to ffh. p. 326 in the carrier generator mode, three operating clocks (signal selected by the tmhmdn.ckshn0 to tmhmdn.ckshn2 bits) ar e required for actual transfer of the new value to the register after the cmpn1 register has been rewritten. p. 326 be sure to perform the tmcycn.rmcn bit setting before the start of the count operation. p. 326 chapter 9 soft 8-bit timer h register settings in carrier generator mode when using the carrier generator mode, set the 8-bit timer hn count clock frequency to six times the 8-bit timer/ev ent counter 5n count clock frequency or higher. p. 326
appendix d list of cautions user?s manual u17705ej2v0ud 682 (11/27) chapter classification function details of function cautions page set these bits so that the fo llowing conditions are satisfied. v dd = 4.0 to 5.5 v: f bgcs 10 mhz v dd = 2.7 to 4.0 v: f bgcs 5 mhz p. 332 do not change the values of the todis, bgcs1, and bgcs0 bits while interval timer brg is operating (bgce bit = 1). set the todis, bgcs1, and bgcs0 bits before setting (1) the bgce bit. p. 332 prsm register when the bgce bit is cleared (to 0), the 8-bit counter is cleared. p. 332 prscm register do not rewrite the prscm regi ster while interval timer brg is operating (prsm.bgce bit = 1). set the prscm r egister before setting (1) the bgce bit. p. 333 wtm register rewrite the wtm2 to wtm7 bits while both the wtm0 and wtm1 bits are 0. p. 337 soft some time is required before the first watch timer interrupt request (intwt) is generated after operation is enabled (wtm .wtm1 and wtm.wtm0 bits = 11). p. 339 hard operation as watch timer it takes 0.515625 (max.) seconds for the first intwt to be generated (2 9 1/32768 = 0.015625 (max.) seconds longer). intwt is then generated every 0.5 seconds. p. 339 when watch timer and interval timer brg operate simultaneously when using the subclock as the count clock for the watch timer, the interval time of interval timer brg can be set to any value. changing the interval time does not affect the watch timer (before c hanging the interval time, stop operation). when using the main clock as the count clo ck for the watch timer, set the interval time of interval timer brg to approximately 65.536 khz. do not change this value. p. 340 when interval timer brg and interval timer wt operate simultaneously when using the subclock as the count clo ck for interval timer wt, the interval times of interval timers brg and wt can be set to any values. they can also be changed later (before changing the value, stop operation). when using the main clock as the count cl ock for interval timer wt, the interval time of interval timer brg can be set to any value, but cannot be changed later (it can be changed only when interval timer wt stops operation). the interval time of interval timer wt can be set to 2 5 to 2 12 of the set value of interval timer brg. it can also be changed later. p. 340 when watch timer and interval timer wt operate simultaneously the interval time of interval timer wt can be set to a value between 488 s and 62.5 ms. it cannot be changed later. do not stop interval timer wt (clear (0) the wtm.wtm0 bit) while the watch timer is operating. if the wtm0 bit is set (1) after it had been cleared (0), the watch timer will have a discrepancy of up to 0.5 or 0.25 seconds. p. 340 chapter 10 soft interval timer, watch timer when watch timer, interval timer brg, and interval timer wt operate simultaneously when using the subclock as the count clock for the watch timer, the interval times of interval timers brg and wt can be set to any values. the interval time of interval timer brg can be changed later (before changing the value, stop operation). when using the main clock as the count clo ck for the watch timer, set the interval time of interval timer brg to approximately 65.536 khz. it cannot be changed later. the interval time of interval timer wt can be set to a value between 488 s and 62.5 ms. it cannot be changed later. do not stop interval timer brg (clear (0 ) the prsm.bgce bit) or interval timer wt (clear (0) the wtm.wtm0 bit) while the watch timer is operating. p. 340 when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm1 register. for details, refer to 3.4.8 (2). p. 344 once the run1 bit is set (to 1), it cannot be cleared (to 0) by software. therefore, when counting is start ed, it cannot be stopped except reset. p. 344 chapter 11 soft watchdog timer functions wdtm1 register once the wdtm13 and wdtm14 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only by reset. p. 344
appendix d list of cautions user?s manual u17705ej2v0ud 683 (12/27) chapter classification function details of function cautions page when the subclock is selected for the cp u clock, the count operation of watchdog timer 1 is stopped (the value of watchdog timer 1 is maintained). p. 345 operation as watchdog timer 1 for non-maskable interrupt servicing due to the intwdt1 signal, refer to 17.10 cautions. p. 345 once the wdtm14 bit is set to 1 (thereby selecting the watchdog timer 1 mode), the interval timer mode is not entered as long as reset is not performed. p. 346 operation as interval timer when the subclock is selected for the cp u clock, the count operation of the watchdog timer 1 stops (the value of the watchdog timer is maintained). p. 346 watchdog timer 2 automatically starts in the reset mode following reset release. when watchdog timer 2 is not used, eit her stop its operation before reset is executed through this function, or clear once watchdog timer 2 and stop it within the next interval time. also, write to the wdtm2 register for ve rification purposes only once, even if the default settings (reset mode, interval time: f xx /2 25 ) need not be changed. p. 347 watchdog timer 2 for non-maskable interrupt servicing due to a non-maskable interrupt request signal (intwdt2), refer to 17.10 cautions. p. 347 when the main clock is stopped and the cpu is operating on the subclock, do not access the wdtm2 register. for details, refer to 3.4.8 (2). p. 348 to stop the operation of watchdog timer 2, write ?1fh? to the wdtm2 register. p. 348 if the wdtm2 register is written twice afte r a reset, an overflow signal is forcibly output. p. 348 wdtm2 register to intentionally generate an overflow si gnal, write data to the wdtm2 register only twice, or write a value other than ?ach? to the wdte register only once. however, when watchdog timer 2 is set to stop operation, an overflow signal is not generated even if data is written to the wdtm2 register only twice, or a value other than ?ach? is written to the wdte register only once. p. 348 when a value other than ?ach? is writt en to the wdte register, an overflow signal is forcibly output. p. 349 when a 1-bit memory manipulation instruct ion is executed for the wdte register, an overflow signal is forcibly output. p. 349 the read value of the wdte register is always ?9ah? (value that differs from written value ?ach?). p. 349 chapter 11 soft watchdog timer functions wdte register to intentionally generate an overflow signal , write a value other than ?ach? to the wdte register only once, or write dat a to the wdtm2 register only twice. however, when watchdog timer 2 is set to stop operation, an overflow signal is not generated even if data is written to the wdtm2 register only twice, or a value other than ?ach? is written to the wdte register only once. p. 349 when writing to bits 6 and 7 of the rtbh0 register, always write 0. p. 352 rtbl0 and rtbh0 registers when the main clock is stopped and the cpu is operating on the subclock, do not access the rtbl0 and rtbh0 registers. for details, refer to 3.4.8 (2). p. 352 chapter 12 soft real-time output function (rto) operation during manipulation of rtbl0 and rtbh0 registers after setting the real-time output port, set output data to the rtbl0 and rtbh0 registers by the time a realti me output trigger is generated. p. 352
appendix d list of cautions user?s manual u17705ej2v0ud 684 (13/27) chapter classification function details of function cautions page to reflect real-time output signals (rtpout00 to rtpout05) to the pins (rtp00 to rtp05), set them to the real-time output port with the pmc5 and pfc5 registers. p. 353 by enabling real-time output operation (rtpc0.rtpoe0 bit = 1), the bits specified as real-time output enabled per form real-time output, and the bits specified as real-time output disabled output 0. p. 353 rtpm0 register if real-time output is disabled (rtpoe 0 bit = 0), real-time output signals (rtpout00 to rtpout05) all output 0, regardless of the rtpm0 register setting. p. 353 when real-time output operation is disabl ed (rtpoe0 bit = 0), real-time output signals (rtpout00 to rtpout05) all output 0. p. 354 rtpc0 register perform the settings for the byte0 and ext r0 bits only when the rtpoe0 bit = 0. p. 354 if write to the rtbh0 and rtbl0 register s is performed when the rtpoe0 bit = 0, that value is transferred to real-tim e output latches 0h and 0l, respectively. p. 356 rtpoe0 bit even if write is performed to the rtbh 0 and rtbl0 registers when the rtpoe0 bit = 1, data transfer to real-time out put latches 0h and 0l is not performed. p. 356 real-time output signals to reflect the real-time output signals (r tpout00 to rtpout05) to the pins, set the real-time output ports (rtp00 to rtp05) with the pmc5 and pfc5 registers. p. 356 conflicts prevent the followi ng conflicts by software. ? conflict between real-time output dis able/enable switching (rtpoe0 bit) and selected real-time output trigger. ? conflict between write to the rtbh0 and rtbl0 registers in the real-time output enabled status and the selected real-time output trigger. p. 356 initialization before performing initialization, disable real-time output (rtpoe0 bit = 0). p. 356 soft resetting once real-time output has been disabl ed (rtpoe0 bit = 0), be sure to initialize the rtbh0 and rtbl0 registers before enabling real-time output again (rtpoe0 bit = 0 1). p. 356 hard regardless of the port settings, p50 to p55 pins are all placed in high impedance via the intp0 pin. p. 357 security function the bits that are initialized are all the bits corresponding to p50 to p55 pins of the following registers. ? p5 register ? pm5 register ? pmc5 register ? pu5 register ? pfc5 register p. 357 before outputting a value to the real-time output ports (rtp00 to rtp05), select the intp0 pin interrupt edge detection and then set the rtost0 bit. p. 358 to set again the ports (p50 to p55 pins) as real-time output ports after placing them in high impedance via the intp0 pin, first cancel the security function. [procedure to set ports again] <1> cancel the security function and enable port setting by clearing the rtost0 bit to 0. <2> set the rtost0 bit to 1 (only if required) <3> set again as real-time output port. p. 358 chapter 12 soft real-time output function (rto) pllctl register be sure to clear bits 4 to 7 to ?0?. c hanging bit 3 does not affect the operation. p. 358
appendix d list of cautions user?s manual u17705ej2v0ud 685 (14/27) chapter classification function details of function cautions page hard a/d converter when using the a/ d converter, operate with av ref0 at the same potential as v dd and ev dd . p. 359 writing to the adm register is prohibi ted during a/d conversion operation (adcs bit = 1) in normal mode (adhs1, adhs0 bits = 00). if the same value is written to the ad m register during a/d conversion operation in high-speed mode (adhs1, adhs0 bits = 10 or 01), conversion is aborted and started again from the beginning. writing to the fr2 to fr0, adhs1, and adhs0 bits is prohibited during t he a/d conversion operation. p. 363 setting adhs1 and adhs0 bits to 11 is prohibited. p. 363 adm register do not access the adm register when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2) access to special on-chip peripheral i/o register. p. 363 if the adcs and adcs2 bits are changed from 00b to 10b, the reference voltage generator for boosting automatically turns on. if the adcs bit is cleared to 0 while the adcs2 bit is 0, the voltage generator automatically turns off. in the software trigger mode (ads.trg bit = 0), use of the first a/d conversion result is prohibited. in the hardware trigger mode (trg bit = 1) , use the a/d conversion result only if a/d conversion is started after the lapse of the oscillation stabilization time of the reference voltage generator for boosting. p. 365 setting of adcs bit and adcs2 bit if the adcs and adcs2 bits are changed from 00b to 11b, the reference voltage generator for boosting automatically turns on. if the adcs bit is cleared to 0 while the adcs2 bit is 1, the voltage generator stays on. in the software trigger mode (trg bit = 0), use of the first a/ d conversion result is prohibited. in the hardware trigger mode (trg bit = 1) , use the a/d conversion result only if a/d conversion is started after the lapse of the oscillation stabilization time of the reference voltage generator for boosting. p. 365 operation sequence 1 s (high-speed mode) or 14 s (normal mode) or more are required for the operation of the reference voltage generator for boosting between when the adcs2 bit is set (1) and when the adcs bit is set (1). p. 365 the ega1 and ega0 bits are valid only when the hardware trigger mode (trg bit = 1) and external trigger mode (adtrg pi n input: adtmd bit = 1) are selected. p. 366 the adtmd bit is valid only when the har dware trigger mode (trg bit = 1) is selected. p. 366 writing to the ads register is pr ohibited during a/d conversion operation (adm.adcs bit = 1) in normal mode (adm.adhs1, adm.adhs0 bits = 00). p. 366 inputting software/hardware triggers redundantly is prohibited during a/d conversion operation (adcs bit = 1) in normal mode (adhs1, adhs0 bits = 00). p. 366 do not access the ads register when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2) access to special on-chip peripheral i/o register. p. 366 ads register be sure to clear bit 3 to ?0?. p. 366 adcr and adcrh registers do not access the adcr and adcrh registers when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2) access to special on- chip peripheral i/o register. p. 367 writing to the pfm register is pr ohibited during a/d conversion operation (adm.adcs bit = 1) in normal mode (adm.adhs1, adm.adhs0 bits = 00). p. 369 chapter 13 soft a/d converter pfm register do not access the pfm register when the main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2 ) access to special on-chip peripheral i/o register. p. 369
appendix d list of cautions user?s manual u17705ej2v0ud 686 (15/27) chapter classification function details of function cautions page writing to the pft register is pr ohibited during a/d conversion operation (adm.adcs bit = 1) in normal mode (adm.adhs1, adm.adhs0 bits = 00). p. 369 pft register do not access the pft register when t he main clock is stopped and the subclock is operating. for details, refer to 3.4.8 (2 ) access to special on-chip peripheral i/o register. p. 369 the time taken from <1> to <3> must be 1 s (high-speed mode) or 14 s (normal mode) or longer. p. 376 steps <1> and <2> may be reversed. p. 376 step <1> may be omitted. however, if omitted, do not use the first conversion result after <3>. p. 376 when using the a/d converter for a/d conversion the time taken from <4> to <7> is differ ent from the conversion time set by the adhs1, adhs0, and fr2 to fr0 bits. the time taken for <6> and <7> is the conversion time set by the adhs1, adhs0, and fr2 to fr0 bits. p. 376 soft power consumption in standby mode the operation of the a/d converter stops in the standby mode. at this time, the power consumption can be reduced by stopping the conversion operation (the adm.adcs bit = 0) and the reference voltage generator (the adm.adcs2 bit = 0). p. 377 hard input range of ani0 to ani7 pins use the a/d converter with the ani0 to ani7 pin input voltages within the specified range. if a voltage of av ref0 or higher or av ss or lower (even if within the absolute maximum ratings) is input to these pins, the conversion value of the channel is undefined. also, this may a ffect the conversion value of other channels. p. 377 conflict between writing to the adcr r egister and reading from adcr register upon the end of conversion reading the adcr register takes precedence. after the register has been read, a new conversion result is written to the adcr register. p. 377 soft conflicting operations conflict between writing to the adcr regist er and writing to the adm register or writing to the ads register upon the end of conversion writing to the adm register or ads register takes precedence. the adcr register is not written, and neither is the conversion end interrupt request signal (intad) generated. p. 377 to keep a resolution of 10 bits, be aware of noise on the av ref0 and ani0 to ani7 pins. the higher the output im pedance of the analog input source, the greater the effect of noise. therefor e, it is recommended to connect external capacitors as shown in fi gure 13-8 to reduce noise. p. 378 measures against noise if noise of av ref0 or higher or av ss or lower could be generated, clamp with a diode with a small v f (0.3 v or lower). p. 378 ani0/p70 to ani7/p77 pins the analog input pins (ani0 to ani7) func tion alternately as input port pins (p70 to p77). when performing a/d conversion by selecti ng any of the ani0 to ani7 pins, do not execute an input instruction to port 7 during conversion. this may decrease the conversion resolution. if digital pulses are applied to the pin adjacent to the pin subject to a/d conversion, the value of the a/d conver sion may differ from the expected value because of coupling noise. therefore, do not apply pulses to the pin adjacent to the pin subject to a/d conversion. p. 378 chapter 13 hard a/d converter input impedance of av ref0 pin a series resistor string of tens of k is connected between the av ref0 pin and av ss pin. therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the av ref0 pin and av ss pin, resulting in a large reference voltage error. p. 378
appendix d list of cautions user?s manual u17705ej2v0ud 687 (16/27) chapter classification function details of function cautions page interrupt request flag (adic.adif bit) even when the ads register is changed, the adif bit is not cleared (0). therefore, if the analog input pin is c hanged during a/d conversion, the adif bit may be set (1) because a/d conversion of the previous analog input pin ends immediately before the ads register is rewri tten. in a such case, note that if the adif bit is read immediately after the ad s register has been rewritten, the adif bit is set (1) even though a/d conversion of the analog input pin after the change has not been completed. when stopping a/d conversion once and resumi ng it, clear the adif bit (0) before resuming a/d conversion. p. 379 conversion results immediately after a/d conversion start if the adm.adcs bit is set to 1 within 1 s (high-speed mode) or 14 s (normal mode) after the adm.adcs2 bit has been set to 1, or if the adcs bit is set to 1 with the adcs2 bit cleared to 0, the c onverted value immediately after the a/d conversion operation has started may not satisfy the rating. take appropriate measures such as polling the a/d conversion end interrupt request signal (intad) and discarding the first conversion result. p. 379 reading a/d conversion result register (adcr) when the adm or ads register has been written, the contents of the adcr register may become undefined. when t he conversion operation is complete, read the conversion results before writing to the adm or ads register. a correct conversion result may not be able to be read at a timing other than the above. accessing the adcr and adcrh registers is prohibited when the cpu operates with the subclock and the main clock oscillation (f x ) is stopped. for details, refer to 3.4.8 (2) access to special on-chip peripheral i/o register. p. 379 a/d converter sampling time and a/d conversion start delay time the a/d converter sampling time differs depending on the set value of the adm register. a delay time exis ts until actual sampling is started after a/d converter operation is enabled. when using a set in which the a/d conver sion time must be strictly observed, care is required for the contents shown in figure 13-10 and table 13-4. p. 380 register write response time, trigger response time each response time is the time after the wait period. for the wait function, refer to 3.4.8 (2) access to special on-chip peripheral i/o register. p. 381 variation of a/d conversion results the results of the a/d conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noi se. to reduce the variation, take counteractive measures wi th the program such as averaging the a/d conversion results. p. 382 a/d conversion result hysteresis characteristics the successive approximation type a/d c onverter holds the analog input voltage in the internal sample & hold capacitor and then performs a/d conversion. after the a/d conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur. ? when the same channel is used for a/d c onversions, if the voltage is higher or lower than the previous a/d conversion, then hysteresis characteristics may appear where the conversion result is affe cted by the previous value. thus, even if the conversion is performed at t he same potential, the result may vary. ? when switching the analog input channel , hysteresis characteristics may appear where the conversion result is affe cted by the previous channel value. this is because one a/d conv erter is used for the a/d conversions. thus, even if the conversion is performed at the same potential, the result may vary. therefore, to obtain more accurate c onversion result, perform a/d conversion twice successively for the same channel, and discard the first conversion result. p. 382 chapter 13 soft a/d converter a/d conversion operation in normal mode ? in software trigger mode: writing to the adm, ads, pfm, or pft register is prohibi ted during conversion in normal mode (adm.adhs1, adm.adhs0 bits = 00). ? in hardware trigger (external trigger/timer trigger) mode: normal mode (adhs1, adhs0 bits = 00) cannot be used. use high-speed mode (adhs1, adhs0 bits = 10 or 01). p. 382
appendix d list of cautions user?s manual u17705ej2v0ud 688 (17/27) chapter classification function details of function cautions page when using uartn, be sure to set the exte rnal pins related to uartn functions to the control made before setting the cksrn and brgcn registers, and then set the uarten bit to 1. then set the other bits. p. 390 set the uarten and rxen bits to 1 while a high level is input to the rxdn pin. if these bits are set to 1 while a low level is input to the rxdn pin, reception will be started. p. 390 asimn register when reception is disabled, the receive sh ift register does not detect a start bit. no shift-in processing or transfer proce ssing to the rxbn register is performed, and the contents of the rxbn register are retained. when reception is enabled, the receive sh ift operation starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the receive shift register are transferred to the rxbn register. a reception completion interrupt request signal (intsrn) is also generated in synchronization with the transfer to the rxbn register. p. 391 when the asimn.uarten bit or asimn.rxen bit is cleared to 0, or when the asisn register is read, the pen, fe n, and oven bits are cleared (0). p. 392 operation using a bit manipulation instruction is prohibited. p. 392 asisn register when the main clock is stopped and the cpu is operating on the subclock, do not access the asisn register. for details, refer to 3.4.8 (2). p. 392 transmission interrupt normally, when the transmit shift register becomes empty, the intstn signal is generated. however, the intstn signal is not generated if the transmit shift register becomes empty due to reset. p. 398 the values of the asif.txbf n and asif.txsfn bits change 10 11 01 in continuous transmission. therefore, do not confirm the status based on the combination of the txbfn and txsfn bits. read only the txbfn bit duri ng continuous transmission. p. 400 txbfn bit when transmission is performed continuously, write the fi rst transmit data (first byte) to the txbn register and confirm t hat the txbfn bit is 0, and then write the next transmit data (second byte ) to the txbn register. if writing to the txbn register is performed when the txbf n bit is 1, transmit data cannot be guaranteed. p. 400 the values of the asif.txbf n and asif.txsfn bits change 10 11 01 in continuous transmission. therefore, do not confirm the status based on the combination of the txbfn and txsfn bits. read only the txbfn bit duri ng continuous transmission. p. 400 when initializing the transmission uni t when continuous transmission is completed, confirm that the txsfn bit is 0 after the occurrence of the transmission completion interrupt, and then execut e initialization. if initialization is performed when the txsfn bit is 1, transmit data cannot be guaranteed. p. 400 txsfn bit while transmission is being performed conti nuously, an overrun error may occur if the next transmission is completed before t he intstn interrupt servicing following the transmission of 1 data frame is execut ed. an overrun error can be detected by embedding a program that can c ount the number of transmit data and referencing txsfn bit. p. 400 be sure to read the rxbn register even when a reception error occurs. if the rxbn register is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely. p. 405 chapter 14 soft asynchro- nous serial interface (uart) uartn reception completion interrupt timing reception is always performed a ssuming a stop bit length of 1. a second stop bit is ignored. p. 405
appendix d list of cautions user?s manual u17705ej2v0ud 689 (18/27) chapter classification function details of function cautions page set f uclk so as to satisfy the following conditions. ? v dd = 4.5 to 5.5 v: f uclk 12 mhz ? v dd = 2.7 to 4.5 v: f uclk 6 mhz p. 409 baud rate generator n (brgn) asck0 pin input can be used only by uart0. p. 409 clear the asimn.uarten bit to 0 before rewriting the tpsn3 to tpsn0 bits. p. 410 set f uclk so as to satisfy the following conditions. ? v dd = 4.5 to 5.5 v: f uclk 12 mhz ? v dd = 2.7 to 4.5 v: f uclk 6 mhz p. 410 cksrn register asck0 pin input clock can be used only by uart0. setting of uart1 and uart2 is prohibited. p. 410 brgcn register if the mdln7 to mdln0 bits are to be overwritten, the asimn.txen and asimn.rxen bits should be cleared to 0 first. p. 411 make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. p. 412 baud rate error make sure that the baud rate error during reception is within the allowable baud rate range during reception, which is described in 14.6.4 allowable baud rate range during reception. p. 412 baud rate generator setting the allowable frequency of the base clock (f uclk ) is as follows. ? v dd = 4.5 to 5.5 v: f uclk 12 mhz ? v dd = 2.7 to 4.5 v: f uclk 6 mhz p. 413 allowable baud rate range during reception the equations described below should be us ed to set the baud rate error during reception so that it always is within the allowable error range. p. 414 when the supply of clocks to uartn is stopped (for example, in idle or stop mode), operation stops with each register retaining the value it had immediately before the supply of clocks was stopped. the txdn pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. however, operation is not guaranteed after the supply of clocks is restarted. therefore, after the supply of clocks is restarted, the circuits should be initialized by clearing the asimn.uarten, asimn.rxen, and asimn.txen bits to 000. p. 416 chapter 14 soft asynchro- nous serial interface (uart) caution for uartn uartn has a 2-stage buffer configuration c onsisting of the txbn register and the transmission shift register, and has stat us flags (asifn.txbfn and asifn.txsfn bits) that indicate the status of each bu ffer. if the txbfn and txsfn bits are read in continuous transmissi on, the value changes 10 11 01. for the timing to write the next data to the txbn regi ster, read only the txbfn bit during continuous transmission. p. 416 csim0n register overwriting the csim0n.trmd n, csim0n.ccln, csim0n.dirn, csim0n.csitn, and csim0n.auton bits can be done only when the csotn bit = 0. if these bits are overwritten at any other ti me, the operation cannot be guaranteed. p. 421 the csicn register can be overwritten onl y when the csim0n.csi0en bit = 0. p. 423 csicn register set the serial clock so as to satisfy the following conditions. ? v dd = 4.0 to 5.5 v: serial clock 5 mhz ? v dd = 2.7 to 4.0 v: serial clock 2.5 mhz p. 423 read the sirbn register only when a 16-bit data length has been set (csim0n.ccln bit = 1). read the sirbnl register only when an 8-bit data length has been set (ccln bit = 0). p. 424 chapter 15 soft clocked serial interface (csi0) sirbn and sirbnl registers when the single transfer mode has been set (csim0n.auton bit = 0), perform a read operation only in the idle state (csim0n.csotn bit = 0). if the sirbn or sirbnl register is read during data transfer, the data cannot be guaranteed. p. 424
appendix d list of cautions user?s manual u17705ej2v0ud 690 (19/27) chapter classification function details of function cautions page the receive operation is not started ev en if data is read from the sirben and sirbenl registers. p. 425 sirben and sirbenl registers the sirben register can be read only if a 16-bit data length has been set (csim0n.ccln bit = 1). the sirbenl register can be read only if an 8-bit data length has been set (ccln bit = 0). p. 425 access the sotbn register only w hen a 16-bit data length has been set (csim0n.ccln bit = 1). access the sotbnl register only when an 8-bit data length has been set (ccln bit = 0). p. 426 sotbn and sotbnl registers when the single transfer mode is set (c sim0n.auton bit = 0), perform access only in the idle state (csim0n.csotn bit = 0). if the sotbn and sotbnl registers are accessed during data tr ansfer, the data cannot be guaranteed. p. 426 sotbfn and sotbfnl registers access the sotbfn register and sotb fnl register only when a 16-bit data length has been set (csim0n.ccln bit = 1), and only when an 8-bit data length has been set (ccln bit = 0), respecti vely, and only in the idle state (csim0n.csotn bit = 0). if the sotb fn and sotbfnl registers are accessed during data transfer, the data cannot be guaranteed. p. 427 sio0n and sio0nl registers read the sio0n register and sio0nl regi ster only when a 16-bit data length has been set (csim0n.ccln bit = 1), and only when an 8-bit data length has been set (ccln bit = 0), respectively, and only in t he idle state (csim0n.csotn bit = 0). if the sio0n and sio0nl registers are read during data transfer, the data cannot be guaranteed. p. 428 csim0n.csitn bit = 1 the delay mode (csim0n.csitn bit = 1) is valid only in the master mode (csicn.cks0n2 to csicn.cks0n0 bits are not 111b). the delay mode cannot be set when the slave mode is set (cks0n2 to cks0n0 bits = 111b). p. 430 csim0n.csotn bit = 1 when the csotn bit = 1, do not manipulate the csi0n register. p. 432 to continue continuous transfers , it is necessary to either read the sirbn register or write to the sotbn register dur ing the transfer reservation period. p. 441 in case of conflict between transfe r request clear and register access since transfer request clear has higher priority, t he next transfer request is ignored. therefore, transfer is inte rrupted, and normal data transfer cannot be performed. p. 441 chapter 15 soft clocked serial interface (csi0) caution for continuous transfer mode in case of conflict between transmission/ reception completion interrupt request signal (intcsi0n) generat ion and register access since continuous transfer has stopped onc e, executed as a new continuous transfer. in the slave mode, a bit phase error trans fer error results (refer to figure 15-8). in the transmission/reception mode, the value of the sotbfn register is retransmitted, and illegal data is sent. p. 442 pin setting to use the i 2 c bus function, use the p38/sda0 and p39/scl0 pins as the serial transmit/receive data i/o pin (sda0) and the serial clock i/o pin (scl0), respectively, and set them to n-ch open-drain output. p. 444 iicc0 register if the i 2 c0 operation is enabled (iice0 bit = 1) when the scl0 line is high level and the sda0 line is low level, the star t condition is detected immediately. to avoid this, after enabling the i 2 c0 operation, immediately set the lrel0 bit to 1 with a bit manipulation instruction. p. 450 chapter 16 soft i 2 c bus iicc0.spt0 bit set the spt0 bit to 1 only in master mode. however, the spt0 bit must be set to 1 and a stop condition generated before t he first stop condition is detected following the switch to operation enable status. for details, refer to 16.14 cautions. p. 453
appendix d list of cautions user?s manual u17705ej2v0ud 691 (20/27) chapter classification function details of function cautions page iicc0.spt0 bit when the iics0.trc0 bit is set to 1, the wrel0 bit is set to 1 during the ninth clock and wait is canceled, after which t he trc0 bit is cleared to 0 and the sda0 line is set to high impedance. p. 453 iics0 register when the main clock is stopped and the cpu is operating on the subclock, do not access the iics0 register. for details, refer to 3.4.8 (2). p. 454 write to the stcen0 bit only when the operation is stopped (iice0 bit = 0). p. 458 as the bus release status (iicbsy0 bit = 0) is recognized regardless of the actual bus status when the stcen0 bit = 1, when generating the first start condition (stt0 bit = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. p. 458 iicf0 register write to the iicrsv0 bit only when the operation is stopped (iice0 bit = 0). p. 458 pp. to generate a stop condition, set the wtim0 bit to 1 and change the timing of the generation of the interrupt request signal (intiic0). 473 to 475 to generate a start condition, set the wtim0 bit to 1 and change the timing of the generation of the interrupt request signal (intiic0). p. 474 i 2 c interrupt request signal clear the wtim0 bit to 0 to make the settings original. p. 474 the slave device?s intiic0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to the sva0 register. at this point, ack is generated regardless of the value set to the iicc0.acke0 bit. for a slave device that has receiv ed an extension code, the intiic0 signal occurs at the falling edge of the eighth clock. when the address does not match after restart, the intiic0 signal is generated at the falling edge of the ninth clock, but no wait occurs. p. 494 interrupt request signal (intiic0) generation timing and wait control if the received address does not match the contents of the sva0 register and extension codes have not been received, neither the intiic0 signal nor a wait occurs. p. 494 when the iicc0.wtim0 bit = 1, an interrupt request occurs at the falling edge of the ninth clock. when the wtim0 bit = 0 and the extension code?s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. p. 498 arbitration when there is a possibility that arbitration will occur, set the spie0 bit = 1 for master device operation. p. 498 when iicf0.stcen0 bit = 0 immediately after i 2 c0 operation is enabled, the bus communication status (iicf0.iicbsy0 bit = 1) is recognized regar dless of the actual bus status. to execute master communication in the st atus where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. use the following sequence for generating a stop condition. <1> set the iiccl0 register. <2> set the iicc0.iice0 bit. <3> set the iicc0.spt0 bit. p. 503 when iicf0.stcen0 bit = 1 immediately after i 2 c0 operation is enabled, the bus released status (iicbsy0 bit = 0) is recognized regardless of the actual bus status. to generate the first start condition (iicc0.stt0 bit = 1), it is nec essary to confirm that the bus has been released, so as to not di sturb other communications. p. 503 iicc0.iice0 bit is set to 1 when the iicc0.iice0 bit of the v850es/ke2 is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line. be sure to set the iicc0.iice0 bit to 1 when the scl0 and sda0 lines are high level. p. 503 chapter 16 soft i 2 c bus iicc0.iice0 bit = 1 determine the operation clock frequency by the iiccl0 and iicx0 registers before enabling the operation (iicc0.iice0 bit = 1). to change the operation clock frequency, clear the iicc0.iice0 bit to 0 once. p. 503
appendix d list of cautions user?s manual u17705ej2v0ud 692 (21/27) chapter classification function details of function cautions page iicc0.stt0 and iicc0.spt0 bits after the iicc0.stt0 and iicc0.spt0 bits have been set to 1, they must not be re-set without being cleared to 0 first. p. 503 transmission reservation if transmission has been reserved, set the iicc0.spie0 bit to 1 so that an interrupt request is generated by the det ection of a stop condition. after an interrupt request has been generated, the wait state will be released by writing communication data to i 2 c0, then transferring will begin. if an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait state because an interrupt request was not generated. however, it is not necessary to set the spie0 bit to 1 for the software to detect the iics0.msts0 bit. p. 503 master operation in single master system release the i 2 c0 bus (scl0, sda0 pins = high level) in conformity with the specifications of the product in communication. for example, when the eeprom outputs a low level to the sda0 pin, set the scl0 pin to the output port and output clock pulses from that output port until when the sda0 pin is constantly high level. p. 505 confirm that the bus release status (ii ccl0.cld0 bit = 1, iiccl0.dad0 bit = 1) has been maintained for a certain period (1 frame, for example). when the sda0 pin is constantly low level, det ermine whether to release the i 2 c0 bus (scl0, sda0 pins = high level) by referring to the specifications of the product in communication. p. 506 conform the transmission and reception form ats to the specifications of the product in communication. p. 508 when using the v850es/ke2 as the master in the multimaster system, read the iics0.msts0 bit for each intiic0 interrupt occurrence to confirm the arbitration result. p. 508 master operation in multimaster system when using the v850es/ke2 as the slave in the multimaster system, confirm the status using the iics0 and iicf0 register s for each intiic0 interrupt occurrence to determine the next processing. p. 508 pp. slave wait cancellation to cancel slave wait, write ffh to iic0 or set wrel0. 513 to 515 pp. chapter 16 soft i 2 c bus master wait cancellation to cancel master wait, write ffh to iic0 or set wrel0. 516 to 518 for non-maskable interrupt servicing fr om non-maskable interrupt request signals (intwdt1, intwdt2), refer to 17.10 cautions. p. 522 non-maskable interrupts when the ep bit and the np bit are changed by the ldsr instruction during non- maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to clear the ep bit back to 0 and set the np bit back to 1 using the ldsr instruction immediately before the reti instruction. p. 526 maskable interrupts when the ep bit and the np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to clear the ep bit back to 0 and the np bit back to 0 using the ldsr in struction immediately before the reti instruction. p. 530 multiple interrupts the values of eipc and eipsw must be saved before executing multiple interrupts. p. 532 be sure to read the xxicn.xxifn bit while interrupts are disabled (di). if the xxifn bit is read while interrupts are enabled (ei), an incorrect value may be read if there is a conflict between acknowledgment of the interrupt and reading of the bit. p. 535 chapter 17 soft interrupt/ exception processing function interrupt control register automatically reset by hardware when in terrupt request is acknowledged. p. 535
appendix d list of cautions user?s manual u17705ej2v0ud 693 (22/27) chapter classification function details of function cautions page in the device file, the xxmkn bit of the xxicn register is defined as a reserved word. therefore, if bit manipulati on is performed using the name xxmkn, the xxicn register, not the imrm register, is rewritten (as a result, the imrm register is also rewritten). p. 537 when reading from or writing to bits 8 to 15 of the imr0 and imr1 registers in 8- bit or 1-bit units, specify these bits as bits 0 to 7 of the imr0h and imr1h registers. p. 537 imr0, imr1, imr3 registers set bits 9 and 8 of the imr0 register, bi ts 15 and 8 of the imr1 register, and bits 15 to 5 and 0 of the imr3 register to 1. the operation is not guaranteed if their value is changed. p. 537 ispr register if an interrupt is acknowledged wh ile the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after the bits of the register have been set to 1 by acknowledging the interrupt may be read. to accurately read the value of the ispr register before an interrupt is acknowledged, read the register while interrupts are disabled (di status). p. 538 once the run1 bit has been set (1), it cannot be cleared (0) by software. therefore, once counting starts, it cannot be stopped except by reset. p. 540 wdtm1 register once the wdtm14 and wdtm13 bits have been set (1), they cannot be cleared (0) by software. reset is the only way to clear these bits. p. 540 intr0 and intf0 registers when switching to the port function from t he external interrupt function (alternate function), edge detection may be performed. therefore, set the port mode after setting the intf0n and intr0n bits = 00. p. 544 intr3 and intf3 registers when switching to the port function from t he external interrupt function (alternate function), edge detection may be performed. therefore, set the port mode after setting the intf31 and intr31 bits = 00. p. 545 intr9h and intf9h registers when switching to the port function from t he external interrupt function (alternate function), edge detection may be performed. therefore, set the port mode after setting the intf9n and intr9n bits = 00. p. 546 restore from software exception processing when the ep bit and the np bit are changed by the ldsr instruction during software exception processing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to set the ep bit back to 1 using the ldsr instruction immediat ely before the reti instruction. p. 548 illegal opcode it is recommended not to use an illegal opcode because instructions may newly be assigned in the future. p. 550 restore from illegal opcode dbpc and dbpsw can be accessed only during the interval between the execution of an illegal opcode and the dbret instruction. p. 551 restore from debug trap processing dbpc and dbpsw can be accessed only during the interval between the execution of the dbtrap instruction and the dbret instruction. p. 553 chapter 17 soft interrupt/ exception processin g function to generate exception in service program in a non-maskable interrupt servicing routi ne (in the time until the reti instruction is executed), maskable interrupts are not acknowledged and held pending. p. 555
appendix d list of cautions user?s manual u17705ej2v0ud 694 (23/27) chapter classification function details of function cautions page chapter 17 soft interrupt/ exception process- ing function restore from nmi design the system so that restoring by the reti instruction is as follows after a non-maskable interrupt triggered by a non-maskable interrupt request signal (intwdt1/intwdt2) is serviced. <1> generation of intwdt1/intwdt2 <2> fepc software reset processing address fepsw value to set np bit =1, ep bit = 1 reti <3> ten reti instructions (fepc and fepsw must be set) psw initial set value of psw initialization processing p. 557 hard kr0 to kr7 pins if any of the kr0 to kr7 pins is at lo w level, the intkr signal is not generated even if a falling edge is input to another pin. p. 558 chapter 18 soft key interrupt function krm register if the krm register is changed, an interrupt request signal (intkr) may be generated. to prevent this, change the kr m register after disabling interrupts (di), and then enable interrupts (ei) after clearing the interrupt request flag (kric.krif bit) to 0. p. 559 idle mode the pll does not stop. to rea lize low power consumption, stop the pll and then shift to the idle mode. p. 560 stop mode change to the clock-through mode, st op the pll, then shift to the stop mode. for details, refer to chapter 5 clock generation function. p. 560 if the nmi2m, nmi0m, or intm bit is set to 1 at the same time the stp bit is set to 1, the setting of nmi2m, nmi0m, or intm bit becomes invalid. if there is an unmasked interrupt request signal being held pending when the idle/stop mode is set, set the bit corresponding to the interrupt request signal (nmi2m, nmi0m, or intm) to 1, and then set the stp bit to 1. p. 563 psc register when the idle/stop mode is set, set the psmr.psm bit and then set the stp bit. p. 563 be sure to clear the xtstp bit to 0 during subclock resonat or connection. p. 564 be sure to clear bits 1 to 6 of the psmr register to 0. p. 564 psmr register the psm bit is valid only when the psc.stp bit is 1. p. 564 the wait time following release of the stop mode does not include the time until the clock oscillation starts (?a? in the figure below) following release of the stop mode, regardless of whether the stop mode is released by reset or the occurrence of an interrupt request signal. p. 565 be sure to clear bits 3 to 7 to ?0?. p. 565 the oscillation stabilization time following reset release is 2 15 /f x (because the initial value of the osts register = 01h). p. 565 osts register the oscillation stabilization time is also inserted during external clock input. p. 565 insert five or more nop instructions after the halt instruction. p. 566 halt instruction if the halt instruction is executed with an unmasked interrupt request signal held pending, the system shift to the halt mode, but the halt mode is immediately released by the pending interrupt request signal. p. 566 idle mode insert five or more nop instructions after the instruction that stores data in the psc register to set the idle mode. p. 568 chapter 19 soft standby function releasing idle mode the interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (inte rrupt disabled) becomes invalid and the idle mode is not released. p. 569
appendix d list of cautions user?s manual u17705ej2v0ud 695 (24/27) chapter classification function details of function cautions page stop mode insert five or more nop instructions after the instruction that stores data in the psc register to set the stop mode. p. 571 releasing stop mode the interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (inte rrupt disabled) becomes invalid and the stop mode is not released. p. 572 when manipulating the ck3 bit, do not change the set values of the pcc.ck2 to pcc.ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details, refer to 5.3 (1 ) processor clock control register (pcc). p. 575 subclock operation mode if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied and set the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 p. 575 releasing subclock operation mode when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instructi on to manipulate the bit is recommended). for details, refer to 5.3 (1) proce ssor clock control register (pcc). p. 575 sub-idle mode following the store instruction to the psc register for setting the sub-idle mode, insert five or more nop instructions. p. 577 chapter 19 soft standby function releasing sub- idle mode the interrupt request signal that is disabled by setting the psc.nmi2m, psc.nmi0m, and psc.intm bits to 1 (inte rrupt disabled) becomes invalid and the sub-idle mode is not released. p. 578 flash memory for the electrical specifications related to the fl ash memory rewriting, refer to chapter 23 electrical specifications. p. 585 wire the pin as shown in figure 21-6, or connect it to gnd on board via a pull- down resistor. p. 593 connect these pins to supply a clock from the pg-fp4 (wire as shown in figure 21-6, or create an oscillator on board and supply the clock). p. 593 pg-fp4 when using the clock out of the flash programmer, connect clk of the programmer to x1, and connect its inverse signal to x2. p. 594 wire the flmd1 pin as shown in the fi gure, or connect it to gnd on board via a pull-down resistor. p. 596 hard fa-80gc-8bt-a be sure to set and connect as follows w hen the clock is supplied from the pg- fp4. ? set j1 of the flash adapter (fa) to the vdd side. ? connect clkout of fa to clkin of fa. ? connect x1 of fa to x1 of the device. ? connect x2 of fa to x2 of the device. if an oscillator is created on the flash adapter and a clock is supplied, the above setting and connections will not necessary. p. 596 soft selection of communication mode when uart0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the flmd0 pulse. p. 598 flmd1 pin if the v dd signal is input to the flmd1 pi n from another device during on-board writing and immediately after reset, isolate this signal. p. 601 chapter 21 hard flash memory flmd0 pin make sure that the flmd0 pin is at 0 v when reset is released. p. 608 chapter 22 hard on-chip debug function cautions do not mount a device that was used for debugging on a mass-produced product, because the flash memory was rewr itten during debugging and the number of rewrites of the flash memory cannot be guaranteed. moreover, do not embed the debug monitor program into mass-produced products. p. 618
appendix d list of cautions user?s manual u17705ej2v0ud 696 (25/27) chapter classification function details of function cautions page forced breaks cannot be executed if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial inte rface, which is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby re lease by a maskable interrupt is prohibited ? mode for communication between minicube2 and the target device is uart0, and the main clock has been stopped p. 618 the pseudo rrm function and dmm function do not operate if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial inte rface, which is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby re lease by a maskable interrupt is prohibited ? mode for communication between minicube2 and the target device is uart0, and the main clock has been stopped ? mode for communication between minicube2 and the target device is uart0, and a clock different from the one specified in the debugger is used for communication p. 618 the standby mode is released by the pseudo rrm function and dmm function if one of the following conditions is satisfied. ? mode for communication between minicube2 and the target device is csi00 ? mode for communication between minicube2 and the target device is uart0, and the main clock has been supplied. p. 618 peripheral i/o registers that requires a specific sequenc e cannot be written with the dmm function. p. 618 cautions if a space where the debug monitor program is allocated is rewritten by flash self programming, the debugger can no longer operate normally. p. 618 chapter 22 soft on-chip debug function security id after the flash memory is eras ed, 1 is written to the entire area. p. 619 be sure not to exceed the absolute maxi mum ratings (max. value) of each supply voltage. p. 622 pp. do not directly connect the output (or i/o) pi ns of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possibl e, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 622, 623 pp. absolute maximum ratings product quality may suffer if the absol ute maximum rating is exceeded even momentarily for any parameter. that is , the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under c onditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristi cs represent the quality assurance range during normal operation. 622, 623 chapter 23 hard electrical specifica- tions eeprom emulation do not stop the main clock. p. 625
appendix d list of cautions user?s manual u17705ej2v0ud 697 (26/27) chapter classification function details of function cautions page the duty ratio of the input waveform must be within 50% 5%. p. 626 hard when using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a gr ound pattern through which a high current flows. ? do not fetch signals from the oscillator. p. 626 soft main clock oscillator characteristics when the main clock is stopped and the devic e is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. p. 626 the duty ratio of the input waveform must be within 50% 5%. p. 627 when using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a gr ound pattern through which a high current flows. ? do not fetch signals from the oscillator. p. 627 subclock oscillator characteristics the subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillator. particular care is therefore required with the wiring method when the subclock is used. p. 627 dc characteristics refer to i ol1 for i ol of p38 and p39. p. 629 data retention characteristics shifting to stop mode and restoring from stop mode must be performed within the rated operating range. p. 631 hard ac characteristics if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. p. 632 the system requires a minimum of 300 ns hold time internally for the sda0 signal (at v ihmin. of scl0 signal) in order to occupy the undefined area at the falling edge of scl0. p. 640 chapter 23 soft electrical specifica- tions i 2 c bus mode if the system does not extend the scl0 signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. p. 640
appendix d list of cautions user?s manual u17705ej2v0ud 698 (27/27) chapter classification function details of function cautions page soft i 2 c bus mode the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl0 signal?s low state hold time: t su : dat 250 ns ? if the system extends the scl0 signal?s low state hold time: transmit the following data bit to the sda0 line prior to the scl0 line release (t rmax. + t su:dat = 1000 + 250 = 1250 ns: normal mode i 2 c bus specification). p. 640 chapter 23 hard electrical specifica- tions flash memory programming characteristics when writing initially to shipped products , it is counted as one rewrite for both ?erase to write? and ?write only?. example (p: write, e: erase) shipped product ?? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites p. 643 chapter 25 hard recom- mended soldering conditions recommended soldering conditions do not use different soldering methods t ogether (except for partial heating). p. 645 appendix a soft develop- ment tools rx850 or rx850 pro to purchase the rx850 or rx850 pro, first fill in the purchase application form and sign the license agreement. p. 655 appendix b soft instruction set list instruction set do not specify the same regi ster for general-purpose registers reg1 and reg3. p. 665
user?s manual u17705ej2v0ud 699 appendix e revision history e.1 major revisions in this edition page description p. 42 addition of description to 3.2.2 (6) exception/debug trap stat us saving registers (dbpc, dbpsw) p. 49 addition of 3.4.4 (4) number of clocks for access p. 135 modification of 6.4 (3) tmp0 i/o control register 0 (tp0ioc0) p. 178 addition of caution to figure 6-22 setting of registers in one-shot pulse output mode p. 288 modification of figure 8-1 block diagram of 8-bit timer/event counter 5n p. 316 addition of note to figure 9-3 timing of interval timer/square wave output operation p. 334 modification of 10.1.4 (1) operation of interval timer brg p. 348 modification of cautions in 11.2.3 (1) watchdog timer mode register 2 (wdtm2) p. 349 modification of cautions in 11.2.3 (2) watchdog timer enable register (wdte) p. 363 modification of cautions in 13.4 (1) a/d converter mode register (adm) p. 366 modification of cautions in 13.4 (2) analog input channel specification register (ads) p. 369 modification of cautions in 13.4 (4) power fail comparison mode register (pfm) p. 369 modification of cautions in 13.4 (5) power fail comparison threshold register (pft) p. 371 modification of 13.5.2 trigger modes p. 372 modification of 13.5.3 (1) select mode p. 373 modification of 13.5.3 (2) scan mode p. 374 modification of figure 13-5 example of scan mode oper ation timing (ads.ads2 to ads.ads0 bits = 011b) p. 377 modification of figure 13-7 example of how to reduce power consumption in standby mode p. 382 addition of 13.6 (14) a/d conversion operation in normal mode p. 502 modification of wait period in table 16-7 wait periods p. 551 addition of caution to 17.6.1 (2) restore p. 553 addition of caution to 17.6.2 (2) restore p. 588 modification of table 21-2 basic functions p. 588 modification of table 21-3 security functions p. 589 addition of table 21-4 security setting p. 590 addition of 21.3 (1) security setting by pg-fp4 (security flag settings) p. 592 modification of transfer rate in 21.4.2 (1) uart0 p. 599 modification of table 21-7 flash memory control commands p. 610 modification of chapter 22 on-chip debug function p. 628 addition of note 3 to dc characteristics in chapter 23 electrical specifications p. 645 addition of chapter 25 recommended soldering conditions p. 646 addition of appendix a development tools p. 672 addition of appendix d list of cautions p. 699 addition of appendix e revision history
nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ nec electronics shanghai ltd. room 2511-2512, bank of china tower, 200 yincheng road central, pudong new area, shanghai p.r. china p.c:200120 tel: 021-5888-5400 http://www.cn.necel.com/ nec electronics hong kong ltd. 12/f., cityplaza 4, 12 taikoo wan road, hong kong tel: 2886-9318 http://www.hk.necel.com/ nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-8175-9600 http://www.tw.necel.com/ nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ nec electronics korea ltd. 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 http://www.kr.necel.com/ for further information, please contact: g06.11a [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielskistrasse 166 b 30177 hannover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands steijgerweg 6 5616 hs eindhoven the netherlands tel: 040 265 40 10

▲Up To Search▲

Price & Availability of UPD70F3726GB-8EU-A

	To Download UPD70F3726GB-8EU-A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .