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rev. 4.2 _00 cmos serial e 2 prom s-93c46b/56b/66b seiko instruments inc. 1 the s-93c46b/56b/66b is a high speed, low current consumption, 1/2/4 k-bit serial e 2 prom with a wide operating voltage range. it is organized as 64-word 16- bit, 128-word 16-bit, 256-word 16-bit, respectively. each is capable of sequential read, at which time addresses are automatically incremented in 16-bit blocks. the instruction code is compatible with the nm93cs46/56/66. ? features ? low current consumption standby: 1.5 a max. (v cc = 5.5 v) operating: 0.8 ma max. (v cc = 5.5 v) 0.4 ma max. (v cc = 2.5 v) ? wide operating voltage range read: 1.8 to 5.5 v (at ? 40 to + 85 c) write: 2.7 to 5.5 v (at ? 40 to + 85 c) ? sequential read capable ? write disable function when power supply voltage is low ? function to protect against write due to erroneous instruction recognition ? endurance: 10 7 cycles/word *1 (at + 25 c) write capable, 10 6 cycles/word *1 (at + 85 c) 3 10 5 cycles/word *1 (at + 105 c) *1. for each address (word: 16 bits) ? data retention: 10 years (after rewriting 10 6 cycles/word at + 85 c) ? s-93c46b: 1 k-bit nm93cs46 instruction code compatible ? s-93c56b: 2 k-bit nm93cs56 instruction code compatible ? s-93c66b: 4 k-bit nm93cs66 instruction code compatible ? high-temperature operation: + 105 c max. supported (only s-93cx6bd0h-j8t2g, s-93cx6bd0h-t8t2g) ? lead-free products ? packages drawing code package name package tape reel 8-pin dip dp008-f ? ? 8-pin sop(jedec) fj008-a fj008-d fj008-d 8-pin tssop ft008-a ft008-e ft008-e snt-8a ph008-a ph008-a ph008-a caution this product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devi ces. before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to sii is indispensable.
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 2 ? pin configurations 8-pin dip top view table 1 pin no. symbol description 1 cs chip select input 2 sk serial clock input 3 di serial data input 4 do serial data output 5 gnd ground 6 test *1 test 7 nc no connection 8 vcc power supply *1. connect to gnd or v cc . even if this pin is not connec ted, performance is not affected so long as the absolute maximum rating is not exceeded. 1 2 3 4 8 7 6 5 vcc nc test gnd cs sk do di figure 1 s-93c46bd0i-d8s1g s-93c56bd0i-d8s1g s-93c66bd0i-d8s1g remark see dimensions for details of the package drawings. 8-pin sop(jedec) top view table 2 pin no. symbol description 1 cs chip select input 2 sk serial clock input 3 di serial data input 4 do serial data output 5 gnd ground 6 test *1 test 7 nc no connection 8 vcc power supply *1. connect to gnd or v cc . even if this pin is not connec ted, performance is not affected so long as the absolute maximum rating is not exceeded. 1 2 3 4 8 7 6 5 vcc nc test gnd cs sk do di figure 2 s-93c46bd0i-j8t1g s-93c46bd0h-j8t2g s-93c56bd0i-j8t1g s-93c56bd0h-j8t2g s-93c66bd0i-j8t1g s-93c66bd0h-j8t2g remark see dimensions for details of the package drawings.
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 3 8-pin sop(jedec) (rotated) top view table 3 pin no. symbol description 1 nc no connection 2 vcc power supply 3 cs chip select input 4 sk serial clock input 5 di serial data input 6 do serial data output 7 gnd ground 8 test *1 test *1. connect to gnd or v cc . even if this pin is not connec ted, performance is not affected so long as the absolute maximum rating is not exceeded. 1 2 3 4 8 7 6 5 cs sk test gnd do di vcc nc figure 3 s-93c46br0i-j8t1g s-93c56br0i-j8t1g s-93c66br0i-j8t1g remark see dimensions for details of the package drawings. 8-pin tssop top view table 4 pin no. symbol description 1 cs chip select input 2 sk serial clock input 3 di serial data input 4 do serial data output 5 gnd ground 6 test *1 test 7 nc no connection 8 vcc power supply *1. connect to gnd or v cc . even if this pin is not connec ted, performance is not affected so long as the absolute maximum rating is not exceeded. 1 2 3 4 8 7 6 5 vcc nc test gnd cs sk do di figure 4 s-93c46bd0i-t8t1g s-93c46bd0h-t8t2g s-93c56bd0i-t8t1g s-93c56bd0h-t8t2g s-93c66bd0i-t8t1g s-93c66bd0h-t8t2g remark see dimensions for details of the package drawings.
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 4 snt-8a top view table 5 pin no. symbol description 1 cs chip select input 2 sk serial clock input 3 di serial data input 4 do serial data output 5 gnd ground 6 test *1 test 7 nc no connection 8 vcc power supply *1. connect to gnd or v cc . even if this pin is not connect ed, performance is not affected so long as the absolute maximum rating is not exceeded. 1 2 3 4 8 7 6 5 vcc nc test gnd cs sk di do figure 5 s-93c46bd0i-i8t1g s-93c56bd0i-i8t1g s-93c66bd0i-i8t1g remark see dimensions for details of the package drawings.
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 5 ? block diagram memory array data register address decoder mode decode logic clock pulse monitoring circuit output buffer vcc gnd do di cs clock generator voltage detector sk figure 6
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 6 ? instruction sets 1. s-93c46b table 6 instruction start bit operation code address data sk input clock 1 2 3 4 5 6 7 8 9 10 to 25 read (read data) 1 1 0 a5 a4 a3 a2 a1 a0 d15 to d0 output *1 write (write data) 1 0 1 a5 a4 a3 a2 a1 a0 d15 to d0 input erase (erase data) 1 1 1 a5 a4 a3 a2 a1 a0 ? wral (write all) 1 0 0 0 1 x x x x d15 to d0 input eral (erase all) 1 0 0 1 0 x x x x ? ewen (write enable) 1 0 0 1 1 x x x x ? ewds (write disable) 1 0 0 0 0 x x x x ? *1. when the 16-bit data in the specified address has been output, the data in the next address is output. remark x: don?t care 2. s-93c56b table 7 instruction start bit operation code address data sk input clock 1 2 3 4 5 6 7 8 9 10 11 12 to 27 read (read data) 1 1 0 x a6 a5 a4 a3 a2 a1 a0 d15 to d0 output *1 write (write data) 1 0 1 x a6 a5 a4 a3 a2 a1 a0 d15 to d0 input erase (erase data) 1 1 1 x a6 a5 a4 a3 a2 a1 a0 ? wral (write all) 1 0 0 0 1 x x x x x x d15 to d0 input eral (erase all) 1 0 0 1 0 x x x x x x ? ewen (write enable) 1 0 0 1 1 x x x x x x ? ewds (write disable) 1 0 0 0 0 x x x x x x ? *1. when the 16-bit data in the specified address has been output, the data in the next address is output. remark x: don?t care
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 7 3. s-93c66b table 8 instruction start bit operation code address data sk input clock 1 2 3 4 5 6 7 8 9 10 11 12 to 27 read (read data) 1 1 0 a7 a6 a5 a4 a3 a2 a1 a0 d15 to d0 output *1 write (write data) 1 0 1 a7 a6 a5 a4 a3 a2 a1 a0 d15 to d0 input erase (erase data) 1 1 1 a7 a6 a5 a4 a3 a2 a1 a0 ? wral (write all) 1 0 0 0 1 x x x x x x d15 to d0 input eral (erase all) 1 0 0 1 0 x x x x x x ? ewen (write enable) 1 0 0 1 1 x x x x x x ? ewds (write disable) 1 0 0 0 0 x x x x x x ? *1. when the 16-bit data in the specified address has been output, the data in the next address is output. remark x: don?t care
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 8 ? absolute maximum ratings table 9 item symbol ratings unit power supply voltage v cc ? 0.3 to + 7.0 v input voltage v in ? 0.3 to v cc + 0.3 v output voltage v out ? 0.3 to v cc v operating ambient temperature t opr ? 40 to + 105 c storage temperature t stg ? 65 to + 150 c caution the absolute maximum ratings are rated values exceeding which the product could suffer physical damage. these values must therefore not be exceeded under any conditions. ? recommended operating conditions table 10 ? 40 to + 85 c + 85 to + 105 c item symbol conditions min. typ. max. min. typ. max. unit read/ewds 1.8 ? 5.5 4.5 ? 5.5 v power supply voltage v cc write/erase/ wral/eral/ewen 2.7 ? 5.5 4.5 ? 5.5 v v cc = 4.5 to 5.5 v 2.0 ? v cc 2.0 ? v cc v v cc = 2.7 to 4.5 v 0.8 v cc ? v cc ? ? ? v high level input voltage v ih v cc = 1.8 to 2.7 v 0.8 v cc ? v cc ? ? ? v v cc = 4.5 to 5.5 v 0.0 ? 0.8 0.0 ? 0.8 v v cc = 2.7 to 4.5 v 0.0 ? 0.2 v cc ? ? ? v low level input voltage v il v cc = 1.8 to 2.7 v 0.0 ? 0.15 v cc ? ? ? v ? pin capacitance table 11 (ta = 25 c, f = 1.0 mhz, v cc = 5.0 v) item symbol conditions min. typ. max. unit input capacitance c in v in = 0 v ? ? 8 pf output capacitance c out v out = 0 v ? ? 10 pf ? endurance table 12 item symbol operating temperature min. typ. max. unit ? 40 to + 85 c 10 6 ? ? endurance n w + 85 to + 105 c 3 10 5 ? ? cycles/word *1 *1. for each address (word: 16 bits)
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 9 ? dc electrical characteristics table 13 ? 40 to + 85 c + 85 to + 105 c v cc = 4.5 to 5.5 v v cc = 2.5 to 4.5 v v cc = 1.8 to 2.5 v v cc = 4.5 to 5.5 v item symbol conditions min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit current consumption (read) i cc1 do no load ? ? 0.8 ? ? 0.5 ? ? 0.4 ? ? 0.8 ma table 14 ? 40 to + 85 c + 85 to + 105 c v cc = 4.5 to 5.5 v v cc = 2.7 to 4.5 v v cc = 4.5 to 5.5 v item symbol conditions min. typ. max. min. typ. max. min. typ. max. unit current consumption (write) i cc2 do no load ? ? 2.0 ? ? 1.5 ? ? 2.0 ma table 15 ? 40 to + 85 c + 85 to + 105 c v cc = 4.5 to 5.5 v v cc = 2.5 to 4.5 v v cc = 1.8 to 2.5 v v cc = 4.5 to 5.5 v item symbol conditions min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit standby current consumption i sb cs = gnd, do = open, other inputs to v cc or gnd ? ? 1.5 ? ? 1.5 ? ? 1.5 ? ? 1.5 a input leakage current i li v in = gnd to v cc ? 0.1 1.0 ? 0.1 1.0 ? 0.1 1.0 ? 0.1 1.0 a output leakage current i lo v out = gnd to v cc ? 0.1 1.0 ? 0.1 1.0 ? 0.1 1.0 ? 0.1 1.0 a i ol = 2.1 ma ? ? 0.4 ? ? ? ? ? ? ? ? 0.4 v low level output voltage v ol i ol = 100 a ? ? 0.1 ? ? 0.1 ? ? 0.1 ? ? 0.1 v i oh = ? 400 a 2.4 ? ? ? ? ? ? ? ? 2.4 ? ? v i oh = ? 100 a v cc ? 0.3 ? ? v cc ? 0.3 ? ? ? ? ? v cc ? 0.3 ? ? v high level output voltage v oh i oh = ? 10 a v cc ? 0.2 ? ? v cc ? 0.2 ? ? v cc ? 0.2 ? ? v cc ? 0.2 ? ? v write enable latch data hold voltage v dh only when write disable mode 1.5 ? ? 1.5 ? ? 1.5 ? ? 1.5 ? ? v
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 10 ? ac electrical characteristics table 16 measurement conditions input pulse voltage 0.1 v cc to 0.9 v cc output reference voltage 0.5 v cc output load 100 pf table 17 ? 40 to + 85 c + 85 to + 105 c v cc = 4.5 to 5.5 v v cc = 2.5 to 4.5 v v cc = 1.8 to 2.5 v v cc = 4.5 to 5.5 v item symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit cs setup time t css 0.2 ? ? 0.4 ? ? 1.0 ? ? 0.2 ? ? s cs hold time t csh 0 ? ? 0 ? ? 0 ? ? 0 ? ? s cs deselect time t cds 0.2 ? ? 0.2 ? ? 0.4 ? ? 0.2 ? ? s data setup time t ds 0.1 ? ? 0.2 ? ? 0.4 ? ? 0.1 ? ? s data hold time t dh 0.1 ? ? 0.2 ? ? 0.4 ? ? 0.1 ? ? s output delay time t pd ? ? 0.4 ? ? 0.8 ? ? 2.0 ? ? 0.6 s clock frequency *1 f sk 0 ? 2.0 0 ? 0.5 0 ? 0.25 0 ? 1.0 mhz sk clock time ?l? *1 t skl 0.1 ? ? 0.5 ? ? 1.0 ? ? 0.25 ? ? s sk clock time ?h? *1 t skh 0.1 ? ? 0.5 ? ? 1.0 ? ? 0.25 ? ? s output disable time t hz1 , t hz2 0 ? 0.15 0 ? 0.5 0 ? 1.0 0 ? 0.15 s output enable time t sv 0 ? 0.15 0 ? 0.5 0 ? 1.0 0 ? 0.15 s *1. the clock cycle of the sk clock (frequency: f sk ) is 1/f sk s. this clock cycle is determined by a combination of several ac characteristics, so be aware that even if the sk clock cycle time is minimized, the clock cycle (1/f sk ) cannot be made equal to t skl (min.) + t skh (min.). table 18 ? 40 to + 85 c + 85 to + 105 c v cc = 2.7 to 5.5 v v cc = 4.5 to 5.5 v item symbol min. typ. max. min. typ. max. unit write time t pr ? 4.0 8.0 ? 4.0 8.0 ms
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 11 t skh t cds t css cs valid data valid data di t skl sk t sv t hz2 t csh t hz1 t pd t pd t ds t dh t ds t dh hi-z hi-z hi-z do do (read) (verify) hi-z *1 1/f sk *2 *1. indicates high impedance. *2. 1/f sk is the sk clock cycle. this clock cycle is determined by a combination of several ac characteristics, so be aware that even if the sk clock cycle time is minimized, the clock cycle (1/f sk ) cannot be made equal to t skl (min.) + t skh (min.). figure 7 timing chart
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 12 ? operation all instructions are executed by inputting di in synchronization with the rising edge of sk after cs goes high. an instruction set is input in the or der of start bit, instruction, address, and data. instruction input finishes when cs goes low. a lo w level must be input to cs between commands during t cds . while a low level is being input to cs, the s- 93c46b/56b/66b is in standby mode, so the sk and di inputs are invalid and no instructions are allowed. ? start bit a start bit is recognized when the di pin goes high at t he rise of sk after cs goes high. after cs goes high, a start bit is not recognized even if the sk pulse is input as long as the di pin is low. 1. dummy clock sk clocks input while the di pin is low before a st art bit is input are called dummy clocks. dummy clocks are effective when aligning t he number of instruction sets (clo cks) sent by the cpu with those required for serial memory operation. for example, when a cpu instruction set is 16 bits, the number of instruction set clocks can be adjusted by insert ing a 7-bit dummy clock for the s-93c46b and a 5-bit dummy clock for the s-93c56b/66b. 2. start bit input failure ? when the output status of the do pin is high during the verify period after a write operation, if a high level is input to the di pin at the rising edge of sk, the s-93c46b/56b/66b re cognizes that a start bit has been input. to prevent this failure, input a lo w level to the di pin during the verify operation period (refer to ? 4.1 verify operation ?). ? when a 3-wire interface is configured by connecti ng the di input pin and do output pin, a period in which the data output from the cpu and the serial memory co llide may be generated, preventing successful input of the start bit. take the measures described in ? ? 3-wire interface (direct connection between di and do) ?.
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 13 3. reading (read) the read instruction reads data from a specified address. after cs has gone high, input an instru ction in the order of the start bit, read instruction, and address. since the last input address (a 0 ) has been latched, the output status of the do pin changes from high impedance (hi-z) to low, which is held until the next rise of sk. 16-bit data starts to be output in synchronization with the next rise of sk. 3. 1 sequential read after the 16-bit data at the specified addre ss has been output, inputting sk while cs is high automatically increments the addr ess, and causes the 16-bit data at the next address to be output sequentially. the above method makes it possible to read the data in the whole memory space. the last address (a n yyy a 1 a 0 = 1 yyy 1 1) rolls over to the top address (a n yyy a 1 a 0 = 0 yyy 0 0). d 15 d 15 d 14 d 14 d 13 d 14 d 13 d 0 d 1 d 2 d 15 0 d 0 d 1 d 2 d 13 a 1 a 2 a 3 a 4 a 5 0 1 <1> a 0 sk di cs do adrinc hi-z 28 27 26 25 24 23 12 11 10 9 8 7 6 5 4 3 2 1 44 43 42 41 40 39 adrinc hi-z figure 8 read timing (s-93c46b) sk d 13 d 15 0 d 14 d 14 d 13 d 0 d 1 d 2 d 1 5 d 14 d 0 d 1 d 2 d 13 d 15 41 40 43 44 42 28 27 26 25 24 a 3 a 4 a 5 a 0 a 1 a 2 di 13 11 10 9 8 7 6 5 4 3 2 1 12 cs do a 6 45 29 14 hi - z hi-z 0 1 <1> adrinc adrinc x: s-93c56b a 7 : s-93c66b figure 9 read timing (s-93c56b, s-93c66b)
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 14 4. writing (write, erase, wral, eral) a write operation includes four write instructions: data write (write), data erase (erase), chip write (wral), and chip erase (eral). a write instruction (write, erase, wral, eral) st arts a write operation to the memory cell when a low level is input to cs after a specified number of clocks have been input. the sk and di inputs are invalid during the write period, so do not input an instruction. input an instruction while the output status of the do pin is high or high impedance (hi-z). a write operation is valid only in program enable mode (refer to ? 5. write enable (ewen) and write disable (ewds) ?). 4. 1 verify operation a write operation executed by any instruction is completed within 8 ms (write time t pr : typically 4 ms), so if the completion of the write operation is recognized, the write cycle can be minimized. a sequential operation to confirm the status of a wr ite operation is called a verify operation. (1) operation after the write operation has started (cs = low), the status of the write operation can be verified by confirming the output status of the do pin by inputting a high level to cs again. this sequence is called a verify operation, and the period t hat a high level is input to the cs pin after the write operation has started is called the verify operation period. the relationship between the output status of the do pin and the write operation during the verify operation period is as follows. ? do pin = low: writing in progress (busy) ? do pin = high: writing completed (ready) (2) operation example there are two methods to perform a verify operat ion: waiting for a change in the output status of the do pin while keeping cs high, or suspending the verify operation (cs = low) once and then performing it again to verify the output status of the do pin. the latter method allows the cpu to perform other processing during the wait period, allowing an efficient system to be designed. caution 1. input a low level to the di pin during a verify operation. 2. if a high level is input to the di pin at the rise of sk when the output status of the do pin is high, the s-93c46b/56b/66b latches th e instruction assuming that a start bit has been input. in this case, note that the do pin immediately enters a high-impedance (hi-z) state.
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 15 4. 2 writing data (write) to write 16-bit data to a specified address, change cs to high and then input the write instruction, address, and 16-bit data following the start bit. the write operation starts when cs goes low. there is no need to set the data to 1 befor e writing. if the clocks more than the specified number have been input, the clock pulse monitoring ci rcuit cancels the write instruction. for details of the clock pulse monitoring circuit, refer to ? ? function to protect against write due to erroneous instruction recognition ?. hz1 a5 a3 a2 a1 a0 d15 a4 1 3 4 5 6 7 8 9 10 2 0 1 <1> 25 t cds verify busy standby t sv t ready t pr hi-z cs sk di do hi-z d0 figure 10 data write timing (s-93c46b) <1> r eady busy t pr t sv t cds 27 1 2 3 4 5 6 7 8 9 10 11 12 0 1 d0 a6 a5 a4 a3 a2 a1 a0 d15 cs sk di do hi-z verify standby hi-z t hz1 x : s-93c56b a7: s-93c66b figure 11 data write timing (s-93c56b, s-93c66b)
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 16 4. 3 erasing data (erase) to erase 16-bit data at a specified address, set a ll 16 bits of the data to 1, change cs to high, and then input the erase instruction and address following t he start bit. there is no need to input data. the data erase operation starts when cs goes low. if the clocks more than the specified number have been input, the clock pulse monitoring circuit c ancels the erase instruction. for details of the clock pulse monitoring circuit, refer to ? ? function to protect against write due to erroneous instruction recognition ?. verify t sv sk di a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 cs do t cds t pr busy hi-z standby hi-z t hz1 <1> 1 a0 ready 1 figure 12 data erase timing (s-93c46b) ready t cds t sv hi-z t hz1 t pr sk di <1> a6 a5 a4 a3 a2 a1 a0 1 2 3 4 5 6 7 8 9 10 11 cs do busy verify standby hi-z 1 1 x : s-93c56b a7: s-93c66b figure 13 data erase timing (s-93c56b, s-93c66b)
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 17 4. 4 writing to chip (wral) to write the same 16-bit data to the entire me mory address space, change cs to high, and then input the wral instruction, an address, and 16-bit data following the start bit. any address can be input. the write operation starts when cs goes lo w. there is no need to set the data to 1 before writing. if the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the wral instruction. for details of the clock pulse monitoring circuit, refer to ? ? function to protect against write due to erroneous instruction recognition ?. 2 3 4 5 6 7 8 9 10 1 sk di t cds t sv t hz1 hi-z t pr cs do b usy verify standby hi-z 25 <1> 0 d0 r eady 0 0 1 4xs d15 figure 14 chip write timing (s-93c46b) verify 2 3 4 5 6 7 8 9 10 1 sk di t cds t sv t hz1 hi-z t pr cs do b usy standby hi-z 11 12 27 <1> 0 d0 r eady 0 0 1 6xs d15 figure 15 chip write timing (s-93c56b, s-93c66b)
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 18 4. 5 erasing chip (eral) to erase the data of the entire memory address s pace, set all the data to 1, change cs to high, and then input the eral instruction and an address follow ing the start bit. any address can be input. there is no need to input data. the chips erase operation starts when cs goes low. if the clocks more than the specified number have been input, t he clock pulse monitoring circuit cancels the eral instruction. for details of the clock pulse monitoring circuit, refer to ? ? function to protect against write due to erroneous instruction recognition ?. t cds 4xs 0 1 0 8 7 6 5 4 3 2 1 <1> 0 t pr hi-z t hz1 r eady b usy t sv standby verify 9 sk di cs do figure 16 chip erase timing (s-93c46b) 7 6 5 4 3 2 1 9 8 cs sk di do t cds t sv r eady b usy t hz1 hi-z t pr 11 6xs 0 1 0 <1> 0 standby verify 10 figure 17 chip erase timing (s-93c56b, s-93c66b)
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 19 5. write enable (ewen) and write disable (ewds) the ewen instruction is an instruction that enables a write operation. the status in which a write operation is enabled is called the program enable mode. the ewds instruction is an instruction that disables a write operation. the status in which a write operation is disabled is called the program disable mode. after cs goes high, input an instruction in the order of the start bit, ewen or ewds instruction, and address (optional). each mode becomes valid by in putting a low level to cs after the last address (optional) has been input. 5 4 3 2 1 9 8 7 6 sk di cs 4xs 11 = ewen 00 = ewds 0 <1> 0 standby figure 18 write enable/disable timing (s-93c46b) di sk 6 5 4 3 2 1 9 8 11 10 7 cs 6xs 11 = ewen 00 = ewds 0 <1> 0 standby figure 19 write enable/disab le timing (s-93c56b, s-93c66b) (1) recommendation for write operation disable instruction it is recommended to implement a design that pr events an incorrect write operation when a write instruction is erroneously recognized by execut ing the write operation disable instruction when executing instructions other than write instru ction, and immediately after power-on and before power off.
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 20 ? write disable function when power supply voltage is low the s-93c46b/56b/66b provides a built-in detecto r to detect a low power supply voltage and disable writing. when the power supply voltage is low or at power application, the write instructions (write, erase, wral, and eral) are cancelled, and the write disable state (ewds) is automatically set. the detection voltage is 1.75 v typ., the release voltage is 2.05 v typ., and there is a hysteresis of about 0.3 v (refer to figure 20 ). therefore, when a write operation is performed after the power supply voltage has dropped and then risen again up to the level at which writ ing is possible, a write enable instruction (ewen) must be sent before a write instruction (write, erase, wral, or eral) is executed. when the power supply voltage drops during a write operat ion, the data being written to an address at that time is not guaranteed. release voltage ( + v det ) 2.05 v typ. power supply voltage hysteresis a bout 0.3 v detection voltage ( ? v det ) 1.75 v typ. write instruction cancelled write disable state (ewds) automatically set figure 20 operation when power supply voltage is low
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 21 ? function to protect against write due to erroneous instruction recognition the s-93c46b/56b/66b provides a bu ilt-in clock pulse monitoring circuit which is used to prevent an erroneous write operation by canceling write instru ctions (write, erase, wral, and eral) recognized erroneously due to an erroneous clock count caused by the application of noise pulses or double counting of clocks. instructions are cancelled if a clock pulse more or less than specified number decided by each write operation (write, erase, wral , or eral) is detected. erroneous recognition of program disable in struction (ewds) as erase instruction (erase) 1 3 4 5 6 7 2 8 9 cs sk di input ewds instruction erroneous recognition as erase instruction due to noise pulse 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 noise pulse example of s-93c46b 1 in products that do not include a clock pulse monitoring circuit, ffff is mistakenly written on address 00h. howeve r the s-93c46b detects the overcount and cancels the instruction without performing a write operation. figure 21 example of clock pul se monitoring circuit operation
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 22 ? 3-wire interface (direct connection between di and do) there are two types of serial interface configurations : a 4-wire interface configured using the cs, sk, di, and do pins, and a 3-wire interface that connects the di input pin and do output pin. when the 3-wire interface is employed, a period in which the data output from the cpu and the data output from the serial memory collide may occur, causing a malfunction. to prevent such a malfunction, connect the di and do pins of the s-93c46b/ 56b/66b via a resistor (10 to 100 k ? ) so that the data output from the cpu takes precedence in being input to the di pin (refer to ? figure 22 connection of 3-wire interface ?). cpu di sio do s-93c46b/56b/66b r: 10 to 100 k ? figure 22 connection of 3-wire interface ? i/o pins 1. connection of input pins all the input pins of the s-93c46b/ 56b/66b employ a cmos structure, so design the equipment so that high impedance will not be input while the s-93c46b/56b/ 66b is operating. especially, deselect the cs input (a low level) when turning on/off power and dur ing standby. when the cs pin is deselected (a low level), incorrect data writing will not occur. connec t the cs pin to gnd via a resistor (10 to 100 k ? pull- down resistor). to prevent malfunction, it is recommended to use equivalent pull-down resistors for pins other than the cs pin. 2. input and output pin equivalent circuits the following shows the equivalent circuits of input pins of the s-93c46b/56b/66b. none of the input pins incorporate pull-up and pull-down elements, so special care must be taken when designing to prevent a floating status. output pins are high-level/low-level/high-impedance tri-state outputs. the test pin is disconnected from the internal circuit by a switching transisto r during normal operation. as long as the absolute maximum rating is satisfied, the test pin and internal circuit will never be connected.
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 23 2. 1 input pin cs figure 23 cs pin sk, di figure 24 sk, di pin test figure 25 test pin
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 24 2. 2 output pin do vcc figure 26 do pin 3. input pin noise elimination time the s-93c46b/56b/66b include a built-i n low-pass filter to eliminate noise at the sk, di, and cs pins. this means that if the supply voltage is 5.0 v (at r oom temperature), noise with a pulse width of 20 ns or less can be eliminated. note, therefore, the noise with a pulse width of more than 20 ns will be recognized as a pulse if the voltage exceeds v ih /v il . ? precaution ? do not apply an electrostatic discharge to this ic that exceeds the performance ratings of the built-in electrostatic protection circuit. ? sii claims no responsibility for any and all disputes aris ing out of or in connection with any infringement by products including this ic of patents owned by a third party.
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 25 ? characteristics (typical data) 1. dc characteristics 1. 1 current consumption (read) i cc1 vs. ambient temperature ta 1. 2 current consumption (read) i cc1 vs. ambient temperature ta ta ( c) 0.4 0.2 v cc = 5.5 v f sk = = ? 40 0 85 i cc1 (ma) ta ( c) 0.4 0.2 v cc = 3.3 v f sk = 500 khz data = 0101 0 ? 40 0 85 i cc1 (ma) 1. 3 current consumption (read) i cc1 vs. ambient temperature ta 1. 4 current consumption (read) i cc1 vs. power supply voltage v cc i cc1 (ma) ta ( c) 0.4 0.2 v cc = 1.8 v f sk = = ? 40 0 85 1 mhz 500 khz i cc1 (ma) 0.4 0.2 0 2 3 4 5 6 7 ta = 25 c f sk = 1 mhz, 500 khz data = 0101 v cc (v) 1. 5 current consumption (read) i cc1 vs. power supply voltage v cc 1. 6 current consumption (read) i cc1 vs. clock frequency f sk 100 khz 10 khz i cc1 (ma) 0.4 0.2 0 2 3 4 5 6 7 v cc (v) ta = 25 c f sk = 100 khz, 10 khz data = 0101 i cc1 ( ma ) 0.4 0.2 0 v cc = 5.0 v ta = 25 c 1 m 2m 10m 10 k 100 k f sk (hz)
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 26 1. 7 current consumption (write) i cc2 vs. ambient temperature ta 1. 8 current consumption (write) i cc2 vs. ambient temperature ta ta ( c) 1.0 0.5 v cc = 5.5 v 0 ? 40 085 i cc2 (ma) i cc2 (ma) ta ( c) 1.0 0.5 v cc = 3.3 v 0 ? 40 0 85 1. 9 current consumption (write) i cc2 vs. ambient temperature ta 1. 10 current consumption (write) i cc2 vs. power supply voltage v cc ta ( c) 1.0 0.5 v cc = 2.7 v 0 ? 40 085 i cc2 (ma) 1.0 0.5 0 2 3 4 5 6 7 ta = c v cc (v) i cc2 (ma) 1. 11 current consumption in standby mode i sb vs. ambient temperature ta 1. 12 current consumption in standby mode i sb vs. power supply voltage v cc ta (c) 1.0 0.5 v cc = 5.5 v cs = gnd 0 ? 40 0 85 i sb ( a) i sb ( a) 1.0 0.5 0 2 3 4 5 6 7 ta = 25 c cs = gnd v cc (v)
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 27 1. 13 input leakage current i li vs. ambient temperature ta 1. 14 input leakage current i li vs. ambient temperature ta 1.0 0.5 v cc =5.5 v cs, sk, di, test=0 v 0 -40 0 85 l li ( a) ta ( c) ta ( c) 1.0 0.5 0 ? 40 0 85 v cc = 5.5 v cs, sk, di, test = 5.5 v i li ( a) 1. 15 output leakage current i lo vs. ambient temperature ta 1. 16 output leakage current i lo vs. ambient temperature ta ta ( c) 1.0 0.5 v cc = 5.5 v do = 0 v 0 ? 40 0 85 i lo ( a) ta (c) 1.0 0.5 v cc = 5.5 v do = 5.5 v 0 ? 40 0 85 i lo ( a) 1. 17 high-level output voltage v oh vs. ambient temperature ta 1. 18 high-level output voltage v oh vs. ambient temperature ta ta ( c) 4.6 4.4 v cc = 4.5 v i oh = ? 400 a ? 40 0 85 v oh (v) 4.2 ta ( c) 2.7 2.6 v cc = 2.7 v i oh = ? 100 ? 40 0 85 v oh (v) 2.5
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 28 1. 19 high-level output voltage v oh vs. ambient temperature ta 1. 20 high-level output voltage v oh vs. ambient temperature ta ta ( c) 2.5 2.4 v cc = 2.5 v i oh = ? 100 ? 40 0 85 v oh (v) 2.3 ta ( c) 1.9 1.8 v cc = 1.8 v i oh = ? 10 a ? 40 0 85 v oh (v) 1.7 1. 21 low-level output voltage v ol vs. ambient temperature ta 1. 22 low-level output voltage v ol vs. ambient temperature ta ta ( c) 0.3 0.2 v cc = 4.5 v i ol = ? 40 085 v ol (v) 0.1 ta ( c) 0.03 0.02 v cc = 1.8 v i ol = ? 40 0 85 v ol (v) 0.01 1. 23 high-level output current i oh vs. ambient temperature ta 1. 24 high-level output current i oh vs. ambient temperature ta ta ( c) ? 20.0 ? 10.0 v cc = 4.5 v v oh = 2.4 v 0 ? 40 0 85 i oh (ma) ta ( c) ? 2 ? 1 v cc = 2.7 v v oh = 2.4 v 0 ? 40 0 85 i oh (ma)
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 29 1. 25 high-level output current i oh vs. ambient temperature ta 1. 26 high-level output current i oh vs. ambient temperature ta ta ( c) ? 2 ? 1 v cc = 2.5 v v oh = 2.2 v 0 ? 40 0 85 i oh (ma) ta ( c) ? 1.0 ? 0.5 v cc = 1.8 v v oh = 1.6 v 0 ? 40 0 85 i oh (ma) 1. 27 low-level output current i ol vs. ambient temperature ta 1. 28 low-level output current i ol vs. ambient temperature ta ta ( c) 20 10 v cc = 4.5 v v ol = 0.4 v 0 ? 40 0 85 i ol (ma) ta ( c) 1.0 0.5 v cc = 1.8 v v ol = 0.1 v 0 ? 40 0 85 i ol (ma) 1. 29 input inverted voltage v inv vs. power supply voltage v cc 1. 30 input inverted voltage v inv vs. ambient temperature ta 3.0 1.5 0 1 2 3 4 5 6 ta = c cs, sk, di v cc (v) v inv (v) 7 ta ( c) 3.0 2.0 v cc = 5.0 v cs, sk, di 0 ? 40 0 85 v inv (v)
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 30 1. 31 low supply voltage detection voltage ? v det vs. ambient temperature ta 1. 32 low supply voltage release voltage + v det vs. ambient temperature ta ta ( c) 2.0 1.0 0 ? 40 0 85 ? v det (v) ta ( c) 2.0 1.0 0 ? 40 0 85 + v det (v)
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 31 2. ac characteristics 2. 1 maximum operating frequency f max. vs. power supply voltage v cc 2. 2 write time t pr vs. power supply voltage v cc 10k 2 3 4 5 ta = 25 c v cc (v) f max. (hz) 1 100k 1m 2m 4 2 2 3 4 5 6 7 ta = 25 c v cc (v) t pr (ms) 1 2. 3 write time t pr vs. ambient temperature ta 2. 4 write time t pr vs. ambient temperature ta ta ( c) 6 4 v cc = 5.0 v ? 40 085 2 t pr (ms) ta ( c) 6 4 v cc = 3.0 v ? 40 0 85 2 t pr (ms) 2. 5 write time t pr vs. ambient temperature ta 2. 6 data output delay time t pd vs. ambient temperature ta ta ( c) 6 4 v cc = 2.7 v ? 40 0 85 2 t pr (ms) ta ( c) 0.3 0.2 v cc = 4.5 v ? 40 0 85 0.1 t pd ( s)
cmos serial e 2 prom s-93c46b/56b/66b rev.4.2 _00 seiko instruments inc. 32 2. 7 data output delay time t pd vs. ambient temperature ta 2. 8 data output delay time t pd vs. ambient temperature ta ta ( c) 0.6 0.4 v cc = 2.7 v ? 40 085 0.2 t pd ( s) ta ( c) 1.5 1.0 v cc = 1.8 v ? 40 0 85 0.5 t pd ( s)
cmos serial e 2 prom rev.4.2 _00 s-93c46b/56b/66b seiko instruments inc. 33 ? product name structure s-93cxxb x 0 x - xxxx g package name (abbreviation) and ic packing specifications d8s1: 8-pin dip, tube j8t1: 8-pin sop(jedec), tape j8t2: 8-pin sop(jedec), tape, + 105 c max.supported t8t1: 8-pin tssop, tape t8t2: 8-pin tssop, tape, + 105 c max. supported i8t1: snt-8a, tape operation temperature i: ? 40 to + 85 c h: ? 40 to + 105 c (only 8-pin sop(jedec) , 8-pin tssop) fixed pin assignment d: 8-pin dip 8-pin sop(jedec) 8-pin tssop snt-8a r: 8-pin sop(jedec) (rotated) product name s-93c46b : 1 k-bit s-93c56b : 2 k-bit s-93c66b : 4 k-bit

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the information described herein is subject to change without notice. seiko instruments inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. the application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. when the products described herein are regulated products subject to the wassenaar arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. use of the information described herein for other purposes and/or reproduction or copying without the express permission of seiko instruments inc. is strictly prohibited. the products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of seiko instruments inc. although seiko instruments inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. the user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.

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