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| november 2006 hys64t16000hu?[3.7/5]?a hys72t32000hu?[2.5/25f/3/3s/3.7/5]?a hys64t32001hu?[2.5/25f/3/3s/3.7/5]?a hys[64/72]t64020hu?[2.5/25f/3/3s/3.7]?a 240-pin unbuffered ddr2 sdram modules ddr2 sdram udimm sdram rohs compliant internet data sheet rev. 1.41
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 03062006-0gn5-wtpw hys64t16000hu?[3.7/5]?a, hys72t32000hu?[2.5/25f/3/3 s/3.7/5]?a, hys64t32001hu? [2.5/25f/3/3s/3.7/5]?a, hys[64/72]t64020hu?[2.5/25f/3/3s/3.7]?a revision history: 2006-11, rev. 1.41 page subjects (major changes since last revision) all qimonda update all adapted internet edition previous revision: 2006-04, rev. 1.4 product portfolio extended : added -2.5f and -3.7 products chapter 1.1 added features for average self refresh and self refresh rate to feature list chapter 3 updated i dd currents chapter 3 corrected note 4 - table 18 chapter 4 updated spd codes previous revision: 2005-09, rev. 1.3 chapter 4 spd codes update: byte 49 bit 0 = 1 ( hight_srfentry) for all product types chapter 5 package outlines updated previous revision: 2005-05, rev. 1.2 internet data sheet rev. 1.41, 2006-11 3 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 1overview this chapter gives an overview of the 1.8 v 240-pin unbuffered ddr2 sdram module s product family and describes its main characteristics. 1.1 features ? 240-pin pc2?6400, pc2?5300, pc2?4200 and pc2? 3200 ddr2 sdram memory modules for use as main memory when installed in systems such as mobile personal computers. ? 16m 64, 32m 64, 32m 72, 64m 64, 64m 72 module organization and 16m 16, 32m 8 chip organization ? 128 mb, 256 mb and 512 mb modules built with 256-mbit ddr2 sdrams in pg-tfbga-60 and pg-tfbga-84 chipsize packages ? standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply ? all speed grades faster than ddr2?400 comply with ddr2?400 timing specifications ? programmable cas latencies (3, 4, 5 and 6), burst length (4 & 8) and burst type ? auto refresh (cbr) and self refresh ? average refresh period 7.8 s at a t case lower than 85 c, 3.9 s between 85 c and 95 c ? programmable self refres h rate via emrs2 setting ? all inputs and outputs sstl_18 compatible ? off-chip driver impedance adjustment (ocd) and on-die termination (odt) ? serial presence detect with e 2 prom ? udimm dimensions (nominal): 30 mm high, 133.35 mm wide ? based on standard reference la youts raw card ?a?, ?c?, ?d?, ?e?, ?f? and ?g? ? rohs compliant products 1) table 1 performance table 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed code ?25f ?2.5 ?3 ?3s ?3.7 ?5 unit speed grade pc2?6400 5?5?5 pc2?6400 6?6?6 pc2?5300 4?4?4 pc2?5300 5?5?5 pc2?4200 4?4?4 pc2?3200 3?3?3 ? max. clock frequency @cl6 f ck6 400 400 ? ? ? ? mhz @cl5 f ck5 400 333 333 333 266 200 mhz @cl4 f ck4 266 266 333 266 266 200 mhz @cl3 f ck3 200 200 200 200 200 200 mhz min. ras-cas-delay t rcd 12.51512151515ns min. row precharge time t rp 12.51512151515ns min. row active time t ras 45 45 45 45 45 40 ns min. row cycle time t rc 57.56057606055ns internet data sheet rev. 1.41, 2006-11 4 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 1.2 description the qimonda hys[64/72]t[ 16/32/64]0xxhu?[2.5/../5]?a module family are unbuffered dimm modules ?udimms? with 30,0 mm height based on ddr2 technology. dimms are available as non-ecc modules in 16m 64 (128mb), 32m 64 (256mb), 64m 64 (512mb) and as ecc modules in 32m 72 (256mb), 64m 72 (512mb) organization and density, intended for mounting into 240-pin connector sockets. the memory array is designed with 256-mbit double-data- rate-two (ddr2) synchronous drams. decoupling capacitors are mounted on the pcb board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration da ta and are write protected; the second 128 bytes are available to the customer. table 2 ordering information for rohs compliant products product type 1) compliance code 2) description sdram technology pc2?6400 hys64t32001hu?2.5?a 256mb 1rx8 pc2?6400u?666?12?d0 1 rank, non-ecc 256 mbit (x8) hys64t64020hu?2.5?a 512mb 2rx8 pc2?6400u?666 ?12?e0 2 ranks, non-ecc 256 mbit (x8) hys72t32000hu?2.5?a 256mb 1rx8 pc2?6400e?666?12?f0 1 rank, ecc 256 mbit (x8) hys72t64020hu?2.5?a 512mb 2rx8 pc2?6400e? 666?12?g0 2 ranks, ecc 256 mbit (x8) hys64t32001hu?25f?a 256mb 1rx8 pc2?6400u?555?12?d0 1 rank, non-ecc 256 mbit (x8) hys64t64020hu?25f?a 512mb 2rx8 pc2?6400u?555?12?e0 2 ranks, non-ecc 256 mbit (x8) hys72t32000hu?25f?a 256mb 1rx8 pc2?6400e?555?12?f0 1 rank, ecc 256 mbit (x8) hys72t64020hu?25f?a 512mb 2rx8 pc2?6400e?555?12?g0 2 ranks, ecc 256 mbit (x8) pc2?5300 hys64t32001hu?3?a 256mb 1rx8 pc2?5300u?444?12?d0 1 rank, non-ecc 256 mbit (x8) hys64t64020hu?3?a 512mb 2rx8 pc2?5300u?444?12?e0 2 ranks, non-ecc 256 mbit (x8) hys72t32000hu?3?a 256mb 1rx8 pc2?5300e?444?12?f0 1 rank, ecc 256 mbit (x8) hys72t64020hu?3?a 512mb 2rx8 pc2?5300e?444?12?g0 2 ranks, ecc 256 mbit (x8) hys64t32001hu?3s?a 256mb 1rx8 pc2?5300u?555?12?d0 1 rank, non-ecc 256 mbit (x8) hys64t64020hu?3s?a 512mb 2rx8 pc2?5300u?555 ?12?e0 2 ranks, non-ecc 256 mbit (x8) hys72t32000hu?3s?a 256mb 1rx8 pc2?5300e?555?12?f0 1 rank, ecc 256 mbit (x8) hys72t64020hu?3s?a 512mb 2rx8 pc2?5300e ?555?12?g0 2 ranks,ecc 256 mbit (x8) pc2?4200 hys64t16000hu?3.7?a 128mb 1rx16 pc2?4200u?444?11?c1 1 rank, non-ecc 256 mbit (x16) hys64t32001hu?3.7?a 256mb 1rx8 pc2?4200u?444?11?a1 1 rank, non-ecc 256 mbit (x8) hys72t32000hu?3.7?a 256mb 1rx8 pc2?4200e?444?11?a1 1 rank, ecc 256 mbit (x8) hys64t64020hu?3.7?a 512mb 2rx8 pc2?4200u?444 ?12?e1 2 ranks, non-ecc 256 mbit (x8) internet data sheet rev. 1.41, 2006-11 5 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 3 address format table 4 components on modules pc2?3200 hys64t16000hu?5?a 128mb 1rx16 pc2?3200u?333?11?c1 1 rank, non-ecc 256 mbit (x16) hys64t32001hu?5?a 256mb 1rx8 pc2?3200u?333?11?a1 1 rank, non-ecc 256 mbit (x8) hys72t32000hu?5?a 256mb 1rx8 pc2?3200e?333?11?a1 1 rank, ecc 256 mbit (x8) 1) all product types end with a place code, des ignating the silicon die revision. exampl e: hys64t16000hu?3.7?a, indicating rev. ?a? dies are used for ddr2 sdram components. for all qimonda ddr2 module and component nomenclature see chapter 6 of this data sheet. 2) the compliance code is printed on the module label and describes the speed grade, for example ?pc2?4200u?444?11?c1?, where 4200u means unbuffered dimm modules with 4.26 gb/sec module b andwidth and ?444-11? means column address strobe (cas) latency = 4, row column delay (rcd) latency = 4 and row precharge (rp) latency = 4 using the latest jedec spd revision 1.1 and produced on the raw card ?c?. dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/column bits raw card 128 mbyte 16m 64 1 non-ecc 4 13/2/9 c 256 mbyte 32m 64 1 non-ecc 8 13/2/10 a,d 32m 72 1 ecc 9 13/2/10 a,f 512 mbyte 64m 64 2 non-ecc 16 13/2/10 e 64m 72 2 ecc 18 13/2/10 g product type 1) 1) green product dram components 1) dram density dram organisation note 2) 2) for a detailed description of all functionalities of the dram components on these modules see the component data sheet. hys64t16000hu hyb18t256160af 256 mbit 16m 16 hys64t32001hu hyb18t256800af 256 mbit 32m 8 hys64t64020hu hyb18t256800af 256 mbit 32m 8 hys72t32000hu hyb18t256800af 256 mbit 32m 8 hys72t64020hu hyb18t256800af 256 mbit 32m 8 product type 1) compliance code 2) description sdram technology internet data sheet rev. 1.41, 2006-11 6 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 2 pin configuration the pin configuration of the unbuffered ddr2 sdram dimm is listed by function in table 5 (240 pins). the abbreviations used in columns pin and buffer type are explained in table 6 and table 7 respectively. the pin numbering is depicted in figure 1 for non-ecc modules ( 64) and figure 2 for ecc modules ( 72). table 5 pin configuration of udimm ball no. name pin type buffer type function clock signals 185 ck0 i sstl clock signals 2:0, comple ment clock signals 2:0 137 ck1 i sstl 220 ck2 i sstl 186 ck0 i sstl 138 ck1 i sstl 221 ck2 i sstl 52 cke0 i sstl clock enable rank 1:0 note: 2 ranks module 171 cke1 i sstl nc nc ? not connected note: 1 rank module control signals 193 s0# i sstl chip select rank 1:0 note: 2 ranks module 76 s1# i sstl nc nc ? not connected note: 1 rank module 192 ras i sstl row address strobe 74 cas i sstl column addr ess strobe 73 we i sstl write enable address signals 71 ba0 i sstl bank address bus 1:0 190 ba1 i sstl 54 ba2 i sstl bank address bus 2 greater than 512mb ddr2 sdrams nc nc ? not connected less than 1gb ddr2 sdrams internet data sheet rev. 1.41, 2006-11 7 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 188 a0 i sstl address bus 12:0 183 a1 i sstl 63 a2 i sstl 182 a3 i sstl 61 a4 i sstl 60 a5 i sstl 180 a6 i sstl 58 a7 i sstl 179 a8 i sstl 177 a9 i sstl 70 a10 i sstl ap i sstl 57 a11 i sstl 176 a12 i sstl 196 a13 i sstl address signal 13 note: 1 gbit based module and 512m 4/ 8 nc nc ? not connected note: module based on 1 gbit 16 module based on 512 mbit 16 or smaller 174 a14 i sstl address signal 14 note: modules based on 2 gbit nc nc ? not connected note: modules based on 1 gbit or smaller data signals 3 dq0 i/o sstl data bus 63:0 data input/output pins 4 dq1 i/o sstl 9 dq2 i/o sstl 10 dq3 i/o sstl 122 dq4 i/o sstl 123 dq5 i/o sstl 128 dq6 i/o sstl 129 dq7 i/o sstl ball no. name pin type buffer type function internet data sheet rev. 1.41, 2006-11 8 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 12 dq8 i/o sstl data bus 63:0 data input/output pins 13 dq9 i/o sstl 21 dq10 i/o sstl 22 dq11 i/o sstl 131 dq12 i/o sstl 132 dq13 i/o sstl 140 dq14 i/o sstl 141 dq15 i/o sstl 24 dq16 i/o sstl 25 dq17 i/o sstl 30 dq18 i/o sstl 31 dq19 i/o sstl 143 dq20 i/o sstl 144 dq21 i/o sstl 149 dq22 i/o sstl 150 dq23 i/o sstl 33 dq24 i/o sstl 34 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 152 dq28 i/o sstl 153 dq29 i/o sstl 158 dq30 i/o sstl 159 dq31 i/o sstl 80 dq32 i/o sstl 81 dq33 i/o sstl 86 dq34 i/o sstl 87 dq35 i/o sstl 199 dq36 i/o sstl 200 dq37 i/o sstl 205 dq38 i/o sstl 206 dq39 i/o sstl 89 dq40 i/o sstl 90 dq41 i/o sstl 95 dq42 i/o sstl 96 dq43 i/o sstl 208 dq44 i/o sstl 209 dq45 i/o sstl 214 dq46 i/o sstl 215 dq47 i/o sstl ball no. name pin type buffer type function internet data sheet rev. 1.41, 2006-11 9 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 98 dq48 i/o sstl data bus 63:0 data input/output pins 99 dq49 i/o sstl 107 dq50 i/o sstl 108 dq51 i/o sstl 217 dq52 i/o sstl 218 dq53 i/o sstl 226 dq54 i/o sstl 227 dq55 i/o sstl 110 dq56 i/o sstl 111 dq57 i/o sstl 116 dq58 i/o sstl 117 dq59 i/o sstl 229 dq60 i/o sstl 230 dq61 i/o sstl 235 dq62 i/o sstl 236 dq63 i/o sstl check bit signals 42 cb0 i/o sstl check bit 0 note: ecc type module only nc nc ? not connected note: ecc type module only 43 cb1 i/o sstl check bit 1 note: ecc type module only nc nc ? not connected note: ecc type module only 48 cb2 i/o sstl check bit 2 note: ecc type module only nc nc ? not connected note: ecc type module only 49 cb3 i/o sstl check bit 3 note: ecc type module only nc nc ? not connected note: ecc type module only 161 cb4 i/o sstl check bit 4 note: ecc type module only nc nc ? not connected note: ecc type module only 162 cb5 i/o sstl check bit 5 note: ecc type module only nc nc ? not connected note: ecc type module only ball no. name pin type buffer type function internet data sheet rev. 1.41, 2006-11 10 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 167 cb6 i/o sstl check bit 6 note: ecc type module only nc nc ? not connected note: ecc type module only 168 cb7 i/o sstl check bit 7 note: ecc type module only nc nc ? not connected note: non-ecc module data strobe bus 7 dqs0 i/o sstl data strobe bus 8:0 16 dqs1 i/o sstl 28 dqs2 i/o sstl 37 dqs3 i/o sstl 84 dqs4 i/o sstl 93 dqs5 i/o sstl 105 dqs6 i/o sstl 114 dqs7 i/o sstl 46 dqs8 i/o sstl 6 dqs0 i/o sstl complement data strobe bus 8:0 15 dqs1 i/o sstl 27 dqs2 i/o sstl 36 dqs3 i/o sstl 83 dqs4 i/o sstl 92 dqs5 i/o sstl 104 dqs6 i/o sstl 113 dqs7 i/o sstl 45 dqs8 i/o sstl data mask signals 125 dm0 i sstl data mask bus 8:0 134 dm1 i sstl 146 dm2 i sstl 155 dm3 i sstl 202 dm4 i sstl 211 dm5 i sstl 223 dm6 i sstl 232 dm7 i sstl 164 dm8 i sstl eeprom 120 scl i cmos serial bus clock 119 sda i/o od serial bus data ball no. name pin type buffer type function internet data sheet rev. 1.41, 2006-11 11 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 239 sa0 i cmos serial address select bus 2:0 240 sa1 i cmos 101 sa2 i cmos power supplies 1 v ref ai ? i/o reference voltage 238 v ddspd pwr ? eeprom power supply 51,56,62,72,75,, 78,170,175,181,, 191,194 v ddq pwr ? i/o driver power supply 53,59,64,67,69,, 172,178,184,187, 189,197 v dd pwr ? power supply 2,5,8,11,14,17,, 20,23,26,29,32, 35,38,41,44,47,, 50,65,66,79,82, 85,88,91,94,97,, 100,103,106, 109,112,115,118, 121,124,127,, 130,133,136,139, 142,145,148,, 151,154,157,160, 163,166,169, 198,201,204,207, 210,213,216,, 219,222,225,228, 231,234,237 v ss gnd ? ground plane other pins 195 odt0 i sstl on-die termination control 0 77 odt1 i sstl on-die termination control 1 note: 2 rank modules nc nc ? not connected note: 1 rank modules 18,19,55,68,102,1 26,135,147, 156,165,173,203, 212, 224,233 nc nc ? not connected ball no. name pin type buffer type function internet data sheet rev. 1.41, 2006-11 12 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 6 abbreviations for pin type table 7 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tri-state, and allows multiple devices to share as a wire-or. internet data sheet rev. 1.41, 2006-11 13 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules figure 1 pin configuration udimm 64 (240 pin) 0 3 3 7 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 1 & 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 1 & 9 6 6 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 1 & 9 6 6 1 & 1 & 9 6 6 & . ( 1 & % $ 9 ' ' 4 $ $ 9 ' ' 4 9 ' ' 9 6 6 1 & $ $ 3 9 ' ' 4 & $ 6 1 & 6 9 ' ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 6 & / 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 1 & 1 & 9 6 6 1 & 9 ' ' 4 9 ' ' 1 & $ 9 ' ' $ $ 9 6 6 9 ' ' 9 ' ' % $ : ( 9 ' ' 4 2 ' 7 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 6 $ 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 6 ' $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & & . 9 6 6 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 & . ' 4 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 1 & 1 & 9 6 6 1 & 9 ' ' 4 9 ' ' $ $ 9 ' ' $ $ 9 ' ' & . $ % $ 5 $ 6 9 ' ' 4 1 & $ 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 & . 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 9 ' ' 6 3 ' 6 $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 1 & 9 6 6 1 & 1 & 9 6 6 & . ( 1 & 9 ' ' 4 $ $ 9 ' ' 4 $ & . 9 ' ' 9 ' ' 9 ' ' 4 6 2 ' 7 9 ' ' ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 & . ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 6 $ ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( internet data sheet rev. 1.41, 2006-11 14 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules figure 2 pin configuration udimm 72 (240 pin) 0 3 3 7 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 1 & 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 1 & 9 6 6 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 ' 4 6 9 6 6 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 & % 9 6 6 ' 4 6 & % 9 6 6 & . ( 1 & % $ 9 ' ' 4 $ $ 9 ' ' 4 9 ' ' 9 6 6 1 & $ $ 3 9 ' ' 4 & $ 6 1 & 6 9 ' ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 6 & / 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 & % ' 4 6 9 6 6 & % 9 ' ' 4 9 ' ' 1 & $ 9 ' ' $ $ 9 6 6 9 ' ' 9 ' ' % $ : ( 9 ' ' 4 2 ' 7 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 9 6 6 9 6 6 ' 4 6 $ 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 6 ' $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & & . 9 6 6 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 1 & & . ' 4 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 & % ' 0 9 6 6 & % 9 ' ' 4 9 ' ' $ $ 9 ' ' $ $ 9 ' ' & . $ % $ 5 $ 6 9 ' ' 4 1 & $ 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 & . 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 9 ' ' 6 3 ' 6 $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 & % 9 6 6 1 & & % 9 6 6 & . ( 1 & 9 ' ' 4 $ $ 9 ' ' 4 $ & . 9 ' ' 9 ' ' 9 ' ' 4 6 2 ' 7 9 ' ' ' 4 9 6 6 1 & ' 4 9 6 6 ' 4 ' 0 9 6 6 ' 4 ' 4 9 6 6 & . ' 0 9 6 6 ' 4 ' 4 9 6 6 1 & ' 4 9 6 6 6 $ ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( internet data sheet rev. 1.41, 2006-11 15 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 3 electrical characteristics this chapter lists the el ectrical characteristics. 3.1 absolute maximum ratings caution is needed not to exceed absolute maximum ratings of the dram device listed in table 8 at any time. table 8 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. table 9 dram component operating temperature range symbol parameter rating unit note min. max. v dd voltage on v dd pin relative to v ss ?1.0 +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 +2.3 v 1)2) v ddl voltage on v ddl pin relative to v ss ?0.5 +2.3 v 1)2) v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v 1) t stg storage temperature ?55 +100 c 1)2) 2) storage temperature is the case surface temperature on the center/top side of the dram. symbol parameter rating unit note min. max. t oper operating temperature 0 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dr am specification will be suppor ted. during operation, the dr am case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c tcase tem perature range, the high temperature self refresh has to be enable d by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50% internet data sheet rev. 1.41, 2006-11 16 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 3.2 dc operating conditions this chapter describes the dc operating characteristics. table 10 operating conditions table 11 supply voltage levels an d dc operating conditions parameter symbol values unit note min. max. operating temperature (ambient) t opr 0+65 c dram case temperature t case 0+95 c 1)2)3)4) 1) dram component case temperature is the surface temperature in the center on the top side of any of the drams. 2) within the dram component case temperature range all dram specificat ions will be supported 3) above 85 c dram case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c t case temperature range, the high temperature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50%. storage temperature t stg ? 50 +100 c barometric pressure (operating & storage) pbar +69 +105 kpa 5) 5) up to 3000 m. operating humidity (relative) h opr 10 90 % parameter symbol values unit note min. typ. max. device supply voltage v dd 1.7 1.8 1.9 v output supply voltage v ddq 1.7 1.8 1.9 v 1) 1) under all conditions, v ddq must be less than or equal to v dd input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc). v ref is also expected to track noise in v ddq . spd supply voltage v ddspd 1.7 ? 3.6 v dc input logic high v ih(dc) v ref +0.125 ? v ddq +0.3 v dc input logic low v il (dc ) ? 0.30 ? v ref ? 0.125 v in / output leakage current i l ? 5 ? 5 a 3) 3) input voltage for any connector pin under test of 0 v v in v ddq + 0.3 v; all other pins at 0 v. current is per pin internet data sheet rev. 1.41, 2006-11 17 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 3.3 timing characteristics this chapter describes the ac characteristics. 3.3.1 speed grade definitions all speed grades faster than ddr2-ddr400b comply with ddr2-ddr400b timing specifications ( t ck = 5ns with t ras = 40ns). speed grade definition for ddr2-800 ( table 12 ), ddr2-667( table 13 ), ddr2-533c( table 14 ) and ddr2-400b( table 15 ). table 12 speed grade definition speed bins for ddr2?800 speed grade ddr2?800d ddr2?800e unit note qag sort name ?2.5f ?2.5 cas-rcd-rp latencies 5?5?5 6?6?6 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 58 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 2.5 8 3 8 ns 1)2)3)4) @ cl = 6 t ck 2.5 8 2.5 8 ns 1)2)3)4) row active time t ras 45 70000 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 57.5 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 12.5 ? 15 ? ns 1)2)3)4) row precharge time t rp 12.5 ? 15 ? ns 1)2)3)4) internet data sheet rev. 1.41, 2006-11 18 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 13 speed grade definition speed bins for ddr2?667 table 14 speed grade definition speed bins for ddr2?533c speed grade ddr2?667c ddr2?667d unit note qag sort name ?3 ?3s cas-rcd-rp latencies 4?4?4 5?5?5 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 5858ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) . 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3 8 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 3838ns 1)2)3)4) row active time t ras 45 70000 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devi ce can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 57 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 12 ? 15 ? ns 1)2)3)4) row precharge time t rp 12 ? 15 ? ns 1)2)3)4) speed grade ddr2?533c unit note qag sort name ?3.7 cas-rcd-rp latencies 4?4?4 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode.timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 3.75 8 ns 1)2)3)4) row active time t ras 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4) internet data sheet rev. 1.41, 2006-11 19 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 15 speed grade defi nition speed bi ns for ddr2-400b speed grade ddr2?400b unit note qag sort name ?5 cas-rcd-rp latencies 3?3?3 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) . 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 58 ns 1)2)3)4) @ cl = 5 t ck 58 ns 1)2)3)4) row active time t ras 40 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 55 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4) internet data sheet rev. 1.41, 2006-11 20 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 3.3.2 component ac timing parameters timing parameters for ddr2-800 ( table 16 ), ddr2-667( table 17 ), ddr2-533( table 18 ) and ddr2-400( table 19 ). table 16 dram component timing parameter by speed grade - ddr2?800 parameter symbol ddr2?800 unit note 1)2)3)4)5)6)7) 8) min. max. dq output access time from ck / ck t ac ?400 +400 ps 9) dqs output access time from ck / ck t dqsck ?350 +350 ps 9) average clock high pulse width t ch.avg 0.48 0.52 t ck.avg 10)11) average clock low pulse width t cl.avg 0.48 0.52 t ck.avg 10)11) average clock period t ck.avg 2500 8000 ps 10)11) dq and dm input setup time t ds.base 50 ? ps 12)13)14) dq and dm input hold time t dh.base 125 ? ps 13)14)15) control & address input pulse width for each input t ipw 0.6 ? t ck.avg dq and dm input pulse width for each input t dipw 0.35 ? t ck.avg data-out high-impedance time from ck / ck t hz ? t ac.max ps 9)16) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max ps 9)16) dq low impedance time from ck/ck t lz.dq 2 t ac.min t ac.max ps 9)16) dqs-dq skew for dqs & associated dq signals t dqsq ? 200 ps 17) ck half pulse width t hp min( t ch.abs , t cl.abs ) __ ps 18) dq hold skew factor t qhs ? 300 ps 19) dq/dqs output hold time from dqs t qh t hp ? t qhs ?ps 20) write command to dqs associated clock edges wl rl ? 1 nck dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 t ck.avg 21) dqs input high pulse width t dqsh 0.35 ? t ck.avg dqs input low pulse width t dqsl 0.35 ? t ck.avg dqs falling edge to ck setup time t dss 0.2 ? t ck.avg 21) dqs falling edge hold time from ck t dsh 0.2 ? t ck.avg 21) write postamble t wpst 0.4 0.6 t ck.avg write preamble t wpre 0.35 ? t ck.avg address and control input setup time t is.base 175 ? ps 22)23) address and control input hold time t ih.base 250 ? ps 23)24) read preamble t rpre 0.9 1.1 t ck.avg 25)26) read postamble t rpst 0.4 0.6 t ck.avg 25)27) cas to cas command delay t ccd 2?nck write recovery time t wr 15 ? ns 28) auto-precharge write recovery + precharge time t dal wr + t nrp ?nck 28)29) internal write to read command delay t wtr 7.5 ? ns 28)30) internet data sheet rev. 1.41, 2006-11 21 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules internal read to precharge command delay t rtp 7.5 ? ns 28) exit self-refresh to a non-read command t xsnr t rfc +10 ? ns 28) exit self-refresh to read command t xsrd 200 ? nck exit precharge power-down to any valid command (other than nop or deselect) t xp 2?nck exit power down to read command t xard 2?nck exit active power-down mode to read command (slow exit, lower power) t xards 8 ? al ? nck cke minimum pulse width ( high and low pulse width) t cke 3?nck 31) mode register set command cycle time t mrd 2?nck mrs command to odt update delay t mod 012ns 28) ocd drive mode output delay t oit 012ns 28) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck .avg + t ih ?ns 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. see notes 5)6)7)8) 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . 9) when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 10) input clock jitter spec parameter. these parameters are refe rred to as 'input clock jitter s pec parameters' and these param eters apply to ddr2?667 and ddr2?800 only. the jitter specified is a random jitter meeting a gaussian distribution. 11) these parameters are specified per their average values, however it is understood t hat the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of spec values are to be used for calculations ). 12) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is referenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a ri sing signal, and from the input signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal appl ied to the device under test. dqs, dqs signals must be monotonic between v il(dc)max and v ih(dc)min . see figure 4 . 13) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 14) these parameters are measured from a data signal ((l/u)dm, (l/u )dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 15) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is refer enced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see figure 4 . parameter symbol ddr2?800 unit note 1)2)3)4)5)6)7) 8) min. max. internet data sheet rev. 1.41, 2006-11 22 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 16) t hz and t lz transitions occur in the same access time as valid data tran sitions. these parameters are referenced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 17) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. 18) t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. 19) t qhs accounts for: 1) the pulse duration distortion of on-ch ip clock circuits, which repr esents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to da ta pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers. 20) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse widt h distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 21) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 22) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see figure 5 . 23) these parameters are measured from a comm and/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 24) input waveform timing is referenced from the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see figure 5 . 25) t rpst end point and t rpre begin point are not referenced to a specific voltage le vel but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). figure 3 shows a method to calculate these point s when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement poi nts are not critical as long as the calculation is consistent. 26) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!). 27) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 28) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 29) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 30) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. 31) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 cloc ks of registration. thus, after any cke trans ition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . internet data sheet rev. 1.41, 2006-11 23 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 17 dram component timing parameter by speed grade - ddr2?667 parameter symbol ddr2?667 unit note 1)2)3)4)5)6)7) 8) min. max. dq output access time from ck / ck t ac ?450 +450 ps 9) dqs output access time from ck / ck t dqsck ?400 +400 ps 9) average clock high pulse width t ch.avg 0.48 0.52 t ck.avg 10)11) average clock low pulse width t cl.avg 0.48 0.52 t ck.avg 10)11) average clock period t ck.avg 3000 8000 ps dq and dm input setup time t ds.base 100 ? ps 12)13)14) dq and dm input hold time t dh.base 175 ? ps 13)14)15) control & address input pulse width for each input t ipw 0.6 ? t ck.avg dq and dm input pulse width for each input t dipw 0.35 ? t ck.avg data-out high-impedance time from ck / ck t hz ? t ac.max ps 9)16) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max ps 9)16) dq low impedance time from ck/ck t lz.dq 2x t ac.min t ac.max ps 9)16) dqs-dq skew for dqs & associated dq signals t dqsq ? 240 ps 17) ck half pulse width t hp min( t ch.abs , t cl.abs ) __ ps 18) dq hold skew factor t qhs ? 340 ps 19) dq/dqs output hold time from dqs t qh t hp ? t qhs ?ps 20) write command to dqs associated clock edges wl rl?1 nck dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 t ck.avg 21) dqs input high pulse width t dqsh 0.35 ? t ck.avg dqs input low pulse width t dqsl 0.35 ? t ck.avg dqs falling edge to ck setup time t dss 0.2 ? t ck.avg 21) dqs falling edge hold time from ck t dsh 0.2 ? t ck.avg 21) write postamble t wpst 0.4 0.6 t ck.avg write preamble t wpre 0.35 ? t ck.avg address and control input setup time t is.base 200 ? ps 22)23) address and control input hold time t ih.base 275 ? ps 23)24) read preamble t rpre 0.9 1.1 t ck.avg 25)26) read postamble t rpst 0.4 0.6 t ck.avg 25)27) cas to cas command delay t ccd 2?nck write recovery time t wr 15 ? ns 28) auto-precharge write recovery + precharge time t dal wr + t nrp ?nck 28)29) internal write to read command delay t wtr 7.5 ? ns 28)30) internal read to precharge command delay t rtp 7.5 ? ns 28) exit self-refresh to a non-read command t xsnr t rfc +10 ? ns 28) exit self-refresh to read command t xsrd 200 ? nck internet data sheet rev. 1.41, 2006-11 24 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules exit precharge power-down to any valid command (other than nop or deselect) t xp 2?nck exit power down to read command t xard 2?nck exit active power-down mode to read command (slow exit, lower power) t xards 7 ? al ? nck cke minimum pulse width ( high and low pulse width) t cke 3?nck 31) mode register set command cycle time t mrd 2?nck mrs command to odt update delay t mod 012ns 28) ocd drive mode output delay t oit 012ns 28) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck .avg + t ih ?ns 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. see notes 5)6)7)8) 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . 9) when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 10) input clock jitter spec parameter. these parameters are refe rred to as 'input clock jitter s pec parameters' and these param eters apply to ddr2?667 and ddr2?800 only. the jitter specified is a random jitter meeting a gaussian distribution. 11) these parameters are specified per their average values, however it is understood t hat the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of spec values are to be used for calculations ). 12) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is referenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a ri sing signal, and from the input signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal appl ied to the device under test. dqs, dqs signals must be monotonic between v il(dc)max and v ih(dc)min . see figure 4 . 13) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 14) these parameters are measured from a data signal ((l/u)dm, (l/u )dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 15) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is refer enced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see figure 4 . 16) t hz and t lz transitions occur in the same access time as valid data tran sitions. these parameters are referenced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 17) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. parameter symbol ddr2?667 unit note 1)2)3)4)5)6)7) 8) min. max. internet data sheet rev. 1.41, 2006-11 25 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 18) t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. 19) t qhs accounts for: 1) the pulse duration distortion of on-ch ip clock circuits, which repr esents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to da ta pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers. 20) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse widt h distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 21) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 22) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see figure 5 . 23) these parameters are measured from a comm and/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 24) input waveform timing is referenced from the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see figure 5 . 25) t rpst end point and t rpre begin point are not referenced to a specific voltage le vel but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). figure 3 shows a method to calculate these point s when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement poi nts are not critical as long as the calculation is consistent. 26) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!). 27) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 28) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 29) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 30) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. 31) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 cloc ks of registration. thus, after any cke trans ition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . internet data sheet rev. 1.41, 2006-11 26 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules figure 3 method for calculating transitions and endpoint figure 4 differential input waveform timing - t ds and t ds figure 5 differential input waveform timing - t ls and t lh w + = w 5 3 6 7 h q g s r l q w 7 7 9 2 + [ p 9 9 2 + [ p 9 9 2 / [ p 9 9 2 / [ p 9 w / = w 5 3 5 ( e h j l q s r l q w 7 7 9 7 7 [ p 9 9 7 7 [ p 9 9 7 7 [ p 9 9 7 7 [ p 9 w / = w 5 3 5 ( e h j l q s r l q w 7 7 w + = w 5 3 6 7 h q g s r l q w 7 7 w ' 6 9 ' ' 4 9 , + d f p l q 9 , + g f p l q 9 5 ( ) g f 9 , / g f p d [ 9 , / d f p d [ 9 6 6 ' 4 6 ' 4 6 w ' + w ' 6 w ' + w , 6 9 ' ' 4 9 , + d f p l q 9 , + g f p l q 9 5 ( ) g f 9 , / g f p d [ 9 , / d f p d [ 9 6 6 & . & . w , + w , 6 w , + internet data sheet rev. 1.41, 2006-11 27 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 18 dram component timing parameter by speed grade - ddr2?533 parameter symbol ddr2?533 unit note 1)2)3)4)5) 6)7) min. max. dq output access time from ck / ck t ac ?500 +500 ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 8)18) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?ns 9) dq and dm input hold time (differential data strobe) t dh (base) 225 ? ps 10) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps 11) dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ?450 + 450 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ps 11) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setup time (differential data strobe) t ds (base) 100 ? ps 11) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps 11) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck clock half period t hp min. ( t cl, t ch )? 12) data-out high-impedance time from ck / ck t hz ? t ac.max ps 13) address and control input hold time t ih (base) 375 ? ps 11) address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 250 ? ps 11) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps 14) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 14) mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ?? data hold skew factor t qhs ? 400 ps internet data sheet rev. 1.41, 2006-11 28 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules average periodic refresh interval t refi ?7.8 s 14)15) ?3.9 s 16)18) auto-refresh to active/auto-refresh command period t rfc 75 ? ns 17) precharge-all (4 banks) command period t rp t rp +1 t ck ?ns precharge-all (8 banks) command period t rp 15 + 1 t ck ?ns read preamble t rpre 0.9 1.1 t ck 14) read postamble t rpst 0.40 0.60 t ck 14) active bank a to active bank b command period t rrd 7.5 ? ns 14)18) 10 ? ns 16)20) internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 ? t ck write postamble t wpst 0.40 0.60 t ck 19) write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck ? t ck 20) internal write to read command delay t wtr 7.5 ? ns 21) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 22) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 22) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 5)6)7)8) 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 9) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) for timing definition, refer to the component data sheet. 11) consists of data pin skew and output pattern effects, and p-ch annel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 12) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). parameter symbol ddr2?533 unit note 1)2)3)4)5) 6)7) min. max. internet data sheet rev. 1.41, 2006-11 29 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 19 dram component timing parameter by speed grade - ddr2-400 13) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the devic e output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 14) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 15) 0 c t case 85 c 16) 85 c < t case 95 c 17) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 18) the t rrd timing parameter depends on the page size of the dram organization. see table 2 ?ordering information for rohs compliant products? on page 4 . 19) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 21) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 22) user can choose two different active pow er-down modes for additional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. parameter symbol ddr2?400 unit note 1)2)3)4)5) 6)7) min. max. dq output access time from ck / ck t ac ?600 +600 ps cas a to cas b command period t ccd 2? t ck ck, ck high-level width t ch 0.45 0.55 t ck cke minimum high and low pulse width t cke 3? t ck ck, ck low-level width t cl 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 8)22) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?ns 9) dq and dm input hold time (differential data strobe) t dh (base) 275 ? ps 10) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps 11) dq and dm input pulse width (each input) t dipw 0.35 ? t ck dqs output access time from ck / ck t dqsck ?500 + 500 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 350 ps 11) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck dq and dm input setup time (differential data strobe) t ds (base) 150 ? ps 11) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps 11) internet data sheet rev. 1.41, 2006-11 30 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck clock half period t hp min. ( t cl, t ch ) 12) data-out high-impedance time from ck / ck t hz ? t ac.max ps 13) address and control input hold time t ih (base) 475 ? ps 11) address and control input pulse width (each input) t ipw 0.6 ? t ck address and control input setup time t is (base) 350 ? ps 11) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps 14) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 14) mode register set command cycle time t mrd 2? t ck ocd drive mode output delay t oit 012ns data output hold time from dqs t qh t hp ? t qhs ? data hold skew factor t qhs ? 450 ps average periodic refresh interval t refi ?7.8 s 14)15) ? 3.9 s 16)18) auto-refresh to active/auto-refresh command period t rfc 75 ? ns 17) precharge-all (4 banks) command period t rp t rp +1 t ck ?ns precharge-all (8 banks) command period t rp 15 + 1 t ck ?ns read preamble t rpre 0.9 1.1 t ck 14) read postamble t rpst 0.40 0.60 t ck 14) active bank a to active bank b command period t rrd 7.5 ? ns 14)18) 10 ? ns 16)20) internal read to precharge command delay t rtp 7.5 ? ns write preamble t wpre 0.25 ? t ck write postamble t wpst 0.40 0.60 t ck 19) write recovery time for write without auto- precharge t wr 15 ? ns write recovery time for write with auto- precharge wr t wr / t ck ? t ck 20) internal write to read command delay t wtr 10 ? ns 21) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 22) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 22) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? t ck parameter symbol ddr2?400 unit note 1)2)3)4)5) 6)7) min. max. internet data sheet rev. 1.41, 2006-11 31 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 5)6)7)8) 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 9) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) for timing definition, refer to the component data sheet. 11) consists of data pin skew and output pattern effects, and p-ch annel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 12) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 13) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the devic e output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 14) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 15) 0 c t case 85 c 16) 85 c < t case 95 c 17) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 18) the t rrd timing parameter depends on the page size of the dram organization. see table 2 ?ordering information for rohs compliant products? on page 4 . 19) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 21) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 22) user can choose two different active pow er-down modes for additional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. internet data sheet rev. 1.41, 2006-11 32 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 3.3.3 odt ac electrical characteristics ? table 20 ?odt ac character. and operating conditions for ddr2-667 & ddr2-800? on page 32 ? table 21 ?odt ac character. and operating conditions for ddr2-533 & ddr2-400? on page 33 table 20 odt ac character. and operating co nditions for ddr2 -667 & ddr2-800 symbol parameter / cond ition values unit note min. max. t aond odt turn-on delay 2 2 nck 1) 1) new units, ' t ck.avg ' and 'nck', are introduced in ddr2-667 and ddr2-800. unit ' t ck.avg ' represents the actual t ck.avg of the input clock under operation. unit 'nck' represents one clock cycle of the input clock, counting the actual clock edges. note that in ddr2-4 00 and ddr2-533, ' t ck ' is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 t ck.avg + t epr.2per(min) . t aon odt turn-on t ac.min t ac.max + 0.7 ns ns 1)2) 2) odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is w hen the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-667/800, t aond is 2 clock cycles after the clock edge that registered a first odt high counting the actual input clock edges. t aonpd odt turn-on (pow er-down modes) t ac.min +2 ns 2 t ck + t ac.max + 1 ns ns 1) t aofd odt turn-off delay 2.5 2.5 nck 1) t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 1)3) 3) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-667/800,if t ck.avg = 3 ns is assumed, t aofd = 1.5 ns (0.5 3 ns) after the second trailing clock edge counting from the clock edge that registered a first odt low and by counting the actual input clock edge. t aofpd odt turn-off (p ower-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns 1) t anpd odt to power down mode entry latency 3 ? nck 1) t axpd odt power down exit latency 8 ? nck 1) internet data sheet rev. 1.41, 2006-11 33 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 21 odt ac character. and operating co nditions for ddr2 -533 & ddr2-400 symbol parameter / cond ition values unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is w hen the odt resistance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2-400/533, t aond is 10 ns (= 2 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aonpd odt turn-on (pow er-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . both are measured from t aofd , which is interpreted differently per speed bin. for ddr2-400/533, t aofd is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first odt high if t ck = 5 ns. t aofpd odt turn-off (p ower-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck internet data sheet rev. 1.41, 2006-11 34 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 3.4 i dd specifications and conditions list of tables defining i dd specifications and conditions. ? table 22 ?idd measurement conditions? on page 34 ? table 23 ?definitions for idd? on page 35 ? table 24 ?i dd specification for hys[64/72]t[32/64]xxxhu-[2.5/2.5f]?a? on page 36 ? table 25 ?i dd specification for hys[64/72]t[32/64]xxxhu-[3/3s]?a? on page 37 ? table 26 ?i dd specification for hys[64/72]t[16/32/64]xxxhu-[3.7/5]?a? on page 38 table 22 i dd measurement conditions parameter symbol note 1)2)3)4)5) operating current 0 one bank active - precharge; t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , t rcd = t rcd.min , al = 0, cl = cl min ; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are switching, databus inputs are switching. i dd2n precharge power-down current other control and address inputs are st able, data bus inputs are floating. i dd2p precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are stable, data bus inputs are floating. i dd2q active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max , t rp = t rp.min ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n active power-down current all banks open; t ck = t ck.min , cke is low; other control and addre ss inputs are stable, data bus inputs are floating. mrs a12 bit is se t to low (fast power-down exit); i dd3p(0) active power-down current all banks open; t ck = t ck.min , cke is low; other control and addre ss inputs are stable, data bus inputs are floating. mrs a12 bit is set to high (slow power-down exit); i dd3p(1) operating current - burst read all banks open; continuous burst re ads; bl = 4; al = 0, cl = cl min ; t ck = t ckmin ; t ras = t rasmax ; t rp = t rpmin ; cke is high, cs is high between valid co mmands; address inputs are switching; data bus inputs are switching; i out = 0ma. i dd4r 6) operating current - burst write all banks open; continuous burst wr ites; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max. , t rp = t rp.max ; cke is high, cs is high between valid commands. address inputs are switching; data bus in puts are switching; i dd4w burst refresh current t ck = t ck.min ., refresh command every t rfc = t rfc.min interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b internet data sheet rev. 1.41, 2006-11 35 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 23 definitions for i dd distributed refresh current t ck = t ck.min. , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5d self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 6) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) i dd specifications are tested after t he device is properly initialized and i dd parameter are specified with odt disabled. 3) definitions for i dd see table 23 . 4) for two rank modules: for all active current meas urements the other rank is in precharge power-down mode i dd2p . 5) for details and notes see the relevant qimonda component data sheet. 6) i dd1 , i dd4r and i dd7 current measurements are defined with the outputs disabled ( i out = 0 ma). to achieve this on module level the output buffers can be disabled using an emrs(1) (extended m ode register command) by setting a12 bit to high. parameter description low v in v il(ac).max , high is defined as v in v ih(ac).min stable inputs are stable at a high or low level floating inputs are v ref = v ddq /2 switching inputs are changing between hi gh and low every other clock (once per 2 cycles) for address and control signals, and inputs changing between high and low ever y other data transfer (once per cycle) for dq signals not including mask or strobes parameter symbol note 1)2)3)4)5) internet data sheet rev. 1.41, 2006-11 36 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 24 i dd specification for hys[64/72]t[32/64]xxxhu-[2.5/2.5f]?a product type hys64t32001hu?2.5?a hys64t64020hu?2.5?a hys72t32000hu?2.5?a hys72t64020hu?2.5?a hys64t32001hu?25f?a hys64t64020hu?25f?a hys72t32000hu?25f?a hys72t64020hu?25f?a unit note 1) 1) calculated values from component data. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 256mb 512mb 256mb 512mb 256mb 512mb 1 rank 2 ranks 1 rank 2 ranks 1 rank 2 ranks 1 rank 2 ranks x64 x64 x72 x72 x64 x64 x72 x72 ?2.5 ?2.5 ?2.5 ?2.5 ?25f ?25f ?25f ?25f symbol max. max. max. max. max. max. max. max. i dd0 600 640 680 720 640 680 720 770 ma 2) 2) the other rank is in i dd2p precharge power-down current mode. i dd1 680 720 770 810 720 760 810 860 ma 2) i dd2n 400 800 450 900 400 800 450 900 ma 3) 3) both ranks are in the same i dd current mode. i dd2p 40 80 50 90 40 80 50 90 ma 3) i dd2q 280 560 320 630 280 560 320 630 ma 3) i dd3p( mrs = 0) 180 350 200 400 180 350 200 400 ma 3) i dd3p( mrs = 1) 40 80 50 90 40 80 50 90 ma 3) i dd3n 400 800 450 900 400 800 450 900 ma 3) i dd4r 1000 1040 1130 1170 1000 1040 1130 1170 ma 2) i dd4w 1080 1120 1220 1260 1080 1120 1220 1260 ma 2) i dd5b 760 800 860 900 760 800 860 900 ma 2) i dd5d 50 100 50 110 50 100 50 110 ma 3)4) 4) i dd5d and i dd6 values are for 0 c t case 85 c. i dd6 32 64 36 72 32 64 36 72 ma 3)4) i dd7 1240 1280 1400 1440 1320 1360 1485 1530 ma 2) internet data sheet rev. 1.41, 2006-11 37 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 25 i dd specification for hys[64/72]t[32/64]xxxhu-[3/3s]?a product type hys64t32001hu?3?a hys64t64020hu?3?a hys72t32000hu?3?a hys72t64020hu?3?a hys64t32001hu?3s?a hys64t64020hu?3s?a hys72t32000hu?3s?a hys72t64020hu?3s?a unit note 1) 1) calculated values from component data. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled. organization 256 mb 512 mb 256 mb 512 mb 256 mb 512 mb 256 mb 512 mb 1 rank 2 ranks 1 rank 2 ranks 1 rank 2 ranks 1 rank 2 ranks x64 x64 x72 x72 x64 x64 x72 x72 ?3 ?3 ?3 ?3 ?3s ?3s ?3s ?3s symbol max. max. max. max. max. max. max. max. i dd0 520 560 590 630 500 540 560 600 ma 2) 2) the other rank is in i dd2p precharge power-down current mode i dd1 600 640 680 720 570 610 640 680 ma 2) i dd2n 360 720 410 810 360 720 410 810 ma 3) 3) both ranks are in the same i dd current mode i dd2p 40 80 50 90 40 80 50 90 ma 3) i dd2q 240 480 270 540 240 480 270 540 ma 3) i dd3p( mrs = 0) 150 300 170 340 150 300 170 340 ma 3) i dd3p( mrs = 1) 40 80 50 90 40 80 50 90 ma 3) i dd3n 360 720 410 810 360 720 410 810 ma 3) i dd4r 880 920 990 1040 880 920 990 1040 ma 2) i dd4w 920 960 1040 1080 920 960 1040 1080 ma 2) i dd5b 760 800 860 900 760 800 860 900 ma 2) i dd5d 50 100 50 110 50 100 50 110 ma 3)4) 4) i dd5d and i dd6 values are for 0 c t case 85 c. i dd6 32 64 36 72 32 64 36 72 ma 3)4) i dd7 1160 1200 1310 1350 1100 1140 1240 1290 ma 2) internet data sheet rev. 1.41, 2006-11 38 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 26 i dd specification for hys[64/72]t[16/32/64]xxxhu-[3.7/5]?a product type hys64t16000hu?3.7?a hys64t32001hu?3.7?a hys72t32000hu?3.7?a hys64t64020hu?3.7?a hys64t16000hu?5?a hys64t32001hu?5?a hys72t32000hu?5?a unit note 1) 1) calculated values from component data. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled. organization 128 mb 256 mb 256 mb 512 mb 128 mb 256 mb 256 mb 1 rank 1 rank 1 rank 2 ranks 1 rank 1 rank 1 rank x64 x64 x72 x64 x64 x64 x72 ?3.7 ?3.7 ?3.7 ?3.7 ?5 ?5 ?5 symbol max. max. max. max. max. max. max. i dd0 220 470 500 530 200 400 450 ma 2) 2) the other rank is in i dd2p precharge power-down current mode. i dd1 240 510 540 580 220 440 500 ma 2) i dd2n 140 560 320 630 110 220 250 ma 3) 3) both ranks are in the same i dd current mode. i dd2p 20 65 40 70 20 30 40 ma 3) i dd2q 100 400 230 450 80 160 180 ma 3) i dd3p( mrs = 0) 60 260 140 290 50 100 120 ma 3) i dd3p( mrs = 1) 20 65 40 70 20 30 40 ma 3) i dd3n 140 560 320 630 120 240 270 ma 3) i dd4r 320 590 630 670 280 480 540 ma 2) i dd4w 400 710 770 800 360 560 630 ma 2) i dd5b 340 710 770 800 320 640 720 ma 2) i dd5d 20 100 50 110 20 50 50 ma 3)4) 4) i dd5d and i dd6 values are for 0 c t case 85 c. i dd6 16 64 36 72 16 32 36 ma 3)4) i dd7 600 1110 1220 1250 560 1000 1130 ma 2) internet data sheet rev. 1.41, 2006-11 39 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 4 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 27 ?spd codes for pc2?6400[u/e]?666? on page 39 ? table 28 ?spd codes for pc2?6400[u/e]?555? on page 44 ? table 29 ?spd codes for pc2?5300[u/e]?444? on page 48 ? table 30 ?spd codes for pc2?5300[u/e]?555? on page 52 ? table 31 ?spd codes for pc2?4200[u/e]?444? on page 56 ? table 32 ?spd codes for pc2?3200[u/e]?333? on page 60 table 27 spd codes for pc2?6400[u/e]?666 product type hys64t32001hu?2.5?a hys64t64020hu?2.5?a hys72t32000hu?2.5?a hys72t64020hu?2.5?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 6400u?666 pc2? 6400u?666 pc2? 6400e?666 pc2? 6400e?666 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 60 61 60 61 6 data width 40 40 48 48 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 25 25 25 25 10 t ac sdram @ cl max (byte 18) [ns] 40 40 40 40 internet data sheet rev. 1.41, 2006-11 40 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 11 error correction support (non-ecc, ecc) 00 00 02 02 12 refresh rate and type 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 00 08 08 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 70 70 70 70 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 02 02 02 02 21 dimm attributes 00 00 00 00 22 component attributes 03 03 03 03 23 t ck @ cl max -1 (byte 18) [ns] 30 30 30 30 24 t ac sdram @ cl max -1 [ns] 45 45 45 45 25 t ck @ cl max -2 (byte 18) [ns] 3d 3d 3d 3d 26 t ac sdram @ cl max -2 [ns] 50 50 50 50 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 40 40 32 t as.min and t cs.min [ns] 17 17 17 17 33 t ah.min and t ch.min [ns] 25 25 25 25 34 t ds.min [ns] 05 05 05 05 35 t dh.min [ns] 12 12 12 12 36 t wr.min [ns] 3c 3c 3c 3c product type hys64t32001hu?2.5?a hys64t64020hu?2.5?a hys72t32000hu?2.5?a hys72t64020hu?2.5?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 6400u?666 pc2? 6400u?666 pc2? 6400e?666 pc2? 6400e?666 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 41 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 3c 3c 3c 3c 42 t rfc.min [ns] 4b 4b 4b 4b 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 14 14 14 14 45 t qhs.max [ns] 1e 1e 1e 1e 46 pll relock time 00 00 00 00 47 t case.max delta / ? t 4r4w delta 53535353 48 psi(t-a) dram 82 82 82 82 49 ? t 0 (dt0) 5b5b5b5b 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 3e 3e 3e 3e 51 ? t 2p (dt2p) 29 29 29 29 52 ? t 3n (dt3n) 29 29 29 29 53 ? t 3p.fast (dt3p fast) 36363636 54 ? t 3p.slow (dt3p slow) 19191919 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 4e 4e 4e 4e 56 ? t 5b (dt5b) 17 17 17 17 57 ? t 7 (dt7) 26262626 58psi(ca) pll 00000000 59 psi(ca) reg 00 00 00 00 60 ? t pll (dtpll) 00 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 12 12 12 12 product type hys64t32001hu?2.5?a hys64t64020hu?2.5?a hys72t32000hu?2.5?a hys72t64020hu?2.5?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 6400u?666 pc2? 6400u?666 pc2? 6400e?666 pc2? 6400e?666 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 42 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 63 checksum of bytes 0-62 76 77 88 89 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 37 37 74 product type, char 2 34 34 32 32 75 product type, char 3 54 54 54 54 76 product type, char 4 33 36 33 36 77 product type, char 5 32 34 32 34 78 product type, char 6 30 30 30 30 79 product type, char 7 30 32 30 32 80 product type, char 8 31 30 30 30 81 product type, char 9 48 48 48 48 82 product type, char 10 55 55 55 55 83 product type, char 11 32 32 32 32 84 product type, char 12 2e 2e 2e 2e 85 product type, char 13 35 35 35 35 86 product type, char 14 41 41 41 41 87 product type, char 15 20 20 20 20 88 product type, char 16 20 20 20 20 product type hys64t32001hu?2.5?a hys64t64020hu?2.5?a hys72t32000hu?2.5?a hys72t64020hu?2.5?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 6400u?666 pc2? 6400u?666 pc2? 6400e?666 pc2? 6400e?666 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 43 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 3x 3x 3x 3x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 128 - 255 blank for customer use ffffffff product type hys64t32001hu?2.5?a hys64t64020hu?2.5?a hys72t32000hu?2.5?a hys72t64020hu?2.5?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 6400u?666 pc2? 6400u?666 pc2? 6400e?666 pc2? 6400e?666 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 44 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 28 spd codes for pc2?6400[u/e]?555 product type hys64t32001hu?25f?a hys64t64020hu?25f?a hys72t32000hu?25f?a hys72t64020hu?25f?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 6400u?555 pc2? 6400u?555 pc2? 6400e?555 pc2? 6400e?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 60 61 60 61 6 data width 40 40 48 48 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 25 25 25 25 10 t ac sdram @ cl max (byte 18) [ns] 40 40 40 40 11 error correction support (non-ecc, ecc) 00 00 02 02 12 refresh rate and type 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 00 08 08 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 70 70 70 70 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 02 02 02 02 21 dimm attributes 00 00 00 00 22 component attributes 03 03 03 03 internet data sheet rev. 1.41, 2006-11 45 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 23 t ck @ cl max -1 (byte 18) [ns] 25 25 25 25 24 t ac sdram @ cl max -1 [ns] 40 40 40 40 25 t ck @ cl max -2 (byte 18) [ns] 3d 3d 3d 3d 26 t ac sdram @ cl max -2 [ns] 50 50 50 50 27 t rp.min [ns] 32 32 32 32 28 t rrd.min [ns] 1e 1e 1e 1e 29 t rcd.min [ns] 32 32 32 32 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 40 40 32 t as.min and t cs.min [ns] 17 17 17 17 33 t ah.min and t ch.min [ns] 25 25 25 25 34 t ds.min [ns] 05 05 05 05 35 t dh.min [ns] 12 12 12 12 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 30303030 41 t rc.min [ns] 39 39 39 39 42 t rfc.min [ns] 4b 4b 4b 4b 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 14 14 14 14 45 t qhs.max [ns] 1e 1e 1e 1e 46 pll relock time 00 00 00 00 47 t case.max delta / ? t 4r4w delta 53535353 48 psi(t-a) dram 82 82 82 82 product type hys64t32001hu?25f?a hys64t64020hu?25f?a hys72t32000hu?25f?a hys72t64020hu?25f?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 6400u?555 pc2? 6400u?555 pc2? 6400e?555 pc2? 6400e?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 46 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 49 ? t 0 (dt0) 5b5b5b5b 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 3e 3e 3e 3e 51 ? t 2p (dt2p) 29 29 29 29 52 ? t 3n (dt3n) 29 29 29 29 53 ? t 3p.fast (dt3p fast) 36363636 54 ? t 3p.slow (dt3p slow) 19191919 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 4e 4e 4e 4e 56 ? t 5b (dt5b) 17 17 17 17 57 ? t 7 (dt7) 26262626 58psi(ca) pll 00000000 59 psi(ca) reg 00 00 00 00 60 ? t pll (dtpll) 00 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 7f 80 91 92 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 37 37 74 product type, char 2 34 34 32 32 product type hys64t32001hu?25f?a hys64t64020hu?25f?a hys72t32000hu?25f?a hys72t64020hu?25f?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 6400u?555 pc2? 6400u?555 pc2? 6400e?555 pc2? 6400e?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 47 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 75 product type, char 3 54 54 54 54 76 product type, char 4 33 36 33 36 77 product type, char 5 32 34 32 34 78 product type, char 6 30 30 30 30 79 product type, char 7 30 32 30 32 80 product type, char 8 31 30 30 30 81 product type, char 9 48 48 48 48 82 product type, char 10 55 55 55 55 83 product type, char 11 32 32 32 32 84 product type, char 12 35 35 35 35 85 product type, char 13 46 46 46 46 86 product type, char 14 41 41 41 41 87 product type, char 15 20 20 20 20 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 3x 3x 3x 3x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 128 - 255 blank for customer use ffffffff product type hys64t32001hu?25f?a hys64t64020hu?25f?a hys72t32000hu?25f?a hys72t64020hu?25f?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 6400u?555 pc2? 6400u?555 pc2? 6400e?555 pc2? 6400e?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 48 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 29 spd codes for pc2?5300[u/e]?444 product type hys64t32001hu?3?a hys64t64020hu?3?a hys72t32000hu?3?a hys72t64020hu?3?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 5300u?444 pc2? 5300u?444 pc2? 5300e?444 pc2? 5300e?444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 60 61 60 61 6 data width 40 40 48 48 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 45 11 error correction support (non-ecc, ecc) 00 00 02 02 12 refresh rate and type 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 00 08 08 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 02 02 02 02 21 dimm attributes 00 00 00 00 22 component attributes 03 03 03 03 23 t ck @ cl max -1 (byte 18) [ns] 30 30 30 30 internet data sheet rev. 1.41, 2006-11 49 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 24 t ac sdram @ cl max -1 [ns] 45 45 45 45 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 27 t rp.min [ns] 30 30 30 30 28 t rrd.min [ns] 1e 1e 1e 1e 29 t rcd.min [ns] 30 30 30 30 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 40 40 32 t as.min and t cs.min [ns] 20 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 27 34 t ds.min [ns] 10 10 10 10 35 t dh.min [ns] 17 17 17 17 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 39 39 39 39 42 t rfc.min [ns] 4b 4b 4b 4b 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 18 18 18 18 45 t qhs.max [ns] 22 22 22 22 46 pll relock time 00 00 00 00 47 t case.max delta / ? t 4r4w delta 52525252 48 psi(t-a) dram 82 82 82 82 49 ? t 0 (dt0) 47474747 product type hys64t32001hu?3?a hys64t64020hu?3?a hys72t32000hu?3?a hys72t64020hu?3?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 5300u?444 pc2? 5300u?444 pc2? 5300e?444 pc2? 5300e?444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 50 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 38 38 38 38 51 ? t 2p (dt2p) 29 29 29 29 52 ? t 3n (dt3n) 25 25 25 25 53 ? t 3p.fast (dt3p fast) 2f2f2f2f 54 ? t 3p.slow (dt3p slow) 19191919 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 44 44 44 44 56 ? t 5b (dt5b) 17 17 17 17 57 ? t 7 (dt7) 24242424 58psi(ca) pll 00000000 59 psi(ca) reg 00 00 00 00 60 ? t pll (dtpll) 00 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 47 48 59 5a 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 37 37 74 product type, char 2 34 34 32 32 75 product type, char 3 54 54 54 54 product type hys64t32001hu?3?a hys64t64020hu?3?a hys72t32000hu?3?a hys72t64020hu?3?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 5300u?444 pc2? 5300u?444 pc2? 5300e?444 pc2? 5300e?444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 51 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 76 product type, char 4 33 36 33 36 77 product type, char 5 32 34 32 34 78 product type, char 6 30 30 30 30 79 product type, char 7 30 32 30 32 80 product type, char 8 31 30 30 30 81 product type, char 9 48 48 48 48 82 product type, char 10 55 55 55 55 83 product type, char 11 33 33 33 33 84 product type, char 12 41 41 41 41 85 product type, char 13 20 20 20 20 86 product type, char 14 20 20 20 20 87 product type, char 15 20 20 20 20 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 6x 5x 6x 5x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 128 - 255 blank for customer use ffffffff product type hys64t32001hu?3?a hys64t64020hu?3?a hys72t32000hu?3?a hys72t64020hu?3?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 5300u?444 pc2? 5300u?444 pc2? 5300e?444 pc2? 5300e?444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 52 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 30 spd codes for pc2?5300[u/e]?555 product type hys64t32001hu?3s?a hys64t64020hu?3s?a hys72t32000hu?3s?a hys72t64020hu?3s?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 5300u?555 pc2? 5300u?555 pc2? 5300e?555 pc2? 5300e?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 60 61 60 61 6 data width 40 40 48 48 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 45 11 error correction support (non-ecc, ecc) 00 00 02 02 12 refresh rate and type 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 00 08 08 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 dimm mechanical characteristics 01 01 01 01 20 dimm type information 02 02 02 02 21 dimm attributes 00 00 00 00 22 component attributes 03 03 03 03 internet data sheet rev. 1.41, 2006-11 53 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 40 40 32 t as.min and t cs.min [ns] 20 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 27 34 t ds.min [ns] 10 10 10 10 35 t dh.min [ns] 17 17 17 17 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 3c 3c 3c 3c 42 t rfc.min [ns] 4b 4b 4b 4b 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 18 18 18 18 45 t qhs.max [ns] 22 22 22 22 46 pll relock time 00 00 00 00 47 t case.max delta / ? t 4r4w delta 52525252 48 psi(t-a) dram 82 82 82 82 product type hys64t32001hu?3s?a hys64t64020hu?3s?a hys72t32000hu?3s?a hys72t64020hu?3s?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 5300u?555 pc2? 5300u?555 pc2? 5300e?555 pc2? 5300e?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 54 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 49 ? t 0 (dt0) 43434343 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 38 38 38 38 51 ? t 2p (dt2p) 29 29 29 29 52 ? t 3n (dt3n) 25 25 25 25 53 ? t 3p.fast (dt3p fast) 2f2f2f2f 54 ? t 3p.slow (dt3p slow) 19191919 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 44 44 44 44 56 ? t 5b (dt5b) 17 17 17 17 57 ? t 7 (dt7) 22222222 58psi(ca) pll 00000000 59 psi(ca) reg 00 00 00 00 60 ? t pll (dtpll) 00 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 12 12 12 12 63 checksum of bytes 0-62 74 75 86 87 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 37 37 74 product type, char 2 34 34 32 32 product type hys64t32001hu?3s?a hys64t64020hu?3s?a hys72t32000hu?3s?a hys72t64020hu?3s?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 5300u?555 pc2? 5300u?555 pc2? 5300e?555 pc2? 5300e?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 55 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 75 product type, char 3 54 54 54 54 76 product type, char 4 33 36 33 36 77 product type, char 5 32 34 32 34 78 product type, char 6 30 30 30 30 79 product type, char 7 30 32 30 32 80 product type, char 8 31 30 30 30 81 product type, char 9 48 48 48 48 82 product type, char 10 55 55 55 55 83 product type, char 11 33 33 33 33 84 product type, char 12 53 53 53 53 85 product type, char 13 41 41 41 41 86 product type, char 14 20 20 20 20 87 product type, char 15 20 20 20 20 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 3x 5x 3x 5x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 128 - 255 blank for customer use ffffffff product type hys64t32001hu?3s?a hys64t64020hu?3s?a hys72t32000hu?3s?a hys72t64020hu?3s?a organization 256mb 512mb 256mb 512mb 64 64 72 72 1 rank ( 8) 2 ranks ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 5300u?555 pc2? 5300u?555 pc2? 5300e?555 pc2? 5300e?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 56 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 31 spd codes for pc2?4200[u/e]?444 product type hys64t16000hu?3.7?a hys64t32001hu?3.7?a hys72t32000hu?3.7?a hys64t64020hu?3.7?a organization 128mb 256mb 256mb 512mb 64 64 72 64 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 4200u?444 pc2? 4200u?444 pc2? 4200e?444 pc2? 4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.2 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 09 0a 0a 0a 5 dimm rank and stacking information 60 60 60 61 6 data width 40 40 48 40 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 11 error correction support (non-ecc, ecc) 00 00 02 00 12 refresh rate and type 82 82 82 82 13 primary sdram width 10 08 08 08 14 error checking sdram width 00 00 08 00 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 dimm mechanical characteristics 00 00 00 01 20 dimm type information 02 02 02 02 21 dimm attributes 00 00 00 00 22 component attributes 01 01 01 03 internet data sheet rev. 1.41, 2006-11 57 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 28 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 20 40 40 40 32 t as.min and t cs.min [ns] 25 25 25 25 33 t ah.min and t ch.min [ns] 37 37 37 37 34 t ds.min [ns] 10 10 10 10 35 t dh.min [ns] 22 22 22 22 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00000000 41 t rc.min [ns] 3c 3c 3c 3c 42 t rfc.min [ns] 4b 4b 4b 4b 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 1e 1e 1e 1e 45 t qhs.max [ns] 28 28 28 28 46 pll relock time 00 00 00 00 47 t case.max delta / ? t 4r4w delta 56555555 48 psi(t-a) dram 7a 82 82 82 product type hys64t16000hu?3.7?a hys64t32001hu?3.7?a hys72t32000hu?3.7?a hys64t64020hu?3.7?a organization 128mb 256mb 256mb 512mb 64 64 72 64 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 4200u?444 pc2? 4200u?444 pc2? 4200e?444 pc2? 4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 58 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 49 ? t 0 (dt0) 33373737 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 29 2b 2b 2b 51 ? t 2p (dt2p) 1f 21 21 21 52 ? t 3n (dt3n) 1b 1d 1d 1d 53 ? t 3p.fast (dt3p fast) 25282828 54 ? t 3p.slow (dt3p slow) 13141414 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 2e 2c 2c 2c 56 ? t 5b (dt5b) 14 15 15 15 57 ? t 7 (dt7) 23212121 58psi(ca) pll 00000000 59 psi(ca) reg 00 00 00 00 60 ? t pll (dtpll) 00 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 11 11 11 12 63 checksum of bytes 0-62 46 67 79 6c 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 37 36 74 product type, char 2 34 34 32 34 product type hys64t16000hu?3.7?a hys64t32001hu?3.7?a hys72t32000hu?3.7?a hys64t64020hu?3.7?a organization 128mb 256mb 256mb 512mb 64 64 72 64 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 4200u?444 pc2? 4200u?444 pc2? 4200e?444 pc2? 4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 59 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 75 product type, char 3 54 54 54 54 76 product type, char 4 31 33 33 36 77 product type, char 5 36 32 32 34 78 product type, char 6 30 30 30 30 79 product type, char 7 30 30 30 32 80 product type, char 8 30 31 30 30 81 product type, char 9 48 48 48 48 82 product type, char 10 55 55 55 55 83 product type, char 11 33 33 33 33 84 product type, char 12 2e 2e 2e 2e 85 product type, char 13 37 37 37 37 86 product type, char 14 41 41 41 41 87 product type, char 15 20 20 20 20 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 4x 4x 4x 2x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number xx xx xx xx 99 - 127 not used 00 00 00 00 128 - 255 blank for customer use ffffffff product type hys64t16000hu?3.7?a hys64t32001hu?3.7?a hys72t32000hu?3.7?a hys64t64020hu?3.7?a organization 128mb 256mb 256mb 512mb 64 64 72 64 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) label code pc2? 4200u?444 pc2? 4200u?444 pc2? 4200e?444 pc2? 4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.2 byte# description hex hex hex hex internet data sheet rev. 1.41, 2006-11 60 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 32 spd codes for pc2?3200[u/e]?333 product type hys64t16000hu?5?a hys64t32001hu?5?a hys72t32000hu?5?a organization 128mb 256mb 256mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 pc2?3200u?333 pc2?3200e?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0d 0d 0d 4 number of column addresses 09 0a 0a 5 dimm rank and stacking information 60 60 60 6 data width 40 40 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 60 60 60 11 error correction support (non-ecc, ecc) 00 00 02 12 refresh rate and type 82 82 82 13 primary sdram width 10 08 08 14 error checking sdram width 00 00 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 dimm mechanical characteristics 00 00 00 20 dimm type information 02 02 02 21 dimm attributes 00 00 00 22 component attributes 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 50 50 50 24 t ac sdram @ cl max -1 [ns] 60 60 60 internet data sheet rev. 1.41, 2006-11 61 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 28 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 28 28 28 31 module density per rank 20 40 40 32 t as.min and t cs.min [ns] 35 35 35 33 t ah.min and t ch.min [ns] 47 47 47 34 t ds.min [ns] 15 15 15 35 t dh.min [ns] 27 27 27 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 28 28 28 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 37 37 37 42 t rfc.min [ns] 4b 4b 4b 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 23 23 23 45 t qhs.max [ns] 2d 2d 2d 46 pll relock time 00 00 00 47 t case.max delta / ? t 4r4w delta 565353 48 psi(t-a) dram 7a 82 82 49 ? t 0 (dt0) 2b 2f 2f 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 20 23 23 51 ? t 2p (dt2p) 1f 21 21 product type hys64t16000hu?5?a hys64t32001hu?5?a hys72t32000hu?5?a organization 128mb 256mb 256mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 pc2?3200u?333 pc2?3200e?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex internet data sheet rev. 1.41, 2006-11 62 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 52 ? t 3n (dt3n) 17 19 19 53 ? t 3p.fast (dt3p fast) 1e 20 20 54 ? t 3p.slow (dt3p slow) 131414 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 28 26 26 56 ? t 5b (dt5b) 13 14 14 57 ? t 7 (dt7) 20 1f 1f 58psi(ca) pll 000000 59 psi(ca) reg 00 00 00 60 ? t pll (dtpll) 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 62 spd revision 11 11 11 63 checksum of bytes 0-62 9a ba cc 64 manufacturer?s jedec id code (1) 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 36 36 37 74 product type, char 2 34 34 32 75 product type, char 3 54 54 54 76 product type, char 4 31 33 33 77 product type, char 5 36 32 32 78 product type, char 6 30 30 30 product type hys64t16000hu?5?a hys64t32001hu?5?a hys72t32000hu?5?a organization 128mb 256mb 256mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 pc2?3200u?333 pc2?3200e?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex internet data sheet rev. 1.41, 2006-11 63 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 79 product type, char 7 30 30 30 80 product type, char 8 30 31 30 81 product type, char 9 48 48 48 82 product type, char 10 55 55 55 83 product type, char 11 35 35 35 84 product type, char 12 41 41 41 85 product type, char 13 20 20 20 86 product type, char 14 20 20 20 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 4x 4x 4x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 128 - 255 blank for customer use ff ff ff product type hys64t16000hu?5?a hys64t32001hu?5?a hys72t32000hu?5?a organization 128mb 256mb 256mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 pc2?3200u?333 pc2?3200e?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex internet data sheet rev. 1.41, 2006-11 64 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 5 package outlines this chapter contains the package outlines of the products. figure 6 package outline raw card a l-dim-240-1 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * / ' & % $ % ? ? ? ? ? ? ? $ ? ? ? 0 , 1 ' h w d l o r i f r q w d f w v & ? $ % ? 2 q ( & & p r g x o h v r q o \ % x u u p d [ d o o r z h g 0 $ ; & ? internet data sheet rev. 1.41, 2006-11 65 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules figure 7 package outline raw card c l-dim-240-3 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * / ' % & $ & ? 0 $ ; % ? % x u u p d [ d o o r z h g ? $ % & ' h w d l o r i f r q w d f w v ? $ ? [ internet data sheet rev. 1.41, 2006-11 66 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules figure 8 package outline raw card d l-dim-240-8 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * / ' & % $ ? % ? ? ? ? ? 0 $ ; & ? ? ? $ ? ? ? 0 , 1 % x u u p d [ d o o r z h g ' h w d l o r i f r q w d f w v & ? $ % ? internet data sheet rev. 1.41, 2006-11 67 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules figure 9 package outline raw card e l-dim-240-9 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * / ' & % $ ? % ? ? ? ? ? 0 $ ; & ? ? ? $ ? ? ? 0 , 1 % x u u p d [ d o o r z h g ' h w d l o r i f r q w d f w v & ? $ % ? internet data sheet rev. 1.41, 2006-11 68 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules figure 10 package outline raw card f l-dim-240-6 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * / ' & % $ ? % ? ? ? ? ? 0 $ ; & ? ? ? $ ? ? ? 0 , 1 % x u u p d [ d o o r z h g ' h w d l o r i f r q w d f w v & ? $ % ? internet data sheet rev. 1.41, 2006-11 69 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules figure 11 package outline raw card g l-dim-240-7 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * / ' & % $ ? % ? ? ? ? ? 0 $ ; & ? ? ? $ ? ? ? 0 , 1 % x u u p d [ d o o r z h g ' h w d l o r i f r q w d f w v & ? $ % ? internet data sheet rev. 1.41, 2006-11 70 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 6 product type nomenclature qimonda?s nomenclature uses simple coding combined with some propriatory coding. table 33 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 34 and for components in table 35 . table 33 nomenclature fields and examples table 34 ddr2 dimm nomenclature example for field number 1234567891011 micro-dimm hys 64 t 64/128 0 2 0 k m ?5 ?a ddr2 dram hyb 18 t 512/1g 16 0 a c ?5 field description values coding 1 qimonda module prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3 dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 512 4 gbyte 5 raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free stat us a .. z look up table 9 module type d so- d imm m m icro-dimm r r egistered u u nbuffered f f ully buffered internet data sheet rev. 1.41, 2006-11 71 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules table 35 ddr2 dram nomenclature 10 speed grade ?2.5f pc2?6400 5?5?5 ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the o verall module memory density in mbytes as listed in column ?coding?. field description values coding 1 qimonda component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status c fbga, lead-containing f fbga, lead-free 10 speed grade ?25f ddr2-800 5-5-5 ?2.5 ddr2-800 6-6-6 ?3 ddr2-667 4-4-4 ?3s ddr2-667 5-5-5 ?3.7 ddr2-533 4-4-4 ?5 ddr2-400 3-3-3 field description values coding internet data sheet rev. 1.41, 2006-11 72 03062006-0gn5-wtpw hys[64/72]t[16/32/64 ]0xxhu?[2.5/../5]?a unbuffered ddr2 sdram modules 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.2 component ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6 product type nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table of contents edition 2006-11 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2006. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet |
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