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description the puma 68e4001/a is a 4mbit cmos eeprom module in a jedec 68 pin surface mount plcc. the plastic device is screened to ensure high reliability. access times of 120, 150 and 200ns are available.the output width is user configurable as 8, 16, or 32 bits wide using cs1-4 and is available in two pinout options, single we or we1-4 (version /a) . page write (128 bytes) is performed in 5 ms (typical). the device also features both hardware and software data protec- tion with data polling and toggle bit indication of end of write . write cycle endurance is 10,000 erase/write cycles with a data retention time of 10 years. pin functions a0~16 address inputs d0~31 data inputs/outputs cs1~4 chip select oe output enable we write enable ( we1~4 on version a) nc no connect v cc power (+5v) gnd ground 128k x 32 eeprom module puma 68e4001/a-12/15/20 issue 4.2 : november 1998 block diagram (see page 11 for block diagram of option /a) pin definition (see page 11 for option /a pinout) oe cs1 nc a0 a1 a2 a3 a4 a5 cs3 gnd cs4 we a6 a7 a8 a9 a10 vcc d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 puma 68e4001 view from above vcc a11 a12 a13 a14 a15 a16 cs2 nc nc nc nc nc gnd nc d16~23 d0~7 d8~15 d24~31 cs1 cs2 cs3 cs4 oe we a0~a16 128k x 8 eeprom 128k x 8 eeprom 128k x 8 eeprom 128k x 8 eeprom 4,194,304 bit cmos eeprom module features access times of 120/150/200 ns. user configurable as 8 / 16 / 32 bit wide output. commercial, industrial, or military grades. operating power 490 / 913 / 1760 mw (max). jedec 68 pin surface mount plcc, available in two pinouts : single we, we1~4 is version a. high reliability plastic design hardware and software data protection. endurance of 10 4 erase/write cycles and data retention time of 10 years. 11403 west bernado court, suite 100, san diego, ca 92127. tel no: (619) 674 2233, fax no: (619) 674 2230
issue 4.2 : november 1998 puma 68e4001/a-12/15/17/20 2 capacitance (t a =25c,?=1mhz) note: these parameters are calculated, not measured. parameter symbol test condition typ max unit input capacitance cs1~4, we1~4 (1) c in1 v in =0v - 20 pf other inputs c in2 v in =0v - 22 pf output capacitance c out v out =0v - 22 pf notes: (1) on the puma 68e4001a version only. dc electrical characteristics (t a =-55c to +125c,v cc =5v 10%) parameter symbol test condition min max unit input leakage current i li1 v in = gnd to v cc +1 -40a output leakage current 32 bit i lo v i/o = gnd to v cc , cs (1) =v ih -40a operating supply current 32 bit i cc32 cs (1) =oe=v il , we=v ih , i out =0ma, ?=5mhz (2) - 320 ma 16 bit i cc16 as above - 166 ma 8 bit i cc8 as above -89ma standby supply current ttl levels i sb1 cs (1) = 2.0v to v cc +1v -12ma cmos levels i sb2 cs (1) = v cc -0.3v to v cc +1v - 1.2 ma output low voltage v ol i ol = 2.1ma. - 0.45 v output high voltage v oh i oh = -400a. 2.4 - v notes (1) cs above are accessed through cs1-4. these inputs must be operated simultaneously for 32 bit operation, in pairs in 16 bit mode and singly for 8 bit mode. (2) also for we1~4 on the puma 68e4001a version. additionally, we1~4 are accessed as in note (1) above. recommended operating conditions min typ max dc power supply voltage v cc 4.5 5.0 5.5 v input low voltage v il -1.0 - 0.8 v input high voltage v ih 2.0 - v cc +1 v operating temp range t a 0-70 c t ai -40 - 85 c ( i suffix) t am -55 - 125 c ( m suffix) dc operating conditions absolute maximum ratings (1) operating temperature t opr -55 to +125 c storage temperature t stg -65 to +150 c input voltages (including n.c. pins) with respect to gnd v in -0.6 to +6.25 v output voltages with respect to gnd v out -0.6 to v cc +0.6 v notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
puma 68e4001/a-12/15/17/20 issue 4.2 : november 1998 ac operating conditions read cycle 12 15 20 parameter symnbol min max min max min max unit read cycle time t rc 120 - 150 - 200 - ns address access time t aa - 120 - 150 - 200 ns chip select access time t cs - 120 - 150 - 200 ns output enable access time t oe 0 600 70 0 80 ns chip select high to high z output (1) t hz 0 500 50 0 50 ns output enable high to high z output (1) t ohz 0 500 50 0 50 ns chip select low to active output (1) t lz 0-0-0 - ns output enable low to active output (1) t olz 0-0-0 - ns output hold from address change t oh 0-0-0 - ns notes: (1) t hz max. and t olz max. are measured with cl = 5pf, from the point when chip select or output enable return high (whichever occurs first) to the time when the outputs are no longer driven. t hz and t ohz are shown for reference only: they are characterized and not tested. write cycle parameter symbol min typ max unit write cycle time t wc --10 ms address set-up time t as 0- -ns address hold time t ah 50 - - ns output enable set-up time t oes 0- -ns output enable hold time t oeh 0- -ns chip select set-up time t cs 0- -ns chip select hold time t ch 0- -ns write pulse width t wp 100 - - ns write enable high recovery t wph 50 - - ns data set-up time t ds 50 - - ns data hold time t dh 0- -ns delay to next write t dw 10 - - s byte load cycle t blc - - 150 s ac test conditions output test load * input pulse levels: 0v to 3.0v * input rise and fall times: 10ns * input and output timing reference levels: 1.5v * output load: 1 ttl gate + 100pf * v cc =5v10% 645 100pf i/o pin 1.76v w
issue 4.2 : november 1998 puma 68e4001/a-12/15/17/20 4 read cycle timing waveform ac write waveform - we controlled t wc t as t ah t wp t cs t oes t ds t dh t oeh t ch t wph address we oe cs1~4 data a0~a16 cs1~4 oe data high z t cs t oe t aa t ohz t oh t rc output valid address valid t clz t olz t ohz
puma 68e4001/a-12/15/17/20 issue 4.2 : november 1998 ac write waveform - cs controlled t wc t as t ah t wp t cs t oes t ds t dh t oeh t ch t wph address we cs1~4 oe data page mode write waveform note: a8 through a16 must specify the page address during each high to low transition of write enable (or chip select). output enable must be high only when write enable and chip select are both low. oe cs1~4 we a0-a16 data t wp t wph t blc t as t ah t dh t ds t wc valid add valid data byte 0 byte 1 byte 2 byte 3 byte 126 byte 127
issue 4.2 : november 1998 puma 68e4001/a-12/15/17/20 6 software protected write waveform oe cs1~4 we/we1~4 a0~a6 t wp t as t ah t dh data t ds t wc byte 0 byte 126 byte 127 05555 02aaa 05555 aa 55 a0 a7~a16 byte address page address t wph blc t toggle bit waveform cs1~4 we/we1~4 oe t oe t oeh t dh t wr d6,d14, d22,d30 high z t dw data polling waveform we/ we1~4 cs1~4 oe d7,d15, d23,d31 a0-a16 t oe t oeh t dh t wr an an an an an high z t dw
puma 68e4001/a-12/15/17/20 issue 4.2 : november 1998 device operation the following description deals with the puma 68e4001 device, with the references to we meaning we1~4 on the puma 68e4001a part. read the puma 68e4001 read operations are initiated by both output enable and chip select low. the read operation is terminated by either chip select or output enable returning high. this 2-line control architecture eliminates bus contention in a system environment. the data bus will be in a high impendence state when either output enable or chip select is high. write write operations are initiated when both chip select and write enable are low and output enable is high. the puma 68e4001 supports both a chip select and write enable controlled write cycle. that is, the address is latched by the falling edge of either chip select or write enable, whichever occurs last. similarly, the data is latched internally by the rising edge of either chip select or write enable, whichever occurs first. a byte write operation, once initiated, will automatically continue to completion, typically within 5 ms. page mode write the page write feature of the puma 68e4001 allows the entire memory to be written in 5 seconds. page write allows 128 bytes of data to be written prior to the internal programming cycle. the host can fetch data from another location within the system during a page write operation (change the source address), but the page address (a8 through a16) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following the initial byte write cycle, the host can write up to 128 bytes in the same manner as the first byte written. each successive byte load cycle, started by the write enable high to low transition, must begin within 150 s of the falling edge of the preceding write enable. if a subsequent write enable high to low transition is not detected within 150 s, the internal automatic programming cycle will commence. data polling the puma 68e4001 features data polling to indicate if the write cycle is completed. during the internal programming cycle, any attempt to read the last byte written will produce the compliment of that data on d7. once the programming is complete, d7 will reflect the true data. note: if the the puma 68e4001 is in a protected state and an illegal write operation is attempted data polling will not operate. toggle bit in addition to data polling, another method is provided to determine the end of a write cycle. during a write operation successive attempts to read data will result in d6 toggling between 1 and 0. once a write is complete, this toggling will stop and valid data will be read. hardware data protection the puma 68e4001 provides three hardware features to protect non-volalitile data from inadvertent writes. ? noise protection - a write enable pulse less than 15 ns will not initiate a write cycle. ? default v cc sence - all functions are inhibited when v cc < 3.6 v. ? write inhibit - holding either output enable low, write enable high or chip select high will prevent an inadvertent write cycle during power on or power off, maintaining data integrity.
issue 4.2 : november 1998 puma 68e4001/a-12/15/17/20 8 mode cs1~4 oe outputs read write standby write inhibit we 0 0 1 x x 1 0 x 1 x 0 i x x 0 data out data in floating software data protection the puma 68e4001 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protect feature. the internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. this circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the puma 68e4001 is also protected against inadvertent and accidental writes in that, the software algorithm must be issued prior to writing additional data to the device. operating modes the table below shows the logic inputs required to control the operation of the puma 68e4001. 0 = v il : 1 = v ih : x = v ih or v il
puma 68e4001/a-12/15/17/20 issue 4.2 : november 1998 notes: (1) data format i/o7-i/o0 (hex); once initiated, this sequence of write operations should not be interrupted. (2) enable write protect state will be initiated at end of write even if no other data is loaded. (3) disable write protect state will be initiated at end of write period even if no other data is loaded. (4) 1 to 128 bytes of data may be loaded. software algorithms selecting the software data protection mode requires the host system to precede datawrite operations by a series of three write operations to three specfic addresses. the three byte sequence opens the page write window enabling the host to write from from 1 to 128 bytes of data. once the page load cycle has been completed, the device will automatically be returned to the data protected state software data protection algorithm regardless of wheather the device has been protected or not, once the software data protected aglorithm is used and the data is written, the puma 68e4001 will automatically disable further writes unless another command is issued to cancel it. if no further commands are issued the puma 68e4001 will be write protected during power- down and any subsequent power-up. load data a0 to address 5555 load data 55 to address 2aaa load data aa to address 5555 last byte / word to last address load data xx to any address (4) writes enabled (2) enter data protect state
issue 4.2 : november 1998 puma 68e4001/a-12/15/17/20 10 software data protect disable in the event the user wants to deactivate the software data protection feature for testing or reprogramming in an e 2 prom programmer. the following six step algorithm will reset the internal protection circuit. after t wc , the puma 68e4001 will be in standard operating mode. last byte / word to last address load data xx to any address load data 20 to address 5555 load data 55 to address 2aaa load data aa to address 5555 load data 80 to address 5555 load data 55 to address 2aaa load data aa to address 5555 (4) exit data protect state (3)
puma 68e4001/a-12/15/17/20 issue 4.2 : november 1998 pin definifion 'a' version block diagram 'a' version nc a0 a1 a2 a3 a4 a5 cs3 gn d cs4 we1 a6 a7 a8 a9 a10 vcc d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 puma 68e4001a view from above vcc a11 a12 a13 a14 a15 a16 cs1 oe cs2 nc we2 we3 we4 nc gnd nc d16~23 d0~7 d8~15 d24~31 cs1 cs2 cs3 cs4 oe we1 a0~a16 128k x 8 eeprom 128k x 8 eeprom 128k x 8 eeprom 128k x 8 eeprom we2 we3 we4
issue 4.2 : november 1998 puma 68e4001/a-12/15/17/20 12 endurance blank = 10k cycles e = 100k cycles speed 12 = 120ns 15 = 150ns 20 = 200ns temperature range blank = commercial temperature i = industrial temperature m = military temperature special features blank = we a = we1~4 organisation 4001 = 128k x 32, user configurable as 256k x 16 and 512k x 8 memory type e = eeprom package puma 67 = 68 pin "j" leaded plcc package information dimensions in mm(inches) plastic 68 pin jedec surface mount plcc 1.02 (0.040) typ. 5.08 (0.200) max. 23.11 ( 0.910 ) 24.13 (0.950) 25.40 (1.000) 24.89 (0.980) 1.27 (0.050) typ. 0.43 (0.017) typ. puma 68e4001am-15e ordering information
puma 68e4001/a-12/15/17/20 issue 4.2 : november 1998 soldering recommendations bake as specified on product packaging if not specified hmpltd recommend a minimum bake of 6 hours duration @ 125c if parts have been exposed to the atmosphere for 24hrs or more soldering must not exceed vpr 215 - 219c, 60 secs ir / convection ramp rate 6c/sec max temp maintained at 125c, 120secs max temp exceeding 183c, 120-180secs time at max temp 10-40secs max temp 220 +5/-0 c ramp down -6c/sec max although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantability or fitness for a particular purpose. products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices or systems without the express written approval of a company director

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