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m16c/28 group single-chip 16-bit cmos microcomputer rej03b0026-0040z rev.0.40 2004.06.15 rev.0.40 2004.06.15 page 1 of 26 rej03b0026-0040z 1. overview the m16c/28 group of single-chip microcomputers is built using the high-performance silicon gate cmos process using a m16c/60 series cpu core and is packaged in a 64-pin and 80-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc- tion efficiency. with 1m bytes of address space, they are capable of executing instructions at high speed. in addition, this microcomputer contains a multiplier and a dmac which combined with fast instruction pro- cessing capability, makes it suitable for control of various oa, communication, and industrial equipment which requires high-speed arithmetic/logic operations. 1.1 applications audio, cameras, office/communications/portable/industrial equipment, home appliances (inverter solution), etc specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. ------table of contents------
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 2 of 26 rej03b0026-0040z item performance number of basic instructions 91 instructions shortest instruction execution time 50 ns (f(bclk)= 20mh z , v cc = 3.0v to 5.5v) (normal-ver./t-ver.) 100 ns (f(bclk)= 10mh z , v cc = 2.7v to 5.5v) (normal-ver.) 50 ns (f(bclk)= 20mh z , v cc = 4.2v to 5.5v -40 to 105 c) (v-ver.) 62.5 ns (f(bclk)= 16mh z , v cc = 4.2v to 5.5v -40 to 125 c) (v-ver.) memory rom (see the product list) capacity ram (see the product list) i/o port 71 lines multifunction timer timera:16 bits x 5 channels, timerb:16 bits x 3 channels three-phase motor control timer timers (input capture/output compare) : 16bit base timer x 1 channel (input/output x 8 channels ) serial i/o 2 channels (uart0, uart1) uart, clock synchronous 1 channel (uart2) uart, clock synchronous, i 2 c bus 1 , or iebus 2 2 channels (si/o3, si/o4) clock synchronous 1 channel (multi-master i 2 c bus 1 ) a/d converter 10 bits x 24 channels (normal-ver.) 27channels (t-ver./v-ver.) dmac 2 channels (trigger: 31 sources) crc calcuration circuit 2 polynomial (crc-ccitt and crc-16) with msb/lsb selectable (t-ver./v-ver.) watchdog timer 15 bits x 1 (with prescaler) interrupt 25 internal and 8 external sources, 4 software sources, 7 levels clock generation circuit 4 circuits ? main clock ? sub-clock ? on-chip oscillator (main-clock oscillation stop detect function) ? pll frequency synthesizer low voltage detection circuit available (normal-ver.) not available (t-ver./v-ver.) power supply voltage v cc =3.0v to 5.5v ( f(bclk)=20mh z ) (normal-ver.) v cc = 2.7v to 5.5v ( f(bclk)=10mh z ) v cc =3.0v to 5.5v (t-ver.) v cc =4.2v to 5.5v (v-ver.) flash memory program/erase voltage 2.7v to 5.5v (normal-ver.) 3.0v to 5.5v (t-ver.) 4.2v to 5.5v (v-ver.) number of program/erase 100 times ( block a ,block b : 10,000 times (option 3 ) ) power consumption 16ma (vcc=5v, f(bclk)=20mhz) 25 a (vcc=3v, f(bclk)=f(x cin )=32khz on ram) 1.8 a (vcc=3v, f(bclk)=f(x cin )=32khz, in wait mode) 0.7 a (vcc=3v, when stop mode) operating ambient temperature -20 to 85 c / -40 to 85 c 4 (normal-ver.) -40 to 85 c (t-ver.) -40 to 105 c / -40 to 125 c (v-ver.) package 80-pin plastic mold qfp notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. iebus is a trademark of nec electronics corporation. 3. if you desire this option,please so specify. 4. see table 1.4.4 for the operating ambient temperature. table 1.2.1. performance outline of m16c/28 group (80-pin device) 1.2 performance outline table 1.2.1 lists performance outline of m16c/28 group 80-pin device. table 1.2.2 lists performance outline of m16c/28 group 64-pin device. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (these circuits contain a built-in feedback resistor and external ceramic/quartz oscillator)
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 3 of 26 rej03b0026-0040z item performance number of basic instructions 91 instructions shortest instruction execution time 50 ns (f(bclk)= 20mh z , v cc = 3.0v to 5.5v) (normal-ver./t-ver.) 100 ns (f(bclk)= 10mh z , v cc = 2.7v to 5.5v) (normal-ver.) 50 ns (f(bclk)= 20mh z , v cc = 4.2v to 5.5v -40 to 105 c) (v-ver.) 62.5 ns (f(bclk)= 16mh z , v cc = 4.2v to 5.5v -40 to 125 c) (v-ver.) memory rom (see the product list) capacity ram (see the product list) i/o port 55 lines multifunction timer timera:16 bits x 5 channels, timerb:16 bits x 3 channels three-phase motor control timer timers (input capture/output compare) : 16bit base timer x 1 channel (input/output x 8 channels ) serial i/o 2 channels (uart0, uart1) uart, clock synchronous 1 channel (uart2) uart, clock synchronous, i 2 c bus 1 , or iebus 2 1 channel (si/o3) clock synchronous 1 channel (multi-master i 2 c bus 1 ) a/d converter 10 bits x 13 channels (normal-ver.) 16 channels (t-ver./v-ver.) dmac 2 channels (trigger: 30 sources) crc calcuration circuit 2 polynomial (crc-ccitt and crc-16) with msb/lsb selectable (t-ver./v-ver.) watchdog timer 15 bits x 1 (with prescaler) interrupt 24 internal and 8 external sources, 4 software sources, 7 levels clock generation circuit 4 circuits ? main clock ? sub-clock ? on-chip oscillator (main-clock oscillation stop detect function) ? pll frequency synthesizer low voltage detection circuit available (normal-ver.) not available (t-ver./v-ver.) power supply voltage v cc =3.0v to 5.5v ( f(bclk)=20mh z ) (normal-ver.) v cc = 2.7v to 5.5v ( f(bclk)=10mh z ) v cc =3.0v to 5.5v (t-ver.) v cc =4.2v to 5.5v (v-ver.) flash memory program/erase voltage 2.7v to 5.5v (normal-ver.) 3.0v to 5.5v (t-ver.) 4.2v to 5.5v (v-ver.) number of program/erase 100 times ( block a ,block b : 10,000 times (option 3 ) ) power consumption 16ma (vcc=5v, f(bclk)=20mhz) 25 a (vcc=3v, f(bclk)=f(x cin )=32khz on ram) 1.8 a (vcc=3v, f(bclk)=f(x cin )=32khz, in wait mode) 0.7 a (vcc=3v, when stop mode) operating ambient temperature -20 to 85 c / -40 to 85 c 4 (normal-ver.) -40 to 85 c (t-ver.) -40 to 105 c / -40 to 125 c (v-ver.) package 64-pin plastic mold qfp notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. iebus is a trademark of nec electronics corporation. 3. if you desire this option,please so specify. 4. see table 1.4.4 for the operating ambient temperature. table 1.2.2. performance outline of m16c/28 group (64-pin device) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (these circuits contain a built-in feedback resistor and external ceramic/quartz oscillator)
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 4 of 26 rej03b0026-0040z i/o ports internal peripheral functions timer timer a0 (16 bits) timer a1 (16 bits) timer a2 (16 bits) timer a3 (16 bits) timer a4 (16 bits) timer b0 (16 bits) timer b1 (16 bits) timer b2 (16 bits) watchdog timer a/d converter (10bits x 24 channels (normal-ver.)) (10bits x 27 channels (t-ver./v-ver.)) u(s)art/sio (channel 0) serial ports system clock generator xin-xout xcin-xcout on-chip oscillator m16c/60 series 16-bit cpu core r0l r0h r1l r1h r2 r3 a0 a1 fr r0l r0h r1l r1h r2 r3 a0 a1 fb registers sb pc isp usp program counter stack pointers intb vector table flg flag register memory multiplier flash rom ram u(s)art/sio (channel 1) u(s)art/sio/i 2 c bus/iebus (channel 2) 3-phase pwm port p0 8 port p1 8 port p2 8 port p3 8 port p6 8 port p7 8 port p8 8 port p9 7 port p10 8 timer s input capture (8 channels) output compare (8 channels) flash rom (data flash) multi-master i 2 c bus sio (channel 3) sio (channel 4) dmac (2 channels) pll frequency synthesizer crc arithmetic circuit (ccitt, crc-16) (t-ver./v-ver.) 1.3 block diagram figure 1.3.1 is a block diagram of the m16c/28 group, 80-pin device. figure 1.3.1. m16c/28 group, 80-pin block diagram
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 5 of 26 rej03b0026-0040z figure 1.3.2 is a block diagram of the m16c/28 group, 64-pin device. figure 1.3.2. m16c/28 group, 64-pin block diagram i/o ports internal peripheral functions timer timer a0 (16 bits) timer a1 (16 bits) timer a2 (16 bits) timer a3 (16 bits) timer a4 (16 bits) timer b0 (16 bits) timer b1 (16 bits) timer b2 (16 bits) watchdog timer a/d converter (10bits x 13 channels (normal-ver.)) (10bits x 16 channels (t-ver./v-ver.)) system clock generator xin-xout xcin-xcout on-chip oscillator m16c/60 series 16-bit cpu core r0l r0h r1l r1h r2 r3 a0 a1 fr r0l r0h r1l r1h r2 r3 a0 a1 fb registers sb pc isp usp program counter stack pointers intb vector table flg flag register memory multiplier flash rom ram 3-phase pwm port p0 4 port p1 3 port p2 8 port p3 4 port p6 8 port p7 8 port p8 8 port p9 4 port p10 8 timer s input capture (8 channels) output compare (8 channels) flash rom (data flash) u(s)art/sio (channel 0) serial ports u(s)art/sio (channel 1) u(s)art/sio/i 2 c bus/iebus (channel 2) multi-master i 2 c bus sio (channel 3) pll frequency synthesizer dmac (2 channels) crc arithmetic circuit (ccitt, crc-16) (t-ver./v-ver.)
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 6 of 26 rej03b0026-0040z 1.4 product list tables 1.4.1 to 1.4.3 list the m16c/28 group products and figure 1.4.1 shows the type numbers, memory sizes and packages. table 1.4.1. product list (1) -normal-ver. as of jun 2004 type no. rom capacity ram capacity package type remarks m30280f6hp (d) 48k + 4k byte 4k byte m30280f8hp (d) 64k + 4k byte 4k byte 80p6q-a m30280fahp (d) 96k + 4k byte 8k byte flash rom version m30281f6hp (d) 48k + 4k byte 4k byte m30281f8hp (d) 64k + 4k byte 4k byte 64p6q-a m30281fahp (d) 96k + 4k byte 8k byte m30280m8-xxxhp (p) 64k byte 4k byte 80p6q-a M30280MA-XXXHP (p) 96k byte 8k byte mask rom version m30281m8-xxxhp (p) 64k byte 4k byte 64p6q-a m30281ma-xxxhp (p) 96k byte 8k byte (p) : under planning (d) : under development table 1.4.2. product list (2) -t-ver. as of jun 2004 type no. rom capacity ram capacity package type remarks m30280fathp (d) 96k + 4k byte 8k byte 80p6q-a flash rom version m30281fathp (d) 96k + 4k byte 8k byte 64p6q-a m30280m8t-xxxhp (p) 64k byte 4k byte 80p6q-a m30280mat-xxxhp (p) 96k byte 8k byte mask rom version m30281m8t-xxxhp (p) 64k byte 4k byte 64p6q-a m30281mat-xxxhp (p) 96k byte 4k byte (p) : under planning (d) : under development notes: specification of t-ver. partly varies from the one of normal-ver. table 1.4.3. product list (3) -v-ver. as of jun 2004 type no. rom capacity ram capacity package type remarks m30280favhp (d) 96k + 4k byte 8k byte 80p6q-a flash rom version m30281favhp (d) 96k + 4k byte 8k byte 64p6q-a m30280m8v-xxxhp (p) 64k byte 4k byte 80p6q-a m30280mav-xxxhp (p) 96k byte 8k byte mask rom version m30281m8v-xxxhp (p) 64k byte 4k byte 64p6q-a m30281mav-xxxhp (p) 96k byte 8k byte (p) : under planning (d) : under development notes: specification of v-ver. partly varies from the one of normal-ver.
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 7 of 26 rej03b0026-0040z package type: hp : package 80p6q, 64p6q version: (no): normal-ver. t : t-ver. v : v-ver. rom capacity / ram capacity: 6: (48k+4k) bytes (note 1) /4k bytes 8: (64k+4k) bytes (note 1) /4k bytes a: (96k+4k) bytes (note 1) /8k bytes note 1: only flash memory version exists in "+4k bytes" memory type: m: mask rom version f: flash memory version type no. m 3 0 2 8 0 f 8 t h p - d3 m16c/28 group m16c family shows pin count (the value itself has no specific meaning) product code figure 1.4.1. type no., memory size, and package table 1.4.4. product code (flash memory version, normal-ver.) d 3 d 5 d 7 d 9 u 3 u 5 u 7 u 9 p r o d u c t c o d e p a c k a g e m i c r o c o m p u t e r o p e r a t i n g t e m p e r a t u r e i n t e r n a l r o m b l o c k ( 0 t o 4 ) t e m p e r a t u r e r a n g e e / w c y c l e s i n t e r n a l r o m b l o c k ( a , b ) t e m p e r a t u r e r a n g e e / w c y c l e s non-lead free lead free 1 0 0 1 , 0 0 0 1 0 0 1 , 0 0 0 0 c to 60 c 1 0 0 10,000 1 0 0 1 0 , 0 0 0 0 c t o 6 0 c -40 c to 85 c - 2 0 c t o 8 5 c 0 c t o 6 0 c - 4 0 c t o 8 5 c - 2 0 c t o 8 5 c - 4 0 c t o 8 5 c - 2 0 c t o 8 5 c - 4 0 c t o 8 5 c - 2 0 c t o 8 5 c - 4 0 c t o 8 5 c - 2 0 c t o 8 5 c - 4 0 c t o 8 5 c - 2 0 c t o 8 5 c
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 8 of 26 rej03b0026-0040z figure 1.4.2. product marking (top view) note 1. the product of the first edition and version a do not support the following functions delayed trigger mode 0 of a/d conversion delayed trigger mode 1 of a/d conversion m16c m30280fahp a d3 xxxxxxx product name : indicates m30280fahp chip version and product code: a ? indicates chip version (note 1) the first edition is shown to be blank and continues with a and b. d3 ? indicates product code (see table 1.4.4) date code (7 digits) ? indicates manufacturing management code 30281fa a d3 xxxxxxx product name : indicates m30281fahp chip version and product code: a ? indicates chip version (note 1) the first edition is shown to be blank and continues with a and b. d3 ? indicates product code (see table 1.4.4) date code (7 digits) ? indicates manufacturing management code (1) flash rom version, 80p6q-a, normal-ver. (2) flash rom version, 64p6q-a, normal-ver.
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 9 of 26 rej03b0026-0040z 1 2 3 4 5 6 7 8 9 10 11 12 p9 5 /an 25 /clk 4 13 14 15 16 17 18 19 20 cnvss reset x out vss x in vcc 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 a v cc v r e f a v ss p8 4 /int 2 /zp p9 3 /an 24 p9 2 /an 32 /tb 2in (note 2) p9 1 /an 31 /tb 1in (note 2) p9 0 /an 30 /tb 0in /clk out (note 2) p8 7 /x cin p8 6 /x cout p8 5 /nmi/sd p8 3 /int 1 p8 2 /int 0 p8 1 /ta 4in /u p8 0 /ta 4out /u p7 7 /ta 3in p 7 6 /t a 3 o u t p 7 5 /t a 2 in /w p 7 4 /t a 2 o u t /w p 7 2 /c lk 2 /t a 1 o u t /v /r x d 1 p 7 1 /r x d 2 /s c l /t a 0 in /c lk 1 p 6 7 /t x d 1 p 6 6 /r x d 1 p 6 5 /c l k 1 p 3 7 p 3 6 p 3 5 p 3 4 p 3 3 p 3 2 /s o u t 3 p 3 1 /s in 3 p 3 0 /c l k 3 p 6 3 /t x d 0 p6 2 /rxd 0 p6 1 /clk 0 p6 0 /rts 0 /cts 0 p2 7 /outc1 7 /inpc1 7 p2 6 /outc1 6 /inpc1 6 p2 5 /outc1 5 /inpc1 5 p2 4 /outc1 4 /inpc1 4 p2 3 /outc1 3 /inpc1 3 p2 2 /outc1 2 /inpc1 2 p2 1 /outc1 1 /inpc1 1 /scl mm p2 0 /outc1 0 /inpc1 0 /sda mm p1 7 /int 5 /inpc1 7 p1 6 /int 4 p1 5 /int 3 /ad trg p1 4 p1 3 /an 23 p1 2 /an 22 p1 1 /an 21 p1 0 /an 20 p0 7 /an 07 p 0 6 /a n 0 6 p 0 5 /a n 0 5 p 0 4 /a n 0 4 p 0 3 /a n 0 3 p 0 2 /a n 0 2 p 0 1 /a n 0 1 p 0 0 /a n 0 0 p 1 0 3 /a n 3 p 1 0 2 /a n 2 p 10 1 /a n 1 p 10 0 /a n 0 p 9 7 /a n 2 7 /s in 4 p 9 6 /a n 2 6 /s o u t 4 p 7 3 /c t s 2 /r t s 2 /t a 1 in /v /t x d 1 p 1 0 7 /a n 7 /k i 3 p 10 4 /a n 4 /k i 0 p 1 0 5 /a n 5 /k i 1 p 1 0 6 /a n 6 /k i 2 p 6 4 /r t s 1 /c t s 1 /c t s 0 /c l k s 1 /idv /idw /idu { / p 7 0 /t x d 2 s d a /t a 0 o u t 0 /r t s 1 /c t s 1 /c t s /c lk s 1 note 1. set pacr2 to pacr0 bit in the pacr register to "011 2 " before you input and output it after resetting to each pin. when the pacr register isnt set up, the input and output function of some of the pins are disabled. note 2. the 3 to 5 pins are shown as p9 2 /tb 2in , p9 1 /tb 1in and p9 0 /tb 0in for normal-ver. package: 80p6q-a figure 1.5.1. pin configuration (top view) of m16c/28 group, 80-pin package pin configuration (top view) 1.5 pin configuration figures 1.5.1 and 1.5.2 show the pin configurations (top view).
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 10 of 26 rej03b0026-0040z figure 1.5.2. pin configuration (top view) of m16c/28 group, 64-pin package pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cnvss vss vcc 21 22 23 24 25 26 27 28 29 30 3 1 3 2 33 34 35 36 37 38 39 40 6 0 5 9 58 5 7 56 55 54 53 52 51 5 0 4 9 48 47 46 45 44 43 42 41 64 63 62 61 avcc avss 17 18 1 9 20 p9 1 /an 31 /tb 1in (note 2) p9 0 /an 30 /tb 0in /clk out (note 2) p8 7 /x cin p8 6 /x cout x out x in p8 4 /int 2 /zp p8 3 /int 1 p8 2 /int 0 p8 1 /ta 4in /u p8 0 /ta 4out /u p7 7 /ta 3 in p7 6 /ta 3 o u t p7 5 /ta 2 in /w p7 4 /ta 2 o u t /w p7 2 /clk 2 /ta 1 o u t /v/rxd 1 p7 1 /rxd 2 /scl/ta 0 in /clk 1 p6 7 /txd 1 p6 6 /rxd 1 p6 5 /clk 1 p3 3 p3 2 /s o u t 3 p3 1 /s in 3 p3 0 /clk 3 p6 3 /txd 0 p6 2 /rxd 0 p6 1 /clk 0 p2 7 /outc1 7 /inpc1 7 p2 6 /outc1 6 /inpc1 6 p2 5 /outc1 5 /inpc1 5 p2 4 /outc1 4 /inpc1 4 p2 3 /outc1 3 /inpc1 3 p2 2 /outc1 2 /inpc1 2 p2 1 /outc1 1 /inpc1 1 /scl mm p2 0 /outc1 0 /inpc1 0 /sda mm p0 3 /an 03 p0 2 /an 0 2 p0 1 /an 0 1 p0 0 /an 0 0 p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 p10 0 /an 0 v r e f p9 3 /an 2 4 p9 2 /an 3 2 /tb 2 in (note 2) p8 5 /nmi/sd reset p7 3 /cts 2 /rts 2 /ta 1 in /v/txd 1 p6 0 /rts 0 /cts 0 p10 7 /an 7 /ki 3 p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4 /ki 0 p6 4 /rts 1 /cts 1 /cts 0 /clks 1 p1 5 /int 3 /ad trg /idv p1 6 /int 4 /idw p1 7 /int 5 /inpc1 7 /idu p7 0 /txd 2 /sda /ta 0 o u t 1 /rts 1 /cts 1 0 /cts /clks { note1. set pacr2 to pacr0 bit in the pacr register to "010 2 " before you input and output it after resetting to each pin. when the pacr register isnt set up, the input and output function of some of the pins are disabled. note 2. the 64, 1 and 2 pins are shown as p9 2 /tb 2in , p9 1 /tb 1in and p9 0 /tb 0in for normal-ver. package: 64p6q-a
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 11 of 26 rej03b0026-0040z table 1.6.1 pin description(1) 1.6 pin description table 1.6.1 and 1.6.2 describes the available pins. pin name signal name i/o type function v cc ,v ss power supply apply 0v to the vss pin, and the following voltage to the vcc pin. input 2.7 to 5.5v (normal-ver.) 3.0 to 5.5v (t-ver.) 4.2 to 5.5v (v-ver.) cnv ss cnv ss input connect this pin to vss. ____________ reset reset input input "l" on this input resets the microcomputer. x in clock input input these pins are provided for the main clock generating circuit input/ x out clock output output output. connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. if x in is not used (for external oscillator or external clock) connect x in pin to v cc and leave x out pin open. av cc analog power this pin is a power supply input for the a/d converter. connect this supply input pin to v cc . av ss analog power this pin is a power supply input for the a/d converter. connect this supply input pin to v ss . v ref reference input this pin is a reference voltage input for the a/d converter. voltage input p0 0 ~p0 7 i/o port p0 input/output this is an 8-bit cmos i/o port. it has an input/output port direction register that allows the user to set each pin for input or output individually. when used for input, a pull-up resister option can be selected for the entire group of four pins.software can also select this port to function as a/d converter input pins. p0 4 ~p0 7 are not available in the 64 pin version. p1 0 ~p1 7 i/o port p1 input/output this is an 8-bit i/o port equivalent to p0. additional software-select able secondary functions are: 1) p1 0 to p1 3 can act as a/d converter input pins; 2) p1 5 to p1 7 can be configured as external interrupt pins; 3) p1 5 to p1 7 can be configured as position-data-retain function input pins,and; 4) p1 5 can input a trigger for the a/d converter. p1 0 ~p1 4 are not available in the 64 pin version. p2 0 ~p2 7 i/o port p2 input/output this is an 8-bit i/o port equivalent to p0. software can also select this port to perform as i/o for the timer s (all pins), and multimaster i 2 c bus (p2 0 and p2 1 only) p3 0 ~p3 7 i/o port p3 input/output this is an 8-bit i/o port equivalent to p0. p3 0 to p3 2 also function as sio3 i/o, as selected by software. p3 4 ~p3 7 are not available in the 64 pin version. p6 0 ~p6 7 i/o port p6 input/output this is an 8-bit i/o port equivalent to p0. pins in this port also func- tion as uart0 and uart1 i/o, as selected by software. p7 0 ~p7 7 i/o port p7 input/output this is an 8-bit i/o port equivalent to p0. p7 can also function as i/o for timer a0-a3, as selected by software. additional programming options are: p7 0 to p7 3 can assume uart1 or uart2 i/o capa- bilities, and p7 2 to p7 5 can function as output pins for the three- phase motor control timer.
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 1. overview rev.0.40 2004.06.15 page 12 of 26 rej03b0026-0040z table 1.6.2 pin description(2) pin name signal name i/o type function p8 0 ~p8 7 i/o port p8 input/output this is an 8-bit i/o port equivalent to p0. additional software-select able secondary functions are: 1) p8 0 and p8 1 can act as either i/o for timer a4, or as output pins for the three-phase motor control timer; 2) p8 2 to p8 4 can be configured as external interrupt pins. p8 4 can be used for timer a zphase function; 3) p8 5 can be used _______ _____ as nmi/sd. p8 5 can not be used as i/o port while the three-phase motor control is enabled. apply a stable "h" to p8 5 after setting the direction register for p8 5 to "0" when the three-phase motor control is enabled, and; 4) p8 6 and p8 7 can serve as i/o pins for the sub-clock generation circuit. in this latter case, a quartz oscillator must be connented between p8 6 (x cout pin) and p8 7 (x cin pin). p9 0 ~p9 3 , i/o port p9 input/output this is an 7-bit i/o port equivalent to p0. additional software-select p9 5 ~p9 7 able secondary functions are: 1) p9 0 to p9 2 can act as timer b0~b2 input pins, or as a/d converter input pins for t-ver./v-ver.; 2) p9 0 outputs a no division, divide-by-8 or divide-by-32 clock of x in or a clock of the same frequency as xcin as selected by program for t-ver./v-ver.; 3) p9 3 , p9 5 to p9 7 can act as a/d converter input pins, and; 4) p9 5 to p9 7 can assume si/o4 i/o. p9 5 to p9 7 are not available in the 64 pin version. p10 0 ~p10 7 i/o port p10 input/output this is an 8-bit i/o port equivalent to p0. this port can also function as a/d converter input pins, as selected by software. furthermore, p10 4 -p10 7 can also function as input pins for the key input interrupt function.
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 2. central processing unit(cpu) rev.0.40 2004.06.15 page 13 of 26 rej03b0026-0040z 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. figure 2.1. central processing unit register 2.1 data registers (r0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32- bit data register (r2r0). r3r1 is the same as r2r0. 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. they also are used for transfers and arithmetic/logic operations. a1 is the same as a0. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). data registers (note) address registers (note) frame base registers (note) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register note: these registers comprise a register bank. there are two register banks. r0h(r0's high bits) b15 b8 b7 b0 r3 intbh usp isp sb aa aa a a aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl r0l(r0's low bits) r1h(r1's high bits) r1l(r1's low bits) r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl.
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 2. central processing unit(cpu) rev.0.40 2004.06.15 page 14 of 26 rej03b0026-0040z 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to 0. 2.8.3 zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0. 2.8.4 sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0 . 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. 2.8.6 overflow flag (o flag) this flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0. 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is 0, and are enabled when the i flag is 1. the i flag is cleared to 0 when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is 0; usp is selected when the u flag is 1. the u flag is cleared to 0 when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write "0". when read, its content is indeterminate.
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 3. memory rev.0.40 2004.06.15 page 15 of 26 rej03b0026-0040z 3. memory figure 3.1 is a memory map of the m16c/28 group. the linear address space of 1m bytes extends from address 00000 16 to fffff 16 . from fffff 16 down is rom. for example, in the m30280f8hp,there are 64 kbytes of internal rom from f0000 16 to fffff 16 . the vector table for fixed interrupts, such as reset and nmi, is mapped from fffdc 16 to fffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts,etc.,can be set as desired using the interrupt table register(intb). see the section on interrupts for details. from 00400 16 up is ram. for example, in the m30280fahp, 4k bytes of internal ram is mapped to the space from 00400 16 to 013ff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. these devices also contain two blocks of flash rom as data flash memory to store data. these two blocks of 2k bytes are located from 0f000 16 to 0ffff 16 on all versions. the sfr area is mapped from 00000 16 to 003ff 16 . this area accommodates the control registers for peripheral devices such as i/o ports, a/d converter, serial i/o, and timers, etc. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is allocated to the address from ffe00 16 to fffdb 16 . this vector is used by the jmps or jsrs instruction. for details, refer to the "m16c/60 and m16c/20 series software manual". figure 3.1. memory map 00000 16 xxxxx 16 fffff 16 00400 16 yyyyy 16 internal rom area (program area) sfr area internal ram area ffe00 16 fffdc 16 fffff 16 undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc reserved internal rom area (data area) reserved 0f000 16 xxxxx 16 yyyyy 16 internal ram area internal rom area memory size 013ff 16 023ff 16 f4000 16 f0000 16 4k byte 8k byte 48k byte 64k byte memory size e8000 16 96k byte note 1 : the block a (2k bytes) and block b (2k bytes) are shown (only flash memory) note 2 : when using the masked rom version, write nothing to internal rom area. (note1) 0ffff 16 nmi (note2)
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.40 2004.06.15 page 16 of 26 rej03b0026-0040z note 1: the blank areas are reserved and cannot be accessed by users. note 2: the cm20, cm21, and cm27 bits do not change at oscillation stop detection reset. note 3: tjhe wdc5 bit is "0" (cold start) immediately after power-on. it can only be set to "1" in a program. it is set to "0" when the input voltage at the vcc pin drops to vdet2 or less while the vc25 bit in the vcr2 register is set to "1"(ram retention limit dete ction circuit enable). note 4: this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. note 5: this register can not use for t-ver. and v-ver. x : noting is mapped to this bit ? : value indeterminate at reset 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address register name acronym value after reset processor mode register 0 pm0 00 16 processor mode register 1 pm1 00001000 2 system clock control register 0 cm0 01001000 2 system clock control register 1 cm1 00100000 2 address match interrupt enable register aier xxxxxx00 2 protect register prcr xx000000 2 oscillation stop detection register (note 2) cm2 0x000010 2 watchdog timer start register wdts ?? 16 watchdog timer control register wdc 00?????? 2 (note 3) address match interrupt register 0 rmad0 00 16 00 16 x0 16 address match interrupt register 1 rmad1 00 16 00 16 x0 16 voltage detection register 1 (note 4,5) vcr1 00001000 2 voltage detection register 2 (note 4,5) vcr2 00 16 pll control register 0 plc0 0001x010 2 processor mode register 2 pm2 xxx00000 2 voltage down detection interrupt register (note 5) d4int 00 16 dma0 source pointer sar0 ?? 16 ?? 16 x? 16 dma0 destination pointer dar0 ?? 16 ?? 16 x? 16 dma0 transfer counter tcr0 ?? 16 ?? 16 dma0 control register dm0con 00000?00 2 dma1 source pointer sar1 ?? 16 ?? 16 x? 16 dma1 destination pointer dar1 ?? 16 ?? 16 x? 16 dma1 transfer counter tcr1 ?? 16 ?? 16 dma1 control register dm1con 00000?00 2 4. special function register (sfr) map figure 4.1. sfr map (1 of 7)
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.40 2004.06.15 page 17 of 26 rej03b0026-0040z int3 interrupt control register int3ic xx00?000 2 ic/oc 0 interrupt control register icoc0ic xxxx?000 2 ic/oc 1 interrupt control register, i 2 c-bus interface interrupt control register icoc1ic, iicic x xxx?000 2 ic/oc base timer interrupt control register, s cl s da interrupt control register btic, scldaic xxxx?000 2 si/o4 interrupt control register, int5 interrupt control register s4ic, int5ic xx00?000 2 si/o3 interrupt control register, int4 interrupt control register s3ic, int4ic xx00?000 2 uart2 bus collision detection interrupt control register bcnic xxxx?000 2 dma0 interrupt control register dm0ic xxxx?000 2 dma1 interrupt control register dm1ic xxxx?000 2 key input interrupt control register kupic xxxx?000 2 a/d conversion interrupt control register adic xxxx?000 2 uart2 transmit interrupt control register s2tic xxxx?000 2 uart2 receive interrupt control register s2ric xxxx?000 2 uart0 transmit interrupt control register s0tic xxxx?000 2 uart0 receive interrupt control register s0ric xxxx?000 2 uart1 transmit interrupt control register s1tic xxxx?000 2 uart1 receive interrupt control register s1ric xxxx?000 2 timer a0 interrupt control register ta0ic xxxx?000 2 timer a1 interrupt control register ta1ic xxxx?000 2 timer a2 interrupt control register ta2ic xxxx?000 2 timer a3 interrupt control register ta3ic xxxx?000 2 timer a4 interrupt control register ta4ic xxxx?000 2 timer b0 interrupt control register tb0ic xxxx?000 2 timer b1 interrupt control register tb1ic xxxx?000 2 timer b2 interrupt control register tb2ic xxxx?000 2 int0 interrupt control register int0ic xx00?000 2 int1 interrupt control register int1ic xx00?000 2 int2 interrupt control register int2ic xx00?000 2 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 address register name acronym value after reset note 1: the blank areas are reserved and cannot be accessed by users. x : noting is mapped to this bit ? : value indeterminate at reset figure 4.2. sfr map (2 of 7)
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.40 2004.06.15 page 18 of 26 rej03b0026-0040z 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 01be 16 01bf 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 02e0 16 02e1 16 02e2 16 02e3 16 02e4 16 02e5 16 02e6 16 02e7 16 02e8 16 02e9 16 02ea 16 02fe 16 02ff 16 note 1:the blank areas are reserved and cannot be accessed by users. note 2:this register is included in the flash memory version. note 3:this register is included in t-ver. and v-ver. x : noting is mapped to this bit ? : value indeterminate at reset address register name acronym value after reset flash memory control register 4 (note 2) fmr4 01000000 2 flash memory control register 1 (note 2) fmr1 000???0? 2 flash memory control register 0 (note 2) fmr0 01 16 three-phase protect control register (note 3) tprc 00 16 on-chip oscillator control register rocr 00000101 2 pin assignment control register pacr 00 16 peripheral clock select register pclkr 00000011 2 i 2 c0 data shift register s00 ?? 16 i 2 c0 address register s0d0 00 16 i 2 c0 control register 0 s1d0 00 16 i 2 c0 clock control register s20 00 16 i 2 c0 start/stop condition control register s2d0 00011010 2 i 2 c0 control register 1 s3d0 00110000 2 i 2 c0 control register 2 s4d0 00 16 i 2 c0 status register s10 0001000x 2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ figure 4.3. sfr map (3 of 7)
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.40 2004.06.15 page 19 of 26 rej03b0026-0040z note 1:the blank areas are reserved and cannot be accessed by users. x : noting is mapped to this bit ? : value indeterminate at reset 0300 16 0301 16 0302 16 0303 16 0304 16 0305 16 0306 16 0307 16 0308 16 0309 16 030a 16 030b 16 030c 16 030d 16 030e 16 030f 16 0310 16 0311 16 0312 16 0313 16 0314 16 0315 16 0316 16 0317 16 0318 16 0319 16 031a 16 031b 16 031c 16 031d 16 031e 16 031f 16 0320 16 0321 16 0322 16 0323 16 0324 16 0325 16 0326 16 0327 16 0328 16 0329 16 032a 16 032b 16 032c 16 032d 16 032e 16 032f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 tm, wg register 0 g1tm0, g1po0 ?? 16 ?? 16 tm, wg register 1 g1tm1, g1po1 ?? 16 ?? 16 tm, wg register 2 g1tm2, g1po2 ?? 16 ?? 16 tm, wg register 3 g1tm3, g1po3 ?? 16 ?? 16 tm, wg register 4 g1tm4, g1po4 ?? 16 ?? 16 tm, wg register 5 g1tm5, g1po5 ?? 16 ?? 16 tm, wg register 6 g1tm6, g1po6 ?? 16 ?? 16 tm, wg register 7 g1tm7, g1po7 ?? 16 ?? 16 wg control register 0 g1pocr0 0x00xx00 2 wg control register 1 g1pocr1 0x00xx00 2 wg control register 2 g1pocr2 0x00xx00 2 wg control register 3 g1pocr3 0x00xx00 2 wg control register 4 g1pocr4 0x00xx00 2 wg control register 5 g1pocr5 0x00xx00 2 wg control register 6 g1pocr6 0x00xx00 2 wg control register 7 g1pocr7 0x00xx00 2 tm control register 0 g1tmcr0 00 16 tm control register 1 g1tmcr1 00 16 tm control register 2 g1tmcr2 00 16 tm control register 3 g1tmcr3 00 16 tm control register 4 g1tmcr4 00 16 tm control register 5 g1tmcr5 00 16 tm control register 6 g1tmcr6 00 16 tm control register 7 g1tmcr7 00 16 base timer register g1bt ?? 16 ?? 16 base timer control register 0 g1bcr0 00 16 base timer control register 1 g1bcr1 00 16 tm prescale register 6 g1tpr6 00 16 tm prescale register 7 g1tpr7 00 16 function enable register g1fe 00 16 function select register g1fs 00 16 base timer reset register g1btrr ?? 16 ?? 16 divider register g1dv 00 16 interrupt request register g1ir ?? 16 interrupt enable register 0 g1ie0 00 16 interrupt enable register 1 g1ie1 00 16 nmi digital debounce register nddr ff 16 p17 digital debounce register p17ddr ff 16 address register name acronym value after reset figure 4.4. sfr map (4 of 7)
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.40 2004.06.15 page 20 of 26 rej03b0026-0040z 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 note 1: the blank areas are reserved and cannot be accessed by users. note 2: write "1" to bit 0 after reset. note 3:this register is included in t-ver. and v-ver. x : noting is mapped to this bit ? : value indeterminate at reset timer a1-1 register ta11 ?? 16 ?? 16 timer a2-1 register ta21 ?? 16 ?? 16 timer a4-1 register ta41 ?? 16 ?? 16 three-phase pwm control register 0 invc0 00 16 three-phase pwm control register 1 invc1 00 16 three-phase output buffer register 0 idb0 00 16 three-phase output buffer register 1 idb1 00 16 dead time timer dtt ?? 16 timer b2 interrupt occurrence frequency set counter ictb2 x? 16 position-data-retain function contol register pdrf xxxx0000 2 port function control register (note 3) pfcr 00111111 2 interrupt request cause select register 2 ifsr2a 00xxxxx0 2 (note 2) interrupt request cause select register ifsr 00 16 si/o3 transmit/receive register s3trr ?? 16 si/o3 control register s3c 01000000 2 si/o3 bit rate generator s3brg ?? 16 si/o4 transmit/receive register s4trr ?? 16 si/o4 control register s4c 01000000 2 si/o4 bit rate generator s4brg ?? 16 uart2 special mode register 4 u2smr4 00 16 uart2 special mode register 3 u2smr3 000x0x0x 2 uart2 special mode register 2 u2smr2 x0000000 2 uart2 special mode register u2smr x0000000 2 uart2 transmit/receive mode register u2mr 00 16 uart2 bit rate generator u2brg ?? 16 uart2 transmit buffer register u2tb ???????? 2 xxxxxxx? 2 uart2 transmit/receive control register 0 u2c0 00001000 2 uart2 transmit/receive control register 1 u2c1 00000010 2 uart2 receive buffer register u2rb ???????? 2 ?????xx? 2 address register name acronym value after reset figure 4.5. sfr map (5 of 7)
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.40 2004.06.15 page 21 of 26 rej03b0026-0040z 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 count start flag tabsr 00 16 clock prescaler reset flag cpsrf 0xxxxxxx 2 one-shot start flag onsf 00 16 trigger select register trgsr 00 16 up-down flag udf 00 16 timer a0 register ta0 ?? 16 ?? 16 timer a1 register ta1 ?? 16 ?? 16 timer a2 register ta2 ?? 16 ?? 16 timer a3 register ta3 ?? 16 ?? 16 timer a4 register ta4 ?? 16 ?? 16 timer b0 register tb0 ?? 16 ?? 16 timer b1 register tb1 ?? 16 ?? 16 timer b2 register tb2 ?? 16 ?? 16 timer a0 mode register ta0mr 00 16 timer a1 mode register ta1mr 00 16 timer a2 mode register ta2mr 00 16 timer a3 mode register ta3mr 00 16 timer a4 mode register ta4mr 00 16 timer b0 mode register tb0mr 00??0000 2 timer b1 mode register tb1mr 00?x0000 2 timer b2 mode register tb2mr 00?x0000 2 timer b2 special mode register tb2sc x0000000 2 uart0 transmit/receive mode register u0mr 00 16 uart0 bit rate generator u0brg ?? 16 uart0 transmit buffer register u0tb ???????? 2 xxxxxxx? 2 uart0 transmit/receive control register 0 u0c0 00001000 2 uart0 transmit/receive control register 1 u0c1 00000010 2 uart0 receive buffer register u0rb ???????? 2 ?????xx? 2 uart1 transmit/receive mode register u1mr 00 16 uart1 bit rate generator u1brg ?? 16 uart1 transmit buffer register u1tb ???????? 2 xxxxxxx? 2 uart1 transmit/receive control register 0 u1c0 00001000 2 uart1 transmit/receive control register 1 u1c1 00000010 2 uart1 receive buffer register u1rb ???????? 2 ?????xx? 2 uart transmit/receive control register 2 ucon x0000000 2 crc snoop address register (note 2) crcsar ?? 16 00xxxx?? 2 crc mode register (note 2) crcmr 0xxxxxx0 2 dma0 request cause select register dm0sl 00 16 dma1 request cause select register dm1sl 00 16 crc data register (note 2) crcd ?? 16 ?? 16 crc input register (note 2) crcin ?? 16 address register name acronym value after reset note 1:the blank areas are reserved and cannot be accessed by users. note 2:this register is included in t-ver. and v-ver. x : noting is mapped to this bit ? : value indeterminate at reset figure 4.6. sfr map (6 of 7)
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function register (sfr) map rev.0.40 2004.06.15 page 22 of 26 rej03b0026-0040z figure 4.7. sfr map (7 of 7) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 a/d register 0 ad0 ???????? 2 xxxxxx?? 2 a/d register 1 ad1 ???????? 2 xxxxxx?? 2 a/d register 2 ad2 ???????? 2 xxxxxx?? 2 a/d register 3 ad3 ???????? 2 xxxxxx?? 2 a/d register 4 ad4 ???????? 2 xxxxxx?? 2 a/d register 5 ad5 ???????? 2 xxxxxx?? 2 a/d register 6 ad6 ???????? 2 xxxxxx?? 2 a/d register 7 ad7 ???????? 2 xxxxxx?? 2 a/d trigger control register adtrgcon xxxx0000 2 a/d convert status register 0 adstat0 00000x00 2 a/d control register 2 adcon2 00 16 a/d control register 0 adcon0 00000??? 2 a/d control register 1 adcon1 00 16 port p0 register p0 ?? 16 port p1 register p1 ?? 16 port p0 direction register pd0 00 16 port p1 direction register pd1 00 16 port p2 register p2 ?? 16 port p3 register p3 ?? 16 port p2 direction register pd2 00 16 port p3 direction register pd3 00 16 port p6 register p6 ?? 16 port p7 register p7 ?? 16 port p6 direction register pd6 00 16 port p7 direction register pd7 00 16 port p8 register p8 ?? 16 port p9 register p9 ???x???? 2 port p8 direction register pd8 00 16 port p9 direction register pd9 000x0000 2 port p10 register p10 ?? 16 port p10 direction register pd10 00 16 pull-up control register 0 pur0 00 16 pull-up control register 1 pur1 00 16 pull-up control register 2 pur2 00 16 port control register pcr 00 16 note 1:the blank areas are reserved and cannot be accessed by users. x : noting is mapped to this bit ? : value indeterminate at reset address register name acronym value after reset
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 5. package rev.0.40 2004.06.15 page 23 of 26 rej03b0026-0040z 5. package lqfp64-p-1010-0.5 weight(g) jedec code eiaj package code lead material cu alloy 64p6q-a plastic 64pin 10 ? 10mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 10.4 m e 10.4 10 0 0.1 1.0 0.7 0.5 0.3 12.2 12.0 11.8 12.2 12.0 11.8 0.5 10.1 10.0 9.9 10.1 10.0 9.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e h e 49 48 33 32 17 16 1 64 h d d m d m e a f y b 2 i 2 recommended mount pad lp 0.45 0.6 0.25 0.75 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c e recommended lqfp80-p-1212-0.5 weight(g) 0.47 jedec code eiaj package code lead material cu alloy 80p6q-a plastic 80pin 12 ? 12mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 0.9 m d 12.4 m e 12.4 10 0 0.1 1.0 0.7 0.5 0.3 14.2 14.0 13.8 14.2 14.0 13.8 0.5 12.1 12.0 11.9 12.1 12.0 11.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e a f e h d e h e d 1 20 21 40 41 60 61 80 y lp 0.45 0.6 0.25 0.75 0.08 x a3 m d l 2 b 2 m e e recommended mount pad b x m a 1 a 2 l 1 l detail f lp a3 c recommended
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 6. functional differences rev.0.40 2004.06.15 page 24 of 26 rej03b0026-0040z 6. functional differences 6.1 functional differences between normal-ver. and t-ver./v-ver. of m16c/28 group (note1) item detailed item m16c/28(normal-ver.) m16c/28(t-ver./v-ver.) clock clock output function not available available (b1-b0 bit of cm0 register) (reserved bit) (clock output function select bit) reset voltage detection circuit available not available (function of 0019 16 , 001a 16 , (power supply detection register 1, (reserved register) 001f 16 ) power supply detection register 2, power supply down detection interrupt register) three-phase motor three-phase/port output not available available control timer switch function (0358 16 ) (nothing is assigned) (port function control register) a/d conversionanalog input pins 24 channels 27 channels (an 30 to an 32 not available) (an 30 to an 32 available) delayed trigger mode 0 the product of the first edition available and version a do not available delayed trigger mode 1 the product of the first edition available and version a do not available crc calculation crc-ccitt and crc-16 not available available (related registers are not assigned) (1 curcuit) pin function 3 pin (80 pin version) p9 2 /tb 2in p9 2 /an 32 /tb 2in 64 pin (64 pin version) 4 pin (80 pin version) p9 1 /tb 1in p9 1 /an 31 /tb 1in 1 pin (64 pin version) 5 pin (80 pin version) p9 0 /tb 0in p9 0 /an 30 /tb 0in /clk out 2 pin (64 pin version) note 1. since the emulator between the m16c/28 and m16c/29 group are same, all functions of m16c/29 are built in the emulator. when evaluating m16c/28 group, do not access to the sfr which is not built in m16c/28 group. refer to hardware manual about detail and electrical characteristics.
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 6. functional differences rev.0.40 2004.06.15 page 25 of 26 rej03b0026-0040z 6.2 functional differences between m16c/28 group and m16c/29 group (normal-ver.) (note 1) item detailed item m16c/28(normal-ver.) m16c/29(normal-ver.) clock clock output function not available available (reserved bit) (clock output function select bit) protect prc0 bit function enable wrtite to cm0, cm1, enable write to cm0, cm1, cm2, pocr, plc0, pclkr cm2, pocr, plc0, pclkr, registers cclkr registers interrupt ifsr20 bit of ifsr2a must be set to "1" must be set to "0" register b1 bit of ifsr2a register nothing is assigned interrupt request cause select bit (when write, set to "0") (0:a/d conversion 1:key input) b2 bit of ifsr2a register nothing is assigned interrupt request cause select bit (when write, set to "0") (0:can0 wakeup/error) interrupr source of software key input interrupt can0 error interrupt number 13 interrupr source of software a/d conversion interrupt a/d conversion/key input interrupt interrupt number 14 three-phase motor three-phase/port output not available available control timer switch function (0358 16 ) (nothing is assigned) (port function control register) a/d conversion analog input pins 24 channels 27 channels (an 30 to an 32 not available) (an 30 to an 32 available) delayed trigger mode 0 the product of the first edition available and version a do not available delayed trigger mode 1 the product of the first edition available and version a do not available can module 2.0b bosch compliant not available available (related registers are not assigned) (1channel) crc calculation crc-ccitt and crc-16 not available available (related registers are not assigned) (1 curcuit) pin function 2 pin (80 pin version) p9 3 /an 24 p9 3 /an 24 /ctx 62 pin (64 pin version) 3 pin (80 pin version) p9 2 /tb 2in p9 2 /an 32 /tb 2in /crx 64 pin (64 pin version) 4 pin (80 pin version) p9 1 /tb 1in p9 1 /an 31 /tb 1in 1 pin (64 pin version) 5 pin (80 pin version) p9 0 /tb 0in p9 0 /an 30 /tb 0in /clk out 2 pin (64 pin version) note 1. since the emulator between the m16c/28 and m16c/29 group are same, all functions of m16c/29 are built in the emulator. when evaluating m16c/28 group, do not access to the sfr which is not built in m16c/28 group. refer to hardware manual about detail and electrical characteristics.
m16c/28 group under development preliminary specification specifications in this manual are tentative and subject to change. 6. functional differences rev.0.40 2004.06.15 page 26 of 26 rej03b0026-0040z item detailed item m16c/28(t-ver./v-ver.) m16c/29(t-ver./v-ver.) protect prc0 bit function enable wrtite to cm0, cm1, enable write to cm0, cm1, cm2, pocr, plc0, pclkr cm2, pocr, plc0, pclkr, registers cclkr registers interrupt ifsr20 bit of ifsr2a must be set to "1" must be set to "0" register b1 bit of ifsr2a register nothing is assigned interrupt request cause select bit (when write, set to "0") (0:a/d conversion 1:key input) b2 bit of ifsr2a register nothing is assigned interrupt request cause select bit (when write, set to "0") (0:can0 wakeup/error) interrupr source of software key input interrupt can0 error interrupt number 13 interrupr source of software a/d conversion interrupt a/d conversion/key input interrupt interrupt number 14 can module 2.0b bosch compliant not available available (related registers are not assigned) (1channel) pin function 2 pin (80 pin version) p9 3 /an 24 p9 3 /an 24 /ctx 62 pin (64 pin version) 3 pin (80 pin version) p9 2 /tb 2in p9 2 /an 32 /tb 2in /crx 64 pin (64 pin version) note 1. since the emulator between the m16c/28 and m16c/29 group are same, all functions of m16c/29 are built in the emulator. when evaluating m16c/28 group, do not access to the sfr which is not built in m16c/28 group. refer to hardware manual about detail and electrical characteristics. 6.3 functional differences between m16c/28 group and m16c/29 group (t-ver./v-ver.)(note 1)
revision history m16c/28 short sheet rev. date description page summary a-1 0.20 dec/ 01/ 03 first edition 0.40 jun/15/04 2,3 table 1.2.1 and 1.2.2 are partly revised, and integrated descriptions. 4,5 figure 1.3.1 and 1.3.2 are integrated descriptions. 6 table 1.4.1 to 1.4.3 are partly revised. 7 figure 1.4.1 and table 1.4.4 are partly revised. table 1.4.5 is deleted. 8 figure 1.4.2 is added. 9, 10 figure 1.5.1 and 1.5.2 are partly revised. 11,12 table 1.6.1 and 1.6.2 are partly revised and integrated descriptions. 15 the chapter 3. memory and figure 3.1 are integrated descriptions and partly r evised. note 2 in figure 3.1 is revised. 16 figure 4.1 is partly revised. 17,18 figure 4.2 and 4.3 are integrated descriptions. 18 three-phase protect control register is added. 19,20 figure 4.4 and 4.5 are partly revised. 20 port function control register is added. 21 registers of the crc arithmetic circuit are added. 22 figure 4.7 is integrated descriptions. 23 64p6q-a package is revised. 24 to 26 the chapter 6. functional differences is added.
m16c/26a group keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation p roduct best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporat ion or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origin ating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reas ons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas te chnology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp oration assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor wh en considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan.

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