TLP715F 2009-04-20 1 weight:0.26 g(typ.) toshiba 11-5j101 unit in mm 0.25 ? 0.05 +0.10 4.580.25 0.40.1 1 2 3 6.80.25 1.270.2 3.65 +0.15 ? 0.25 6 5 4 11.70.3 3.9 +0.25 ? 0.15 0.750.25 7.620.25 11-5j101 toshiba photocoupler gaa ? as ired & photo-ic TLP715F isolated bus drivers high speed line receivers microprocessor system interfaces the toshiba TLP715F consists of a gaa ? as light-emitting diode and an integrated high-gain, high-s peed photodetector. this unit is a 6-pin sdip. the TLP715F is 50% smaller than the 8-pin dip and meets the reinforced insulation class requirements of internat ional safety standards. therefore the mounting area can be reduced in equip ment requiring safety standard certification. the detector has a totem pole output stage to provide both source and sink driving. the detector ic has an internal shield that provides a guaranteed common-mode transient immunity of 10 kv/ s. the TLP715F is buffer logic type. for inverter logic type, the tlp718f is in line-up. absolute maximum ratings and electrical characteristics are the same as in the tlp715 technical data sheets. z buffer logic output (totem pole output) z guaranteed performance over temperature : ? 40 to 100c z power supply voltage : 4.5 to 20 v z input current: i flh = 3ma (max.) z switching time ( t plh / t phl) : 250 ns (max.) z common-mode transient immunity : 10 kv/ s (min) z isolation voltage : 5000 vrms (min) z ul recognized ul1577, file no.e67349 z c-ul recognized csa component acceptance service no. 5a, file no.e67349 z option (d4) tv recognized / vde under application : din en60747-5-2 maximum operati ng insulation voltage : 1140v pk highest permissible over voltage : 8000v pk (note) : when a en60747-5-2 approved type is needed, please designate ?option(d4)? z construction mechanical rating 7.62 mm pitch standard type 10.16 mm pitch tlpxxxf type creepage distance clearance insulation thickness 7.0 mm (min) 7.0 mm (min) 0.4 mm (min) 8.0 mm (min) 8.0 mm (min) 0.4 mm (min) truth table input led tr1 tr2 output h on on off h l off off on l pin configuration (top view) 0.1 f bypass capacitor must be connected between pins 6 and 4. schematic v cc v o gnd i cc i o 6 5 4 shield 3- 1+ i f vf tr1 tr2 vcc gnd shield 1 3 4 5 6 2 1:anode 2:n.c. 3:cathode 4:gnd 5:vo (output) 6:vcc v cc v o gnd i cc i o 6 5 4 shield 3- 1+ i f vf tr1 tr2
TLP715F 2009-04-20 2 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collect ively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software a nd systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba?s written permission, reproduc tion is permissible only if reproducti on is without alteration/omission. ? though toshiba works continually to improve product?s quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a ma lfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before creating and producing des igns and using, customers mus t also refer to and comply with (a) the latest versions of all re levant toshiba information, including without limitation, this d ocument, the specifications, the data sheets and applic ation notes for product and the precautions and conditions set forth in the ?tosh iba semiconductor reliability handbook? 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