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pz3032 32 macrocell cpld product specification 1997 feb 20 integrated circuits ic27 data handbook
philips semiconductors product specification pz3032 32 macrocell cpld 2 1997 feb 20 8531852 17780 features ? industry's first totalcmos ? pld both cmos design and process technologies ? fast zero power (fzp ? ) design technique provides ultra-low power and very high speed ? high speed pin-to-pin delays of 8ns ? ultra-low static power of less than 35 m a ? dynamic power that is 70% lower at 50mhz than competing devices ? 100% routable with 100% utilization while all pins and all macrocells are fixed ? deterministic timing model that is extremely simple to use ? 2 clocks with programmable polarity at every macrocell ? support for complex asynchronous clocking ? innovative xpla ? architecture combines high speed with extreme flexibility ? 1000 erase/program cycles guaranteed ? 20 years data retention guaranteed ? logic expandable to 37 product terms ? pci compliant ? advanced 0.5 m e 2 cmos process ? security bit prevents unauthorized access ? design entry and verification using industry standard and philips cae tools ? reprogrammable using industry standard device programmers ? innovative control term structure provides either sum terms or product terms in each logic block for: programmable 3-state buffer asynchronous macrocell register preset/reset ? programmable global 3-state pin facilitates `bed of nails' testing without using logic resources ? available in both plcc and tqfp packages table 1. pz3032 features pz3032 usable gates 1000 maximum inputs 36 maximum i/os 32 number of macrocells 32 i/o macrocells 32 buried macrocells 0 propagation delay (ns) 8.0 packages 44-pin plcc, 44-pin tqfp description the pz3032 cpld (complex programmable logic device) is the first in a family of fast zero power (fzp ? ) cplds from philips semiconductors. these devices combine high speed and zero power in a 32 macrocell cpld. with the fzp ? design technique, the pz3032 offers true pin-to-pin speeds of 8ns, while simultaneously delivering power that is less than 35 m a at standby without the need for `turbo bits' or other power down schemes. by replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in plds since the bipolar era) with a cascaded chain of pure cmos gates, the dynamic power is also substantially lower than any competing cpld 70% lower at 50mhz. these devices are the first totalcmos ? plds, as they use both a cmos process technology and the patented full cmos fzp ? design technique. for 5v applications, philips also offers the high speed pz5032 cpld that offers pin-to-pin speeds of 6ns. the philips fzp ? cplds introduce the new patent-pending xpla ? (extended programmable logic array) architecture. the xpla ? architecture combines the best features of both pla and pal ? type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. the xpla ? structure in each logic block provides a fast 8ns pal ? path with 5 dedicated product terms per output. this pal ? path is joined by an additional pla structure that deploys a pool of 32 product terms to a fully programmable or array that can allocate the pla product terms to any output in the logic block. this combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. the speed with which logic is allocated from the pla array to an output is only 2.5ns, regardless of the number of pla product terms used, which results in worst case t pd 's of only 10.5ns from any pin to any other pin. in addition, logic that is common to multiple outputs can be placed on a single pla product term and shared across multiple outputs via the or array, effectively increasing design density. the pz3032 cplds are supported by industry standard cae tools (cadence, mentor, synopsys, synario, viewlogic, orcad), using text (abel, vhdl, verilog) and/or schematic entry. design verification uses industry standard simulators for functional and timing simulation. development is supported on personal computer, sparc, and hp platforms. device fitting uses either minc or philips semiconductors-developed tools. the pz3032 cpld is reprogrammable using industry standard device programmers from vendors such as data i/o, bp microsystems, sms, and others. pal is a registered trademark of advanced micro devices, inc.
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 3 ordering information order code description description drawing number pz30328a44 44-pin plcc, 8ns t pd commercial temp range, 3.3 volt power supply, 10% sot187-2 pz303210a44 44-pin plcc, 10ns t pd commercial temp range, 3.3 volt power supply, 10% sot187-2 pz303212a44 44-pin plcc, 12ns t pd commercial temp range, 3.3 volt power supply, 10% sot187-2 pz3032i10a44 44-pin plcc, 10ns t pd industrial temp range, 3.3 volt power supply, 10% sot187-2 pz3032i12a44 44-pin plcc, 12ns t pd industrial temp range, 3.3 volt power supply, 10% sot187-2 pz30328bc 44-pin tqfp, 8ns t pd , commercial temp range, 3.3 volt power supply, 10% sot376-1 pz303210bc 44-pin tqfp, 10ns t pd commercial temp range, 3.3 volt power supply, 10% sot376-1 pz303212bc 44-pin tqfp, 12ns t pd commercial temp range, 3.3 volt power supply, 10% sot376-1 pz3032i10bc 44-pin tqfp, 10ns t pd industrial temp range, 3.3 volt power supply, 10% sot376-1 pz3032i12bc 44-pin tqfp, 12ns t pd industrial temp range, 3.3 volt power supply, 10% sot376-1 xpla ? architecture figure 1 shows a high level block diagram of a 64 macrocell device implementing the xpla ? architecture. the xpla ? architecture consists of logic blocks that are interconnected by a zero-power interconnect array (zia). the zia is a virtual crosspoint switch. each logic block is essentially a 36v16 device with 36 inputs from the zia and 16 macrocells. each logic block also provides 32 zia feedback paths from the macrocells and i/o pins. from this point of view, this architecture looks like many other cpld architectures. what makes the coolrunner ? family unique is what is inside each logic block and the design technique used to implement these logic blocks. the contents of the logic block will be described next. logic block architecture figure 2 illustrates the logic block architecture. each logic block contains control terms, a pal array, a pla array, and 16 macrocells. the 6 control terms can individually be configured as either sum or product terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. the pal array consists of a programmable and array with a fixed or array, while the pla array consists of a programmable and array with a programmable or array. the pal array provides a high speed path through the array, while the pla array provides increased product term density. each macrocell has 5 dedicated product terms from the pal array. the pin-to-pin t pd of the pz3032 device through the pal array is 8ns. this performance is the fastest 3 volt cpld available today. if a macrocell needs more than 5 product terms, it simply gets the additional product terms from the pla array. the pla array consists of 32 product terms, which are available for use by all 16 macrocells. the additional propagation delay incurred by a macrocell using 1 or all 32 pla product terms is just 2.5ns. so the total pin-to-pin t pd for the pz3032 using 6 to 37 product terms is 10.5ns (8ns for the pal + 2.5ns for the pla). logic block i/o 36 16 16 36 16 16 mc0 mc1 mc15 i/o mc0 mc1 mc15 logic block i/o 36 16 16 36 16 16 mc0 mc1 mc15 i/o mc0 mc1 mc15 sp00439 zia logic block logic block figure 1. philips xpla cpld architecture
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 4 to 16 macrocells 6 5 control pal array 36 zia inputs pla array (32) sp00435 figure 2. philips logic block architecture
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 5 macrocell architecture figure 3 shows the architecture of the macrocell used in the coolrunner ? family. the macrocell consists of a flip-flop that can be configured as either a d or t type. a d-type flip-flop is generally more useful for implementing state machines and data buffering. a t-type flip-flop is generally more useful in implementing counters. all coolrunner ? family members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. these devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. there are 2 clocks (clk0 and clk1) available on the pz3032 device. clock 0 (clk0) is designated as the asynchronouso clock and must be driven by an external source. clock 1 (clk1) can either be used as a synchronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). two of the control terms (ct0 and ct1) are used to control the preset/reset of the macrocell's flip-flop. the preset/reset feature for each macrocell can also be disabled. note that the power-on reset leaves all macrocells in the azeroo state when power is properly applied. the other 4 control terms (ct2ct5) can be used to control the output enable of the macrocell's output buffers. the reason there are as many control terms dedicated for the output enable of the macrocell is to insure that all coolrunner ? devices are pci compliant. the macrocell's output buffers can also be always enabled or disabled. all coolrunner ? devices also provide a global tri-state (gts ) pin, which, when pulled low, will 3-state all the outputs of the device. this pin is provided to support ain-circuit testingo or abed-of-nails testingo. there are two feedback paths to the zia: one from the macrocell, and one from the i/o pin. the zia feedback path before the output buffer is the macrocell feedback path, while the zia feedback path after the output buffer is the i/o pin zia path. when the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. when the i/o pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the zia via the i/o feedback path, and the logic implemented in the buried macrocell can be fed back to the zia via the macrocell feedback path. it should be noted that unused inputs or i/os should be properly terminated. ct2 ct3 ct4 ct5 v cc gnd init (p or r) d/t q sp00440 clk0 clk0 clk1 clk1 to zia gnd ct0 ct1 gnd gts figure 3. pz3032 macrocell architecture
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 6 simple timing model figure 4 shows the coolrunner ? timing model. the coolrunner ? timing model looks very much like a 22v10 timing model in that there are three main timing parameters, including t pd , t su , and t co . in other competing architectures, the user may be able to fit the design into the cpld, but is not sure whether system timing requirements can be met until after the design has been fit into the device. this is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of x and y routing channels used, etc. in the xpla ? architecture, the user knows up front whether the design will meet system timing requirements. this is due to the simplicity of the timing model. for example, in the pz3032 device, the user knows up front that if a given output uses 5 product terms or less, the t pd = 8ns, the t su = 6.5ns, and the t co = 7.5ns. if an output is using 6 to 37 product terms, an additional 2.5ns must be added to the t pd and t su timing parameters to account for the time to propagate through the pla array. totalcmos ? design technique for fast zero power philips is the first to offer a totalcmos ? cpld, both in process technology and design technique. philips employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate implementation allows philips to offer cplds which are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. refer to figure 5 and table 2 showing the i dd vs. frequency of our pz3032 totalcmos ? cpld. output pin input pin sp00441 t pd_pal = combinatorial pal only t pd_pla = combinatorial pal + pla clock output pin input pin dq registered t su_pal = pal only t su_pla = pal + pla registered t co figure 4. coolrunner ? timing model
typical i dd (ma) frequency (mhz) sp00443 figure 5. i dd vs. frequency @ v dd = 3.3v table 2. i dd vs frequency v dd = 3.3v freq (mhz) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 typical i dd (ma) 0.01 2.37 4.65 6.80 9.06 11.1 13.5 15.5 17.4 20.0 22.1 24.4 26.6 28.5
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 7 absolute maximum ratings 1 symbol parameter min. max. unit v dd supply voltage 0.5 7.0 v v i input voltage 1.2 v dd +0.5 v v out output voltage 0.5 v dd +0.5 v i in input current 30 30 ma i out output current 100 100 ma t j maximum junction temperature 40 150 c t str storage temperature 65 150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. operating range product grade temperature voltage commercial 0 to +70 c 3.3 10% v industrial 40 to +85 c 3.3 10% v
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 8 dc electrical characteristics for commercial grade devices commercial: 0 c t amb +70 c; 3.0v v dd 3.6v symbol parameter test conditions min. max. unit v il input voltage low v dd = 3.0v 0.8 v v ih input voltage high v dd = 3.6v 2.0 v v i input clamp voltage v dd = 3.0v, i in = 18ma 1.2 v v ol output voltage low v dd = 3.0v, i ol = 8ma 0.5 v v oh output voltage high v dd = 3.0v, i oh = 8ma 2.4 v i il input leakage current low v dd = 3.6v (except cko), v in = 0v 10 10 m a i ih input leakage current high v dd = 3.6v, v in = 3.0v 10 10 m a i il clock input leakage current v dd = 3.6v, v in = 0.4v 10 10 m a i ozl 3-stated output leakage current low v dd = 3.6v, v in = 0.4v 10 10 m a i ozh 3-stated output leakage current high v dd = 3.6v, v in = 3.0v 10 10 m a i ddq standby current v dd = 3.6v, t amb = 0 c 35 m a i ddd 1 dynamic current v dd = 3.6v, t amb = 0 c @ 1mhz 0.5 ma i ddd 1 dynamic current v dd = 3.6v, t amb = 0 c @ 50mhz 18 ma i os short circuit output current 1 pin at a time for no longer than 1 second 5 100 ma c in input pin capacitance t amb = 25 c, f = 1mhz 8 pf c clk clock input capacitance t amb = 25 c, f = 1mhz 5 12 pf c i/o i/o pin capacitance t amb = 25 c, f = 1mhz 10 pf note: 1. this parameter measured with a 16bit, loadable up/down counter loaded into every logic block, with all outputs enabled and u nloaded. inputs are tied to v dd or ground. this parameter guaranteed by design and characterization, not testing. ac electrical characteristics 1 for commercial grade devices commercial: 0 c t amb +70 c; 3.0v v dd 3.6v symbol parameter 8 10 12 unit symbol parameter min. max. min. max. min. max. unit t pd_pal propagation delay time, input (or feedback node) to output through pal 2 8 2 10 2 12 ns t pd_pla propagation delay time, input (or feedback node) to output through pal & pla 3 10.5 3 13 3 15 ns t co clock to out delay time 2 7 2 9 2 11 ns t su_pal setup time (from input or feedback node) through pal 6.5 8.5 10.5 ns t su_pla setup time (from input or feedback node) through pal + pla 9 11.5 13.5 ns t h hold time 0 0 0 ns t ch clock high time 3 4 5 ns t cl clock low time 3 4 5 ns t r input rise time 20 20 20 ns t f input fall time 20 20 20 ns f max1 maximum ff toggle rate 2 (1/t ch + t cl ) 167 125 100 mhz f max2 maximum internal frequency 2 (1/t supal + t cf ) 83 63 50 mhz f max3 maximum external frequency 2 (1/t supal + t co ) 74 57 47 mhz t buf output buffer delay time 1.5 1.5 1.5 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 6.5 8.5 10.5 ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal + pla 9 11.5 13.5 ns t cf clock to internal feedback node delay time 5.5 7.5 9.5 ns t init delay from valid v dd to valid reset 50 50 50 m s t er input to output disable 3 15 17 19 ns t ea input to output valid 15 17 19 ns t rp input to register preset 16 18 20 ns t rr input to register reset 19 21 23 ns notes: 1. specifications measured with one output switching. see figure 6 and table 3 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5pf.
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 9 dc electrical characteristics for industrial grade devices industrial: 40 c t amb +85 c; 3.0v v dd 3.6v symbol parameter test conditions min. max. unit v il input voltage low v dd = 3.0v 0.8 v v ih input voltage high v dd = 3.6v 2.0 v v i input clamp voltage v dd = 3.0v, i in = 18ma 1.2 v v ol output voltage low v dd = 3.0v, i ol = 8ma 0.5 v v oh output voltage high v dd = 3.0v, i oh = 8ma 2.4 v i il input leakage current low v dd = 3.6v (except cko), v in = 0.4v 10 10 m a i ih input leakage current high v dd = 3.6v, v in = 3.0v 10 10 m a i il clock input leakage current v dd = 3.6v, v in = 0.4v 10 10 m a i ozl 3-stated output leakage current low v dd = 3.6v, v in = 0.4v 10 10 m a i ozh 3-stated output leakage current high v dd = 3.6v, v in = 3.0v 10 10 m a i ddq standby current v dd = 3.6v, t amb = 40 c 45 m a i ddd 1 dynamic current v dd = 3.6v, t amb = 40 c @ 1mhz 0.5 ma i ddd 1 dynamic current v dd = 3.6v, t amb = 40 c @ 50mhz 18 ma i os short circuit output current 1 pin at a time for no longer than 1 second 5 120 ma c in input pin capacitance t amb = 25 c, f = 1mhz 8 pf c clk clock input capacitance t amb = 25 c, f = 1mhz 5 12 pf c i/o i/o pin capacitance t amb = 25 c, f = 1mhz 10 pf note: 1. this parameter measured with a 16bit, loadable up/down counter loaded into every logic block, with all outputs enabled and u nloaded. inputs are tied to v dd or ground. this parameter guaranteed by design and characterization, not testing. ac electrical characteristics 1 for industrial grade devices industrial: 40 c t amb +85 c; 3.0v v dd 3.6v symbol parameter i10 i12 unit symbol parameter min. max. min. max. unit t pd_pal propagation delay time, input (or feedback node) to output through pal 2 10 2 12 ns t pd_pla propagation delay time, input (or feedback node) to output through pal & pla 3 12.5 3 15 ns t co clock to out delay time 2 9 2 11 ns t su_pal setup time (from input or feedback node) through pal 8 10.5 ns t su_pla setup time (from input or feedback node) through pal + pla 10.5 13.5 ns t h hold time 0 0 ns t ch clock high time 4 5 ns t cl clock low time 4 5 ns t r input rise time 20 20 ns t f input fall time 20 20 ns f max1 maximum ff toggle rate 2 (1/t ch + t cl ) 125 100 mhz f max2 maximum internal frequency 2 (1/t supal + t cf ) 64.5 50 mhz f max3 maximum external frequency 2 (1/t supal + t co ) 58.8 47 mhz t buf output buffer delay time 1.5 1.5 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 8 10.5 ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal + pla 10.5 13.5 ns t cf clock to internal feedback delay time 7.5 9.5 ns t init delay from valid v dd to valid reset 50 50 m s t er input to output disable 3 16 19 ns t ea input to output valid 16 19 ns t rp input to register preset 17 20 ns t rr input to register reset 20 23 ns notes: 1. specifications measured with one output switching. see figure 6 and table 3 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5pf.
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 10 switching characteristics the test load circuit and load values for the ac electrical characteristics are illustrated below. v dd v in v out c1 r1 r2 s1 s2 component values r1 390 w r2 390 w c1 35pf measurement s1 s2 t pzh open closed t pzl closed closed t p closed closed note: for t phz and t plz c = 5pf, and 3-state levels are measured 0.5v from steady-state active level. sp00477 v cc = 3.3v, 25 c ns 9.50 8.50 7.50 6.50 5.50 4.50 12 4 8 12 16 typical sp00449a figure 6. t pd_pal vs. outputs switching table 3. t pd_pal vs. # of outputs switching v dd = 3.30v # of outputs 1 2 4 8 12 16 typical (ns) 6.2 6.4 6.6 6.9 7.2 7.5 voltage waveform 90% 10% 1.5ns 1.5ns +3.0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00368
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 11 pin descriptions pz3032 44-pin plastic leaded chip carrier 1 6 7 17 18 28 29 39 40 pin function 1 in1 2 in3 3v dd 4 i/oa0ck1 5 i/oa1 6 i/oa2 7 i/oa3 8 i/oa4 9 i/oa5 10 gnd 11 i/oa6 12 i/oa7 13 i/oa8 14 i/oa9 15 v dd pin function 16 i/oa10 17 i/oa11 18 i/oa12 19 i/oa13 20 i/oa14 21 i/oa15 22 gnd 23 v dd 24 i/ob15 25 i/ob14 26 i/ob13 27 i/ob12 28 i/ob11 29 i/ob10 30 gnd pin function 31 i/ob9 32 i/ob8 33 i/ob7 34 i/ob6 35 v dd 36 i/ob5 37 i/ob4 38 i/ob3 39 i/ob2 40 i/ob1 41 i/ob0 42 gnd 43 in0ck0 44 in2gtsn plcc sp00420 pz3032 44-pin thin quad flat package 44 1 11 12 22 23 33 34 pin function 1 i/oa3 2 i/oa4 3 i/oa5 4 gnd 5 i/oa6 6 i/oa7 7 i/oa8 8 i/oa9 9v dd 10 i/oa10 11 i/oa11 12 i/oa12 13 i/oa13 14 i/oa14 15 i/oa15 pin function 16 gnd 17 v dd 18 i/ob15 19 i/ob14 20 i/ob13 21 i/ob12 22 i/ob11 23 i/ob10 24 gnd 25 i/ob9 26 i/ob8 27 i/ob7 28 i/ob6 29 v dd 30 i/ob5 pin function 31 i/ob4 32 i/ob3 33 i/ob2 34 i/ob1 35 i/ob0 36 gnd 37 in0/ck0 38 in2gtsn 39 in1 40 in3 41 v dd 42 i/oa0ck1 43 i/oa1 44 i/oa2 tqfp sp00433 package thermal characteristics philips semiconductors uses the temperature sensitive parameter (tsp) method to test thermal resistance. this method meets mil-std-883c method 1012.1 and is described in philips 1995 ic package databook . thermal resistance varies slightly as a function of input power. as input power increases, thermal resistance changes approximately 5% for a 100% change in power. figure 7 is a derating curve for the change in q ja with airflow based on wind tunnel measurements. it should be noted that the wind flow dynamics are more complex and turbulent in actual applications than in a wind tunnel. also, the test boards used in the wind tunnel contribute significantly to forced convection heat transfer, and may not be similar to the actual circuit board, especially in size. package q ja 44-pin plcc 49.8 c/w 44-pin tqfp 66.3 c/w 0 10 20 30 40 50 01234 5 percentage reduction in q ja (%) air flow (m/s) plcc/ qfp sp00419a figure 7. average effect of airflow on q ja
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 12 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 13 tqfp44: plastic thin quad flat package; 44 leads; body 10 x 10 x 1.0 mm sot376-1
philips semiconductors product specification pz3032 32 macrocell cpld 1997 feb 20 14 philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. ? copyright philips electronics north america corporation 1997 all rights reserved. printed in u.s.a.

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