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ne56632-xx active-low system reset with adjustable delay time product data supersedes data of 2002 mar 25 2003 oct 14 integrated circuits
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2 2003 oct 14 description the ne56632-xx is a family of active-low, power-on reset that offers precision threshold voltage detection within 1.5% and super low operating supply current of typically 3.0 m a. it includes a reset delay that is user adjustable with an external capacitor. several detection threshold voltages are available at 1.9v , 2.0 v, 2.7 v, 2.8 v, 2.9 v, 3.0 v, 3.1 v, 4.2 v, 4.3 v, 4.4 v, 4.5 v, and 4.6 v. other thresholds are offered upon request at 100 mv steps from 1.9 v to 4.6 v. with its ultra low supply current and high precision voltage threshold detection capability, the ne56632-xx is well suited for various battery powered applications such as reset circuits for logic and microprocessors, voltage check, and level detecting. it is available in the 5-lead small outline package (sop003). features ? high precision threshold detection voltage: v s 1.5% ? super low operating supply current: 3 m a typ. ? built-in hysteresis voltage: 50 mv typ. ? detection threshold voltage: 1.9 v, 2.0 v, 2.7 v, 2.8 v, 2.9 v, 3.0 v, 3.1 v, 4.2 v, 4.3 v, 4.4 v, 4.5 v, and 4.6 v. ? reset output: active-low, open collector ? other detection threshold voltages available upon request at 100 mv steps from 1.9 v to 4.6 v. ? large low reset output current: 30 ma typ. ? power-on reset delay time adjustable with external capacitor: 200 m s to 200 ms ? reset assertion with v cc down to 0.65 v applications ? reset for microprocessor and logic circuits ? voltage level detection circuit ? battery voltage check circuit ? detection circuit for battery back-up simplified system diagram 123 4 5 ne56632-xx r pu to reset terminal of cpu sl01605 c d to v cc figure 1. simplified system diagram.
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 3 ordering information type number package temperature type number description version range ne56632- xx d plastic small outline package; 5 leads (see dimensional drawing) sop003 20 to +75 c note: the device has 12 voltage output options, indicated by the xx on the `type number'. xx voltage (typical) 19 1.9 v 20 2.0 v 27 2.7 v 28 2.8 v 29 2.9 v 30 3.0 v 31 3.1 v 42 4.2 v 43 4.3 v 44 4.4 v 45 4.5 v 46 4.6 v part number marking the package is marked with a four letter code. the first three letters designate the product. the fourth letter, represented by `x', is a date tracking code. part number marking ne56632-19d akzx ne56632-20d alax ne56632-27d albx ne56632-28d alcx ne56632-29d aldx ne56632-30d alex ne56632-31d alfx ne56632-42d algx ne56632-43d alhx ne56632-44d aljx ne56632-45d alkx ne56632-46d allx pin configuration sl01604 1 2 34 5v cc v out gnd sub tc ne56632-xx figure 2. pin configuration. pin description pin symbol description 1 tc delay time control; set with external capacitor. 2 sub substrate. connect to ground (gnd). 3 gnd ground. negative supply. 4 v out reset output voltage. active-low. 5 v cc positive supply voltage; detection threshold voltage input. maximum ratings symbol parameter min. max. unit v cc supply voltage 0.3 +10 v t amb ambient operating temperature 20 +75 c t stg storage temperature 40 +125 c p power dissipation 150 mw
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 4 electrical characteristics t amb = 25 c, unless otherwise specified. symbol parameter conditions -xx min. typ. max. unit v s detection threshold v cc = high-to-low; r l = 4.7 k w ; s1=on; v 04v 46 4.531 4.600 4.669 v v ol 0 . 4 v ; test circuit 1 ( fi g ure 27 ) 45 4.432 4.500 4.568 v test circuit 1 (figure 27) 44 4.334 4.400 4.466 v 43 4.235 4.300 4.365 v 42 4.137 4.200 4.263 v 31 3.053 3.100 3.147 v 30 2.955 3.000 3.045 v 29 2.856 2.900 2.944 v 28 2.758 2.800 2.842 v 27 2.659 2.700 2.741 v 20 1.970 2.000 2.030 v 19 1.871 1.900 1.929 v v hys hysteresis voltage r l = 4.7 k w ; v cc = low-to-high-to-low; s1 = on; test circuit 1 (figure 27) 25 50 100 mv v s / d t detection threshold voltage temperature coefficient r l = 4.7 k w ; t amb = 20 c to +75 c; s1 = on; test circuit 1 (figure 27) 0.01 %/ c v ol low-level output voltage v cc1 = v s(min) 0.05 v; r l = 4.7 k w ; s1 = on; test circuit 1 (figure 27) 0.2 0.4 v i lo output leakage current v cc1 = v cc2 = 10 v; s2 = on; test circuit 1 (figure 27) 0.1 m a i ccl supply current (on time) v cc1 = v s(min) 0.05 v; r l = ; test circuit 1 (figure 27) 5.0 9.0 m a i cch supply current (off time) v cc1 = v s(typ) /0.85; r l = ; test circuit 1 (figure 27) 3.0 5.0 m a t plh low-to-high delay time c l = 100 pf; r l = 4.7 k w ; c d = 10 nf (note 1) (note 3) ms t phl high-to-low delay time c l = 100 pf; r l = 4.7 k w ; c d = 10 nf (note 2) (note 3) m s v opl minimum operating threshold voltage r l = 4.7 k w ; v ol 0.4 v; s1 = on; test circuit 1 (figure 27) 0.65 0.80 v i ol1 output current (on time 1) v o = 0.4 v; r l = 0; v cc1 = v s(min) 0.05 v; v cc2 = 0.4 v; s2 = on; test circuit 1 (figure 27) 5 ma i ol2 output current (on time 2) v o = 0.4 v; r l = 0; v cc1 = v s(min) 0.05 v; t amb = 20 c to +75 c; s2 = on; test circuit 1 (figure 27) 3 ma notes: 1. t plh :v cc = (v s(typ) 0.4 v) to (v s(typ) + 0.4 v); t plh is release delay time (test circuit 2, figure 28). 2. t phl :v cc = (v s(typ) + 0.4 v) to (v s(typ) 0.4 v); t phl is assertion delay time (test circuit 2, figure 28). 3. see table 1. table 1. ne56632-xx series typical delay time xx t plh t phl 46 195 ms 140 m s 45 190 ms 140 m s 44 185 ms 140 m s 43 180 ms 140 m s 42 175 ms 140 m s 31 120 ms 120 m s 30 115 ms 120 m s 29 110 ms 120 m s 28 105 ms 100 m s 27 100 ms 100 m s 20 65 ms 100 m s 19 60 ms 100 m s
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 5 typical performance curves, ne56632-20 sl01620 ambient temperature, t amb ( c) 1.9850 1.9875 1.9900 1.9925 1.9950 1.9975 2.0000 2.0025 2.0050 40 20 0 20 40 60 80 100 v s , detection threshold (v) test circuit 1 v cc = high-to-low r l = 4.7 k w v ol 0.4 v s1 = on figure 3. detection threshold versus temperature. sl01621 ambient temperature, t amb ( c) v hys , hysteresis voltage (mv) 30 40 50 60 70 80 90 100 40 20 0 20 40 60 80 100 test circuit 1 v cc = low-to-high-to-low r l = 4.7 k w s1 = on figure 4. hysteresis voltage versus temperature. sl01622 ambient temperature, t amb ( c) v ol , low-level output voltage (v) 40 20 0 20 40 60 80 100 0.185 0.190 0.195 0.200 0.205 0.210 0.215 0.220 0.225 test circuit 1 v cc1 = v s(min) 0.05 v r l = 4.7 k w s1 = on figure 5. low-level output voltage versus temperature. sl01623 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 i ccl , supply current (on time), ( a) m 3 4 5 6 7 8 9 test circuit 1 v cc1 = v s(min) 0.05 v r l = figure 6. supply current (on time) versus temperature. sl01624 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 i cch , supply current (off time), ( a) m 2.0 2.5 3.0 3.5 4.0 4.5 test circuit 1 r l = v cc1 = v s(typ) /0.85 figure 7. supply current (off time) versus temperature. sl01625 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 v opl , min. operating threshold voltage (v) 0.3 0.4 0.5 0.6 0.7 0.8 0.9 test circuit 1 r l = 4.7 k w v ol 0.4 v s1 = on figure 8. min. operating threshold voltage versus temperature.
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 6 typical performance curves, ne56632-20 (continued) sl01626 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 i ol1 , output current (on time 1), (ma) 25 27 29 31 33 35 37 test circuit 1 v cc1 = v s(min) 0.05 v v cc2 = 0.4 v v o = 0.4 v r l = 0 w s2 = on figure 9. output current (on time 1) versus temperature. sl01627 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 t plh , low-to-high delay time (ms) 40 50 60 70 80 90 100 test circuit 2 c l = 100 pf r l = 4.7 k w c d = 10 nf v cc = (v s(typ) 0.4 v) to (v s(typ) + 0.4 v) t plh = release delay time figure 10. low-to-high delay time versus temperature. sl01628 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 t phl , high-to-low delay time ( s) m 80 85 90 95 100 105 110 115 120 test circuit 2 c l = 100 pf r l = 4.7 k w c d = 10 nf v cc = (v s(typ) + 0.4 v) to (v s(typ) 0.4 v) t phl = assertion delay time figure 11. high-to-low delay time versus temperature.
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 7 typical performance curves, ne56632-31 sl01629 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 v s , detection threshold (v) 3.08 3.09 3.10 3.11 test circuit 1 v cc = high-to-low r l = 4.7 k w v ol 0.4 v s1 = on figure 12. detection threshold versus temperature. sl01630 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 v hys , hysteresis voltage (mv) 30 40 50 60 70 80 90 test circuit 1 v cc = low-to-high r l = 4.7 k w s1 = on figure 13. hysteresis voltage versus temperature. sl01631 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 0.17 0.18 0.19 0.20 0.21 0.22 0.23 v ol , low-level output voltage (v) test circuit 1 v cc1 = v s(min) 0.05 v r l = 4.7 k w s1 = on figure 14. lowlevel output voltage versus temperature. sl01632 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 2 3 4 5 6 7 8 9 i ccl , supply current (on time), ( a) m test circuit 1 v cc1 = v s(min) 0.05 v r l = figure 15. supply current (on time) versus temperature. sl01633 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 2.0 2.5 3.0 3.5 4.0 4.5 i cch , supply current (off time), ( a) m test circuit 1 r l = v cc1 = v s(typ) /0.85 figure 16. supply current (off time) versus temperature. sl01634 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 0.3 0.4 0.5 0.6 0.7 0.8 0.9 v opl , min. operating threshold voltage (v) test circuit 1 r l = 4.7 k w v ol 0.4 v s1 = on figure 17. min. operating threshold voltage versus temperature.
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 8 typical performance curves, ne56632-31 (continued) sl01635 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 i ol1 , output current (on time 1), (ma) test circuit 1 v cc1 = v s(min) 0.05 v v cc2 = 0.4 v v o = 0.4 v r l = 0 w s2 = on figure 18. output current (on time 1) versus temperature. sl01636 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 i ol2 , output current (on time 2), (ma) 27 29 31 33 35 37 test circuit 1 v cc1 = v s(min) 0.05 v v cc2 = 0.4 v v o = 0.4 v r l = 0 w s2 = on figure 19. output current (on time 2) versus temperature. sl01637 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 t plh , low-to-high delay time (ms) 40 60 80 100 120 140 160 180 test circuit 2 c l = 100 pf r l = 4.7 k w c d = 10 nf v cc = (v s(typ) 0.4 v) to (v s(typ) + 0.4 v) t plh = release delay time figure 20. low-to-high delay time versus temperature. sl01638 ambient temperature, t amb ( c) 40 20 0 20 40 60 80 100 80 90 100 110 120 130 140 150 160 test circuit 2 c l = 100 pf r l = 4.7 k w c d = 10 nf t phl , high-to-low delay time ( s) m v cc = (v s(typ) + 0.4 v) to (v s(typ) 0.4 v) t phl = assertion delay time figure 21. high-to-low delay time versus temperature.
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 9 technical discussion the ne56632-xx is a bipolar ic designed to provide power source monitoring and a system reset function in the event the power sags below an acceptable level for the system to operate reliably. the reset threshold incorporates a typical hysteresis of 50 mv to prevent erratic reasserts from being generated. an internal delay time circuit provides a adjustable power-on reset delay of typically 200 m s to 200 ms using an external capacitor. the output of the ne56632-xx utilizes an open collector topology, which requires an external pull-up resistor to v cc . though this may be regarded as a disadvantage, it is advantageous in many sensitive applications. because the open collector output cannot source reset current when both are operated from a common supply, the ne56632-xx offers a safe interconnect to a wide variety of microprocessors. the ne56632-xx operates at low supply currents, typically 3 m a, while offering precision threshold detection ( 1.5%). figure 22 is a functional block diagram of the ne56632-xx. the internal reference source voltage, v ref , is typically 0.65 v over the temperature range. the reference voltage is connected to the non-inverting inputs of the threshold comparator 1 and comparator 2, while the inverting input of comparator 1 monitors the supply voltage through a voltage divider (r1 and r2). the output of the comparator drives the series base resistor, r3 of a common emitter amplifier, q1. the collector of q1 is connected to the inverting terminal of comparator 2. the output of comparator 2 is connected to the series base resistor, r4 of the output common emitter transistor, q2. the open collector output of q2 provides the reset output. the delay time control is outputted at the junction of the collector of q1 and the inverting input of comparator 2. the reset release time delay, t plh is set with an external capacitor. figures 25 and 26 show t plh as a function of the external delay capacitor, c d . when the supply voltage sags to the threshold detection voltage, the resistor divider network supplies a voltage to the inverting terminal of the threshold comparator which is less than v ref , causing the output of the comparator to go to a high state. this causes the common emitter amplifier, q1 to turn on pulling down the non-inverting terminal of comparator 2 which causes its output to go to a high state. this high output level turns on the output common emitter transistor, q2. the collector output of q2 is pulled low through the external pull-up resistor, thereby asserting the active-low reset. threshold hysteresis is established by turning on the bipolar common emitter transistor, q1 when the input threshold comparator 1 goes to a high state. this occurs when v cc sags to or below the threshold level. with the output of q1 connected to the non-inverting terminal of comparator 2, the non-inverting terminal has a level near ground at about 0.4 v when the reset is asserted (active-low). for the comparator 2 to reverse its output, the comparator 1 output and q1 must overcome the additional pull-down voltage present on the inverting input of comparator 2. the differential voltage required to do this establishes the hysteresis voltage of the sensed threshold voltage. typically, it is 50 mv. when v cc sags, and it is below the detection threshold (v sl ), the device will assert a reset low output at or near ground potential. as v cc rises from (v cc < v sl ) to v sh or higher, the reset is released and the output follows v cc . conversely, decreases in v cc from (v cc > v sl ) to v sl will cause the output to be pulled to ground. hysteresis voltage = release voltage detection threshold voltage v hys = v sh v sl where: v sh = v sl + v hys v sl = v sh v hys when v cc drops below the minimum operating voltage, typically 0.65 v, the output is undefined and the output reset low assertion is no longer guaranteed. at this level of v cc the output will try to rise to v cc . as v cc drops even further to zero, v out reset also goes to zero. 3 4 r3 q1 q2 r4 2 v out gnd sub comp2 comp1 (substrate) i d r2 r1 1 tc 5 v ref v cc sl01607 figure 22. functional diagram.
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 10 timing diagram the timing diagram in figure 23 depicts the operation of the device. letters an on the time axis indicates specific events. a: at aao, v cc begins to increase. also the v out voltage initially increases but abruptly decreases when v cc reaches the level (approximately 0.65 v) that activates the internal bias circuitry and reset is asserted. b: at abo, v cc reaches the threshold level of v sh . at this point the delay time, t plh is initiated while v cc rises above v sh to its normal operating level. the v out voltage remains in a low voltage state. c: at aco, v cc is above v sl and the delay time elapses. at this instant, the ic releases the hold on the v out reset. the reset output then goes high (assuming the reset pull-up resistor r pu is connected to v cc ). in a microprocessor based system these events release the reset from the microprocessor, allowing the microprocessor to function normally. d-e: at ado, v cc begins to fall, causing v out to follow. v cc continues to fall until the v sl undervoltage detection threshold is reached at aeo. this causes a reset signal to be generated (v out goes low). e-f: between aeo and afo, v cc continues to fall and then starts rising. f: at afo, v cc rises to the v sh level. once again, the device initiates the delay timer. f-g: v cc rises above v sh and returns to normal. at ago, the delay (t plh ) times out and once again, then it releases the hold on the v out reset. g-h: at ago, v cc is above the upper threshold and begins to fall, causing v out to follow it. as long as v cc remains above the v sh , no reset signal will be generated. h: at event aho, v cc falls until the v sl undervoltage detection threshold is reached. at this level, a reset signal is generated and v out goes low. h-i: between aho and aio, v cc continues to fall and then starts to rise rising. v cc rises to the v sh level at aio, where the delay time is again initiated. i-j: between aio and ajo, v cc rises above v sh to v cc normal and then falls back to v sl level at ajo. at ajo, the reset signal is reasserted before the delay time has elapsed. the time between aio and ajo is less than t plh (reset delay time). thus, the reset is not released and the reset output remains low. kl: between ako and alo, v cc rises again back to normal operating level causing the reset delay to be initiated at ako and the reset to be released at alo. m: at amo, v cc falls to v sl where the reset is asserted (v out reset goes low). n: at ano, the v cc voltage has decreased until normal internal circuit bias is unable to maintain a v out reset. as a result, v cc may rise to less than 0.65 v. as v cc decreases further, the v out reset also decreases to zero. v hys t plh abcdef ghi (reset ) v out v t plh t plh v jk l m n < t plh v sh v sl v cc sl01606 figure 23. timing diagram.
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 11 application information a typical application circuit for the ne56632-xx is shown in figure 24. note that a pull-up resistor, r pu is necessary since the output is an open collector. the value of rpu is calculated by the following expression. r pu (v cc v reset ) / i ol where: v cc = v s(min) 0.05 v (for a 3 v reset this is 2.905 v) v reset = 0.4 v (this is v ol(max) ) i ol = 5 ma; minimum output current at t amb = 25 c substituting these values into the expression and calculating, finds r pu should be greater than or equal to 510 w. to ensure that the active-low level is sufficient, a value of 4.7 k w is chosen in the test and application examples. 123 4 5 ne56632-xx r pu to reset terminal of cpu sl01605 c d to v cc figure 24. typical application. figure 25 (ne56632-20 c d versus t plh ) and figure 26 (ne56632-44 c d versus t plh ) show how t phl , the aho transmission delay or reset release delay time varies as a function of the external delay capacitance, c d . from figure 26, typical range of the delay capacitance is 1 pf to 10 nf which yields typical delays from 200 m s to 200 ms. the following formula can be used to find the approximate delay time based on external delay capacitance, c d and the delay time coefficient, d shown in table 2. t plh (ms) c d ( m f) d for example, a ne56632-44 using an external capacitor, c d = 1 nf = 1000 pf yields: t plh (ms) (1 10 3 ) (1.85 10 4 ) 18.5 ms compare this to the value of t plh 17 ms for c d = 1000 pf that is extracted from figure 26. sl01611 c d (pf) t plh (s) 1.0e+01 1.0e+02 1.0e+03 1.0e+00 1.0e+00 1.0e+04 1.0e01 1.0e02 1.0e03 1.0e04 1.0e05 figure 25. ne56632-20 c d versus t plh characteristics. sl01612 c d (pf) t plh (s) 1.0e+01 1.0e+02 1.0e+03 1.0e+00 1.0e+00 1.0e+04 1.0e01 1.0e02 1.0e03 1.0e04 1.0e05 figure 26. ne56632-44 c d versus t plh characteristics. table 2. delay time coefficient device d ne5663246 1.95 10 4 ne5663245 1.90 10 4 ne5663244 1.85 10 4 ne5663243 1.80 10 4 ne5663242 1.75 10 4 ne5663231 1.20 10 4 ne5663230 1.15 10 4 ne5663229 1.10 10 4 ne5663228 1.05 10 4 ne5663227 1.00 10 4 ne5663220 0.65 10 4 ne5663219 0.60 10 4
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 12 test circuits 123 4 5 ne56632-xx sl01608 c d v2 a2 s2 s1 r l s3 v cc2 a1 v1 v cc1 10 m f /10 v figure 27. test circuit 1. input pulse 123 4 5 ne56632-xx sl01609 crt 5.0 v c d c l 100 pf r l 10 m f /10 v figure 28. test circuit 2. sl01610 v s(typ) + 0.4 v v s(typ) 0.4 v 0v figure 29. input pulse. notes: a = dc amperemeter v = dc voltmeter crt = oscilloscope
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 13 packing method the ne56632-xx is packed in reels, as shown in figure 30. sl01305 tape detail cover tape carrier tape reel assembly tape guard band barcode label box figure 30. tape and reel packing method.
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 14 plastic small outline package; 5 leads; body width 1.6 mm sop003
philips semiconductors product data ne56632-xx active-low system reset with adjustable delay time 2003 oct 14 15 revision history rev date description _2 20031014 product data (9397 750 12143). ecn 853-2329 30316 of 08 september 2003. supersedes data of 2002 mar 25 (9397 750 10239). modifications: ? change package outline version to sop003 in ordering information table and package outline sections. _1 20020325 product data (9397 750 10239). ecn 853-2329 27919 of 25 march 2002. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. date of release: 10-03 document order number: 9397 750 12143

data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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