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products and specifications discussed herein are subject to change by micron without notice. pdf: 09005aef807924d2, source: 09005aef807924f1 sdf16c32_64x64hg.fm - rev. e 4/06 en 1 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb (x64, dr) 144-pin sdram sodimm small-outline sdram module mt16lsdf3264(l)h ? 256mb mt16lsdf6464(l)h ? 512mb for the latest data sheet, please refer to the micron ? web site: www.micron.com/products/modules features ? pc100- and pc133-compliant, 144-pin, small- outline, dual in-line memory module (sodimm) ? utilizes 100 mhz and 133 mhz sdram components ? unbuffered ? 256mb (32 meg x 64) and 512mb (64 meg x 64) ? single +3.3v power supply ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operat ion; column address can be changed every clock cycle ? internal sdram banks for hiding row access/ precharge ? programmable burst lengths: 1, 2, 4, 8, or full page ? auto precharge and auto refresh modes ? self refresh mode: standard and low-power ? 256mb module: 64ms, 4,096-cycle refresh (15.625s refresh interval); 512mb: 64ms, 8,192-cycle refresh (7.81s refresh interval) ? lvttl-compatible inputs and outputs ? serial presence-detect (spd) ? gold edge connectors figure 1: 144-pin sodimm (mo-190) note: 1. contact micron for product availability. table 1: timing parameters cl = cas (read) latency module marking clock frequency access time setup time hold time cl = 2 cl = 3 -13e 133 mhz 5.4ns ? 1.5ns 0.8ns -133 133 mhz ? 5.4ns 1.5ns 0.8ns -10e 100 mhz 6ns ? 2ns 1ns options marking ? self refresh current standard none low power l 1 ?package 144-pin sodimm (standard) g 144-pin sodimm (lead-free) y 1 ? memory clock/cl 7.5ns (133 mhz)/cl = 2 -13e 7.5ns (133 mhz)/cl = 3 -133 10ns (100 mhz)/cl = 2 -10e ?pcb height 1.25in (31.75mm) see page 2 note pcb height: 1.25in (31.75mm) table 2: address table 256mb 512mb refresh count 4k 8k device banks 4 (ba0, ba1) 4 (ba0, ba1) device configuration 128mb (16 meg x 8) 256mb (32 meg x 8) row addressing 4k (a0?a11) 8k (a0?a12) column addressing 1k (a0?a9) 1k (a0?a9) module ranks 2 (s0#, s1#) 2 (s0#, s1#))
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 2 ?2006 micron technology, inc. all rights reserved. note: 1. the designators for component and pcb revision are the last two characters of each part number consult factory for current revision codes. exam ple: mt16lsdf32264(l)hg-133b1. table 3: part numbers part number module density configuration system bus speed mt16lsdf3264(l)hg-13e_ 256mb 32 meg x 64 133 mhz mt16lsdf3264(l)hy-13e_ 256mb 32 meg x 64 133 mhz mt16lsdf3264(l)hg-133_ 256mb 32 meg x 64 133 mhz mt16lsdf3264(l)hy-133_ 256mb 32 meg x 64 133 mhz mt16lsdf3264(l)hg-10e_ 256mb 32 meg x 64 100 mhz mt16lsdf3264(l)hy-10e_ 256mb 32 meg x 64 100 mhz mt16lsdf6464(l)hg-13e_ 512mb 64 meg x 64 133 mhz mt16lsdf6464(l)hy-13e_ 512mb 64 meg x 64 133 mhz mt16lsdf6464(l)hg-133_ 512mb 64 meg x 64 133 mhz mt16lsdf6464(l)hy-133_ 512mb 64 meg x 64 133 mhz mt16lsdf6464(l)hg-10e_ 512mb 64 meg x 64 100 mhz mt16lsdf6464(l)hy-10e_ 512mb 64 meg x 64 100 mhz
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 3 ?2006 micron technology, inc. all rights reserved. note: 1. pin 70 is no connect for 256mb mo dules, or a12 fo r 512mb modules. figure 2: pin loca tions (144-pin sodimm) table 4: pin assignment (144-pin sodimm front) pin symbol pin symbol pin symbol pin symbol 1v ss 37 dq8 73 nc 109 a9 3dq039dq9 75 vss 111 a10 5 dq1 41 dq10 77 nc 113 v dd 7dq2 43 dq11 79 nc 115 dqmb2 9dq3 45 v dd 81 v dd 117 dqmb3 11 v dd 47 dq12 83 dq16 119 v ss 13 dq4 49 dq13 85 dq17 121 dq24 15 dq5 51 dq14 87 dq18 123 dq25 17 dq6 53 dq15 89 dq19 125 dq26 19 dq7 55 v ss 91 v ss 127 dq27 21 v ss 57 nc 93 dq20 129 v dd 23 dqmb0 59 nc 95 dq21 131 dq28 25 dqmb1 61 ck0 97 dq22 133 dq29 27 v dd 63 v dd 99 dq23 135 dq30 29 a0 65 ras# 101 v dd 137 dq31 31 a1 67 we# 103 a6 139 v ss 33 a2 69 s0# 105 a8 141 sda 35 v ss 71 s1# 107 v ss 143 v dd table 5: pin assignment (144-pin sodimm back) pin symbol pin symbol pin symbol pin symbol 2vss 38 dq40 74 ck1 110 ba1 4 dq32 40 dq41 76 v ss 112 a11 6 dq33 42 dq42 78 nc 114 v dd 8 dq34 44 dq43 80 nc 116 dqmb6 10 dq35 46 v dd 82 v dd 118 dqmb7 12 v dd 48 dq44 84 dq48 120 v ss 14 dq36 50 dq45 86 dq49 122 dq56 16 dq37 52 dq46 88 dq50 124 dq57 18 dq38 54 dq47 90 dq51 126 dq58 20 dq39 56 v ss 92 v ss 128 dq59 22 v ss 58 nc 94 dq52 130 v dd 24 dqmb4 60 nc 96 dq53 132 dq60 26 dqmb5 62 cke0 98 dq54 134 dq61 28 v dd 64 v dd 100 dq55 136 dq62 30 a3 66 cas# 102 v dd 138 dq63 32 a4 68 cke1 104 a7 140 v ss 34 a5 70 nc/ a12 1 106 ba0 142 scl 36 v ss 72 nc 108 v ss 144 v dd u1 u2 u17 u10 u9 u3 u4 u5 u6 u7 u8 u16 u15 u14 u13 u12 u11 back view front view pin 1 pin 143 (all odd pins) pin 2 pin 144 (all even pins) indicates a v dd or v ddq pin indicates a v ss pin
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 4 ?2006 micron technology, inc. all rights reserved. table 6: pin descriptions pin numbers may not correlate with symb ols; refer to the pin assignment ta bles on page 3 for more information pin numbers symbol type description 65, 66, 67 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 61, 74 ck0, ck1 input clock: ck is driven by the system clock. all sdram input signals are sampled on the positive edge of ck. ck also increments the internal burst co unter and controls the output registers. 62, 68 cke0, cke1 input clock enable: cke activates (hi gh) and deactivates (low) the ck signal. deactivating the clock provides precharge power- down and self refresh operation (all device banks idle), active power-down (row active in any device bank), or clock suspend operation (burst access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where ck e becomes asynchronous until after exiting the same mode. th e input buffers, including ck, are disabled during power-down and self refresh modes, providing low standby power. 69, 71 s0#,s1# input chip select: s# enables (registered low) and disables (registered high) the command decoder. all commands are masked when s# is registered hi gh. s# is considered part of the command code. 23, 24, 25, 26, 115, 116, 117, 118 dqmb0?dqmb7 input input/output mask: dqmb is an input mask signal for write accesses and an output enable si gnal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (two- clock latency) when dqmb is sampled high during a read cycle. 106, 110 ba0, ba1 input bank address: ba0 and ba1 defi ne to which device bank the active, read, write, or precharge command is being applied. 29, 30, 31, 32, 33, 34, 70 (512mb) , 103, 104, 105, 109, 111, 112 a0?a11 (256mb) a0?a12 (512mb) input address inputs: provide the row address for active commands and the column address and au to precharge bit (a10) for read/write commands, to select one location out of the memory array in the respecti ve device bank. a10 sampled during a precharge command determines whether the precharge applies to one devi ce bank (a10 low, device bank selected by ba0, ba1) or all device banks (a10 high). the address inputs also provide the op-code during a mode register set command. 142 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfe r to and from the module. 141 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and data out of the presence- detect portion of the module. 3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 16, 17, 18,19, 20, 37, 38, 39, 40, 41, 42, 43, 44, 47, 48, 49, 50, 51, 52, 53, 54, 83, 84, 85, 86, 87, 88, 89, 90, 93, 94, 95, 96, 97, 98, 99, 100, 121, 122, 123, 124, 125, 126, 127, 128, 131, 132, 133, 134, 135, 136, 137, 138 dq0?dq63 input/ output data i/o: data bus.
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 5 ?2006 micron technology, inc. all rights reserved. 11, 12, 27, 28, 45, 46, 63, 64, 81, 82, 101, 102, 113, 114, 129, 130, 143, 144 v dd supply power supply: +3.3v 0.3v. 1, 21, 35, 55, 75, 91, 107, 119, 139, 2, 22, 36, 56, 76, 92, 108, 120, 140 v ss supply ground. 57, 58, 59, 60, 70 (256mb), 72, 73, 77, 78, 79, 80 nc ? not connected: these pins should be left unconnected. table 6: pin descriptions (continued) pin numbers may not correlate with symb ols; refer to the pin assignment ta bles on page 3 for more information pin numbers symbol type description
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 6 ?2006 micron technology, inc. all rights reserved. figure 3: functional block diagram ras# cas# cas#: sdrams we#: sdrams a0-a11: sdrams a0-a12: sdrams ba0, ba1: sdrams (256mb) a0?a11 (512mb) a0?a12 ba0, ba1 v dd v ss sdrams sdrams clk (u6, u7, u14, u15) clk (u2, u8, u10, u16) u5 cs# dqm ras#: sdrams we# serial pd sda wp scl a0 a1 a2 clk (u1, u3, u9, u11) clk (u4, u5, u12, u13) ck0 ck1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 u3 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 u11 dq dq dq dq dq dq dq dq dqm cs# u4 u13 u1 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 cke0 cke0 (u1?u8) u17 u8 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb3 u15 u2 u16 u6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u9 u12 u14 u10 dqmb1 dqm cs# cs# dqm s0# cs# dqm dqmb2 dqm cs# cs# dqm dqm cs# dqmb4 dqm cs# cs# dqm dqmb5 dqm cs# cs# dqm dqmb6 dqm cs# cs# dqm dqmb7 dqm cs# cs# dqm cke1 cke1 (u9?u16) 0 0 s1# 0 dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq 0 0 0 0 0 0 0 0 note: 1. all resistor values are 10 unless otherwise specified. 2. per industry standard, micron utilizes various component speed grades as referenced in the module part numbering guide at www.micron.com/ support/numbering.html . standard modules use the following sdram devices: mt48lc16m8a2fb (256mb); mt48lc32m8a2fb (512mb) lead-free modules use the following sdram devices: mt48lc16m8a2bb (256mb); mt48lc32m8a2bb (512mb)
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 7 ?2006 micron technology, inc. all rights reserved. general description the mt16lsdf3264(l)h and mt16lsdf6464(l)h are high-speed cmos, dynamic random-access 256mb and 512mb unbuffered memory modules, organized in x64 configurations. these modules use internally configured quad -bank sdrams with a syn- chronous interface (all signals are registered on the positive edge of the clock signal ck). read and write accesses to the sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the device bank and row to be accessed (ba0, ba1 select the device bank, a0?a11 [256mb] or a0?a12 [512mb] select the device row). the address bits a0?a9 (for both 256mb and 512mb modules) registered coincident with the read or write command are used to select the starting device column location for the burst access. these modules provide for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. these modules use an internal pipelined architec- ture to achieve high-speed operation. this architec- ture is compatible with the 2 n rule of prefetch architectures, but it also enables the column address to be changed on every clock cycle to achieve a high- speed, fully random access. precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. these modules are designed to operate in 3.3v, low- power memory systems. an auto refresh mode is pro- vided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a fast data rate with auto- matic column-address generation, the ability to inter- leave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding sdram opera- tion, refer to the 128mb or 256mb sdram component data sheets. serial presence detect operation these modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonv olatile storage device contains 256 bytes. the first 128 bytes are programmed by micron to identify the module type, sdram charac- teristics and module timing parameters. the remain- ing 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa[2:0], which provide eight unique dimm/ eeprom addresses. write protect (wp) is tied to ground on the module, permanently disabling hard- ware write protect. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. when power is applied to v dd and v dd q (simul- taneously), and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. when the 100s delay has been satisfied with at least one command inhibit or nop command hav- ing been applied, a precharge command should be applied. all device banks must then be precharged, thereby placing the device in the all banks idle state. when in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. mode register definition the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cl, an operating mode, and a write burst mode, as shown in figure 4 on page 8. the mode register is pro- grammed via the load mode register command and will retain the stored information until it is pro- grammed again or the device loses power.
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 8 ?2006 micron technology, inc. all rights reserved. mode register bits m0?m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify the cl, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. for the 256mb and 512mb, m12 (a12) is undefined, but should be driven low during loading of the mode reg- ister. the mode register must be loaded when all device banks are idle, and the contro ller must wait the speci- fied time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst ori- ented, with the burst length being programmable, as shown in figure 4. the bu rst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in table 7 on page 9. the block is uniquely selected by a1?a9 when the burst length is set to tw o; by a2?a9 when the burst length is set to four; and by a3?a9 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting loca- tion within the block. full-page bursts wrap within the page if the boundary is reached, as shown in table 7 on page 9. figure 4: mode register definition diagram m3 = 0 1 2 4 8 reserve d reserve d reserve d full pa g e m3 = 1 1 2 4 8 reserve d reserve d reserve d reserve d operatin g mo d e s tan d ar d operation all other states reserve d 0 - 0 - define d - 0 1 burst type s equential interleave d c a s laten c y reserve d reserve d 2 3 reserve d reserve d reserve d reserve d burst len g th 512mb module 256mb module m0 0 1 0 1 0 1 0 1 burst len g th c a s laten c ybt a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 mo d e re g ister (mx) a dd ress bus 97 6 543 8210 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m 6 0 0 0 0 1 1 1 1 m 6 -m0 m8 m7 op mo d e a10 a11 10 11 reserve d *wb 0 1 write burst mo d e pro g ramme d b urst len g th s in g le lo c ation a cc ess m9 * s houl d pro g ram m12, m11, an d m10 = ?0, 0, 0? to ensure c ompati b ility with future d evi c es. * s houl d pro g ram m11 an d m10 = ?0, 0? to ensure c ompati b ility with future d evi c es. a12 12 burst len g th c a s laten c ybt a9 a7 a 6 a5 a4 a3 a8 a2 a1 a0 mo d e re g ister (mx) a dd ress bus 97 6 543 8210 op mo d e a10 a11 10 11 reserve d * wb
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 9 ?2006 micron technology, inc. all rights reserved. note: 1. for full-page accesses: y = 1,024 (both 256mb and 512mb modules) 2. for a burst length of two, a1?a9 select the block-of- two burst; a0 selects the st arting column within the block. 3. for a burst length of four, a2?a9 select the block-of- four burst; a0?a1 select the starting column within the block. 4. for a burst length of eight, a3?a9 select the block-of- eight burst; a0?a2 select th e starting colu mn within the block. 5. for a full-page burst, the full row is selected and a0?a9 select the starting column. 6. whenever a boundary of the block is reached within a given se q uence above, the following access wraps within the block. 7. for a burst length of one, a0?a9 select the uni q ue col- umn to be accessed, and mode register bit m3 is ignored. figure 5: cl diagram burst type accesses within a given burst may be programmed to be either sequential or in terleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type, and the starting column address, as shown in table 7. cas latency (cl) cl is the delay, in clock cycles, between the registra- tion of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dq will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the rele vant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all rele- vant access times are met, if a read command is regis- tered at t0 and the latency is programmed to two clocks, the dq will start driving after t1 and the data will be valid by t2, as shown in figure 4 on page 8. table 8 on page 10 indicates the operating frequencies at which each cl setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. table 7: burst definition table burst length starting column address order of accesses within a burst ty pe = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0-a9 (location 0-y) c n , c n + 1, c n + 2 c n + 3, c n + 4... ?c n - 1, c n ? not supported clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 10 ?2006 micron technology, inc. all rights reserved. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0- m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (non- burst) accesses. table 8: cl table allowable operating clock frequency (mhz) speed cl = 2 cl = 3 -13e 133 < 143 -133 100 < 133 -10e 100 na
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 11 ?2006 micron technology, inc. all rights reserved. commands the truth table provides a quick reference of avail- able commands. this is followed by written descrip- tion of each command. for a more detailed description of commands and operations, refer to the 128mb or 256mb sdram component data sheet. note: 1. a0?a11 (256mb) or a0?a12 (512mb) provide device row addr ess, and ba0, ba1 determine which device bank is made active. 2. a0?a9 (256mb and 512mb) provide device column address; a10 high enables th e auto precharge feature (nonpersis- tent), while a10 low disables the auto pr echarge feature; ba0, ba1 determine which device bank is being read from or written to. 3. a10 low: ba0, ba1 determine which devi ce bank is being precharged. a10 high: all device banks are precharged and ba0, ba1 are ?don?t care. ? 4. this command is auto refresh if cke is high, self refresh if cke is low. 5. internal refresh counter controls ro w addressing; all inputs and i/os are ? don?t care ? except for cke. 6. a0?a11 define the op-code written to the mode register; for the 256mb and 512mb, a12 should be driven low. 7. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). table 9: truth table ? sdram commands and dqmb operation cke is high for all commands shown except self refresh name (function) cs# ras# cas# we# dqmb addr dq notes command inhibit (nop) hxxx x x x no operation (nop) lhhh x x x active (select bank and activate row) l l h h x bank/row x 1 read (select bank and colu mn, and start read burst) lh l h l/h 8 bank/col x 2 write (select bank and column, and start write burst) lh l l l/h 8 bank/col valid 2 burst terminate lh h l x x active precharge (deactivate row in bank or banks) ll h l x code x 3 auto refresh or self refresh (enter self refresh mode) ll l h x x x 4, 5 load mode register llll xop-codex 6 write enable/output enable ???? l ?active7 write inhibit/output high-z ???? h ?high-z7
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 12 ?2006 micron technology, inc. all rights reserved. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. th is is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd supply, relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss . . . . . . . . . . . . . . . . . . . -1v to +4.6v operating temperature, t opr (commercial - ambient) . . . . . .0c to +65c storage temperature (plastic) . . . . . . -55c to +125c short circuit output current. . . . . . . . . . . . . . . . 50ma table 10: dc electrical charac teristics and operating conditions notes: 1, 5, 6; note s appear on page 16; v dd , v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd , v dd q3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il ?0.3 0.8 v 22 input leakage current: any input 0v v in v dd (all other pins not under test = 0v) command and address inputs i i ?80 80 a 33 ck, cke, s# ?40 40 dqmb ?10 10 output leakage current: dq pins are disabled; 0v v out v dd q dq i oz ?10 10 a 33 output levels: output high voltage (i out = -4ma) output low voltage (i out = 4ma) v oh 2.4 ? v v ol ?0.4v table 11: i dd specifications an d conditions ? 256mb notes: 1, 5, 6, 11, 13; sdram components only; not es appear on page 16; v dd , v dd q = +3.3v 0.3v max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 a 1,296 1,216 1,136 ma 3, 17, 19, 32 standby current: power-down mode; all device banks idle; cke = low i dd 2 b 32 32 32 ma 32 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 a 416 416 336 ma 3, 12, 19, 32 operating current: burst mode; co ntinuous burst; read or write; all devi ce banks active i dd 4 a 1,336 1,216 1,136 ma 3, 18, 19, 32 auto refresh current cke = high; s# = high t rfc = t rfc (min) i dd 5 b 5,280 4,960 4,320 ma 3, 12, 18, 19, 32,30 t rfc = 15.625s i dd 6 b 48 48 48 ma self refresh current: cke 0.2v standard i dd 7 b 32 32 32 ma 4 low power (l) i dd 7 b 16 16 16 ma a - value calculated as one module rank in this operat ing condition, and all other ranks in power-down mode. b - value calculated reflects all module ranks in this operation condition.
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 13 ?2006 micron technology, inc. all rights reserved. table 12: i dd specifications an d conditions ? 512mb notes: 1, 5, 6, 11, 13; sdram components only; not es appear on page 16; v dd , v dd q = +3.3v 0.3v max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 a 1,096 1,016 1,016 ma 3, 17,19, 32 standby current: power-down mode; all device banks idle; cke = low i dd 2 b 32 32 32 ma 32 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 a 336 336 336 ma 3, 12, 19, 32 operating current: burst mo de; continuous burst; read or write; all device banks active i dd 4 a 1,096 1,096 1,096 ma 3, 18, 19, 32 auto refresh current cke = high; s# = high t rfc = t rfc (min) i dd 5 b 4,560 4,320 4,320 ma 3, 12, 18, 19, 32,30 t rfc = 7.8125s i dd 6 b 56 56 56 ma self refresh current: cke < 0.2v standard i dd 7 b 40 40 40 ma 4 low power (l) i dd 7 b 24 24 24 ma a - value calculated as one module rank in this operat ing condition, and all other ranks in power-down mode. b - value calculated reflects all module ranks in this operation condition. table 13: capacitance note 2; notes appear on page 16 parameter symbol min max units input capacitance: address and command c i1 40 60.8 pf input capacitance: ck c i2 20 28 pf input capacitance: cke, s# c i3 20 30.4 pf input capacitance: dqmb c i4 57.6pf input/output capacitance: dq c io 812pf
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 14 ?2006 micron technology, inc. all rights reserved. table 14: electrical characteristics an d recommended ac operating conditions notes: 5, 6, 8, 9, 11, 31; notes appear on page 16; comply with pc100 and pc133 specifications, based on sdram device ac characteristics -13e -133 -10e parameter symbol min max min max min max units notes access time from clk (positive edge) cl = 3 t ac(3) 5.4 5.4 6 ns 27 cl = 2 t ac(2) 5.4 6 6 ns address hold time t ah 0.8 0.8 1 ns address setup time t as 1.5 1.5 2 ns clk high-level width t ch 2.5 2.5 3 ns clk low-level width t cl 2.5 2.5 3 ns clock cycle time cl = 3 t ck(3) 77.58 ns23 cl = 2 t ck(2) 7.5 10 10 ns 23 cke hold time t ckh 0.8 0.8 1 ns cke setup time t cks 1.5 1.5 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 2 ns data-in hold time t dh 0.8 0.8 1 ns data-in setup time t ds 1.5 1.5 2 ns data-out high-z time cl = 3 t hz(3) 5.4 5.4 6 ns 10 cl = 2 t hz(2) 5.4 6 6 ns 10 data-out low-z time t lz 111 ns data-out hold time (load) t oh 333 ns data-out hold time (no load) t ohn 1.8 1.8 1.8 ns 28 active-to-precharge command t ras 37 120,000 44 120,000 50 120,000 ns 32 active-to-active command period t rc 60 66 70 ns active-to-read or write delay t rcd 15 20 20 ns refresh period t ref 64 64 64 ms auto refresh period t rfc 66 66 70 ns precharge command period t rp 15 20 20 ns active bank a to active bank b command t rrd 14 15 20 ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 1 clk + 7ns 1 clk + 7.5ns 1 clk + 7ns ns 24 14 15 15 ns 25 exit self refresh to active command t xsr 67 75 80 ns 20
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 15 ?2006 micron technology, inc. all rights reserved. table 15: ac function al characteristics notes: 5, 6, 7, 8, 9, 11, 31; notes appear on page 16; comp ly with pc100 and pc133 specifications, based on sdram device parameter symbol -13e -133 -10e units notes read/write command to read/write command t ccd 11 1 t ck 17 cke to clock disable or power-down entry mode t cked 11 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 11 1 t ck 14 dqm to input data delay t dqd 00 0 t ck 17 dqm to data mask during writes t dqm 00 0 t ck 17 dqm to data high-z during reads t dqz 22 2 t ck 17 write command to input data delay t dwd 00 0 t ck 17 data-in to active command t dal 45 4 t ck 15, 21 data-in to precharge command t dpl 22 2 t ck 16, 21 last data-in to burst stop command t bdl 11 1 t ck 17 last data-in to ne w read/write command t cdl 11 1 t ck 17 last data-in to precharge command t rdl 22 2 t ck 16, 21 load mode register command to active or refresh command t mrd 22 2 t ck 26 data-out to high-z from precharge command cl = 3 t roh(3) 33 3 t ck 17 cl = 2 t roh(2) 22 2 t ck 17
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 16 ?2006 micron technology, inc. all rights reserved. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz, t a = 25c; pin under test biased at 1.4v. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0c t a +70c). 6. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh-command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 9. outputs measured at 1.5v with equivalent load: 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v ih (min) and no longer at the 1.5v crossover point. 12. other input signals can change no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i dd specifications are test ed after the device is properly initialized. 14. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 18. the i dd current will increase or decrease propor- tionally according to the amount of frequency alteration for the test condition. 19. address transitions aver age one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 10ns for -10e, and t ck = 7.5ns for - 133 and -13e. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, includ- ing t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge time ( t rp) begins at 7ns for -13e; 7.5ns for -133 and 7ns for -10e after the first clock delay, after the last write is executed. may not exceed limit set for precharge mode. 25. precharge mode only. 26. jedec and pc100 specify three clocks. 27. t ac for -133/-13e at cl = 3 with no load is 4.6ns and is guaranteed by design. 28. parameter guaranteed by design. 29. for -10e, cl = 2 and t ck = 10ns; for -133, cl = 3 and t ck = 7.5ns; for -13e, cl = 2 and t ck = 7.5ns. 30. cke is high during refresh command period t rfc (min), else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 31. refer to device data sheet for timing waveforms. 32. the value of t ras used in -13e speed grade mod- ule spds is calculated from t rc - t rp = 45ns. 33. leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. q 50pf
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 17 ?2006 micron technology, inc. all rights reserved. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (see figures 6, and 7). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (see figure 8). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no st op condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. figure 6: data validity figure 7: definition of start and stop figure 8: acknowledge response from receiver sc l s da data sta b le data c han g e data sta b le sc l s da s tart b it s top b it sc l from master data output from transmitter data output from re c eiver a c knowle dg e ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 18 ?2006 micron technology, inc. all rights reserved. figure 9: spd eeprom timing diagram table 16: eeprom device select code most significan t bit (b7) is sent first device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1010sa2sa1sa0rw protection register select code 0110sa2sa1sa0rw table 17: eeprom operating modes mode rw# bit w c bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = 1 random address read 0v ih or v il 1 start, device select, rw = 0, address 1v ih or v il restart, device select, rw = 1 se q uential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = 0 page write 0v il 16 start, device select, rw # = 0 sc l s da in s da out t low t s u: s ta t hd: s ta t f t hi g h t r t buf t dh t aa t s u: s to t s u:dat t hd:dat undefined
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 19 ?2006 micron technology, inc. all rights reserved. note: 1. to avoid spurious start and stop conditions, a minimum de lay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom wr ite cycle time ( t wrc) is the time from a valid stop condition of a write se q uence to the end of the eeprom internal erase/prog ram cycle. during the write cycle, the eepr om bus interface circuit is disabled, sda remains high due to pull-up resistor, and the ee prom does not respond to its slave address. table 18: serial presence-detec t eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = 2.3v to 3.6v parameter/condition symbol min max units supply voltage v dd 33.6 v input high voltage: logic 1; all inputs v ih v dd 0.7 v dd 0.5 v input low voltage: logic 0; all inputs v il ?1 v dd 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v 10% i sb ?30a power supply current: scl clock fre q uency = 100 khz i cc ?2ma table 19: serial presence-detec t eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = 2.3v to 3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 s data-out hold time t dh 200 ns sda and scl fall time t f300ns2 data-in hold time t hd:dat 0 s start condition hold time t hd:sta 0.6 s clock high period t high 0.6 s noise suppression time con stant at scl, sda inputs t i50ns clock low period t low 1.3 s sda and scl rise time t r0.3s2 scl clock fre q uency f scl 400 khz data-in setup time t su:dat 100 ns start condition setup time t su:sta 0.6 s 3 stop condition setup time t su:sto 0.6 s write cycle time t wrc 10 ms 4
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 20 ?2006 micron technology, inc. all rights reserved. table 20: serial pres ence-detect matrix ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low ? ; v dd = +3.3v 0.3v byte description entry (version) mt16lsdf3264h mt16lsdf6464h 0 number of bytes used by micron 128 80 80 1 total number of spd memory bytes 256 08 08 2 memory type sdram 04 04 3 number of row addresses 12 or 13 0c 0d 4 number of column addresses 10 0a 0a 5 number of banks 202 02 6 module data width 64 40 40 7 module data width (continued) 000 00 8 module voltage interface levels lvttl 01 01 9 sdram cycle time, t ck (cl = 3) 7ns (-13e) 7.5ns (-133) 8ns (-10e) 70 75 80 70 75 80 10 sdram access from clock, t ac (cl = 3) 5.4ns (-13e/-133) 6ns (-10e) 54 60 54 60 11 module configuration type none 00 00 12 refresh rate/type 15.6s or 7.81s/self 80 82 13 sdram width (primary sdram) 808 08 14 error-checking sdram data width 00 00 15 min clock delay from back-to-back random column addresses, t ccd 101 01 16 burst lengths supported 1, 2, 4, 8, page 8f 8f 17 number of banks on sdram device 404 4 18 cas latencies supported 2, 3 06 6 19 cs latency 001 01 20 we latency 001 01 21 sdram module attributes unbuffered 00 00 22 sdram device attributes: general 14 0e 0e 23 sdram cycle time, t ck (cl = 2) 7.5ns (13e) 10ns (-133/-10e) 75 a0 75 a0 24 sdram access from clk, t ac (cl = 2) 5.4ns (-13e) 6ns (-133/-10e) 54 60 54 60 25 sdram cycle time, t ck (cl = 1) ?00 00 26 sdram access from clk, t ac (cl = 1) ?00 00 27 min row precharge time, t rp 15ns (-13e) 20ns (-133/-10e) 0f 14 0f 14 28 min row active-t o-row active, t rrd 14ns (-13e) 15ns (-133) 20ns (-10e) 0e 0f 14 0e 0f 14 29 min ras#-to-cas# delay, t rcd 15ns (-13e) 20ns (-133/-10e) 0f 14 0f 14 30 min ras# pulse width, t ras 45ns (-13e) 44ns (133) 50ns (-10e) 2d 2c 32 2d 2c 32
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 21 ?2006 micron technology, inc. all rights reserved. note: 1. the value of t ras used for the -13e modu le is calculated from t rc - t rp. actual device spec value is 37ns. 31 module rank density 128mb or 256mb 20 40 32 command and address setup time, t as, t cms 1.5ns (-13e/-133) 2ns (-10e) 15 20 15 20 33 command and address hold time, t ah, t cmh 0.8ns (-13e/-133) 1ns (-10e) 08 10 08 10 34 data signal input setup time, t ds 1.5ns (-13e/-133) 2ns (-10e) 15 20 15 20 35 data signal input hold time, t dh 0.8ns (-13e/-133) 1ns (-10e) 08 10 08 10 36?40 reserved 00 00 41 device min active/ auto-refresh time, t rc 66ns (-13e) 71ns (-133) 66ns (-10e) 3c 42 46 3c 42 46 42?61 reserved 00 00 62 spd revision rev. 2.0 02 02 63 checksum for bytes 0-62 (-13e) (-133) (-10e) 95 e1 2d b8 04 50 64 manufacturer?s jedec id code micron 2c 2c 65?71 manufacturer?s jedec id code (continued) ff ff 72 manufacturing location 1?12 01?0c 01? 0c 73?90 module part number (ascii) variable data variable data 91 pcb identification code 1?9 01?09 01?09 92 identification co de (continued) 000 00 93 year of manufacture in bcd variable data variable data 94 week of manufacture in bcd variable data variable data 95-98 module serial number variable data variable data 99?125 manufacturer-specific data (rsvd) 126 system fre q uency 100 mhz/133 mhz (-13e/-133/-10e) 64 64 127 sdram component and clock detail cf cf table 20: serial presence-d etect matrix (continued) ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low ? ; v dd = +3.3v 0.3v byte description entry (version) mt16lsdf3264h mt16lsdf6464h
256mb, 512mb (x64, dr) 144-pin sdram sodimm pdf: 09005aef807924d2, source: 09005aef807924f1 micron technology, inc., reserves the right to change products or specifications without notice. sdf16c32_64x64hg.fm - rev. e 4/06 en 22 ?2006 micron technology, inc. all rights reserved. ? 8000 s. fe d eral way, p.o. box 6 , boise, id 83707-000 6 , tel: 208-3 6 8-3900 e-mail: pro d mktg@micron.com, internet: http://www.micr on.com, customer comme nt line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. figure 10: 144-pin sodimm dimensions note: all dimensions in inches (millim eters); or typical where noted. data sheet designation released (no mark): this data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifica- tions are subject to change, as further product devel- opment and data characterization sometimes occur. u1 u2 u17 u10 u9 u3 u4 u5 u6 u7 u8 u16 u15 u14 u13 u12 u11 0.150 (3.80) max 0.043 (1.10) 0.035 (0.90) pin 1 2.666 (67.72) 2.655 (67.45) 0.787 (20.00) typ 0.071 (1.80) (2x) 2.386 (60.60) 0.0315 (0.80) typ 83.82 (3.30) 0.024 (0.60) typ 0.079 (2.00) r (2x) pin 143 pin 144 pin 2 front view back view 0.079 (2.00) 0.236 (6.00) 2.504 (63.60) 0.100 (2.55) 0.059 (1.50) typ 0.157 (4.00) 1.255 (31.88) 1.245 (31.62) max min

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