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128kx36 pipelined sram with nobl? architecture cy7c1350a/gvt71128zc36 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05124 rev. ** revised september 12, 2001 350a features ? zero bus latency, no dead cycles between write and read cycles fast clock speed: 143, 133 and 100 mhzinternally syn- chronized registered outputs eliminate the need to con- trol oe single 3.3v ?5% and +5% power supply v cc separate v ccq for 3.3v or 2.5v i/o single r/w (read/write) control pin positive clock-edge triggered, address, data, and con- trol signal registers for fully pipelined applications interleaved or linear 4-word burst capability individual byte write (bwa ?bwd ) control (may be tied low) cke pin to enable clock and suspend operations three chip enables for simple depth expansion snooze mode for low-power standby automatic power-down packaged in a jedec standard 100-pin tqfp package functional description the cy7c1350a/gvt71128zc36 sram are designed to eliminate dead cycles when transitioning from read to write or vice versa. this sram is optimized for 100 percent bus utilization and achieve zero bus latency (zbl)/no bus laten- cy ? (nobl ? ). it integrates 131,072x36 sram cells with ad- vanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. the cypress synchronous burst sram family employs high-speed, low-power cmos designs using advanced triple-layer polysilicon, double-layer metal technology. each memory cell consists of four transistors and two high-valued resistors. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, depth-expansion chip enables (ce , ce 2 and ce 2 ), cycle start input (adv/ld ), clock enable (cke ), byte write enables (bwa , bwb , bwc , and bwd ), and read-write control (r/w ). address and control signals are applied to the sram during one clock cycle, and two cycles later, its associated data oc- curs, either read or write. a clock enable (cke ) pin allows operation of the cy7c1350a/gvt71128zc36 to be suspended as long as necessary. all synchronous inputs are ignored when (cke ) is high and the internal device registers will hold their previous values. there are three chip enable pins (ce , ce 2 , ce 2 ) that allow the user to deselect the device when desired. if any one of these three are not active when adv/ld is low, no new memory operation can be initiated and any burst cycle in progress is stopped. however, any pending data transfers (read or write) will be completed. the data bus will be in high-impedance state two cycles after chip is deselected or a write cycle is initiated. the cy7c1350a/gvt71128zc36 has an on-chip 2-bit burst counter. in the burst mode, the cy7c1350a/gvt71128zc36 provides four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the mode input pin. the mode pin selects between linear and interleaved burst sequence. the adv/ld signal is used to load a new external address (adv/ld = low) or increment the internal burst counter (adv/ld = high) output enable (oe ), snooze enable (zz) and burst sequence select (mode) are the asynchronous signals. oe can be used to disable the outputs at any given time. zz may be tied to low if it is not used. the cy7c1350a/gvt71128zc36 utilizes a high-perfor- mance high-volume 3.3v cmos process, and is packaged in a jedec standard 14-mm x 20-mm 100-pin plastic quad flat- pack (tqfp) for high board density. selection guide 7c1350a-143 71128zc36-4 7c1350a-133 71128zc36-5 7c1350a-133 71128zc36-6 7c1350a-100 71128zc36-7 maximum access time (ns) 4.0 4.2 4.2 5.0 maximum operating current (ma) com ? l 400 380 380 300 maximum cmos standby current (ma) com ? l 10 10 10 10 no bus latency and nobl are trademarks of cypress semiconductor corporation.
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 2 of 16 . note: 1. the functional block diagram illustrates simplified device operation. see truth table, pin descriptions and timing diagrams f or detailed information. functional block diagram ? 128kx36 [1] functional block diagram ? 512kx18 [1] 128k x 9 x 4 sram array dqa-dqd, dqpa, dqpb dqpc, dqpd clk input registers mux output registers output buffers address control di do sel control logic oe# zz mode cke# adv/ld# r/w# bwa#, bwb# bwc#, bwd# ce#, ce2#, ce2 sa0, sa1, sa
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 3 of 16 pin configurations sa sa sa sa sa1 sa0 nc nc v ss v cc nc sa sa sa sa sa sa v ccq v ss dqb dqb dqb v ss v ddq dqb dqb v ss v cc v cc dqa dqa v ccq v ss dqa dqa v ss v ccq v ccq v ss dqc dqc v ss v ccq dqc dqc v cc v ss dqd dqd v ccq v ss dqd dqd dqd v ss v ddq sa sa ce ce 2 bwa ce 2 v cc v ss clk r/w cke oe nc sa sa 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 sa sa adv/ld zz nc cy7c1350a/ 100-pin tqfp package bwd mode bwc dqc dqc dqc dqc dqpc dqd dqd dqpd dqd dqpb dqb dqa dqa dqa dqa dqpa dqb dqb (128k x 36) bwb v cc v cc gvt71128zc36 pin descriptions tqfp pins name type description 37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 sa0, sa1, sa input- synchronous synchronous address inputs: the address register is triggered by a combination of the rising edge of clk, adv/ld low, cke low and true chip enables. sa0 and sa1 are the two least significant bits of the address field and set the internal burst counter if burst cycle is initiated. 93, 94, 95, 96 bwa , bwb , bwc , bwd input- synchronous synchronous byte write enables: each 9-bit byte has its own active low byte write enable. on load write cycles (when r/w and adv/ld are sampled low), the appropriate byte write signal (bwx ) must be valid. the byte write signal must also be valid on each cycle of a burst write. byte write signals are ignored when r/w is sampled high. the appropriate byte(s) of data are written into the device two cycles later. bwa controls dqa pins; bwb controls dqb pins; bwc controls dqc pins; bwd controls dqd pins. bwx can all be tied low if always doing write to the entire 36-bit word.
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 4 of 16 87 cke input- synchronous synchronous clock enable input: when cke is sampled high, all other synchro- nous inputs, including clock are ignored and outputs remain unchanged. the effect of cke sampled high on the device outputs is as if the low-to-high clock transition did not occur. for normal operation, cke must be sampled low at rising edge of clock. 88 r/w input- synchronous read write: r/w signal is a synchronous input that identifies whether the current loaded cycle and the subsequent burst cycles initiated by adv/ld is a read or write operation. the data bus activity for the current cycle takes place two clock cycles later. 89 clk input- synchronous clock: this is the clock input to cy7c1350a/gvt71128zc36. except for oe , zz and mode, all timing references for the device are made with respect to the rising edge of clk. 98, 92 ce , ce 2 input- synchronous synchronous active low chip enable: ce and ce 2 are used with ce 2 to enable the cy7c1350a/gvt71128zc36. ce or ce 2 sampled high or ce 2 sampled low, along with adv/ld low at the rising edge of clock, initiates a deselect cycle. the data bus will be high-z two clock cycles after chip deselect is initiated. 97 ce 2 input- synchronous synchronous active high chip enable: ce 2 is used with ce and ce 2 to enable the chip. ce 2 has inverted polarity but otherwise is identical to ce and ce 2 . 86 oe input asynchronous output enable: oe must be low to read data. when oe is high, the i/o pins are in high-impedance state. oe does not need to be actively con- trolled for read and write cycles. in normal operation, oe can be tied low. 85 adv/l d input- synchronous advance/load: adv/ld is a synchronous input that is used to load the internal registers with new address and control signals when it is sampled low at the rising edge of clock with the chip is selected. when adv/ld is sampled high, then the internal burst counter is advanced for any burst that was in progress. the external addresses and r/w are ignored when adv/ld is sampled high. 31 mode input- static burst mode: when mode is high or nc, the interleaved burst sequence is selected. when mode is low, the linear burst sequence is selected. mode is a static dc input. 64 zz input- asynchronous snooze enable: this active high input puts the device in low power consumption standby mode. for normal operation, this input has to be either low or nc. 52, 53, 56-59, 62, 63, 68, 69, 72-75, 78, 79 2, 3, 6 ? 9, 12, 13 18, 19, 22 ? 25, 28, 29 dqa dqb dqc dqd input/ output data inputs/outputs: both the data input path and data output path are registered and triggered by the rising edge of clk. byte ? a ? is dqa pins; byte ? b ? is dqb pins; byte ? c ? is dqc pins; byte ? d ? is dqd pins. 51, 80, 1, 30 dqpa, dqpb, dqpc, dqpd input/ output parity inputs/outputs: both the data input path and data output path are registered and triggered by the rising edge of clk. dqpa is parity bit for byte ? a ? ; dqpb is parity bit for byte ? b ? ; dqpc is parity bit for byte ? c ? ; dqpd is parity bit for byte ? d ? . 14, 15, 16, 41, 65, 66, 91 v cc supply power supply: +3.3v ? 5% and +5%. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss ground ground: gnd. 4, 11, 20, 27, 54, 61, 70, 77 v ccq i/o supply output buffer supply: +3.3v ? 0.165v and +0.165v for 3.3v i/o. +2.5v ? 0.125v and +0.4v for 2.5v i/o. 38, 39, 42, 43, 83, 84 nc - no connect: these signals are not internally connected. it can be left floating or be connected to v cc or to gnd. pin descriptions (continued) tqfp pins name type description
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 5 of 16 notes: 2. upon completion of the burst sequence, the counter wraps around to its initial state and continues counting. 3. l means logic low. h means logic high. x means ? don ? t care. ? 4. multiple bytes may be selected during the same cycle. 5. this assumes that cke , ce , ce 2 and ce 2 are all true. 6. all addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. d ata out is valid after a clock-to-data delay from the rising edge of clock. interleaved burst address table (mode = v cc or nc) first address (external) second address (internal) third address (internal) fourth address (internal) [2] a...a 00 a...a 01 a...a 10 a...a 11 a...a 01 a...a 00 a...a 11 a...a 10 a...a 10 a...a 11 a...a 00 a...a 01 a...a 11 a...a 10 a...a 01 a...a 00 linear burst address table (mode = v ss ) first address (external) second address (internal) third address (internal) fourth address (internal) [2] a...a 00 a...a 01 a...a 10 a...a 11 a...a 01 a...a 10 a...a 11 a...a 00 a...a 10 a...a 11 a...a 00 a...a 01 a...a 11 a...a 00 a...a 01 a...a 10 partial truth table for read/write [3] function r/w bwa bwb bwc bwd read hxxxx no write lhhhh write byte a (dqa, dqpa) [4] llhhh write byte b (dqb, dqpb) [4] lhlhh write byte c (dqc, dqpc) [4] lhhlh write byte d (dqd, dqpd) [4] lhhhl write all bytes l l l l l functional timing diagram [5, 6] clock address (sa0, sa1, sa) cycle n+19 n+20 n+21 n+22 n+23 n+24 n+25 n+26 n+27 a 19 a 22 a 20 a 21 a 23 a 24 a 25 a 26 control (r/w#, bwx#, adv/ld#) c 19 c 20 c 21 c 22 c 23 c 24 c 25 c 26 data dq[a:d] dqp[a:d] dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 a 27 c 27 dq 25
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 6 of 16 notes: 7. l means logic low. h means logic high. x means ? don ? t care. ? high-z means high impedance. bwx = l means [bwa *bwb *bwc *bwd ] equals low. bwx = h means [bwa *bwb *bwc *bwd ] equals high. 8. ce equals h means ce and ce 2 are low along with ce 2 being high. ce equals l means ce or ce 2 is high or ce 2 is low. ce equals x means ce , ce 2 , and ce 2 are ? don ? t care. ? 9. bwa enables write to byte ? a ? (dqa pins). bwb enables write to byte ? b ? (dqb pins). bwc enables write to byte ? c ? (dqc pins). bwd enables write to byte ? d ? (dqd pins). 10. the device is not in snooze mode, i.e. the zz pin is low. 11. during snooze mode, the zz pin is high and all the address pins and control pins are ? don ? t care. ? the snooze mode can only be entered two cycles after the write cycle, otherwise the write cycle may not be completed. 12. all inputs, except oe , zz, and mode pins, must meet set-up time and hold time specification against the clock (clk) low-to-high transition edge. 13. oe may be tied to low for all the operation. this device automatically turns off the output driver during write cycle. 14. device outputs are ensured to be in high-z during device power-up. 15. this device contains a 2-bit burst counter. the address counter is incremented for all continue burst cycles. address wraps to the initial address every fourth burst cycle. 16. continue burst cycles, whether read or write, use the same control signals. the type of cycle performed, read or write, depe nds upon the r/w control signal at the begin burst cycle. a continue deselect cycle can only be entered if a deselect cycle is executed first. 17. dummy read and abort write cycles can be entered to set up subsequent read or write cycles or to increment the burst counter . 18. when an ignore clock edge cycle enters, the output data (q) will remain the same if the previous cycle is read cycle or rema in high-z if the previous cycle is write or deselect cycle. truth table [7, 8, 9, 10, 11, 12, 13, 14, 15] operation previous cycle address used r/w adv/ld ce cke bwx oe dq (2 cycles later) deselect cycle x x x l h l x x high-z continue deselect/nop [16] deselect x x h x l x x high-z read cycle (begin burst) x external h l l l x x q read cycle (continue burst) [16] read next x h x l x x q dummy read (begin burst) [17] x external h l l l x h high-z dummy read (continue burst) [16, 17] read next x h x l x h high-z write cycle (begin burst) x external l l l l l x d write cycle (continue burst) [16] write next x h x l l x d abort write (begin burst) [17] x external l l l l h x high-z abort write (continue burst) [16, 17] write next x h x l h x high-z ignore clock edge/nop [18] xxxhxhxx-
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 7 of 16 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) voltage on v cc supply relative to v ss ......... ? 0.5v to +4.6v v in ........................................................... ? 0.5v to v cc +0.5v storage temperature (plastic) .................... ? 55 c to +125 c junction temperature ............................................... +125 c power dissipation ......................................................... 2.0w short circuit output current ....................................... 50 ma operating range range ambient temperature [19] v cc /v ccq com ? l 0 c to +70 c 3.3v 5% electrical characteristics over the operating range [20] parameter description test conditions min. max. unit v ihd input high (logic 1) voltage [21, 22] data inputs (dqxx) 2.0 v cc +0.3 v v ih all other inputs 2.0 4.6 v v il input low (logic 0) voltage [21, 22] ? 0.5 0.8 v il i input leakage current 0v < v in < v cc - 5 a il i mode and zz input leakage current [21] 0v < v in < v cc - 30 a il o output leakage current output(s) disabled, 0v < v out < v cc - 5 a v oh output high voltage [21] i oh = ? 5.0 ma for 3.3v i/o 2.4 v i oh = ? 1.0 ma for 2.5v i/o 2.0 v v ol output low voltage [21] i ol = 8.0 ma 0.4 v v cc supply voltage [21] 3.135 3.465 v v ccq i/o supply voltage [21] 3.3v i/o 3.135 3.465 v 2.5v i/o 2.4 2.9 v parameter description conditions typ. 143 mhz/ -4 133 mhz/ -5 117 mhz/ -6 100 mhz/ -7 unit i cc power supply current: operating [24, 25, 26, 27] device selected; all inputs < v il or > v ih ; cycle time > t kc min.; v cc =max.; outputs open, adv/ld = x, f = f max 2 150 400 380 350 300 ma i sb2 cmos standby [25, 26, 27] device deselected; v cc = max.; all inputs < v ss + 0.2 or > v cc ? 0.2; all inputs static; clk frequency = 0 510101010ma i sb3 ttl standby [25, 26, 27] device deselected; all inputs < v il or > v ih ; all inputs static; v cc = max.; clk frequency = 0 20 40 40 40 40 ma i sb4 clock running [25, 26, 27] device deselected; all inputs < v il or > v ih ; v cc = max; clk cycle time > t kc min. 50 95 85 80 70 ma notes: 19. t a is the case temperature. 20. values in table are associated with the operating frequencies listed. 21. all voltages referenced to v ss (gnd). 22. overshoot: v ih < +6.0v for t < t kc /2 undershoot:v il < ? 2.0v for t < t kc /2. 23. mode pin has an internal pull-up and zz pin has an internal pull-down. these two pins exhibit an input leakage current of 5 0 a. 24. i cc is given with no output current. i cc increases with greater output loading and faster cycle times. 25. ? device deselected ? means the device is in power-down mode as defined in the truth table. ? device selected ? means the device is active. 26. typical values are measured at 3.3v, 25 c, and 20 ns cycle time. 27. at f = f max , inputs are cycling at the maximum frequency of read cycles of 1/t cyc ; f = 0 means no input lines are changing.
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 8 of 16 note: 28. this parameter is sampled. capacitance [28] parameter description test conditions typ. max. unit c i input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 4 4 pf c o input/output capacitance (dq) 7 6.5 pf thermal resistance description test conditions symbol tqfp typ. units thermal resistance (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, 4-layer pcb ja 25 c/w thermal resistance (junction to case) jc 9 c/w dq 317 ? 351 ? 5pf (a) (b) dq 50 ? z 0 =50 ? v t = 1.5v 3.3v all input pulses 3.0v 0v 90% 10% 90% 10% 1.0 ns 1.0 ns (c) ac test loads and waveforms
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 9 of 16 switching characteristics over the operating range [29] -4/ 143 mhz -5/ 133 mhz -6/ 117 mhz -7/ 100 mhz parameter description min. max. min. max. min. max. min. max. unit clock t kc clock cycle time 7.0 7.5 8.5 10 ns t kh clock high time 2.0 2.2 3.4 3.5 ns t kl clock low time 2.0 2.2 3.4 3.5 ns output times t kq clock to output valid 4.0 4.2 4.5 5.0 ns t kqx clock to output invalid 1.5 1.5 1.5 1.5 ns t kqlz clock to output in low-z [28, 30, 31] 1.5 1.5 1.5 1.5 ns t kqhz clock to output in high-z [28, 30, 31] 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 ns t oeq oe to output valid 4.0 4.2 4.5 5.0 ns t oelz oe to output in low-z [28, 30, 31] 0 0 0 0 ns t oehz oe to output in high-z [28, 30, 31] 4 5 6 6 ns set-up times t s address and controls [32] 2.0 2.0 2.0 2.2 ns t sd data in [32] 1.7 1.7 1.7 2.0 ns hold times t h address and controls [32] 0.5 0.5 0.5 0.5 ns t hd data in [32] 0.5 0.5 0.5 0.5 ns notes: 29. test conditions as specified with the output loading as shown in part (a) of ac test loads unless otherwise noted. values in table are associated with the operating frequencies listed. 30. output loading is specified with c l =5 pf as in part (a) of ac test loads. 31. at any given temperature and voltage condition, t kqhz is less than t kqlz and t oehz is less than t oelz . 32. this is a synchronous device. all synchronous inputs must meet specified set-up and hold time, except for ? don ? t care ? as defined in the truth table.
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 10 of 16 switching waveforms read timing [33, 34, 35, 36] notes: 33. q(a 1 ) represents the first output from the external address a 1 . q(a 2 ) represents the first output from the external address a 2 ; q(a 2 +1) represents the next output data in the burst sequence of the base address a 2 , etc. where address bits sa0 and sa1 are advancing for the four word burst in the sequence defined by the state of the mode input. 34. ce 2 timing transitions are identical to the ce signal. for example, when ce is low on this waveform, ce 2 is low. ce 2 timing transitions are identical but inverted to the ce signal. for example, when ce is low on this waveform, ce 2 is high. 35. burst ends when new address and control are loaded into the sram by sampling adv/ld low. 36. r/w is ? don ? t care ? when the sram is bursting (adv/ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/w signal when new address and control are loaded into the sram. clk cke# r/w# address bwa#, bwb# bwc#, bwd# ce# (see note) adv/ld# oe# dq a 1 a 2 q(a 1 ) q(a 2 ) q(a 2 +1) q(a 2 +2) q(a 2 +3) q(a 2 ) t kqlz t kqx t kq pipeline read burst pipeline read pipeline read t kqhz (cke# high, eliminates current l-h clock edge) (burst wraps around to initial state) t kl t kc t kh t s t h t s t h t s t h t s t h t s t h
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 11 of 16 write timing [34, 35, 36, 37, 38] notes: 37. d(a 1 ) represents the first input to the external address a1. d(a 2 ) represents the first input to the external address a 2 ; d(a 2 +1) represents the next input data in the burst sequence of the base address a 2 , etc. where address bits sa0 and sa1 are advancing for the four word burst in the sequence defined by the state of the mode input. 38. individual byte write signals (bwx ) must be valid on all write and burst-write cycles. a write cycle is initiated when r/w signal is sampled low when adv/ld is sampled low. the byte write information comes in one cycle before the actual data is presented to the sram. switching waveforms (continued) clk cke# r/w# address bwa#, bwb# bwc#, bwd# ce# (see note) adv/ld# oe# dq a 1 a 2 d(a 1 ) d(a 2 ) d(a 2 +1) d(a 2 +2) d(a 2 +3) d(a 2 ) t sd t hd pipeline write burst pipeline write pipeline write (cke# high, eliminates current l-h clock edge) (burst wraps around to initial state) t kl t kc t kh t s t h t s t h t s t h t s t h t s t h t s t h bw(a 1 ) bw(a 2 ) bw(a 2 +1) bw(a 2 ) bw(a 2 +2) bw(a 2 +3)
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 12 of 16 read/write timing [34, 38, 39] note: 39. q(a 1 ) represents the first output from the external address a 1 . d(a 2 ) represents the input data to the sram corresponding to address a 2 . switching waveforms (continued) clk cke# r/w# address bwa#, bwb# bwc#, bwd# ce# (see note) adv/ld# oe# data in (d) a 1 a 2 write a 3 a 4 a 5 a 6 a 7 a 8 a 9 q(a 1 ) q(a 3 ) q(a 6 ) q(a 7 ) d(a 2 ) d(a 4 ) d(a 5 ) write ata out (q) read read read t kq t kqhz t kql z t kqx t kl t kc t kh bw(a 2 ) t s t h t s t h t s t h t s t h t s t h t s t h bw(a 4 ) bw(a 5 )
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 13 of 16 cke timing [34, 38, 39, 40] note: 40. cke when sampled high on the rising edge of clock will block that l-h transition of the clock from propagating into the sram. the part will behave as if the l-h clock transition did not occur. all internal register in the sram will retain their previous state. switching waveforms (continued) clk cke# r/w# address bwa#, bwb# bwc#, bwd# ce# (see note) adv/ld# oe# data in (d) a 1 a 2 t s t h t h t kl t kc t h t s t sd t s a 3 a 4 a 5 q(a 1 ) d(a 2 ) t hd data out (q) t kqx t kh t kqhz t kq t kqlz q(a 3 ) t s t s t s t h t h t h
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 14 of 16 ce timing [34, 38, 41, 42] notes: 41. q(a 1 ) represents the first output from the external address a 1 . d(a 3 ) represents the input data to the sram corresponding to address a 3 , etc. 42. when either one of the chip enables (ce , ce 2 , or ce 2 ) is sampled inactive at the rising clock edge, a chip deselect cycle is initiated. the data-bus high-z one cycle after the initiation of the deselect cycle. this allows for any pending data transfers (reads or writes) to be comple ted. switching waveforms (continued) clk cke# r/w# address bwa#, bwb# bwc#, bwd# ce# (see note) adv/ld# oe# data in (d) a 1 a 2 t s t kl t kc t s t h t sd a 3 a 4 a 5 d(a 3 ) t hd data out (q) t kh t kqx t kqhz t kq t kqlz t h t s t h t s t h t s t h t s q(a 1 ) q(a 2 ) q(a 4 ) t h t oelz t oeq t oehz
cy7c1350a/gvt71128zc36 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. ordering information speed (mhz) ordering code package name package type operating range 143 cy7c1350a-143ac/ gvt71128zc36t-4 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial 133 cy7c1350a-133ac/ gvt71128zc36t-5 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack 133 cy7c1350a-133ac/ GVT71128ZC36T-6 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack 100 cy7c1350a-100ac/ gvt71128zc36t-7 a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack package diagram 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1350a/gvt71128zc36 document #: 38-05124 rev. ** page 16 of 16 document title: cy7c1350a/gvt71128zc36 128kx36 pipelined sram with nobl ? architecture document number: 38-05124 rev. ecn no. issue date orig. of change description of change ** 108315 09/25/01 bri new cypress data sheet ? converted from galvantech format

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