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general features: ?operating voltage: 3v to 5.5v (v dd - v ss ) ?5v count frequency: 40mhz ?3v count frequency: 20mhz ?32-bit counter (cntr). ?32-bit data register (dtr) and comparator. ?32-bit output register (otr). ?two 8-bit mode registers (mdr0, mdr1) for programmable functional modes. ?8-bit instruction register (ir). ?8-bit status register (str). ?latched interrupt output on carry or borrow or compare or index. ?index driven counter load, output register load or counter reset. ?internal quadrature clock decoder and filter. ?x1, x2 or x4 mode of quadrature counting. ?non-quadrature up/down counting. ?modulo-n, non-recycle, range-limit or free-running modes of counting ?8-bit, 16-bit, 24-bit and 32-bit programmable configuration synchronous (spi) serial interface ?LS7366R (dip), LS7366R-s (soic), LS7366R-ts (tssop) - see figure 1 - spi/microwire (serial peripheral interface): ?standard 4-wire connection: mosi, miso, ss/ and sck. ?slave mode only. general description: LS7366R is a 32-bit cmos counter, with direct interface for quadra- ture clocks from incremental encoders. it also interfaces with the index signals from incremental encoders to perform variety of marker functions. for communications with microprocessors or microcontrollers, it provides a 4-wire spi/microwire bus.the four standard bus i/os are ss/, sck, miso and mosi. the data transfer between a micro- controller and a slave LS7366R is synchronous. the synchroniza- tion is done by the sck clocks supplied by the microcontroller. each transmission is organized in blocks of 1 to 5 bytes of data. a trans- mission cycle is intitiated by a high to low transition of the ss/ input. the first byte received in a transmission cycle is always an instruc- tion byte, whereas the second through the fifth bytes are always interpreted as data bytes. a transmission cycle is terminated with the low to high transition of the ss/ input. received bytes are shifted in at the mosi input, msb first, with the leading edges (high transi- tion) of the sck clocks. output data are shifted out on the miso output, msb first, with the trailing edges (low transition) of the sck clocks. 32-bit quadrature counter with serial interface lsi/csi lsi computer systems, inc. 1235 walt whitman road, melville, ny 11747 (631) 271-0400 fax (631) 271-0405 LS7366R u l a3800 may 2006 7366r-050106-1 read and write commands cannot be combined. for example, when the device is shifting out read data on miso output, it ignores the mosi input, even though the ss/ input is active. ss/ must be terminated and reasserted before the device will accept a new command. the counter can be configured to operate as 1, 2, 3 or 4-byte counter. when configured as an n-byte counter, the cntr, dtr and otr are all config- ured as n-byte registers, where n = 1, 2, 3 or 4. the content of the instruction/data identity is automatically adjusted to match the n-byte configu- ration. for example, if the counter is configured as a 2-byte counter, the instruction ?rite to dtr expects 2 data bytes following the instruction byte. if the counter is configured as a 3-byte counter, the same instruction will expect 3 bytes of data follow- ing the instruction byte. following the transfer of the appropriate number of bytes any further attempt of data transfer is ignored until a new instruction cycle is started by switching the ss/ input to high and then low. the counter can be programmed to operate in a number of different modes, with the operating characteristics being written into the two mode registers mdr0 and mdr1. hardware i/os are provided for event driven operations, such as processor interrupt and index related functions. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vss v dd b a index/ lflag/ ss/ sck LS7366R miso mosi f cki f cko cnt_en dflag/ figure 1 lsi pin assignment top view
7366r-050106-2 i/o pins: following is a description of all the input/output pins. a ( pin 12) b (pin 11) inputs. a and b quadrature clock outputs from incremental encoders are directly applied to the a and b inputs of the LS7366R. these clocks are ideally 90 degrees out-of-phase signals. a and b inputs are validated by on-chip digital filters and then decoded for up/down direction and count clocks. in non-quadrature mode, a serves as the count input and b serves as the direction input (b = high enables up count, b = low enables down count). in non-quadrature mode, the a and b inputs are not filtered internally, and are instan- taneous in nature. index/ (pin 10) input. the index/ is a programmable input that can be driven directly by the index output of an incremental encod- er. it can be programmed via the mdr0 to function as one of the following: lcntr (load cntr with data from dtr), rcntr (reset cntr), or lotr (load otr with data from cntr). alternatively, the index input can be masked out for "no functionality". in quadrature mode, the index/ input can be configured to operate in either synchronous or asynchronous mode. in the synchronous mode the index/ input is sampled with the same filter clock used for sampling the a and the b inputs and must satisfy the phase relationship in which the index/ is in the active level of logic 0 during a minimum of a quarter cycle of both a and b high or both a and b low. in non-quadrature mode, the index/ input is unconditionally set to the asynchronous mode. in the asynchronous mode, the index/ input is not sampled and can be applied in any phase relationship with respect to a and b. f ck i (pin 2) , f ck0 (pin 1) input, output. a crystal connected between these 2 pins generates the basic clock for filtering the a, b and index/ inputs in the quadrature count mode. instead of a crystal the f cki input may also be driven by an external clock. the frequency at the f cki input is either divided by 2 (if mdr0 = 1) or divided by 1 (if mdr0 = 0) for the filter circuit. for proper filtering of the a, b and the index/ inputs the following condition must be satisfied: f f 3 4f qa where f f is the internal filter clock frequency derived from the f ck i in accordance with the status of mdr0 and f qa is the maximum frequency of clock a in quadrature mode. in non-quadrature count mode, f cki is not used and should be tied off to any stable logic state. ss/ (pin 4) a high to low transition at the ss/ (slave select) input selects the LS7366R for serial bi-directional data transfer; a low to high transition disables serial data transfer and brings the miso output to high impedance state. this allows for the accommodation of multiple slave units on the serial i/o. cnt_en (pin 13) input. counting is enabled when cnt_en input is high; counting is disabled when this input is low. there is an internal pull-up resistor on this input. lflag/ (pin 8), dflag/ (pin 9) outputs. lflag/ and dflag/ are programmable outputs to flag the occurences of carry (counter overflow), borrow (counter underflow), compare (cntr = dtr) and index. the lflag/ is an open drain latched output. in contrast, the dflag/ is a push- pull instantaneous output. the lflag/ can be wired in multi- slave configuration, forming a single processor interrupt line. when active lflag/ switches to logic 0 and can be restored to the high impedence state only by clearing the status register, str. in contrast, the dflag/ dynamically switches low with occurences of carry, barrow, compare and index conditions. the configuration of lflag/ and dflag/ are made through the control register mdr1. mosi (rxd ) (pin 7) input. serial output data from the host processor is shifted into the LS7366R at this input. miso (txd) (pin 6) output. serial output data from the LS7366R is shifted out on the miso (master in slave out) pin. the miso output goes into high impedance state when ss/ input is at logic high, providing multiple slave-unit serial outputs to be wire-ored. sck (pin 5) input. the sck input serves as the shift clock input for transmit- ting data in and out of LS7366R on the mosi and the miso pins, respectively. since the LS7366R can operate only in the slave mode, the sck signal is provided by the host processor as a means for synchronizing the serial transmission between itself and the slave LS7366R. registers: the following is a list of ls7366 internal registers: upon power-up the registers dtr, cntr, str, mdr0 and mdr1 are reset to zero. dtr. the dtr is a software configurable 8, 16, 24 or 32-bit input data register which can be written into directly from mosi, the serial input. the dtr data can be transferred into the 32-bit counter (cntr) under program control or by hardware index signal. the dtr can be cleared to zero by software control. in certain count modes, such as modulo-n and range-limit, dtr holds the data for "n" and the count range, respectively. in compare operations, whereby compare flag is set, the dtr is compared with the cntr.
str. the str is an 8-bit status register which stores count related status information. cy bw cmp idx cen pls u/d s 7 6 5 4 3 2 1 0 7366r-122205-3 ir . the ir is an 8-bit register that fetches instruction bytes from the received data stream and executes them to perform such functions as setting up the operating mode for the chip (load the mdr) and data transfer among the various registers. b7 b6 b5 b4 b3 b2 b1 b0 b2 b1 b0 = xxx (don? care) b5 b4 b3 = 000: select none = 001: select mdr0 = 010: select mdr1 = 011: select dtr = 100: select cntr = 101: select otr = 110: select str = 111: select none b7 b6 = 00: clr register = 01: rd register = 10: wr register = 11: load register the actions of the four functions, clr, rd, wr and load are elaborated in table 1. table 1 number of bytes op code register operation mdr0 clear mdr0 to zero mrd1 clear mdr1 to zero 1 clr dtr none cntr clear cntr to zero otr none str clear str to zero mdr0 output mdr0 serially on txd (miso) mdr1 output mdr1 serially on txd (miso) 2 to 5 rd dtr none cntr transfer cntr to otr, then output otr serially on txd (miso) otr output otr serially on txd (miso) str output str serially on txd (miso) mdr0 write serial data at rxd (mosi) into mdr0 mdr1 write serial data at rxd (mosi) into mdr1 2 to 5 wr dtr write serial data at rxd (mosi) into dtr cntr none otr none str none mdr0 none mdr1 none 1 load dtr none cntr transfer dtr to cntr in ?arallel otr transfer cntr to otr in ?arallel cntr. the cntr is a software configurable 8, 16, 24 or 32-bit up/down counter which counts the up/down pulses resulting from the quadrature clocks applied at the a and b inputs, or alternatively, in non-quadrature mode, pulses applied at the a input. by means of ir intructions the cntr can be cleared, loaded from the dtr or in turn, can be transferred into the otr. otr. the otr is a software configuration 8, 16, 24 or 32-bit register which can be read back on the miso output. since instantaneous cntr value is often needed to be read while the cntr continues to count, the otr serves as a convenient dump site for instantaneous cntr data which can then be read without interfering with the counting process. cy: carry (cntr overflow) latch bw: borrow (cntr underflow) latch cmp: compare (cntr = dtr) latch idx: index latch cen: count enable status: 0: counting disabled, 1: counting enabled pls: power loss indicator latch; set upon power up u/d: count direction indicator: 0: count down, 1: count up s: sign bit. 1: negative, 0: positive
7366r-041906-4 absolute maximum ratings: (all voltages referenced to vss) parameter symbol values unit dc supply voltage v dd +7.0 v input voltage v in vss - 0.3 to v dd + 0.3 v operating temperature t a -25 to +80 o c storage temperature t stg 65 to +150 o c mdr1. the mdr1 (mode register 1) is an 8-bit read/write register which is appended to mdr0 for additional modes. upon power-up mdr1 is cleared to zero. b7 b6 b5 b4 b3 b2 b1 b0 b1 b0 = 00: 4-byte counter mode = 01: 3-byte counter mode = 10: 2-byte counter mode. = 11: 1-byte counter mode b2 = 0: enable counting = 1: disable counting b3 = : not used b4 = 0: nop = 1: flag on idx (b4 of str) b5 = 0: nop = 1: flag on cmp (b5 of str) b6 = 0: nop = 1: flag on bw (b6 of str) b7 = 0: nop = 1: flag on cy (b7 of str) mdr0. the mdr0 (mode register 0) is an 8-bit read/write register that sets up the operating mode for the LS7366R. the mdr0 is written into by executing the "write-to-mdr0" instruction via the instruction register. upon power up mdr0 is cleared to zero. the following is a breakdown of the mdr bits: b7 b6 b5 b4 b3 b2 b1 b0 b1 b0 = 00: non-quadrature count mode. (a = clock, b = direction). = 01: x1 quadrature count mode (one count per quadrature cycle). = 10: x2 quadrature count mode (two counts per quadrature cycle). = 11: x4 quadrature count mode (four counts per quadrature cycle). b3 b2 = 00: free-running count mode. = 01: single-cycle count mode (counter disabled with carry or borrow, re-enabled with reset or load). = 10: range-limit count mode (up and down count-ranges are limited between dtr and zero, respectively; counting freezes at these limits but resumes when direction reverses). = 11: modulo-n count mode (input count clock frequency is divided by a factor of (n+1), where n = dtr, in both up and down directions). b5 b4 = 00: disable index. = 01: configure index as the "load cntr" input (transfers dtr to cntr). = 10: configure index as the "reset cntr" input (clears cntr to 0). = 11: configure index as the "load otr" input (transfers cntr to otr). b6 = 0: asynchronous index = 1: synchronous index (overridden in non-quadrature mode) b7 = 0: filter clock division factor = 1 = 1: filter clock division factor = 2 note: applicable to both lflag/ and dflag/
dc electrical characteristics . (t a = -25?c to +85?) parameter symbol min. typ max. unit remarks supply voltage v dd 3.0 - 5.5 v - supply current i dd 300 400 450 ? v dd = 3.0v i dd 700 800 950 ? v dd = 5.0v input voltages f cki , logic high v ch 2.3 - - v v dd = 3.0v v ch 3.7 - - v v dd = 5.0v f cki , logic low v cl - - 0.7 v v dd = 3.0v v cl - - 1.3 v v dd = 5.0 all other inputs, logic high v ah 2.1 - v v dd = 3.0v v ah 3.5 - v v dd = 5.0v all other inputs, logic low v al - - 0.5 v v dd = 3.0v v al - - 1.0 v v dd = 5.0v input currents : cnt_en low i iel - 3.0 5.0 ? v al = 0.7v, v dd = 3.0v i iel - 10.0 15.0 ? v al = 1.2v, v dd = 5.0v cnt_en high i ieh - 1.0 3.0 ? v ah = 1.9v, v dd = 3.0v i ieh - 4.0 6.0 ? v ah = 3.2v, v dd = 5.0v all other inputs, high or low - - 0 0 ? - output currents: lflag, dflag sink i ofl -1.3 -2.0 - ma v out = 0.5v, v dd = 3.0v i ofl -3.2 -4.0 - ma v out = 0.5v, v dd = 5.0v lflag source - 0 0 - ma open drain output dflag source i ofh 1.0 1.8 - ma v out = 2.5v, v dd = 3.0v i ofh 2.8 3.6 - ma v out = 4.5v, v dd = 5.0v f cko sink i ocl -1.3 -2.0 - ma v out = 0.5v, v dd = 3.0v i ocl -3.2 -4.0 - ma v out = 0.5v, v dd = 5.0v f cko source i och 1.3 2.0 - ma v out = 2.5v, v dd = 3.0v i och 3.2 4.0 - ma v out = 4.5v, v dd = 5.0v txd/miso: sink i oml -1.5 -2.4 - ma v out = 0.5v, v dd = 3.0v i oml -3.8 -4.8 - ma v out = 0.5v, v dd = 5.0v source i omh 1.5 2.4 - ma v out = 2.5v, v dd = 3.0v i omh 3.8 4.8 - ma v out = 4.5v, v dd = 5.0v 7366r-041906-5 transient characteristics . (t a = -25?c to +85?c, v dd = 5v ?10%) parameter symbol min. value max.value unit remarks (see fig. 2) sck high pulse width t ch 100 - ns - sck low pulse width t cl 100 - ns - ss/ set up time t csl 100 - ns - ss/ hold time t csh 100 - ns - quadrature mode (see fig. 5, 7 & 8 ) f cki high pulse width t 1 12 - ns - f cki pulse width t 2 12 - ns - f cki frequency f fck - 40 mhz - effective filter clock f f period t 3 25 - ns t 3 = t 1 +t 2 , mdr0 <7> = 0 t 3 50 - ns t 3 = 2(t 1 +t 2 ), mdr0 <7> = 1 effective filter clock f f frequency f f - 40 mhz f f = 1/ t 3 quadrature separation t 4 26 - ns t 4 > t 3 quadrature clock pulse width t 5 52 - ns t 5 3 2 t3 quadrature clock frequency f qa , f qb - 9.6 mhz f qa = f qb < 1/4t 3 quadrature clock to count delay t q1 4t 3 5t 3 - - x1 / x2 / x4 count clock pulse width t q2 12 - ns t q2 = (t 3) /2 index input pulse width ti d 32 - ns t id > t 4 index set up time ti s - 5 ns - index hold time ti h - 5 ns - quadrature clock to t fl 4.5t 3 5.5t 3 ns - dflag/ or lflag/ delay dflag/ output width t fw 26 - ns t fw = t 4
parameter symbol min. value max.value unit remarks non-quadrature mode (see fig. 6 & 9) clock a - high pulse width t 6 12 - ns - clock a - low pulse width t 7 12 - ns - direction input b set-up time t 8s 12 - ns - direction input b hold time t 8h 10 - ns - clock frequency (non-mod-n) f a - 40 mhz f a = (1/(t 6 + t 7 )) clock to dflag/ or t 9 20 - ns - lflag/ delay dflag/ output width t 10 12 - ns t 10 = t 7 transient characteristics . (t a = -25?c to +85?c, v dd = 3.3v ?10%) parameter symbol min. value max.value unit remarks (see fig. 2) sck high pulse width t ch 120 - ns - sck low pulse width t cl 120 - ns - ss/ set up time t csl 120 - ns - ss/ hold time t csh 120 - ns - quadrature mode (see fig. 5, 7 & 8) f cki high pulse width t 1 24 - ns - f cki pulse width t 2 24 - ns - f cki frequency f fck - 20 mhz - effective filter clock ff period t 3 50 - ns t 3 = t 1 +t 2 , mdr0 <7> = 0 t 3 100 - ns t 3 = 2(t 1 +t 2 ), mdr0 <7> = 1 effective filter clock f f frequency f f - 20 mhz f f = 1/ t 3 quadrature separation t 4 52 - ns t 4 > t 3 quadrature clock pulse width t 5 105 - ns t 5 3 2 t3 quadrature clock frequency f qa , f qb - 4.5 mhz f qa = f qb < 1/4t 3 quadrature clock to count delay t q1 4t 3 5t 3 - - x1/x2/x4 count clock pulse width t q2 25 - ns t q2 = (t 3) /2 index input pulse width ti d 60 - ns t id > t 4 index set up time ti s - 10 ns - index hold time ti h - 10 ns - quadrature clock to t fl 4.5t 3 5.5t 3 ns - dflag/ or lflag/ delay dflag/ output width t fw 52 - ns t fw = t 4 non-quadrature mode (see fig. 6 & 9) clock a - high pulse width t 6 24 - ns - clock a - low pulse width t 7 24 - ns - direction input b set-up time t 8s 24 - ns - direction input b hold time t 8h 24 - ns - clock frequency (non-mod-n) f a - 40 mhz f a = (1/(t 6 + t 7 )) clock to dflag/or t 9 40 - ns - lflag/ delay dflag/ output width t 10 24 - ns t 10 = t 7 7366r-041906-6
note 1. the spi port of the host mcu must be set up as follows: 1. spi master mode. 2. sck idle state = low 3. clock edge for mosi data shift = high to low 4. clock edge for input data (miso) sample by the processor = low to high (or bit middle) note 2. to conform with the multibyte transmission protocol of LS7366R, the ss/ output port of the mcu may require direct manipulation by the application program. figure 2. spi timings 7366r-041906-7 t csh t cl t ch t csl msb lsb ss/ sck mosi miso high impedance ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
d7 d6 d5 d4 d3 d3 d2 d1 d0 d2 d6 d5 d7 d4 x x x random data x x x d1 d0 x ss/ sck mosi miso bit # 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 start of new command rd mdr1 data wr mdr1 t csl bit # 7 6 5 4 3 2 1 0 t ch t cl tri-state d7 d6 d5 d4 d3 d3 d2 d1 d0 d2 d6 d5 d7 d4 x x x x x x d1 d0 ss/ sck mosi miso bit # 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 rd cntr t csi bit # 7 6 5 4 3 2 1 0 byte 1 byte 0 clr str random data 7 6 5 4 3 2 1 0 tri-state note: write to mdr1 followed by read from mdr1 operation 7366r-041906-8 figure 3. wr mdr1 - rd mdr1 figure 4. rd cntr - clr str figure 5. f cki , a, b and index note 1. synchronous index coincident with both a and b high. note 2. synchronous index coincident with both a and b low.. note 3. f f is the internal effective filter clock . note: read cntr (in 2-byte configuration) followed by clr str operation . f cki t 1 t 2 f f (note 4) (mdr0 <7> = 0) f f (note 4) (mdr0 <7> = 1) a b index/ t 3 t 3 t 5 t 5 t 4 t 4 t 4 t 4 note 1 note 2 t id t is t ih t is t ih
7366-050106-9 down up down t 6 t 7 t 8 s t 8h up down a b x4_clk x2_clk x1_clk (see note) (see note) (see note) t q1 t q2 note: x1, x2, and x4 clks are internal up/down clocks derived from filtered and decoded quadrature clocks. figure 7. a/b quadrature clocks vs internal count clocks note: cntr values are indicated in 3-byte mode figure 8. quadrature clocks vs flag outputs figure 6. count (a) and direction (b) inputs in non-quadrature mode up down a b x4_clk t fl cntr dflg/ lflg/ t fl cy cmp bw fffffc fffffd fffffe ffffff ffffff fffffe fffffd 000000 000001 000002 000001 000000 (shown with dtr = 000oo1) t fw
7366r-050106-10 note: cntr values are indicated in 2-byte mode figure 9. single-cycle, non-quadrature note: cntr values are indicated in 1-byte mode figure 10. modulo-n, non-quadrature note: cntr values are indicated in 1-byte mode figure 11. range-limit, non-quadrature indx/ dflg/ cntr a b ffffffc ffffffd ffffffe fffffff 0 2 1 0 fffffff cy t 9 t 10 t 11 cntr disabled cntr disabled (shown with dtr = 2) cntr enabled (load cntr) up down dflag/ cntr a b 000000 000002 000001 000000 cmp (shown with dtr = 3) bw up down 000001 000002 000003 000003 000000 000001 000002 000001 dflag/ cntr a b 000003 000002 000001 cmp (shown with dtr = 3) up down 000000 000001 000002 000000 bw bw bw cmp cmp cmp
7366r-041906-11 figure 12. LS7366R block diagram clock control io data control filter mux mode control io shift reg ? flag mask str mdr1 mdr0 otr cntr dtr (32) i r load clr rd wr clr rd flags wr por en_mdr1 en_otr por en_dtr (32) (32) (8) (8) (8) (5) en_cntr cmpr flag logic sck rxd/mosi ss/ a b index/ f ck i f cko v dd v ss por gen por flags lflag/ txd/mis0 (8) mdr0<7> (v-) (v+) spi_xmit/ cnt_en v+ v+ (8) en_str en_dtr en_cntr en_otr en_mdr0 en_mdr1 en_str (8) 6 buffer load 8 5 7 4 12 11 10 2 1 13 14 3 load en_mdr0 buffer dflag/ 9
LS7366R 1m w 40mhz 15pf 15pf f cko f cki encoder index/ a b 1 2 10 12 11 vss ss/ sck int/ rxd txd sck ss/ gnd mosi miso lflag/ 8 6 7 5 4 +v +v +v v dd v dd mcu 3 7366r-042106-12 figure 14. pic18c to LS7366R figure 13. general i/o connections LS7366R miso mosi sck ss/ pic18cxxx rc3/sck rc4/sdi rc5/sdo ra5 4 5 6 7
;sample routines for pic18cxxx interface /***********************************************************************************************************************/ ;initialize pic18cxxx portc in ls7366 compatible spi ;setup: master mode, sck idle low, sdi/sdo datashift on high to low transition of sck ;ss/ assertion/deassertion made with direct manipulation of ra5 ;initialize portc clrf portc ;clear portc clrf latc ;clear data latches movlw 0x10 ;rc4 is input, rc3 & rc5 are outputs movwf trisc ;rc3=clk, rc4=sdi, rc5=sdo bcf trisa, 5 ;ra5=output bsf porta, 5 ;ra5=ss/=high clrf sspstat ;smp=0 => sdi data sampled at mid-data bsf sspstat, cke ;cke=1 => data shifts on active to idle sck transitions movlw 0x21 ;spi mode initialization data movwf sspcon ;master mode, clk/16, ckp=0 => clk idles low ;data shifted on active to idle clk edge /***********************************************************************************************************************/ ; wr_mdr0 bsf porta, 5 ;ss/=high bcf porta, 5 ;ss/=low movlw 0x88 ;ls7366 wr_mdr0 command movwf sspbuf ;transmit command byte loop1 btfss sspstat, bf ;transmission complete with bf flag set? bra loop1 ;no, check again movf sspbuf, w ;dummy read to clear bf flag. movlw 0xa3 ;mdr0 data:fck/2, synchronous index. index=rcntr, x4 movwf sspbuf ;transmit data loop2 btfss sspstat, bf ;bf set? bra loop2 ;no, check again bsf porta, 5 ;ss/=high /***********************************************************************************************************************/ ;rd_mdr0 bsf porta, 5 ;ss/=high bcf porta, 5 ;ss/=low movlw 0x48 ;ls7366 rd_mdr0 command movwf sspbuf ;transmit command byte loop1 btfss sspstat, bf ;bf flag set? bra loop1 ;no, check again movwf sspbuf ;send dummy byte to generate clock & receive data loop2 btfss sspstat, bf ;bf flag set? bra loop2 ;no, check again movf sspbuf, w ;recieved data in wreg. movwf rxdata ;save received data in ram bsf porta, 5 ;ss/=high 7366r-041906-13

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