integrated circuit systems, inc. ics93727 preliminary product preview 0711b?10/10/02 block diagram ddr phase lock loop zero delay clock buffer (patent pending) pin configuration recommended application: ddr zero delay clock buffer product description/features: low skew, low jitter pll clock driver i 2 c for functional and output control spread spectrum tolerant inputs input to output skew control (r fix , r step ) (patent pending) northbridge reference clock for output delay control switching characteristics: peak - peak jitter (66mhz): <120ps peak - peak jitter (>100mhz): <75ps cycle - cycle jitter (66mhz):<120ps cycle - cycle jitter (>100mhz):<65ps output - output skew: <100ps output rise and fall time: 450ps - 950ps duty cycle: 49% - 51% functionality clk_in pll sclk r step r fix sdata l c ddrc9 ddrt9 fs_prog0 cs_prog (1:0) ddrc(8:0) ddrt(8:0) ddr9 step skew programming block fix skew programming block step skew programming block fix skew programming block step skew programming block pll control logic ddr(8:0) step skew programming block product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and o ther specifications are subject to change without notice. avdd clkin ddrt ddrc fb 2.5v (nom) average voltage > 0.4v on 2.5v (nom) average voltage < 0.4v hi z hi z hi z off gnd l l h l bypassed/off gnd h h l h bypassed/off inputs outputs pll state in phase with clkin gnd 1 48 gnd ddrc0 2 47 ddrc5 ddrt0 3 46 ddrt5 vdd2.5 4 45 vdd2.5 ddrt1 5 44 ddrt6 ddrc1 6 43 ddrc6 gnd 7 42 gnd gnd 8 41 gnd ddrc2 9 40 ddrc7 ddrt2 10 39 ddrt7 vdd2.5 11 38 vdd2.5 sclk 12 37 sdata clk_in 13 36 cs_prog1* **fs_prog0 14 35 r fix vdd2.5 15 34 vdd2.5 avdd 16 33 r step agnd 17 32 cs_prog0** gnd 18 31 gnd ddrc3 19 30 ddrc8 ddrt3 20 29 ddrt8 vdd2.5 21 28 vdd2.5 ddrt4 22 27 ddrt9 ddrc4 23 26 ddrc9 gnd 24 25 gnd 48-ssop * internal pull-up resistor ** internal pull-down resistor ics93727
2 ics93727 preliminary product preview 0711b?10/10/02 pin descriptions pin pin pin # name type 1 gnd pwr ground pin. 2 ddrc0 out "complementary" clock of differential pair output. 3 ddrt0 out "true" clock of differential pair output. 4 vdd2.5 pwr power supply, nominal 2.5v 5 ddrt1 out "true" clock of differential pair output. 6 ddrc1 out "complementary" clock of differential pair output. 7 gnd pwr ground pin. 8 gnd pwr ground pin. 9 ddrc2 out "complementary" clock of differential pair output. 10 ddrt2 out "true" clock of differential pair output. 11 vdd2.5 pwr power supply, nominal 2.5v 12 sclk in clock pin of i2c circuitry 5v tolerant 13 clk_in in reference clock input. 14 **fs_prog0 in latch input pin to change byte 1 bit 7 fine skew programming default polarity (pulling this bit low will set ddr output to be advance vs the input). 15 vdd2.5 pwr power supply, nominal 2.5v 16 avdd pwr 2.5v analog power pin for core pll 17 agnd pwr analog ground pin for core pll 18 gnd pwr ground pin. 19 ddrc3 out "complementary" clock of differential pair output. 20 ddrt3 out "true" clock of differential pair output. 21 vdd2.5 pwr power supply, nominal 2.5v 22 ddrt4 out "true" clock of differential pair output. 23 ddrc4 out "complementary" clock of differential pair output. 24 gnd pwr ground pin. 25 gnd pwr ground pin. 26 ddrc9 out "complementary" clock of differential pair output. 27 ddrt9 out "true" clock of differential pair output. 28 vdd2.5 pwr power supply, nominal 2.5v 29 ddrt8 out "true" clock of differential pair output. 30 ddrc8 out "complementary" clock of differential pair output. 31 gnd pwr ground pin. 32 cs_prog0** in latch input pin to change byte 3 bit 5 coarse skew programming default (pulling this bit high wi ll advance the ddr output vs the input, refer to table 1 for timing details). 33 rstep in exnterna pull-down resistor can be set on this pin to program input vs ddr clocks skew. 34 vdd2.5 pwr power supply, nominal 2.5v 35 rfix in exnterna pull-down resistor can be set on this pin to program input vs ddr clocks skew. 36 cs_prog1* in latch input pin to change byte 3 bit 7 coarse skew programming default (pulling this bit high wi ll advance the ddr output vs the input, refer to table 1 for timing details). 37 sdata i/o data pin for i2c circuitry 5v tolerant 38 vdd2.5 pwr power supply, nominal 2.5v 39 ddrt7 out "true" clock of differential pair output. 40 ddrc7 out "complementary" clock of differential pair output. 41 gnd pwr ground pin. 42 gnd pwr ground pin. 43 ddrc6 out "complementary" clock of differential pair output. 44 ddrt6 out "true" clock of differential pair output. 45 vdd2.5 pwr power supply, nominal 2.5v 46 ddrt5 out "true" clock of differential pair output. 47 ddrc5 out "complementary" clock of differential pair output. 48 gnd pwr ground pin. description
3 ics93727 preliminary product preview 0711b?10/10/02 i 2 c table: reserved register pin # name 0 1 pwd bit 7 - - (reserved) r/w - - 1 bit 6 - - (reserved) r/w - - 1 bit 5 - - (reserved) r/w - - 1 bit 4 - - (reserved) r/w - - 1 bit 3 - - (reserved) r/w - - 1 bit 2 - - (reserved) r/w - - 1 bit 1 - - (reserved) r/w - - 1 bit 0 - - (reserved) r/w - - 1 i 2 c table: fix delay control register pin # name 0 1 pwd bit 7 - - fix delay polarity selection r/w ddr outputs advance ddr outputs delay latch bit 6 - - fix delay enable r/w enable bypass 0 bit 5 - - (reserved) r/w - - 1 bit 4 - - (reserved) r/w - - 1 bit 3 - - (reserved) r/w - - 1 bit 2 - - (reserved) r/w - - 1 bit 1 - - (reserved) r/w - - 1 bit 0 - - (reserved) r/w - - 1 i 2 c table: output drive strength control register pin # name 0 1 pwd bit 7 - - (reserved) r/w - - 0 bit 6 - - ddr output driver strength r/w 1x 1.5x 0 bit 5 - - (reserved) r/w - - 0 bit 4 - - (reserved) r/w - - 0 bit 3 - - (reserved) r/w - - 0 bit 2 - - (reserved) r/w - - 0 bit 1 - - (reserved) r/w - - 0 bit 0 - - (reserved) r/w - - 0 i 2 c table: step delay control register pin # name pwd bit 7 - - r/w latch bit 6 - - r/w 0 bit 5 - - r/w latch bit 4 - - r/w 0 bit 3 - - r/w 0 bit 2 - - r/w 0 bit 1 - - r/w 0 bit 0 - - r/w 0 bit control byte 1 control function type bit control byte 0 affected pin control function type affected pin type bit control byte 3 affected pin control function type byte 2 affected pin control function bit control step advance skew programming for ddr outputs step delay skew programming for ddr outputs see table 1 see table 2
4 ics93727 preliminary product preview 0711b?10/10/02 i 2 c table: step delay control register pin # name pwd bit 7 - - r/w 0 bit 6 - - r/w 0 bit 5 - - r/w 0 bit 4 - - r/w 0 bit 3 - - r/w 0 bit 2 - - r/w 0 bit 1 - - r/w 0 bit 0 - - r/w 0 i 2 c table: output control register pin # name 0 1 pwd bit 7 2, 3 ddrc0, ddrt0 output enable r/w stop run 1 bit 6 5, 6 ddrc1, ddrt1 output enable r/w stop run 1 bit 5 9, 10 ddrc2, ddrt2 output enable r/w stop run 1 bit 4 19, 20 ddrc3, ddrt3 output enable r/w stop run 1 bit 3 22, 23 ddrc4, ddrt4 output enable r/w stop run 1 bit 2 27,26 ddrc9, ddrt9 output enable r/w stop run 1 bit 1 - - (reserved) r/w - - 1 bit 0 - - (reserved) r/w - - 1 i 2 c table: output control register pin # name 0 1 pwd bit 7 - - (reserved) r/w - - 1 bit 6 - - (reserved) r/w - - 1 bit 5 - - (reserved) r/w - - 1 bit 4 30, 29 ddrc8, ddrt8 output enable r/w stop run 1 bit 3 40, 39 ddrc7, ddrt7 output enable r/w stop run 1 bit 2 44, 43 ddrc6, ddrt6 output enable r/w stop run 1 bit 1 47, 46 ddrc5, ddrt5 output enable r/w stop run 1 bit 0 - - (reserved) r/w - - 1 i 2 c table: reserved register pin # name 0 1 pwd bit 7 - - (reserved) r/w - - 1 bit 6 - - (reserved) r/w - - 1 bit 5 - - (reserved) r/w - - 1 bit 4 - - (reserved) r/w - - 1 bit 3 - - (reserved) r/w - - 1 bit 2 - - (reserved) r/w - - 1 bit 1 - - (reserved) r/w - - 1 bit 0 - - (reserved) r/w - - 1 byte 4 affected pin control function byte 7 affected pin control function byte 5 affected pin control function byte 6 step delay skew programming for ddr 9 outputs see table 2 type bit control type bit control affected pin control function type bit control step delay skew programming for ddr (8:0) outputs see table 2 bit control type
5 ics93727 preliminary product preview 0711b?10/10/02 table 1: step advance skew programming bit7 bit5 csp1 csp0 0000 0 0 0 0001 -200 -250 -350 0010 -400 -500 -700 0011 -600 -750 -1050 0100 -800 -1000 -1400 0101 -1000 -1250 -1750 0110 -1200 -1500 -2100 0111 -1400 -1750 -2450 1000 -1600 -2000 -2800 1001 -1800 -2250 -3150 1010 -2000 -2500 -3500 1011(reserved)(reserved)(reserved) 1100(reserved)(reserved)(reserved) 1101(reserved)(reserved)(reserved) 1110(reserved)(reserved)(reserved) 1111(reserved)(reserved)(reserved) byte 3 bit6 bit4 bit r step =1k r step =2k r step =3k fix delay programmi ng - ddr vs clk_in -1000 -800 -600 -400 -200 0 200 400 600 800 1000 123456 r fi x (k ? ) delay(ps) advancing ddr outputs delaying ddr outputs table 2: step delay skew programming bit7/3 bit5/1 csp1 csp0 0000 0 0 0 0001 200 250 350 0010 400 500 700 0011 600 750 1050 0100 800 1000 1400 0101 1000 1250 1750 0110 1200 1500 2100 0111 1400 1750 2450 1000 1600 2000 2800 1001 1800 2250 3150 1010 2000 2500 3500 1011(reserved)(reserved)(reserved) 1100(reserved)(reserved)(reserved) 1101(reserved)(reserved)(reserved) 1110(reserved)(reserved)(reserved) 1111(reserved)(reserved)(reserved) bit byte 3 byte 4 r step =1k r step =2k r step =3k bit6/2 bit4/0
6 ics93727 preliminary product preview 0711b?10/10/02 absolute maximum ratings supply voltage (vdd & avdd). . . . . . . . . . . -0.5v to 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +85c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. parameter symbol conditions min typ max unit s analog / core supply voltage av dd 2.3 2.5 2.7 v input voltage level v in v output differential pair crossing voltage v oc 1.05 1.25 1.45 v recommended operating conditions t a = 0 - 70c; supply voltage av dd , v dd = 2.5 v +/-0.2v (unless otherwise stated) electrical characteristics - input / supply / common output parameters t a = 0 - 70c; supply voltage v dd = 2.5 v +/-0.2v (unless otherwise stated) parameter symbol conditions min typ max unit s input high current i ih v i = v dd or gnd ma input low current i il v i = v dd or gnd ma i dd2. 5 c l = 0 pf at 133 mhz 245 300 ma i ddpd c l = 0 pf 200 a output high current i oh v dd = 2.3v, v out = 1v -43 -18 ma output high current i ol v dd = 2.3v, v out = 1.2v 26 43 ma high impedance output current i oz v dd = 2.7v, v out = v dd or gnd 10 a input clamp voltage v ik iin = -18 ma; v v dd = min to max, i oh = -1ma 2.1 2.42 v v dd = 2.3v, i oh = -12ma 1.87 v v ol v dd = min to max, i oh = 1ma 0.04 0.1 v v dd = 2.3v, i oh = 12ma 0.35 0.6 v input capacitance 1 c in v i = v dd or gnd pf output capacitance 1 c out v i = v dd or gnd 3 pf 1. guaranteed by design, not 100% tested in production. operating supply current high-level output voltage v oh low-level output voltage
7 ics93727 preliminary product preview 0711b?10/10/02 parameter symbol conditions min typ max unit s operating clock frequency 1 freq op 66 170 mhz input clock duty cycle 1 d tin 40 60 % clock stabilization 1 t stab from v dd = 2.5v to 1% target frequency 100 s t a = 0 - 70c; supply voltage av dd , v dd = 2.5 v +/-0.2v (unless otherwise stated) timing requirements 1. guaranteed by design, not 100% tested in production. switching characteristics t a = 0 - 70c; supply voltage v dd = 2.5 v +/-0.2v (unless otherwise stated) parameter symbol conditions min typ max units 66 mhz 120 100 / 125 / 133 / 167 mhz 75 66 mhz 50 110 100 / 125 / 133 / 167 mhz 35 65 phase error 1 t pe output to output skew 1 t skew low-to-high level propagation delay time, bypass mode 1 t plh clk_in to any output, load = 120 ? 12pf 44.56ns duty cycle (differential) 1,3 d c no loads, 66 mhz to 167 mhz 49 50 51 % rise time, fall time 1 t r , t f single-ended 20 - 80 %; load = 120 ? + 12 pf 450 550 950 ps 1. guaranteed by design, not 100% tested in production. 2. refers to transistion on non-inverting period. 3. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle = t wh / t c , where the cycle time (t c ) decreases as the frequency increases. see programmable information absolute jitter 1 t jabs ps cycle to cycle jitter 1,2 t c-c ps
8 ics93727 preliminary product preview 0711b?10/10/02 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. controller (host) sends the write address d4 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 6 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d5 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 6 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver ) start bit address d4 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack stop bit how to write: controller (host) ics (slave/receiver ) start bit address d5 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack stop bit how to read:
9 ics93727 preliminary product preview 0711b?10/10/02 ordering information ics93727 y f-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp - t min max min max a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 basic 0.025 basic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n a0808 variations min max min max 48 15.748 16.002 .620 .630 jedec mo- 118 doc# 10- 0034 6/ 1/ 00 rev b symbol see variations see variations in millimeters common dimensions in inches common dimensions see variations n d mm. d (inch) see variations 300 mil ssop index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l
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