104 high street, west wickham, london. br4. 0nf. england. 05/08/2005 ph: +44 208 325 1062, fax: +44 208 181 6751 page 1 of 4 www.fiduciauk.com sales@fiduciauk.com product specification monochrome lcd module part number : FDG128064D description : 64x128graphic revision : rev a approval for specification only approval for sample only approval for mass pr oduction approval for pre-production x
FDG128064D ( 128 dots x 64 dots ) features mechanical data built-in controller (ks0107 or equivalent) item dimensions unit +5 v power supply module size (w x h x t) 93.0 x 70.0 x 11.8 mm 1/64 duty cycle viewing area ( w x h ) 70.7 x 40.0 mm 8-bit parallel interface active area ( w x h ) 66.52 x 33.24 mm 4.2 v led forward voltage dot size ( w x h ) 0.48 x 0.48 mm dot pitch ( w x h ) 0.52 x 0.52 mm interface pin connections absolute maximum ratings no. symbol level function item symbol min. typ. max. unit 1v ss 0v power supply ground supply voltage for logic v dd -v ss 0 - 7 v 2v dd 5v power supply voltage supply voltage for lcd drive v dd -v o 0 - 14 v 3v o - contrast adjustment voltage input voltage v i vss - v dd v 4 d/i h/l h : data, l : instruction code 5 r/w h/l h : read / l : wrtie electrical characteristics 6 e h l enable signal item symbol condition min. typ. max. unit 7~14 db0~db7 h/l data bus line supply voltage for logic v dd -v ss - 4.5 5 5.5 v 15 cs1 h chip select signal for ic1 supply voltage for lcd v dd -v o v dd =5v ta=25 7.6 8.3 9.2 v 16 cs2 h chip select signal for ic2 supply current i dd v dd =5v - 4.5 10 ma 17 /res l reset signal input "high" level v ih - 2.2 - v dd v 18 vout - power supply voltage for lcd voltage "low" level v il - - - 0.6 v 19 k 0v led power (-) output "high" level v oh - 2.4 - - v 20 a 4.2v led power (+) voltage "low" level v ol - - - 0.4 v external dimensions
FDG128064D ( 128 dots x 64 dots ) timing characteristics timing characteristics timing characteristics timing characteristics item symbol min. typ. max. unit. fig e cycle time t cyc 1000 - - ns 1,2 e high level width p weh 450 - - ns 1,2 e low level width p wel 450 - - ns 1,2 e rise time t r - - 25 ns 1,2 e fall time t f - - 25 ns 1,2 address setup time t as 140 - - ns 1,2 address hold time t ah 10 - - ns 1,2 data setup time t dsw 200 - - ns 1 data delay time t ddr - - 320 ns 2 data hold time write t dhw 10 - - ns 1 data hold time read t dhr 20 - - ns 2 block diagram block diagram block diagram block diagram
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