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AMMP-6430 27-32 ghz 0.5w power amplifer in smt package data sheet description the AMMP-6430 mmic is a broadband 1w power amplifer in a surface mount package designed for use in transmitters that operate in various frequency bands between 27ghz and 32ghz. at 30ghz, it provides 29dbm of output power (p-1db) and 19db of small-signal gain from a small easy-to-use device. the device has input and output matching circuitry for use in 50? environ - ments. the AMMP-6430 also integrates a temperature compensated rf power detection circuit that enables power detection of 0.3v/w. dc bias is simple and the device operates on widely available 5v for current supply (negative voltage only needed for vg). it is fabricated in a phemt process for exceptional power and gain perfor - mance. pin connections (top view) 1 2 3 7 5 6 4 8 gnd base package pi n 1 v gg 2 v dd 3 d et _o 4 r f_ou t 5 d et _r 6 v dd 7 v gg 8 r f_ in fu ncti on rohs-exemption please refer to hazardous substances table on page 11. features ? wide frequency range 27-32ghz ? half watt output power ? 50 match on input and output ? esd protection (50v mm, and 150v hbm) ? specifcations (vd=5v, idsq=650ma) ? frequency range 27 to 32 ghz ? small signal gain of 20db ? output power @p-1 of 27dbm (typ.) ? input/output return-loss of -10db applications ? microwave radio systems ? satellite vsat, dbs up/down link ? lmds & pt-pt mmw long haul ? broadband wireless access (including 802.16 and 802.20 wimax) ? wll and mmds loops ? commercial grade military note: 1. this mmic uses depletion mode phemt devices. negative supply is used for dc gate biasing. attention: observe precautions for handling electrostatic sensitive devices. esd machine model (class a): 50v esd human body model (class 0): 150v refer to avago application note a004r: electrostatic discharge damage and control.
2 absolute maximum ratings [1] symbol parameters [1] units value notes v d positive supply voltage v 6 2 v g gate supply voltage v -3 to 0.5 i dq drain current ma 700 p d power dissipation w 5.5 2, 3 p in cw input power dbm 23 2 t ch, max maximum operating channel temp. c +155 4, 5 t stg storage case temp. c -65 to +155 t max maximum assembly temp (20 sec max) c +260 notes: 1. operation in excess of any one of these conditions may result in permanent damage to this device. 2. combinations of supply voltage, drain current, input power, and output power shall not exceed pd. 3. when operate at this condition with a base plate temperature of 85 c, the median time to failure (mttf) is signifcantly reduced. 4. these ratings apply to each individual fet 5. junction operating temperature will directly afect the device mttf. for maximum life, it is recommended that junction temperatures be maintained at the lowest possible levels. dc specifcations/ physical properties [6] symbol parameters and test conditions units value i dq drain supply current (vd=5 v, vg set for id typical) ma 650 v g gate supply operating voltage (id(q) = 650 (ma)) v -1.1 r jc thermal resistance [6] (channel-to-base plate) c/w 16.8 t ch channel temperature c 139.6 notes: 6. assume snpb soldering to an evaluation rf board at 85 c base plate temperatures. worst case is at saturated output power when dc power consumption rises to 5.24w with 0.9w rf power delivered to load. power dissipation is 4.34w and the temperature rise in the channel is 72.9 c. in this condition, the base plate temperature must be remained below 82.1 c to maintain maximum operating channel temperature below 155 c. AMMP-6430 rf specifcations [1, 2, 3, 4] t a = 25 c, v dd = 5.0 v, i dq =650 ma, v g = -1.1v, z o =50? symbol parameters and test conditions units minimum typical maximum freq operational frequency ghz 27 32 gain small-signal gain [3, 4] freq = 27 ghz db 16 20 p -1db output power at 1db [3] gain compression dbm 26 27 oip3 output third order intercept point dbm 35 rl in input return loss db 10 rl out output return loss db 10 isolation reverse isolation db 43 notes: 1. small/large -signal data measured in packaged form on a 2.4-mm connecter based evaluation board at ta = 25 c. 2. this fnal package part performance is verifed by a functional test correlated to actual performance at one or more frequencies 3. specifcations are derived from measurements in a 50? test environment. 4. pre-assembly into package performance verifed 100% on-wafer published specifcations at frequencies=27, 30, and 32ghz 5. the gain and p1db tested at 27ghz guaranteed with measurement accuracy 1.5 db for gain and 1.6db for p1db.
3 0 5 10 15 20 25 30 10 15 20 25 30 35 40 45 frequency [ghz] -50 -30 s21[db] s12[db] -25 -20 -15 -10 -5 0 10 15 20 25 30 35 40 45 frequency [ghz] return loss [db] 0 5 10 15 20 25 30 35 24 25 26 27 28 29 30 31 32 33 34 frequency[ghz] p-1, p-3 [dbm], pae[%] p-1 pae, @p-1 p-3 pae, @p-3 -5 0 5 10 15 20 25 30 35 40 -25 -20 -15 -10 -5 0 5 10 15 20 pin [dbm] po[dbm], and, pae[%] 400 500 600 700 800 900 1000 1100 1200 1300 ids [ma] ip3[db m] 30 32 34 36 38 40 42 44 46 25 26 27 28 29 30 31 32 33 34 35 frequency [ghz] 0 2 4 6 8 10 24 26 28 30 32 34 36 frequency [ghz] noise figure [db] s12[db] s21[db] s11[db] s22[db] po ut (d bm ) pa e[ %] id (t ot al ) AMMP-6430 typical performance (data obtained from 2.4-mm connector based test fxture, and this data is including connecter loss, and board loss.) (t a = 25c, vdd=5v, idq=650ma, v g =-1.1 v, z in = z out = 50?) figure 6. typical noise figure figure 1. typical gain and reverse isolation figure 2. typical input & output return loss figure 4. typical pout, ids, and pae vs. pin at freq=30ghz figure 3. typical p-1 and pae figure 5. typical ip3 (third order intercept) @pin=-20dbm
4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 5 10 15 20 25 30 35 pout[dbm] det_r - det_o [v] 0.001 0.01 0.1 1 det_r - det_o [v] -25 -20 -15 -10 -5 0 15 20 25 30 35 40 frequency[ghz] s22[db] s22_20 s22_-40 s22_85 -25 -20 -15 -10 -5 0 15 20 25 30 35 40 frequency[ghz] s11[db] s11_20 s11_-40 s11_85 20 22 24 26 28 30 32 24 26 28 30 32 34 36 frequency [ghz] p-1 [dbm] p-1_85de g p-1_20de g p-1_-40deg 10 15 20 25 30 15 20 25 30 35 40 frequency[ghz] s21[db] s21_20 s21_-40 s21_85 figure 7. typical detector voltage vs. output power @30ghz figure 8. typical s22 over temperature figure 10. typical p-1 over temperature figure 9. typical s11 over temperature figure 11. typical gain over temperature
5 typical scattering parameters [1] (t a = 25c, vdd =5 v, i dq = 650 ma, z in = z out = 50?) freq [ghz] s11 s21 s12 s22 db mag phase db mag phase db mag phase db mag phase 1 -0.077 0.991 -30.672 -60.460 0.001 156.200 -81.678 8.24e-05 13.553 -0.075 0.991 -31.001 2 -0.244 0.972 -61.135 -52.134 0.002 7.598 -79.982 1.00e-04 -1.433 -0.218 0.975 -61.826 3 -0.507 0.943 -91.481 -55.059 0.002 -178.810 -78.816 1.15e-04 -26.240 -0.450 0.949 -92.759 4 -0.857 0.906 -121.770 -62.791 0.001 135.030 -73.965 2.00e-04 -79.414 -0.847 0.907 -123.780 5 -1.286 0.862 -152.370 -43.769 0.006 72.309 -66.459 4.75e-04 -89.529 -1.465 0.845 -152.600 6 -1.834 0.810 176.860 -43.125 0.007 -55.096 -61.854 8.08e-04 -141.380 -1.593 0.832 177.570 7 -2.497 0.750 146.160 -47.710 0.004 -138.310 -59.371 1.08e-03 -174.860 -2.056 0.789 145.900 8 -3.218 0.690 115.480 -50.926 0.003 167.090 -58.859 1.14e-03 151.750 -2.614 0.740 114.510 9 -3.952 0.634 84.820 -48.273 0.004 127.030 -51.689 2.60e-03 128.260 -3.234 0.689 82.673 10 -4.734 0.580 54.869 -47.156 0.004 82.462 -49.760 3.25e-03 76.311 -3.919 0.637 51.597 11 -5.372 0.539 26.213 -46.361 0.005 37.278 -47.391 4.27e-03 33.764 -4.545 0.593 21.330 12 -5.892 0.507 -1.577 -49.213 0.003 16.009 -48.433 3.79e-03 -0.070 -5.413 0.536 -7.654 13 -6.334 0.482 -28.136 -43.321 0.007 -18.990 -47.536 4.20e-03 -31.732 -4.738 0.580 -29.552 14 -6.785 0.458 -52.977 -49.276 0.003 -50.499 -50.113 3.12e-03 -62.027 -4.740 0.579 -63.489 15 -7.246 0.434 -75.942 -48.968 0.004 -66.480 -47.510 4.21e-03 -80.734 -5.196 0.550 -93.519 16 -7.822 0.406 -95.873 -50.759 0.003 79.915 -49.051 3.53e-03 -117.620 -5.850 0.510 -122.580 17 -8.056 0.396 -113.940 -31.831 0.026 37.293 -53.232 2.18e-03 -135.710 -6.891 0.452 -151.530 18 -8.011 0.398 -130.700 -19.650 0.104 -11.371 -54.404 1.90e-03 -136.240 -8.605 0.371 179.660 19 -8.003 0.398 -150.530 -8.565 0.373 -65.975 -52.389 2.40e-03 -100.790 -11.491 0.266 151.610 20 -8.086 0.394 -172.380 2.944 1.404 -130.730 -45.317 5.42e-03 -135.360 -15.971 0.159 128.630 21 -10.147 0.311 160.910 16.205 6.460 130.360 -44.518 5.94e-03 179.470 -32.906 0.023 80.680 22 -10.495 0.299 156.560 19.584 9.533 -6.027 -44.477 5.97e-03 146.120 -18.247 0.122 -170.070 23 -12.051 0.250 132.580 19.712 9.674 -99.417 -44.466 5.98e-03 129.370 -18.242 0.122 169.400 24 -15.378 0.170 122.010 20.404 10.476 174.220 -44.254 6.13e-03 102.170 -17.689 0.130 159.240 25 -16.652 0.147 127.100 20.339 10.398 91.597 -44.452 5.99e-03 63.925 -18.009 0.126 147.290 26 -17.111 0.139 113.670 19.880 9.862 16.978 -44.351 6.06e-03 36.998 -19.138 0.110 134.330 27 -23.026 0.071 100.620 20.040 10.046 -54.022 -45.333 5.41e-03 1.733 -23.261 0.069 137.140 28 -20.256 0.097 166.160 20.218 10.255 -128.560 -52.770 2.30e-03 -49.664 -18.834 0.114 161.640 29 -14.571 0.187 152.630 20.087 10.100 157.600 -49.161 3.48e-03 -75.571 -15.869 0.161 147.670 30 -13.363 0.215 128.640 19.761 9.729 85.669 -57.520 1.33e-03 15.834 -15.535 0.167 128.380 31 -11.814 0.257 107.980 19.830 9.807 10.808 -86.823 4.56e-05 -92.886 -14.211 0.195 109.870 32 -10.715 0.291 83.770 19.352 9.282 -68.718 -58.807 1.15e-03 -82.154 -13.484 0.212 82.184 33 -10.889 0.285 65.105 18.619 8.531 -150.100 -62.898 7.16e-04 92.036 -14.452 0.189 72.563 34 -11.417 0.269 41.069 18.093 8.028 124.500 -51.835 2.56e-03 -4.332 -15.301 0.172 53.869 35 -12.098 0.248 36.792 15.162 5.730 14.850 -52.719 2.31e-03 -115.640 -12.933 0.226 56.976 36 -11.897 0.254 24.365 7.101 2.265 -75.509 -58.568 1.18e-03 -48.164 -12.205 0.245 32.346 37 -11.125 0.278 13.967 -0.825 0.909 -142.060 -57.430 1.34e-03 -124.980 -12.066 0.249 15.583 38 -10.020 0.316 -0.758 -7.753 0.410 161.700 -52.497 2.37e-03 -154.340 -11.605 0.263 0.967 39 -9.222 0.346 -16.019 -13.812 0.204 110.760 -56.625 1.47e-03 116.090 -11.065 0.280 -12.574 40 -8.609 0.371 -32.089 -19.209 0.110 62.155 -55.294 1.72e-03 91.256 -10.402 0.302 -26.857 41 -8.175 0.390 -47.230 -24.340 0.061 13.948 -56.805 1.44e-03 1.705 -9.889 0.320 -40.144 42 -7.588 0.417 -62.593 -29.416 0.034 -31.372 -57.472 1.34e-03 -87.233 -9.293 0.343 -52.531 43 -7.587 0.417 -78.246 -34.254 0.019 -72.562 -64.193 6.17e-04 -136.190 -8.532 0.374 -64.211 44 -7.506 0.421 -89.361 -38.657 0.012 -112.560 -69.135 3.49e-04 -109.180 -7.654 0.414 -77.188 45 -7.332 0.430 -101.290 -43.475 0.007 -145.910 -60.759 9.16e-04 -29.843 -7.062 0.444 -90.938 note: 1. data obtained from a 2.4-mm connecter based module, and this data is including connecter loss, and board loss.
6 AMMP-6430 application and usage recommended quiescent dc bias condition for optimum power and linearity performances is vd=5 volts with vg (-1.1v) set for id=650 ma. minor improvements in per - formance are possible depending on the application. the drain bias voltage range is 3 to 5v. a single dc gate supply connected to vg will bias all gain stages. muting can be accomplished by setting vg to the pinch-of voltage vp. a simplifed schematic for the ammp6430 mmic die is shown in figure 12. the mmic die contains esd and over voltage protection diodes for vg, and vd terminals. the package diagram for the recommended assembly is shown in figure 13. in fnalized package form, esd diodes protect all possible esd or over voltage damages between vgg and ground, vgg and vdd, vdd and ground. typical esd diode current versus diode voltage for 11- connected diodes in series is shown in figure 14. under the recommended dc quiescent biasing condition at vds=5v, ids=650ma, vgg=-1v, typical gate terminal current is approximately 0.3ma. if an active biasing technique is selected for the ammp6430 mmic pa dc biasing, the active biasing circuit must have more than 10-times higher internal current that the gate terminal current. an optional output power detector network is also provided. the diferential voltage between the det-ref and det-out pads can be correlated with the rf power ( ) of s re f v v v v ? ? = de t emerging from the rf output port. the detected voltage is given by : where v ref is the voltage at the det_r port, v det is a voltage at the det_0 port, v ofs and is the zero-input- power ofset voltage. there are three methods to calculate v ofs : 1. v ofs can be measured before each detector measurement (by removing or switching of the power source and measuring v ref - v det ). this method gives an error due to temperature drift of less than 0.01db/50c. 2. v ofs can be measured at a single reference temperature. the drift error will be less than 0.25db. 3. v ofs can either be characterized over temperature and stored in a lookup table, or it can be measured at two temperatures and a linear ft used to calculate v ofs at any temperature. this method gives an error close to the method #1. the rf ports are ac coupled at the rf input to the frst stage and the rf output of the fnal stage. no ground wired are needed since ground connections are made with plated through-holes to the backside of the device. d v g v three stage 0.5w power amplifier in rf out rf det_ o det_r dq figure 12. simplied schematic for the mmic die
7 1 3 7 5 6 4 8 rf input rf output pf 100 v 5 v 8 . 0 ? pf 100 f 1 f 1 det_o det_r 50 pin 1 vgg 2 vdd 3 det_o 4 rf_out 5 det_r 6 vdd 7 vgg 8 rf_in function 2 figure 13. typical dc connection 5 5.5 6 6.5 7 7.5 8 voltage (v) 0 2 4 6 8 10 12 14 16 18 20 diode current [ma] |icomp(i_meter.amp1,0)| (ma) diode_current figure 14. typical esd diode current versus diode voltage for 11-connected diodes in series
8 ground vias should be solder filled figure 15a. suggested pcb land pattern and stencil layout figure 15c. stencil outline drawing(mm) figure 15b. pcb land pattern and stencil layouts the ammp packaged devices are compatible with high volume surface mount pcb assembly processes. the pcb material and mounting pattern, as defned in the data sheet, optimizes rf performance and is strongly rec - ommended. an electronic drawing of the land pattern is available upon request from avago sales & application engineering.
9 manual assembly ? follow esd precautions while handling packages. ? handling should be along the edges with tweezers. ? recommended attachment is conductive solder paste. please see recommended solder refow profle. neither conductive epoxy or hand soldering is recommended. ? apply solder paste using a stencil printer or dot placement. the volume of solder paste will be dependent on pcb and component layout and should be controlled to ensure consistent mechanical and electrical performance. ? follow solder paste and vendors recommendations when developing a solder refow profle. a standard profle will have a steady ramp up from room temperature to the pre-heat temp. to avoid damage due to thermal shock. ? packages have been qualifed to withstand a peak temperature of 260c for 20 seconds. verify that the profle will not expose device beyond these limits. 0 50 100 150 200 250 300 0 50 100 150 200 250 300 seconds temp (c) peak = 250 5c ramp 1 preheat ramp 2 reflow cooling melting point = 218c 0 50 100 150 200 250 300 0 5 0 100 150 200 250 300 seconds temp ( c) peak = 250 5?c ramp 1 preheat ramp 2 reow cooling melting point = 218?c figure 16. suggested lead-free refow profle for snagcu solder paste AMMP-6430 part number ordering information part number devices per container container AMMP-6430-blkg 10 antistatic bag AMMP-6430-tr1g 100 7 reel AMMP-6430-tr2g 500 7 reel a properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the pcb pads. the recommended stencil layout is shown in figure 15b. the stencil has a solder paste depo - sition opening approximately 70% to 90% of the pcb pad. reducing stencil opening can potentially generate more voids underneath. on the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the i/o pads. considering the fact that solder paste thickness will directly afect the quality of the solder joint, a good choice is to use a laser cut stencil composed of 0.127mm (5 mils) thick stainless steel which is capable of producing the required fne stencil outline. the most commonly used solder refow method is ac - complished in a belt furnace using convection heat transfer. the suggested refow profle for automated refow processes is shown in figure 16. this profle is designed to ensure reliable fnished joints. however, the profle indicated in figure 1 will vary among diferent solder pastes from diferent manufacturers and is shown here for reference only.
10 package, tape & reel, and ordering information top view dimensional tolerances: 0.002" [0.05mm] .0 11 back vi ew side view 3 2 1 4 8 back view 0.012 (0.30) 0.016 (0.40) 0.014 (0.365) 0.011 (0.28) 0.018 (0.46) 0.114 (2.90) 0.100 (2.54) 0.100 (2.54) 0.059 (1.5) 0.126 (3.2) 0.029 (0.75) 5 6 7 0.016 (0.40) 0.93 (2.36) 0.028 (0.70) dimensional tolerance for back view: 0.002" (0.05 mm) 1 2 3 7 6 5 4 8 .075 [1.91] .200 [5.08] .200 [5.08] ammp xxxx ywwdnn front view side view * notes: 1. dimensions are in inches [milimeters] 2. all grounds must be soldered to pcb rf 3. material is rogers ro4350, 0.010 thick 12 mm 4 mm ammp xxxx amm p xxxx ammp xxxx k o k o b o b o a o section b-b section a- a a o 0.30 0.05 b b a a 1.75 0.10 5.50 0.05 12.00 0.10 r 0.50 typ . ? 1.55 0.05 8.00 0.10 ? 1.50 (min.) 4.00 0.10 see note #2 2.00 0.05 a o : b o : k o : pitch: width : 5.30 5.30 2.20 8.00 12.00 ao bo ko min. 5.20 5.20 2.10 nom. 5.30 5.30 2.20 max. 5.40 5.40 2.30 notes: 1. a o and b o measured at 0.3 mm above base of pocket. 2. 10 pitches cumulative tolerance is 0.2 mm. 3. dimensions are in millimeters (mm).
names and contents of the toxic and hazardous substances or elements in the products part name lead (pb) (pb) mercur y (hg) hg cadmium (cd) cd hexavalent (cr(vi)) cr(vi) polybrominated biphenyl (pbb) pb b polybrominated diphenylether (pbde) pbde 100pf capacito r : indicates that the content of the toxic and hazardous substance in all the homogeneous materials of the part is below the concentration limit requirement as described in sj/t 11363-2006. : indicates that the content of the toxic and hazardous substance in at least one homogeneous material of the part exceeds the concentration limit requirement as described in sj/t 11363-2006. (the enterprise may further explain the technical reasons for the ?x? indicated portion in the table in accordance with the actual situations.) sj/t 11363-2006 sj/t 11363-2006 ? ? note: eu rohs compliant under ex emption clause of ?lead in elec tronic ceramic par ts (e .g . piezoele ct ronic devices) ? toxic and hazardous substances or elements for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countries. data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. av02-0623en - november 9, 2007

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