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? 1999 microchip technology inc. preliminary ds35008b-page 1 microcontroller core features: ? high-performance risc cpu ? only 35 single word instructions to learn ? all single cycle instructions except for program branches, which are two cycle ? operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle ? 2k x 14 words of program memory, 128 x 8 bytes of data memory (ram) ? interrupt capability ? eight level deep hardware stack ? direct, indirect, and relative addressing modes ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? brown-out detection circuitry for brown-out reset (bor) ? programmable code-protection ? power saving sleep mode ? selectable oscillator options ? low-power, high-speed cmos eprom technology ? fully static design ? in-circuit serial programming ? (icsp) ? wide operating voltage range: 2.5v to 5.5v ? high sink/source current 25/25 ma ? commercial, industrial and extended temperature ranges ? low-power consumption: - < 2 ma @ 5v, 4 mhz - 22.5 m a typical @ 3v, 32 khz -< 1 m a typical standby current pin diagram peripheral features: ? timer0: 8-bit timer/counter with 8-bit prescaler ? timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? capture, compare, pwm module ? capture is 16-bit, max. resolution is 12.5 ns, compare is 16-bit, max. resolution is 200 ns, pwm maximum resolution is 10-bit ? 8-bit multi-channel analog-to-digital converter ? synchronous serial port (ssp) with enhanced spi ? and i 2 c ? pic16c72a mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/ss/an4 v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7 rc6 rc5/sdo rc4/sdi/sda ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sdip, soic, ssop, windowed cerdip pic16c62b/72a 28-pin 8-bit cmos microcontrollers
pic16c62b/72a ds35008b-page 2 preliminary ? 1999 microchip technology inc. pin diagrams pic16c62b mclr /v pp ra0 ra1 ra2 ra3 ra4/t0cki ra5/ss v ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7 rc6 rc5/sdo rc4/sdi/sda ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sdip, soic, ssop, windowed cerdip key features picmicro? mid-range reference manual (ds33023) pic16c62b pic16c72a operating frequency dc - 20 mhz dc - 20 mhz resets (and delays) por, bor (pwrt, ost) por, bor (pwrt, ost) program memory (14-bit words) 2k 2k data memory (bytes) 128 128 interrupts 7 8 i/o ports ports a,b,c ports a,b,c timers 3 3 capture/compare/pwm modules 1 1 serial communications ssp ssp 8-bit analog-to-digital module 5 input channels
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 3 table of contents 1.0 device overview ............................................................................................................. ....................................... 5 2.0 memory organization ......................................................................................................... .................................... 7 3.0 i/o ports ................................................................................................................... ............................................ 19 4.0 timer0 module ............................................................................................................... ...................................... 25 5.0 timer1 module ............................................................................................................... ...................................... 27 6.0 timer2 module ............................................................................................................... ...................................... 31 7.0 capture/compare/pwm (ccp) module ............................................................................................ ................... 33 8.0 synchronous serial port (ssp) module ........................................................................................ ....................... 39 9.0 analog-to-digital converter (a/d) module .................................................................................... ........................ 49 10.0 special features of the cpu................................................................................................ ................................ 55 11.0 instruction set summary .................................................................................................... .................................. 67 12.0 development support........................................................................................................ ................................... 75 13.0 electrical characteristics ................................................................................................. ..................................... 81 14.0 dc and ac characteristics graphs and tables................................................................................ ................. 103 15.0 packaging information...................................................................................................... .................................. 105 appendix a: revision history ................................................................................................... ................................ 111 appendix b: conversion considerations .......................................................................................... ........................ 111 appendix c: migration from base-line to mid-range devices ...................................................................... ............ 112 index .......................................................................................................................... ................................................. 113 on-line support................................................................................................................ .......................................... 117 reader response ................................................................................................................ ....................................... 118 pic16c62b/72a product identification system .................................................................................... ...................... 119 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number. e.g., ds30000a is version a of document ds30000. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the re vi- sion of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchips worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literature center; u.s. fax: (480) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de liter- ature number) you are using. corrections to this data sheet we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that this document is correct. however, we realize that we may have missed a few things. if you find any information that is missing or appears in error, please: ? fill out and mail in the reader response form in the back of this data sheet. ? e-mail us at webmaster@microchip.com. we appreciate your assistance in making this a better document.
pic16c62b/72a ds35008b-page 4 preliminary ? 1999 microchip technology inc. notes:
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 5 1.0 device overview this document contains device-specific information. additional information may be found in the picmicro? mid-range reference manual, (ds33023), which may be obtained from your local microchip sales represen- tative or downloaded from the microchip website. the reference manual should be considered a comple- mentary document to this data sheet, and is highly rec- ommended reading for a better understanding of the device architecture and operation of the peripheral modules. there are two devices (pic16c62b, pic16c72a) cov- ered by this datasheet. the pic16c62b does not have the a/d module implemented. figure 1-1 is the block diagram for both devices. the pinouts are listed in table 1-1. figure 1-1: pic16c62b/pic16c72a block diagram eprom program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc rb0/int rb7:rb1 rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6 rc7 8 8 brown-out reset note 1: higher order bits are from the status register. 2: the a/d module is not available on the pic16c62b. ccp1 synchronous a/d (2) timer0 timer1 timer2 serial port ra4/t0cki ra5/ss /an4 (2) ra3/an3/v ref (2) ra2/an2 (2) ra1/an1 (2) ra0/an0 (2) 8 3 2k x 14 128 x 8
pic16c62b/72a ds35008b-page 6 preliminary ? 1999 microchip technology inc. table 1-1 pic16c62b/pic16c72a pinout description pin name dip pin# soic pin# i/o/p type buffer type description osc1/clkin 9 9 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 10 10 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, the osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 1 i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 (4) 2 2 i/o ttl ra0 can also be analog input 0 ra1/an1 (4) 3 3 i/o ttl ra1 can also be analog input 1 ra2/an2 (4) 4 4 i/o ttl ra2 can also be analog input 2 ra3/an3/v ref (4) 5 5 i/o ttl ra3 can also be analog input 3 or analog reference voltage ra4/t0cki 6 6 i/o st ra4 can also be the clock input to the timer0 module. output is open drain type. ra5/ss/ an4 (4) 7 7 i/o ttl ra5 can also be analog input 4 or the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 21 21 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1 22 22 i/o ttl rb2 23 23 i/o ttl rb3 24 24 i/o ttl rb4 25 25 i/o ttl interrupt on change pin. rb5 26 26 i/o ttl interrupt on change pin. rb6 27 27 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 28 28 i/o ttl/st (2) interrupt on change pin. serial programming data. portc is a bi-directional i/o port. rc0/t1oso/t1cki 11 11 i/o st rc0 can also be the timer1 oscillator output or timer1 clock input. rc1/t1osi 12 12 i/o st rc1 can also be the timer1 oscillator input. rc2/ccp1 13 13 i/o st rc2 can also be the capture1 input/compare1 output/ pwm1 output. rc3/sck/scl 14 14 i/o st rc3 can also be the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 15 15 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 16 i/o st rc5 can also be the spi data out (spi mode). rc6 17 17 i/o st rc7 18 18 i/o st v ss 8, 19 8, 19 p ground reference for logic and i/o pins. v dd 20 20 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power or program = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured in rc oscillator mode and a cmos input otherwise. 4: the a/d module is not available on the pic16c62b.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 7 2.0 memory organization there are two memory blocks in each of these micro- controllers. each block (program memory and data memory) has its own bus, so that concurrent access can occur. additional information on device memory may be found in the picmicro ? mid-range reference manual, (ds33023). 2.1 program memory organization the pic16c62b/72a devices have a 13-bit program counter capable of addressing an 8k x 14 program memory space. each device has 2k x 14 words of pro- gram memory. accessing a location above 07ffh will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: program memory map and stack pc<12:0> 13 0000h 0004h 0005h 07ffh 0800h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw user memory space
pic16c62b/72a ds35008b-page 8 preliminary ? 1999 microchip technology inc. 2.2 data memory organization the data memory is partitioned into multiple banks which contain the general purpose registers and the special function registers. bits rp1 and rp0 are the bank select bits. = 00 ? bank0 = 01 ? bank1 = 10 ? bank2 (not implemented) = 11 ? bank3 (not implemented) each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function re gisters. some high use special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register file can be accessed either directly, or indi- rectly through the file select register fsr (section 2.5). figure 2-2: register file map rp1 (1) rp0 (status<6:5>) note 1: maintain this bit clear to ensure upward compati- bility with future products. unimplemented data memory locations, read as '0'. note 1: not a physical register. 2: these registers are not implemented on the pic16c62b, read as '0'. file address file address 00h indf (1) indf (1) 80h 01h tmr0 option_reg 81h 02h pcl pcl 82h 0 3 h s tat u s s tat u s 8 3 h 04h fsr fsr 84h 05h porta trisa 85h 06h portb trisb 86h 07h portc trisc 87h 08h 88h 09h 89h 0ah pclath pclath 8ah 0bh intcon intcon 8bh 0ch pir1 pie1 8ch 0dh 8dh 0eh tmr1l pcon 8eh 0fh tmr1h 8fh 10h t1con 90h 11h tmr2 91h 12h t2con pr2 92h 13h sspbuf sspadd 93h 14h sspcon sspstat 94h 15h ccpr1l 95h 16h ccpr1h 96h 17h ccp1con 97h 18h 98h 19h 99h 1ah 9ah 1bh 9bh 1ch 9ch 1dh 9dh 1eh adres (2) 9eh 1fh adcon0 (2) adcon1 (2) 9fh 20h general purpose registers general purpose registers a0h bfh c0h 7fh ffh bank 0 bank 1
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 9 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 2-1. the special function registers can be classified into two sets; core (cpu) and peripheral. those registers associated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in the peripheral feature section. table 2-1 special function register summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (4) bank 0 00h indf (1) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h pcl (1) program counter's (pc) least significant byte 0000 0000 0000 0000 03h status (1) irp (5) rp1 (5) rp0 to pd zdcc 0001 1xxx 000q quuu 04h fsr (1) indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta (6,7) porta data latch when written: porta pins when read --0x 0000 --0u 0000 06h portb (6,7) portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 07h portc (6,7) portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h-09h unimplemented 0ah pclath (1,2) write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh intcon (1) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif (3) sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 0dh unimplemented 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h-1dh unimplemented 1eh adres (3) a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 (3) adcs1 adcs0 chs2 chs1 chs0 go/done adon 0000 00-0 0000 00-0 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', shaded locations are unimplemented, read as '0'. note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: a/d not implemented on the pic16c62b, maintain as 0. 4: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. 5: the irp and rp1 bits are reserved. always maintain these bits clear. 6: on any device reset, these pins are configured as inputs. 7: this is the value that will be in the port output latch.
pic16c62b/72a ds35008b-page 10 preliminary ? 1999 microchip technology inc. bank 1 80h indf (1) addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl (1) program counter's (pc) least significant byte 0000 0000 0000 0000 83h status (1) irp (5) rp1 (5) rp0 to pd zdcc 0001 1xxx 000q quuu 84h fsr (1) indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h-89h unimplemented 8ah pclath (1,2) write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh intcon (1) gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 adie (3) sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 8dh unimplemented 8eh pcon por bor ---- --qq ---- --uu 8fh-91h unimplemented 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 95h-9eh unimplemented 9fh adcon1 (3) pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', shaded locations are unimplemented, read as '0'. note 1: these registers can be addressed from either bank. 2: the upper byte of the program counter is not directly accessible. pclath is a holding register for pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: a/d not implemented on the pic16c62b, maintain as 0. 4: other (non power-up) resets include: external reset through mclr and the watchdog timer reset. 5: the irp and rp1 bits are reserved. always maintain these bits clear. 6: on any device reset, these pins are configured as inputs. 7: this is the value that will be in the port output latch. table 2-1 special function register summary (c ont.d) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (4)
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 11 2.2.2.1 status register the status register, shown in register 2-1, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, the write to these three bits is dis- abled. these bits are set or cleared according to the device logic. the to and pd bits are not writable. the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect the z, c or dc bits from the status register. for other instructions, not affecting any status bits, see the "instruction set summary." register 2-1: status register (address 03h, 83h) note 1: the irp and rp1 bits are reserved. main- tain these bits clear to ensure upward compatibility with future products. note 2: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: irp : register bank select bit (used for indirect addressing) (reserved, maintain clear) bit 6-5: rp1:rp0 : register bank select bits (used for direct addressing) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes note: rp1 is reserved, maintain clear bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (for borrow , the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c : carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (for borrow , the polarity is reversed) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow , the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
pic16c62b/72a ds35008b-page 12 preliminary ? 1999 microchip technology inc. 2.2.2.2 option_reg register the option_reg register is a readable and writable register, which contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assign- able register known as the prescaler), the external int interrupt, tmr0 and the weak pull-ups on portb. register 2-2: option_reg register (address 81h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit - n = value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled for all portb inputs bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 13 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter, which contains various interrupt enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. register 2-3: intcon register (address 0bh, 8bh) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit - n = value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: peie : peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5: t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: iinte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (software must clear bit) 0 = tmr0 register did not overflow bit 1: intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (software must clear bit) 0 = the rb0/int external interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = at least one of the rb7:rb4 input pins have changed state (clear by reading portb) 0 = none of the rb7:rb4 input pins have changed state
pic16c62b/72a ds35008b-page 14 preliminary ? 1999 microchip technology inc. 2.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. register 2-4: pie1 register (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adie (1) sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented: read as 0 bit 6: adie (1) : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5-4: unimplemented : read as 0 bit 3: sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt note 1: the pic16c62b does not have an a/d module. this bit location is reserved on these devices. always maintain this bit clear.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 15 2.2.2.5 pir1 register this register contains the individual flag bits for the peripheral interrupts. register 2-5: pir1 register (address 0ch) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adif (1) sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented : read as 0 bit 6: adif (1) : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5-4: unimplemented : read as 0 bit 3: sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow note 1: the pic16c62b does not have an a/d module. this bit location is reserved on these devices. always maintain this bit clear.
pic16c62b/72a ds35008b-page 16 preliminary ? 1999 microchip technology inc. 2.2.2.6 pcon register the power control register (pcon) contains flag bits to allow differentiation between a power-on reset (por), brown-out reset (bor) and resets from other sources. . register 2-6: pcon register (address 8eh) note: on power-on reset, the state of the bor bit is unknown and is not predictable. if the boden bit in the configuration word is set, the user must first set the bor bit on a por, and check it on subsequent resets. if bor is cleared while por remains set, a brown-out reset has occurred. if the boden bit is clear, the bor bit may be ignored. u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-q por bor r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs)
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 17 2.3 pcl and pclath the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 13 bits wide. the low byte is called the pcl register and is readable and writable. the high byte is called the pch register. this register contains the pc<12:8> bits and is not directly accessible. all updates to the pch regis- ter go through the pclath register. 2.3.1 stack the stack allows any combination of up to 8 program calls and interrupts to occur. the stack contains the return address from this branch in program execution. mid-range devices have an 8 level deep hardware stack. the stack space is not part of either program or data space and the stack pointer is not accessible. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a ret- fie instruction execution. pclath is not modified when the stack is pushed or poped. after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 program memory paging the call and goto instructions provide 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper bit of the address is provided by pclath<3>. the user must ensure that the page select bit is programmed to address the proper pro- gram memory page. if a return from a call instruction (or interrupt) is executed, the entire 13-bit pc is popped from the stack. therefore, manipulation of the pclath<3> bit is not required for the return instruc- tions.
pic16c62b/72a ds35008b-page 18 preliminary ? 1999 microchip technology inc. 2.5 indirect addressing, indf and fsr registers the indf register is not a physical register. address- ing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-1. example 2-1: how to clear ram using indirect addressing movlw 0x20 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-3. however, irp is not used in the pic16c62b/72a. figure 2-3: direct/indirect addressing note 1: maintain clear for upward compatibility with future products. 2: not implemented. data memory indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 not used ffh 80h 7fh 00h 17fh 100h 1ffh 180h (1) (1) (2) (2)
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 19 3.0 i/o ports some i/o port pins are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro? mid-range reference manual, (ds33023). 3.1 porta and the trisa register porta is a 6-bit wide bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (=1) will make the corresponding porta pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisa bit (=0) will make the corresponding porta pin an output, (i.e., put the contents of the output latch on the selected pin). the porta register reads the state of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. there- fore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. pin ra5 is multiplexed with the ssp to become the ra5/ss pin. on the pic16c72a device, other porta pins are mul- tiplexed with analog inputs and analog v ref input. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. figure 3-1: block diagram of ra3:ra0 and ra5 pins figure 3-2: block diagram of ra4/t0cki pin note: on a power-on reset, pins with analog functions are configured as analog inputs with digital input buffers disabled . a digital read of these pins will return 0. data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter (72a only) (72a only) data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input q d q ck q d q ck en qd en note 1: i/o pin has protection diodes to v ss only.
pic16c62b/72a ds35008b-page 20 preliminary ? 1999 microchip technology inc. table 3-1 porta functions table 3-2 summary of registers associated with porta name bit# buffer function ra0/an0 bit0 ttl input/output or analog input (1) ra1/an1 bit1 ttl input/output or analog input (1) ra2/an2 bit2 ttl input/output or analog input (1) ra3/an3/v ref bit3 ttl input/output or analog input (1) or v ref (1) ra4/t0cki bit4 st input/output or external clock input for timer0 output is open drain type ra5/ss /an4 bit5 ttl input/output or slave select input for synchronous serial port or analog input (1) legend: ttl = ttl input, st = schmitt trigger input note 1: the pic16c62b does not implement the a/d module. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 05h porta (for pic16c72a only) ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 05h porta (for pic16c62b only) ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu 85h trisa porta data direction register --11 1111 --11 1111 9fh adcon1 (1) pcfg2pcfg1pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. note 1: the pic16c62b does not implement the a/d module. maintain this register clear.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 21 3.2 portb and the trisb register portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (=1) will make the corresponding portb pin an input, (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisb bit (=0) will make the corresponding portb pin an output, (i.e., put the contents of the output latch on the selected pin). each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. figure 3-3: block diagram of rb3:rb0 pins four of portbs pins, rb7:rb4, have an interrupt on change feature. only pins configured as inputs can cause this interrupt to occur (i.e. any rb7:rb4 pin con- figured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the mismatch outputs of rb7:rb4 are ored together to generate the rb port change inter- rupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. rb0/int is an external interupt pin and is configured using the intedg bit (option_reg<6>). rb0/int is discussed in detail in section 10.10.1. figure 3-4: block diagram of rb7:rb4 pins data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). schmitt trigger buffer tris latch data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . st buffer rb7:rb6 in serial programming mode q3 q1 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>).
pic16c62b/72a ds35008b-page 22 preliminary ? 1999 microchip technology inc. table 3-3 portb functions table 3-4 summary of registers associated with portb name bit# buffer function rb0/int bit0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h trisb portb data direction register 1111 1111 1111 1111 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 23 3.3 portc and the trisc register portc is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisc. setting a trisc bit (=1) will make the corresponding portc pin an input, (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisc bit (=0) will make the corresponding portc pin an output, (i.e., put the contents of the output latch on the selected pin). portc is multiplexed with several peripheral functions (table 3-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override maybe in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisc as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. figure 3-5: portc block diagram (peripheral output override) port/peripheral select (2) data bus wr port wr tris rd data latch tris latch rd tris schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss port peripheral oe (3) peripheral input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active.
pic16c62b/72a ds35008b-page 24 preliminary ? 1999 microchip technology inc. table 3-5 portc functions table 3-6 summary of registers associated with portc name bit# buffer type function trisc override rc0/t1oso/t1cki bit0 st input/output port pin or timer1 oscillator output/timer1 clock input yes rc1/t1osi bit1 st input/output port pin or timer1 oscillator input yes rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/pwm1 output no rc3/sck/scl bit3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. no rc4/sdi/sda bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). no rc5/sdo bit5 st input/output port pin or synchronous serial port data output no rc6 bit6 st input/output port pin no rc7 bit7 st input/output port pin no legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 25 4.0 timer0 module the timer0 module timer/counter has the following fea- tures: ? 8-bit timer/counter - read and write - int on overflow ? 8-bit software programmable prescaler ? int or ext clock select - ext clock edge select figure 4-1 is a simplified block diagram of the timer0 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). 4.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without pres- caler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. additional information on external clock requirements is available in the electrical specifications section of this manual, and in the picmicro? mid-range refer- ence manual, (ds33023). 4.2 pre scaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer, respectively (figure 4-2). for simplicity, this counter is being referred to as prescaler throughout this data sheet. there is only one prescaler available which is shared between the timer0 module and the watchdog timer. a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. the prescaler is not readable or writable. the psa and ps2:ps0 bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. setting bit psa will assign the prescaler to the watch- dog timer (wdt). when the prescaler is assigned to the wdt, prescale values of 1:1, 1:2, ..., 1:128 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. figure 4-1: timer0 block diagram note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment or ratio. note 1: t0cs, t0se, psa, ps2:ps0 (option_reg<5:0>). 2: the prescaler is shared with watchdog timer (refer to figure 4-2 for detailed block diagram). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 psout (t cy delay) psout data bus 8 psa ps2, ps1, ps0 set interrupt flag bit t0if on overflow 3
pic16c62b/72a ds35008b-page 26 preliminary ? 1999 microchip technology inc. 4.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, ( i.e., it can be changed on-the-fly during program execution). 4.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut off during sleep. figure 4-2: block diagram of the timer0/wdt prescaler table 4-1 registers associated with timer0 note: to avoid an unintended device reset, a specific instruction sequence (shown in the picmicro? mid-range reference man- ual, ds33023) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa porta data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0. ra4/t0cki t0se pin m u x clkout (= fosc/4) sync 2 t cy tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs prescaler
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 27 5.0 timer1 module the timer1 module timer/counter has the following fea- tures: ? 16-bit timer/counter ? readable and writable ? internal or external clock select ? interrupt on overflow from ffffh to 0000h ? reset from ccp module trigger timer1 has a control register, shown in register 5-1. timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). figure 5-1 is a simplified block diagram of the timer1 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). 5.1 timer1 operation timer1 can operate in one of these modes: ?as a timer ? as a synchronous counter ? as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer1 also has an internal reset input. this reset can be generated by the ccp module as a special event trigger (section 7.0). register 5-1:t1con: timer1 control register (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3: t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled (trisc<1:0> ignored) 0 = oscillator is shut off (the oscillator is turned off to reduce power drain bit 2: t1sync : timer1 external clock input synchronization control bit t mr1cs = 1 1 = do not synchronize external clock input 0 = synchronize external clock input t mr1cs = 0 this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1: tmr1cs : timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0: tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1
pic16c62b/72a ds35008b-page 28 preliminary ? 1999 microchip technology inc. figure 5-1: timer1 block diagram tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi note 1: when the t1oscen bit is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. set flag bit tmr1if on overflow tmr1
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 29 5.2 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). when the timer1 oscillator is enabled, rc0 and rc1 pins become t1oso and t1osi inputs, overriding trisc<1:0>. the oscillator is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. table 5-1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 5-1 capacitor selection for the timer1 oscillator 5.3 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled by setting tmr1 interrupt enable bit tmr1ie (pie1<0>). 5.4 resetting timer1 using a ccp trigger output if the ccp module is configured in compare mode to generate a special event trigger" (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1, the write will take prece- dence. in this mode of operation, the ccpr1h:ccpr1l regis- ters pair effectively becomes the period register for timer1. table 5-2 registers associated with timer1 as a timer/counter osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. note: the special event trigger from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer1 module.
pic16c62b/72a ds35008b-page 30 preliminary ? 1999 microchip technology inc. notes:
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 31 6.0 timer2 module the timer2 module timer has the following features: ? 8-bit timer (tmr2 register) - readable and writable ? 8-bit period register (pr2) - readable and writable ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) ? interrupt on match (tmr2 = pr2) ? timer2 can be used by ssp and ccp timer2 has a control register, shown in register 6-1. timer2 can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. figure 6-1 is a simplified block diagram of the timer2 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). figure 6-1: timer2 block diagram register 6-1:t2con: timer2 control register (address 12h) comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6-3: toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 0010 = 1:3 postscale ? ? ? 1111 = 1:16 postscale bit 2: tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0: t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16
pic16c62b/72a ds35008b-page 32 preliminary ? 1999 microchip technology inc. 6.1 t imer2 operation the timer2 output is also used by the ccp module to generate the pwm "on-time", and the pwm period with a match with pr2. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling) to gener- ate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr2 is not cleared when t2con is written. 6.2 timer2 interrupt the timer2 module has an 8-bit period register pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is ini- tialized to ffh upon reset. 6.3 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module, which optionally uses it to generate shift clock. table 6-1 registers associated with timer2 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -00- 0000 0000 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 0000 0000 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer2 module.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 33 7.0 capture/compare/pwm (ccp) module the ccp (capture/compare/pwm) module contains a 16-bit register, which can operate as a 16-bit capture register, as a 16-bit compare register or as a pwm master/slave duty cycle register. table 7-1 shows the timer resources of the ccp module modes. capture/compare/pwm register 1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. additional information on the ccp module is available in the picmicro? mid-range reference manual, (ds33023). table 7-1 ccp mode - timer resource table 7-2 interaction of two ccp modules register 7-1:ccp1con register (address 17h) ccp mode timer resource capture compare pwm timer1 timer1 timer2 ccpx mode ccpy mode interaction capture capture same tmr1 time-base. capture compare the compare should be configured for the special event trigger, which clears tmr1. compare compare the compare(s) should be configured for the special event trigger, which clears tmr1. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). pwm capture none. pwm compare none. u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: ccp1x:ccp1y : pwm least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccpr1l. bit 3-0: ccp1m3:ccp1m0 : ccp1 mode select bits 0000 = capture/compare/pwm off (resets ccp1 module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccp1if bit is set) 1001 = compare mode, clear output on match (ccp1if bit is set) 1010 = compare mode, generate software interrupt on match (ccp1if bit is set, ccp1 pin is unaffected) 1011 = compare mode, trigger special event (ccp1if bit is set; ccp1 resets tmr1 and starts an a/d conversion (if a/d module is enabled)) 11xx = pwm mode
pic16c62b/72a ds35008b-page 34 preliminary ? 1999 microchip technology inc. 7.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register, when an event occurs on pin rc2/ccp1. an event is defined as: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ,ccp1if (pir1<2>), is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. figure 7-1: capture mode operation block diagram 7.1.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be config- ured as an input by setting the trisc<2> bit. 7.1.2 timer1 mode selection timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work consistently. 7.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should clear ccp1ie (pie1<2>) before changing the capture mode to avoid false interrupts. clear the interrupt flag bit, ccp1ie before setting ccp1ie. 7.1.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. example 7-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the false interrupt. example 7-1: changing between capture prescalers clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; mode value and ccp on movwf ccp1con ;load ccp1con with this ; value note: if the rc2/ccp1 is configured as an out- put, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable qs ccp1con<3:0> rc2/ccp1 prescaler ? 1, 4, 16 and edge detect pin
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 35 7.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: ?driven high ? driven low ? remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). the inter- rupt flag bit, ccp1if, is set on all compare matches. figure 7-2: compare mode operation block diagram 7.2.1 ccp pin configuration the user must configure the rc2/ccp1 pin as an out- put by clearing the trisc<2> bit. 7.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 7.2.3 software interrupt mode when a generated software interrupt is chosen, the ccp1 pin is not affected. only a ccp interrupt is gen- erated (if enabled). 7.2.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special trigger output of ccp1 resets the tmr1 register pair and starts an a/d conversion (if the a/d module is enabled). table 7-3 registers associated with capture, compare, and timer1 ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: reset timer1, but not set interrupt flag bit tmr1if (pir1<0>), and set bit go/done (adcon0<2>), which starts an a/d conversion note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by capture and timer1.
pic16c62b/72a ds35008b-page 36 preliminary ? 1999 microchip technology inc. 7.3 pwm mode in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 7-3 shows a simplified block diagram of the ccp module in pwm mode. for a step by step procedure on how to set up the ccp module for pwm operation, see section 7.3.3. figure 7-3: simplified pwm block diagram a pwm output (figure 7-4) has a time base (period) and a time that the output stays high (on-time). the fre- quency of the pwm is the inverse of the period (1/period). figure 7-4: pwm output 7.3.1 pwm period the pwm period is specified by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = [(pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h 7.3.2 pwm on-time the pwm on-time is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. ccpr1l contains eight msbs and ccp1con<5:4> contains two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm on-time = (ccpr1l:ccp1con<5:4>) ? tosc ? (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the on-time value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm on-time. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. maximum pwm resolution (bits) for a given pwm frequency: for an example pwm period and on-time calculation, see the picmicro? mid-range reference manual, (ds33023). note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. period on-time tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 6.0) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different fre- quency than the pwm output. note: if the pwm on-time value is larger than the pwm period, the ccp1 pin will not be cleared. log ( fpwm log(2) fosc ) bits = resolution
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 37 7.3.3 set-up for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 regis- ter. 2. set the pwm on-time by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 7-4 example pwm frequencies and resolutions at 20 mhz table 7-5 registers associated with pwm and timer2 pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 modules register 0000 0000 0000 0000 92h pr2 timer2 modules period register 1111 1111 1111 1111 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by pwm and timer2.
pic16c62b/72a ds35008b-page 38 preliminary ? 1999 microchip technology inc. notes:
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 39 8.0 synchronous serial port (ssp) module 8.1 ssp module overview the synchronous serial port (ssp) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the ssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c) for more information on ssp operation (including an i 2 c overview), refer to the picmicro? mid-range ref- erence manual, (ds33023). also, refer to application note an578, use of the ssp module in the i 2 c multi- master environment. 8.2 spi mode this section contains register definitions and opera- tional characteristics of the spi module. additional information on spi operation may be found in the picmicro? mid-range reference manual, (ds33023). 8.2.1 operation of ssp module in spi mode a block diagram of the ssp module in spi mode is shown in figure 8-1. the spi mode allows 8-bits of data to be synchro- nously transmitted and received simultaneously. to accomplish communication, three pins are used: ? serial data out (sdo)rc5/sdo ? serial data in (sdi)rc4/sdi/sda ? serial clock (sck)rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: ?slave select (ss )ra5/ss /an4 when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>) and sspstat<7:6>. these control bits allow the fol- lowing to be specified: ? master operation (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master operation only) ? slave select mode (slave mode only) to enable the serial port, ssp enable bit, sspen (sspcon<5>) must be set. to reset or reconfigure spi mode, clear bit sspen, re-initialize the sspcon reg- ister, and then set bit sspen. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the trisc register) appro- priately programmed. that is: ? sdi must have trisc<4> set ? sdo must have trisc<5> cleared ? sck (master operation) must have trisc<3> cleared ? sck (slave mode) must have trisc<3> set ?ss must have trisa<5> set (if used) figure 8-1: ssp block diagram (spi mode) note: when the spi is in slave mode with ss pin control enabled, (sspcon<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . note: if the spi is used in slave mode with cke = '1', then the ss pin control must be enabled. read write internal data bus rc4/sdi/sda rc5/sdo ra5/ss /an4 rc3/sck/ sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 trisc<3> 2 edge select 2 4 scl
pic16c62b/72a ds35008b-page 40 preliminary ? 1999 microchip technology inc. table 8-1 registers associated with spi operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 85h trisa porta data direction register --11 1111 --11 1111 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in spi mode.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 41 8.3 ssp i 2 c operation the ssp module in i 2 c mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to support firmware implementations of the master functions. the ssp module implements the standard mode specifica- tions, as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rc3/sck/scl pin, which is the clock (scl), and the rc4/sdi/sda pin, which is the data (sda). the user must configure these pins as inputs or outputs through the trisc<4:3> bits. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon<5>). figure 8-2: ssp block diagram (i 2 c mode) the ssp module has five registers for i 2 c operation. these are the: ? ssp control register (sspcon) ? ssp status register (sspstat) ? serial receive/transmit buffer (sspbuf) ? ssp shift register (sspsr) - not accessible ? ssp address register (sspadd) the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled for firmware master mode support ?i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled for firmware master mode support ?i 2 c start and stop bit interrupts enabled for firm- ware master mode support, slave mode idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be operated as open drain outputs, provided these pins are programmed to inputs by setting the appropriate trisc bits. additional information on ssp i 2 c operation may be found in the picmicro? mid-range reference manual, (ds33023). 8.3.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the ssp module will override the input state with the output data when required (slave-transmitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse, and load the sspbuf register with the received value in the sspsr register. there are certain conditions that will cause the ssp module not to give this ack pulse. this happens if either of the following conditions occur: a) the buffer full bit bf (sspstat<0>) was set before the transfer was completed. b) the overflow bit sspov (sspcon<6>) was set before the transfer was completed. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. table 8-2 shows what happens when a data transfer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user soft- ware did not properly clear the overflow condition. flag bit bf is cleared by reading the sspbuf register, while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the ssp module, is shown in timing parameter #100, t high , and parameter #101, t low . read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda
pic16c62b/72a ds35008b-page 42 preliminary ? 1999 microchip technology inc. 8.3.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condi- tion, 8 bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit, bf is set. c) an ack pulse is generated. d) ssp interrupt flag bit, sspif (pir1<3>), is set (interrupt is generated if enabled) on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal 1111 0 a9 a8 0 , where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7- 9 for slave-transmit- ter: 1. receive first (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the first (high) byte of address, if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. table 8-2 data transfer received byte actions status bits as data transfer is received sspsr ? sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 ye s ye s ye s 10 no no yes 11 no no yes 0 1 ye s no ye s note: shaded cells show the conditions where the user software did not properly clear the overflow condition.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 43 8.3.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat reg- ister is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then no acknowledge (ack ) pulse is given. an overflow con- dition is defined as either bit bf (sspstat<0>) is set or bit sspov (sspcon<6>) is set. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the byte. figure 8-3: i 2 c waveforms for reception (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w =0 receiving address sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon<6>) ack ack is not sent.
pic16c62b/72a ds35008b-page 44 preliminary ? 1999 microchip technology inc. 8.3.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and the ckp will be cleared by hardware, holding scl low. slave devices cause the master to wait by holding the scl line low. the transmit data is loaded into the sspbuf register, which in turn loads the sspsr register. when bit ckp (ssp- con<4>) is set, pin rc3/sck/scl releases scl. when the scl line goes high, the master may resume operating the scl line and receiving data. the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 8-4). an ssp interrupt is generated for each data transfer byte. flag bit sspif must be cleared in software, and the sspstat register used to determine the status of the byte. flag bit sspif is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master- receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not ack ), then the data transfer is complete. when the ack is latched by the slave, the slave logic is reset (resets sspstat reg- ister) and the slave then monitors for another occur- rence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf reg- ister, which also loads the sspsr register. then pin rc3/sck/scl should be enabled by setting bit ckp. figure 8-4: i 2 c waveforms for transmission (7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written-to before the ckp bit can be set)
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 45 8.3.2 master operation master operation is supported in firmware using inter- rupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared by a reset or when the ssp module is dis- abled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle and both the s and p bits are clear. in master operation, the scl and sda lines are manip- ulated in software by clearing the corresponding trisc<4:3> bit(s). the output level is always low, irre- spective of the value(s) in portc<4:3>. so when transmitting data, a '1' data bit must have the trisc<4> bit set (input) and a '0' data bit must have the trisc<4> bit cleared (output). the same scenario is true for the scl line with the trisc<3> bit. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): ? start condition ? stop condition ? byte transfer completed master operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ) or with the slave active. when both master operation and slave modes are used, the software needs to differentiate the source(s) of the interrupt. for more information on master operation, see an554 - software implementation of i 2 c bus master . 8.3.3 multi-master operation in multi-master operation, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle based on the start and stop conditions. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle and both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored to see if the signal level is the expected output level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set trisc<4:3>). there are two stages where this arbitration can be lost, these are: ? address transfer ? data transfer when the slave logic is enabled, the slave continues to receive. if arbitration was lost during the address trans- fer stage, communication to the device may be in progress. if addressed, an ack pulse will be gener- ated. if arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. for more information on master operation, see an578 - use of the ssp module in the of i 2 c multi-master environment . table 8-3 registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp (1) cke (1) d/a psr/w ua bf 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by ssp module in spi mode. note 1: maintain these bits clear in i 2 c mode.
pic16c62b/72a ds35008b-page 46 preliminary ? 1999 microchip technology inc. register 8-1: sspstat: sync serial port status register (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf r = readable bit w = writable bit u = unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7: smp: spi data input sample phase spi master operation 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode smp must be cleared when spi is used in slave mode i 2 c mode this bit must be maintained clear bit 6: cke : spi clock edge select spi mode ckp = 0 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck i 2 c mode this bit must be maintained clear bit 5: d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4: p : stop bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, or when the start bit is detected last, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3: s : start bit (i 2 c mode only. this bit is cleared when the ssp module is disabled, or when the stop bit is detected last, sspen is cleared) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2: r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or ack bit. 1 = read 0 = write bit 1: ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0: bf : buffer full status bit receive (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only) 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 47 register 8-2: sspcon: sync serial port control register (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7: wcol : write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6: sspov : receive overflow indicator bit in spi mode 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master operation, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no overflow in i 2 c mode 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "dont care" in transmit mode. sspov must be cleared in software in either mode. 0 = no overflow bit 5: sspen : synchronous serial port enable bit in spi mode 1 = enables serial port and configures sck, sdo, and sdi as serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode 1 = enables the serial port and configures the sda and scl pins as serial port pins 0 = disables serial port and configures these pins as i/o port pins in both modes, when enabled, these pins must be properly configured as input or output. bit 4: ckp : clock polarity select bit in spi mode 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c mode sck release control 1 = enable clock 0 = holds clock low (clock stretch) bit 3-0: sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master operation, clock = f osc /4 0001 = spi master operation, clock = f osc /16 0010 = spi master operation, clock = f osc /64 0011 = spi master operation, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1011 = i 2 c firmware controlled master operation (slave idle) 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled
pic16c62b/72a ds35008b-page 48 preliminary ? 1999 microchip technology inc. notes:
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 49 9.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has five input channels. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to applica- tion note an546 for use of a/d converter). the output of the sample and hold is the input into the converter, which generates the result via successive approxima- tion. the analog reference voltage is software select- able to either the devices positive supply voltage (v dd ) or the voltage level on the ra3/an3/v ref pin. the a/d converter has the feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d conversion clock must be derived from the a/ds internal rc oscillator. additional information on the a/d module is available in the picmicro? mid-range reference manual, (ds33023). the a/d module has three registers. these registers are: ? a/d result register (adres) ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the adcon0 register, shown in figure 9-1, controls the operation of the a/d module. the adcon1 regis- ter, shown in figure 9-2, configures the functions of the port pins. the port pins can be configured as analog inputs (ra3 can also be a voltage reference) or as dig- ital i/o. register 9-1:adcon0 register (address 1fh) note: this section applies to the pic16c72a only. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done adon r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: adcs1:adcs0: a/d conversion clock select bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (clock derived from an internal rc oscillator) bit 5-3: chs2:chs0 : analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 100 = channel 4, (ra5/an4) bit 2: go/done : a/d conversion status bit if adon = 1 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1: unimplemented : read as '0' bit 0: adon : a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shutoff and consumes no operating current
pic16c62b/72a ds35008b-page 50 preliminary ? 1999 microchip technology inc. register 9-2:adcon1 register (address 9fh) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 pcfg2 pcfg1 pcfg0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-3: unimplemented: read as '0' bit 2-0: pcfg2:pcfg0 : a/d port configuration control bits a = analog input d = digital i/o pcfg2:pcfg0 ra0 ra1 ra2 ra5 ra3 v ref 000 aaaaa v dd 001 aaaav ref ra3 010 aaaaa v dd 011 aaaav ref ra3 100 aadda v dd 101 aaddv ref ra3 11x ddddd v dd
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 51 when the a/d conversion is complete, the result is loaded into the adres register, the go/done bit, adcon0<2>, is cleared, and the a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 9-1. the value that is in the adres register is not modified for a power-on reset. the adres register will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 9.1. after this acquisition time has elapsed, the a/d conver- sion can be started. the following steps should be fol- lowed for doing an a/d conversion: 1. configure the a/d module: ? configure analog pins / voltage reference / and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d conversion clock (adcon0) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set gie bit 3. wait the required acquisition time. 4. start conversion: ? set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result register (adres), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 9-1: a/d block diagram (input voltage) v in v ref (reference voltage) v dd pcfg2:pcfg0 chs2:chs0 000 or 010 or 100 or 001 or 011 or 101 ra5/an4 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 100 011 010 001 000 a/d converter 11x
pic16c62b/72a ds35008b-page 52 preliminary ? 1999 microchip technology inc. 9.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 9-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the ana- log input (due to pin leakage current). the maximum recommended impedance for analog sources is 10 k w . after the analog input channel is selected (changed), this acquisition must pass before the con- version can be started. to calculate the minimum acquisition time, t acq , see equation 9-1. this equation calculates the acquisition time to within 1/2 lsb error (512 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified accuracy. in general; assuming r s = 10k w vdd = 3.0v (r ss = 10k w) te m p. = 5 0 c (122 f) t acq ? 13.0 m sec by increasing v dd and reducing r s and temp., t acq can be substantially reduced. figure 9-2: analog input model equation 9-1: acquisition time note: when the conversion is started, the hold- ing capacitor is disconnected from the input pin. t acq = = amplifier settling time + hold capacitor charging time + temperature coefficient t amp + t c + t coff t amp = 5 m s t c = - (51.2pf)(1k w + r ss + r s ) in(1/511) t coff = (temp -25 c)(0.05 m s/ c) c pin va rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v r ss 5v 4v 3v 2v 567891011 (k w ) v dd = 51.2 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 53 9.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 9.5t ad per 8-bit conversion. the source of the a/d conversion clock is software selectable. the four possible options for t ad are: ?2t osc ?8t osc ?32t osc ? internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 m s. the a/d module can operate during sleep mode, but the rc oscillator must be selected as the a/d clock source prior to the sleep instruction. table 9-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 9.3 configuring analog port pins the adcon1 and trisa registers control the opera- tion of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs2:chs0 bits and the tris bits. table 9-1 t ad vs. device operating frequencies note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs, will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. note 2: analog levels on any pin that is defined as a digital input (including the an4:an0 pins) may cause the input buffer to con- sume current that is out of the devices specification. ad clock source (t ad ) device frequency operation adcs1:adcs0 20 mhz 5 mhz 1.25 mhz 333.33 khz 2t osc 00 100 ns (2) 400 ns (2) 1.6 m s6 m s 8t osc 01 400 ns (2) 1.6 m s6.4 m s 24 m s (3) 32t osc 10 1.6 m s6.4 m s 25.6 m s (3) 96 m s (3) rc (5) 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) legend: shaded cells are outside of recommended range. note 1: the rc source has a typical t ad time of 4 m s. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when device frequency is greater than 1 mhz, the rc a/d conversion clock source is recommended for sleep operation only. 5: for extended voltage devices (lc), please refer to electrical specifications section.
pic16c62b/72a ds35008b-page 54 preliminary ? 1999 microchip technology inc. 9.4 a/d conversions 9.5 use of the ccp trigger an a/d conversion can be started by the special event trigger of the ccp1 module. this requires that the ccp1m3:ccp1m0 bits (ccp1con<3:0>) be pro- grammed as 1011 and that the a/d module be enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead. the appropriate ana- log input channel must be selected and the minimum acquisition time must pass before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the special event trigger will be ignored by the a/d module, but will still reset the timer1 counter. table 9-2 summary of a/d registers note: the go/done bit should not be set in the same instruction that turns on the a/d. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done adon 0000 00-0 0000 00-0 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h porta ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa porta data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 55 10.0 special features of the cpu the pic16c62b/72a devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protec- tion. these are: ? oscillator mode selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming? (icsp) these devices have a watchdog timer, which can be shut off only through configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay on power-up only and is designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. additional information on special features is available in the picmicro? mid-range reference manual, (ds33023). 10.1 configuration bits the configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/configuration memory space (2000h - 3fffh), which can be accessed only during program- ming. figure 10-1: configuration word cp1 cp0 cp1 cp0 cp1 cp0 boden cp1 cp0 pwrte wdte fosc1 fosc0 register: config address: 2007h bit13 bit0 bit 13-8 cp1:cp0 : code protection bits (2) 5-4: 11 = code protection off 10 = upper half of program memory code protected 01 = upper 3/4th of program memory code protected 00 = all memory is code protected bit 7: unimplemented : read as '1' bit 6: boden : brown-out reset enable bit (1) 1 = bor enabled 0 = bor disabled bit 3: pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables power-up timer (pwrt), regardless of the value of bit pwrte . all of the cp1:cp0 pairs must be given the same value to enable the code protection scheme listed.
pic16c62b/72a ds35008b-page 56 preliminary ? 1999 microchip technology inc. 10.2 oscillator configurations 10.2.1 oscillator types the pic16cxxx can be operated in four different oscil- lator modes. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: ? lp low power crystal ? xt crystal/resonator ? hs high speed crystal/resonator ? rc resistor/capacitor 10.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 10-2). the pic16cxxx oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- tions. when in xt, lp or hs modes, the device can use an external clock source to drive the osc1/clkin pin (figure 10-3). figure 10-2: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 10-3: external clock input operation (hs, xt or lp osc configuration) table 10-1 ceramic resonators table 10-2 capacitor selection for crystal oscillator note1: see table 10-1 and table 10-2 for recom- mended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to logic pic16cxxx rs (2) internal osc1 osc2 open clock from ext. system pic16cxxx ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes at bottom of page. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% resonators did not have built-in capacitors. osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes at bottom of page. crystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm note 1: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: since each resonator/crystal has its own charac- teristics, the user should consult the resona- tor/crystal manufacturer for appropriate values of external components. 3: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 4: oscillator performance should be verified when migrating between devices (including pic16c62a to pic16c62b and pic16c72 to pic16c72a)
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 57 10.2.3 rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 10-4 shows how the r/c combina- tion is connected to the pic16cxxx. figure 10-4: rc oscillator mode 10.3 reset the pic16cxxx differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt reset (during normal operation) ? wdt wake-up (during sleep) ? brown-out reset (bor) some registers are not affected in any reset condition; their status is unknown on por and unchanged by any other reset. most other registers are reset to a reset state on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep, and on brown-out reset (bor). they are not affected by a wdt wake-up from sleep, which is viewed as the resumption of normal operation. the to and pd bits are set or cleared depending on the reset situation, as indicated in table 10-4. these bits are used in software to determine the nature of the reset. see table 10-6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 10-5. the picmicro devices have a mclr noise filter in the mclr reset path. the filter will ignore small pulses. however, a valid mclr pulse must meet the minimum pulse width (tmcl, specification #30). no internal reset source (wdt, bor, por) willdrive the mclr pin low. osc2/clkout cext rext pic16cxx osc1 fosc/4 internal clock v dd v ss recommended values: 3 k w rext 100 k w cext > 20pf
pic16c62b/72a ds35008b-page 58 preliminary ? 1999 microchip technology inc. figure 10-5: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden (1)
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 59 10.4 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.5v - 2.1v). to take advantage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will elimi- nate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is specified (sv dd , parameter d004). for a slow rise time, see figure 10-6. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure oper- ation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the start-up con- ditions. figure 10-6: external power-on reset circuit (for slow v dd power-up) 10.5 power-up timer (pwrt) the power-up timer provides a fixed nominal time-out (t pwrt , parameter #33) from the por. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrts time delay allows v dd to rise to an acceptable level. a configuration bit is provided to enable/disable the pwrt. the power-up time delay will vary from chip-to-chip due to v dd , temperature and process variation. see dc parameters for details. 10.6 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a delay of 1024 oscillator cycles (from osc1 input) after the pwrt delay is over (t ost , parameter #32). this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 10.7 brown-out reset (bor) the configuration bit, boden, can enable or disable the brown-out reset circuit. if v pp falls below vbor (parameter #35, about 100 m s), the brown-out situation will reset the device. if v dd falls below v bor for less than t bor , a reset may not occur. once the brown-out occurs, the device will remain in brown-out reset until v dd rises above v bor . the power-up timer then keeps the device in reset for t pwrt (parameter #33, about 72ms). if v dd should fall below v bor during t pwrt , the brown-out reset pro- cess will restart when v dd rises above v bor with the power-up timer reset. the power-up timer is always enabled when the brown-out reset circuit is enabled, regardless of the state of the pwrt configuration bit. note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k w is recommended to make sure that voltage drop across r does not violate the devices electrical specification. 3: r1 = 100 w to 1 k w will limit any current flowing into mclr from external capacitor c in the event of mclr/ v pp pin break- down due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic16cxx note: the ost delay may not occur when the device wakes from sleep.
pic16c62b/72a ds35008b-page 60 preliminary ? 1999 microchip technology inc. 10.8 time-out sequence when a por reset occurs, the pwrt delay starts (if enabled). when pwrt ends, the ost counts 1024 oscillator cycles (lp, xt, hs modes only). when ost completes, the device comes out of reset. the total time-out will vary based on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution imme- diately. this is useful for testing purposes or to synchro- nize more than one pic16cxxx device operating in parallel. table 10-5 shows the reset conditions for the status, pcon and pc registers, while table 10-6 shows the reset conditions for all the registers. 10.9 power control/status register (pcon) the bor bit is unknown on power-on reset. if the brown-out reset circuit is used, the bor bit must be set by the user and checked on subsequent resets to see if it was cleared, indicating a brown-out has occurred. p or (power-on reset status bit) is cleared on a power-on reset and unaffected otherwise. the user status register pcon register table 10-3 time-out in various situations table 10-4 status bits and their significance table 10-5 reset condition for special registers irp rp1 rp0 to pd z dc c por bor oscillator configuration power-up brown-out wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024t osc rc 72 ms 72 ms por bor to pd 0x11 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h).
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 61 table 10-6 initialization conditions for all registers register applicable devices power-on reset, brown-out reset mclr resets wdt reset wake-up via wdt or interrupt w62b72a xxxx xxxx uuuu uuuu uuuu uuuu indf 62b 72a n/a n/a n/a tmr0 62b 72a xxxx xxxx uuuu uuuu uuuu uuuu pcl 62b 72a 0000h 0000h pc + 1 (2) status 62b 72a 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 62b 72a xxxx xxxx uuuu uuuu uuuu uuuu porta (4) 62b 72a --0x 0000 --0u 0000 --uu uuuu portb (5) 62b 72a xxxx xxxx uuuu uuuu uuuu uuuu portc (5) 62b 72a xxxx xxxx uuuu uuuu uuuu uuuu pclath 62b 72a ---0 0000 ---0 0000 ---u uuuu intcon 62b 72a 0000 000x 0000 000u uuuu uuuu (1) pir1 62b 72a ---- 0000 ---- 0000 ---- uuuu (1) 62b 72a -0-- 0000 -0-- 0000 -u-- uuuu (1) tmr1l 62b 72a xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 62b 72a xxxx xxxx uuuu uuuu uuuu uuuu t1con 62b 72a --00 0000 --uu uuuu --uu uuuu tmr2 62b 72a 0000 0000 0000 0000 uuuu uuuu t2con 62b 72a -000 0000 -000 0000 -uuu uuuu sspbuf 62b 72a xxxx xxxx uuuu uuuu uuuu uuuu sspcon 62b 72a 0000 0000 0000 0000 uuuu uuuu ccpr1l 62b 72a xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 62b 72a xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 62b 72a --00 0000 --00 0000 --uu uuuu adres 62b 72a xxxx xxxx uuuu uuuu uuuu uuuu adcon0 62b 72a 0000 00-0 0000 00-0 uuuu uu-u option_reg 62b 72a 1111 1111 1111 1111 uuuu uuuu trisa 62b 72a --11 1111 --11 1111 --uu uuuu trisb 62b 72a 1111 1111 1111 1111 uuuu uuuu trisc 62b 72a 1111 1111 1111 1111 uuuu uuuu pie1 62b 72a ---- 0000 ---- 0000 ---- uuuu 62b 72a -0-- 0000 -0-- 0000 -u-- uuuu pcon 62b 72a ---- --0q ---- --uq ---- --uq pr2 62b 72a 1111 1111 1111 1111 1111 1111 sspadd 62b 72a 0000 0000 0000 0000 uuuu uuuu sspstat 62b 72a 0000 0000 0000 0000 uuuu uuuu adcon1 62b 72a ---- -000 ---- -000 ---- -uuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 10-5 for reset value for specific condition. 4: on any device reset, these pins are configured as inputs. 5: this is the value that will be in the port output latch.
pic16c62b/72a ds35008b-page 62 preliminary ? 1999 microchip technology inc. 10.10 i nterrupts the interrupt control register (intcon) records individ- ual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables or disables all interrupts. when bit gie is enabled, and an interrupts flag bit and mask bit are set, the interrupt will vector immediately. individual inter- rupts can be disabled through their corresponding enable bits in various registers. individual interrupt flag bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the return from interrupt instruction, retfie , exits the interrupt routine and sets the gie bit, which re- enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the spe- cial function registers pir1 and pir2. the correspond- ing interrupt enable bits are contained in special function registers pie1 and pie2, and the peripheral interrupt enable bit is contained in special function reg- ister intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupts, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine, the source of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit must be cleared in software before re-enabling interrupts to avoid recur- sive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles, depending on when the interrupt event occurs. the latency is the same for one or two cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the gie bit figure 10-7: interrupt logic note: individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the gie bit. adif (1) adie (1) sspif sspie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu note 1: the a/d module is not implemented on the pic16c62b.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 63 10.10.1 int interrupt the external interrupt on rb0/int pin is edge trig- gered: either rising, if bit intedg (option_reg<6>) is set, or falling, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service rou- tine before re-enabling this interrupt. the int interrupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global inter- rupt enable bit gie decides whether or not the proces- sor branches to the interrupt vector following wake-up. see section 10.13 for details on sleep mode. 10.10.2 tmr0 interrupt an overflow (ffh ? 00h) in the tmr0 register will set flag bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>). (section 4.0) 10.10.3 portb intcon change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>). (section 3.2) 10.11 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt, (i.e., w register and status register). this will have to be implemented in software. example 10-1 stores and restores the w and status registers. the register, w_temp, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if w_temp is defined at 0x20 in bank 0, it must also be defined at 0xa0 in bank 1). the example: a) stores the w register. b) stores the status register in bank 0. c) stores the pclath register. d) executes the interrupt service routine code (user-generated). e) restores the status register (and bank select bit). f) restores the w and pclath registers. example 10-1: saving status, w, and pclath registers in ram movwf w_temp ;copy w to temp register, could be bank one or zero swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register : :(isr) : swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
pic16c62b/72a ds35008b-page 64 preliminary ? 1999 microchip technology inc. 10.12 watchdog timer (wdt) the watchdog timer is a free running on-chip rc oscil- lator which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. the wdt will run, even if the clock on the osc1/clkin and osc2/clkout pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the status register will be cleared upon a watchdog timer time-out. the wdt can be permanently disabled by clearing configuration bit wdte (section 10.1). the wdt time-out period (t wdt , parameter #31) is multiplied by the prescaler ratio, when the prescaler is assigned to the wdt. the prescaler assignment (assigned to either the wdt or timer0) and prescaler ratio are set in the option_reg register. . figure 10-8: watchdog timer block diagram figure 10-9: summary of watchdog timer registers note: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits boden cp1 cp0 pwrte wdte fosc1 fosc0 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. from tmr0 clock source (figure 4-2) to tmr0 (figure 4-2) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option_reg register. 8
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 65 10.13 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d and disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc , parameter d042). 10.13.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change, or some peripheral interrupts. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a "wake-up". the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ccp capture mode interrupt. 3. special event trigger (timer1 in asynchronous mode using an external clock. ccp1 is in com- pare mode). 4. ssp (start/stop) bit detect interrupt. 5. ssp transmit or receive in slave mode (spi/i 2 c). 6. usart rx or tx (synchronous slave mode). other peripherals cannot generate interrupts since dur- ing sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device resumes execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, a nop should follow the sleep instruction. 10.13.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
pic16c62b/72a ds35008b-page 66 preliminary ? 1999 microchip technology inc. figure 10-10: wake-up from sleep through interrupt 10.14 program verification/code protection if the code protection bits have not been programmed, the on-chip program memory can be read out for verifi- cation purposes. 10.15 id locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code-identification numbers. these locations are not accessible during normal execution, but are read- able and writable during program/verify. it is recom- mended that only the 4 least significant bits of the id location are used. for rom devices, these values are submitted along with the rom code. 10.16 in-circuit serial programming ? pic16cxxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three more lines for power, ground and the programming volt- age. this allows customers to manufacture boards with unprogrammed devices, and then program the micro- controller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. for complete details of serial programming, please refer to the in-circuit serial programming (icsp?) guide, ds30277. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout(4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will cont inue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference. note: microchip does not recommend code pro- tecting windowed devices.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 67 11.0 instruction set summary each pic16cxxx instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxx instruction set summary in table 11-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 11-1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file reg- ister designator and 'd' represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 11-1 opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 m s. table 11-2 lists the instructions recognized by the mpasm assembler. figure 11-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 11-1: general format for instructions a description of each instruction is available in the picmicro? mid-range reference manual, (ds33023). field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1 pc program counter to time-out bit pd power-down bit z zero bit dc digit carry bit c carry bit note: to maintain upward compatibility with future pic16cxxx products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c62b/72a ds35008b-page 68 preliminary ? 1999 microchip technology inc. table 11-2 pic16cxxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 69 11.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register . addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d ? [0,1] operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f' . andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are anded with the eight bit literal 'k'. the result is placed in the w register . andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f' . bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 ? (f) status affected: none description: bit 'b' in register 'f' is cleared . bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 ? (f) status affected: none description: bit 'b' in register 'f' is set.
pic16c62b/72a ds35008b-page 70 preliminary ? 1999 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit 'b' in register 'f' is '0', then the next instruction is executed. if bit 'b' is '1', then the next instruction is discarded and a nop is executed instead, making this a 2t cy instruc- tion. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit 'b' in register 'f' is '1', then the next instruction is executed. if bit 'b' in register 'f' is '0', then the next instruction is discarded, and a nop is executed instead, making this a 2t cy instruction . call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register 'f' are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits to and pd are set.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 71 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d ? [0,1] operation: (f ) ? (destination) status affected: z description: the contents of register 'f' are comple- mented. if 'd' is 0, the result is stored in w. if 'd' is 1, the result is stored back in register 'f'. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (destination) status affected: z description: decrement register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in regis- ter 'f' . decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register 'f' are decre- mented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. if the result is 1, the next instruction, is executed. if the result is 0, then a nop is executed instead making it a 2t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (destination) status affected: z description: the contents of register 'f' are incre- mented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register 'f' are incre- mented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. if the result is 1, the next instruction is executed. if the result is 0, a nop is executed instead making it a 2t cy instruction .
pic16c62b/72a ds35008b-page 72 preliminary ? 1999 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register is o red with the eight bit literal 'k'. the result is placed in the w register . iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with regis- ter 'f'. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d ? [0,1] operation: (f) ? (destination) status affected: z description: the contents of register f is moved to a destination dependant upon the sta- tus of d. if d = 0, destination is w reg- ister. if d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k ? (w) status affected: none description: the eight bit literal 'k' is loaded into w register . the dont cares will assem- ble as 0s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) ? (f) status affected: none description: move data from w register to register 'f' . nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 73 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is stored back in register 'f'. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 10.13 for more details. register f c register f c
pic16c62b/72a ds35008b-page 74 preliminary ? 1999 microchip technology inc. sublw subtract w from literal syntax: [ label ]sublw k operands: 0 k 255 operation: k - (w) ? ( w) status affected: c, dc, z description: the w register is subtracted (2s com- plement method) from the eight bit lit- eral 'k'. the result is placed in the w register. subwf subtract w from f syntax: [ label ]subwf f,d operands: 0 f 127 d ? [0,1] operation: (f) - (w) ? ( destination) status affected: c, dc, z description: subtract (2s complement method) w register from register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d ? [0,1] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of regis- ter 'f' are exchanged. if 'd' is 0, the result is placed in w register. if 'd' is 1, the result is placed in register 'f'. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ? ( w) status affected: z description: the contents of the w register are xored with the eight bit literal 'k'. the result is placed in the w regis- ter. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .xor. (f) ? ( destination) status affected: z description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in regis- ter 'f'.
? 1999 microchip technology inc. preliminary ds35008b-page 75 pic16c62b/72a 12.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab? ide software ? assemblers/compilers/linkers - mpasm assembler - mplab-c17 and mplab-c18 c compilers - mplink/mplib linker/librarian ? simulators - mplab-sim software simulator ?emulators - mplab-ice real-time in-circuit emulator - picmaster ? /picmaster-ce in-circuit emulator - icepic? ? in-circuit debugger - mplab-icd for pic16f877 ? device programmers -pro mate a ii universal programmer - picstart a plus entry-level prototype programmer ? low-cost demonstration boards - simice - picdem-1 - picdem-2 - picdem-3 - picdem-17 - seeval a -k ee l oq a 12.1 mplab integrated development environment software - the mplab ide software brings an ease of software development previously unseen in the 8-bit microcontroller market. mplab is a windows a -based application which contains: ? multiple functionality -editor - simulator - programmer (sold separately) - emulator (sold separately) ? a full featured editor ? a project manager ? customizable tool bar and key mapping ? a status bar ? on-line help mplab allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) ? debug using: - source files - absolute listing file - object code the ability to use mplab with microchips simulator, mplab-sim, allows a consistent platform and the abil- ity to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining. 12.2 mpasm assembler mpasm is a full featured universal macro assembler for all picmicro mcus. it can produce absolute code directly in the form of hex files for device program- mers, or it can generate relocatable objects for mplink. mpasm has a command line interface and a windows shell and can be used as a standalone application on a windows 3.x or greater system. mpasm generates relocatable object files, intel standard hex files, map files to detail memory usage and symbol reference, an absolute lst file which contains source lines and gen- erated machine code, and a cod file for mplab debugging. mpasm features include: ? mpasm and mplink are integrated into mplab projects. ? mpasm allows user defined macros to be created for streamlined assembly. ? mpasm allows conditional assembly for multi pur- pose source files. ? mpasm directives allow complete control over the assembly process. 12.3 mplab-c17 and mplab-c18 c compilers the mplab-c17 and mplab-c18 code development systems are complete ansi c compilers and inte- grated development environments for microchips pic17cxxx and pic18cxxx family of microcontrol- lers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display.
pic16c62b/72a ds35008b-page 76 preliminary ? 1999 microchip technology inc. 12.4 mplink/mplib linker/librarian mplink is a relocatable linker for mpasm and mplab-c17 and mplab-c18. it can link relocatable objects from assembly or c source files along with pre- compiled libraries using directives from a linker script. mplib is a librarian for pre-compiled code to be used with mplink. when a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. this allows large libraries to be used efficiently in many dif- ferent applications. mplib manages the creation and modification of library files. mplink features include: ? mplink works with mpasm and mplab-c17 and mplab-c18. ? mplink allows all memory areas to be defined as sections to provide link-time flexibility. mplib features include: ? mplib makes linking easier because single librar- ies can be included instead of many smaller files. ? mplib helps keep code maintainable by grouping related modules together. ? mplib commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. 12.5 mplab-sim software simulator the mplab-sim software simulator allows code development in a pc host environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. the execution can be performed in single step, execute until break, or trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mplab-c18 and mpasm. the soft- ware simulator offers the flexibility to develop and debug code outside of the laboratory environment mak- ing it an excellent multi-project software development tool. 12.6 mplab-ice high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of mplab-ice is provided by the mplab integrated development environment (ide), which allows editing, make and download, and source debugging from a single environment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support new picmicro microcon- trollers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc platform and microsoft ? windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. mplab-ice 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring fea- tures. both systems use the same processor modules and will operate across the full operating speed range of the picmicro mcu. 12.7 picmaster/picmaster ce the picmaster system from microchip technology is a full-featured, professional quality emulator system. this flexible in-circuit emulator provides a high-quality, universal platform for emulating microchip 8-bit picmicro microcontrollers (mcus). picmaster sys- tems are sold worldwide, with a ce compliant model available for european union (eu) countries. 12.8 icepic icepic is a low-cost in-circuit emulation solution for the microchip technology pic16c5x, pic16c6x, pic16c7x, and pic16cxxx families of 8-bit one-time- programmable (otp) microcontrollers. the modular system can support different subsets of pic16c5x or pic16cxxx products through the use of interchangeable personality modules or daughter boards. the emulator is capable of emulating without target application circuitry being present. 12.9 mplab-icd in-circuit debugger microchip's in-circuit debugger, mplab-icd, is a pow- erful, low-cost run-time development tool. this tool is based on the flash pic16f877 and can be used to develop for this and other picmicro microcontrollers from the pic16cxxx family. mplab-icd utilizes the in-circuit debugging capability built into the pic16f87x. this feature, along with microchip's in-cir- cuit serial programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. the mplab-icd is also a programmer for the flash pic16f87x family.
? 1999 microchip technology inc. preliminary ds35008b-page 77 pic16c62b/72a 12.10 pro mate ii universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode the pro mate ii can read, verify or program picmicro devices. it can also set code-protect bits in this mode. 12.11 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus supports all picmicro devices with up to 40 pins. larger pin count devices such as the pic16c92x, and pic17c76x may be supported with an adapter socket. picstart plus is ce compliant. 12.12 simice entry-level hardware simulator simice is an entry-level hardware development sys- tem designed to operate in a pc-based environment with microchips simulator mplab-sim. both simice and mplab-sim run under microchip technologys mplab integrated development environment (ide) software. specifically, simice provides hardware sim- ulation for microchips pic12c5xx, pic12ce5xx, and pic16c5x families of picmicro 8-bit microcontrollers. simice works in conjunction with mplab-sim to pro- vide non-real-time i/o port emulation. simice enables a developer to run simulator code for driving the target system. in addition, the target system can provide input to the simulator code. this capability allows for simple and interactive debugging without having to manually generate mplab-sim stimulus files. simice is a valu- able debugging tool for entry-level system develop- ment. 12.13 picdem-1 low-cost picmicro demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and download the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 12.14 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 12.15 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals.
pic16c62b/72a ds35008b-page 78 preliminary ? 1999 microchip technology inc. 12.16 picdem-17 the picdem-17 is an evaluation board that demon- strates the capabilities of several microchip microcon- trollers, including pic17c752, pic17c756, pic17c762, and pic17c766. all necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. a programmed sample is included, and the user may erase it and program it with the other sample programs using the pro mate ii or picstart plus device programmers and easily debug and test the sample code. in addition, picdem-17 sup- ports down-loading of programs to and executing out of external flash memory on board. the picdem-17 is also usable with the mplab-ice or picmaster emu- lator, and all of the sample programs can be run and modified using either emulator. additionally, a gener- ous prototype area is available for user hardware. 12.17 seeval evaluation and programming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can significantly reduce time-to-market and result in an optimized system. 12.18 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
? 1999 microchip technology inc. preliminary ds35008b-page 79 pic16c62b/72a table 12-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 compiler mplab ? c18 compiler mpasm/mplink emulators mplab ?-ice ** picmaster/picmaster-ce icepic ? low-cost in-circuit emulator debugger mplab-icd in-circuit debugger * * programmers picstart a plus low-cost universal dev. kit ** pro mate a ii universal programmer ** demo boards and eval kits simice picdem-1 ? picdem-2 ? ? picdem-3 picdem-14a picdem-17 k ee l oq ? evaluation kit k ee l oq transponder kit microid ? programmers kit 125 khz microid developers kit 125 khz anticollision microid developers kit 13.56 mhz anticollision microid developers kit mcp2510 can developers kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab-icd in-circuit deb ugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77 ** contact microchip technology inc. for availability date. ? development tool is available on select devices.
pic16c62b/72a ds35008b-page 80 preliminary ? 1999 microchip technology inc. notes:
? 1998 microchip technology inc. preliminary ds35008b-page 81 pic16c62b/72a 13.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ........... .-55c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr , and ra4).......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2).......................................................................................... 0v to +13.25v voltage on ra4 with respect to vss ............................................................................................. .................. 0v to +8.5v total power dissipation (note 1)............................................................................................... .................................1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta and portb (combined) .................................................................................200 ma maximum current sourced by porta and portb (combined).......................................................................... ..200 ma maximum current sunk by portc.................................................................................................. ......................200 ma maximum current sourced by portc ............................................................................................... ...................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) 2: voltage spikes below v ss at the mclr/ v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a low level to the mclr/ v pp pin, rather than pulling this pin directly to v ss . ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic16c62b/72a ds35008b-page 82 preliminary ? 1998 microchip technology inc. figure 13-1: pic16c62b/72a-20 voltage-frequency graph figure 13-2: pic16lc62b/72a and pic16c62b/72a/jw voltage-frequency graph frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 20 mhz 5.0 v 3.5 v 3.0 v 2.5 v pic16cxxx pic16cxxx-20 frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 10 mhz 5.0 v 3.5 v 3.0 v 2.5 v f max = (12.0 mhz/v) (v ddappmin - 2.5 v) + 4 mhz note: v ddappmin is the minimum voltage of the picmicro ? device in the application. 4 mhz pic16lcxxx-04 fmax is no greater than 10 mhz.
? 1998 microchip technology inc. preliminary ds35008b-page 83 pic16c62b/72a figure 13-3: pic16c62b/72a-04 voltage-frequency graph frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 5.0 v 3.5 v 3.0 v 2.5 v pic16cxxx-04 4 mhz
pic16c62b/72a ds35008b-page 84 preliminary ? 1998 microchip technology inc. 13.1 dc characteristics: pic16c62b/72a-04 (commercial, industrial, extended) pic16c62b/72a-20 (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions d001 d001a v dd supply voltage 4.0 4.5 v bor * - - - 5.5 5.5 5.5 v v v xt, rc and lp osc mode hs osc mode bor enabled (note 7) d002* v dr ram data retention voltag e (note 1) -1.5- v d003 v por v dd start voltage to ensure internal power-on reset signal -v ss - v see section on power-on reset for details d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 tbd - - - - v/ms pwrt enabled (pwrte bit clear) pwrt disabled (pwrte bit set) see section on power-on reset for details d005 v bor brown-out reset voltage trip point 3.65 - 4.35 v boden bit set d010 d013 i dd supply current (note 2, 5) - - 2.7 10 5 20 ma ma xt, rc osc modes f osc = 4 mhz, v dd = 5.5v (note 4) hs osc mode f osc = 20 mhz, v dd = 5.5v d020 d021 d021b i pd power-down current (note 3, 5) - - - - 10.5 1.5 1.5 2.5 42 16 19 19 m a m a m a m a v dd = 4.0v, wdt enabled,-40 c to +85 c v dd = 4.0v, wdt disabled, 0 c to +70 c v dd = 4.0v, wdt disabled,-40 c to +85 c v dd = 4.0v, wdt disabled,-40 c to +125 c d022* d022a* d i wdt d i bor module differential current (note 6) watchdog timer brown-out reset - - 6.0 tbd 20 200 m a m a wdte bit set , v dd = 4.0v boden bit set, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through rext is not included. the current through the resistor can be estimated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the specification. this value is from charac- terization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: this is the voltage where the device enters the brown-out reset. when bor is enabled, the device will perform a brown-out reset when v dd falls below v bor .
? 1998 microchip technology inc. preliminary ds35008b-page 85 pic16c62b/72a 13.2 dc characteristics: pic16lc62b/72a-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial -40c t a +85c for industrial param no. sym characteristic min typ? max units conditions d001 v dd supply voltage 2.5 v bor * - - 5.5 5.5 v v lp, xt, rc osc modes (dc - 4 mhz) bor enabled (note 7) d002* v dr ram data retention voltag e (note 1) -1.5- v d003 v por v dd start voltage to ensure internal power-on reset signal -v ss - v see section on power-on reset for details d004* d004a* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 tbd - - - - v/ms pwrt enabled (pwrte bit clear) pwrt disabled (pwrte bit set) see section on power-on reset for details d005 v bor brown-out reset voltage trip point 3.65 - 4.35 v boden bit set d010 d010a i dd supply current (note 2, 5) - - 2.0 22.5 3.8 48 ma m a xt, rc osc modes f osc = 4 mhz, v dd = 3.0v (note 4) lp osc mode f osc = 32 khz, v dd = 3.0v, wdt disabled d020 d021 d021a i pd power-down current (note 3, 5) - - - 7.5 0.9 0.9 30 5 5 m a m a m a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, 0 c to +70 c v dd = 3.0v, wdt disabled, -40 c to +85 c d022* d022a* d i wdt d i bor module differential current (note 6) watchdog timer brown-out reset - - 6.0 tbd 20 200 m a m a wdte bit set , v dd = 4.0v boden bit set, v dd = 5.0v * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc mode, current through rext is not included. the current through the resistor can be estimated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: timer1 oscillator (when enabled) adds approximately 20 m a to the specification. this value is from charac- terization and is for design guidance only. this is not tested. 6: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: this is the voltage where the device enters the brown-out reset. when bor is enabled, the device will perform a brown-out reset when v dd falls below v bor .
pic16c62b/72a ds35008b-page 86 preliminary ? 1998 microchip technology inc. 13.3 dc characteristics: pic16c62b/72a-04 (commercial, industrial, extended) pic16c62b/72a-20 (commercial, industrial, extended) pic16lc62b/72a-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc spec section 13.1 and section 13.2 param no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 d030a with ttl buffer v ss vss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger buffer v ss -0.2v dd v d032 mclr , osc1 (in rc mode) vss - 0.2v dd v d033 osc1 (in xt, hs and lp modes) vss - 0.3v dd v note1 input high voltage v ih i/o ports - d040 with ttl buffer 2.0 - v dd v4.5v v dd 5.5v d040a 0.25v d d + 0.8v - vdd v for entire v dd range d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr 0.8v dd -v dd v d042a osc1 (xt, hs and lp modes) 0.7v dd -v dd v note1 d043 osc1 (in rc mode) 0.9v dd -vddv input leakage current (notes 2, 3) d060 i il i/o ports - - 1 m avss v pin v dd , pin at hi-impedance d061 mclr , ra4/t0cki - - 5 m avss v pin v dd d063 osc1 - - 5 m avss v pin v dd , xt, hs and lp osc modes d070 i purb portb weak pull-up current 50 250 400 m av dd = 5v, v pin = v ss output low voltage d080 v ol i/o ports - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the device be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is defined as current sourced by the pin.
? 1998 microchip technology inc. preliminary ds35008b-page 87 pic16c62b/72a --0.6vi ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clkout (rc osc mode) --0.6vi ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c --0.6vi ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c output high voltage d090 v oh i/o ports (note 3) v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c v dd -0.7 - - v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clkout (rc osc mode) v dd -0.7 - - v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c v dd -0.7 - - v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150* v od open-drain high voltage - - 8.5 v ra4 pin capacitive loading specs on output pins d100 c osc2 osc2 pin - - 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 c io all i/o pins and osc2 (in rc mode) --50pf d102 cb scl, sda in i 2 c mode - - 400 pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc spec section 13.1 and section 13.2 param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator mode, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the device be driven with external clock in rc mode. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input volt- ages. 3: negative current is defined as current sourced by the pin.
pic16c62b/72a ds35008b-page 88 preliminary ? 1998 microchip technology inc. 13.4 ac (timing) characteristics 13.4.1 timing parameter symbology the timing parameter symbols have been created fol- lowing one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t ffrequency ttime lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
? 1998 microchip technology inc. preliminary ds35008b-page 89 pic16c62b/72a 13.4.2 timing conditions the temperature and voltages specified in table 13-1 apply to all timing specifications unless otherwise noted. figure 13-4 specifies the load conditions for the timing specifications. table 13-1: temperature and voltage specifications - ac figure 13-4: load conditions for device timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature 0c t a +70c for commercial -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc spec section 13.1 and section 13.2. lc parts operate for commercial/industrial temps only. v dd /2 c l r l pin pin v ss v ss c l r l =464 w c l = 50 pf for all pins except osc2/clkout 15 pf for osc2 output load condition 1 load condition 2
pic16c62b/72a ds35008b-page 90 preliminary ? 1998 microchip technology inc. 13.4.3 timing diagrams and specifications figure 13-5: external clock timing table 13-2: external clock timing requirements param no. sym characteristic min typ? max units conditions 1a fosc external clkin frequency (note 1) dc 4 mhz rc and xt osc modes dc 4 mhz hs osc mode (-04) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1 tosc external clkin period (note 1) 250 ns rc and xt osc modes 250 ns hs osc mode (-04) 50 ns hs osc mode (-20) 5 m slp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 50 250 ns hs osc mode (-20) 5 m slp osc mode 2 t cy instruction cycle time (note 1) 200 dc ns t cy = 4/f osc 3* to s l , to s h external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4* to s r , to s f external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. 3 3 4 4 1 2 q4 q1 q2 q3 q4 q1 osc1 clkout
? 1998 microchip technology inc. preliminary ds35008b-page 91 pic16c62b/72a figure 13-6: clkout and i/o timing table 13-3: clkout and i/o timing requirements param no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - tosc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0nsnote 1 17* to s h 2 i o v o s c 1 - (q1 cycle) to port out valid 50 150 ns 18* to s h 2 i o i o s c 1 - (q2 cycle) to port input invalid (i/o in hold time) pic16cxx 100 ns 18a* pic16lcxx 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time pic16cxx 10 40 ns 20a* pic16lcxx 80 ns 21* tiof port output fall time pic16cxx 10 40 ns 21a* pic16lcxx 80 ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ??these parameters are asynchronous events not related to any internal clock edge. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 13-4 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16c62b/72a ds35008b-page 92 preliminary ? 1998 microchip technology inc. figure 13-7: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 13-8: brown-out reset timing table 13-4: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements param no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m sv dd = 5v, -40c to +125c 31* twdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40c to +125c 32 tost oscillator start-up timer period 1024 t osc t osc = osc1 period 33* tpwrt power-up timer period 28 72 132 ms v dd = 5v, -40c to +125c 34 t ioz i/o hi-impedance from mclr low or wdt reset 2.1 m s 35 t bor brown-out reset pulse width 100 m sv dd b vdd (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 13-4 for load conditions. v dd bv dd 35
? 1998 microchip technology inc. preliminary ds35008b-page 93 pic16c62b/72a figure 13-9: timer0 and timer1 external clock timings table 13-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4,..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16cxx 15 ns pic16lcxx 25 ns asynchronous pic16cxx 30 ns pic16lcxx 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16cxx 15 ns pic16lcxx 25 ns asynchronous pic16cxx 30 ns pic16lcxx 50 ns 47* tt1p t1cki input period synchronous pic16cxx g reater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) pic16lcxx g reater of : 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous pic16cxx 60 ns pic16lcxx 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc 200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 13-4 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1
pic16c62b/72a ds35008b-page 94 preliminary ? 1998 microchip technology inc. figure 13-10: capture/compare/pwm timings table 13-6: capture/compare/pwm requirements param no. sym characteristic min typ? max units conditions 50* tccl ccp1 input low time no prescaler 0.5t cy + 20 ns with prescaler pic16cxx 10 ns pic16lcxx 20 ns 51* tcch ccp1 input high time no prescaler 0.5t cy + 20 ns with prescaler pic16cxx 10 ns pic16lcxx 20 ns 52* tccp ccp1 input period 3t cy + 40 n ns n = prescale value (1,4, or 16) 53* tccr ccp1 output rise time pic16cxx 1025ns pic16lcxx 2545ns 54* tccf ccp1 output fall time pic16cxx 1025ns pic16lcxx 2545ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 13-4 for load conditions. ccp1 (capture mode) 50 51 52 ccp1 53 54 (compare or pwm mode)
? 1998 microchip technology inc. preliminary ds35008b-page 95 pic16c62b/72a figure 13-11: example spi master mode timing (cke = 0) table 13-7: example spi mode requirements (master mode, cke = 0) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time pic16cxx 1025ns pic16lcxx 2045ns 76 tdof sdo data output fall time 10 25 ns 78 tscr sck output rise time (master mode) pic16cxx 1025ns pic16lcxx 2045ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16cxx 50ns pic16lcxx 100 ns ? data in typ column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 note: refer to figure 13-4 for load conditions.
pic16c62b/72a ds35008b-page 96 preliminary ? 1998 microchip technology inc. figure 13-12: example spi master mode timing (cke = 1) table 13-8: example spi mode requirements (master mode, cke = 1) param. no. symbol characteristic min typ? max units conditions 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time pic16cxx 1025ns pic16lcxx 20 45 ns 76 tdof sdo data output fall time 10 25 ns 78 tscr sck output rise time (master mode) pic16cxx 1025ns pic16lcxx 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16cxx 50 ns pic16lcxx 100 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ns ? data in typ column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb note: refer to figure 13-4 for load conditions.
? 1998 microchip technology inc. preliminary ds35008b-page 97 pic16c62b/72a figure 13-13: example spi slave mode timing (cke = 0) table 13-9: example spi mode requirements (slave mode timing (cke = 0) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time pic16cxx 1025ns pic16lcxx 20 45 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic16cxx 1025ns pic16lcxx 20 45 ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16cxx 50ns pic16lcxx 100 ns 83 tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 ns ? data in typ column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 note: refer to figure 13-4 for load conditions.
pic16c62b/72a ds35008b-page 98 preliminary ? 1998 microchip technology inc. figure 13-14: example spi slave mode timing (cke = 1) table 13-10: example spi slave mode requirements (cke = 1) param. no. symbol characteristic min typ? max units conditions 70 tssl2sch, tssl2scl ss to sck or sck - input t cy ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ns 71a single byte 40 ns note 1 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ns 72a single byte 40 ns note 1 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ns note 1 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ns 75 tdor sdo data output rise time pic16cxx 1025ns pic16lcxx 20 45 ns 76 tdof sdo data output fall time 10 25 ns 77 tssh2doz ss - to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic16cxx 1025ns pic16lcxx 2045ns 79 tscf sck output fall time (master mode) 10 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic16cxx 50ns pic16lcxx 100ns 82 tssl2dov sdo data output valid after ss edge pic16cxx 50ns pic16lcxx 100ns 83 tsch2ssh, tscl2ssh ss - after sck edge 1.5t cy + 40 ns ? data in typ column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: specification 73a is only required if specifications 71a and 72a are used. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 note: refer to figure 13-4 for load conditions.
? 1998 microchip technology inc. preliminary ds35008b-page 99 pic16c62b/72a figure 13-15: i 2 c bus start/stop bits timing table 13-11: i 2 c bus start/stop bits requirements parameter no. sym characteristic min ty p max unit s conditions 90* t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91* t hd : sta start condition 100 khz mode 4000 ns after this period the first clock pulse is generated hold time 400 khz mode 600 92* t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 * these parameters are characterized but not tested. note: refer to figure 13-4 for load conditions. 91 92 93 scl sda start condition stop condition 90
pic16c62b/72a ds35008b-page 100 preliminary ? 1998 microchip technology inc. figure 13-16: i 2 c bus data timing table 13-12: i 2 c bus data requirements param. no. sym characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 0.6 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 101* t low clock low time 100 khz mode 4.7 m s device must operate at a min- imum of 1.5 mhz 400 khz mode 1.3 m s device must operate at a min- imum of 10 mhz ssp module 1.5t cy 102* t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10-400 pf 103* t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10-400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 m s only relevant for repeated start condition 400 khz mode 0.6 m s 91* t hd : sta start condition hold time 100 khz mode 4.0 m s after this period the first clock pulse is generated 400 khz mode 0.6 m s 106* t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 m s 107* t su : dat data input setup time 100 khz mode 250 ns note 2 400 khz mode 100 ns 92* t su : sto stop condition setup time 100 khz mode 4.7 m s 400 khz mode 0.6 m s 109* t aa output valid from clock 100 khz mode 3500 ns note 1 400 khz mode ns 110* t buf bus free time 100 khz mode 4.7 m s time the bus must be free before a new transmission can start 400 khz mode 1.3 m s cb bus capacitive loading 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the fall- ing edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu:dat 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. i f such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. note: refer to figure 13-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
? 1998 microchip technology inc. preliminary ds35008b-page 101 pic16c62b/72a table 13-13: a/d converter characteristics: pic16c72a-04 (commercial, industrial, extended) pic16c72a-20 (commercial, industrial, extended) pic16lc72a-04 (commercial, industrial) param no. sym characteristic min typ? max units conditions a01 n r resolution 8-bits bit v ref = v dd = 5.12v, v ss v ain v ref a02 e abs total absolute error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 monotonicity guaranteed (note 3) v ss v ain v ref a20 v ref reference voltage 2.5v v dd + 0.3 v a25 v ain analog input voltage v ss - 0.3 v ref + 0.3 v a30 z ain recommended impedance of analog voltage source 10.0k w a40 i ad a/d conversion current (v dd ) pic16cxx 180 m a average current con- sumption when a/d is on. (note 1) pic16lcxx 90 m a a50 i ref v ref input current (note 2) 10 1000 10 m a m a during v ain acquisi- tion. based on differ- ential of v hold to v ain to charge c hold , see section 9.1. during a/d conver- sion cycle * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from ra3 pin or v dd pin, whichever is selected as reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
pic16c62b/72a ds35008b-page 102 preliminary ? 1998 microchip technology inc. figure 13-17: a/d conversion timing table 13-14: a/d conversion requirements param no. sym characteristic min typ? max unit s conditions 130 t ad a/d clock period pic16cxx 1.6 m st osc based, v ref 3 3.0v pic16lcxx 2.0 m st osc based, v ref full range pic16cxx 2.0 4.0 6.0 m sa/d rc mode pic16lcxx 3.0 6.0 9.0 m sa/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 11 11 t ad 132 t acq acquisition time note 2 5* 20 m s m s the minimum time is the amplifier settling time. this may be used if the "new" input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sam- pled voltage (as stated on c hold ). 134 t go q4 to a/d clock start t osc /2 if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 135 tswc switching from convert ? sample time 1.5 t ad * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 9.1 for min conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (tosc/2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 134
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 103 14.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'typical' represents the mean of the distribution at 25 c. 'max' or 'min' represents (mean + 3 s ) or (mean - 3 s ) respectively, where s is standard deviation, over the whole temperature range. graphs and tables not available at this time. data is not available at this time but you may reference the pic16c72 series data sheet (ds39016,) dc and ac char- acteristic section, which contains data similar to what is expected.
pic16c62b/72a ds35008b-page 104 preliminary ? 1999 microchip technology inc. notes:
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 105 15.0 packaging information 15.1 package marking information 28-lead soic xxxxxxxxxxxxxxxxxxxx aabbcde mmmmmmmmmmmmmmmm example pic16c62b-20/so xxxxxxxxxxxxxxx aabbcde 28-lead pdip (skinny dip) mmmmmmmmmmmm example pic16c72a-04/sp example 28-lead cerdip windowed xxxxxxxxxxx xxxxxxxxxxx aabbcde pic16c72a/jw aabbcde xxxxxxxxxxxx xxxxxxxxxxxx 28-lead ssop 20i/ss025 pic16c62b example 9917hat 9917cat 9910/saa 9917sbp xxxxxxxxxxx legend: mm...m microchip part number information xx...x customer specific information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week 01) c facility code of the plant at which wafer is manufactured o = outside vendor c = 5 line s = 6 line h = 8 line d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
pic16c62b/72a ds35008b-page 106 preliminary ? 1999 microchip technology inc. 15.2 28-lead skinny plastic dual in-line (sp) C 300 mil (pdip) 15 10 5 15 10 5 b mold draft angle bottom 15 10 5 15 10 5 a mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 8.51 7.80 7.09 .335 .307 .279 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb b e a p l a2 b b1 a a1 *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: mo-095 drawing no. c04-070
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 107 15.3 28-lead ceramic dual in-line with window (jw) C 300 mil (cerdip) 3.30 3.56 3.81 7.87 7.62 7.37 .310 .300 .290 w2 window length .150 .140 .130 w1 window width 10.80 9.78 8.76 .425 .385 .345 eb overall row spacing 0.53 0.47 0.41 .021 .019 .016 b lower lead width 1.65 1.46 1.27 .065 .058 .050 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.68 3.56 3.43 .145 .140 .135 l tip to seating plane 37.72 37.02 36.32 1.485 1.458 1.430 d overall length 7.49 7.37 7.24 .295 .290 .285 e1 ceramic pkg. width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.76 0.57 0.38 .030 .023 .015 a1 standoff 4.19 4.06 3.94 .165 .160 .155 a2 ceramic package height 4.95 4.64 4.32 .195 .183 .170 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n w2 w1 e1 e eb p a2 l b1 b a1 a *controlling parameter c jedec equivalent: mo-058 drawing no. c04-080
pic16c62b/72a ds35008b-page 108 preliminary ? 1999 microchip technology inc. 15.4 28-lead plastic small outline (so) C wide, 300 mil (soic) foot angle top f 048048 15 12 0 15 12 0 b mold draft angle bottom 15 12 0 15 12 0 a mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c b 45 h f a2 a a a1 *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 109 15.5 28-lead plastic shrink small outline (ss) C 209 mil, 5.30 mm (ssop) *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-150 drawing no. c04-073 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 a mold draft angle top 0.38 0.32 0.25 .015 .013 .010 b lead width 203.20 101.60 0.00 8 4 0 f foot angle 0.25 0.18 0.10 .010 .007 .004 c lead thickness 0.94 0.75 0.56 .037 .030 .022 l foot length 10.34 10.20 10.06 .407 .402 .396 d overall length 5.38 5.25 5.11 .212 .207 .201 e1 molded package width 8.10 7.85 7.59 .319 .309 .299 e overall width 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.83 1.73 1.63 .072 .068 .064 a2 molded package thickness 1.98 1.85 1.73 .078 .073 .068 a overall height 0.66 .026 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e1 e l b c f a a2 a1 a b
pic16c62b/72a ds35008b-page 110 preliminary ? 1999 microchip technology inc. notes:
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 111 appendix a: revision history appendix b: conversion considerations considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in ta bl e b - 1 . version date revision description a 7/98 this is a new data sheet. however, the devices described in this data sheet are the upgrades to the devices found in the pic16c6x data sheet , ds30234, and the pic16c7x data sheet , ds30390. table b-1: conversion considerations difference pic16c62a/72 pic16c62b/72a voltage range 2.5v - 6.0v 2.5v - 5.5v ssp module basic ssp (2 mode spi) ssp (4 mode spi) ccp module ccp does not reset tmr1 when in special event trigger mode. n/a timer1 module writing to tmr1l register can cause over- flow in tmr1h register. n/a
pic16c62b/72a ds35008b-page 112 preliminary ? 1999 microchip technology inc. appendix c: migration from base-line to mid-range devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to a mid-range device (i.e., pic16cxxx). the following are the list of modifications over the pic16c5x microcontroller family: 1. instruction word length is increased to 14-bits. this allows larger page sizes both in program memory (2k now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before). 2. a pc high latch register (pclath) is added to handle program memory paging. bits pa2, pa1, pa0 are removed from status register. 3. data memory paging is redefined slightly. status register is modified. 4. four new instructions have been added: return, retfie, addlw , and sublw . two instructions tris and option are being phased out although they are kept for compati- bility with pic16c5x. 5. option_reg and tris registers are made addressable. 6. interrupt capability is added. interrupt vector is at 0004h. 7. stack size is increased to 8 deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revisited. five different reset (and wake-up) types are recognized. reg- isters are reset differently. 10. wake up from sleep through interrupt is added. 11. two separate timers, oscillator start-up timer (ost) and power-up timer (pwrt) are included for more reliable power-up. these tim- ers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt on change feature. 13. t0cki pin is also a port pin (ra4) now. 14. fsr is made a full eight bit register. 15. in-circuit serial programming is made possible. the user can program pic16cxx devices using only five pins: v dd , v ss , mclr /v pp , rb6 (clock) and rb7 (data in/out). 16. pcon status register is added with a power-on reset status bit (por ). 17. code protection scheme is enhanced such that portions of the program memory can be pro- tected, while the remainder is unprotected. 18. brown-out protection circuitry has been added. controlled by configuration word bit boden. brown-out reset ensures the device is placed in a reset condition if v dd dips below a fixed set- point. to convert code written for pic16c5x to pic16cxxx, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. redefine data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h.
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 113 index a a/d ..................................................................................... 49 a/d converter enable (adie bit) ............................... 14 a/d converter flag (adif bit) ............................ 15 , 51 a/d converter interrupt, configuring ......................... 51 adcon0 register ................................................ 9 , 49 adcon1 register ........................................10 , 49 , 50 adres register .............................................9 , 49 , 51 analog port pins .......................................................... 6 analog port pins, configuring ................................... 53 block diagram ........................................................... 51 block diagram, analog input model .......................... 52 channel select (chs2:chs0 bits) ............................ 49 clock select (adcs1:adcs0 bits) ........................... 49 configuring the module ............................................. 51 conversion clock (t ad ) ............................................. 53 conversion status (go/done bit) ..................... 49 , 51 conversions ............................................................... 54 converter characteristics ........................................ 101 module on/off (adon bit) ........................................ 49 port configuration control (pcfg2:pcfg0 bits) ...... 50 sampling requirements ............................................ 52 special event trigger (ccp) .............................. 35 , 54 timing diagram ....................................................... 102 absolute maximum ratings ............................................... 81 adcon0 register ........................................................ 9 , 49 adcs1:adcs0 bits ................................................... 49 adon bit ................................................................... 49 chs2:chs0 bits ....................................................... 49 go/done bit ..................................................... 49 , 51 adcon1 register ................................................10 , 49 , 50 pcfg2:pcfg0 bits ................................................... 50 adres register .....................................................9 , 49 , 51 architecture pic16c62b/pic16c72a block diagram ..................... 5 assembler mpasm assembler ................................................... 75 b banking, data memory ................................................. 8 , 11 brown-out reset (bor) .......................... 55 , 57 , 59 , 60 , 61 bor enable (boden bit) ......................................... 55 bor status (bor bit) ............................................... 16 timing diagram ......................................................... 92 c capture (ccp module) ...................................................... 34 block diagram ........................................................... 34 ccp pin configuration .............................................. 34 ccpr1h:ccpr1l registers .................................... 34 changing between capture prescalers .................... 34 software interrupt ...................................................... 34 timer1 mode selection .............................................. 34 capture/compare/pwm interaction of two ccp modules ............................... 33 capture/compare/pwm (ccp) ......................................... 33 ccp1con register .............................................. 9 , 33 ccpr1h register ................................................ 9 , 33 ccpr1l register ................................................. 9 , 33 enable (ccp1ie bit) .................................................. 14 flag (ccp1if bit) ...................................................... 15 rc2/ccp1 pin ............................................................. 6 timer resources ....................................................... 33 timing diagram ......................................................... 94 ccp1con register .......................................................... 33 ccp1m3:ccp1m0 bits ............................................. 33 ccp1x:ccp1y bits .................................................. 33 code protection ...........................................................55 , 66 cp1:cp0 bits ............................................................ 55 compare (ccp module) .................................................... 35 block diagram ........................................................... 35 ccp pin configuration .............................................. 35 ccpr1h:ccpr1l registers .................................... 35 software interrupt ...................................................... 35 special event trigger ................................... 29 , 35 , 54 timer1 mode selection ............................................. 35 configuration bits .............................................................. 55 conversion considerations ............................................. 111 d data memory ....................................................................... 8 bank select (rp1:rp0 bits) ..................................8 , 11 general purpose registers ......................................... 8 register file map ........................................................ 8 special function registers ......................................... 9 dc characteristics ......................................................84 , 86 development support ........................................................ 75 direct addressing .............................................................. 18 e electrical characteristics ................................................... 81 errata ................................................................................... 3 external power-on reset circuit ....................................... 59 f firmware instructions ........................................................ 67 i i/o ports ............................................................................ 19 i 2 c (ssp module) .............................................................. 41 ack pulse .......................................41 , 42 , 43 , 44 , 45 addressing ................................................................ 42 block diagram ........................................................... 41 buffer full status (bf bit) ......................................... 46 clock polarity select (ckp bit) ................................. 47 data/address (d/a bit) .............................................. 46 master mode ............................................................. 45 mode select (sspm3:sspm0 bits) .......................... 47 multi-master mode .................................................... 45 read/write bit information (r/w bit) .... 42 , 43 , 44 , 46 receive overflow indicator (sspov bit) .................. 47 reception .................................................................. 43 reception timing diagram ........................................ 43 slave mode ............................................................... 41 start (s bit) ..........................................................45 , 46 stop (p bit) ..........................................................45 , 46 synchronous serial port enable (sspen bit) .......... 47 timing diagram, data ............................................. 100 timing diagram, start/stop bits ................................ 99 transmission ............................................................. 44 update address (ua bit) ........................................... 46 id locations ................................................................55 , 66 in-circuit serial programming (icsp) .........................55 , 66 indirect addressing ............................................................ 18 fsr register .................................................... 8 , 9 , 18 indf register ............................................................. 9 instruction format ............................................................. 67
pic16c62b/72a ds35008b-page 114 preliminary ? 1999 microchip technology inc. instruction set .................................................................... 67 addlw ...................................................................... 69 addwf ...................................................................... 69 andlw ...................................................................... 69 andwf ...................................................................... 69 bcf ............................................................................ 69 bsf ............................................................................ 69 btfsc ....................................................................... 70 btfss ....................................................................... 70 call .......................................................................... 70 clrf ......................................................................... 70 clrw ......................................................................... 70 clrwdt ................................................................... 70 comf ........................................................................ 71 decf ......................................................................... 71 decfsz .................................................................... 71 goto ........................................................................ 71 incf .......................................................................... 71 incfsz ...................................................................... 71 iorlw ....................................................................... 72 iorwf ....................................................................... 72 movf ........................................................................ 72 movlw ..................................................................... 72 movwf ..................................................................... 72 nop ........................................................................... 72 retfie ...................................................................... 73 retlw ...................................................................... 73 return .................................................................... 73 rlf ............................................................................ 73 rrf ........................................................................... 73 sleep ....................................................................... 73 sublw ...................................................................... 74 subwf ...................................................................... 74 swapf ...................................................................... 74 xorlw ...................................................................... 74 xorwf ..................................................................... 74 summary table ......................................................... 68 intcon register .......................................................... 9 , 13 gie bit ....................................................................... 13 inte bit ..................................................................... 13 intf bit ...................................................................... 13 peie bit ..................................................................... 13 rbie bit ..................................................................... 13 rbif bit .............................................................. 13 , 21 t0ie bit ...................................................................... 13 t0if bit ...................................................................... 13 interrupt sources ........................................................ 55 , 62 a/d conversion complete ......................................... 51 block diagram ........................................................... 62 capture complete (ccp) ........................................... 34 compare complete (ccp) ......................................... 35 interrupt on change (rb7:rb4 ) ............................... 21 rb0/int pin, external ........................................... 6 , 63 ssp receive/transmit complete .............................. 39 tmr0 overflow ................................................... 26 , 63 tmr1 overflow ................................................... 27 , 29 tmr2 to pr2 match .................................................. 32 tmr2 to pr2 match (pwm) ............................... 31 , 36 interrupts, context saving during ...................................... 63 interrupts, enable bits a/d converter enable (adie bit) ............................... 14 ccp1 enable (ccp1ie bit) ....................................... 14 global interrupt enable (gie bit) ........................ 13 , 62 interrupt on change (rb7:rb4) enable (rbie bit) ................................................ 13 , 63 peripheral interrupt enable (peie bit) ....................... 13 rb0/int enable (inte bit) ........................................ 13 ssp enable (sspie bit) ............................................ 14 tmr0 overflow enable (t0ie bit) ............................. 13 tmr1 overflow enable (tmr1ie bit) ....................... 14 tmr2 to pr2 match enable (tmr2ie bit) ................ 14 interrupts, flag bits a/d converter flag (adif bit) .............................15 , 51 ccp1 flag (ccp1if bit) .............................. 15 , 34 , 35 interrupt on change (rb7:rb4) flag (rbif bit) .............................................. 13 , 21 , 63 rb0/int flag (intf bit) ............................................ 13 ssp flag (sspif bit) ................................................ 15 tmr0 overflow flag (t0if bit) ...........................13 , 63 tmr1 overflow flag (tmr1if bit) ............................ 15 tmr2 to pr2 match flag (tmr2if bit) .................... 15 k keeloq evaluation and programming tools .................. 78 m master clear (mclr ) .......................................................... 6 mclr reset, normal operation .................. 57 , 60 , 61 mclr reset, sleep ................................... 57 , 60 , 61 memory organization data memory ............................................................... 8 program memory ......................................................... 7 mplab integrated development environment software .. 75 o opcode field descriptions ............................................. 67 option_reg register ..............................................10 , 12 intedg bit ................................................................ 12 ps2:ps0 bits .......................................................12 , 25 psa bit ................................................................12 , 25 rbpu bit ................................................................... 12 t0cs bit ..............................................................12 , 25 t0se bit ..............................................................12 , 25 osc1/clkin pin ................................................................. 6 osc2/clkout pin .............................................................. 6 oscillator configuration ...............................................55 , 56 hs .......................................................................56 , 60 lp ........................................................................56 , 60 rc .................................................................. 6 , 57 , 60 selection (fosc1:fosc0 bits).................................. 55 xt ........................................................................56 , 60 oscillator, timer1 ........................................................27 , 29 oscillator, wdt ................................................................. 64 p packaging ........................................................................ 105 paging, program memory .............................................7 , 17 pcon register ............................................................16 , 60 bor bit ..................................................................... 16 por bit ..................................................................... 16 picdem-1 low-cost picmicro demo board .................... 77 picdem-2 low-cost pic16cxx demo board ................. 77 picdem-3 low-cost pic16cxxx demo board ............... 77 picstart plus entry level development system ........ 77 pie1 register ..............................................................10 , 14 adie bit ..................................................................... 14 ccp1ie bit ................................................................ 14 sspie bit ................................................................... 14 tmr1ie bit ................................................................ 14 tmr2ie bit ................................................................ 14 pinout descriptions pic16c62b/pic16c72a ............................................. 6
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 115 pir1 register ............................................................... 9 , 15 adif bit ..................................................................... 15 ccp1if bit ................................................................. 15 sspif bit ................................................................... 15 tmr1if bit ................................................................ 15 tmr2if bit ................................................................ 15 pointer, fsr ...................................................................... 18 porta ................................................................................ 6 analog port pins .......................................................... 6 porta register ................................................... 9 , 19 ra3:ra0 and ra5 port pins ..................................... 19 ra4/t0cki pin ..................................................... 6 , 19 ra5/ss /an4 pin ................................................... 6 , 39 trisa register ................................................... 10 , 19 portb ................................................................................ 6 portb register ................................................... 9 , 21 pull-up enable (rbpu bit) ......................................... 12 rb0/int edge select (intedg bit) .......................... 12 rb0/int pin, external .......................................... 6 , 63 rb3:rb0 port pins .................................................... 21 rb7:rb4 interrupt on change ................................... 63 rb7:rb4 interrupt on change enable (rbie bit) ............................................... 13 , 63 rb7:rb4 interrupt on change flag (rbif bit) ..............................................13 , 21 , 63 rb7:rb4 port pins .................................................... 21 trisb register ................................................... 10 , 21 portc ................................................................................ 6 block diagram ........................................................... 23 portc register ................................................... 9 , 23 rc0/t1oso/t1cki pin ............................................... 6 rc1/t1osi pin ............................................................ 6 rc2/ccp1 pin ............................................................. 6 rc3/sck/scl pin ................................................ 6 , 39 rc4/sdi/sda pin ................................................. 6 , 39 rc5/sdo pin ....................................................... 6 , 39 rc6 pin ....................................................................... 6 rc7 pin ....................................................................... 6 trisc register .................................................. 10 , 23 postscaler, timer2 select (toutps3:toutps0 bits) ............................ 31 postscaler, wdt ................................................................ 25 assignment (psa bit) ......................................... 12 , 25 block diagram ........................................................... 26 rate select (ps2:ps0 bits) ................................ 12 , 25 switching between timer0 and wdt ........................ 26 power-on reset (por) ........................... 55 , 57 , 59 , 60 , 61 oscillator start-up timer (ost) .......................... 55 , 59 por status (por bit) ............................................... 16 power control (pcon) register ................................ 60 power-down (pd bit) .......................................... 11 , 57 power-on reset circuit, external .............................. 59 power-up timer (pwrt) .................................... 55 , 59 pwrt enable (pwrte bit) ...................................... 55 time-out (to bit) ................................................ 11 , 57 time-out sequence ................................................... 60 timing diagram ......................................................... 92 prescaler, capture ............................................................. 34 prescaler, timer0 .............................................................. 25 assignment (psa bit) ......................................... 12 , 25 block diagram ........................................................... 26 rate select (ps2:ps0 bits) ................................ 12 , 25 switching between timer0 and wdt ........................ 26 prescaler, timer1 .............................................................. 28 select (t1ckps1:t1ckps0 bits)............................... 27 prescaler, timer2 .............................................................. 36 select (t2ckps1:t2ckps0 bits) ............................. 31 pro mate ii universal programmer ............................. 77 program counter pcl register .........................................................9 , 17 pclath register ........................................... 9 , 17 , 63 reset conditions ....................................................... 60 program memory ................................................................. 7 interrupt vector ........................................................... 7 paging ...................................................................7 , 17 program memory map ................................................ 7 reset vector ............................................................... 7 program verification .......................................................... 66 programming pin (vpp) ....................................................... 6 programming, device instructions .................................... 67 pwm (ccp module) .......................................................... 36 block diagram ........................................................... 36 ccpr1h:ccpr1l registers .................................... 36 duty cycle ................................................................. 36 example frequencies/resolutions ............................ 37 output diagram ......................................................... 36 period ........................................................................ 36 set-up for pwm operation ....................................... 37 tmr2 to pr2 match ............................................31 , 36 tmr2 to pr2 match enable (tmr2ie bit) ................ 14 tmr2 to pr2 match flag (tmr2if bit) .................... 15 q q-clock ............................................................................. 36 r register file ........................................................................ 8 register file map ................................................................ 8 reset ...........................................................................55 , 57 block diagram ........................................................... 58 reset conditions for all registers ............................ 61 reset conditions for pcon register ........................ 60 reset conditions for program counter ..................... 60 reset conditions for status register .................... 60 timing diagram ......................................................... 92 revision history .............................................................. 111 s seeval evaluation and programming system ............. 78 sleep .................................................................. 55 , 57 , 65 software simulator (mplab-sim) ..................................... 76 special features of the cpu ............................................. 55 special function registers .................................................. 9 speed, operating ................................................................ 1 spi (ssp module) block diagram ........................................................... 39 buffer full status (bf bit) ......................................... 46 clock edge select (cke bit) ..................................... 46 clock polarity select (ckp bit) ................................. 47 data input sample phase (smp bit) ......................... 46 mode select (sspm3:sspm0 bits) .......................... 47 receive overflow indicator (sspov bit) .................. 47 serial clock (rc3/sck/scl) .................................... 39 serial data in (rc4/sdi/sda) .................................. 39 serial data out (rc5/sdo) ...................................... 39 slave select (ra5/ss /an4) ...................................... 39 synchronous serial port enable (sspen bit) .......... 47
pic16c62b/72a ds35008b-page 116 preliminary ? 1999 microchip technology inc. ssp .................................................................................... 39 enable (sspie bit) .................................................... 14 flag (sspif bit) ......................................................... 15 ra5/ss /an4 pin .......................................................... 6 rc3/sck/scl pin ....................................................... 6 rc4/sdi/sda pin ........................................................ 6 rc5/sdo pin ............................................................... 6 sspadd register ...................................................... 10 sspbuf register ........................................................ 9 sspcon register ................................................ 9 , 47 sspstat register ............................................. 10 , 46 tmr2 output for clock shift ...................................... 32 write collision detect (wcol bit) ............................. 47 sspcon register ............................................................. 47 ckp bit ...................................................................... 47 sspen bit ................................................................. 47 sspm3:sspm0 bits .................................................. 47 sspov bit ................................................................. 47 wcol bit ................................................................... 47 sspstat register ............................................................ 46 bf bit ......................................................................... 46 cke bit ...................................................................... 46 d/a bit ........................................................................ 46 p bit ..................................................................... 45 , 46 r/w bit ................................................... 42 , 43 , 44 , 46 s bit .................................................................... 45 , 46 smp bit ...................................................................... 46 ua bit ......................................................................... 46 stack .................................................................................. 17 status register ...................................................9 , 11 , 63 c bit ........................................................................... 11 dc bit ........................................................................ 11 irp bit ........................................................................ 11 pd bit .................................................................. 11 , 57 rp1:rp0 bits ............................................................. 11 to bit .................................................................. 11 , 57 z bit ........................................................................... 11 t t1con register ........................................................... 9 , 27 t1ckps1:t1ckps0 bits ........................................... 27 t1oscen bit ............................................................. 27 t1sync bit ............................................................... 27 tmr1cs bit ............................................................... 27 tmr1on bit .............................................................. 27 t2con register ........................................................... 9 , 31 t2ckps1:t2ckps0 bits ........................................... 31 tmr2on bit .............................................................. 31 toutps3:toutps0 bits .......................................... 31 timer0 ................................................................................ 25 block diagram ........................................................... 25 clock source edge select (t0se bit) ................ 12 , 25 clock source select (t0cs bit) .......................... 12 , 25 overflow enable (t0ie bit) ........................................ 13 overflow flag (t0if bit) ...................................... 13 , 63 overflow interrupt ............................................... 26 , 63 ra4/t0cki pin, external clock ................................... 6 timing diagram ......................................................... 93 tmr0 register ............................................................. 9 timer1 ............................................................................... 27 block diagram ........................................................... 28 capacitor selection ................................................... 29 clock source select (tmr1cs bit) ........................... 27 external clock input sync (t1sync bit) .................. 27 module on/off (tmr1on bit) ................................... 27 oscillator .............................................................27 , 29 oscillator enable (t1oscen bit) .............................. 27 overflow enable (tmr1ie bit) .................................. 14 overflow flag (tmr1if bit) ....................................... 15 overflow interrupt ................................................27 , 29 rc0/t1oso/t1cki pin ............................................... 6 rc1/t1osi .................................................................. 6 special event trigger (ccp) ...............................29 , 35 t1con register ....................................................9 , 27 timing diagram ......................................................... 93 tmr1h register .......................................................... 9 tmr1l register .......................................................... 9 timer2 block diagram ........................................................... 32 pr2 register ................................................ 10 , 31 , 36 ssp clock shift ......................................................... 32 t2con register ....................................................9 , 31 tmr2 register ......................................................9 , 31 tmr2 to pr2 match enable (tmr2ie bit) ................ 14 tmr2 to pr2 match flag (tmr2if bit) .................... 15 tmr2 to pr2 match interrupt ...................... 31 , 32 , 36 timing diagrams i 2 c reception (7-bit address) ................................... 43 wake-up from sleep via interrupt ........................... 66 timing diagrams and specifications ................................. 90 a/d conversion ....................................................... 102 brown-out reset (bor) ............................................ 92 capture/compare/pwm (ccp) ................................. 94 clkout and i/o ....................................................... 91 external clock ........................................................... 90 i 2 c bus data ........................................................... 100 i 2 c bus start/stop bits .............................................. 99 oscillator start-up timer (ost) ................................. 92 power-up timer (pwrt) ........................................... 92 reset ........................................................................... 2 timer0 and timer1 .................................................... 93 watchdog timer (wdt) ............................................ 92 w w register ......................................................................... 63 wake-up from sleep .................................................55 , 65 interrupts .............................................................60 , 61 mclr reset .............................................................. 61 timing diagram ......................................................... 66 wdt reset ................................................................ 61 watchdog timer (wdt) ..............................................55 , 64 block diagram ........................................................... 64 enable (wdte bit) ..............................................55 , 64 programming considerations .................................... 64 rc oscillator ............................................................. 64 timing diagram ......................................................... 92 wdt reset, normal operation .................... 57 , 60 , 61 wdt reset, sleep ..................................... 57 , 60 , 61 www, on-line support ...................................................... 3
pic16c62b/72a ? 1999 microchip technology inc. preliminary ds35008b-page 117 on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ?device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development sys- tems, technical information and more ? listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom, mplab and fuzzy- lab are trademarks and sqtp is a service mark of micro- chip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. 981103
pic16c62b/72a ds35008b-page 118 preliminary 1998 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds35008b pic16c62b/72a
1998 microchip technology inc. preliminary ds35008b-page 119 pic16c62b/72a pic16c62b/72a product identification system to order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type (including lc devices). sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. -xx x /xx xxx pattern: qtp, sqtp, code or special requirements package: jw = windowed cerdip so = soic sp = skinny plastic dip p=pdip ss = ssop temperature range: -=0 c to +70 c i=-40 c to +85 c e=-40 c to +125 c frequency range: 04 = 4 mhz 10 = 10 mhz 20 = 20 mhz device pic16c62b: v dd range 4.0v to 5.5v pic16c62bt: v dd range 4.0v to 5.5v (tape/reel) pic16lc62b: v dd range 2.5v to 5.5v pic16lc62bt: v dd range 2.5v to 5.5v (tape/reel) examples a) pic16c72a-04/p 301 commercial temp., pdip package, 4 mhz, normal v dd limits, qtp pattern #301 b)
? 2002 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on picmicro ? mcus. the picmicro family meets the specifications contained in the microchip data sheet. microchip believes that its family of picmicro microcontrollers is one of the most secure products of its kind on the market to day, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowl - edge, require using the picmicro microcontroller in a manner outside the operating specifications contained in the data sheet. the person doing so may be engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ? unbreakable ? . code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our product. if you have any further questions about this matter, please contact the local sales office nearest to you.
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