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| h8s/2237 series h8s/2227 series overview ade- rev. 0.2 nov. 13, 1997 hitachi, ltd. mc-setsu
notice when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. preface hitachis h8s family of single-chip microcomputers comprises a number of new series offering the high performance and low power consumption of the existing h8 series, which is widely used for machine control, etc., together with significantly greater ease of use. the h8s/2000 series features cpu object-level compatibility with the h8/300h series, h8/300 series, and h8/300l series within the h8 series. series features h8s/2000 upward-compatible with the h8/300h series and h8/300 series; twice the performance at the same frequency h8/300h 16-mbyte linear address space; upward-compatible with the h8/300 series; concise instruction set; powerful word-size and longword-size arithmetic instructions h8/300 64-kbyte address space; general register system; concise instruction set; powerful bit manipulation instructions h8/300l same cpu as the h8/300 series; consumer application oriented supporting modules; low voltage, low power consumption this document gives an overview of the new h8s/2000 series products, which is suitable for single chip application in the h8s series. intended readership: this overview is intended for readers who have a basic understanding of microcomputers, and are looking for information on the features and functions of the h8s/2237, and h8s/2227 series. readers undertaking system design using these products, or requiring more detailed information on their use, should refer to the relevant hardware manuals and the h8s/2600 and h8s/2000 series programming manual. related documents contents title document no. h8s/2237 series and h8s/2227 series hardware h8s/2237 series and h8s/2227 series hardware manual tbd (scheduled publication: 5/98) h8s/2000 series execution instructions h8s/2600 series and h8s/2000 series programming manual ade-602-083a the product specifications in this overview are subject to change without notice. the relevant hardware manual must be used when undertaking product design. on-chip supporting modules series h8s/2237 series h8s/2227 series product names h8s/2237, 2235, 2233 h8s/2227, 2225, 2223 bus controller (bsc) available (16-bit) available (16-bit) data transfer controller (dtc) available available 16-bit timer pulse unit (tpu) 6 3 8-bit timer (tmr) 2 2 watchdog timer (wdt) 2 2 serial communication interface (sci) 4 3 a/d converter 8 8 d/a converter 2 pc break controller 2 2 i contents section 1 features of h8s/2237 series and h8s/2227 series ............................. 1 1.1 features of h8s/2237 series and h8s/2227 series .......................................................... 1 1.1.1 high-performance h8s/2000 cpu ...................................................................... 1 1.2 pin arrangement and functions ........................................................................................ 5 1.2.1 h8s/2237 series pin arrangement ...................................................................... 5 1.2.2 h8s/2227 series pin arrangement ...................................................................... 7 1.3 internal block diagram ..................................................................................................... 11 section 2 cpu ..................................................................................................................... 13 2.1 overview............................................................................................................................ 13 2.1.1 features ................................................................................................................ 13 2.2 register configuration ...................................................................................................... 16 2.3 data formats...................................................................................................................... 19 2.4 addressing modes ............................................................................................................. 22 2.5 instruction set.................................................................................................................... 26 2.6 basic timing...................................................................................................................... 38 2.7 processing states ............................................................................................................... 42 2.8 exception handling ........................................................................................................... 44 2.9 interrupts............................................................................................................................ 46 2.10 mcu operating modes ..................................................................................................... 51 2.11 address maps .................................................................................................................... 53 section 3 supporting modules ....................................................................................... 56 3.1 pc break controller (pbc) ............................................................................................... 56 3.1.1 features ................................................................................................................ 56 3.2 bus controller (bsc) ........................................................................................................ 58 3.2.1 features ................................................................................................................ 58 3.2.2 area partitioning .................................................................................................. 60 3.2.3 bus specifications ................................................................................................ 61 3.2.4 memory interfaces................................................................................................ 61 3.3 data transfer controller (dtc)........................................................................................ 66 3.3.1 features ................................................................................................................ 66 3.3.2 data transfer operation ....................................................................................... 68 3.4 16-bit timer pulse unit (tpu) ......................................................................................... 78 3.4.1 features ................................................................................................................ 78 3.4.2 interrupt sources and data transfer controller (dtc) activation...................... 82 3.4.3 operation .............................................................................................................. 83 3.4.4 pwm modes ........................................................................................................ 84 3.4.5 input capture operation ....................................................................................... 85 ii 3.5 8-bit timer (tmr)............................................................................................................ 91 3.5.1 features ................................................................................................................ 91 3.5.2 interrupt source and data transfer controller (dtc) activation ....................... 93 3.5.3 example of pulse output...................................................................................... 93 3.6 watchdog timer (wdt) ................................................................................................... 94 3.6.1 features ................................................................................................................ 94 3.6.2 block diagram...................................................................................................... 95 3.7 serial communication interface (sci).............................................................................. 99 3.7.1 features ................................................................................................................ 99 3.7.2 block diagram...................................................................................................... 100 3.8 smart card interface.......................................................................................................... 107 3.8.1 features ................................................................................................................ 107 3.8.2 operation .............................................................................................................. 108 3.8.3 schematic connection diagram ........................................................................... 109 3.8.4 data format.......................................................................................................... 109 3.9 a/d converter ................................................................................................................... 110 3.9.1 features ................................................................................................................ 110 3.10 d/a converter ................................................................................................................... 113 3.10.1 features ................................................................................................................ 113 3.10.2 operation .............................................................................................................. 113 3.10.3 d/a converter block diagram ............................................................................ 114 3.11 i/o ports............................................................................................................................. 114 3.12 ram .................................................................................................................................. 121 3.12.1 features ................................................................................................................ 122 3.13 rom .................................................................................................................................. 123 section 4 power-down modes ...................................................................................... 124 section 5 development environment .......................................................................... 129 5.1 development environment................................................................................................ 129 5.1.1 lineup................................................................................................................... 129 5.2 cross software................................................................................................................... 130 5.3 emulators........................................................................................................................... 132 5.4 socket adapters ................................................................................................................. 134 5.5 hi series os ...................................................................................................................... 135 appendix .............................................................................................................................. 137 a.1 packages ............................................................................................................... 137 figures figure 1.1 100-pin plastic tqfp (tfp100b, tfp-100g), 100-pin plastic qfp (fp-100b) ... 5 figure 1.2 100-pin plastic qfp (fp-100a).............................................................................. 6 figure 1.3 100-pin plastic tqfp (tfp-100b, tfp-100g), 100-pin plastic qfp (fp-100b).. 7 iii figure 1.4 100-pin plastic qfp (fp-100a).............................................................................. 8 figure 1.5 internal block diagram of h8s/2237 series .......................................................... 11 figure 1.6 internal block diagram of h8s/2227 series .......................................................... 12 figure 2.1 cpu registers......................................................................................................... 16 figure 2.2 usage of general registers .................................................................................... 17 figure 2.3 general register data formats............................................................................... 19 figure 2.4 memory data formats............................................................................................ 21 figure 2.5 basic clock timing ................................................................................................ 38 figure 2.6 on-chip memory access cycle (one-state access).............................................. 39 figure 2.7 pin states during on-chip memory access .......................................................... 39 figure 2.8 on-chip supporting module access cycle (two-state access)............................ 40 figure 2.9 pin states during on-chip supporting module access.......................................... 41 figure 2.10 state transition diagram........................................................................................ 43 figure 2.11 block diagram of interrupt controller ................................................................... 46 figure 2.12 block diagram of interrupt control operation ..................................................... 47 figure 2.13 h8s/2237 and h8s/2227 address map in each operating mode ......................... 53 figure 2.14 h8s/2235 and h8s/2225 address map in each operating mode ......................... 54 figure 2.15 h8s/2233 and h8s/2223 address map in each operating mode ......................... 55 figure 3.1 pbc block diagram ............................................................................................... 57 figure 3.2 bus controller block diagram ............................................................................... 59 figure 3.3 overview of area partitioning................................................................................ 60 figure 3.4 basic bus timing (word access to 16-bit 2-state access space)........................ 62 figure 3.5 basic bus timing (word access to 16-bit 3-state access space)........................ 63 figure 3.6 example of burst rom access timing (when ast0 = brsts1 = 1) ................ 64 figure 3.7 example of burst rom access timing (when ast0 = brsts1 = 0) ................ 65 figure 3.8 dtc block diagram ............................................................................................... 67 figure 3.9 flowchart of dtc operation.................................................................................. 68 figure 3.10 location of dtc register information in address space...................................... 69 figure 3.11 dtc operation timing (example for normal and repeat modes) ....................... 72 figure 3.12 operation in normal mode..................................................................................... 75 figure 3.13 operation in repeat mode...................................................................................... 76 figure 3.14 operation in block transfer mode ......................................................................... 77 figure 3.15 h8s/2237 series tpu block diagram ................................................................... 80 figure 3.16 h8s/2227 series tpu block diagram ................................................................... 81 figure 3.17 example of 0 output/1 output operation .............................................................. 83 figure 3.18 example of toggle output operation .................................................................... 84 figure 3.19 operation in pwm mode 1 .................................................................................... 84 figure 3.20 operation in pwm mode 2 .................................................................................... 85 figure 3.21 input capture operation ......................................................................................... 86 figure 3.22 example of operation in phase counting mode 1 ................................................. 86 figure 3.23 example of buffer operation (1) (when tgr is an output compare register)... 88 figure 3.24 example of buffer operation (2) (when tgr is an input capture register)........ 89 figure 3.25 example of cascaded operation (32-bit input capture operation) ...................... 90 iv figure 3.26 8-bit timer block diagram.................................................................................... 92 figure 3.27 example of pulse output ........................................................................................ 93 figure 3.28 block diagram of wdt0........................................................................................ 95 figure 3.29 block diagram of wdt1........................................................................................ 96 figure 3.30 operation in watchdog timer mode...................................................................... 97 figure 3.31 interval timer operation ........................................................................................ 98 figure 3.32 block diagram of sci ............................................................................................ 100 figure 3.33 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) ........................................... 105 figure 3.34 data format in synchronous communication........................................................ 105 figure 3.35 smart card interface block diagram ..................................................................... 108 figure 3.36 schematic diagram of smart card interface pin connections .............................. 109 figure 3.37 smart card interface data format.......................................................................... 109 figure 3.38 a/d converter block diagram ............................................................................... 111 figure 3.39 block diagram of d/a converter........................................................................... 114 figure 3.40 block diagram of ram (example of h8s/2237, h8s/2227)................................ 121 figure 3.41 rom block diagram (example of h8s/2237 in modes 6 and 7).......................... 123 figure 4.1 mode transitions .................................................................................................... 126 figure 5.1 method of use ........................................................................................................ 134 figure 5.2 hi8-2600 system configuration diagram.............................................................. 135 tables table 1.1 four mcu operating modes.................................................................................. 4 table 1.2 product lineup (preliminary) ................................................................................. 4 table 1.3 pin functions .......................................................................................................... 9 table 2.1 addressing modes .................................................................................................. 22 table 2.2 number of states per cycle.................................................................................... 36 table 2.3 condition code notation........................................................................................ 36 table 2.4 operation notation.................................................................................................. 37 table 2.5 exception types and priority.................................................................................. 44 table 2.6 exception vector table .......................................................................................... 45 table 2.7 interrupt control modes ......................................................................................... 47 table 2.8 interrupt sources, vector addresses, and interrupt priorities................................ 48 table 2.9 mcu operating mode selection ............................................................................ 52 table 3.1 bus specifications for each area (basic bus interface) ........................................ 61 table 3.2 interrupt sources, dtc vector addresses, and corresponding dtces................ 70 table 3.3 number of dtc execution states .......................................................................... 72 table 3.4 number of states required in each execution state.............................................. 73 table 3.5 8-bit timer interrupts ............................................................................................. 93 table 3.6 sci interrupt sources and data transfer controller (dtc) activation................. 101 table 3.7 serial transfer formats (asynchronous mode) ..................................................... 103 table 3.8 brr settings for various bit rates (clocked synchronous mode) ...................... 106 table 3.9 h8s/2237 series port functions in each operating mode .................................... 115 v table 3.10 h8s/2227 series port functions in each operating mode .................................... 118 table 4.1 internal states in each mode.................................................................................. 127 table 4.2 power-down mode transition conditions............................................................. 128 table 5.1 cross software product lineup .............................................................................. 131 table 5.2 emulator product lineup........................................................................................ 133 table 5.3 applicable eprom programmers.......................................................................... 134 table 5.4 hi series os product lineup.................................................................................. 136 1 section 1 features of h8s/2237 series and h8s/2227 series 1.1 features of h8s/2237 series and h8s/2227 series h8s/2237 series and h8s/2227 series microcomputers are designed for faster instruction execution, using a real-time control oriented cpu with an internal 32-bit architecture, and can run programs based on the c high-level language efficiently. as well as large-capacity rom and ram, these microcomputers include comprehensive on-chip supporting modules needed for control systems, simplifying the implementation of sophisticated, high-performance systems. 1.1.1 high-performance h8s/2000 cpu general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) high-speed operation suitable for real-time control ? 10 mhz maximum operating frequency (10 mhz oscillation frequency): ztat 13 mhz maximum operating frequency (13 mhz oscillation frequency): mask rom ? high-speed arithmetic operations (at 10 mhz operation) 8/16/32-bit register-register add/subtract: 100 ns 16 16-bit register-register multiply: 2000 ns 32 ? 16-bit register-register divide: 2000 ns instruction set suitable for high-speed operation ? sixty-five types of basic instructions ? 8/16/32-bit transfer instructions ? unsigned/signed multiply and divide instructions ? powerful bit manipulation instructions cpu operating mode ? advanced mode: maximum 16-mbyte address space on-chip byte prom (mask rom) 64 kbytes or 128 kbytes on-chip high-speed static ram 4 kbytes or 16 kbytes bus controller 2 address space divided into 8 areas, with bus specifications settable independently for each area chip select output possible for areas 0 to 7 selection of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area number of program wait states can be set for each area burst rom directly connectable external bus release function data transfer controller (dtc) activated by internal interrupt or software multiple transfers or multiple types of transfer possible for one activation source transfer possible in repeat mode, block transfer mode, etc. request can be sent to cpu for interrupt that activated dtc 16-bit timer-pulse unit (tpu) six-channel (h8s/2237 series) or three-channel (h8s/2227 series) 16-bit timer on-chip pulse i/o processing capability for up to 16 pins (h8s/2237 series) or 8 pins (h8s/2227 series) automatic 2-phase encoder count capability two on-chip 8-bit timer channels 8-bit up-counter (external event count capability) two time constant registers two-channel connection possible watchdog timer (wdt: 2 channels) watchdog timer or interval timer function selectable subclock operation capability (channel 1 only) on-chip serial communication interface (sci) channels channels ? h8s/2237 series: 4 channels (sci0, sci1, sci2, sci3) ? h8s/2227 series: 3 channels (sci0, sci1, sci3) asynchronous mode or synchronous mode selectable multiprocessor communication function smart card interface function 3 a/d converter resolution: 10 bits input: 8 channels high-speed conversion: 13.4 m s minimum conversion time (10 mhz operation) single or scan mode selectable sample-and-hold function a/d conversion can be activated by external trigger or timer trigger on-chip d/a converter resolution: 8 bits output: 2 channels pc break controller (pbc: 2 channels) supports debugging functions by means of pc break interrupts two break channels eleven i/o ports 72 i/o pins, 10 input-only pins interrupt controller nine external interrupt pins (nmi, irq0 to irq7 ) 53 internal interrupt sources eight priority levels settable power-down state medium-speed mode subactive mode subsleep mode watch mode sleep mode module stop mode software standby mode hardware standby mode 4 table 1.1 four mcu operating modes external data bus mode cpu operating mode description on-chip rom initial value maximum value 4 advanced on-chip rom disabled expansion mode disabled 16 bits 16 bits 5 on-chip rom disabled expansion mode disabled 8 bits 16 bits 6 on-chip rom enabled expansion mode enabled 8 bits 16 bits 7 single-chip mode enabled on-chip clock pulse generator (1:1 oscillation) built-in duty correction circuit packages 100-pin plastic tqfp (tfp-100b, tfp-100g) 100-pin plastic qfp (fp-100a, fp-100b) table 1.2 product lineup (preliminary) product name series mask rom version ztat? version rom/ram (bytes) package h8s/2237 series hd6432237 hd6472237 128 k/16 k tfp-100b, tfp-100g, hd6432235 128 k/4 k fp-100a, fp-100b hd6432233 64 k/4 k h8s/2227 series hd6432227 128 k/16 k hd6432225 128 k/4 k hd6432223 64 k/4 k note: ztat? is a trademark of hitachi ltd. 5 1.2 pin arrangement and functions 1.2.1 h8s/2237 series pin arrangement p30/txd0 p31/rxd0 p32/sck0/ irq4 p33/txd1 p34/rxd1 p35/sck1/ irq5 p36 p77/txd3 p76/rxd3 p75/sck3 p74/ mres p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 pg0/ irq6 pg1/ cs3 / irq7 pg2/ cs2 pg3/ cs1 pg4/ cs0 pe0/d0 pe1/d1 pe2/d2 pe3/d3 pe4/d4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pf0/ breq / irq2 pf1/ back /buzz pf2/ wait pf3/ lwr / adtrg / irq3 pf4/ hwr pf5/ rd pf6/ as pf7/ md2 fwe extal vss xtal vcc stby nmi res osc1 osc2 md1 md0 avcc vref p40/an0 p41/an1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p42/an2 p43/an3 p44/an4 p45/an5 p46/an6 p47/an7 p96/da0 p97/da1 p17/tiocb2/tclkd p16/tioca2/ irq1 p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0/a16 pb7/a15/tiocb5 pb6/a14/tioca5 pb5/a13/tiocb4 pb4/a12/tioca4 avss p15/tiocb1/tclkc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pe5/d5 pe6/d6 pe7/d7 pd0/d8 pd1/d9 pd2/d10 pd3/d11 pd4/d12 pd5/d13 pd6/d14 pd7/d15 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pc6/a6 pc7/a7 pb0/a8/tioca3 pb2/a10/tiocc3 pb3/a11/tiocd3 vcc pc0/a0 vss pb1/a9/tiocb3 tfp-100b tfp-100g fp-100b (top view) figure 1.1 100-pin plastic tqfp (tfp100b, tfp-100g), 100-pin plastic qfp (fp-100b) 6 p32/sck0/ irq4 p33/txd1 p34/rxd1 p35/sck1/ irq5 p36 p77/txd3 p76/rxd3 p75/sck3 p74/ mres p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 pg0/ irq6 pg1/ cs3 / irq7 pg2/ cs2 pg3/ cs1 pg4/ cs0 pe0/d0 pe1/d1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 pf3/ lwr / adtrg / irq3 pf2/ wait pf1/ back /buzz pf0/ breq / irq2 p30/txd0 p31/rxd0 pf4/ hwr pf5/ rd pf6/ as pf7/ md2 fwe extal vss xtal vcc stby nmi res osc1 osc2 md1 md0 avcc vref p40/an0 p41/an1 p42/an2 p43/an3 p44/an4 75 74 76 77 78 79 80 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p45/an5 p46/an6 p47/an7 p97/da1 avss p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0/a16 pb7/a15/tiocb5 pb6/a14/tioca5 p96/da0 p17/tiocb2/tclkd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pe2/d2 pe3/d3 pe4/d4 pe5/d5 pe6/d6 pe7/d7 pd0/d8 pd1/d9 pd2/d10 pd3/d11 pd4/d12 vcc pc0/a0 vss pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pb1/a9/tiocb3 pb2/a10/tiocc3 pb3/a11/tiocd3 pb4/a12/tioca4 pb5/a13/tiocb4 pc7/a7 pb0/a8/tioca3 pd5/d13 pd6/d14 pd7/d15 pc6/a6 fp-100a (top view) figure 1.2 100-pin plastic qfp (fp-100a) 7 1.2.2 h8s/2227 series pin arrangement p30/txd0 p31/rxd0 p32/sck0/ irq4 p33/txd1 p34/rxd1 p35/sck1/ irq5 p36 p77/txd3 p76/rxd3 p75/sck3 p74/ mres p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 pg0/ irq6 pg1/ cs3 / irq7 pg2/ cs2 pg3/ cs1 pg4/ cs0 pe0/d0 pe1/d1 pe2/d2 pe3/d3 pe4/d4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pf0/ breq / irq2 pf1/ back /buzz pf2/ wait pf3/ lwr / adtrg / irq3 pf4/ hwr pf5/ rd pf6/ as pf7/ md2 fwe extal vss xtal vcc stby nmi res osc1 osc2 md1 md0 avcc vref p40/an0 p41/an1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p42/an2 p43/an3 p44/an4 p45/an5 p46/an6 p47/an7 p96 p97 p17/tiocb2/tclkd p16/tioca2/ irq1 p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 pa3/a19 pa2/a18 pa1/a17 pa0/a16 pb7/a15 pb6/a14 pb5/a13 pb4/a12 avss p15/tiocb1/tclkc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pe5/d5 pe6/d6 pe7/d7 pd0/d8 pd1/d9 pd2/d10 pd3/d11 pd4/d12 pd5/d13 pd6/d14 pd7/d15 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pc6/a6 pc7/a7 pb0/a8 pb2/a10 pb3/a11 vcc pc0/a0 vss pb1/a9 tfp-100b tfp-100g fp-100b (top view) figure 1.3 100-pin plastic tqfp (tfp-100b, tfp-100g), 100-pin plastic qfp (fp-100b) 8 p32/sck0/ irq4 p33/txd1 p34/rxd1 p35/sck1/ irq5 p36 p77/txd3 p76/rxd3 p75/sck3 p74/ mres p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 pg0/ irq6 pg1/ cs3 / irq7 pg2/ cs2 pg3/ cs1 pg4/ cs0 pe0/d0 pe1/d1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 pf3/ lwr / adtrg / irq3 pf2/ wait pf1/ back /buzz pf0/ breq / irq2 p30/txd0 p31/rxd0 pf4/ hwr pf5/ rd pf6/ as pf7/ md2 fwe extal vss xtal vcc stby nmi res osc1 osc2 md1 md0 avcc vref p40/an0 p41/an1 p42/an2 p43/an3 p44/an4 75 74 76 77 78 79 80 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p45/an5 p46/an6 p47/an7 p97 avss p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 pa3/a19 pa2/a18 pa1/a17 pa0/a16 pb7/a15 pb6/a14 p96 p17/tiocb2/tclkd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pe2/d2 pe3/d3 pe4/d4 pe5/d5 pe6/d6 pe7/d7 pd0/d8 pd1/d9 pd2/d10 pd3/d11 pd4/d12 vcc pc0/a0 vss pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pb1/a9 pb2/a10 pb3/a11 pb4/a12 pb5/a13 pc7/a7 pb0/a8 pd5/d13 pd6/d14 pd7/d15 pc6/a6 fp-100a (top view) figure 1.4 100-pin plastic qfp (fp-100a) 9 table 1.3 pin functions type symbol i/o name and function power vcc input power supply vss input ground: all vss pins should be connected to the system power supply (0 v). clock xtal input connects to a crystal oscillator. extal input connects to a crystal oscillator, or external clock input. osc1 input connect to a 32.768 khz crystal oscillator osc2 input ? output system clock operating mode control md2 to md0 input mode pins system control res input reset input mres input manual reset input stby input standby breq input bus request back output bus request acknowledge fwe input flash write enable interrupts nmi input nonmaskable interrupt irq7 to irq0 input interrupt request 7 to 0 address bus a23 to a0 output address bus data bus d15 to d0 i/o data bus bus control cs7 to cs0 output chip select as output address strobe rd output read hwr output high write lwr output low write wait input wait 16-bit timer-pulse tclka to tclkd input clock input a to d unit (tpu) tioca0, tiocb0, tiocc0, tiocd0 i/o input capture/output compare match a0 to d0 tioca1, tiocb1 i/o input capture/output compare match a1 and b1 tioca2, tiocb2 i/o input capture/output compare match a2 and b2 10 type symbol i/o name and function 16-bit timer-pulse unit (tpu) tioca3, tiocb3, tiocc3, tiocd3 i/o input capture/output compare match a3 to d3 tioca4, tiocb4 i/o input capture/output compare match a4 and b4 tioca5, tiocb5 i/o input capture/output compare match a5 and b5 8-bit timer tmo0, tmo1 output compare match output tmci0, tmci1 input counter external clock input tmri0, tmri1 input counter external reset input watchdog timer (wdt) buzz output buzzer output serial communication txd3, txd2, txd1, txd0 output transmit data (channel 3, 2, 1, 0) interface (sci) smart card rxd3, rxd2, rxd1, rxd0 input receive data (channel 3, 2, 1, 0) interface sck3, sck2, sck1, sck0 i/o serial clock (channel 3, 2 1, 0) a/d converter an7 to an0 input analog input adtrg input a/d conversion external trigger input d/a converter da1, da0 output analog output a/d converter and d/a converters avcc input this is the power supply pin for the a/d converter and d/a converter. avss input this is the ground pin for the a/d converter and d/a converter. vref input this is the reference voltage input pin for the a/d converter and d/a converter. i/o ports p17 to p10 i/o port 1 p36 to p30 i/o port 3 p47 to p40 input port 4 p77 to p70 i/o port 7 p97, p96 input port 9 pa3 to pa0 i/o port a pb7 to pb0 i/o port b pc7 to pc0 i/o port c pd7 to pd0 i/o port d pe7 to pe0 i/o port e pf7 to pf0 i/o port f pg4 to pg0 i/o port g 11 1.3 internal block diagram pe7 / d7 pe6 / d6 pe5 / d5 pe4 / d4 pe3 / d3 pe2 / d2 pe1 / d1 pe0/d0 internal data bus peripheral data bus peripheral address bus pd7 / d15 pd6 / d14 pd5 / d13 pd4 / d12 pd3 / d11 pd2 / d10 pd1 / d9 pd0/d8 port d v cc v cc v ss v ss pa3 / a19/sck2 pa2 / a18/rxd2 pa1 / a17/txd2 pa0 / a16 pb7 / a15/tiocb5 pb6 / a14/tioca5 pb5 / a13/tiocb4 pb4 / a12/tioca4 pb3 / a11/tiocd3 pb2/a10/tiocc3 pb1 / a9/tiocb3 pb0 / a8/tioca3 pc7 / a7 pc6 / a6 pc5 / a5 pc4 / a4 pc3 / a3 pc2 / a2 pc1 / a1 pc0/a0 p36 p35 / sck1/ irq5 p34 / rxd1 p33 / txd1 p32 / sck0/ irq4 p31 / rxd0 p30 / txd0 p97 / da1 p96 /da0 p47 / an7 p46 / an6 p45 / an5 p44 / an4 p43 / an3 p42 / an2 p41 / an1 p40 / an0 vref avcc avss p10 / tioca0 /a20 p11 / tiocb0 /a21 p12 / tiocc0 / tclka/a22 p13 / tiocd0 / tclkb/a23 p14 / tioca1/ irq0 p15 / tiocb1 / tclkc p16 / tioca2/ irq1 p17 / tiocb2/ tclkd p70/tmr01/ tmci01/ cs4 p71 / cs5 p72 / tmo0/ cs6 p73 / tmo1/ cs7 p74 / mres p75 / sck3 p76 / rxd3 p77 / txd3 pg4 / cs0 pg3 / cs1 pg2 / cs2 pg1 / cs3 / irq7 pg0 / irq6 pf7/ pf6 / as pf5 / rd pf4 / hwr pf3 / lwr / adtrg / irq3 pf2 / wait pf1 / back /buzz pf0 / breq / irq2 pc break controller (2 channels) rom ram tpu (6 channels) sci (4 channels) d/a converter (2 channels) 8-bit timer (2 channels) a/d converter (8 channels) md2 md1 md0 extal xtal osc1 osc2 stby res nmi fwe h8s/2000 cpu dtc wdt0 wdt1 (subclock operation) interrupt controller port e port 4 port 1 port 7 internal address bus subsystem clock pulse generator system clock pulse generator port a port b bus controller port c port 3 port 9 port g port f figure 1.5 internal block diagram of h8s/2237 series 12 pe7 / d7 pe6 / d6 pe5 / d5 pe4 / d4 pe3 / d3 pe2 / d2 pe1 / d1 pe0/d0 internal data bus peripheral data bus peripheral address bus pd7 / d15 pd6 / d14 pd5 / d13 pd4 / d12 pd3 / d11 pd2 / d10 pd1 / d9 pd0/d8 port d v cc v cc v ss v ss pa3 / a19 pa2 / a18 pa1 / a17 pa0 / a16 pb7 / a15 pb6 / a14 pb5 / a13 pb4 / a12 pb3 / a11 pb2/a10 pb1 / a9 pb0/a8 pc7 / a7 pc6 / a6 pc5 / a5 pc4 / a4 pc3 / a3 pc2 / a2 pc1 / a1 pc0/a0 p36 p35 / sck1/ irq5 p34 / rxd1 p33 / txd1 p32 / sck0/ irq4 p31 / rxd0 p30 / txd0 p97 p96 p47 / an7 p46 / an6 p45 / an5 p44 / an4 p43 / an3 p42 / an2 p41 / an1 p40 / an0 vref avcc avss p10 / tioca0 /a20 p11 / tiocb0 /a21 p12 / tiocc0 / tclka/a22 p13 / tiocd0 / tclkb/a23 p14 / tioca1/ irq0 p15 / tiocb1 / tclkc p16 / tioca2/ irq1 p17 / tiocb2/ tclkd p70/tmr01/ tmci01/ cs4 p71 / cs5 p72 / tmo0/ cs6 p73 / tmo1/ cs7 p74 / mres p75 / sck3 p76 / rxd3 p77 / txd3 pg4 / cs0 pg3 / cs1 pg2 / cs2 pg1 / cs3 / irq7 pg0 / irq6 pf7/ pf6 / as pf5 / rd pf4 / hwr pf3 / lwr / adtrg / irq3 pf2 / wait pf1 / back /buzz pf0 / breq / irq2 pc break controller (2 channels) rom ram tpu (3 channels) sci (3 channels) 8-bit timer (2 channels) a/d converter (8 channels) md2 md1 md0 extal xtal osc1 osc2 stby res nmi fwe h8s/2000 cpu dtc wdt0 wdt1 (subclock operation) interrupt controller port e internal address bus port a port b port c port 3 port 9 port 4 port 1 port 7 port g port f subsystem clock pulse generator system clock pulse generator bus controller figure 1.6 internal block diagram of h8s/2227 series 13 section 2 cpu 2.1 overview the h8s/2000 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2000 cpu has sixteen 16-bit general registers, can address a 16-mbyte (architecturally 4-gbyte) linear address space, and is ideal for real-time control. 2.1.1 features upward-compatible with h8/300 and h8/300h cpus ? can execute h8/300 and h8/300h object programs general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) sixty-five basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @Cern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] 16-mbyte address space ? program: 16 mbytes ? data: 16 mbytes (4 gbytes architecturally) 14 high-speed operation ? all frequently-used instructions execute in one or two states ? maximum clock frequency: 10 mhz (ztat), 13 mhz (mask rom) ? 8/16/32-bit register-register add/subtract: 100 ns (at 10 mhz operation) ? 8 8-bit register-register multiply: 1200 ns (at 10 mhz operation) ? 16 ? 8-bit register-register divide: 1200 ns (at 10 mhz operation) ? 16 16-bit register-register multiply: 2000 ns (at 10 mhz operation) ? 32 ? 16-bit register-register divide: 2000 ns (at 10 mhz operation) cpu operating mode ? advanced mode power-down state ? transition to power-down state by sleep instruction ? cpu clock speed selection differences between h8s/2600 cpu and h8s/2000 cpu: the differences between the h8s/2600 cpu and the h8s/2000 cpu are as shown below. register configuration the mac register is supported only by the h8s/2600 cpu. basic instructions the four instructions mac, clrmac, ldmac, and stmac are supported only by the h8s/2600 cpu. number of execution states the number of execution states of the mulxu and mulxs instructions. differences from h8/300 cpu: in comparison to the h8/300 cpu, the h8s/2000 cpu has the following enhancements. more general registers and control registers ? eight 16-bit expanded registers, and one 8-bit control register, have been added. expanded address space ? normal mode supports the same 64-kbyte address space as the h8/300 cpu. ? advanced mode supports a maximum 16-mbyte address space. enhanced addressing ? the addressing modes have been enhanced to make effective use of the 16-mbyte address space. 15 enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? signed multiply and divide instructions have been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. higher speed ? basic instructions execute twice as fast. differences from h8/300h cpu: in comparison to the h8/300h cpu, the h8s/2000 cpu has the following enhancements. additional control register ? one 8-bit control register has been added. enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. higher speed ? basic instructions execute twice as fast. 16 2.2 register configuration the h8s/2000 cpu has general registers and control registers. the eight 32-bit general registers all have identical functions and can be used as either address registers or data registers. the control registers are the 24-bit program counter (pc), 8-bit extended register (exr), and 8-bit condition code register (ccr). t i2 i1 i0 exr 76543210 pc 23 0 15 07 07 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers (rn) and extended registers (en) control registers (cr) legend: stack pointer program counter extended control register trace bit interrupt mask bits condition-code register interrupt mask bit user bit or interrupt mask bit * sp: pc: exr: t: i2 to i0: ccr: i: ui: note: * in these series, this bit cannot be used as an interrupt mask. er0 er1 er2 er3 er4 er5 er6 er7 (sp) i ui hunzvc ccr 76543210 half-carry flag user bit negative flag zero flag overflow flag carry flag h: u: n: z: v: c: figure 2.1 cpu registers 17 general registers: the cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. the figure below illustrates the usage of the general registers. the usage of each register can be selected independently. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.2 usage of general registers control registers: the control registers are the 24-bit program counter (pc), 8-bit extended control register (exr), and 8-bit condition-code register (ccr). program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0.) extend register (exr) this 8-bit register comprises a trace bit (t) and interrupt mask bits (i2 to i0). ? bit 7trace bit (t) 18 specifies whether or not trace mode is set. when this bit is cleared to 0, instructions are executed sequentially. when set to 1, trace exception handling is started each time an instruction is executed. ? bits 6 to 3reserved ? bits 2 to 0interrupt mask bits (i2 to i0) these bits specify the interrupt request mask level (0 to 7). see section 2.9, interrupts, for details. exr can be manipulated by the ldc, stc, andc, orc, and xorc instructions. except in the case of stc, interrupts (including nmi) are not accepted for 3 states after the instruction is executed. condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. ? bit 7interrupt mask bit (i): masks interrupts other than nmi when set to 1. (nmi is accepted regardless of the i bit setting.) the i bit is set to 1 by hardware at the start of an exception-handling sequence. for details, refer to section 2.9, interrupts. ? bit 6user bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. in these series, this bit cannot be used as an interrupt mask. ? bit 5half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. ? bit 4user bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. ? bit 3negative flag (n): stores the value of the most significant bit (sign bit) of data. ? bit 2zero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. ? bit 1overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. ? bit 0carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions, to store the carry the carry flag is also used as a bit accumulator by bit manipulation instructions. 19 2.3 data formats the cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, , 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 76543210 don? care 70 don? care 76543210 43 70 70 don? care upper lower lsb msb lsb data type register number data format 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data rnh rnl rnh rnl rnh rnl msb don? care upper lower 43 70 don? care 70 don? care 70 figure 2.3 general register data formats 20 0 msb lsb 15 word data word data rn en 0 lsb 15 16 msb 31 en rn general register er general register e general register r general register rh general register rl most significant bit least significant bit legend: ern: en: rn: rnh: rnl: msb: lsb: 0 msb lsb 15 longword data ern data type register number data format figure 2.3 general register data formats (cont) 21 76543210 70 msb lsb msb lsb msb lsb data type data format 1-bit data byte data word data longword data address address l address l address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2.4 memory data formats 22 2.4 addressing modes the h8s/2000 cpu supports eight addressing modes. table 2.1 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @Cern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 23 effective address calculation: the upper 8 bits of the effective address are ignored, giving a 16- bit address. register indirect with post-increment or pre-decrement ? register indirect with post-increment @ern+ no. addressing mode and instruction format effective address calculation effective address (ea) 1 register direct (rn) op rm rn operand is general register contents. register indirect (@ern) 2 register indirect with displacement @(d:16, ern) or @(d:32, ern) 3 ? register indirect with pre-decrement @?rn 4 general register contents general register contents sign extension disp general register contents 1, 2, or 4 general register contents 1, 2, or 4 byte word longword 1 2 4 operand size value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r r op op r r op disp 24 23 don? care 24 23 don? care 24 23 don? care 24 23 don? care 24 5 @aa:8 absolute address @aa:16 @aa:32 6 immediate #xx:8/#xx:16/#xx:32 31 0 8 7 operand is immediate data. no. addressing mode and instruction format effective address calculation effective address (ea) @aa:24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs op op abs op imm h'ffff don? care 24 23 don? care 24 23 don? care 24 23 don? care sign extension 25 31 0 0 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 ? advanced mode no. addressing mode and instruction format effective address calculation effective address (ea) 23 23 0 31 8 7 0 disp abs h'000000 31 0 24 23 31 0 24 23 op disp op abs sign extension pc contents memory contents don? care don? care 26 2.5 instruction set the h8s/2000 cpu has 65 types of instructions. 2.5.1 features upward-compatible at object level with h8/300h and h8/300 cpus general register architecture 8/16/32-bit transfer instructions and arithmetic and logic instructions ? byte (b), word (w), and longword (l) formats for transfer instructions and basic arithmetic and logic instructions unsigned and signed multiply and divide instructions powerful bit manipulation instructions instructions for saving and restoring multiple registers assembler format: the add instruction format is shown below as an example. mnemonic size source operand destination operand add. b rs, rd 27 data transfer instructions mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa:16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,erd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16,erd mov.l @aa:32,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 pop.w rn pop.l ern push.w rn push.l ern ldm @sp+,(erm-ern) stm (erm-ern),@-sp movfpe @aa:16,rd movtpe rs,@aa:16 b b b b b b b b b b b b b b b b w w w w w w w w w w w w w w l l l l l l l l l l l l l l w l w l l l 2 4 6 2 2 2 2 2 2 2 4 4 4 8 4 8 4 8 4 8 6 10 6 10 2 2 2 2 4 4 2 4 6 2 4 6 4 6 4 6 6 8 6 8 mov pop push ldm stm movfpe movtpe #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa #xx:8 ? rd8 rs8 ? rd8 @ers ? rd8 @(d:16,ers) ? rd8 @(d:32,ers) ? rd8 @ers ? rd8,ers32+1 ? ers32 @aa:8 ? rd8 @aa:16 ? rd8 @aa:32 ? rd8 rs8 ? @erd rs8 ? @(d:16,erd) rs8 ? @(d:32,erd) erd32-1 ? erd32,rs8 ? @erd rs8 ? @aa:8 rs8 ? @aa:16 rs8 ? @aa:32 #xx:16 ? rd16 rs16 ? rd16 @ers ? rd16 @(d:16,ers) ? rd16 @(d:32,ers) ? rd16 @ers ? rd16,ers32+2 ? ers32 @aa:16 ? rd16 @aa:32 ? rd16 rs16 ? @erd rs16 ? @(d:16,erd) rs16 ? @(d:32,erd) erd32-2 ? erd32,rs16 ? @erd rs16 ? @aa:16 rs16 ? @aa:32 #xx:32 ? erd32 ers32 ? erd32 @ers ? erd32 @(d:16,ers) ? erd32 @(d:32,ers) ? erd32 @ers ? erd32,ers32+4 ? ers32 @aa:16 ? erd32 @aa:32 ? erd32 ers32 ? @erd ers32 ? @(d:16,erd) ers32 ? @(d:32,erd) erd32-4 ? erd32,ers32 ? @erd ers32 ? @aa:16 ers32 ? @aa:32 @sp ? rn16,sp+2 ? sp @sp ? ern32,sp+4 ? sp sp-2 ? sp,rn16 ? @sp sp-4 ? sp,ern32 ? @sp (@sp ? ern32,sp+4 ? sp) repeated for each register restored (sp-4 ? sp,ern32 ? @sp) repeated for each register saved i hn zvc mnemonic operand size addressing mode/instruction length (bytes) operation condition code number of states *1 advanced 2 4 2 4 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 5 6 4 5 7 5 5 6 3 5 3 5 7/9/11 [1] 7/9/11 [1] [2] [2] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cannot be used with these series. ? ? 28 arithmetic instructions add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd addx #xx:8,rd addx rs,rd adds #1,erd adds #2,erd adds #4,erd inc.b rd inc.w #1,rd inc.w #2,rd inc.l #1,erd inc.l #2,erd daa rd sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subx #xx:8,rd subx rs,rd subs #1,erd subs #2,erd subs #4,erd dec.b rd dec.w #1,rd dec.w #2,rd dec.l #1,erd dec.l #2,erd das rd mulxu.b rs,rd mulxu.w rs,erd mulxs.b rs,rd mulxs.w rs,erd divxu.b rs,rd divxu.w rs,erd divxs.b rs,rd divxs.w rs,erd cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd tas @erd b b w w l l b b l l l b w w l l b b w w l l b b l l l b w w l l b b w b w b w b w b b w w l l b w l w l w l b 2 4 6 2 4 6 2 2 4 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 2 2 4 4 2 2 2 2 2 2 2 2 2 2 add addx adds inc daa sub subx subs dec das mulxu mulxs divxu divxs cmp neg extu exts tas #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ? rd8+#xx:8 ? rd8 rd8+rs8 ? rd8 rd16+#xx:16 ? rd16 rd16+rs16 ? rd16 erd32+#xx:32 ? erd32 erd32+ers32 ? erd32 rd8+#xx:8+c ? rd8 rd8+rs8+c ? rd8 erd32+1 ? erd32 erd32+2 ? erd32 erd32+4 ? erd32 rd8+1 ? rd8 rd16+1 ? rd16 rd16+2 ? rd16 erd32+1 ? erd32 erd32+2 ? erd32 rd8 decimal adjust ? rd8 rd8-rs8 ? rd8 rd16-#xx:16 ? rd16 rd16-rs16 ? rd16 erd32-#xx:32 ? erd32 erd32-ers32 ? erd32 rd8-#xx:8-c ? rd8 rd8-rs8-c ? rd8 erd32-1 ? erd32 erd32-2 ? erd32 erd32-4 ? erd32 rd8-1 ? rd8 rd16-1 ? rd16 rd16-2 ? rd16 erd32-1 ? erd32 erd32-2 ? erd32 rd8 decimal adjust ? rd8 rd8 rs8 ? rd16 (unsigned multiplication) rd16 rs16 ? erd32 (unsigned multiplication) rd8 rs8 ? rd16 (signed multiplication) rd16 rs16 ? erd32 (signed multiplication) rd16?rs8 ? rd16 (rdh: remainder, rdl: quotient) (unsigned division) erd32?rs16 ? erd32 (ed: remainder, rd: quotient) (unsigned division) rd16?rs8 ? rd16 (rdh: remainder, rdl: quotient) (signed division) erd32?rs16 ? erd32 (ed: remainder, rd: quotient) (signed division) rd8-#xx:8 rd8-rs8 rd16-#xx:16 rd16-rs16 erd32-#xx:32 erd32-ers32 0-rd8 ? rd8 0-rd16 ? rd16 0-erd32 ? erd32 0 ? ( 29 logical instructions and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd not.b rd not.w rd not.l erd b b w w l l b b w w l l b b w w l l b w l 2 4 6 2 4 6 2 4 6 2 2 4 2 2 4 2 2 4 2 2 2 and or xor not #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa rd8 #xx:8 ? rd8 rd8 rs8 ? rd8 rd16 #xx:16 ? rd16 rd16 rs16 ? rd16 erd32 #xx:32 ? erd32 erd32 ers32 ? erd32 rd8 #xx:8 ? rd8 rd8 rs8 ? rd8 rd16 #xx:16 ? rd16 rd16 rs16 ? rd16 erd32 #xx:32 ? erd32 erd32 ers32 ? erd32 rd8 ? #xx:8 ? rd8 rd8 ? rs8 ? rd8 rd16 ? #xx:16 ? rd16 rd16 ? rs16 ? rd16 erd32 ? #xx:32 ? erd32 erd32 ? ers32 ? erd32 ?d8 ? rd8 ?d16 ? rd16 ?rd32 ? erd32 i hn zvc 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mnemonic operand size addressing mode/instruction length (bytes) operation condition code number of states *1 advanced 30 shift instructions shal.b rd shal.b #2,rd shal.w rd shal.w #2,rd shal.l erd shal.l #2,erd shar.b rd shar.b #2,rd shar.w rd shar.w #2,rd shar.l erd shar.l #2,erd shll.b rd shll.b #2,rd shll.w rd shll.w #2,rd shll.l erd shll.l #2,erd shlr.b rd shlr.b #2,rd shlr.w rd shlr.w #2,rd shlr.l erd shlr.l #2,erd rotxl.b rd rotxl.b #2,rd rotxl.w rd rotxl.w #2,rd rotxl.l erd rotxl.l #2,erd rotxr.b rd rotxr.b #2,rd rotxr.w rd rotxr.w #2,rd rotxr.l erd rotxr.l #2,erd rotl.b rd rotl.b #2,rd rotl.w rd rotl.w #2,rd rotl.l erd rotl.l #2,erd rotr.b rd rotr.b #2,rd rotr.w rd rotr.w #2,rd rotr.l erd rotr.l #2,erd b b w w l l b b w w l l b b w w l l b b w w l l b b w w l l b b w w l l b b w w l l b b w w l l 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 shal shar shll shlr rotxl rotxr rotl rotr #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa i hn zvc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 c 0 msb lsb c msb lsb c msb lsb c msb lsb c msb lsb c 0 msb lsb c 0 msb lsb c msb lsb mnemonic operand size addressing mode/instruction length (bytes) operation condition code number of states *1 advanced 31 bit manipulation instructions bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 bset bclr bnot btst bld bild bst bist band #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa (#xx:3 of rd8) ? 1 (#xx:3 of @erd) ? 1 (#xx:3 of @aa:8) ? 1 (#xx:3 of @aa:16) ? 1 (#xx:3 of @aa:32) ? 1 (rn8 of rd8) ? 1 (rn8 of @erd) ? 1 (rn8 of @aa:8) ? 1 (rn8 of @aa:16) ? 1 (rn8 of @aa:32) ? 1 (#xx:3 of rd8) ? 0 (#xx:3 of @erd) ? 0 (#xx:3 of @aa:8) ? 0 (#xx:3 of @aa:16) ? 0 (#xx:3 of @aa:32) ? 0 (rn8 of rd8) ? 0 (rn8 of @erd) ? 0 (rn8 of @aa:8) ? 0 (rn8 of @aa:16) ? 0 (rn8 of @aa:32) ? 0 (#xx:3 of rd8) ? [?#xx:3 of rd8)] (#xx:3 of @erd) ? [?#xx:3 of @erd)] (#xx:3 of @aa:8) ? [?#xx:3 of @aa:8)] (#xx:3 of @aa:16) ? [?#xx:3 of @aa:16)] (#xx:3 of @aa:32) ? [?#xx:3 of @aa:32)] (rn8 of rd8) ? [?rn8 of rd8)] (rn8 of @erd) ? [?rn8 of @erd)] (rn8 of @aa:8) ? [?rn8 of @aa:8)] (rn8 of @aa:16) ? [?rn8 of @aa:16)] (rn8 of @aa:32) ? [?rn8 of @aa:32)] ?#xx:3 of rd8) ? z ?#xx:3 of @erd) ? z ?#xx:3 of @aa:8) ? z ?#xx:3 of @aa:16) ? z ?#xx:3 of @aa:32) ? z ?rn8 of rd8) ? z ?rn8 of @erd) ? z ?rn8 of @aa:8) ? z ?rn8 of @aa:16) ? z ?rn8 of @aa:32) ? z (#xx:3 of rd8) ? c (#xx:3 of @erd) ? c (#xx:3 of @aa:8) ? c (#xx:3 of @aa:16) ? c (#xx:3 of @aa:32) ? c ?#xx:3 of rd8) ? c ?#xx:3 of @erd) ? c ?#xx:3 of @aa:8) ? c ?#xx:3 of @aa:16) ? c ?#xx:3 of @aa:32) ? c c ? (#xx:3 of rd8) c ? (#xx:3 of @erd) c ? (#xx:3 of @aa:8) c ? (#xx:3 of @aa:16) c ? (#xx:3 of @aa:32) ? ? (#xx:3 of rd8) ? ? (#xx:3 of @erd) ? ? (#xx:3 of @aa:8) ? ? (#xx:3 of @aa:16) ? ? (#xx:3 of @aa:32) c (#xx:3 of rd8) ? c c (#xx:3 of @erd) ? c c (#xx:3 of @aa:8) ? c c (#xx:3 of @aa:16) ? c c (#xx:3 of @aa:32) ? c i hn zvc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 4 4 5 6 1 4 4 5 6 1 3 3 4 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mnemonic operand size addressing mode/instruction length (bytes) operation condition code number of states *1 advanced 32 bit manipulation instructions (cont) biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bior #xx:3,rd bior #xx:3,@erd bior #xx:3,@aa:8 bior #xx:3,@aa:16 bior #xx:3,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 b b b b b b b b b b b b b b b b b b b b b b b b b biand bor bior bxor bixor #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa c [?#xx:3 of rd8)] ? c c [?#xx:3 of @erd)] ? c c [?#xx:3 of @aa:8)] ? c c [?#xx:3 of @aa:16)] ? c c [?#xx:3 of @aa:32)] ? c c (#xx:3 of rd8) ? c c (#xx:3 of @erd) ? c c (#xx:3 of @aa:8) ? c c (#xx:3 of @aa:16) ? c c (#xx:3 of @aa:32) ? c c [?#xx:3 of rd8)] ? c c [?#xx:3 of @erd)] ? c c [?#xx:3 of @aa:8)] ? c c [?#xx:3 of @aa:16)] ? c c [?#xx:3 of @aa:32)] ? c c ? (#xx:3 of rd8) ? c c ? (#xx:3 of @erd) ? c c ? (#xx:3 of @aa:8) ? c c ? (#xx:3 of @aa:16) ? c c ? (#xx:3 of @aa:32) ? c c ? [?#xx:3 of rd8)] ? c c ? [?#xx:3 of @erd)] ? c c ? [?#xx:3 of @aa:8)] ? c c ? [?#xx:3 of @aa:16)] ? c c ? [?#xx:3 of @aa:32)] ? c i hn zvc 2 2 2 2 2 4 4 4 4 4 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mnemonic operand size addressing mode/instruction length (bytes) operation condition code number of states *1 advanced 33 branch instructions bra d:8(bt d:8) bra d:16(bt d:16) brn d:8(bf d:8) brn d:16(bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8(bhs d:8) bcc d:16(bhs d:16) bcs d:8(blo d:8) bcs d:16(blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts bcc jmp bsr jsr rts #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa i hn zvc 2 2 4 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 2 always never c z=0 c z=1 c=0 c=1 z=0 z=1 v=0 v=1 n=0 n=1 n ? v=0 n ? v=1 z (n ? v)=0 z (n ? v)=1 2 if condition is true then pc ? pc+d else next; pc ? ern pc ? aa:24 pc ? @aa:8 pc ? @-sp,pc ? pc+d:8 pc ? @-sp,pc ? pc+d:16 pc ? @-sp,pc ? ern pc ? @-sp,pc ? aa:24 pc ? @-sp,pc ? @aa:8 pc ? @sp+ 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 5 4 5 4 5 6 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mnemonic operand size addressing mode/instruction length (bytes) operation branch condition condition code number of states *1 advanced 34 system control instructions trapa #xx:2 rte sleep ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr ldc @aa:32,ccr ldc @aa:32,exr stc ccr,rd stc exr,rd stc ccr,@erd stc exr,@erd stc ccr,@(d:16,erd) stc exr,@(d:16,erd) stc ccr,@(d:32,erd) stc exr,@(d:32,erd) stc ccr,@-erd stc exr,@-erd stc ccr,@aa:16 stc exr,@aa:16 stc ccr,@aa:32 stc exr,@aa:32 andc #xx:8,ccr andc #xx:8,exr orc #xx:8,ccr orc #xx:8,exr xorc #xx:8,ccr xorc #xx:8,exr nop ? ? ? b b b b w w w w w w w w w w w w b b w w w w w w w w w w w w b b b b b b trapa rte sleep ldc stc andc orc xorc nop #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa pc ? @-sp,ccr ? @-sp, exr ? @-sp, 35 block transfer instructions eepmov.b eepmov.w ? eepmov #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa i hn zvc 4 4 4+2n * 2 4+2n * 2 ? ? ? ? ? ? ? ? ? ? ? ? if r4l 0 repeat @er5 ? @er6 er5+1 ? er5 er6+1 ? er6 r4l-1 ? r4l until r4l=0 else next; if r4 0 repeat @er5 ? @er6 er5+1 ? er5 er6+1 ? er6 r4-1 ? r4 until r4=0 else next; notes: * 1: the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. * 2: n is the initial value of r4l or r4. [1] 7 states when the number of restored/saved registers is 2, 9 states when 3, and 11 states when 4. [2] cannot be used with these series. [3] set to 1 when there is a carry from or borrow to bit 11; otherwise cleared to 0. [4] set to 1 when there is a carry from or borrow to bit 27; otherwise cleared to 0. [5] if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. [6] set to 1 if the divisor is negative: otherwise cleared to 0. [7] set to 1 if the divisor is zero; otherwise cleared to 0. [8] set to 1 if the quotient is negative; otherwise cleared to 0. [9] when exr is valid, the number of states is increased by 1. mnemonic operand size addressing mode/instruction length (bytes) operation condition code number of states *1 advanced 36 number of states required for execution: the number of states shown in the instruction set table is the number of states required for execution when the op code and operand data are located in a one-cycle area on which word access is possible, such as on-chip memory. when the op code or operand data is accessed from an on-chip supporting module or an external address, the number of states increases as shown in the table below. table 2.2 number of states per cycle access conditions external device on-chip supporting module 8-bit bus 16-bit bus * cycle on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch 1 4 2 4 6 + 2m 2 3 + m branch instruction read stack operation byte data access 2 2 3 + m word data access 4 4 6 + 2m internal operation 1 1 1 1 1 1 1 legend m: number of wait states inserted in external device access note: * cannot be used with these series. table 2.3 condition code notation symbol meaning changes according operation result. * indeterminate (value not guaranteed). 0 always cleared to 0. 1 always set to 1. not affected by operation result. 37 table 2.4 operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition C subtraction multiplication ? division logical and logical or ? logical exclusive or ? move ? not (logical complement) ( ) < > operand contents :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). 38 2.6 basic timing the cpu is driven by a system clock, denoted by the symbol ? . the period from one rising edge of ? to the next is referred to as a state. the memory cycle or bus cycle consists of one, two, or three states. different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. basic clock timing: an external clock is input to the extal pin, or a crystal oscillator is connected to the extal pin, to generate the system clock ( ? ). an external clock or crystal oscillator of the same frequency as the ? clock should be used. the following methods can be used to generate the system clock ( ? ): 1. input an external clock of the same frequency as the system clock to the extal pin 2. connect a crystal oscillator of the same frequency as the system clock to the extal and xtal pins 3. connect a 32.768 khz crystal oscillator to the osc1 and osc2 pins extal duty adjustment circuit waveform shaping circuit system clock oscillator subclock oscillator medium- speed clock divider system clock to ?pin wdt1 count clock internal clock to supporting modules bus master clock to cpu, dtc ?2 to ?32 ?ub clock selection circuit sck2 to sck0 bus master clock selection circuit xtal osc1 osc2 sckcr rfcut lpwrcr figure 2.5 basic clock timing cpu read/write cycles: the cpu operates on the basis of the ? clock. one ? clock cycle is called a state, and a bus cycle consists of one, two, or three states. different access methods are used for on-chip memory, on-chip supporting modules, and external address space. access to the external address space can be controlled by the bus controller. 39 on-chip memory: on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word access. internal address bus internal read signal internal data bus internal write signal internal data bus bus cycle t1 address read data write data read access write access figure 2.6 on-chip memory access cycle (one-state access) bus cycle t1 unchanged address bus as rd hwr , lwr data bus high high high high-impedance state figure 2.7 pin states during on-chip memory access 40 on-chip supporting module access timing: the on-chip supporting modules are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. bus cycle t1 t2 address read data write data internal read signal internal data bus internal write signal internal data bus read access write access internal address bus figure 2.8 on-chip supporting module access cycle (two-state access) 41 bus cycle t1 t2 unchanged address bus as rd hwr , lwr data bus high high high high-impedance state figure 2.9 pin states during on-chip supporting module access external address space access timing: the external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. in three-state access, wait states can be inserted. for further details, refer to section 3.2, bus controller (bsc). 42 2.7 processing states the h8s/2000 cpu has five processing states: the reset state, program execution state, exception- handling state, bus-released state, and power-down state. reset state: state in which the cpu and all on-chip supporting modules are initialized and halted program execution state: state in which the cpu executes the program sequentially exception-handling state: transient state in which exception handling is executed as the result of a reset, interrupt, or trap instruction exception handling source bus-released state: state in which the external bus is released in response to a bus request signal from a bus master other than the cpu power-down state: state in which cpu operation is stopped, and power consumption is kept low (sleep mode, software standby mode, hardware standby mode, subsleep mode, watch mode). the power-down state also includes medium-speed mode, module stop mode, and subactive mode. 43 end of bus release bus request interrupt request external interrupt request res = high mres = high exception-handling request stby = high, res = low end of bus release bus request notes: 1. from any state except hardware standby mode, a transition to the power-on reset state occurs when res goes low. from any state except hardware standby mode and the power-on reset state, a transition to the manual reset state occurs when mres goes low. a transition to the reset state can also be caused by watchdog timer overflow. 2. from any state, a transition to hardware standby mode occurs when stby goes low. 3. there is also a watch mode, subactive mode, and subsleep mode. for details, see section 4, power-down state. end of exception handling power-down state * 3 reset state sleep instruction with ssby = 0 sleep instruction with ssby = 1 sleep mode software standby mode hardware standby mode * 2 manual reset state * 1 exception-handling state bus-released state program execution state power-on reset state * 1 figure 2.10 state transition diagram 44 2.8 exception handling h8s/2000 cpu exception handling is initiated by a reset, a trap instruction, or an interrupt. a priority system is provided for exception handling, and simultaneously generated exceptions are handled in order of priority. table 2.5 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the res pin, or when the watchdog timer overflows. trace starts when execution of the current instruction or exception handling ends, if the trace (t) bit is set to 1 direct transition started by a direct transition resulting from execution of a sleep instruction interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued low trap instruction (trapa) started by execution of a trap instruction (trapa) exception handling operation: exceptions originate from various sources. trap instruction exception handling is always accepted in the program execution state. trap instructions and interrupts are handled as follows: 1. the program counter (pc), condition code register (ccr), and extend register (exr) are pushed onto the stack. 2. the interrupt mask bits are updated. the t bit is cleared to 0. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. for a reset exception, steps 2 and 3 above are carried out. 45 table 2.6 exception vector table vector address * 1 exception source vector number advanced mode power-on reset 0 h'0000 to h'0003 manual reset 1 h'0004 to h'0007 reserved for system use 2 h'0008 to h'000b 3 h'000c to h'000f 4 h'0010 to h'0013 trace 5 h'0014 to h'0017 direct transition 6 h'0018 to h'001b external interrupt nmi 7 h'001c to h'001f trap instruction (4 sources) 8 h'0020 to h'0023 9 h'0024 to h'0027 10 h'0028 to h'002b 11 h'002c to h'002f reserved for system use 12 h'0030 to h'0033 13 h'0034 to h'0037 14 h'0038 to h'003b 15 h'003c to h'003f external interrupt irq0 16 h'0040 to h'0043 irq1 17 h'0044 to h'0047 irq2 18 h'0048 to h'004b irq3 19 h'004c to h'004f irq4 20 h'0050 to h'0053 irq5 21 h'0054 to h'0057 irq6 22 h'0058 to h'005b irq7 23 h'005c to h'005f internal interrupt * 2 24 to 123 h'0060 to h'0063 to h'01ec to h'01ef notes: 1. lower 16 bits of the address. 2. for details of internal interrupt vectors, see section 2.9, interrupts. 46 2.9 interrupts interrupts are controlled by the interrupt controller. there are a total of 62 interrupt sources, comprising nine external interrupts from the external pins (nmi, irq0 to irq7 ), and 53 internal interrupts from on-chip supporting modules. a separate vector number is assigned to each interrupt. interrupt control: either of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). the interrupt controller controls interrupts on the basis of the control mode set by the intm1 and intm0 bits, the interrupt priorities set by interrupt priority register (ipr), and the masking conditions set by the i bit in ccr and bits i2 to i0 in exr. nmi is the highest-priority interrupt, and is always accepted. syscr nmi input irq input internal interrupt requests swdtend to tei3 intm1, intm0 nmieg nmi input unit irq input unit isr iscr ier ipr interrupt controller priority determination interrupt request vector number i ccr i2 to i0 exr cpu irq sense control register irq enable register irq status register interrupt priority register system control register legend: iscr: ier: isr: ipr: syscr: figure 2.11 block diagram of interrupt controller 47 table 2.7 interrupt control modes interrupt syscr priority setting interrupt control mode intm1 intm0 registers mask bits description 0 0 0 i interrupt mask control is performed by the i bit. 1 setting prohibited 2 1 0 ipr i2 to i0 8-level interrupt mask control is performed by bits i2 to i0. 8 priority levels can be set with ipr. 1 setting prohibited interrupt acceptance control 8-level mask control default priority determination vector number interrupt control mode 2 ipr interrupt source i2 to i0 interrupt control mode 0 i figure 2.12 block diagram of interrupt control operation interrupt control mode 0: enabling and disabling of irq interrupts and on-chip supporting module interrupts can be set by means of the i bit in ccr. interrupts are enabled when the i bit is cleared to 0, and disabled when set to 1. interrupt control mode 2: eight-level masking can be implemented for irq interrupts and on- chip supporting module interrupts by comparing the interrupt mask level bits (i2 to i0) in exr and the ipr priority level. 48 table 2.8 interrupt sources, vector addresses, and interrupt priorities origin of vector address* interrupt source interrupt source vector number advanced mode ipr priority nmi external 7 h'001c high irq0 pin 16 h'0040 ipra6Cipra4 irq1 17 h'0044 ipra2Cipra0 irq2 irq3 18 19 h'0048 h'004c iprb6Ciprb4 irq4 irq5 20 21 h'0050 h'0054 iprb2Ciprb0 irq6 irq7 22 23 h'0058 h'005c iprc6Ciprc4 swdtend (software activation interrupt end) dtc 24 h'0060 iprc2Ciprc0 wovi0 (interval timer 0) watchdog timer 0 25 h'0064 iprd6Ciprd4 pc break pc break 27 h'006c ipre6Cipre4 adi (a/d conversion end) a/d 28 h'0070 ipre2Cipre0 wovi1 (interval timer 1) watchdog timer 1 29 h'0074 tgi0a (tgr0a input capture/ compare-match) tgi0b (tgr0b input capture/ compare-match) tgi0c (tgr0c input capture/ compare-match) tgi0d (tgr0d input capture/ compare-match) tci0v (overflow 0) tpu channel 0 32 33 34 35 36 h'0080 h'0084 h'0088 h'008c h'0090 iprf6Ciprf4 tgi1a (tgr1a input capture/ compare-match) tgi1b (tgr1b input capture/ compare-match) tci1v (overflow 1) tci1u (underflow 1) tpu channel 1 40 41 42 43 h'00a0 h'00a4 h'00a8 h'00ac iprf2Ciprf0 low note: * lower 16 bits of the start address 49 origin of vector address * interrupt source interrupt source vector number advanced mode ipr priority tgi2a (tgr2a input capture/ compare-match) tgi2b (tgr2b input capture/ compare-match) tci2v (overflow 2) tci2u (underflow 2) tpu channel 2 44 45 46 47 h'00b0 h'00b4 h'00b8 h'00bc iprg6Ciprg4 high tgi3a (tgr3a input capture/ compare-match) tgi3b (tgr3b input capture/ compare-match) tgi3c (tgr3c input capture/ compare-match) tgi3d (tgr3d input capture/ compare-match) tci3v (overflow 3) tpu channel 3 48 49 50 51 52 h'00c0 h'00c4 h'00c8 h'00cc h'00d0 iprg2Ciprg0 tgi4a (tgr4a input capture/ compare-match) tgi4b (tgr4b input capture/ compare-match) tci4v (overflow 4) tci4u (underflow 4) tpu channel 4 56 57 58 59 h'00e0 h'00e4 h'00e8 h'00ec iprh6Ciprh4 tgi5a (tgr5a input capture/ compare-match) tgi5b (tgr5b input capture/ compare-match) tci5v (overflow 5) tci5u (underflow 5) tpu channel 5 60 61 62 63 h'00f0 h'00f4 h'00f8 h'00fc iprh2Ciprh0 cmia0 (compare-match a) cmib0 (compare-match b) ovi0 (overflow 0) 8-bit timer channel 0 64 65 66 h'0100 h'0104 h'0108 iprj6Ciprj4 cmia1 (compare-match a) cmib1 (compare-match b) ovi1 (overflow 0) 8-bit timer channel 1 68 69 70 h'0110 h'0114 h'0118 ipri2Cipri0 low note: * lower 16 bits of the start address 50 origin of vector address * interrupt source interrupt source vector number advanced mode ipr priority eri0 (receive error 0) rxi0 (reception completed 0) txi0 (transmit data empty 0) tei0 (transmission end 0) sci channel 0 80 81 82 83 h'0140 h'0144 h'0148 h'014c iprj2Ciprj0 high eri1 (receive error 1) rxi1 (reception completed 1) txi1 (transmit data empty 1) tei1 (transmission end 1) sci channel 1 84 85 86 87 h'0150 h'0154 h'0158 h'015c iprk6Ciprk4 eri2 (receive error 2) rxi2 (reception completed 2) txi2 (transmit data empty 2) tei2 (transmission end 2) sci channel 2 88 89 90 91 h'0160 h'0164 h'0168 h'016c iprk2Ciprk0 eri3 (receive error 3) rxi3 (reception completed 3) txi3 (transmit data empty 3) tei3 (transmission end 3) sci channel 3 120 121 122 123 h'01e0 h'01e4 h'01e8 h'01ec ipro6Cipro4 low note: * lower 16 bits of the start address. 51 2.10 mcu operating modes these series have four operating modes, determined by the setting of the mode pins (md1 and md0). mode 4: the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. pins 13 to 10 and ports a, b, and c function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. however, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. mode 5: the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. pins 13 to 10 and ports a, b, and c function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port e becomes a data bus. mode 6: the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. pins 13 to 10 and ports a, b, and c function as input ports immediately after a reset. they can each be set to output addresses: by settings in the pin state control register in the case of pins 13 to 10 and ports a and b, and by setting the corresponding bits in the data direction register (ddr) to 1 in the case of port c. ports d and e function as a data bus, and part of port f carries bus control signals. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port e becomes a data bus. mode 7: the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled, but external addresses cannot be accessed. all i/o ports are available for use as input-output ports. 52 table 2.9 mcu operating mode selection mcu cpu external data bus operating mode md2 md1 md0 operating mode description on-chip rom initial width max. width 4 1 0 0 advanced on-chip rom disabled, disabled 16 bits 16 bits 51 expanded mode 8 bits 16 bits 6 1 0 on-chip rom enabled, expanded mode enabled 8 bits 16 bits 7 1 single-chip mode 53 2.11 address maps this section shows the address maps in each operating mode. the address space is 16 mbytes in modes 4 to 7 (advanced mode). mode 7 (advanced single-chip mode) h'000000 h'000000 h'01ffff h'000000 external address space on-chip rom on-chip rom note: * external addresses can be accessed by clearing the rame bit in syscr to 0. mode 6 (advanced expanded mode with on-chip rom enabled) modes 4 and 5 (advanced expanded modes with on-chip rom disabled) on-chip ram on-chip ram internal i/o registers internal i/o registers h'ffff3f h'ffefbf h'ffb000 h'fff800 h'ffffff h'ffffc0 h'ffff60 h'ffffff h'ffff40 h'ffffc0 h'ffff60 h'ffb000 h'fff800 h'ffefc0 h'020000 internal i/o registers on-chip ram * on-chip ram * internal i/o registers h'ffffff h'ffff40 h'ffffc0 h'ffff60 h'ffb000 h'fff800 h'ffefc0 external address space external address space internal i/o registers on-chip ram * on-chip ram * internal i/o registers external address space external address space external address space figure 2.13 h8s/2237 and h8s/2227 address map in each operating mode 54 h'000000 h'000000 h'01ffff h'000000 external address space on-chip rom on-chip rom note: * external addresses can be accessed by clearing the rame bit in syscr to 0. on-chip ram on-chip ram internal i/o registers internal i/o registers h'ffff3f h'ffefbf h'fff800 h'ffffff h'ffffc0 h'ffff60 h'ffffff h'ffff40 h'ffffc0 h'ffff60 h'ffb000 h'fff800 h'ffefc0 h'020000 internal i/o registers on-chip ram * on-chip ram * reserved area reserved area internal i/o registers h'ffffff h'fffe40 h'ffffc0 h'ffff60 h'ffb000 h'ffe000 h'ffe000 h'ffe000 h'fff800 h'ffefc0 external address space external address space internal i/o registers on-chip ram * on-chip ram * internal i/o registers external address space external address space external address space mode 7 (advanced single-chip mode) mode 6 (advanced expanded mode with on-chip rom enabled) modes 4 and 5 (advanced expanded modes with on-chip rom disabled) figure 2.14 h8s/2235 and h8s/2225 address map in each operating mode 55 h'000000 h'000000 h'00ffff h'000000 external address space external address space on-chip rom on-chip rom note: * external addresses can be accessed by clearing the rame bit in syscr to 0. on-chip ram on-chip ram internal i/o registers internal i/o registers h'ffff3f h'ffefbf h'ffe000 h'fff800 h'ffffff h'ffffc0 h'ffff60 h'ffffff h'ffff40 h'ffffc0 h'ffff60 h'ffe000 h'fff800 h'ffefc0 h'020000 h'010000 h'ffb000 internal i/o registers on-chip ram * on-chip ram * internal i/o registers h'ffffff h'ffff40 h'ffffc0 h'ffff60 h'ffe000 h'ffb000 h'fff800 h'ffefc0 external address space external address space reserved area * internal i/o registers on-chip ram * on-chip ram * internal i/o registers external address space external address space reserved area * reserved area mode 7 (advanced single-chip mode) mode 6 (advanced expanded mode with on-chip rom enabled) modes 4 and 5 (advanced expanded modes with on-chip rom disabled) figure 2.15 h8s/2233 and h8s/2223 address map in each operating mode 56 section 3 supporting modules 3.1 pc break controller (pbc) these series have a two-channel on-chip pc break controller (pbc) that simplifies user program debugging. this function makes it easy to create a high-performance self-monitoring debugger, enabling programs to be debugged with the chip alone, without using a large-scale in-circuit emulator. 3.1.1 features two channels (a and b) can be set independently the following can be set as break conditions: ? 24 address bits bit masking possible ? bus cycle instruction fetch data access: data read, data write, data read/write ? bus master either cpu or cpu/dtc can be selected the timing of pc break exception handling after the occurrence of a break condition is as follows: ? immediately before execution of the instruction fetched at the set address (instruction fetch) ? immediately after execution of the instruction that accesses data at the set address (data access) module stop mode can be set ? as the initial setting, pbc operation halted. register access is enabled by exiting module stop mode. 57 output control output control mask control match signal pc break interrupt match signal mask control bara bcra barb bcrb comparator control logic comparator control logic internal address access status figure 3.1 pbc block diagram 58 3.2 bus controller (bsc) the bus controller (bsc) manages the external address space divided into eight areas. the bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the cpu and data transfer controller (dtc). 3.2.1 features manages external address space in area units ? in advanced mode, manages the external space as 8 areas of 2-mbytes ? bus specifications can be set independently for each area ? burst rom interfaces can be set basic bus interface ? chip select ( cs0 to cs7 ) can be output for areas 0 to 7 ? 8-bit access or 16-bit access can be selected for each area ? 2-state access or 3-state access can be selected for each area ? program wait states can be inserted for each area burst rom interface ? burst rom interface can be set for area 0 ? choice of 1- or 2-state burst access idle cycle insertion bus arbitration function ? includes a bus arbiter that arbitrates bus mastership among the cpu and dtc other features ? external bus release function 59 internal address bus cs0 to cs7 external bus control signals breq back internal control signals internal data bus bus mode signal bus arbiter cpu bus request signal dtc bus request signal cpu bus acknowledge signal dtc bus acknowledge signal wait wait controller wcrh wcrl area decoder bus controller abwcr astcr bcrh bcrl legend: abwcr: bus width control register astcr: access state control register bcrh: bus control register h bus control register l wait control register h wait control register l bcrl: wcrh: wcrl: figure 3.2 bus controller block diagram 60 3.2.2 area partitioning the bus controller partitions the 16-mbyte address space into eight areas, 0 to 7, in 2-mbyte units, and performs bus control for external space in area units. area partitioning is only effective in expanded mode, and has no significance in single-chip mode. area 0 (2 mbytes) h'000000 h'ffffff h'1fffff h'200000 area 1 (2 mbytes) h'3fffff h'400000 area 2 (2 mbytes) h'5fffff h'600000 area 3 (2 mbytes) h'7fffff h'800000 area 4 (2 mbytes) h'9fffff h'a00000 area 5 (2 mbytes) h'bfffff h'c00000 area 6 (2 mbytes) h'dfffff h'e00000 area 7 (2 mbytes) figure 3.3 overview of area partitioning 61 3.2.3 bus specifications the external address space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. the bus width and number of access states for on-chip memory and internal i/o registers are fixed , and are not affected by the bus controller. bus specifications can be set as shown below by means of the bus controller control registers. table 3.1 bus specifications for each area (basic bus interface) abwcr astcr wcrh, wcrl bus specifications (basic bus interface) abwn astn wn1 wn0 bus width access states program wait states 0016 2 0 100 3 0 11 10 2 13 108 2 0 100 3 0 11 10 2 13 3.2.4 memory interfaces these series memory interfaces comprise (1) a basic bus interface that allows direct connection of rom, sram, and so on; and (2) a burst rom interface that allows direct connection of burst rom. the interface can be designated independently for each area. basic bus interface this interface can be designated for areas 0 to 7. when external space is accessed, the chip select signal ( cs0 to cs7 ) for the relevant area (0 to 7) can be output. in 3-state access space, 0 to 3 program wait states or a pin wait by means of the wait pin can be inserted. after a reset, all areas are designated as basic bus interface, 3-state access space (the bus width is determined by the mcu operating mode). 62 basic bus timing bus cycle t 1 t 2 address bus csn as rd d15 to d8 valid d7 to d0 valid read hwr lwr d15 to d8 valid d7 to d0 valid write note: n = 0 to 7 figure 3.4 basic bus timing (word access to 16-bit 2-state access space) 63 bus cycle t 1 t 2 address bus csn as rd d15 to d8 valid d7 to d0 valid read hwr lwr d15 to d8 valid d7 to d0 valid write note: n = 0 to 7 t 3 figure 3.5 basic bus timing (word access to 16-bit 3-state access space) 64 burst rom interface external space area 0 can be designated as burst rom space, and burst rom space interfacing can be performed. the burst rom space interface enables 16-bit configuration rom with burst access capability to be accessed at high speed. consecutive burst accesses of a maximum 4 words or 8 words can be performed for cpu instruction fetches only. one or two states can be selected for burst access. t 1 address bus cs0 as data bus t 2 t 3 t 1 t 2 t 1 full access t 2 rd burst access only lower address changed read data read data read data figure 3.6 example of burst rom access timing (when ast0 = brsts1 = 1) 65 t 1 address bus cs0 as data bus t 2 t 1 t 1 full access rd burst access only lower address changed read data read data read data figure 3.7 example of burst rom access timing (when ast0 = brsts1 = 0) 66 3.3 data transfer controller (dtc) the data transfer controller (dtc) is activated by an interrupt or software, and can transfer data without imposing any load on the cpu. 3.3.1 features transfer possible over any number of channels ? transfer information is stored in memory ? one activation source can trigger a number of data transfers (chain transfer) variety of transfer modes ? normal, repeat, and block transfer modes available ? incrementing, decrementing, and fixing of source and destination addresses can be selected direct specification of 16-mbyte address space possible transfer can be set in byte or word units a cpu interrupt can be requested for the interrupt that activated the dtc ? an interrupt request can be issued to the cpu after one data transfer ends ? an interrupt request can be issued to the cpu after all specified data transfers have ended can be activated by software module stop mode can be set ? the initial setting enables dtc registers to be accessed. dtc operation is halted by setting module stop mode. 67 internal data bus dtcer a to dtcer f, dtceri dtvecr interrupt controller dtc on-chip ram internal data bus register information control logic dtc activa- tion request cpu interrupt request mra mrb cra crb dar sar interrupt request legend: mra, mrb: cra, crb: sar: dar: dtcera to dtcerf, dtceri: dtvecr: dtc mode registers a and b dtc transfer count registers a and b dtc source address register dtc destination address register dtc enable registers a to f, i dtc vector register figure 3.8 dtc block diagram 68 3.3.2 data transfer operation the dtc reads register information previously stored in memory, and transfers data on the basis of that register information. after the data transfer, it writes updated register information back to memory. pre-storage of register information in memory makes it possible to transfer data over any required number of channels. the dtc can also execute a number of transfers with a single activation (chain transfer). next transfer read dtc vector read register information data transfer write register information clear an activation flag chne = 1? transfer counter = 0 or disel = 1 no no yes yes clear dtcer interrupt exception handling end start figure 3.9 flowchart of dtc operation 69 dtc activation sources: the dtc operates when activated by an interrupt or by a write to the dtc vector register (dtvecr) by software. an interrupt request can be designated as a cpu interrupt source or a dtc activation source. when an interrupt has been designated a dtc activation source, existing cpu mask level and interrupt controller priorities have no effect. if there is more than one activation source at the same time, the dtc operates in accordance with the default priorities. interrupt sources and dtc vector address: the dtc vector address indicates the start address of the register information in memory. the mra, sar, mrb, dar, cra, and crb registers are located in that order from the start address of the register information. locate the register information in the on-chip ram (addresses h'ffebc0 to h'ffefbf). lower address 0123 mra sar dar mrb cra crb mra sar dar mrb cra crb register information register information for 2nd transfer in chain transfer register information start address chain transfer 4 bytes figure 3.10 location of dtc register information in address space 70 table 3.2 interrupt sources, dtc vector addresses, and corresponding dtces interrupt source origin of interrupt source vector number vector address * dtce priority write to dtvecr software dtvecr h'0400+ (dtvecr [6:0]<<1) high irq0 external pin 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 irq3 19 h'0426 dtcea4 irq4 20 h'0428 dtcea3 irq5 21 h'042a dtcea2 irq6 22 h'042c dtcea1 irq7 23 h'042e dtcea0 adi (a/d conversion end) a/d 28 h'0438 dtceb6 tgi0a (gr0a compare-match/input capture) tpu channel 0 32 h'0440 dtceb5 tgi0b (gr0b compare-match/input capture) 33 h'0442 dtceb4 tgi0c (gr0c compare-match/input capture) 34 h'0444 dtceb3 tgi0d (gr0d compare-match/input capture) 35 h'0446 dtceb2 tgi1a (gr1a compare-match/input capture) tpu channel 1 40 h'0450 dtceb1 tgi1b (gr1b compare-match/input capture) 41 h'0452 dtceb0 tgi2a (gr2a compare-match/input capture) tpu channel 2 44 h'0458 dtcec7 tgi2b (gr2b compare-match/input capture) 45 h'045a dtcec6 tgi3a (gr3a compare-match/input capture) tpu channel 3 48 h'0460 dtcec5 tgi3b (gr3b compare-match/input capture) 49 h'0462 dtcec4 tgi3c (gr3c compare-match/input capture) 50 h'0464 dtcec3 71 tgi3d (gr3d compare-match/input capture) 51 h'0466 dtcec2 low interrupt source origin of interrupt source vector number vector address * dtce priority tgi4a (gr4a compare-match/input capture) tpu channel 4 56 h'0470 dtcec1 high tgi4b (gr4b compare-match/input capture) 57 h'0472 dtcec0 tgi5a (gr5a compare-match/input capture) tpu channel 5 60 h'0478 dtced5 tgi5b (gr5b compare-match/input capture) 61 h'047a dtced4 cmia0 8-bit timer channel 0 64 h'0480 dtced3 cmib0 65 h'0482 dtced2 cmia1 8-bit timer channel 1 68 h'0488 dtced1 cmib1 69 h'048a dtced0 rxi0 (reception complete 0) sci channel 0 81 h'04a2 dtcee3 txi0 (transmit data empty 0) 82 h'04a4 dtcee2 rxi1 (reception complete 1) sci channel 1 85 h'04aa dtcee1 txi1 (transmit data empty 1) 86 h'04ac dtcee0 rxi2 (reception complete 2) sci channel 2 89 h'04b2 dtcef7 txi2 (transmit data empty 2) 90 h'04b4 dtcef6 rxi3 (reception complete 3) sci channel 3 121 h'04f2 dtcei7 txi3 (transmit data empty 3) 122 h'04f4 dtcei6 low note: * lower 16 bits of the address. 72 dtc activation request dtc request address vector read transfer information read transfer information write data transfer read write figure 3.11 dtc operation timing (example for normal and repeat modes) table 3.3 number of dtc execution states mode vector read i register information read/write j data read k data write l internal operations m normal 16113 repeat 16113 block transfer 1 6 n n 3 n: block size (initial setting of crah and cral) 73 table 3.4 number of states required in each execution state access to on- chip ram on- chip rom internal i/o registers external devices bus width 32 16 8 16 8 8 16 16 access states 11222323 execution vector read s i 1 4 6+2m 2 3+m state register information read/write s j 1 byte data read s k 112223+m23+m word data read s k 11424 6+2m 2 3+m byte data write s l 112223+m23+m word data write s l 11424 6+2m 2 3+m internal operation s m 11111111 the number of execution states is calculated from the formula below. number of execution states = i s i + s (j s j + k s k + l s l ) + m s m s indicates the sum of all transfers activated by one activation event (the number in which the chne bit is set to 1, plus 1). 74 3.3.3 transfer modes there are three dtc transfer modesnormal mode, repeat mode, and block transfer mode. the 24-bit dtc source address register (sar) designates the dtc transfer source address and the 24-bit destination address register (dar) designates the transfer destination address. after each transfer, sar and dar are independently incremented, decremented, or left fixed. address registers transfer mode activation source transfer source transfer destination normal mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? up to 65,536 transfers possible repeat mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? after the specified number of transfers (1 to 256), the initial state resumes and operation continues block transfer mode ? one transfer request transfers a block of the specified size ? block size is from 1 to 256 bytes or words ? up to 65,536 transfers possible ? a block area can be designated at either the source or destination irq tpu tgi 8-bit timer cmi sci txi or rxi a/d converter adi software 24 bits 24 bits 75 operation in normal mode: in normal mode, one operation transfers one byte or one word of data. from 1 to 65,536 transfers can be specified. when the specified number of transfers have ended, a cpu interrupt can be requested. transfer sar dar sar: dar: cra: transfer source address transfer destination address transfer count figure 3.12 operation in normal mode 76 operation in repeat mode: in repeat mode, one operation transfers one byte or one word of data. from 1 to 256 transfers can be specified. when the specified number of transfers have ended, the initial settings are restored and transfer is repeated. a cpu interrupt is not requested. transfer repeat area sar or dar dar or sar sar: dar: cra: transfer source address transfer destination address transfer count (8 bits 2) figure 3.13 operation in repeat mode 77 operation in block transfer mode: in block transfer mode, one operation transfers one block of data. either the transfer source or the transfer destination is specified as a block area. the block size is 1 to 256. when the transfer of one block ends, the initial setting of the address register specified in the block area is restored. the other address register is incremented, decremented, or left fixed. from 1 to 65,536 transfers can be specified. when the specified number of transfers have ended, a cpu interrupt can be requested. transfer sar or dar dar or sar block area . . . first block nth block sar: dar: cra: crb: transfer source address transfer destination address block size (8 bits 2) transfer count figure 3.14 operation in block transfer mode 78 3.4 16-bit timer pulse unit (tpu) these series have an on-chip 16-bit timer pulse unit (six channels in the h8s/2227 series, three channels in the h8s/2227 series). the tpu can provide up to 16 kinds of pulse input/output. the tpu can perform pwm output, pulse width measurement, and two-phase encoder processing, and can activate the data transfer controller (dtc) . it can also generate an a/d converter start trigger. 3.4.1 features on-chip channels ? h8s/2237 series: 0, 1, 2, 3, 4, 5 ? h8s/2227 series: 0, 1, 2 maximum 16 pulse input/outputs ? a total of 16 timer general registers (tgrs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register selection of eight counter input clocks for each channel ? internal clocks: ? , ? /4, ? /16, ? /64, ? /256, ? /1024, ? /4096 ? external clocks: tclka, tclkb, tclkc, tclkd the following operations can be set for each channel: ? waveform output at compare-match: selection of 0, 1, or toggle output ? input capture function: selection of rising edge, falling edge, or both edge detection ? counter clear operation: counter clearing possible by compare-match or input capture ? synchronous operation: ? multiple timer counters (tcnt) can be written to simultaneously ? simultaneous clearing by compare-match and input capture possible ? simultaneous input/output possible for each register by counter synchronous operation ? pwm mode: ? any pwm output duty can be set ? maximum 15-phase pwm output possible by combination with synchronous operation buffer operation settable for channels 0 and 3 ? input capture register double-buffering possible ? automatic rewriting of output compare register possible phase counting mode settable independently for each of channels 1, 2, 4, and 5 ? two-phase encoder pulse up/down-count possible 79 cascaded operation ? channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow fast access via internal 16-bit bus ? fast access is possible via a 16-bit bus interface 26 interrupt sources ? for channels 0 and 3, four compare-match/input capture dual-function interrupts and one overflow interrupt can be requested independently ? for channels 1, 2, 4, and 5, two compare-match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently automatic transfer of register data ? block transfer, one-word transfer, and one-byte transfer possible by data transfer controller (dtc) activation a/d converter conversion start trigger can be generated ? channel 0 to 5 compare-match a/input capture a signals can be used as an a/d converter conversion start trigger module stop mode can be set ? as the initial setting, tpu operation is halted. register access is enabled by exiting module stop mode. 80 channel 3 channel 4 channel 5 control logic for channels 3 to 5 channel 2 tior tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tier tgra tcnt tgrb channel 0 control logic for channels 0 to 2 tgra tcnt tgrb tgrd bus interface common tsyr control logic tstr [input/output pins] tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 [clock input] ?1 ?4 ?16 ?64 ?256 ?1024 ?4096 tclka tclkb tclkc tclkd [input/output pins] tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 [interrupt request signals] channel 3: channel 4: channel 5: [interrupt request signals] channel 0: channel 1: channel 2: internal data bus a/d conversion start request signal module data bus tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u channel 3: channel 4: channel 5: internal clock: external clock: channel 0: channel 1: channel 2: tior tior tmdr tsr tcr tiorh tier tiorl tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd tmdr tsr tcr tior tier tgra tcnt tgrb tmdr tsr tcr tior tier tgra tcnt tgrb legend: tstr: tsyr: tcr: tmdr: tior (h, l): tier: tsr: tgr (a, b, c, d): timer general registers (a, b, c, d) timer start register timer synchro register timer control register timer mode register timer i/o control register (h, l) timer interrupt enable register timer status register tmdr tsr tcr tier figure 3.15 h8s/2237 series tpu block diagram 81 channel 2 tior tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tier tgra tcnt tgrb channel 0 control logic for channels 0 to 2 tgra tcnt tgrb tgrd bus interface common tsyr control logic tstr [clock input] ?1 ?4 ?16 ?64 ?256 ?1024 tclka tclkb tclkc tclkd [input/output pins] tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 [interrupt request signals] channel 0: channel 1: channel 2: internal data bus a/d conversion start request signal module data bus tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u internal clock: external clock: channel 0: channel 1: channel 2: tior tior tmdr tsr tcr tiorh tier tiorl legend: tstr: tsyr: tcr: tmdr: tior (h, l): tier: tsr: tgr (a, b, c, d): timer general registers (a, b, c, d) timer start register timer synchro register timer control register timer mode register timer i/o control register (h, l) timer interrupt enable register timer status register tmdr tsr tcr tier figure 3.16 h8s/2227 series tpu block diagram 82 3.4.2 interrupt sources and data transfer controller (dtc) activation table 3.3 tpu interrupts channel interrupt source description dtc activation priority 0 tgi0a tgr0a input capture/compare-match possible high tgi0b tgr0b input capture/compare-match possible tgi0c tgr0c input capture/compare-match possible tgi0d tgr0d input capture/compare-match possible tci0v tcnt0 overflow not possible 1 tgi1a tgr1a input capture/compare-match possible tgi1b tgr1b input capture/compare-match possible tci1v tcnt1 overflow not possible tci1u tcnt1 underflow not possible 2 tgi2a tgr2a input capture/compare-match possible tgi2b tgr2b input capture/compare-match possible tci2v tcnt2 overflow not possible tci2u tcnt2 underflow not possible 3 * tgi3a tgr3a input capture/compare-match possible tgi3b tgr3b input capture/compare-match possible tgi3c tgr3c input capture/compare-match possible tgi3d tgr3d input capture/compare-match possible tci3v tcnt3 overflow not possible 4 * tgi4a tgr4a input capture/compare-match possible tgi4b tgr4b input capture/compare-match possible tci4v tcnt4 overflow not possible tci4u tcnt4 underflow not possible 5 * tgi5a tgr5a input capture/compare-match possible tgi5b tgr5b input capture/compare-match possible tci5v tcnt5 overflow not possible tci5u tcnt5 underflow not possible low notes: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. * only applies to the h8s/2237 series. 83 3.4.3 operation normal operation: each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. buffer operation when tgr is an output compare register when a compare-match occurs, the value in the buffer register for the relevant channel is transferred to tgr. when tgr is an input capture register when input capture occurs, the value in tcnt is transfer to tgr and the value previously held in tgr is transferred to the buffer register. waveform output by compare-match 0, 1, or toggle output can be selected. example of 0 output/1 output operation: in this example, tcnt has been designated as a free-running counter, and settings have been made so that 0 is output by compare-match a, and 1 is output by compare-match b. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb does not change does not change does not change 1 output 0 output does not change figure 3.17 example of 0 output/1 output operation 84 example of toggle output: in this example, settings have been made so that tcnt counter clearing is performed by compare-match b, and output is toggled by both by compare-match a and compare-match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle output counter cleared by tgrb compare-match toggle output figure 3.18 example of toggle output operation 3.4.4 pwm modes in pwm mode, pwm waveforms are output from the output pins. there are two pwm modes pwm mode 1 with a maximum of 8-phase pulse output, and pwm mode 2 with a maximum of 15-phase pulse output. pwm mode 1: pwm output is generated by pairing tgra with tgrb and tgrc with tgrd. in pwm mode 1, a maximum 8-phase pwm output is possible. example of operation in pwm mode 1 in this example, tgra compare-match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 is set as the tgrb output value. in this case, the value set in tgra is the cycle, and the value set in tgrb is the duty. tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare-match figure 3.19 operation in pwm mode 1 85 pwm mode 2: pwm output is generated using one tgr register as the cycle register and the others as duty registers. in pwm mode 2, a maximum 15-phase pwm output is possible by combined use with synchronous operation. example of operation in pwm mode 2 in this example, synchronous operation is designated for channels 0 and 1, tgr1b compare- match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers, to output a 5-phase pwm waveform. in this case, the value set in tgr1b is the cycle, and the value set in the other tgr registers is the duty. tcnt value tgr1b h'0000 tioca0 counter cleared by tgr1b compare-match tgr1a tgr0d tgr0c tgr0b tgr0a tiocb0 tiocc0 tiocd0 tioca1 time figure 3.20 operation in pwm mode 2 3.4.5 input capture operation the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the input edge. example of input capture operation in this example both rising and falling edges have been selected as the tioca pin input edge, falling edge has been selected as the tiocb pin input edge, and counter clearing by tgrb input capture has been designated for tcnt. 86 tcnt value h'0180 h'0000 tioca tgra time h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb figure 3.21 input capture operation 3.4.6 phase counting mode in phase counting mode, the phase difference between two external clock inputs is detected and tcnt operates as an up/down-counter. there are four modes (phase counting modes 1 to 4) with different setting conditions. these modes can be set for channels 1, 2, 4, and 5. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 3.22 example of operation in phase counting mode 1 87 up/down-count conditions in phase counting mode tclka (channels 1 and 5) tclkb (channels 1 and 5) phase counting mode tclkc (channels 2 and 4) tclkd (channels 2 and 4) 1234 high level up-count up-count low level low level high level up-count up-count high level down-count down-count down-count low level high level low level down-count legend : rising edge : falling edge : don't care 88 3.4.7 buffer operation buffer operation, provided for channels 0 and 3, enables tgrc and tgrd to be used as buffer registers. example of buffer operation (1) (when tgr is an output compare register) in this example, pwm mode 1 has been designated for channel 0, and buffer operation has been designated for tgra and tgrc. the settings used are tcnt clearing by a compare- match b, 1 output at compare-match a, and 0 output at compare-match b. when a compare- match a occurs, the output is changed and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. tcnt value tgr0b h'0000 tgr0c time tgr0a h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgr0a h'0450 h'0200 transfer figure 3.23 example of buffer operation (1) (when tgr is an output compare register) 89 example of buffer operation (2) (when tgr is an input capture register) in this example, tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and detection of both rising and falling edges has been selected for the tioca pin. when the tcnt value is stored in tgra upon occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 3.24 example of buffer operation (2) (when tgr is an input capture register) 90 cascading in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. channels 1 and 2, and channels 4 and 5, can be cascaded. example of cascaded operation in this example, counting upon tcnt2 overflow/underflow has been set for tcnt1, tgr1a and tgr2a have been designated as input capture registers, and tioc pin rising edge detection has been selected. when a rising edge is input to the tioca1 and tioca2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to tgr1a, and the lower 16 bits to tgr2a. tcnt2 clock tcnt2 h'ffff h'0000 h'0001 tioca1, tioca2 tgr1a h'03a2 tgr2a h'0000 tcnt1 clock tcnt1 h'03a1 h'03a2 figure 3.25 example of cascaded operation (32-bit input capture operation) synchronous operation when synchronous operation is designated for a channel, tcnt for that channel performs synchronous presetting and clearing. that is, when tcnt for a channel designated for synchronous operation is rewritten, the tcnt counters for the other channels are also rewritten at the same time. when any clearing condition occurs, the tcnt counters for the other channels are also cleared simultaneously. 91 3.5 8-bit timer (tmr) these series includes an 8-bit timer with two channels based on an 8-bit counter. the 8-bit timer can be used for a variety of applications as a multifunctional timer, including pulse output with an arbitrary duty cycle. 3.5.1 features selection of four input clock sources ? the clock source can be selected from three internal clock signals ( ? /8, ? /64, or ? /8192) or an external clock (external event counting is possible). counter clearing specification ? the counters can be cleared on compare-match a or b, or by an external reset signal. timer output controlled by combination of two compare-match signals ? the timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to generate pulse output or pwm output with an arbitrary duty cycle. provision for cascading of two channels ? operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1 for the lower 8 bits (16-bit count mode). ? channel 1 can be used to count channel 0 compare matches (compare match count mode). three interrupt sources for each channel ? there are two compare-match sources and one overflow source, capable of independent requests. a/d converter conversion start trigger can be generated ? channel 0 compare-match a signal can be used as an a/d converter conversion start trigger. module stop mode can be set ? as the initial setting, 8-bit timer operation is halted. register access is enabled by exiting module stop mode. 92 external clocks internal clocks ?8 ?64 ?8192 clock 1 compare-match a1 compare-match a0 clear 1 cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 interrupt signals tmo0 tmri01 internal bus tcora0 comparator a0 comparator b0 tcorb0 tcsr0 tcr0 tcora1 comparator a1 tcnt1 comparator b1 tcorb1 tcsr1 tcr1 tmci01 tcnt0 overflow 1 overflow 0 compare-match b1 compare-match b0 tmo1 clock select control logic clear 0 clock 0 a/d conversion start request signal figure 3.26 8-bit timer block diagram 93 3.5.2 interrupt source and data transfer controller (dtc) activation table 3.5 8-bit timer interrupts channel interrupt source description dtc activation priority 0 cmia0 interrupt by cmfa possible high cmib0 interrupt by cmfb possible ovi0 interrupt by ovf not possible 1 cmia1 interrupt by cmfa possible cmib1 interrupt by cmfb possible ovi1 interrupt by ovf not possible low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. 3.5.3 example of pulse output tcr is used to set counter clearing by a tcora compare-match. the cycle is set in tcora, and the duty in tcorb. the pulses shown below can be output continuously without software intervention. tcnt h'ff counter clearing tcora tcorb h'00 tmo figure 3.27 example of pulse output 94 3.6 watchdog timer (wdt) these series have an on-chip watchdog timer with two channels (wdt0, wdt1) for monitoring system operation. when this watchdog function is not needed, the wdt can be used as an interval timer. when the subclock is selected as the input clock, the wdt can be used as a real-time clock timer. 3.6.1 features choice of 8 (wdt0) or 16 (wdt1) counter input clocks ? maximum wdt interval: system clock period 131072 256 ? subclock can be selected for the wdt1 input counter maximum interval when the subclock is selected: subclock period 256 256 can be used as an interval timer generation of internal reset or internal interrupt in watch timer mode ? wdt0: choice of whether or not the chip is internally reset when the counter overflows ? wdt1: choice of internal reset or nmi interrupt generation when the counter overflows interrupt generation in interval timer mode ? when the counter overflows, the wdt generates an interval timer interrupt. 95 3.6.2 block diagram overflow wovi0 (interrupt request signal) internal reset signal * tcnt tcsr rstcsr ?2 ?64 ?128 ?512 ?2048 ?8192 ?32768 ?131072 clock clock select internal clock source bus interface module bus internal bus wdt legend: tcsr: timer control/status register tcnt: timer counter rstcsr: reset control/status register note: * the internal reset signal can be generated by means of a register setting. power-on reset or manual reset can be selected. interrupt control reset control figure 3.28 block diagram of wdt0 96 overflow tcnt tcsr ?2 ?64 ?128 ?512 ?2048 ?8192 ?32768 ?131072 clock clock select interrupt control reset control internal clock source bus interface module bus internal bus wdt wovi1 (interrupt request signal) internal reset signal * internal nmi (interrupt request signal) legend: tcsr: timer control/status register tcnt: timer counter note: * the internal reset signal can be generated by means of a register setting. the generated reset is a power-on reset. sub /2 sub /4 sub /8 sub /16 sub /32 sub /64 sub /128 sub /256 buzz figure 3.29 block diagram of wdt1 97 watchdog timer operation: the example below shows this module used as a watchdog timer. the timer counter (tcnt) starts counting up using the specified clock. tcnt value h'00 time h'ff wt/ it = 1 tme = 1 h'00 written to tcnt wt/ it = 1 tme = 1 h'00 written to tcnt 518 states (wdt0) 515 or 516 states (wdt1) internal reset signal * overflow internal reset generated wovf = 1 wt/ it : timer mode select bit tme: timer enable bit note: * in wdt0, the internal reset signal is generated only when the rste bit is set to 1. in wdt1, an internal reset or nmi interrupt is generated. figure 3.30 operation in watchdog timer mode 98 interval timer operation: an example of the use of the wdt as an interval timer is shown here. the timer counter (tcnt) starts counting up on the specified clock, and an interval timer interrupt (wovi) occurs each time tcnt overflows. this function can be used to generate interrupt requests at regular intervals. tcnt count h'00 time h'ff wt/ it = 0 tme = 1 wovi overflow overflow overflow overflow legend: wovi: interval timer interrupt request generation wovi wovi wovi figure 3.31 interval timer operation 99 3.7 serial communication interface (sci) these series are equipped with a 4- or 3-channel serial communication interface (sci). the sci can handle both asynchronous and clocked synchronous serial communication. a function is also provided for serial communication between processors (multiprocessor communication function). 3.7.1 features on-chip channels ? h8s/2237 series: 0, 1, 2, 3 ? h8s/2227 series: 0, 1, 3 choice of asynchronous or clocked synchronous serial communication mode full-duplex communication capability data register double-buffering enables continuous transmission/reception on-chip dedicated baud rate generator allows any bit rate to be selected selection of internal clock from baud rate generator or external clock input (sck pin) as serial clock source detection of three receive errors ? overrun errors, framing errors, and parity errors can be detected break detection four interrupt sources ? four interrupt sourcestransmit data empty, transmission end, receive data full, and receive errorthat can issue requests independently ? the transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (dtc) to execute data transfer built-in multiprocessor communication function selection of lsb-first or msb-first transfer ? this choice can be made regardless of the communication mode (with the exception of 7- bit data transfer in asynchronous mode) module stop mode can be set ? as the initial setting, sci operation is halted. register access is enabled by exiting module stop mode. 100 3.7.2 block diagram bus interface tdr rsr rdr module data bus tsr ssr scmr scr smr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock external clock ?4 ?16 ?64 txi tei rxi eri legend: rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register scmr: smart card mode register brr: bit rate register figure 3.32 block diagram of sci 101 table 3.6 sci interrupt sources and data transfer controller (dtc) activation channel interrupt source description dtc activation priority * 1 0 eri0 interrupt due to receive error (orer, fer, or per) not possible high rxi0 interrupt due to receive data full state (rdrf) possible txi0 interrupt due to transmit data empty state (tdre) possible tei0 interrupt due to transmission end (tend) not possible 1 eri1 interrupt due to receive error (orer, fer, or per) not possible rxi1 interrupt due to receive data full state (rdrf) possible txi1 interrupt due to transmit data empty state (tdre) possible tei1 interrupt due to transmission end (tend) not possible 2 * 2 eri2 interrupt due to receive error (orer, fer, or per) not possible rxi2 interrupt due to receive data full state (rdrf) possible txi2 interrupt due to transmit data empty state (tdre) possible tei2 interrupt due to transmission end (tend) not possible 3 eri3 interrupt due to receive error (orer, fer, or per) not possible rxi3 interrupt due to receive data full state (rdrf) possible txi3 interrupt due to transmit data empty state (tdre) possible tei3 interrupt due to transmission end (tend) not possible low notes: 1. the table shows the initial state immediately after a reset. relative channel priorities can be changed by means of the interrupt controller. 2. only applies to the h8s/2237 series. 102 sci asynchronous communication: asynchronous mode is a serial communication mode in which synchronization is achieved on a character by character basis, using a start bit and one or two stop bits. twelve serial data transfer formats ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even/odd/none ? multiprocessor bit: 1 or 0 selection of on-chip baud rate generator or external clock from sck pin as clock source transmit/receive clock can be output from sck pin break detection ? a break can be detected by reading the rxd pin level directly in case of a framing error multiprocessor communication capability 103 table 3.7 serial transfer formats (asynchronous mode) smr settings serial transfer format and frame length chr pe mp stop 123456789101112 0000 s 8-bit data stop 0001 s 8-bit data stop stop 0100 s 8-bit data p stop 0101 s 8-bit data p stop stop 1000 s 7-bit data stop 1001 s 7-bit data stop stop 1100 s 7-bit data p stop 1101 s 7-bit data p stop stop 0 1 0 s 8-bit data mpb stop 0 1 1 s 8-bit data mpb stop stop 1 1 0 s 7-bit data mpb stop 1 1 1 s 7-bit data mpb stop stop legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit 104 multiprocessor communication function: a multiprocessor format, in which a multiprocessor bit is added to the transfer data, can be used for serial communication, enabling data transfer to be performed among a number of processors. the transmitting station first sends the id of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips the data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. sci synchronous communication: in synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. data length: 8 bits per character overrun error detection selection of on-chip baud rate generator or external clock from sck pin as transmit/receive clock source selection of lsb-first or msb-first transfer communication is possible with chips provided with a synchronous mode, such as the h8 series, hd64180, and hd6301 105 transmitting station receiving station a (id = 01) receiving station b (id = 02) receiving station c (id = 03) receiving station d (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend: mpb: multiprocessor bit figure 3.33 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) don? care don? care one unit of transfer data (character or frame) bit 0 serial data serial clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * note: * high except in continuous transfer * figure 3.34 data format in synchronous communication 106 table 3.8 brr settings for various bit rates (clocked synchronous mode) operating frequency ? (mhz) bit rate ? = 2 mhz ? = 4 mhz ? = 6 mhz ? = 8 mhz ? = 10 mhz (bit/s) n n n n n n n n n n 110 3 70 250 2 124 2 249 3 124 500 1 249 2 124 2 249 1 k 1 124 1 249 2 124 2.5 k 0 199 1 99 1 149 1 199 1 249 5 k 0 99 0 199 1 74 1 99 1 124 10 k 0 49 0 99 0 149 0 199 0 249 25 k 0 19 0 39 0 59 0 79 0 99 50 k 0 9 0 19 0 29 0 39 0 49 100 k 0 4 0 9 0 14 0 19 0 24 250 k 0 1 0 3 0 5 0 7 0 9 500 k 0 0 * 01020304 1 m 0 0 * 01 2.5 m 00 * 5 m note: as far as possible, the setting should be made so that the error is no more than 1%. legend: blank: cannot be set. : can be set, but there will be a degree of error. * : continuous transfer is not possible. 107 the brr setting is found from the following formulas. asynchronous mode: n = 10 6 ?1 64 2 2n? b f clocked synchronous mode: n = 10 6 ?1 8 2 2n? b f where b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) ? : operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) n clock 0 ? 1 ? /4 2 ? /16 3 ? /64 3.8 smart card interface the sci supports a smart card interface as an ic card interface serial communication function conforming to iso/iec7816-3 (identification card). 3.8.1 features asynchronous mode ? data length: 8 bits ? parity bit generation and checking ? transmission of error signal (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported internal baud rate generator allows any bit rate to be selected three interrupt sources ? three interrupt sourcestransmit data empty, receive data full, and transmit/receive errorthat can issue requests independently ? the transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (dtc) to execute data transfer 108 bus interface tdr tsr transmission/ reception control baud rate generator internal data bus rxd txd sck parity generation parity check clock ?4 ?16 ?64 txi rxi eri module data bus rsr rdr scmr ssr scr brr smr legend: scmr: smart card mode register rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register brr: bit rate register figure 3.35 smart card interface block diagram 3.8.2 operation only asynchronous communication is supported, with one frame consisting of 8-bit data plus and a parity bit. in transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. if a parity error is detected during reception, a low error signal level is output for a 1 etu period 10.5 etu after the start bit. if the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. 109 3.8.3 schematic connection diagram txd rxd sck rx (port) these series i/o clk rst v cc connected equipment ic card data line clock line reset line figure 3.36 schematic diagram of smart card interface pin connections 3.8.4 data format ds d0 d1 d2 d3 d4 d5 d6 d7 dp when there is no parity error transmitting station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error occurs transmitting station output de receiving station output legend: ds: start bit d0 to d7: data bits dp: parity bit de: error signal figure 3.37 smart card interface data format 110 3.9 a/d converter these series incorporate an on-chip a/d converter with 10-bit precision. analog signals can be input on up to eight channels by the program. 3.9.1 features 10-bit resolution eight input channels settable analog conversion voltage range ? conversion of analog voltages from 0 v to v ref, with the reference voltage pin (v ref ) as the analog reference voltage high-speed conversion ? minimum conversion time: ? 13.4 m s per channel (at 10 mhz operation) selection of single mode or scan mode ? single mode: a/d conversion of one channel ? scan mode: continuous conversion on one to four channels three kinds of conversion start ? selection of software or timer conversion start trigger (tpu or 8-bit timer), or adtrg pin four data registers ? conversion results held in a data register for each channel sample and hold function a/d conversion end interrupt generation ? a/d conversion end interrupt (adi) request can be generated at the end of a/d conversion module stop mode can be set ? as the initial setting, a/d converter operation is halted. register access is enabled by exiting module stop mode. 111 on-chip data bus bus interface module data bus 10-bit d/a successive- approximations register addra addrb addrc addrd adcsr adcr control circuit comparator sample-and- hold circuit + ?4 ?16 ?2 ?8 adi externally triggered by tpu or 8-bit timer analog multi- plexer avcc vref avss an0 an1 an2 an3 an4 an5 an6 an7 adtrg legend: adcr: adcsr: addra: addrb: addrc: addrd: a/d control register a/d control/status register a/d data register a a/d data register b a/d data register c a/d data register d figure 3.38 a/d converter block diagram 112 input channel setting eight-channel analog input is performed by means of the scan mode bit (scan) and channel select bits (ch2 to ch0) in adcsr. bit 2 bit 1 bit 0 description ch2 ch1 ch0 single mode (scan = 0) scan mode (scan = 1) 0 0 0 an0 (initial value) an0 1 an1 an0 to an1 1 0 an2 an0 to an2 1 an3 an0 to an3 1 0 0 an4 an4 1 an5 an4 to an5 1 0 an6 an4 to an6 1 an7 an4 to an7 operation the successive comparison method is used for a/d conversion, with a 10-bit resolution. there are two operating modessingle or scan. single mode: single mode is selected when a/d conversion is to be performed on a single channel only. a/d conversion is started when the adst bit is set to 1, according to the specified conversion start condition. on completion of conversion, the adf flag is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. scan mode: scan mode is selected when a/d conversion is to be performed repeatedly on a number of channels. once the adst bit is set to 1 according to the specified conversion start condition, a/d conversion is performed repeatedly on the selected channel until the adst bit is cleared to 0 by software. an adi interrupt request can be generated on completion of the first conversion operation for all the selected input channels. 113 3.10 d/a converter the h8s/2237 series has an on-chip d/a converter with 8-bit precision. analog signals can be output on up to two channels by the program. 3.10.1 features eight-bit resolution two output channels maximum conversion time of 10 m s (with 20 pf load capacitance) output voltage of 0 v to v ref d/a output hold function in software standby mode module stop mode can be set ? as the initial setting, d/a converter operation is halted. register access is enabled by exiting module stop mode. 3.10.2 operation d/a converter operation is enabled by setting the d/a output enable bit to 1. while this bit is set to 1, dadr contents are constantly converted and output to the corresponding pin. the output value is: dadr contents 256 v ref 114 3.10.3 d/a converter block diagram module data bus internal data bus vref avcc da1 da0 avss 8-bit d/a control circuit dadr0 bus interface dadr1 dacr legend: dacr: d/a control register dadr0: d/a data register 0 dadr1: d/a data register 1 figure 3.39 block diagram of d/a converter 3.11 i/o ports the h8s/2237 series and h8s/2227 series have ten i/o ports (ports 1, 3, 7, and a to g), and two input-only ports (ports 4 and 9). each port includes a data direction register (ddr) that controls input/output, a data register (dr) that stores output data, and a port register (port) used to read the pin states. in addition to ddr and dr, ports a to e also have a mos input pull-up control register (pcr) to control the on/off state of mos pull-up. 115 table 3.9 h8s/2237 series port functions in each operating mode port description pins modes 4 and 5 mode 6 mode 7 port 1 8-bit i/o port schmitt- triggered input ( irq1 , irq0 ) p17/tiocb2/tclk d p16/tioca2/ irq1 p15/tiocb1/tclk c p14/tioca1/ irq0 8-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2), and external interrupt input ( irq0 , irq1 ) p13/tiocd0/tclk b/a23 p12/tiocc0/tclk a/a22 p11/tiocb0/a21 p10/tioca0/a20 8-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tioca0, tiocb0, tiocc0, tiocd0), external interrupt input ( irq0 , irq1 ), and address output (a20 to a23) port 3 7-bit i/o port open-drain output capability schmitt- triggered input ( irq5 , irq4 ) p36 p35/sck1/ irq5 p34/rxd1 p33/txd1 p32/sck0/ irq4 p31/rxd0 p30/txd0 7-bit i/o port also functioning as sci (channel 0 and 1) i/o pins (txd0, rxd0, sck0, txd1, rxd1, sck1) and interrupt input ( irq4 , irq5 ) port 4 8-bit input port p47/an7Cp40/an0 8-bit input port also functioning as a/d converter analog input (an7 to an0) port 7 8-bit i/o port p77/txd3 p76/rxd3 p75/sck3 p74/ mres 8-bit i/o port also functioning as sci (channel 3) i/o pins (txd3, rxd3, sck3), manual reset pin ( mres ), and 8-bit timer (channel 0 and 1) i/o pins (tmri01, tmci01, tmo0, tmo1) p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci0 1/ cs4 when ddr = 0: input port also functioning as 8-bit timer (channel 0 and 1) i/o pins when ddr = 1: 8-bit timer (channel 0 and 1) i/o pins also functioning as cs7 to cs4 output 116 port description pins modes 4 and 5 mode 6 mode 7 port 9 2-bit input port p97/da1Cp96/da0 2-bit input port also functioning as d/a converter analog output (da1, da0) port a 4-bit i/o port built-in mos input pull-up open-drain output capability pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0/a16 i/o port also functioning as sci (channel 2) i/o pins (txd2, rxd2, sck2) and address output (a16 to a19) i/o port also functioning as sci (channel 2) i/o pins (txd2, rxd2, sck2) port b 8-bit i/o port built-in mos input pull-up pb7/a15/tiocb5 pb6/a14/tioca5 pb5/a13/tiocb4 pb4/a12/tioca4 pb3/a11/tiocd3 pb2/a10/tiocc3 pb1/a9/tiocb3 pb0/a8/tioca3 i/o port also functioning as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, tiocb5) and address output (a8 to a15) i/o port also functioning as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, tiocb5) port c 8-bit i/o port built-in mos input pull-up pc7/a7Cpc0/a0 address output (a0 to a7) when ddr = 0: input port when ddr = 1: address output i/o port port d 8-bit i/o port built-in mos input pull-up pd7/d15Cpd0/d8 data bus input/output i/o port port e 8-bit i/o port built-in mos input pull-up pe7/d7Cpe0/d0 8-bit bus mode: i/o port 16-bit bus mode: data bus input/output i/o port port f 8-bit i/o port schmitt- triggered input ( irq3 , irq2 ) pf7/ ? when ddr = 0: input port when ddr = 1 (after reset): ? output when ddr = 0 (after reset): input port when ddr = 1: ? output pf6/ as pf5/ rd pf4/ hwr as , rd , hwr output i/o port pf3/ lwr / adtrg / irq3 16-bit bus mode: lwr output 8-bit bus mode: i/o port also functioning as interrupt input pin ( irq3 ) and a/d converter input ( adtrg ) i/o port also functioning as interrupt input pin ( irq3 ) and a/d converter input ( adtrg ) pf2/ wait when waite = 0 (after reset): i/o port when waite = 1: wait input i/o port 117 port description pins modes 4 and 5 mode 6 mode 7 port f 8-bit i/o port schmitt- triggered input ( irq3 , irq2 ) pf1/ back /buzz when brle = 0 (after reset): i/o port also functioning as wdt output pin (buzz) when brle = 1: back output i/o port also functioning as wdt output pin (buzz) pf0/ breq / irq2 when brle = 0 (after reset): i/o port also functioning as interrupt input pin ( irq2 ) when brle = 1: breq input also functioning as interrupt input pin ( irq2 ) i/o port also functioning as interrupt input pin ( irq2 ) port g 5-bit i/o port schmitt- triggered pg4/ cs0 when ddr = 0 * 1 : input port when ddr = 1 * 2 : cs0 output i/o port also functioning as interrupt input pins input ( irq7 , irq6 ) pg3/ cs1 pg2/ cs2 pg1/ cs3 / irq7 when ddr = 0 (after reset): input port also functioning as interrupt input pin ( irq7 ) when ddr = 1: interrupt input pin ( irq7 ) also functions as cs1 , cs2 , cs3 output ( irq6 , irq7 ) pg0/ irq6 notes: 1. after a mode 6 reset 2. after a mode 4 or 5 reset 118 table 3.10 h8s/2227 series port functions in each operating mode port description pins modes 4 and 5 mode 6 mode 7 port 1 8-bit i/o port schmitt- triggered input ( irq1 , irq0 ) p17/tiocb2/tclkd p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2) and interrupt input ( irq0 , irq1 ) p13/tiocd0/tclkb/ a23 p12/tiocc0/tclka/ a22 p11/tiocb0/a21 p10/tioca0/a20 i/o port also functioning as tpu i/o pins (tclka, tclkb, tioca0, tiocb0, tiocc0, tiocd0) and address output (a20 to a23) port 3 7-bit i/o port open-drain output capability schmitt- triggered input ( irq5 , irq4 ) p36 p35/sck/ irq5 p34/rxd1 p33/txd1 p32/sck0/ irq4 p31/rxd0 p30/txd0 7-bit i/o port also functioning as sci (channel 0 and 1) i/o pins (txd0, rxd0, sck0, txd1, rxd1, sck1) and interrupt input ( irq4 , irq5 ) port 4 8-bit input port p47/an7Cp40/an0 8-bit input port also functioning as a/d converter analog input (an7 to an0) port 7 8-bit i/o port p77/txd3 p76/rxd3 p75/sck3 p74/ mres 8-bit i/o port also functioning as sci (channel 3) i/o pins (txd3, rxd3, sck3), manual reset pin ( mres ), and 8-bit timer (channel 0 and 1) i/o pins (tmri01, tmci01, tmo0, tmo1) p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 when ddr = 0: input port also functioning as 8-bit timer (channel 0 and 1) i/o pins when ddr = 1: 8-bit timer (channel 0 and 1) i/o pins also functioning as cs7 to cs4 output port 9 2-bit input port p97 , p96 input port port a 4-bit i/o port built-in mos input pull-up open-drain output capability pa3/a19Cpa0/a16 i/o port also functioning as address output (a16 to a19) i/o port port b 8-bit i/o port built-in mos input pull-up pb7/a15Cpb0/a8 i/o port also functioning as address output (a8 to a15) i/o port 119 port description pins modes 4 and 5 mode 6 mode 7 port c 8-bit i/o port built-in mos input pull-up pc7/a7Cpc0/a0 address output (a0 to a7) i/o port also functioning as address output (a0 to a7) i/o port port d 8-bit i/o port built-in mos input pull-up pd7/d15Cpd0/d8 data bus input/output i/o port port e 8-bit i/o port built-in mos input pull-up pe7/d7Cpe0/d0 8-bit bus mode: i/o port 16-bit bus mode: data bus input/output i/o port port f 8-bit i/o port schmitt- triggered input ( irq3 , irq2 ) pf7/ ? when ddr = 0: input port when ddr = 1 (after reset): ? output when ddr = 0 (after reset): input port when ddr = 1: ? output pf6/ as pf5/ rd pf4/ hwr as , rd , hwr output i/o port pf3/ lwr / adtrg / irq3 16-bit bus mode: lwr output 8-bit bus mode: i/o port also functioning as interrupt input pin ( irq3 ) and a/d converter input ( adtrg ) i/o port also functioning as interrupt input pin ( irq3 ) and a/d converter input ( adtrg ) pf2/ wait when waite = 0 (after reset): i/o port when waite = 1: wait input i/o port pf1/ back /buzz when brle = 0 (after reset): i/o port also functioning as wdt output pin (buzz) when brle = 1: back output i/o port also functioning as wdt output pin (buzz) pf0/ breq / irq2 when brle = 0 (after reset): i/o port also functioning as interrupt input pin ( irq2 ) when brle = 1: breq input also functioning as interrupt input pin ( irq2 ) i/o port also functioning as interrupt input pin ( irq2 ) 120 port description pins modes 4 and 5 mode 6 mode 7 port g 5-bit i/o port schmitt- triggered input ( irq7 , irq6 ) pg4/ cs0 when ddr = 0 * 1 : input port when ddr = 1 * 2 : cs0 output i/o port also functioning as interrupt input pins ( irq6 , irq7 ) pg3/ cs1 pg2/ cs2 pg1/ cs3 / irq7 when ddr = 0 (after reset): input port also functioning as interrupt input pin ( irq7 ) when ddr = 1: interrupt input pin ( irq7 ) also functions as cs1 , cs2 , cs3 output pg0/ irq6 notes: 1. after a mode 6 reset 2. after a mode 4 or 5 reset 121 3.12 ram the on-chip ram is connected to the cpu by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. this makes it possible to perform fast word data transfer. the on-chip ram can be enabled or disabled by means of the ram enable bit (rame) in the system control register (syscr). internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffb000 h'ffb002 h'ffb004 h'ffefbe h'ffb001 h'ffb003 h'ffb005 h'ffefbf h'ffffc0 h'fffffe h'ffffc1 h'ffffff figure 3.40 block diagram of ram (example of h8s/2237, h8s/2227) ram size ram (bytes) h8s/2237 series h8s/2227 series 16 k h8s/2237 h8s/2227 4 k h8s/2235, h8s/2233 h8s/2225, h8s/2223 122 3.12.1 features the on-chip ram in the h8s/2237 and h8s/2227 is allocated to addresses h'ffb000 h'ffefbf and h'ffffc0h'ffffff (16 kbytes). the on-chip rom in the h8s/2235, h8s/2233, h8s/2225, and h8s/2223 is allocated to addresses h'ffe000h'ffefbf and h'ffffc0h'ffffff (4 kbytes). 123 3.13 rom the rom is connected to the cpu by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. this makes possible rapid instruction fetches and high-speed processing. h'000000 h'000002 h'01fffe h'000001 h'000003 h'01ffff internal data bus (upper 8 bits) internal data bus (lower 8 bits) figure 3.41 rom block diagram (example of h8s/2237 in modes 6 and 7) prom or mask rom size rom (bytes) h8s/2237 series h8s/2227 series 128 k h8s/2237, h8/2235 h8s/2227, h8s/2225 64 k h8s/2233 h8s/2223 prom programming (ztat?) this programming can be done with a prom programmer set up in the same way as for the hn27c101 eprom (v pp = 12.5 v). use of a 100-pin/32-pin socket adapter enables programming with a commercial prom programmer. the address range is h'00000 to h'1ffff. however, page programming is not supported. 124 section 4 power-down modes in addition to the normal program execution state, the these series have power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting modules, and so on. these series operating modes are as follows: 1. high-speed mode 2. medium-speed mode 3. subactive mode 4. sleep mode 5. subsleep mode 6. watch mode 7. module stop mode 8. software standby mode 9. hardware standby mode of these, 2 to 9 are power-down modes. sleep mode and subsleep mode are cpu modes, medium- speed mode is a cpu and bus master mode, subactive mode is a cpu, bus master, and on-chip supporting module mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the cpu). a combination of certain of these modes can be set. medium-speed mode when bits sck2 to sck0 in the standby control register (sbycr) are set to 1 in high-speed mode, medium-speed mode is entered as soon as the current bus cycle ends. in medium-speed mode, the bus mastersthe cpu and dtcoperate on the operating clock (f/2, f/4, f/8, f/16, or f/32) specified by bits sck2 to sck0. however, on-chip supporting modules other than the bus masters operate on the high-speed clock (f). subactive mode if a sleep instruction is executed in high-speed mode when the ssby bit in sbycr is set to 1, the dton bit and lson bit in the low-power control register (lpwrcr) are both set to 1, and the pss bit in the timer control/status register (tcsr (wdt1)) is set to 1, the cpu enters subactive mode. a transition to subactive mode is also caused by an interrupt generated in watch mode when the lson bit in lpwrcr is set to 1, and by an interrupt generated in subsleep mode. in subactive mode, the cpu performs low-speed sequential program execution using the subclock, and supporting modules other than tmr, wdt0, and wdt1 are halted. 125 sleep mode if a sleep instruction is executed when the ssby bit in sbycr and the lson bit in lpwrcr are both cleared to 0, the cpu enters sleep mode. in sleep mode, cpu operation stops but the contents of the cpus internal registers are retained. other supporting modules do not stop. subsleep mode if a sleep instruction is executed in subactive mode when the ssby bit in sbycr is cleared to 0, the lson bit in lpwrcr is set to 1, and the pss bit in tcsr (wdt1) is set to 1, the cpu enters subsleep mode. in subsleep mode, cpu operation stops, together with the operation of supporting modules other than tmr, wdt0, and wdt1. as long as the specified voltage is supplied, the contents of cpu registers, some on-chip peripheral registers, and on-chip ram are retained, and i/o ports retain their states prior to the transition. watch mode if a sleep instruction is executed in high-speed mode or subactive mode when the ssby bit in sbycr is set to 1, the dton bit in lpwrcr is cleared to 0, and the pss bit in tcsr (wdt1) is set to 1, the cpu enters watch mode. in watch mode, cpu operation stops, together with the operation of supporting modules other than wdt1. as long as the specified voltage is supplied, the contents of cpu registers, some on-chip peripheral registers, and on-chip ram are retained, and i/o ports retain their states prior to the transition. module stop mode module stop mode can be set for individual on-chip supporting modules. when the mstp bit corresponding to a particular supporting module in the module stop control register (mstpcr) is set to 1, operation of the specified module stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. software standby mode if a sleep instruction is executed when the ssby bit in sbycr is set to 1, the lson bit in lpwrcr is cleared to 0, and the pss bit in tcsr (wdt1) is cleared to 0, software standby mode is entered. in this mode, the cpu, on-chip supporting modules, and oscillator all stop. however, the contents of the cpus internal registers, on-chip ram data, the states of on-chip supporting modules other than the a/d and d/a, and the states of i/o ports, are retained. hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any state. in hardware standby mode, all functions enter the reset state and stop operation, resulting in extremely low power consumption. as long as the specified voltage is supplied, on-chip ram data is retained. i/o ports go to the high-impedance state. 126 hardware standby mode stby pin = low notes: * 1 nmi, irq0 to irq7, and wdt1 interrupts * 2 nmi, irq0 to irq7, and wdt0 interrupts, wdt1 interrupt, tmr0 interrupt, tmr1 interrupt * 3 all interrupts * 4 nmi, irq0 to irq7 ? when a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. ? from any state except hardware standby mode, a transition to the power-on reset state occurs when res goes low. from any state except hardware standby mode and the power-on reset state, a transition to the manual reset state occurs when mres goes low. ? from any state, a transition to hardware standby mode occurs when stby goes low. ? when making a transition to watch mode, high-speed mode or subactive mode must be set. when making a transition to subactive mode, high-speed mode must be set. sleep mode (main clock) ssby = 0, lson = 0 software standby mode ssby = 1 pss = 0, lson = 0 watch mode (subclock) ssby = 1 pss = 1, dton = 0 subsleep mode (subclock) ssby = 0 pss = 1, lson = 1 medium-speed mode (main clock) subactive mode (subclock) high-speed mode (main clock) power-on reset state manual reset state stby pin = high res pin = low res pin = high mres pin = high sleep instruction ssby = 1, pss = 1, dton = 1, lson = 0 clock switching exception handling after oscillation stabilization time (sts2 to sts0) sleep instruction ssby = 1, pss = 1, dton = 1, lson = 1 clock switching exception handling sck2 to sck0 1 0 sck2 to sck0 = 0 program-halted state reset state sleep instruction any interrupt * 3 sleep instruction external interrupt * 4 sleep instruction interrupt * 1 , lson bit = 0 sleep instruction interrupt * 1 , lson bit = 1 interrupt * 2 sleep instruction : transition after exception handling : power-down mode program execution state figure 4.1 mode transitions 127 table 4.1 internal states in each mode function high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby system clock oscillator function- ing function- ing function- ing function- ing halted halted halted halted halted subclock input function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing/halted halted cpu operation instruc- tions function- ing medium- speed operation halted function- ing halted subclock operation halted halted halted registers retained retained retained retained undefined external interrupts function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing halted peripheral function pbc function- ing medium- speed function- ing function- ing/halted halted (retained) subclock operation halted (retained) halted (retained) halted (reset) operation dtc operation (retained) halted (retained) wdt1 function- ing function- ing function- ing function- ing subclock operation subclock operation subclock operation wdt0 halted (retained) tmr function- ing/halted tpu (retained) halted halted sci (retained) (retained) a/d function- ing/halted halted (reset) halted (reset) halted (reset) halted (reset) d/a (reset) ram function- ing function- ing function- ing (dtc) function- ing retained function- ing retained retained retained i/o function- ing function- ing function- ing function- ing retained function- ing function- ing retained high impedance note: halted (retained) means that internal register values are retained. the internal state is operation interrupted. halted (reset) means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 128 table 4.2 power-down mode transition conditions control bit states at time of transition state before transition ssby pss lson dton state after transition by sleep instruction state after return by interrupt high-speed/ medium-speed 0 * 0 * sleep high-speed/ medium-speed 0 * 1 * 100 * software standby high-speed/ medium-speed 101 * 1100 watch high-speed 1110 watch subactive 1101 1111 subactive subactive 0 0 ** 010 * 011 * subsleep subactive 10 ** 1100 watch high-speed 1110 watch subactive 1101 high-speed 1111 * : dont care : do not set. 129 section 5 development environment 5.1 development environment a comprehensive development environment is provided for these series, including cross software, emulators, an hi series os*, and products offered by third-party suppliers. 5.1.1 lineup cross software ? c compiler ? assembler ? simulator/debugger emulators ? e6000 hi series os* ? hi8-2600 third-party products ? cross software ? emulators c compiler simulator/debugger realtime os h8s series assembler hi series (compliant with itron specification) * os emulators e6000 e6000 note: * the hi series os is hitachi real-time os compliant with m itron specifications. the product described in this publication is based on the itron specifications and was developed under the guidance of dr. ken sakamura of the university of tokyo. itron is an acronym of industrial tron. tron is an acronym of the real time operating system nucleus. m itron is an acronym of micro industrial tron. 130 5.2 cross software various kinds of cross softwareincluding a c compiler, assembler, and simulator/debuggerare available for these series, to improve development efficiency. c compiler: the c programming language allows system operation and control structures to be written in a concise form. the c compiler converts a program written in c into machine language. comprehensive support of h8s/2600. h8s/2000, h8/300, h8/300l, and h8/300 series complies with ansi (american national standard institute) c standard proposals object program size reduced by an average 30% or more through optimization processing extended functions for product embedding ? built-in function facility: h8/2000 system control instructions can be written in function call format ? memory access function: efficient memory access provided by short absolute addressing mode and indirect memory addressing mode ? assembler embedding: assembly language code can be mixed in with c code ? interrupt function creation: interrupt vector setting and interrupt handling routines can be written in c generates object designed with rom programming in mind implements optimization between modules dependent on memory location and function call relationships, across source files supports debugging information output in optimization assembler: assembly language is suited to hardware-dependent processing that requires fast execution. the assembler converts a program written in assembly language into machine language. common assembly language for entire h series structured assembler for easy maintenance ? supports if, for, while, repeat statements, etc. execution instructions and control instructions compliant with ieee standards efficient macro functions 131 simulator/debugger: cpu operation can be simulated by software, and operation of a completed program can be tested without using the actual device. operates on host computer without a target system various powerful debugging functions ? pc, data, register, sequential, and other break conditions can be set ? a 1023-instruction trace buffer is supported, and traces can be executed in instruction or subroutine units ? support of single-line assembly, disassembly, state retention, command history, etc. table 5.1 cross software product lineup host machine c compiler assembler system simulator/debugger ibm pc pps008pc200ia * 1 pps008pc200ia * 1 flora (dos/v) ps008cas2-if3 * 2 ps008cas2-if3 * 2 ps008cas2-if3 * 2 pc-9800 series ps008cpc200ie3 ps008asm2-if3 ps008sim1-if3 windows 95 pps008pc200wa * 1 pps008pc200wa * 1 (pc-9800 series, ps008cas2-mw * 2 ps008cas2-mw * 2 ps008cas2-mw * 2 ibm pc, flora) ps008cpc200iw ps008asm2-mw ps008sim1-mw sparc pps008sl200a * 1 pps008sl200a * 1 (sun os) ps008cas2-slc * 2 ps008cas2-slc * 2 ps008cas2-slc * 2 ps008csl200 ps008asm2-slc ps008sim1-spc sparc pps008sl200a * 1 pps008sl200a * 1 (solaris) ps008cas2-slc * 2 ps008cas2-slc * 2 ps008cas2-slc * 2 hss008clcs2sm hss008ascs2sm hss008sdcs1sm hp9000/700 pps008hp200a * 1 pps008hp200a * 1 hitachi 9000 ps008cas2-h7d * 2 ps008cas2-h7d * 2 ps008cas2-h7d * 2 hitachi 9000v ps008chp7200 ps008asm2-h7d ps008sim1-h7d notes: 1. c compiler package (c compiler + assembler) 2. c compiler/simulator package (c compiler + assembler + simulator) 132 5.3 emulators the e6000 emulator, incorporating a wide variety of functions, is available for use with these series. e6000: the e6000 emulator provides an efficient debugging environment within a windows environment. it is equipped with a dos/v personal computer interface (covering desktop to notebook models), and offers simple operation via a graphical user interface on windows 3.1 or windows 95. the e6000 provides enhanced emulation functions in a compact a5-size body. trace functions ? 80-bit 32k-cycle trace capability, with provision for up to 12 trigger points and sequential settings up to 8 levels ? subroutine trace, specific-condition trace, and point-to-point trace settings ? provision for a time trace every trace cycle break functions ? up to 12 hardware breaks can be set, with provision for sequential settings of up to 8 levels (shared with trace triggers) ? a maximum of 255 software breaks can be set fast downloading ? 4-mbyte/minute downloading c source level debugging ? halting of program execution in the c source program ? displays contents of specified variables in the source program support for windows environment ? runs on windows 3.1 or windows 95 ? comprehensive help functions, for manual-less operation ? more efficient mouse operations through use of pull-down menus and buttons for frequently used commands performance functions ? number of subroutine time measurement modules (max. 8 channels), maximum/minimum measurement (4 channels) ? number of subroutine execution count measurement modules (max. 8 channels) ? timeout function ? number of run time measurement modules (2 channels) ? sampling time (1 m s, 250 ns, 20 ns) 133 table 5.2 emulator product lineup e6000 emulator host system interface board expansion memory user cable hs2633epi60h * (for ibm pc) hs6000eii01h (ibm pc interface board) hs6000ems11h (1m-sram) hs6000ems12h (4m-sram) hs2237ech61h * (fp-100b, tfp-100b) hs2237ecf61h * (fp-100a) note: * under development 134 5.4 socket adapters a socket adapter is a pin conversion adapter for writing or verifying a program in the on-chip prom of a microcomputer using a prom programmer. a different adapter is available for each product and package type, so be sure to choose the correct adapter for the product concerned. table 5.3 applicable eprom programmers product package socket adapter h8s/2237 tfp-100b under development tfp-100g fp-100a fp-100b method of use: refer to the socket adapter instruction manual for details. index pin 1 indication pin 1 indication figure 5.1 method of use 135 5.5 hi series os an hi series os is available for these series, which enables the program structure to be made explicit and a custom-made operating system to be constructed. 5.5.2 features of hi8-2600 series emphasis on real-time performance ? microsecond-order response to interrupts from off-chip support for synchronous communication timeout specification variable-length memory pool function rom implementation capability ? designed with product embedding modular structure using building-block system ? system can be constructed by selecting modules according to the scale of the application system improved development efficiency and reliability ? shorter development time, lower development costs, improved serviceability and reliability support for e6000 emulator multitask debugger ? a multitask debugger that runs in an e6000 emulator windows environment is available, offering more efficient application debugging via a graphical user interface. h8s user application tasks i/o driver tasks interrupt management task attach- ment synchronous communication time manage- ment system manage- ment task manage- ment scheduler figure 5.2 hi8-2600 system configuration diagram 136 table 5.4 hi series os product lineup host machine ibm pc flora (dos/v) pc-9800 series sparc (sun os) sparc (solaris) hp9000/700 hitachi 9000 hi series os hss008itin2sfb (for object contract) hss008itcn2smb (for object contract) hss008itcn2smb (for object contract) hss008ithn2stb (for object contract) hss008itin2sfs (for source contract) hss008itcn2sms (for source contract) hss008itcn2sms (for source contract) hss008ithn2sts (for source contract) multitask debugger hss008ihin1sf * hss008ihin1sf * hss008ihin1sf * hss008ihin1sf * note: * under development 137 appendix a.1 packages package dimension diagrams (unit: mm) indication according to geometrical tolerances pin precision y indication allowable value pin precision tolerance method based on maximum solid state tolerance value kind of geometrical tolerance (in this case, positional tolerance) example: b 0.12 this indicates that the allowable pin displacement from the true central position is 0.12 mm when pin width b is the maximum dimension. if b is smaller than the maximum dimension, the tolerance can be extended accordingly. x m m y 138 16.0 0.2 14 0.08 0.10 0.5 0.1 16.0 0.2 0.5 0.10 0.10 1.20 max 0.17 0.05 0 ?8 75 51 125 76 100 26 50 m 0.22 0.05 1.0 1.00 1.0 0.20 0.04 0.15 0.04 unit: mm dimension including the plating thickness base material dimension tfp-100b 139 14.0 0.2 12 0.07 0.10 0.5 0.1 14.0 0.2 0.4 1.20 max 0.17 0.05 0 ?8 75 51 125 76 100 26 50 m 0.18 0.05 1.0 1.2 0.16 0.04 0.15 0.04 1.00 0.10 0.10 unit: mm dimension including the plating thickness base material dimension tfp-100g 140 0.13 m 0 ?10 0.32 0.08 0.17 0.05 3.10 max 1.2 0.2 24.8 0.4 20 80 51 50 31 30 1 100 81 18.8 0.4 14 0.15 0.65 2.70 2.4 0.20 +0.10 ?.20 0.58 0.83 0.30 0.06 0.15 0.04 unit: mm dimension including the plating thickness base material dimension fp-100a 141 0.10 16.0 0.3 1.0 0.5 0.2 16.0 0.3 3.05 max 75 51 50 26 1 25 76 100 14 0 ?8 0.5 0.08 m 0.22 0.05 2.70 0.17 0.05 0.12 +0.13 ?.12 1.0 0.20 0.04 0.15 0.04 unit: mm dimension including the plating thickness base material dimension fp-100b 142 h8s/2237 series, h8s/2227 series overview publication date: 1st edition, march 1998 published by: electronic devices business group hitachi, ltd. edited by: technical documentation center hitachi microcomputer system ltd. copyright ? hitachi, ltd., 1998. all rights reserved. printed in japan. |
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