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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. document no. u17728ej3v1ud00 (3rd edition) date published march 2008 n printed in japan user?s manual v850es/sg3 32-bit single-chip microcontrollers hardware 2005 pd70f3333(a) pd70f3334(a) pd70f3335(a) pd70f3336(a) pd70f3340(a) pd70f3341(a) pd70f3342(a) pd70f3343(a) pd70f3350(a) pd70f3351(a) pd70f3352(a) pd70f3353(a) user?s manual u17728ej3v1ud 2 [memo] user?s manual u17728ej3v1ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 user?s manual u17728ej3v1ud 4 caution: this product uses superflash ? technology licensed from silicon storage technology, inc. iecube is a registered trademark of nec el ectronics corporation in japan and germany. minicube is a registered tradem ark of nec electronics corporati on in japan and germany or a trademark in the united states of america. eeprom, iebus, and inter equipment bus are trademarks of nec electronics corporation. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. superflash is a registered trademark of silicon st orage technology, inc. in several countries including the united states and japan. user?s manual u17728ej3v1ud 5 the information in this document is current as of january, 2008. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": user?s manual u17728ej3v1ud 6 preface readers this manual is intended for users who wish to understand the functions of the v850es/sg3 and design application systems using these products. purpose this manual is intended to give users an understanding of the har dware functions of the v850es/sg3 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? data types ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. cautions 1. the application examples in this manual a pply to ?standard? quality grade products for genera l electronic systems. when using an example in this manual fo r an application that requires a ?special? quality grade product, thoroughly evaluate the component and circuit to be actually used to see if they satisfy the special quality grade. 2. when using this manual as a manual for a special grade product, read the part numbers as follows. pd70f3333 pd70f3333(a) pd70f3334 pd70f3334(a) pd70f3335 pd70f3335(a) pd70f3336 pd70f3336(a) pd70f3340 pd70f3340(a) pd70f3341 pd70f3341(a) pd70f3342 pd70f3342(a) pd70f3343 pd70f3343(a) pd70f3350 pd70f3350(a) pd70f3351 pd70f3351(a) pd70f3352 pd70f3352(a) pd70f3353 pd70f3353(a) user?s manual u17728ej3v1ud 7 to understand the overall func tions of the v850es/sg3 read this manual according to the contents . to find the details of a regi ster where the name is known use appendix c register index . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defi ned as a reserved word in the device file. to know the electrical spec ifications of the v850es/sg3 see chapter 32 electrical specifications (target) . to understand the details of an instruction function refer to the v850es architecture user?s manual available separately. the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that if ?xxx. yyy? is described as is in a program, however, the compiler/assembler cannot recognize it correctly. the mark user?s manual u17728ej3v1ud 8 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/sg3 document name document no. v850es architecture user?s manual u15943e v850es/sg3 hardware user?s manual this manual v850es/sg2, v850es/sg2-h hard ware user?s manual u16541e documents related to development tools document name document no. ie-v850es-g1 (in-circuit emulator) u16313e ie-703288-g1-em1 (in-circuit em ulator option board) u16697e ie-v850e1-cd-nw (pcmcia card ty pe on-chip debug emulator) u16647e qb-v850essx2 (in-circuit emulator) u17091e qb-v850mini (on-chip debug emulator) u17638e qb-mini2 (on-chip debug emulator with programming function) u18371e operation u17293e c language u17291e assembly language u17292e ca850 ver. 3.00 c compiler package link directive u17294e pm+ ver. 6.30 project manager u18416e id850 ver. 3.00 integrated debugger operation u17358e id850qb ver. 3.40 integrated debugger operation u18604e tw850 ver. 2.00 performance analysis tuning tool u17241e operation u18601e sm+ system simulation user open interface u18212e basics u13430e installation u17419e technical u13431e rx850 ver. 3.20 or later real-time os task debugger u17420e basics u18165e installation u17421e technical u13772e rx850 pro ver. 3.21 real-time os task debugger u17422e az850 ver. 3.30 system performance analyzer u17423e pg-fp4 flash memory programmer u15260e pg-fp5 flash memory programmer u18865e user?s manual u17728ej3v1ud 9 contents chapter 1 introduction ...................................................................................................... ...........21 1.1 general ........................................................................................................................ .............21 1.2 features....................................................................................................................... .............24 1.3 application fields ............................................................................................................. ......25 1.4 ordering information ........................................................................................................... ..26[ 1.5 pin configuration (top view) ......................................... ........................................................27 1.6 function block configuration........................................ ........................................................30 1.6.1 internal bl ock di agram ......................................................................................................... ...... 30 1.6.2 internal units ................................................................................................................. ............. 31 chapter 2 pin funct ions.................................................................................................... ............34 2.1 list of pin functions.......................................................................................................... .....34 2.2 pin states ..................................................................................................................... ............43 2.3 pin i/o circuit types, i/o buffer power suppli es, and connection of unused pins........44 2.4 cautions ....................................................................................................................... ............48 chapter 3 cpu function..................................................................................................... ............49 3.1 features....................................................................................................................... .............49 3.2 cpu register set............................................................................................................... ......50 3.2.1 program regi ster set ........................................................................................................... ....... 51 3.2.2 system regi ster set............................................................................................................ ........ 52 3.3 operation modes ................................................................................................................ .....58 3.3.1 specifying oper ation mode ...................................................................................................... .. 58 3.4 address space .................................................................................................................. ......59 3.4.1 cpu address space.............................................................................................................. ..... 59 3.4.2 wraparound of cpu addr ess spac e .......................................................................................... 60 3.4.3 memory map..................................................................................................................... ......... 61 3.4.4 areas .......................................................................................................................... ............... 63 3.4.5 recommended use of address s pace ....................................................................................... 73 3.4.6 peripheral i/o regist ers....................................................................................................... ....... 76 3.4.7 programmable peripheral i/o regist ers...................................................................................... 87 3.4.8 special r egister s .............................................................................................................. .......... 88 3.4.9 cauti ons ....................................................................................................................... ............. 92 chapter 4 port f unctions................................................................................................... .........96 4.1 features....................................................................................................................... .............96 4.2 basic port configuration ....................................................................................................... .96 4.3 port configuration........................................................... .................................................. ......97 4.3.1 port 0......................................................................................................................... .............. 102 4.3.2 port 1......................................................................................................................... .............. 105 4.3.3 port 3......................................................................................................................... .............. 106 4.3.4 port 4......................................................................................................................... .............. 113 4.3.5 port 5......................................................................................................................... .............. 116 4.3.6 port 7......................................................................................................................... .............. 120 user?s manual u17728ej3v1ud 10 4.3.7 port 9 ......................................................................................................................... ..............122 4.3.8 port cm ........................................................................................................................ ...........130 4.3.9 port ct ........................................................................................................................ ............132 4.3.10 port dh ........................................................................................................................ ............134 4.3.11 port dl ........................................................................................................................ ............136 4.4 block diagrams................................................................................................................. .... 139 4.5 port register settings when alternate function is used ................................................ 169 4.6 cautions ....................................................................................................................... ......... 177 4.6.1 cautions on se tting port pins .................................................................................................. .177 4.6.2 cautions on bit manipulation instru ction for port n r egister (pn) ...............................................180 4.6.3 cautions on on-ch ip debug pi ns...............................................................................................18 1 4.6.4 cautions on p05/in tp2/drst pin...........................................................................................181 4.6.5 cautions on p53 pin when power is tu rned on .........................................................................181 4.6.6 hysteresis char acterist ics ..................................................................................................... ...181 4.6.7 cautions on separ ate bus mode ..............................................................................................181 chapter 5 bus control function ................................ .......................................................... 18 2 5.1 features....................................................................................................................... .......... 182 5.2 bus control pins............................................................................................................... .... 183 5.2.1 pin status when internal rom, internal ra m, or on-chip peripher al i/o is a ccessed...............183 5.2.2 pin status in eac h operation mode ...........................................................................................183 5.3 memory block function....................................................................................................... 184 5.4 external bus interface mode control function ......... ........................................................ 185 5.5 bus access ..................................................................................................................... ...... 186 5.5.1 number of clo cks for a ccess.................................................................................................... 186 5.5.2 bus size setti ng func tion ...................................................................................................... ....186 5.5.3 access by bus si ze ............................................................................................................. .....187 5.6 wait function .................................................................................................................. ...... 194 5.6.1 programmable wait function ....................................................................................................1 94 5.6.2 external wait func tion......................................................................................................... ......195 5.6.3 relationship between programmabl e wait and exte rnal wa it ................................................... 196 5.6.4 programmable address wait func tion .......................................................................................197 5.7 idle state insertion function ............................................................................................... 198 5.8 bus hold function.............................................................................................................. .. 199 5.8.1 functional outlin e............................................................................................................. ........199 5.8.2 bus hold pr ocedur e............................................................................................................. .....200 5.8.3 operation in power save mode ................................................................................................200 5.9 bus priority ................................................................................................................... ........ 201 5.10 bus timing ..................................................................................................................... ....... 202 chapter 6 clock generation function .................... .......................................................... 208 6.1 overview....................................................................................................................... ......... 208 6.2 configuration .................................................................................................................. ...... 209 6.3 registers ...................................................................................................................... ......... 211 6.4 operation...................................................................................................................... ......... 216 6.4.1 operation of each cl ock ........................................................................................................ ...216 6.4.2 clock output functi on .......................................................................................................... .....216 6.5 pll function................................................................................................................... ...... 217 user?s manual u17728ej3v1ud 11 6.5.1 overvi ew ....................................................................................................................... .......... 217 6.5.2 regist ers ...................................................................................................................... ........... 217 6.5.3 usage .......................................................................................................................... ............ 221 chapter 7 16-bit timer/event counter p (tmp) .. ...............................................................222 7.1 overview....................................................................................................................... ..........222 7.2 functions ...................................................................................................................... .........222 7.3 configuration .................................................................................................................. .......223 7.4 registers ...................................................................................................................... ..........225 7.5 timer output operations............................................ ..........................................................23 8 7.6 operation...................................................................................................................... ..........239 7.6.1 interval timer mode (tpnmd2 to tpnmd0 bi ts = 000)............................................................. 246 7.6.2 external event count mode (tpn md2 to tpnmd0 bits = 001)................................................. 258 7.6.3 external trigger pulse output mode (tpnmd2 to tpnmd0 bits = 010) ..................................... 267 7.6.4 one-shot pulse output mode (tpn md2 to tpnmd0 bits = 011) .............................................. 279 7.6.5 pwm output mode (tpnmd2 to tpnmd0 bi ts = 100).............................................................. 286 7.6.6 free-running timer mode (tpnmd2 to tpnmd0 bi ts = 101) .................................................... 295 7.6.7 pulse width measurement mode (tpn md2 to tpnmd0 bits = 110) ........................................ 313 7.7 selector function .............................................................................................................. ....319 chapter 8 16-bit timer/event counter q (tmq) ... .............................................................321 8.1 overview....................................................................................................................... ..........321 8.2 functions ...................................................................................................................... .........321 8.3 configuration .................................................................................................................. .......322 8.4 registers ...................................................................................................................... ..........325 8.5 timer output operations............................................ ..........................................................34 1 8.6 operation...................................................................................................................... ..........342 8.6.1 interval timer mode (tq0md2 to tq0md0 bi ts = 000) ............................................................ 350 8.6.2 external event count mode (tq0 md2 to tq0md0 bits = 001) ................................................ 361 8.6.3 external trigger pulse output mode (tq0md2 to tq0md0 bits = 010) .................................... 371 8.6.4 one-shot pulse output mode (tq0 md2 to tq0md0 bits = 011) ............................................. 384 8.6.5 pwm output mode (tq0md2 to tq0md0 bi ts = 100) ............................................................. 393 8.6.6 free-running timer mode (tq0md2 to tq0md0 bi ts = 101) ................................................... 404 8.6.7 pulse width measurement mode (tq0 md2 to tq0md0 bits = 110)........................................ 426 8.7 selector function .............................................................................................................. ....431 chapter 9 16-bit interval timer m (tmm).......... ...................................................................432 9.1 overview....................................................................................................................... ..........432 9.2 configuration .................................................................................................................. .......433 9.3 register ....................................................................................................................... ...........434 9.4 operation...................................................................................................................... ..........435 9.4.1 interval ti mer m ode............................................................................................................ ...... 435 9.4.2 cauti ons ....................................................................................................................... ........... 439 chapter 10 watch timer functio ns .......................................................................................440 10.1 functions ...................................................................................................................... .........440 10.2 configuration .................................................................................................................. .......441 user?s manual u17728ej3v1ud 12 10.3 control registers .............................................................................................................. ... 443 10.4 operation...................................................................................................................... ......... 447 10.4.1 operation as watch ti mer ....................................................................................................... ..447 10.4.2 operation as in terval timer.................................................................................................... ...448 10.4.3 cauti ons....................................................................................................................... ............449 chapter 11 functions of watchdog timer 2 .. ................................................................. 450 11.1 functions...................................................................................................................... ......... 450 11.2 configuration .................................................................................................................. ...... 451 11.3 registers ...................................................................................................................... ......... 452 11.4 operation...................................................................................................................... ......... 455 chapter 12 real-time output function (rto).. ................................................................. 456 12.1 function....................................................................................................................... .......... 456 12.2 configuration .................................................................................................................. ...... 457 12.3 registers ...................................................................................................................... ......... 459 12.4 operation...................................................................................................................... ......... 461 12.5 usage ......................................................................................................................... .......... 462 12.6 cautions ....................................................................................................................... ......... 462 chapter 13 a/d converter ................................................................................................... ...... 463 13.1 overview....................................................................................................................... ......... 463 13.2 functions...................................................................................................................... ......... 463 13.3 configuration .................................................................................................................. ...... 464 13.4 registers ...................................................................................................................... ......... 467 13.5 operation...................................................................................................................... ......... 478 13.5.1 basic oper ation ................................................................................................................ ........478 13.5.2 conversion operat ion ti ming .................................................................................................... 479 13.5.3 trigger mode ................................................................................................................... ........480 13.5.4 operati on m ode ................................................................................................................. ......482 13.5.5 power-fail co mpare mode ........................................................................................................ 486 13.6 cautions ....................................................................................................................... ......... 491 13.7 how to read a/d converter characteristics table... ........................................................ 496 chapter 14 d/a converter ................................................................................................... ...... 500 14.1 functions...................................................................................................................... ......... 500 14.2 configuration .................................................................................................................. ...... 500 14.3 registers ...................................................................................................................... ......... 501 14.4 operation...................................................................................................................... ......... 503 14.4.1 operation in normal mode ....................................................................................................... 503 14.4.2 operation in real-t ime output mode ..........................................................................................503 14.4.3 cauti ons....................................................................................................................... ............504 chapter 15 asynchronous serial interface a (uarta) ............................................. 505 15.1 mode switching of uarta and other serial interf aces ................................................... 505 15.1.1 csib4 and uarta0 m ode switch ing.......................................................................................505 15.1.2 uarta2 and i 2 c00 mode swit ching .........................................................................................506 user?s manual u17728ej3v1ud 13 15.1.3 uarta1 and i 2 c02 mode swit ching ........................................................................................ 507 15.2 features....................................................................................................................... ...........508 15.3 configuration .................................................................................................................. .......509 15.4 registers ...................................................................................................................... ..........511 15.5 interrupt request signals......................... ............................................................................5 18 15.6 operation...................................................................................................................... ..........519 15.6.1 data fo rmat.................................................................................................................... .......... 519 15.6.2 sbf transmission/rec eption fo rmat.......................................................................................... 521 15.6.3 sbf trans missi on ............................................................................................................... ..... 523 15.6.4 sbf rec eptio n.................................................................................................................. ........ 524 15.6.5 uart trans missi on.............................................................................................................. .... 526 15.6.6 continuous transmi ssion proc edure ........................................................................................ 527 15.6.7 uart rec eptio n ................................................................................................................. ...... 529 15.6.8 reception errors ............................................................................................................... ....... 530 15.6.9 parity types and operat ions .................................................................................................... . 532 15.6.10 receive data noi se f ilter ...................................................................................................... .... 533 15.7 dedicated baud rate generator ................................. .........................................................534 15.8 cautions ....................................................................................................................... ..........542 chapter 16 3-wire variable-length serial i/o (csib) ....................................................543 16.1 mode switching of csib and other serial interfaces ........................................................543 16.1.1 csib4 and uarta0 m ode switch ing ...................................................................................... 543 16.1.2 csib0 and i 2 c01 mode swit ching ............................................................................................ 544 16.2 features....................................................................................................................... ...........545 16.3 configuration .................................................................................................................. .......546 16.4 registers ...................................................................................................................... ..........548 16.5 interrupt request signals......................... ............................................................................5 56 16.6 operation...................................................................................................................... ..........557 16.6.1 single transfer mode (master mode, transmi ssion m ode) ....................................................... 557 16.6.2 single transfer mode (master mode, recept ion m ode)............................................................. 559 16.6.3 single transfer mode (master mode, transmission/rec eption m ode)........................................ 561 16.6.4 single transfer mode (slave mode, transmi ssion m ode) .......................................................... 563 16.6.5 single transfer mode (slave mode, recept ion m ode) ............................................................... 565 16.6.6 single transfer mode (slave mode, transmission/rec eption m ode) .......................................... 567 16.6.7 continuous transfer mode (master mode, transmi ssion m ode) ............................................... 569 16.6.8 continuous transfer mode (master mode, recept ion m ode)..................................................... 571 16.6.9 continuous transfer mode (master m ode, transmission/re ception mode) ................................ 574 16.6.10 continuous transfer mode (slave mode, transmi ssion m ode).................................................. 578 16.6.11 continuous transfer mode (slave mode, recept ion m ode) ....................................................... 580 16.6.12 continuous transfer mode (slave m ode, transmission/re ception mode) .................................. 583 16.6.13 reception error................................................................................................................ ........ 587 16.6.14 clock ti ming ................................................................................................................... .......... 588 16.7 output pins .................................................................................................................... ........590 16.8 baud rate generator ............................................................................................................ 591 16.8.1 baud rate generatio n ........................................................................................................... .... 592 16.9 cautions ....................................................................................................................... ..........593 chapter 17 i 2 c bus......................................................................................................................... ..594 user?s manual u17728ej3v1ud 14 17.1 mode switching of i 2 c bus and other serial interfaces ..... .............................................. 594 17.1.1 uarta2 and i 2 c00 mode swit ching .........................................................................................594 17.1.2 csib0 and i 2 c01 mode swit ching ............................................................................................595 17.1.3 uarta1 and i 2 c02 mode swit ching .........................................................................................596 17.2 features....................................................................................................................... .......... 597 17.3 configuration .................................................................................................................. ...... 598 17.4 registers ...................................................................................................................... ......... 602 17.5 i 2 c bus mode functions....................................................................................................... 618 17.5.1 pin confi guratio n .............................................................................................................. ........618 17.6 i 2 c bus definitions and control methods ..................... ..................................................... 619 17.6.1 start c onditi on................................................................................................................ ..........619 17.6.2 addre sses...................................................................................................................... ..........620 17.6.3 transfer direction specific ation ............................................................................................... .621 17.6.4 ack ............................................................................................................................ .............622 17.6.5 stop condi tion ................................................................................................................. .........623 17.6.6 wait state..................................................................................................................... ............624 17.6.7 wait state cance llation me thod ................................................................................................6 26 17.7 i 2 c interrupt request signals (intiicn) ......................... ..................................................... 627 17.7.1 master devic e operat ion........................................................................................................ ...628 17.7.2 slave device operation (when receiving slave address (addr ess matc h))................................631 17.7.3 slave device operation (when re ceiving extens ion c ode) ........................................................ 635 17.7.4 operation without communica tion ............................................................................................639 17.7.5 arbitration loss operation (operation as slave after arbi tration loss) .........................................640 17.7.6 operation when arbitration loss occurs ( no communication after arbitrati on loss) ...................642 17.8 interrupt request signal (intiicn) generation ti ming and wait control....................... 649 17.9 address match detection method ... ................................................................................... 650 17.10 error detection................................................................................................................ ...... 650 17.11 extension code................................................................................................................. .... 651 17.12 arbitration .................................................................................................................... ......... 652 17.13 wakeup function................................................................................................................ .. 653 17.14 communication reservation............................................................................................... 654 17.14.1 when communication reservation function is enabled (iicfn.iicr svn bit = 0) .......................654 17.14.2 when communication reservation function is disabled (iicfn.ii crsvn bit = 1).......................658 17.15 cautions ....................................................................................................................... ......... 659 17.16 communication operations ................................................................................................ 660 17.16.1 master operation in si ngle master system ................................................................................661 17.16.2 master operation in multimaste r system ..................................................................................662 17.16.3 slave oper ation................................................................................................................ ........665 17.17 timing of data communication .......................................................................................... 668 chapter 18 iebus controller................................................................................................ ... 675 18.1 functions...................................................................................................................... ......... 675 18.1.1 communication protoc ol of i ebus............................................................................................675 18.1.2 determination of bus mast ership (arb itrati on) .......................................................................... 676 18.1.3 communicati on m ode ............................................................................................................. .676 18.1.4 communicati on addres s .......................................................................................................... 676 18.1.5 broadcast comm unicati on........................................................................................................ 677 18.1.6 transfer format of iebus....................................................................................................... ...677 user?s manual u17728ej3v1ud 15 18.1.7 transfer data .................................................................................................................. ......... 687 18.1.8 bit fo rmat ..................................................................................................................... ............ 689 18.2 configuration .................................................................................................................. .......690 18.3 registers ...................................................................................................................... ..........692 18.4 interrupt operations of iebus cont roller............................................................................722 18.4.1 interrupt cont rol bl ock ........................................................................................................ ...... 722 18.4.2 example of ident ifying in terrupt ............................................................................................... 724 18.4.3 interrupt s ource list .......................................................................................................... ........ 727 18.4.4 communication error sour ce processi ng list ............................................................................ 728 18.5 interrupt request signal generation timing and main cpu processing........................730 18.5.1 master tr ansmissi on ............................................................................................................ .... 730 18.5.2 master re ceptio n............................................................................................................... ....... 732 18.5.3 slave trans missi on ............................................................................................................. ..... 734 18.5.4 slave rec eptio n................................................................................................................ ........ 736 18.5.5 interval of occurrence of interrupt request signal for iebus cont rol ......................................... 738 chapter 19 can controller ......................................... ......................................................... ....742 19.1 overview....................................................................................................................... ..........742 19.1.1 featur es ....................................................................................................................... ........... 742 19.1.2 overview of func tions .......................................................................................................... .... 743 19.1.3 configur ation .................................................................................................................. ......... 744 19.2 can protocol ................................................................................................................... ......745 19.2.1 frame fo rmat ................................................................................................................... ........ 745 19.2.2 frame types .................................................................................................................... ........ 746 19.2.3 data frame and re mote frame.................................................................................................. 74 6 19.2.4 error fr ame .................................................................................................................... .......... 754 19.2.5 overload frame................................................................................................................. ....... 755 19.3 functions ...................................................................................................................... .........756 19.3.1 determining bus prio rity....................................................................................................... .... 756 19.3.2 bit stu ffing................................................................................................................... ............. 756 19.3.3 multi ma sters .................................................................................................................. ......... 756 19.3.4 multi cast ..................................................................................................................... ............ 756 19.3.5 can sleep mode/can st op mode func tion .............................................................................. 757 19.3.6 error contro l func tion ......................................................................................................... ...... 757 19.3.7 baud rate cont rol func tion..................................................................................................... ... 762 19.4 connection with target system ................................. .........................................................766 19.5 internal registers of can controller ..................................................................................767 19.5.1 can controller c onfigurat ion................................................................................................... . 767 19.5.2 register a ccess ty pe ........................................................................................................... .... 768 19.5.3 register bit c onfigurat ion ..................................................................................................... .... 785 19.6 registers ...................................................................................................................... ..........789 19.7 bit set/clear function......................................................................................................... ..824 19.8 can controller initialization . ...............................................................................................82 6 19.8.1 initialization of can m odule................................................................................................... .. 826 19.8.2 initialization of message buffer ............................................................................................... . 826 19.8.3 redefinition of message bu ffer ................................................................................................ 8 26 19.8.4 transition from initializati on mode to operat ion m ode.............................................................. 827 19.8.5 resetting error counter c0 erc of can module ...................................................................... 828 user?s manual u17728ej3v1ud 16 19.9 message reception .............................................................................................................. 829 19.9.1 message rec eptio n .............................................................................................................. ....829 19.9.2 reading recept ion dat a......................................................................................................... ...830 19.9.3 receive history list func tion .................................................................................................. ...831 19.9.4 mask func tion.................................................................................................................. .........833 19.9.5 multi buffer receiv e block f uncti on............................................................................................ 835 19.9.6 remote frame recept ion ......................................................................................................... .836 19.10 message transmission ........................................................................................................ 837 19.10.1 message trans missi on ........................................................................................................... ..837 19.10.2 transmit history list func tion ................................................................................................. ...839 19.10.3 automatic block tr ansmission ( abt) ........................................................................................841 19.10.4 transmission abor t proc ess..................................................................................................... 842 19.10.5 remote frame transmissi on .....................................................................................................8 43 19.11 power saving modes............................................................................................................ 8 44 19.11.1 can sleep mode................................................................................................................. .....844 19.11.2 can stop mode .................................................................................................................. .....846 19.11.3 example of using pow er saving modes ....................................................................................847 19.12 interrupt function............................................................................................................. .... 848 19.13 diagnosis functions and special operational mode s ..................................................... 849 19.13.1 receive-onl y m ode .............................................................................................................. ....849 19.13.2 single-shot mode............................................................................................................... ......850 19.13.3 self-tes t mode................................................................................................................. .........851 19.13.4 transmission/reception operati on in each operat ion m ode...................................................... 852 19.14 time stamp function ........................................................................................................... 8 53 19.14.1 time stamp functi on ............................................................................................................ ....853 19.15 baud rate settings............................................................................................................. .. 855 19.15.1 bit rate setti ng condi tions.................................................................................................... .....855 19.15.2 representative examples of baud rate settings .......................................................................859 19.16 operation of can contro ller ............................................................................................... 863 chapter 20 dma function (dma controller) ..... .............................................................. 888 20.1 features....................................................................................................................... .......... 888 20.2 configuration .................................................................................................................. ...... 889 20.3 registers ...................................................................................................................... ......... 890 20.4 transfer targets ............................................................................................................... .... 898 20.5 transfer modes ................................................................................................................. .... 898 20.6 transfer types ................................................................................................................. ..... 899 20.7 dma channel priorities........................................................................................................ 9 00 20.8 time related to dma transfer ............................................................................................ 900 20.9 dma transfer start fact ors................................................................................................. 901 20.10 dma abort factors.............................................................................................................. . 902 20.11 end of dma transfer............................................................................................................ 902 20.12 operation timing ............................................................................................................... ... 902 20.13 cautions ....................................................................................................................... ......... 907 chapter 21 crc function .................................................................................................... ........ 912 21.1 functions...................................................................................................................... ......... 912 21.2 configuration .................................................................................................................. ...... 912 user?s manual u17728ej3v1ud 17 21.3 registers ...................................................................................................................... ..........913 21.4 operation...................................................................................................................... ..........914 21.5 usage ......................................................................................................................... ..........915 chapter 22 interrupt/exception processing fu nction ...............................................917 22.1 features....................................................................................................................... ...........917 22.2 non-maskable interrupts .......................... ............................................................................92 1 22.2.1 operat ion...................................................................................................................... ........... 923 22.2.2 restore........................................................................................................................ ............ 924 22.2.3 np fl ag........................................................................................................................ ............. 925 22.3 maskable interrupts ............................................................................................................ ..926 22.3.1 operat ion...................................................................................................................... ........... 926 22.3.2 restore........................................................................................................................ ............ 928 22.3.3 priorities of ma skable inte rrupts .............................................................................................. 929 22.3.4 interrupt control r egister ( xxicn) ............................................................................................. . 933 22.3.5 interrupt mask registers 0 to 3 (imr0 to imr3 )........................................................................ 936 22.3.6 in-service priority register (ispr)............................................................................................ . 938 22.3.7 id flag ........................................................................................................................ .............. 939 22.3.8 watchdog timer mode regi ster 2 (w dtm2) ............................................................................. 939 22.4 software exception ............................................................................................................. ..940 22.4.1 operat ion...................................................................................................................... ........... 940 22.4.2 restore........................................................................................................................ ............ 941 22.4.3 ep fl ag........................................................................................................................ ............. 942 22.5 exception trap ................................................................................................................. .....943 22.5.1 illegal opcode definit ion ...................................................................................................... ..... 943 22.5.2 debug tr ap..................................................................................................................... .......... 945 22.6 external interrupt request input pins (nmi and intp0 to intp7) ....................................947 22.6.1 noise elim inatio n .............................................................................................................. ....... 947 22.6.2 edge detec tion................................................................................................................. ........ 947 22.7 interrupt acknowledge time of cpu ...................................................................................952 22.8 periods in which interrupts are not acknowledged by cpu...........................................954 22.9 cautions ....................................................................................................................... ..........954 chapter 23 key interrupt function ......................... .............................................................955 23.1 function ....................................................................................................................... ..........955 23.2 register ....................................................................................................................... ...........956 23.3 cautions ....................................................................................................................... ..........956 chapter 24 standby function...................................... .......................................................... ...957 24.1 overview....................................................................................................................... ..........957 24.2 registers ...................................................................................................................... ..........959 24.3 halt mode...................................................................................................................... .......962 24.3.1 setting and operat ion st atus ................................................................................................... . 962 24.3.2 releasing ha lt m ode ............................................................................................................ 962 24.4 idle1 mode ..................................................................................................................... .......964 24.4.1 setting and operat ion st atus ................................................................................................... . 964 24.4.2 releasing id le1 m ode........................................................................................................... . 964 user?s manual u17728ej3v1ud 18 24.5 idle2 mode ..................................................................................................................... ...... 966 24.5.1 setting and operat ion st atus ................................................................................................... .966 24.5.2 releasing id le2 m ode ........................................................................................................... .966 24.5.3 securing setup time when releasing id le2 m ode ................................................................... 968 24.6 stop mode...................................................................................................................... ...... 969 24.6.1 setting and operat ion st atus ................................................................................................... .969 24.6.2 releasing st op m ode ............................................................................................................ 969 24.6.3 securing oscillation stabilization ti me when releasi ng stop mode .........................................972 24.7 subclock operation mode ................................................................................................... 973 24.7.1 setting and operat ion st atus ................................................................................................... .973 24.7.2 releasing subclock operation mode ........................................................................................973 24.8 sub-idle mode .................................................................................................................. ... 975 24.8.1 setting and operat ion st atus ................................................................................................... .975 24.8.2 releasing sub- idle m ode .......................................................................................................9 75 chapter 25 reset functions ................................................................................................. .... 977 25.1 overview....................................................................................................................... ......... 977 25.2 registers to check reset source.................................. ..................................................... 979 25.3 operation...................................................................................................................... ......... 980 25.3.1 reset operation vi a reset pin ...............................................................................................980 25.3.2 reset operation by watc hdog timer 2 (w dt2res) ..................................................................982 25.3.3 reset operation by low-vo ltage detector (lvir es)..................................................................984 25.3.4 reset operation by clo ck monitor (c lmres) ..........................................................................985 25.3.5 operation after reset re lease .................................................................................................. .987 25.3.6 reset function operation flow.................................................................................................. .988 chapter 26 clock monitor ................................................................................................... ..... 989 26.1 functions...................................................................................................................... ......... 989 26.2 configuration .................................................................................................................. ...... 989 26.3 register ....................................................................................................................... .......... 990 26.4 operation...................................................................................................................... ......... 991 chapter 27 low-voltage detector ............................... ........................................................ 994 27.1 functions...................................................................................................................... ......... 994 27.2 configuration .................................................................................................................. ...... 994 27.3 registers ...................................................................................................................... ......... 995 27.4 operation...................................................................................................................... ......... 997 27.4.1 to use for internal re set signal (l vires) .................................................................................997 27.4.2 to use for inte rrupt (intlvi) .................................................................................................. ..998 27.5 ram retention voltage detection operation ............ ........................................................ 999 27.6 emulation function ............................................................................................................ 1 000 chapter 28 regulator ........................................................................................................ ....... 1001 28.1 outline ....................................................................................................................... .......... 1001 28.2 operation...................................................................................................................... ....... 1002 chapter 29 rom correction function................... ............................................................ 1003 user?s manual u17728ej3v1ud 19 29.1 overview....................................................................................................................... ........1003 29.2 registers ...................................................................................................................... ........1004 29.3 rom correction operation and program flow ......... .......................................................1006 29.4 cautions ....................................................................................................................... ........1008 chapter 30 flash memory.................................................................................................... .....1009 30.1 features....................................................................................................................... .........1009 30.2 memory configuration ................................. .......................................................................101 0 30.3 functional outline............................................................................................................. ..1012 30.4 rewriting by dedicated flash memory programmer .......................................................1016 30.4.1 programming env ironment .................................................................................................... 1016 30.4.2 communicati on mode ............................................................................................................ 1 017 30.4.3 flash memory cont rol ........................................................................................................... . 1023 30.4.4 selection of comm unication mode ......................................................................................... 1024 30.4.5 communication commands ................................................................................................... 1025 30.4.6 pin connec tion ................................................................................................................. ...... 1026 30.5 rewriting by self programming............... ..........................................................................1031 30.5.1 overvi ew ....................................................................................................................... ........ 1031 30.5.2 featur es ....................................................................................................................... ......... 1032 30.5.3 standard self progr amming fl ow ............................................................................................ 1033 30.5.4 flash f uncti ons ................................................................................................................ ...... 1034 30.5.5 pin proc essi ng ................................................................................................................. ...... 1034 30.5.6 internal res ources used ........................................................................................................ . 1035 chapter 31 on-chip debug function....................... .............................................................1036 31.1 features....................................................................................................................... .........1036 31.2 connection circuit example ....................................... .......................................................1037 31.3 interface signals.............................................................................................................. ....1037 31.4 register ....................................................................................................................... .........1039 31.5 operation...................................................................................................................... ........1041 31.6 rom security function.......................................................................................................104 2 31.6.1 security id.................................................................................................................... ......... 1042 31.6.2 setti ng ........................................................................................................................ ........... 1043 31.7 cautions ....................................................................................................................... ........1044 chapter 32 electrical specifications..................... ...........................................................1045 32.1 absolute maximum ratings ...............................................................................................1045 32.2 capacitance .................................................................................................................... .....1047 32.3 operating conditions..........................................................................................................1 047 32.4 oscillator characteristics........................................... ........................................................10 48 32.4.1 main clock oscillator characteri stics....................................................................................... 104 8 32.4.2 subclock oscillator c haracterist ics ....................................................................................... 1051 32.4.3 pll characte ristics ............................................................................................................ .... 1052 32.4.4 internal oscillator characteri stics............................................................................................ 1052 32.5 regulator characteristics .......................................... ........................................................1052 32.6 dc characteristics ............................................................................................................. .1053 32.6.1 i/o level ...................................................................................................................... ........... 1053 user?s manual u17728ej3v1ud 20 32.6.2 supply cu rrent................................................................................................................. .......1055 32.7 data retention characteristics . ........................................................................................ 1056 32.8 ac characteristics ............................................................................................................. 1057 32.8.1 clkout output timi ng........................................................................................................... 1058 32.8.2 bus ti ming ..................................................................................................................... .........1059 32.9 basic operation ................................................................................................................ .. 1072 32.10 flash memory programming characteristics........... ...................................................... 1081 chapter 33 package drawings .............................................................................................. 10 83 chapter 34 recommended soldering conditions. ........................................................ 1085 appendix a development tools............................................................................................. 10 87 a.1 software package ............................................................................................................... 1092 a.2 language processing software ........................................................................................ 1092 a.3 control software............................................................................................................... .. 1092 a.4 debugging tools (hardware) .......................................... .................................................. 1093 a.4.1 when using in-circuit em ulator ie-v 850es-g1 ...................................................................... 1093 a.4.2 when using iecu be qb-v850 essx2 .................................................................................. 1095 a.4.3 when using on-chip debug emul ator ie-v850e 1-cd-nw ......................................................1097 a.4.4 when using qb-v850m ini (mini cube) ................................................................................1098 a.5 debugging tools (software).............................................................................................. 1099 a.6 embedded software ........................................................................................................... 110 0 a.7 flash memory writing tools ............................................................................................. 1100 appendix b major differences between v850es/sg3 and v850es/sg2 ................. 1101 appendix c register index .................................................................................................. ..... 1103 appendix d instruction set list ........................................................................................... 1115 d.1 conventions .................................................................................................................... .... 1115 d.2 instruction set (in alphabetical order) ...................... ...................................................... 1118 appendix e list of cautions ............................................................................................... .... 1125 appendix f revision history................................................................................................ .... 1164 f.1 major revisions in this edition .................................. ...................................................... 1164 f.2 revision history of previous editions ....................... ...................................................... 1170 user?s manual u17728ej3v1ud 21 chapter 1 introduction the v850es/sg3 is one of the products in the nec electronics v850 single-chip microcontrollers designed for low- power operation for real-time control applications. 1.1 general the v850es/sg3 is a 32-bit single-chip microcontrolle r that includes the v850es cpu core and peripheral functions such as rom/ram, a timer/counter, serial interfac es, an a/d converter, and a d/a converter. some models of the v850es/sg3 are provided with iebus tm (inter equipment bus tm ) or can (controller area network) as an automotive lan. in addition to high real-time response characteristics and 1- clock-pitch basic instructio ns, the v850es/sg3 features multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo contro l applications. moreover, as a real-time control system, the v850es/sg3 enables an extremely high cost-performance fo r applications that require a low power consumption, such as audio and car audio. table 1-1 lists the products of the v850es/sg3. a model of the v850es/sg3 with expan ded i/o, timer/counter, and serial interface functions, v850es/sj3, is also available. see table 1-2 v850es/sj3 product list . chapter 1 introduction user?s manual u17728ej3v1ud 22 table 1-1. v850es/sg3 product list rom maskable interrupts function part number type size ram size operating frequency (max.) i 2 c iebus can external internal non- maskable interrupts pd70f3333 256 kb 24 kb pd70f3334 384 kb 32 kb none pd70f3335 256 kb 24 kb pd70f3336 384 kb 32 kb 1 ch pd70f3340 512 kb 40 kb pd70f3341 640 kb 48 kb pd70f3342 768 kb 60 kb pd70f3343 1024 kb 60 kb none pd70f3350 512 kb 40 kb pd70f3351 640 kb 48 kb pd70f3352 768 kb 60 kb pd70f3353 flash memory 1024 kb 60 kb 32 mhz on-chip on-chip 1 ch 8 51 2 remark the part numbers of the v850es/sg3 are shown as follows in this manual. ? can controller version pd70f3335, 70f3336, 70f3350, 70f3351, 70f3352, 70f3353 chapter 1 introduction user?s manual u17728ej3v1ud 23 table 1-2. v850es/sj3 product list rom maskable interrupts function part number type size ram size operating frequency (max.) i 2 c iebus can external internal non- maskable interrupts pd70f3344 384 kb 32 kb pd70f3345 512 kb 40 kb pd70f3346 640 kb 48 kb pd70f3347 768 kb 60 kb pd70f3348 1024 kb 60 kb none pd70f3354 384 kb 32 kb pd70f3355 512 kb 40 kb pd70f3356 640 kb 48 kb pd70f3357 768 kb 60 kb pd70f3358 1024 kb 60 kb 1 ch 64 pd70f3364 384 kb 32 kb pd70f3365 512 kb 40 kb pd70f3366 640 kb 48 kb pd70f3367 768 kb 60 kb pd70f3368 flash memory 1024 kb 60 kb 32 mhz on-chip on-chip 2 ch 9 68 2 chapter 1 introduction user?s manual u17728ej3v1ud 24 1.2 features { minimum instruction execution time: 31.25 ns (operating with main clock (f xx ) of 32 mhz) { general-purpose registers: 32 bits 32 registers { cpu features: signed multiplication (16 16 32): 1 to 2 clocks signed multiplication (32 32 64): 1 to 5 clocks saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space (for programs and data) external expansion: up to 4 mb ? internal memory: ram: 24/32/40/48/60 kb (see table 1-1 ) flash memory: 256/ 384/512/640/768/1024 kb (see table 1-1 ) ? external bus interface: separate bus/multiplexed bus output selectable 8/16 bit data bus sizing function wait function ? programmable wait function ? external wait function idle state function bus hold function { interrupts and exceptions: non-maskable interrupts: 2 sources maskable interrupts: 59 sources (see table 1-1 ) software exceptions: 32 sources exception trap: 2 sources { i/o lines: i/o ports: 84 { timer function: 16-bit interval timer m (tmm): 1 channel 16-bit timer/event counter p (tmp): 6 channels 16-bit timer/event counter q (tmq): 1 channel watch timer: 1 channel watchdog timer: 1 channel { real-time output port: 6 bits 1 channel { serial interface: asynchronous serial interface a (uarta) 3-wire variable-length serial interface b (csib) i 2 c bus interface (i 2 c) uarta/csib: 1 channel uarta/i 2 c: 2 channels csib/i 2 c: 1 channel csib: 3 channels { iebus controller: 1 channel { can controller: 1 channel (can controller version only) { a/d converter: 10-bit resolution: 12 channels { d/a converter: 8-bit resolution: 2 channels { dma controller: 4 channels { crc function: 16-bit error detection codes are generated for data in 8-bit units { on-chip debug function: jtag interface { rom correction: 4 correct ion addresses specifiable chapter 1 introduction user?s manual u17728ej3v1ud 25 { clock generator: during main clock or subclock operation 7-level cpu clock (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable { internal oscillation clock: 220 khz (typ.) { power-save functions: halt/idle1/idle2/stop/subclock/sub-idle mode { package: 100-pin plastic lqfp (fine pitch) (14 14) 1.3 application fields audio, car audio, consumer devices chapter 1 introduction user?s manual u17728ej3v1ud 26 1.4 ordering information part number package internal rom pd70f3333gc(a)-ueu-ax pd70f3333gc(a)-8ea-a pd70f3334gc(a)-ueu-ax pd70f3334gc(a)-8ea-a pd70f3335gc(a)-ueu-ax pd70f3335gc(a)-8ea-a pd70f3336gc(a)-ueu-ax pd70f3336gc(a)-8ea-a pd70f3340gc(a)-ueu-ax pd70f3340gc(a)-8ea-a pd70f3341gc(a)-ueu-ax pd70f3342gc(a)-ueu-ax pd70f3343gc(a)-ueu-ax pd70f3350gc(a)-ueu-ax pd70f3350gc(a)-8ea-a pd70f3351gc(a)-ueu-ax pd70f3352gc(a)-ueu-ax pd70f3353gc(a)-ueu-ax 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 256 kb (flash memory) 256 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 256 kb (flash memory) 256 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 512 kb (flash memory) 512 kb (flash memory) 640 kb (flash memory) 768 kb (flash memory) 1024 kb (flash memory) 512 kb (flash memory) 512 kb (flash memory) 640 kb (flash memory) 768 kb (flash memory) 1024 kb (flash memory) remark the v850es/sg3 microcontrollers are lead-free products. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications. chapter 1 introduction user?s manual u17728ej3v1ud 27 1.5 pin configuration (top view) 100-pin plastic lqfp (fine pitch) (14 14) pd70f3333gc(a)-ueu-ax pd70f3336gc(a)-ueu-ax pd70f3343gc(a)-ueu-ax pd70f3333gc(a)-8ea-a pd70f3336gc(a)-8ea-a pd70f3350gc(a)-ueu-ax pd70f3334gc(a)-ueu-ax pd70f3340gc(a)-ueu-ax pd70f3350gc(a)-8ea-a pd70f3334gc(a)-8ea-a pd70f3340gc(a)-8ea-a pd70f3351gc(a)-ueu-ax pd70f3335gc(a)-ueu-ax pd70f3341gc(a)-ueu-ax pd70f3352gc(a)-ueu-ax pd70f3335gc(a)-8ea-a pd70f3342gc(a)-ueu-ax pd70f3353gc(a)-ueu-ax chapter 1 introduction user?s manual u17728ej3v1ud 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p70/ani0 note 6 p71/ani1 note 6 p72/ani2 note 6 p73/ani3 note 6 p74/ani4 note 6 p75/ani5 note 6 p76/ani6 note 6 p77/ani7 note 6 p78/ani8 note 6 p79/ani9 note 6 p710/ani10 note 6 p711/ani11 note 6 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p31/rxda0/intp7/sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01 p34/tip10/top10 p35/tip11/top11 p36/ctxd0 note 4 /ietx0 p37/crxd0 note 4 /ierx0 ev ss ev dd p38/txda2/sda00 p39/rxda2/scl00 p50/tiq01/kr0/toq01/rtp00 p51/tiq02/kr1/toq02/rtp01 p52/tiq03/kr2/toq03/rtp02/ddi p53/sib2/kr3/tiq00/toq00/rtp03/ddo p54/sob2/kr4/rtp04/dck p55/sckb2/kr5/rtp05/dms p90/a0 note 5 /kr6/txda1/sda02 p91/a1 note 5 /kr7/rxda1/scl02 p92/a2 note 5 /tip41/top41 p93/a3 note 5 /tip40/top40 p94/a4 note 5 /tip31/top31 p95/a5 note 5 /tip30/top30 p96/a6 note 5 /tip21/top21 p97/a7 note 5 /sib1/tip20/top20 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pdh3/a19 pdh2/a18 p915/a15 note 5 /intp6/tip50/top50 p914/a14 note 5 /intp5/tip51/top51 p913/a13 note 5 /intp4 p912/a12 note 5 /sckb3 p911/a11 note 5 /sob3 p910/a10 note 5 /sib3 p99/a9 note 5 /sckb1 p98/a8 note 5 /sob1 av ref0 av ss p10/ano0 p11/ano1 av ref1 pdh4/a20 pdh5/a21 flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst note 3 p06/intp3 p40/sib0/sda01 p41/sob0/scl01 p42/sckb0 p30/txda0/sob4 notes 1. connect these pins to v ss in the normal mode. 2. connect the regc pin to v ss via a 4.7 f capacitor. 3. fix this pin to the low level from when the reset status has been released until the ocdm.ocdm0 bit is cleared (0) when the on-chip debug func tion is not used. for details, see 4.6.3 cautions on on-chip debug pins . 4. ctxd0 and crxd0 are valid only in the can controller version. 5. port 9 cannot be used as port pins or other alternat e-function pins when the a0 to a15 pins are used in the separate bus mode. 6. to use port 7 (p70/ani0 to p711/ani11) as a/d converter function pins and port i/o pins in mix, be sure to observe usage cautions (refer to 13.6 (4) alternate i/o ). chapter 1 introduction user?s manual u17728ej3v1ud 29 pin names a0 to a21: ad0 to ad15: adtrg: ani0 to ani11: ano0, ano1: ascka0: astb: av ref0 , av ref1 : av ss : bv dd : bv ss : clkout: crxd0: ctxd0: dck: ddi: ddo: dms: drst: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: ierx0: ietx0: intp0 to intp7: kr0 to kr7: nmi: p02 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p70 to p711: p90 to p915: pcm0 to pcm3: address bus address/data bus a/d trigger input analog input analog output asynchronous serial clock address strobe analog reference voltage analog v ss power supply for bus interface ground for bus interface clock output can receive data can transmit data debug clock debug data input debug data output debug mode select debug reset power supply for port ground for port flash programming mode hold acknowledge hold request iebus receive data iebus transmit data external interrupt input key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 7 port 9 port cm pct0, pct1, pct4, pct6: pdh0 to pdh5: pdl0 to pdl15: rd: regc: reset: rtp00 to rtp05: rxda0 to rxda2: sckb0 to sckb4: scl00 to scl02: sda00 to sda02: sib0 to sib4: sob0 to sob4: tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tiq00 to tiq03: top00, top01, top10, top11, top20, top21, top30, top31, top40, top41, top50, top51, toq00 to toq03: txda0 to txda2: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port ct port dh port dl read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer input timer output transmit data power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock chapter 1 introduction user?s manual u17728ej3v1ud 30 1.6 function block configuration 1.6.1 internal block diagram nmi toq00 to toq03 tiq00 to tiq03 rtp00 to rtp05 sob0/scl01 sib0/sda01 sckb0 intp0 to intp7 intc 16-bit timer/ counter q: 1 ch top00 to top50, top01 to top51 tip00 to tip50, tip01 to tip51 16-bit timer/ counter p: 6 ch kr0 to kr7 rto iebus csib1 dmac watchdog timer 2 watch timer key return function note 1 note 2 ram rom pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 a0 to a21 ad0 to ad15 ports cg regulator pll clm internal oscillator pcm0 to pcm3 pct0, pct1, pct4, pct6 pdh0 to pdh5 pdl0 to pdl15 p90 to p915 p70 to p711 p50 to p55 p40 to p42 p30 to p39 p10, p11 p02 to p06 av ref1 ano0, ano1 ani0 to ani11 av ss av ref0 adtrg clkout xt1 xt2 x1 x2 v dd v ss regc flmd0 flmd1 bv dd bv ss ev dd ev ss instruction queue bcu sob1 sib1 sckb1 csib2 sob2 sib2 sckb2 csib3 sob3 sib3 sckb3 txda0/sob4 rxda0/sib4 ascka0/sckb4 txda2/sda00 rxda2/scl00 ietx0 ierx0 csib0 i 2 c01 rom correction 16-bit interval timer m: 1 ch uarta0 csib4 uarta2 i 2 c00 txda1/sda02 rxda1/scl02 uarta1 i 2 c02 on-chip debug function drst dms ddi dck ddo a/d converter d/a converter can0 note 3 ctxd0 note 3 crxd0 note 3 reset lvi notes 1. 256/384/512/640/768/1024 kb (flash memory) (see table 1-1 ) 2. 24/32/40/48/60 kb (see table 1-1 ) 3. can controller version only chapter 1 introduction user?s manual u17728ej3v1ud 31 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable single -clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space a nd the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the pref etched instruction code is stored in an instruction queue. (3) rom this is a 1024/768/640/512/384/256 kb flash me mory mapped to addresses 0000000h to 00fffffh/0000000h to 00bffffh/0000000h to 00 9ffffh/0000000h to 0 07ffffh/0000000h to 005ffffh/0000000h to 003ffffh. it c an be accessed from the cpu in one clock during instruction fetch. (4) ram this is a 60/48/40/32/24 kb ram mapped to addresses 3ff0000h to 3ffefffh/3ff3000h to 3ffefffh/3ff5000h to 3ffefffh/3ff7000h to 3ffe fffh/3ff9000h to 3ffefffh. it can be accessed from the cpu in one clock during data access. (5) interrupt controller (intc) this controller handles hardware interrupt requests (nm i, intp0 to intp7) from on-chip peripheral hardware and external hardware. eight levels of interrupt priori ties can be specified for these interrupt requests, and multiplexed servicing control can be performed. (6) clock generator (cg) a main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (f x ) and subclock frequency (f xt ), respectively. there are two modes: in the clock-through mode, f x is used as the main clock frequency (f xx ) as is. in the pll mode, f x is used multiplied by 4 or 8. the cpu clock frequency (f cpu ) can be selected from among f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt . (7) internal oscillator an internal oscillator is provided on chip. the oscillation frequency is 220 khz (typ). the internal oscillator supplies the clock for watchdog timer 2 and timer m. (8) timer/counter six-channel 16-bit timer/event c ounter p (tmp), one-channel 16-bit timer/event counter q (tmq), and one- channel 16-bit interval timer m (tmm), are provided on chip. (9) watch timer this timer counts the reference time period (0.5 s) for counting the clock (the 32.768 khz subclock or the 32.768 khz clock f brg from prescaler 3). the watch timer can also be used as an interval timer for the main clock. chapter 1 introduction user?s manual u17728ej3v1ud 32 (10) watchdog timer 2 a watchdog timer is provided on chip to detect inadv ertent program loops, system abnormalities, etc. either the internal oscillation clock, the main clock, or the subclock can be selected as the source clock. watchdog timer 2 generates a non-maskable interrupt request signal (intwdt2) or a system reset signal (wdt2res) after an overflow occurs. (11) serial interface the v850es/sg3 includes three kinds of serial interfac es: asynchronous serial interface a (uarta), 3-wire variable-length serial interface b (csib), and an i 2 c bus interface (i 2 c). in the case of uarta, data is transferred via the txda0 to txda2 pins and rxda0 to rxda2 pins. in the case of csib, data is transferred via the sob0 to sob4 pins, sib0 to sib4 pins, and sckb0 to sckb4 pins. in the case of i 2 c, data is transferred via the sda00 to sda02 and scl00 to scl02 pins. (12) iebus controller the iebus controller is a small-scale digital data transmission system for transferring data between units. (13) can controller the can controller is a small-scale digital data transmission system for transferring data between units. the can controller is provided only in can controller versions (see table 1-1 ). (14) a/d converter this 10-bit a/d converter includes 12 analog input pins. conversion is performed using the successive approximation method. (15) d/a converter a two-channel, 8-bit-resolution d/a converter that uses the r-2r ladder method is provided on chip. (16) dma controller a 4-channel dma controller is provided on chip. this controller transfers data between the internal ram and on-chip peripheral i/o devices in resp onse to interrupt requests sent by on-chip peripheral i/o. (17) rom correction a rom correction function that replaces part of a progra m in the internal rom with a program in the internal ram is provided. up to four correction addresses can be specified. (18) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the key input pins (8 channels). (19) real-time output function the real-time output function transfe rs preset 6-bit data to output la tches upon the occurrence of a timer compare register match signal. chapter 1 introduction user?s manual u17728ej3v1ud 33 (20) crc function a crc operation circuit that generates 16-bit crc (cyclic redundancy check) code upon setting of 8-bit data is provided on chip. (21) on-chip debug function an on-chip debug function via an on-chip debug emulator that uses the jtag (joint test action group) communication specifications is provided. swit ching between the normal port function and on-chip debugging function is done with the control pin input le vel and the on-chip debug mode register (ocdm). (22) ports the following general-purpose port functions and control pin functions are available. port i/o alternate function p0 5-bit i/o nmi, external interrupt, a/d converter trigger, debug reset p1 2-bit i/o d/a converter analog output p3 10-bit i/o external interrupt, serial interface, timer i/o, can data i/o, iebus data i/o p4 3-bit i/o serial interface p5 6-bit i/o timer i/o, real-time output, key in terrupt input, serial interface, debug i/o p7 12-bit i/o a/d converter analog input p9 16-bit i/o external address bus, serial interface, key interrupt input, timer i/o, external interrupt pcm 4-bit i/o external control signal pct 4-bit i/o external control signal pdh 6-bit i/o external address bus pdl 16-bit i/o external address/data bus user?s manual u17728ej3v1ud 34 chapter 2 pin functions 2.1 list of pin functions the names and functions of the pins in the v850es/sg3 are described below. there are four types of pin i/o buffer power supplies: av ref0 , av ref1 , bv dd , and ev dd . the relationship between these power supplies and the pins is described below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref0 port 7 av ref1 port 1 bv dd ports cm, ct, dh (bits 0 to 3), dl ev dd reset, ports 0, 3 to 5, 9, dh (bits 4, 5) (1) port pins (1/3) pin name pin no. i/o function alternate function p02 17 nmi p03 18 intp0/adtrg p04 19 intp1 p05 note 1 20 intp2/drst p06 21 i/o port 0 5-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. intp3 p10 3 ano0 p11 4 i/o port 1 2-bit i/o port input/output can be specified in 1-bit units. ano1 p30 25 txda0/sob4 p31 26 rxda0/intp7/sib4 p32 27 ascka0/sckb4/tip00/top00 p33 28 tip01/top01 p34 29 tip10/top10 p35 30 tip11/top11 p36 31 ctxd0 note 2 /ietx0 p37 32 crxd0 note 2 /ierx0 p38 35 txda2/sda00 p39 36 i/o port 3 10-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. rxda2/scl00 notes 1. fix this pin to low level from when the reset status has been released until the ocdm.ocdm0 bit is cleared to 0 when the on-chip debug function is not used. for details, see 4.6.3 cautions on on-chip debug pins . in addition, this pin incorporates a pull-down re sistor and it can be disconnected by clearing the ocdm.ocdm0 bit to 0. 2. can controller versions only chapter 2 pin functions user?s manual u17728ej3v1ud 35 (2/3) pin name pin no. i/o function alternate function p40 22 sib0/sda01 p41 23 sob0/scl01 p42 24 i/o port 4 3-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. sckb0 p50 37 tiq01/kr0/toq01/rtp00 p51 38 tiq02/kr1/toq02/rtp01 p52 39 tiq03/kr2/toq03/rtp02/ ddi p53 40 sib2/kr3/tiq00/toq00/rtp03/ ddo p54 41 sob2/kr4/rtp04/dck p55 42 i/o port 5 6-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. sckb2/kr5/rtp05/dms p70 100 ani0 p71 99 ani1 p72 98 ani2 p73 97 ani3 p74 96 ani4 p75 95 ani5 p76 94 ani6 p77 93 ani7 p78 92 ani8 p79 91 ani9 p710 90 ani10 p711 89 i/o port 7 12-bit i/o port input/output can be specified in 1-bit units. ani11 p90 43 a0/kr6/txda1/sda02 p91 44 a1/kr7/rxda1/scl02 p92 45 a2/tip41/top41 p93 46 a3/tip40/top40 p94 47 a4/tip31/top31 p95 48 a5/tip30/top30 p96 49 a6/tip21/top21 p97 50 a7/sib1/tip20/top20 p98 51 a8/sob1 p99 52 a9/sckb1 p910 53 a10/sib3 p911 54 a11/sob3 p912 55 a12/sckb3 p913 56 a13/intp4 p914 57 a14/intp5/tip51/top51 p915 58 i/o port 9 16-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. a15/intp6/tip50/top50 chapter 2 pin functions user?s manual u17728ej3v1ud 36 (3/3) pin name pin no. i/o function alternate function pcm0 61 wait pcm1 62 clkout pcm2 63 hldak pcm3 64 i/o port cm 4-bit i/o port input/output can be specified in 1-bit units. hldrq pct0 65 wr0 pct1 66 wr1 pct4 67 rd pct6 68 i/o port ct 4-bit i/o port input/output can be specified in 1-bit units. astb pdh0 87 a16 pdh1 88 a17 pdh2 59 a18 pdh3 60 a19 pdh4 6 a20 pdh5 7 i/o port dh 6-bit i/o port input/output can be specified in 1-bit units. a21 pdl0 71 ad0 pdl1 72 ad1 pdl2 73 ad2 pdl3 74 ad3 pdl4 75 ad4 pdl5 76 ad5/flmd1 pdl6 77 ad6 pdl7 78 ad7 pdl8 79 ad8 pdl9 80 ad9 pdl10 81 ad10 pdl11 82 ad11 pdl12 83 ad12 pdl13 84 ad13 pdl14 85 ad14 pdl15 86 i/o port dl 16-bit i/o port input/output can be specified in 1-bit units. ad15 chapter 2 pin functions user?s manual u17728ej3v1ud 37 (2) non-port pins (1/6) pin name pin no. i/o function alternate function a0 43 p90/kr6/txda1/sda02 a1 44 p91/kr7/rxda1/scl02 a2 45 p92/tip41/top41 a3 46 p93/tip40/top40 a4 47 p94/tip31/top31 a5 48 p95/tip30/top30 a6 49 p96/tip21/top21 a7 50 p97/sib1/tip20/top20 a8 51 p98/sob1 a9 52 p99/sckb1 a10 53 p910/sib3 a11 54 p911/sob3 a12 55 p912/sckb3 a13 56 p913/intp4 a14 57 p914/intp5/tip51/top51 a15 58 output address bus for external memory (when using separate bus) port 9 cannot be used as port pins or other alternate- function pins when the a0 to a15 pins are used in the separate bus mode. n-ch open-drain output selectable. 5 v tolerant. p915/intp6/tip50/top50 a16 87 pdh0 a17 88 pdh1 a18 59 pdh2 a19 60 pdh3 a20 6 pdh4 a21 7 output address bus for external memory pdh5 ad0 71 pdl0 ad1 72 pdl1 ad2 73 pdl2 ad3 74 pdl3 ad4 75 pdl4 ad5 76 pdl5/flmd1 ad6 77 pdl6 ad7 78 pdl7 ad8 79 pdl8 ad9 80 pdl9 ad10 81 pdl10 ad11 82 pdl11 ad12 83 pdl12 ad13 84 pdl13 ad14 85 pdl14 ad15 86 i/o address bus/data bus for external memory pdl15 chapter 2 pin functions user?s manual u17728ej3v1ud 38 (2/6) pin name pin no. i/o function alternate function adtrg 18 input a/d converter external trigger input. 5 v tolerant. p03/intp0 ani0 100 p70 ani1 99 p71 ani2 98 p72 ani3 97 p73 ani4 96 p74 ani5 95 p75 ani6 94 p76 ani7 93 p77 ani8 92 p78 ani9 91 p79 ani10 90 p710 ani11 89 input analog voltage input for a/d converter p711 ano0 3 p10 ano1 4 output analog voltage output for d/a converter p11 ascka0 27 input uarta0 baud rate clock input. 5 v tolerant. p32/sckb4/tip00/top00 astb 68 output address strobe signal output for external memory pct6 av ref0 1 reference voltage input for a/d converter/positive power supply for port 7 ? av ref1 5 ? reference voltage input for d/a converter/positive power supply for port 1 ? av ss 2 ? ground potential for a/d and d/a converters (same potential as v ss ) ? bv dd 70 ? positive power supply pin for bus interface and alternate- function ports ? bv ss 69 ? ground potential for bus interface and alternate-function ports ? clkout 62 output internal system clock output pcm1 crxd0 note 1 32 input can receive data input. 5 v tolerant. p37/ierx0 ctxd0 note 1 31 output can transmit data output. n-ch open-drain output selectable. 5 v tolerant. p36/ietx0 dck 41 input debug clock input. 5 v tolerant. p54/sob2/kr4/rtp04 ddi 39 input debug data input. 5 v tolerant. p52/tiq03/kr2/toq03/rtp02 ddo note 2 40 output debug data output. n-ch open-drain output selectable. 5 v tolerant. p53/sib2/kr3/tiq00/toq00/ rtp03 dms 42 input debug mode select input. 5 v tolerant. p55/sckb2/kr5/rtp05 drst 20 input debug reset input. 5 v tolerant. p05/intp2 ev dd 34 ? positive power supply for external (same potential as v dd ) ? ev ss 33 ? ground potential for external (same potential as v ss ) ? flmd0 8 ? flmd1 76 input flash memory programming mode setting pin pdl5/ad5 notes 1. can controller versions only 2. in the on-chip debug mode, high-level output is forcibly set. chapter 2 pin functions user?s manual u17728ej3v1ud 39 (3/6) pin name pin no. i/o function alternate function hldak 63 output bus hold acknowledge output pcm2 hldrq 64 input bus hold request input pcm3 ierx0 32 input iebus receive data input. 5 v tolerant. p37/crxd0 note 1 ietx0 31 output iebus transmit data output. n-ch open-drain output selectable. 5 v tolerant. p36/ctxd0 note 1 intp0 18 p03/adtrg intp1 19 p04 intp2 20 p05/drst intp3 21 p06 intp4 56 p913/a13 intp5 57 p914/a14/tip51/top51 intp6 58 p915/a15/tip50/top50 intp7 26 input external interrupt request input (maskable, analog noise elimination). analog noise elimination or digital noise elimination selectable for intp3 pin. 5 v tolerant. p31/rxda0/sib4 kr0 note 2 37 p50/tiq01/toq01/rtp00 kr1 note 2 38 p51/tiq02/toq02/rtp01 kr2 note 2 39 p52/tiq03/toq03/ rtp02/ddi kr3 note 2 40 p53/sib2/tiq00/toq00/ rtp03/ddo kr4 note 2 41 p54/sob2/rtp04/dck kr5 note 2 42 p55/sckb2/rtp05/dms kr6 note 2 43 p90/a0/txda1/sda02 kr7 note 2 44 input key interrupt input (on-chip analog noise eliminator). 5 v tolerant. p91/a1/rxda1/scl02 nmi note 3 17 input external interrupt input (non-maskable, analog noise elimination). 5 v tolerant. p02 rd 67 output read strobe signal output for external memory pct4 regc 10 ? connection of regulator output stabilization capacitance (4.7 f) ? reset 14 input system reset input ? rtp00 37 p50/tiq01/kr0/toq01 rtp01 38 p51/tiq02/kr1/toq02 rtp02 39 p52/tiq03/kr2/toq03/ddi rtp03 40 p53/sib2/kr3/tiq00/toq00/ ddo rtp04 41 p54/sob2/kr4/dck rtp05 42 output real-time output port. n-ch open-drain output selectable. 5 v tolerant. p55/sckb2/kr5/dms notes 1. can controller versions only 2. pull this pin up externally. 3. the nmi pin alternately functions as the p02 pin. it f unctions as the p02 pin after reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1. the initial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge using intf0 and intr0 registers. chapter 2 pin functions user?s manual u17728ej3v1ud 40 (4/6) pin name pin no. i/o function alternate function rxda0 26 p31/intp7/sib4 rxda1 44 p91/a1/kr7/scl02 rxda2 36 input serial receive data input (uarta0 to uarta2) 5 v tolerant. p39/scl00 sckb0 24 p42 sckb1 52 p99/a9 sckb2 42 p55/kr5/rtp05/dms sckb3 55 p912/a12 sckb4 27 i/o serial clock i/o (csib0 to csib4) n-ch open-drain output selectable. 5 v tolerant. p32/ascka0/tip00/top00 scl00 36 p39/rxda2 scl01 23 p41/sob0 scl02 44 i/o serial clock i/o (i 2 c00 to i 2 c02) n-ch open-drain output selectable. 5 v tolerant. p91/a1/kr7/rxda1 sda00 35 p38/txda2 sda01 22 p40/sib0 sda02 43 i/o serial transmit/receive data i/o (i 2 c00 to i 2 c02) n-ch open-drain output selectable. 5 v tolerant. p90/a0/kr6/txda1 sib0 22 p40/sda01 sib1 50 p97/a7/tip20/top20 sib2 40 p53/kr3/tiq00/toq00/ rtp03/ddo sib3 53 p910/a10 sib4 26 input serial receive data input (csib0 to csib4) 5 v tolerant. p31/rxda0/intp7 sob0 23 p41/scl01 sob1 51 p98/a8 sob2 41 p54/kr4/rtp04/dck sob3 54 p911/a11 sob4 25 output serial transmit data output (csib0 to csib4) n-ch open-drain output selectable. 5 v tolerant. p30/txda0 tip00 27 external event count input/capture trigger input/external trigger input (tmp0). 5 v tolerant. p32/ascka0/sckb4/top00 tip01 28 capture trigger input (tmp0). 5 v tolerant. p33/top01 tip10 29 external event count input/capture trigger input/external trigger input (tmp1). 5 v tolerant. p34/top10 tip11 30 capture trigger input (tmp1). 5 v tolerant. p35/top11 tip20 50 external event count input/capture trigger input/external trigger input (tmp2). 5 v tolerant. p97/a7/sib1/top20 tip21 49 input capture trigger input (tmp2). 5 v tolerant. p96/a6/top21 chapter 2 pin functions user?s manual u17728ej3v1ud 41 (5/6) pin name pin no. i/o function alternate function tip30 48 external event count input/capture trigger input/external trigger input (tmp3). 5 v tolerant. p95/a5/top30 tip31 47 capture trigger input (tmp3). 5 v tolerant. p94/a4/top31 tip40 46 external event count input/capture trigger input/external trigger input (tmp4). 5 v tolerant. p93/a3/top40 tip41 45 capture trigger input (tmp4). 5 v tolerant. p92/a2/top41 tip50 58 external event count input/capture trigger input/external trigger input (tmp5). 5 v tolerant. p915/a15/intp6/top50 tip51 57 input capture trigger input (tmp5). 5 v tolerant. p914/a14/intp5/top51 tiq00 40 external event count input/capture trigger input/external trigger input (tmq0). 5 v tolerant. p53/sib2/kr3/toq00/rtp03 /ddo tiq01 37 p50/kr0/toq01/rtp00 tiq02 38 p51/kr1/toq02/rtp01 tiq03 39 input capture trigger input (tmq0). 5 v tolerant. p52/kr2/toq03/rtp02/ ddi top00 27 p32/ascka0/sckb4/tip00 top01 28 timer output (tmp0) n-ch open-drain output selectable. 5 v tolerant. p33/tip01 top10 29 p34/tip10 top11 30 timer output (tmp1) n-ch open-drain output selectable. 5 v tolerant. p35/tip11 top20 50 p97/a7/sib1/tip20 top21 49 timer output (tmp2) n-ch open-drain output selectable. 5 v tolerant. p96/a6/tip21 top30 48 p95/a5/tip30 top31 47 timer output (tmp3) n-ch open-drain output selectable. 5 v tolerant. p94/a4/tip31 top40 46 p93/a3/tip40 top41 45 timer output (tmp4) n-ch open-drain output selectable. 5 v tolerant. p92/a2/tip41 top50 58 p915/a15/intp6/tip50 top51 57 output timer output (tmp5) n-ch open-drain output selectable. 5 v tolerant. p914/a14/intp5/tip51 toq00 40 p53/sib2/kr3/tiq00/rtp03/ ddo toq01 37 p50/tiq01/kr0/rtp00 toq02 38 p51/tiq02/kr1/rtp01 toq03 39 output timer output (tmq0) n-ch open-drain output selectable. 5 v tolerant. p52/tiq03/kr2/rtp02/ddi txda0 25 p30/sob4 txda1 43 p90/a0/kr6/sda02 txda2 35 output serial transmit data output (uarta0 to uarta2) n-ch open-drain output selectable. 5 v tolerant. p38/sda00 v dd 9 ? positive power supply pin for internal ? v ss 11 ? ground potential for internal ? chapter 2 pin functions user?s manual u17728ej3v1ud 42 (6/6) pin name pin no. i/o function alternate function wait 61 input external wait input pcm0 wr0 65 write strobe for external memory (lower 8 bits) pct0 wr1 66 output write strove for external memory (higher 8 bits) pct1 x1 12 input ? x2 13 ? connection of resonator for main clock ? xt1 15 input ? xt2 16 ? connection of resonator for subclock ? chapter 2 pin functions user?s manual u17728ej3v1ud 43 2.2 pin states the operation states of pins in the various modes are described below. table 2-2. pin operation states in various modes pin name during reset (immediately after power is turned on) during reset (except immediately after power is turned on) halt mode note 2 idle1, idle2, sub-idle mode note 2 stop mode note 2 idle state note 3 bus hold p05/drst pulled down pulled down note 4 held held held held held p10/ano0, p11/ano1 hi-z hi-z held held note 10 held held p53/ddo undefined note 1 hi-z note 5 held held held held held ad0 to ad15 notes 7, 8 a0 to a15 undefined notes 7, 9 a16 to a21 undefined note 7 hi-z hi-z held hi-z wait ? ? ? ? ? clkout operating l l operating operating wr0, wr1 rd astb h note 7 hi-z hldak h h h l hldrq hi-z note 6 hi-z note 6 operating notes 7 ? ? ? operating other port pins hi-z hi-z held held held held held notes 1. these pins may momentarily output an un defined level upon power application. 2. operates while an alternate function is operating. 3. in separate bus mode, the state of the pins in the idle state inserted after the t2 state is shown. in multiplexed bus mode, the state of the pins in the idle state inserted after the t3 state is shown. 4. pulled down during external reset. during internal reset by the watchdog timer, clock monitor, etc., the state of this pin differs according to the ocdm.ocdm0 bit setting. 5. ddo output is specified in the on-chip debug mode. 6. the bus control pins function alternately as port pins, so they are initialized to the input mode (port mode). 7. operates even in the halt mode, during dma operation. 8. in separate bus mode: hi-z in multiplexed bus mode: undefined 9. in separate bus mode 10. in port mode: held when alternate function is used: hi-z remark hi-z: high impedance held: the state during the immediately preceding external bus cycle is held. l: low-level output h: high-level output ? : input without sampling (not acknowledged) chapter 2 pin functions user?s manual u17728ej3v1ud 44 2.3 pin i/o circuit types, i/o buffer power supplies, and connection of unused pins (1/3) pin alternate function pin no. i/o circuit type recommended connection p02 nmi 17 p03 intp0/adtrg 18 p04 intp1 19 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p05 intp2/drst 20 10-n input: independently connect to ev ss via a resistor. fixing to v dd level is prohibited. output: leave open. internally pull-down after reset by reset pin. p06 intp3 21 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p10, p11 ano0, ano1 3, 4 12-d input: independently connect to av ref1 or av ss via a resistor. output: leave open. p30 txda0/sob4 25 10-g p31 rxda0/intp7/sib4 26 p32 ascka0/sckb4/tip00 27 p33 tip01/top01 28 p34 tip10/top10 29 p35 tip11/top11 30 10-d p36 ctxd0 note /ietx0 31 10-g p37 crxd0 note /ierx0 32 p38 txda2/sda00 35 p39 rxda2/scl00 36 p40 sib0/sda01 22 p41 sob0/scl01 23 p42 sckb0 24 p50 tiq01/kr0/toq01/rtp00 37 p51 tiq02/kr1/toq02/rtp01 38 p52 tiq03/kr2/toq03/rtp02/ddi 39 p53 sib2/kr3/tiq00/toq00/rtp03/ ddo 40 p54 sob2/kr4/rtp04/dck 41 p55 sckb2/kr5/rtp05/dms 42 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. note can controller versions only chapter 2 pin functions user?s manual u17728ej3v1ud 45 (2/3) pin alternate function pin no. i/o circuit type recommended connection p70 to p711 ani0 to ani11 100-89 11-g input: independently connect to av ref0 or av ss via a resistor. output: leave open. p90 a0/kr6/txda1/sda02 43 p91 a1/kr7/rxda1/scl02 44 p92 a2/tip41/top41 45 p93 a3/tip40/top40 46 p94 a4/tip31/top31 47 p95 a5/tip30/top30 48 p96 a6/tip21/top21 49 p97 a7/sib1/tip20/top20 50 10-d p98 a8/sob1 51 10-g p99 a9/sckb1 52 p910 a10/sib3 53 10-d p911 a11/sob3 54 10-g p912 a12/sckb3 55 p913 a13/intp4 56 p914 a14/intp5/tip51/top51 57 p915 a15/intp6/tip50/top50 58 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. pcm0 wait 61 pcm1 clkout 62 pcm2 hldak 63 pcm3 hldrq 64 pct0, pct1 wr0, wr1 65, 66 pct4 rd 67 pct6 astb 68 pdh0 to pdh3 a16 to a19 87, 88, 59, 60 input: independently connect to bv dd or bv ss via a resistor. output: leave open. pdh4, pdh5 a20, a21 6, 7 input: independently connect to ev dd or ev ss via a resistor. output: leave open. pdl0 to pdl4 ad0 to ad4 71-75 pdl5 ad5/flmd1 76 pdl6 to pdl15 ad6 to ad15 77-86 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. chapter 2 pin functions user?s manual u17728ej3v1ud 46 (3/3) pin alternate function pin no. i/o circuit type recommended connection av ref0 ? 1 ? directly connect to v dd and always supply power. av ref1 ? 5 ? directly connect to v dd and always supply power. av ss ? 2 ? directly connect to v ss and always supply power. bv dd ? 70 ? directly connect to v dd and always supply power. bv ss ? 69 ? directly connect to v ss and always supply power. ev dd ? 34 ? ? ev ss ? 33 ? ? flmd0 ? 8 ? directly connect to v ss in a mode other than the flash memory programming mode. regc ? 10 ? connect regulator output stabilization capacitance (4.7 f). reset ? 14 2 ? v dd ? 9 ? ? v ss ? 11 ? ? x1 ? 12 ? ? x2 ? 13 ? ? xt1 ? 15 16 connect to v ss . xt2 ? 16 16 leave open. chapter 2 pin functions user?s manual u17728ej3v1ud 47 figure 2-1. pin i/o circuits in data output disable p-ch in/out ev dd /bv dd ev ss /bv ss n-ch in/out input enable data output disable ev dd ev ss p-ch in/out n-ch open drain input enable data output disable av ref0 p-ch in/out n-ch p-ch n-ch av ref0 input enable + _ av ss av ss data output disable input enable av ref1 p-ch in/out n-ch p-ch n-ch av ss data output disable ev dd ev ss p-ch in/out n-ch open drain input enable n-ch p-ch feedback cut-off xt1 xt2 data output disable ev dd ev ss p-ch in/out n-ch open drain input enable type 2 schmitt-triggered input with hysteresis characteristics type 5 type 10-n type 11-g type 12-d type 10-d type 16 type 10-g analog output voltage (threshold voltage) note note ocdm0 bit note hysteresis characteristics are not available in port mode. chapter 2 pin functions user?s manual u17728ej3v1ud 48 2.4 cautions (1) cautions on power application when the power is turned on, the following pins may momentarily output an undefined level. ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin user?s manual u17728ej3v1ud 49 chapter 3 cpu function the cpu of the v850es/sg3 is based on ri sc architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 features minimum instruction execution time: 31.25 ns (with main clock (f xx ) = 32 mhz operation) 30.5 s (with subclock (f xt ) = 32.768 khz operation) memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear general-purpose registers: 32 bits 32 registers internal 32-bit architecture 5-stage pipeline control multiplication/division instruction saturation operation instruction 32-bit shift instruction: 1 clock load/store instruction with long/short format four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 chapter 3 cpu function user?s manual u17728ej3v1ud 50 3.2 cpu register set the registers of the v850es/sg3 can be classified into two types: general-purpose program registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register) chapter 3 cpu function user?s manual u17728ej3v1ud 51 3.2.1 program register set the program registers include general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used to store a data variable or an address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the sld and sst instructions as a base pointer when these in structions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. when using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time os. if the real-time os does not use r2, it can be used as a register for variables. table 3-1. program registers name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as work ing register to create 32-bit immediate data r2 register for address/data variable (if real-time os does not use r2) r3 stack pointer used to create a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as register that i ndicates the beginning of a text area (area where program codes are located) r6 to r29 register for address/data variable r30 element pointer used as base pointer to access memory r31 link pointer used when t he compiler calls a function pc program counter holds the instruction address during program execution remark for further details on the r1, r3 to r5, and r31 that are used in the assembler and c compiler, refer to the ca850 (c compiler package) assembly language user?s manual . (2) program counter (pc) the program counter holds the instructio n address during program execution. the lower 32 bits of this register are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to 26 is ignored even if it occurs. bit 0 is fixed to 0. this means that execution cannot branch to an odd address. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 default value 00000000h chapter 3 cpu function user?s manual u17728ej3v1ud 52 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. these registers can be read or written by using system register load/store instructions (ldsr and stsr), using the system register numbers listed below. table 3-2. system register numbers operand specification system register number system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) note 1 3 nmi status saving register (fepsw) note 1 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 note 2 19 exception/debug trap status saving register (dbpsw) note 2 note 2 20 callt base pointer (ctbp) 21 to 31 reserved for future function expansion (operation is not guaranteed if these registers are accessed) notes 1. because only one set of these registers is availabl e, the contents of these r egisters must be saved by program if multiple interrupts are enabled. 2. these registers can be accessed only during th e interval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. caution even if eipc or fepc, or bit 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti instruction after interrupt ser vicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). remark : can be accessed : access prohibited chapter 3 cpu function user?s manual u17728ej3v1ud 53 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are used to save the status when an interrupt occurs. if a software exception or a maskable interrupt occurs, the contents of the program counter (pc) are saved to eipc, and the contents of the program status word ( psw) are saved to eipsw (these contents are saved to the nmi status saving registers (fepc and f epsw) if a non-maskable interrupt occurs). the address of the instruction next to the instruction under execution, except some instructions (see 22.8 periods in which interrupts are not acknowledged by cpu ), is saved to eipc when a software exception or a maskable interrupt occurs. the current contents of the psw are saved to eipsw. because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are reserved for future function expansion (these bits are always fixed to 0). the value of eipc is restored to the pc and the val ue of eipsw to the psw by the reti instruction. 31 0 eipc (contents of saved pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (contents of saved psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 3 cpu function user?s manual u17728ej3v1ud 54 (2) nmi status saving registers (fepc and fepsw) fepc and fepsw are used to save the status when a non-maskable interrupt (nmi) occurs. if an nmi occurs, the contents of the program counter (pc) are saved to fepc, and those of the program status word (psw) are saved to fepsw. the address of the instruction next to the one of the instruction under execut ion, except some instructions, is saved to fepc when an nmi occurs. the current contents of t he psw are saved to fepsw. because only one set of nmi status saving registers is avai lable, the contents of thes e registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served for future function expansion (these bits are always fixed to 0). the value of fepc is restored to the pc and the value of fepsw to the psw by the reti instruction. 31 0 fepc (contents of saved pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (contents of saved psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (3) interrupt source register (ecr) the interrupt source register (ecr) hol ds the source of an exception or in terrupt if an exception or interrupt occurs. this register holds the exc eption code of each interrupt source. be cause this register is a read-only register, data cannot be written to this register using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name meaning 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt chapter 3 cpu function user?s manual u17728ej3v1ud 55 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate th e status of the program (result of instruction execution) and the status of the cpu. if the contents of a bit of this regi ster are changed by using the ldsr instruction, the new contents are validated immediately after completion of ldsr instructi on execution. however if the id flag is set to 1, interrupt requests will not be acknowledged while the ldsr instruction is being executed. bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 0 psw rfu default value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupts. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is being proces sed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. th is flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether a ca rry or a borrow occurs as a result of an operation. 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note indicates whether an overflow occurs during operation. 0: overflow does not occur. 1: overflow occurs. 1 s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. remark also read note on the next page. chapter 3 cpu function user?s manual u17728ej3v1ud 56 (2/2) note the result of the operation that has performed satu ration processing is determined by the contents of the ov and s flags. the sat flag is set to 1 only when the ov flag is set to 1 when a saturation operation is performed. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded 1 1 0 7fffffffh maximum negative value is exceeded 1 1 1 80000000h positive (maximum value is not exceeded) 0 negative (maximum value is not exceeded) holds value before operation 0 1 operation result itself (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execution status saving registers. when the callt instruction is execut ed, the contents of the program count er (pc) are saved to ctpc, and those of the program status wo rd (psw) are saved to ctpsw. the contents saved to ctpc are the address of the inst ruction next to callt. the current contents of t he psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (fixed to 0). 31 0 ctpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 3 cpu function user?s manual u17728ej3v1ud 57 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status registers. if an exception trap or debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and those of the program status word (psw) are saved to dbpsw. the contents to be saved to dbpc are the address of th e instruction next to the one that is being executed when an exception trap or debug trap occurs. the current contents of t he psw are saved to dbpsw. this register can be read or written only during the in terval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (fixed to 0). the value of dbpc is restored to the pc and the value of dbpsw to the psw by the dbret instruction. 31 0 dbpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a table address or generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 ctbp (base address) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 chapter 3 cpu function user?s manual u17728ej3v1ud 58 3.3 operation modes the v850es/sg3 has the following operation modes. (1) normal operation mode in this mode, each pin related to the bus interface is set to the port mode after system reset has been released. execution branches to the reset entry address of the intern al rom, and then instruction processing is started. (2) flash memory programming mode in this mode, the internal flash memory can be programmed by using a flash memory programmer. (3) on-chip debug mode the v850es/sg3 is provided with an on- chip debug function that employs t he jtag (joint test action group) communication specifications and that is executed via an on-chip debug emulator. for details, see chapter 31 on-chip debug function . 3.3.1 specifying operation mode specify the operation mode by using the flmd0 and flmd1 pins. in the normal mode, make sure that a low level is input to the flmd0 when reset is released. in the flash memory programming mode, a high level is in put to the flmd0 pin from the flash memory programmer if a flash memory programmer is connected, but it must be input from an external circuit in the self-programming mode. operation when reset is released flmd0 flmd1 operation mode after reset l normal operation mode h l flash memory programming mode h h setting prohibited remark l: low-level input h: high-level input : don?t care chapter 3 cpu function user?s manual u17728ej3v1ud 59 3.4 address space 3.4.1 cpu address space for instruction addressing, up to a combined total of 16 mb of external memory area and internal rom area, plus an internal ram area, are supported in a linear addres s space (program space) of up to 64 mb. for operand addressing (data access), up to 4 gb of a linear address s pace (data space) is supported. the 4 gb address space, however, is viewed as 64 images of a 64 mb physical a ddress space. this means that the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. image on address space program space internal ram area use-prohibited area use-prohibited area external memory area internal rom area (external memory area) data space image 63 image 1 image 0 peripheral i/o area internal ram area programmable peripheral i/o area or use-prohibited area external memory area internal rom area (external memory area) 16 mb 4 gb 64 mb 64 mb caution only the programmable peripheral i/o area is seen as images of 256 mb each in the 4 gb address space. chapter 3 cpu function user?s manual u17728ej3v1ud 60 3.4.2 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. the higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. therefore, the highest address of the program space, 03ffffffh, and the lowest address, 00000000h, are contiguous addresses. that the highest address and t he lowest address of the pr ogram space are contiguous in this way is called wraparound. caution because the 4 kb area of addresses 03fff000h to 03ffffffh is an on-chip peripheral i/o area, instructions cannot be fetc hed from this area. therefore, do not execute an operation in which the result of a branch addr ess calculation affects this area. program space program space (+) direction ( ? ) direction 00000001h 00000000h 03ffffffh 03fffffeh (2) data space the result of an operand address calculation oper ation that exceeds 32 bits is ignored. therefore, the highest address of the data space, ffffffffh, and the lowest address, 00000000h, are contiguous, and wraparound occurs at the boundary of these addresses. data space data space (+) direction ( ? ) direction 00000001h 00000000h ffffffffh fffffffeh chapter 3 cpu function user?s manual u17728ej3v1ud 61 3.4.3 memory map the areas shown below are re served in the v850es/sg3. figure 3-2. data memory map (physical addresses) (80 kb) use prohibited external memory area (14 mb) internal rom area note 4 (1 mb) external memory area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) use prohibited note 1 (2 mb) 03ffffffh 03fec000h 01000000h 00ffffffh 00200000h 001fffffh 00000000h 03febfffh 03ffffffh 03fff000h 03ffefffh 03ff0000h 03feffffh programmable peripheral i/o area note 2 or use prohibited note 3 03fef000h 03feefffh 03fec000h 001fffffh 00100000h 000fffffh 00000000h notes 1. use of addresses 03fef000h to 03feffffh is prohibited because these addresses are in the same area as the on-chip peripheral i/o area. 2. only the programmable peripheral i/o area can be viewed in the 4 gb address space as t he image in 256 mb unit. 3. addresses 03fec000h to 03fec5ffh are alloca ted to addresses 03fec000h to 03feefffh of the can controller version as a programmable per ipheral i/o area. use of these addresses in a version without a can controller is prohibited. 4. fetch access and read access to addresses 000 00000h to 000fffffh is made to the internal rom area. however, data write access to these addresses is made to the external memory area. chapter 3 cpu function user?s manual u17728ej3v1ud 62 figure 3-3. program memory map internal ram area (60 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area (14 mb) external memory area (1 mb) internal rom area (1 mb) 03ffffffh 03fff000h 03ffefffh 01000000h 00ffffffh 03ff0000h 03feffffh 00200000h 001fffffh 00100000h 000fffffh 00000000h chapter 3 cpu function user?s manual u17728ej3v1ud 63 3.4.4 areas (1) internal rom area up to 1 mb is reserved as an internal rom area. (a) internal rom (256 kb) 256 kb are allocated to addre sses 00000000h to 0003ffffh in the following versions. accessing addresses 00040000h to 000fffffh is prohibited. ? pd70f3333, 70f3335 figure 3-4. internal rom area (256 kb) access-prohibited area internal rom (256 kb) 00040000h 0003ffffh 00000000h 000fffffh chapter 3 cpu function user?s manual u17728ej3v1ud 64 (b) internal rom (384 kb) 384 kb are allocated to addre sses 00000000h to 0005ffffh in the following versions. accessing addresses 00060000h to 000fffffh is prohibited. ? pd70f3334, 70f3336 figure 3-5. internal rom area (384 kb) access-prohibited area internal rom (384 kb) 00060000h 0005ffffh 00000000h 000fffffh (c) internal rom (512 kb) 512 kb are allocated to addre sses 00000000h to 0007ffffh in the following versions. accessing addresses 00080000h to 000fffffh is prohibited. ? pd70f3340, 70f3350 figure 3-6. internal rom area (512 kb) access-prohibited area internal rom (512 kb) 00080000h 0007ffffh 00000000h 000fffffh chapter 3 cpu function user?s manual u17728ej3v1ud 65 (d) internal rom (640 kb) 640 kb are allocated to addre sses 00000000h to 0009ffffh in the following versions. accessing addresses 000a0000h to 000fffffh is prohibited. ? pd70f3341, 70f3351 figure 3-7. internal rom area (640 kb) access-prohibited area internal rom (640 kb) 000a0000h 0009ffffh 00000000h 000fffffh (e) internal rom (768 kb) 768 kb are allocated to addresses 00000000h to 000bffffh in the following versions. accessing addresses 000c0000h to 000fffffh is prohibited. ? pd70f3342, 70f3352 figure 3-8. internal rom area (768 kb) access-prohibited area internal rom (768 kb) 000c0000h 000bffffh 00000000h 000fffffh chapter 3 cpu function user?s manual u17728ej3v1ud 66 (f) internal rom (1024 kb) 1024 kb are allocated to addre sses 00000000h to 000fffffh in the following versions. ? pd70f3343, 70f3353 figure 3-9. internal rom area (1024 kb) internal rom (1024 kb) 00000000h 000fffffh chapter 3 cpu function user?s manual u17728ej3v1ud 67 (2) internal ram area up to 60 kb are reserved as the internal ram area. (a) internal ram (24 kb) 24 kb are allocated to addresses 03ff9000h to 03ffefffh of the following versions. accessing addresses 03ff0000h to 03ff8fffh is prohibited. ? pd70f3333, 70f3335 figure 3-10. internal ram area (24 kb) access-prohibited area internal ram (24 kb) 03ff9000h 03ff8fffh 03ff0000h 03ffefffh ffff9000h ffff8fffh ffff0000h ffffefffh physical address space logical address space chapter 3 cpu function user?s manual u17728ej3v1ud 68 (b) internal ram (32 kb) 32 kb are allocated to addresses 03ff7000h to 03ffefffh of the following versions. accessing addresses 03ff0000h to 03ff6fffh is prohibited. ? pd70f3334, 70f3336 figure 3-11. internal ram area (32 kb) access-prohibited area internal ram (32 kb) 03ff7000h 03ff6fffh 03ff0000h 03ffefffh physical address space logical address space ffff7000h ffff6fffh ffff0000h ffffefffh (c) internal ram (40 kb) 40 kb are allocated to addresses 03ff5000h to 03ffefffh of the following versions. accessing addresses 03ff0000h to 03ff4fffh is prohibited. ? pd70f3340, 70f3350 figure 3-12. internal ram area (40 kb) access-prohibited area internal ram (40 kb) 03ff5000h 03ff4fffh 03ff0000h 03ffefffh ffff5000h ffff4fffh ffff0000h ffffefffh physical address space logical address space chapter 3 cpu function user?s manual u17728ej3v1ud 69 (d) internal ram area (48 kb) 48 kb are allocated to addresses 03ff3000h to 03ffefffh of the following versions. accessing addresses 03ff0000h to 03ff2fffh is prohibited. ? pd70f3341, 70f3351 figure 3-13. internal ram area (48 kb) access-prohibited area internal ram (48 kb) 03ff3000h 03ff2fffh 03ff0000h 03ffefffh physical address space logical address space ffff3000h ffff2fffh ffff0000h ffffefffh (e) internal ram (60 kb) 60 kb are allocated to addresses 03ff0000h to 03ffefffh in the following versions. ? pd70f3342, 70f3343, 70f3352, 70f3353 figure 3-14. internal ram area (60 kb) internal ram (60 kb) 03ff0000h 03ffefffh physical address space logical address space ffff0000h ffffefffh chapter 3 cpu function user?s manual u17728ej3v1ud 70 (3) on-chip peripheral i/o area 4 kb of addresses 03fff000h to 03ffffffh are re served as the on-chip peripheral i/o area. figure 3-15. on-chip peripheral i/o area on-chip peripheral i/o area (4 kb) 03ffffffh 03fff000h ffffffffh fffff000h physical address space logical address space peripheral i/o registers that have functions to specif y the operation mode for and mo nitor the status of the on- chip peripheral i/o are mapped to the on-chip periphe ral i/o area. program cannot be fetched from this area. cautions 1. when a register is accessed in word units, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read , and data is written to the lower 8 bits. 3. addresses not defined as registers are r eserved for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. 4. the internal rom/ram area and on-chip peripheral i/o area are assigned to successive addresses. when accessing the in ternal rom/ram area by in crementing or decrementing addresses using pointer operations and such, therefore, be careful not to access the on- chip peripheral i/o area by mistakenly ex tending over the internal rom/ram area boundary. chapter 3 cpu function user?s manual u17728ej3v1ud 71 (4) programmable peripheral i/o area cautions 1. the programmable peripheral i/o area exists only in the can controller versions. this area cannot be used with products that are not equipped with the can controller. 2. only the programmable peripheral i/o area is seen as images of 256 mb each in the 4 gb address space. 12 kb of addresses 03fec000h to 03feefffh are rese rved as the programmable peripheral i/o area. figure 3-16. programmable peripheral i/o area programmable peripheral i/o area (12 kb) 03feefffh 03fec000h chapter 3 cpu function user?s manual u17728ej3v1ud 72 (5) external memory area 15 mb (00100000h to 00ffffffh ) are allocated as the external memory area. for details, see chapter 5 bus control function . caution the v850es/sg3 has 22 address pins (a0 to a21), so the exte rnal memory area appears as a repeated 4 mb image. when the a20 and a21 pins are used, it is necessary that ev dd = bv dd = v dd . (6) product selection register (prdsel) the prdsel register is a register to identif y the product name and the internal ram area. this register is used divided into two 16-bit registers, prdselh and prdsell. this register is read-only, in 16-bit units. caution this register cannot be read by the in-c ircuit emulator (ie-v850es-g1, qb-v850essx2) (an undefined value is read). remarks 1. see table 3-3 for product name setting examples. 2. x: undefined value table 3-3. product name setting examples prdsell register product name bit 15 bit 14 bit 13 bit 12 bit 11 bi t 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 pd70f3 335 0 0 1 1 0 0 1 1 0 1 0 1 pd70f3 336 0 0 1 1 0 0 1 1 0 1 1 0 pd70f3 350 0 0 1 1 0 1 0 1 0 0 0 0 pd70f3 351 0 0 1 1 0 1 0 1 0 0 0 1 pd70f3 352 0 0 1 1 0 1 0 1 0 0 1 0 pd70f3 353 0 0 1 1 0 1 0 1 0 0 1 1 ram3 0 0 1 1 1 ram2 1 1 0 0 0 ram1 1 1 0 0 1 ram0 0 1 0 1 0 ram start address 03ff9000h 03ff7000h after reset: depends on product r address: prdsell fffffcc8h, prdselh fffffccah product name (last 3 digits) prdselh prdsell ram3 ram2 ram1 ram0 03ff5000h 03ff3000h 03ff0000h chapter 3 cpu function user?s manual u17728ej3v1ud 73 3.4.5 recommended use of address space the architecture of the v850es/sg3 r equires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. bec ause the number of general-pur pose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program count er), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, therefore, a 64 mb spac e of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the prog ram space, access the following addresses. caution if a branch instruction is at the upper limi t of the internal ram ar ea, a prefetch operation (invalid fetch) straddling the on-chip peripheral i/o area does not occur. ram size access address 60 kb 03ff0000h to 03ffefffh 48 kb 03ff3000h to 03ffefffh 40 kb 03ff5000h to 03ffefffh 32 kb 03ff7000h to 03ffefffh 24 kb 03ff9000h to 03ffefffh chapter 3 cpu function user?s manual u17728ej3v1ud 74 (2) data space with the v850es/sg3, it seems that there are sixty-four 64 mb addre ss spaces on the 4 gb cpu address space. therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st di sp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by har dware, and practically eliminates the need for registers dedicated to pointers. example : pd70f3334, 70f3336 internal rom area on-chip peripheral i/o area internal ram area 3 2 kb 4 kb 28 kb (r = ) 0005ffffh 00007fffh 00000000h fffff000h ffffefffh ffff8000h chapter 3 cpu function user?s manual u17728ej3v1ud 75 figure 3-17. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited note internal ram program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh ffff0000h fffeffffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ff7000h 03ff6fffh 03ff0000h 03feffffh 01000000h 00ffffffh 00060000h 0005ffffh 00100000h 000fffffh 00000000h ffffffffh fffff000h ffffefffh ffff7000h ffff6fffh ffff0000h fffeffffh 00100000h 000fffffh 00000000h use prohibited note in the can controller version, the data space of addresses 03fec0 00h to 03feefffh is assigned as the programmable peripheral i/o area. only the prog rammable peripheral i/o area is seen as images of 256 mb each in the 4 gb address space. remarks 1. indicates the recommended area. 2. this figure is the recommended memory map of the pd70f3334. chapter 3 cpu function user?s manual u17728ej3v1ud 76 3.4.6 peripheral i/o registers (1/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl register pdl 0000h note 1 fffff004h port dl register l pdll 00h note 1 fffff005h port dl register h pdlh 00h note 1 fffff006h port dh register pdh 00h note 1 fffff00ah port ct register pct 00h note 1 fffff00ch port cm register pcm 00h note 1 fffff024h port dl mode register pmdl ffffh fffff024h port dl mode register l pmdll ffh fffff025h port dl mode register h pmdlh ffh fffff026h port dh mode register pmdh ffh fffff02ah port ct mode register pmct ffh fffff02ch port cm mode register pmcm ffh fffff044h port dl mode control register pmcdl 0000h fffff044h port dl mode control register l pmcdll 00h fffff045h port dl mode control register h pmcdlh 00h fffff046h port dh mode control register pmcdh 00h fffff04ah port ct mode control register pmcct 00h fffff04ch port cm mode control register pmccm 00h fffff064h peripheral i/o area select control register bpc note 2 0000h fffff066h bus size configuration register bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source address register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source address register 1l dsa1l undefined fffff08ah dma source address register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source address register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h undefined fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h undefined fffff098h dma source address register 3l dsa3l undefined fffff09ah dma source address register 3h dsa3h undefined fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h undefined fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 r/w undefined notes 1. the output latch is 00h or 0000h. when these registers are in the input mode, the pin statuses are read. 2. can controller versions only chapter 3 cpu function user?s manual u17728ej3v1ud 77 (2/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff0d0h dma addressing control register 0 dadc0 0000h fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 00h fffff0e2h dma channel control register 1 dchc1 00h fffff0e4h dma channel control register 2 dchc2 00h fffff0e6h dma channel control register 3 dchc3 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff110h interrupt control register lviic 47h fffff112h interrupt control register pic0 47h fffff114h interrupt control register pic1 47h fffff116h interrupt control register pic2 47h fffff118h interrupt control register pic3 47h fffff11ah interrupt control register pic4 47h fffff11ch interrupt control register pic5 47h fffff11eh interrupt control register pic6 47h fffff120h interrupt control register pic7 47h fffff122h interrupt control register tq0ovic 47h fffff124h interrupt control register tq0ccic0 47h fffff126h interrupt control register tq0ccic1 47h fffff128h interrupt control register tq0ccic2 47h fffff12ah interrupt control register tq0ccic3 47h fffff12ch interrupt control register tp0ovic 47h fffff12eh interrupt control register tp0ccic0 47h fffff130h interrupt control register tp0ccic1 47h fffff132h interrupt control register tp1ovic 47h fffff134h interrupt control register tp1ccic0 47h fffff136h interrupt control register tp1ccic1 47h fffff138h interrupt control register tp2ovic 47h fffff13ah interrupt control register tp2ccic0 47h fffff13ch interrupt control register tp2ccic1 r/w 47h chapter 3 cpu function user?s manual u17728ej3v1ud 78 (3/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff13eh interrupt control register tp3ovic 47h fffff140h interrupt control register tp3ccic0 47h fffff142h interrupt control register tp3ccic1 47h fffff144h interrupt control register tp4ovic 47h fffff146h interrupt control register tp4ccic0 47h fffff148h interrupt control register tp4ccic1 47h fffff14ah interrupt control register tp5ovic 47h fffff14ch interrupt control register tp5ccic0 47h fffff14eh interrupt control register tp5ccic1 47h fffff150h interrupt control register tm0eqic0 47h fffff1 52 h interrupt control register cb0ric/iicic1 47h fffff1 54 h interrupt control register cb0tic 47h fffff156h interrupt control register cb1ric 47h fffff158h interrupt control register cb1tic 47h fffff15ah interrupt control register cb2ric 47h fffff15ch interrupt control register cb2tic 47h fffff15eh interrupt control register cb3ric 47h fffff160h interrupt control register cb3tic 47h fffff162h interrupt control register ua0ric/cb4ric 47h fffff164h interrupt control register ua0tic/cb4tic 47h fffff166h interrupt control register ua1ric/iicic2 47h fffff168h interrupt control register ua1tic 47h fffff16ah interrupt control register ua2ric/iicic0 47h fffff16ch interrupt control register ua2tic 47h fffff16eh interrupt control register adic 47h fffff170h interrupt control register dmaic0 47h fffff172h interrupt control register dmaic1 47h fffff174h interrupt control register dmaic2 47h fffff176h interrupt control register dmaic3 47h fffff178h interrupt control register kric 47h fffff17ah interrupt control register wtiic 47h fffff17ch interrupt control register wtic 47h fffff17eh interrupt control register erric0 note / erric 47h fffff180h interrupt control register wupic0 note / staic 47h fffff182h interrupt control register recic0 note / ieic1 47h fffff184h interrupt control register trxic0 note / ieic2 r/w 47h note can controller versions only chapter 3 cpu function user?s manual u17728ej3v1ud 79 (4/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc 00h fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail compare mode register ada0pfm 00h fffff205h power-fail compare threshold value register ada0pft r/w 00h fffff210h a/d conversion result register 0 ada0cr0 undefined fffff211h a/d conversion result register 0h ada0cr0h undefined fffff212h a/d conversion result register 1 ada0cr1 undefined fffff213h a/d conversion result register 1h ada0cr1h undefined fffff214h a/d conversion result register 2 ada0cr2 undefined fffff215h a/d conversion result register 2h ada0cr2h undefined fffff216h a/d conversion result register 3 ada0cr3 undefined fffff217h a/d conversion result register 3h ada0cr3h undefined fffff218h a/d conversion result register 4 ada0cr4 undefined fffff219h a/d conversion result register 4h ada0cr4h undefined fffff21ah a/d conversion result register 5 ada0cr5 undefined fffff21bh a/d conversion result register 5h ada0cr5h undefined fffff21ch a/d conversion result register 6 ada0cr6 undefined fffff21dh a/d conversion result register 6h ada0cr6h undefined fffff21eh a/d conversion result register 7 ada0cr7 undefined fffff21fh a/d conversion result register 7h ada0cr7h undefined fffff220h a/d conversion result register 8 ada0cr8 undefined fffff221h a/d conversion result register 8h ada0cr8h undefined fffff222h a/d conversion result register 9 ada0cr9 undefined fffff223h a/d conversion result register 9h ada0cr9h undefined fffff224h a/d conversion result register 10 ada0cr10 undefined fffff225h a/d conversion result register 10h ada0cr10h undefined fffff226h a/d conversion result register 11 ada0cr11 undefined fffff227h a/d conversion result register 11h ada0cr11h r undefined fffff280h d/a converter conversion va lue setting register 0 da0cs0 00h fffff281h d/a converter conversion va lue setting register 1 da0cs1 00h fffff282h d/a converter mode register da0m 00h fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff310h crc input register crcin 00h fffff312h crc data register crcd 0000h fffff318h noise elimination control register nfc 00h fffff320h brg1 prescaler mode register prsm1 r/w 00h chapter 3 cpu function user?s manual u17728ej3v1ud 80 (5/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff321h brg1 prescaler compare register prscm1 00h fffff324h brg2 prescaler mode register prsm2 00h fffff325h brg2 prescaler compare register prscm2 00h fffff328h brg3 prescaler mode register prsm3 00h fffff329h brg3 prescaler compare register prscm3 00h fffff340h iic division clock select register ocks0 00h fffff344h iic division clock select register ocks1 00h fffff348h iebus clock select register ocks2 00h fffff360h iebus control register bcr 00h fffff361h iebus power save register psr r/w 00h fffff362h iebus slave status register ssr 81h fffff363h iebus unit status register usr r 00h fffff364h iebus interrupt status register isr 00h fffff365h iebus error status register esr 00h fffff366h iebus unit address register uar 0000h fffff368h iebus slave address register sar r/w 0000h fffff36ah iebus partner ad dress register par 0000h fffff36ch iebus receive slave address register rsa r 0000h fffff36eh iebus control data register cdr 00h fffff36fh iebus telegraph length register dlr 01h fffff370h iebus data register dr r/w 00h fffff371h iebus field status register fsr 00h fffff372h iebus success count register scr 01h fffff373h iebus communication count register ccr r 20h fffff400h port 0 register p0 00h note fffff402h port 1 register p1 00h note fffff406h port 3 register p3 0000h note fffff406h port 3 register l p3l 00h note fffff407h port 3 register h p3h 00h note fffff408h port 4 register p4 00h note fffff40ah port 5 register p5 00h note fffff40eh port 7 register l p7l 00h note fffff40fh port 7 register h p7h 00h note fffff412h port 9 register p9 0000h note fffff412h port 9 register l p9l 00h note fffff413h port 9 register h p9h 00h note fffff420h port 0 mode register pm0 ffh fffff422h port 1 mode register pm1 ffh fffff426h port 3 mode register pm3 ffffh fffff426h port 3 mode register l pm3l ffh fffff427h port 3 mode register h pm3h r/w ffh note the output latch is 00h or 0000h. when these registers are input, the pin statuses are read. chapter 3 cpu function user?s manual u17728ej3v1ud 81 (6/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff428h port 4 mode register pm4 ffh fffff42ah port 5 mode register pm5 ffh fffff42eh port 7 mode register l pm7l ffh fffff42fh port 7 mode register h pm7h ffh fffff432h port 9 mode register pm9 ffffh fffff432h port 9 mode register l pm9l ffh fffff433h port 9 mode register h pm9h ffh fffff440h port 0 mode control register pmc0 00h fffff446h port 3 mode control register pmc3 0000h fffff446h port 3 mode control register l pmc3l 00h fffff447h port 3 mode control register h pmc3h 00h fffff448h port 4 mode control register pmc4 00h fffff44ah port 5 mode control register pmc5 00h fffff452h port 9 mode control register pmc9 0000h fffff452h port 9 mode control register l pmc9l 00h fffff453h port 9 mode control register h pmc9h 00h fffff460h port 0 function control register pfc0 00h fffff466h port 3 function control register pfc3 0000h fffff466h port 3 function control register l pfc3l 00h fffff467h port 3 function control register h pfc3h 00h fffff468h port 4 function control register pfc4 00h fffff46ah port 5 function control register pfc5 00h fffff472h port 9 function control register pfc9 0000h fffff472h port 9 function control register l pfc9l 00h fffff473h port 9 function control register h pfc9h 00h fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc aaaah fffff540h tmq0 control register 0 tq0ctl0 00h fffff541h tmq0 control register 1 tq0ctl1 00h fffff542h tmq0 i/o control register 0 tq0ioc0 00h fffff543h tmq0 i/o control register 1 tq0ioc1 00h fffff544h tmq0 i/o control register 2 tq0ioc2 00h fffff545h tmq0 option register 0 tq0opt0 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 0000h fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 counter read buffer register tq0cnt r 0000h chapter 3 cpu function user?s manual u17728ej3v1ud 82 (7/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff590h tmp0 control register 0 tp0ctl0 00h fffff591h tmp0 control register 1 tp0ctl1 00h fffff592h tmp0 i/o control register 0 tp0ioc0 00h fffff593h tmp0 i/o control register 1 tp0ioc1 00h fffff594h tmp0 i/o control register 2 tp0ioc2 00h fffff595h tmp0 option register 0 tp0opt0 00h fffff596h tmp0 capture/compare register 0 tp0ccr0 0000h fffff598h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter read buffer register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 00h fffff5a1h tmp1 control register 1 tp1ctl1 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 00h fffff5a3h tmp1 i/o control register 1 tp1ioc1 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 00h fffff5a5h tmp1 option register 0 tp1opt0 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter read buffer register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 00h fffff5b1h tmp2 control register 1 tp2ctl1 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 00h fffff5b5h tmp2 option register 0 tp2opt0 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 0000h fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter read buffer register tp2cnt r 0000h fffff5c0h tmp3 control register 0 tp3ctl0 00h fffff5c1h tmp3 control register 1 tp3ctl1 00h fffff5c2h tmp3 i/o control register 0 tp3ioc0 00h fffff5c3h tmp3 i/o control register 1 tp3ioc1 00h fffff5c4h tmp3 i/o control register 2 tp3ioc2 00h fffff5c5h tmp3 option register 0 tp3opt0 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 1 tp3ccr1 r/w 0000h fffff5cah tmp3 counter read buffer register tp3cnt r 0000h fffff5d0h tmp4 control register 0 tp4ctl0 00h fffff5d1h tmp4 control register 1 tp4ctl1 00h fffff5d2h tmp4 i/o control register 0 tp4ioc0 00h fffff5d3h tmp4 i/o control register 1 tp4ioc1 00h fffff5d4h tmp4 i/o control register 2 tp4ioc2 00h fffff5d5h tmp4 option register 0 tp4opt0 00h fffff5d6h tmp4 capture/compare register 0 tp4ccr0 0000h fffff5d8h tmp4 capture/compare register 1 tp4ccr1 r/w 0000h chapter 3 cpu function user?s manual u17728ej3v1ud 83 (8/11) manipulatable bits address function register name symbol r/w 1 8 16 32 default value fffff5dah tmp4 counter read buffer register tp4cnt r 0000h fffff5e0h tmp5 control register 0 tp5ctl0 00h fffff5e1h tmp5 control register 1 tp5ctl1 00h fffff5e2h tmp5 i/o control register 0 tp5ioc0 00h fffff5e3h tmp5 i/o control register 1 tp5ioc1 00h fffff5e4h tmp5 i/o control register 2 tp5ioc2 00h fffff5e5h tmp5 option register 0 tp5opt0 00h fffff5e6h tmp5 capture/compare register 0 tp5ccr0 0000h fffff5e8h tmp5 capture/compare register 1 tp5ccr1 r/w 0000h fffff5eah tmp5 counter read buffer register tp5cnt r 0000h fffff680h watch timer operation mode register wtm 00h fffff690h tmm0 control register 0 tm0ctl0 00h fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff6e0h real-time output buffer register 0l rtbl0 00h fffff6e2h real-time output buffer register 0h rtbh0 00h fffff6e4h real-time output port mode register 0 rtpm0 00h fffff6e5h real-time output port control register 0 rtpc0 00h fffff706h port 3 function control expansion register l pfce3l 00h fffff70ah port 5 function control expansion register pfce5 00h fffff712h port 9 function control expansion register pfce9 0000h fffff712h port 9 function control expansion register l pfce9l 00h fffff713h port 9 function control expansion register h pfce9h 00h fffff802h system status register sys 00h fffff80ch internal oscillation mode register rcm 00h fffff810h dma trigger factor register 0 dtfr0 00h fffff812h dma trigger factor register 1 dtfr1 00h fffff814h dma trigger factor register 2 dtfr2 00h fffff816h dma trigger factor register 3 dtfr3 00h fffff820h power save mode register psmr 00h fffff822h clock control register ckc r/w 0ah fffff824h lock register lockr r 00h fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operation clock status register ccls r 00h fffff840h correction address register 0 corad0 00000000h fffff840h correction address register 0l corad0l 0000h fffff842h correction address register 0h corad0h r/w 0000h chapter 3 cpu function user?s manual u17728ej3v1ud 84 (9/11) manipulatable bits address function register name symbol r/w 1 8 16 32 default value fffff844h correction address register 1 corad1 00000000h fffff844h correction address register 1l corad1l 0000h fffff846h correction address register 1h corad1h 0000h fffff848h correction address register 2 corad2 00000000h fffff848h correction address register 2l corad2l 0000h fffff84ah correction address register 2h corad2h 0000h fffff84ch correction address register 3 corad3 00000000h fffff84ch correction address register 3l corad3l 0000h fffff84eh correction address register 3h corad3h 0000h fffff870h clock monitor mode register clm 00h fffff880h correction control register corcn 00h fffff888h reset source flag register resf 00h fffff890h low-voltage detection register lvim 00h fffff891h low-voltage detection level select register lvis 00h fffff892h internal ram data status register rams 01h fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff9fch on-chip debug mode register ocdm 01h fffff9feh peripheral emul ation register 1 pemu1 note 00h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str r/w 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 ffh fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str r/w 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 transmit data register ua1tx ffh fffffa20h uarta2 control register 0 ua2ctl0 10h fffffa21h uarta2 control register 1 ua2ctl1 00h fffffa22h uarta2 control register 2 ua2ctl2 ffh fffffa23h uarta2 option control register 0 ua2opt0 14h fffffa24h uarta2 status register ua2str r/w 00h fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx ffh fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc06h external interrupt falling edge specification register 3 intf3 r/w 00h note only during emulation chapter 3 cpu function user?s manual u17728ej3v1ud 85 (10/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffc13h external interrupt falling edge specification register 9h intf9h 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc26h external interrupt rising edge specification register 3 intr3 00h fffffc33h external interrupt rising edge specification register 9h intr9h 00h fffffc60h port 0 function register pf0 00h fffffc66h port 3 function register pf3 0000h fffffc66h port 3 function register l pf3l 00h fffffc67h port 3 function register h pf3h 00h fffffc68h port 4 function register pf4 00h fffffc6ah port 5 function register pf5 00h fffffc72h port 9 function register pf9 0000h fffffc72h port 9 function register l pf9l 00h fffffc73h port function 9 register h pf9h r/w 00h fffffcc8h product selection register l prdsell depends on product fffffccah product selection register h prdselh r depends on product fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1 control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl 00h fffffd20h csib2 control register 0 cb2ctl0 01h fffffd21h csib2 control register 1 cb2ctl1 00h fffffd22h csib2 control register 2 cb2ctl2 00h fffffd23h csib2 status register cb2str r/w 00h fffffd24h csib2 receive data register cb2rx 0000h fffffd24h csib2 receive data register l cb2rxl r 00h fffffd26h csib2 transmit data register cb2tx 0000h fffffd26h csib2 transmit data register l cb2txl 00h fffffd30h csib3 control register 0 cb3ctl0 01h fffffd31h csib3 control register 1 cb3ctl1 00h fffffd32h csib3 control register 2 cb3ctl2 00h fffffd33h csib3 status register cb3str r/w 00h chapter 3 cpu function user?s manual u17728ej3v1ud 86 (11/11) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffd34h csib3 receive data register cb3rx r 0000h fffffd34h csib3 receive data register l cb3rxl 0000h fffffd36h csib3 transmit data register cb3tx 0000h fffffd36h csib3 transmit data register l cb3txl 00h fffffd40h csib4 control register 0 cb4ctl0 01h fffffd41h csib4 control register 1 cb4ctl1 00h fffffd42h csib4 control register 2 cb4ctl2 00h fffffd43h csib4 status register cb4str 00h fffffd44h csib4 receive data register cb4rx 0000h fffffd44h csib4 receive data register l cb4rxl r 00h fffffd46h csib4 transmit data register cb4tx 0000h fffffd46h csib4 transmit data register l cb4txl 00h fffffd80h iic shift register 0 iic0 00h fffffd82h iic control register 0 iicc0 00h fffffd83h slave address register 0 sva0 00h fffffd84h iic clock select register 0 iiccl0 00h fffffd85h iic function expansion register 0 iicx0 r/w 00h fffffd86h iic status register 0 iics0 r 00h fffffd8ah iic flag register 0 iicf0 00h fffffd90h iic shift register 1 iic1 00h fffffd92h iic control register 1 iicc1 00h fffffd93h slave address register 1 sva1 00h fffffd94h iic clock select register 1 iiccl1 00h fffffd95h iic function expansion register 1 iicx1 r/w 00h fffffd96h iic status register 1 iics1 r 00h fffffd9ah iic flag register 1 iicf1 00h fffffda0h iic shift register 2 iic2 00h fffffda2h iic control register 2 iicc2 00h fffffda3h slave address register 2 sva2 00h fffffda4h iic clock select register 2 iiccl2 00h fffffda5h iic function expansion register 2 iicx2 r/w 00h fffffda6h iic status register 2 iics2 r 00h fffffdaah iic flag register 2 iicf2 00h fffffdbeh external bus interface mode control register eximc r/w 00h chapter 3 cpu function user?s manual u17728ej3v1ud 87 3.4.7 programmable peripheral i/o registers the bpc register is used for programmable peripheral i/o register area selection. (1) peripheral i/o area selec t control register (bpc) the bpc register can be read or written in 16-bit units. reset input clears this register to 0000h. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address default value bpc pa15 0 pa13 pa12 pa11 pa10 pa09 pa08 pa07 pa06 pa05 pa04 pa03 pa02 pa01 pa00 fffff064h 0000h bit position bit name function enables/disables usage of prog rammable peripheral i/o area. pa15 usage of programmable peripheral i/o area 0 usage of programmable peripheral i/o area disabled 1 usage of programmable peripheral i/o area enabled 15 pa15 13 to 0 pa13 to pa00 specify an address in programmabl e peripheral i/o area (corresponding to a27 to a14, respectively). caution when setting the pa15 bit to 1, be sure to set the bpc register to 8ffbh. when clearing the pa15 bit to 0, be su re to set the bpc register to 0000h. for a list of the programmable peripheral i/o register areas, see table 19-16 register access types . chapter 3 cpu function user?s manual u17728ej3v1ud 88 3.4.8 special registers special registers are registers that are protected from being written with illegal data due to a program hang-up. v850es/sg3 has the following eight special registers. ? power save control register (psc) ? clock control register (ckc) ? processor clock control register (pcc) ? clock monitor mode register (clm) ? reset source flag register (resf) ? low-voltage detection register (lvim) ? internal ram data status register (rams) ? on-chip debug mode register (ocdm) in addition, the prcdm register is provided to protect again st a write access to the spec ial registers so that the application system does not inadv ertently stop due to a program hang-up. a write access to the special registers is made in a specific sequence, and an illegal st ore operation is reported to the sys register. chapter 3 cpu function user?s manual u17728ej3v1ud 89 (1) setting data to special registers set data to the special registers in the following sequence. <1> disable dma operation. <2> prepare data to be set to the special register in a general-purpose register. <3> write the data prepared in <2> to the prcmd register. <4> write the setting data to the special re gister (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) (<5> to <9> insert nop instructions (5 instructions).) note <10> enable dma operation if necessary. [example] with psc register (setting standby mode) st.b r11, psmr[r0] ; set psmr register (setting idle1, idle2, and stop modes). <1>clr1 0, dchcn[r0] ; disable dma operation. n = 0 to 3 <2>mov0x02, r10 <3>st.b r10, prcmd[r0] ; write prcmd register. <4>st.b r10, psc[r0] ; set psc register. <5>nop note ; dummy instruction <6>nop note ; dummy instruction <7>nop note ; dummy instruction <8>nop note ; dummy instruction <9>nop note ; dummy instruction <10>set1 0, dchcn[r0] ; enable dma operation. n = 0 to 3 (next instruction) there is no special sequence to read a special register. note five nop instructions or more must be inserted immediately after setting the idle1 mode, idle2 mode, or stop mode (by setting the psc.stp bit to 1). cautions 1. when a store instruction is executed to store data in the comma nd register, interrupts are not acknowledged. this is because it is assumed that steps <3> and <4> above are performed by successive store instructions. if another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. 2. although dummy data is written to th e prcmd register, use the same general-purpose register used to set the speci al register (<4> in example) to write data to the prcmd register (<3> in example). the same applies when a general-purpose register is used for addressing. chapter 3 cpu function user?s manual u17728ej3v1ud 90 (2) command register (prcmd) the prcmd register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that t he system does not inadvertently stop due to a program hang-up. the first write access to a special register is valid after data has be en written in advance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific se quence, so as to protect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch chapter 3 cpu function user?s manual u17728ej3v1ud 91 (3) system status register (sys) status flags that indicate the ope ration status of the overall system are allocated to this register. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 protection error did not occur protection error occurred prerr 0 1 detects protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) (i) when data is written to a special register without writing anything to the prcmd register (when <4> is executed without executing <3> in 3.4.8 (1) setting data to special registers ) (ii) when data is written to an on-chip peripheral i/o register other than a special register (including execution of a bit manipulation instruction) afte r writing data to the prcmd register (if <3> in 3.4.8 (1) setting data to special registers is not the setting of a special register) remark even if an on-chip peripheral i/o register is read (except by a bit manipulation instruction) between an operation to write the prcmd register and an operation to write a special register, the prerr flag is not set, and the set dat a can be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the prerr flag (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcm d register, the prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to the prcmd regist er, which is not a special register, immediately after a write access to the prcmd regi ster, the prerr bit is set to 1. chapter 3 cpu function user?s manual u17728ej3v1ud 92 3.4.9 cautions (1) registers to be set first be sure to set the following registers first when using the v850es/sg3. ? system wait control register (vswc) ? on-chip debug mode register (ocdm) ? watchdog timer mode register 2 (wdtm2) after setting the vswc, ocdm, and wdtm2 registers, set the other registers as necessary. when using the external bus, set each pin to the alternate-function bus control pin mode by using the port- related registers after setting the above registers. (a) system wait control register (vswc) the vswc register controls wait of bus a ccess to the on-chip peripheral i/o registers. three clocks are required to access an on-chip pe ripheral i/o register (without a wait cycle). the v850es/sg3 requires wait cycles according to the o perating frequency. set the following value to the vswc register in accordance with the frequency used. the vswc register can be read or written in 8-bit units (address: fffff06eh, default value: 77h). operating frequency (f clk ) set value of vswc number of waits 32 khz f clk < 16.6 mhz 00h 0 (no waits) 16.6 mhz f clk < 25 mhz 01h 1 25 mhz f clk 32 mhz 11h 2 (b) on-chip debug mode register (ocdm) for details, see chapter 31 on-chip debug function . (c) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time and the operation clock of the watchdog timer 2. the watchdog timer 2 automatically st arts in the reset mode after reset is released. write the wdtm2 register to activate this operation. for details, see chapter 11 functions of watchdog timer 2 . chapter 3 cpu function user?s manual u17728ej3v1ud 93 (2) accessing specific on-chip peripheral i/o registers this product has two types of internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with low-speed peripheral hardware. the clock of the cpu bus and the clock of the peripher al bus are asynchronous. if an access to the cpu and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. if there is a possibility of a conflict, the number of cycles for acce ssing the cpu changes when t he peripheral hardware is accessed, so that correct data is transferred. as a result, the cpu does not start processing of the next instruction but enters the wait status. if this wait status occurs, the number of clocks required to execute an instruction increases by the number of wait clocks shown below. this must be taken into consideration if real-time processing is required. when specific on-chip peripheral i/o registers are access ed, more wait states may be required in addition to the wait states set by the vswc register. the access conditions and how to calculate the number of wait states to be inserted (number of cpu clocks) at this time are shown below. (1/2) peripheral function register name access k tpncnt read 1 or 2 write ? 1st access: no wait ? continuous write: 3 or 4 16-bit timer/event counter p (tmp) (n = 0 to 5) tpnccr0, tpnccr1 read 1 or 2 tq0cnt read 1 or 2 write ? 1st access: no wait ? continuous write: 3 or 4 16-bit timer/event counter q (tmq) tq0ccr0 to tq0ccr3 read 1 or 2 watchdog timer 2 (wdt2) wdtm2 write (when wdt2 operating) 3 rtbl0 write (rtpc0.rtpoe0 bit = 0) 1 real-time output function (rto) rtbh0 write (rtpc0.rtpoe0 bit = 0) 1 ada0m0 read 1 or 2 ada0cr0 to ada0cr11 read 1 or 2 a/d converter ada0cr0h to ada0cr11h read 1 or 2 i 2 c00 to i 2 c02 iics0 to iics2 read 1 chapter 3 cpu function user?s manual u17728ej3v1ud 94 (2/2) peripheral function register name access k c0gmabt, c0gmabtd, c0maskal, c0maskah, c0lec, c0info, c0erc, c0ie, c0ints, c0brp, c0btr, c0ts read/write (f xx /f canmod + 1)/(2 + j) (min.) note (2 f xx /f canmod + 1)/(2 + j) (max.) note c0gmctrl, c0gmcs, c0ctrl read/write (f xx /f can + 1)/(2 + j) (min.) note (2 f xx /f can + 1)/(2 + j) (max.) note write (f xx /f canmod + 1)/(2 + j) (min.) note (2 f xx /f canmod + 1)/(2 + j) (max.) note c0rgpt, c0tgpt read (3 f xx /f canmode + 1)/(2 + j) (min.) note (4 f xx /f canmode + 1)/(2 + j) (max.) note c0lipt, c0lopt read (3 f xx /f canmode + 1)/(2 + j) (min.) note (4 f xx /f canmode + 1)/(2 + j) (max.) note c0mctrlm write (4 f xx /f can + 1)/(2 + j) (min.) note (5 f xx /f can + 1)/(2 + j) (max.) note read (3 f xx /f can + 1)/(2 + j) (min.) note (4 f xx /f can + 1)/(2 + j) (max.) note write (8 bits) (4 f xx /f canmode + 1)/(2 + j) (min.) note (5 f xx /f canmode + 1)/(2 + j) (max.) note write (16 bits) (2 f xx /f canmode + 1)/(2 + j) (min.) note (3 f xx /f canmode + 1)/(2 + j) (max.) note can controller (m = 0 to 31, a = 1 to 4) c0mdata01m, c0mdata0m, c0mdata1m, c0mdata23m, c0mdata2m, c0mdata3m, c0mdata45m, c0mdata4m, c0mdata5m, c0mdata67m, c0mdata6m, c0mdata7m, c0mdlcm, c0mconfm, c0midlm, c0midhm read (8/16 bits) (3 f xx /f canmode + 1)/(2 + j) (min.) note (4 f xx /f canmode + 1)/(2 + j) (max.) note crc crcd write 1 number of clocks necessary for access = 3 + i + j + (2 + j) k note digits below the decimal point are rounded up. caution accessing the above registers is prohibited in the following statuses. if a wait cycle is generated, it can only be cleared by a reset. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock remark f xx : main clock frequency = f xx f canmod : can module system clock f can : clock supplied to can i: values (0 or 1) of higher 4 bits of vswc register j: values (0 or 1) of lower 4 bits of vswc register chapter 3 cpu function user?s manual u17728ej3v1ud 95 (3) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an in terrupt request before the instruction in <1> is complete, the execution result of the instru ction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sl d.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 user?s manual u17728ej3v1ud 96 chapter 4 port functions 4.1 features { i/o ports: 84 ? 5 v tolerant/n-ch open-drain output selectable: 40 (ports 0, 3 to 5, 9) { input/output specifiable in 1-bit units 4.2 basic port configuration the v850es/sg3 features a total of 84 i/o ports consisting of ports 0, 1, 3 to 5, 7, 9, cm, ct, dh, and dl. the port configuration is shown below. figure 4-1. port configuration diagram p02 p06 port 0 pcm0 pcm3 port cm p90 p915 port 9 pct0 pct1 pct4 pct6 port ct pdh0 pdh5 port dh pdl0 pdl15 port dl p30 p39 port 3 port 1 p40 p42 port 4 p50 p55 port 5 p70 p711 port 7 p10 p11 caution ports 0, 3 to 5, and 9 are 5 v tolerant. table 4-1. i/o buffer power supplies for pins power supply corresponding pins av ref0 port 7 av ref1 port 1 bv dd ports cm, ct, dh (bits 0 to 3), dl ev dd reset, ports 0, 3 to 5, 9, dh (bits 4, 5) chapter 4 port functions user?s manual u17728ej3v1ud 97 4.3 port configuration table 4-2. port configuration item configuration control register port n mode register (pmn: n = 0, 1, 3 to 5, 7, 9, cd, cm, ct, dh, dl) port n mode control register (pmcn: n = 0, 3 to 5, 9, cm, ct, dh, dl) port n function control register (pfcn: n = 0, 3 to 5, 9) port n function control expansion register (pfcen: n = 3, 5, 9) port n function register (pfn: n = 0, 3 to 5, 9) ports i/o: 84 (1) port n register (pn) data is input from or output to an external device by writing or reading the pn register. the pn register consists of a port latch that holds output data, and a circ uit that reads the status of pins. each bit of the pn register corresponds to one pin of port n, and can be read or written in 1-bit units. pn7 output 0. output 1. pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h (output latch) r/w data is written to or read from the pn register as follows, regardless of the setting of the pmcn register. table 4-3. writing/reading pn register setting of pmn register writing to pn register reading from pn register output mode (pmnm = 0) data is written to the output latch note . in the port mode (pmcn = 0), the contents of the output latch are output from the pins. the value of the output latch is read. input mode (pmnm = 1) data is written to the output latch. the pin status is not affected note . the pin status is read. note the value written to the output latch is retained until a new value is written to the output latch. chapter 4 port functions user?s manual u17728ej3v1ud 98 (2) port n mode register (pmn) the pmn register specifies the input or output mode of the corresponding port pin. each bit of this register corresponds to one pin of port n, and the input or output mo de can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of input/output mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) the pmcn register specifies the port mode or alternate function. each bit of this register corresponds to one pin of port n, and the mode of the por t can be specified in 1-bit units. port mode alternate function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w chapter 4 port functions user?s manual u17728ej3v1ud 99 (4) port n function control register (pfcn) the pfcn register specifies the alternat e function of a port pin to be used if the pin has two alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function (5) port n function control expansion register (pfcen) the pfcen register specifies the alte rnate function of a port pin to be used if the pin has three or more alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 chapter 4 port functions user?s manual u17728ej3v1ud 100 (6) port n function register (pfn) the pfn register specifies normal output or n-ch open-drain output. each bit of this register corresponds to one pin of por t n, and the output mode of the port pin can be specified in 1-bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 control of normal output/n-ch open-drain output pfn after reset: 00h r/w note the pfnm bit of the pfn register is valid only when the pmnm bit of the pmn register is 0 (when the output mode is specified) in port mode (pmcnm bit = 0). when the pmnm bit is 1 (when the input mode is specified), the set value of the pfn register is invalid. chapter 4 port functions user?s manual u17728ej3v1ud 101 (7) port setting set a port as illustrated below. figure 4-2. setting of each register and pin function pmcn register output mode input mode pmn register ?0? ?1? ?0? ?1? ?0? ?1? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark set the alternate functions in the following sequence. <1> set the pfcn and pfcen registers. <2> set the pfcn register. <3> set the intrn or intfn register (to specify an external interrupt pin). if the pmcn register is set first, an unintende d function may be set while the pfcn and pfcen registers are being set. chapter 4 port functions user?s manual u17728ej3v1ud 102 4.3.1 port 0 port 0 is a 5-bit port for which i/o settings can be controlled in 1-bit units. port 0 includes the following alternate-function pins. table 4-4. port 0 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p02 17 nmi input l-1 p03 18 intp0/adtrg input n-1 p04 19 intp1 input l-1 p05 20 intp2/drst note input aa-1 p06 21 intp3 input selectable as n-ch open-drain output l-1 note the drst pin is for on-chip debugging. if on-chip debugging is not used, fix the p05/intp2/ drst pin to low level between when the reset signal of the reset pin is released and when the ocdm.ocdm0 bit is cleared (0). for details, see 4.6.3 cautions on on-chip debug pins . caution the p02 to p06 pins have hysteresis characteris tics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. (1) port 0 register (p0) 0 outputs 0 outputs 1 p0n 0 1 output data control (in output mode) (n = 2 to 6) p0 p06 p05 p04 p03 p02 0 0 after reset: 00h (output latch) r/w address: fffff400h chapter 4 port functions user?s manual u17728ej3v1ud 103 (2) port 0 mode register (pm0) 1 output mode input mode pm0n 0 1 i/o mode control (n = 2 to 6) pm0 pm06 pm05 pm04 pm03 pm02 1 1 after reset: ffh r/w address: fffff420h (3) port 0 mode control register (pmc0) 0 pmc0 pmc06 pmc05 pmc04 pmc03 pmc02 0 0 i/o port intp3 input pmc06 0 1 specification of p06 pin operation mode i/o port intp2 input pmc05 0 1 specification of p05 pin operation mode i/o port intp1 input pmc04 0 1 specification of p04 pin operation mode i/o port intp0 input/adtrg input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode after reset: 00h r/w address: fffff440h caution the p05/intp2/drst pin becomes the drst pin regardless of the value of the pmc05 bit when the ocdm.ocdm0 bit = 1. chapter 4 port functions user?s manual u17728ej3v1ud 104 (4) port 0 function control register (pfc0) pfc0 after reset: 00h r/w address: fffff460h 0 0 0 0 pfc03 0 0 0 intp0 input adtrg input pfc03 0 1 specification of p03 pin alternate function (5) port 0 function register (pf0) 0 normal output (cmos output) n-ch open drain output pf0n 0 1 control of normal output or n-ch open-drain output (n = 2 to 6) pf0 pf06 pf05 pf04 pf03 pf02 0 0 after reset: 00h r/w address: fffffc60h caution when an output pin is pulled up at ev dd or higher, be sure to set the pf0n bit to 1. chapter 4 port functions user?s manual u17728ej3v1ud 105 4.3.2 port 1 port 1 is a 2-bit port for which i/o settings can be controlled in 1-bit units. port 1 includes the following alternate-function pins. table 4-5. port 1 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p10 3 ano0 output ? a-2 p11 4 ano1 output ? a-2 (1) port 1 register (p1) 0 outputs 0 outputs 1 p1n 0 1 output data control (in output mode) (n = 0, 1) p1 0 0 0 0 0 p11 p10 after reset: 00h (output latch) r/w address: fffff402h caution do not read/write the p1 register during d/a conversion (see 14.4.3 cautions). (2) port 1 mode register (pm1) 1 output mode input mode pm1n 0 1 i/o mode control (n = 0, 1) pm1 1 1 1 1 1 pm11 pm10 after reset: ffh r/w address: fffff422h cautions 1. when using p1n as the alternate functi on (anon pin output), set the pm1n bit to 1. 2. when using one of the p10 and p11 pins as an i/o port and the other as a d/a output pin, do so in an application wher e the port i/o level does not change during d/a output. chapter 4 port functions user?s manual u17728ej3v1ud 106 4.3.3 port 3 port 3 is a 10-bit port for which i/o settings can be controlled in 1-bit units. port 3 includes the following alternate-function pins. table 4-6. port 3 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p30 25 txda0/sob4 output g-3 p31 26 rxda0/intp7/sib4 input n-3 p32 27 ascka0/sckb4/tip00/top00 i/o u-1 p33 28 tip01/top01 i/o g-1 p34 29 tip10/top10 i/o g-1 p35 30 tip11/top11 i/o g-1 p36 31 ctxd0 note /ietx0 output g-3 p37 32 crxd0 note /ierx0 input g-4 p38 35 txda2/sda00 i/o g-12 p39 36 rxda2/scl00 i/o selectable as n-ch open-drain output g-6 note can controller version only caution the p31 to p35 and p37 to p39 pins have h ysteresis characteristics in the input mode of the alternate-function pin, but do not have the h ysteresis characteristics in the port mode. chapter 4 port functions user?s manual u17728ej3v1ud 107 (1) port 3 register (p3) outputs 0 outputs 1 p3n 0 1 output data control (in output mode) (n = 0 to 9) p3 (p3h) after reset: 0000h (output latch) r/w address: p3 fffff406h, p3l fffff406h, p3h fffff407h 0 0 0 0 0 0 p39 p38 p37 p36 p35 p34 p33 p32 p31 p30 8 9 10 11 12 13 14 15 (p3l) remarks 1. the p3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the p3 register as the p3h register and the lower 8 bits as the p3l register, p3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the p3h register. (2) port 3 mode register (pm3) 1 output mode input mode pm3n 0 1 i/o mode control (n = 0 to 9) 1 1 1 1 1 pm39 pm38 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: pm3 fffff426h, pm3l fffff426h, pm3h fffff427h 8 9 10 11 12 13 14 15 pm3 (pm3h) (pm3l) remarks 1. the pm3 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he pm3 register as the pm3h register and the lower 8 bits as the pm3l register, pm3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of t he pm3 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pm3h register. chapter 4 port functions user?s manual u17728ej3v1ud 108 (3) port 3 mode control register (pmc3) (1/2) i/o port rxda2 input/scl00 i/o pmc39 0 1 specification of p39 pin operation mode i/o port txda2 output/sda00 i/o pmc38 0 1 specification of p38 pin operation mode after reset: 0000h r/w address: pmc3 fffff446h, pmc3l fffff446h, pmc3h fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pmc3 (pmc3h) (pmc3l) chapter 4 port functions user?s manual u17728ej3v1ud 109 (2/2) i/o port tip11 input/top11 output pmc35 0 1 specification of p35 pin operation mode i/o port tip10 input/top10 output pmc34 0 1 specification of p34 pin operation mode i/o port crxd0 input/ierx0 input pmc37 0 1 specification of p37 pin operation mode i/o port ctxd0 output/ietx0 output pmc36 0 1 specification of p36 pin operation mode i/o port tip01 input/top01 output pmc33 0 1 specification of p33 pin operation mode i/o port ascka0 input/sckb4 i/o/tip00 input/top00 output pmc32 0 1 specification of p32 pin operation mode i/o port rxda0 input/sib4 input/intp7 input pmc31 0 1 specification of p31 pin operation mode i/o port txda0 output/sob4 output pmc30 0 1 specification of p30 pin operation mode remarks 1. the pmc3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmc3 register as the pmc3h register and the lower 8 bits as the pmc3l register, pmc3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc3h register. chapter 4 port functions user?s manual u17728ej3v1ud 110 (4) port 3 function control register (pfc3) after reset: 0000h r/w address: pfc3 fffff466h, pfc3l fffff466h, pfc3l fffff467h 0 0 0 0 0 0 pfc39 pfc38 pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfc3 (pfc3h) (pfc3l) remarks 1. for details of alternate function specification, see 4.3.3 (6) port 3 alternate function specifications . 2. the pfc3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc3 register as the pfc3h register and the lower 8 bits as the pfc3l register, pfc3 can be read or written in 8-bit and 1-bit units. 3. to read/write bits 8 to 15 of the pfc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc3h register. (5) port 3 function control ex pansion register l (pfce3l) pfce3l after reset: 00h r/w address: fffff706h 0 0 0 0 0 pfce32 0 0 remark for details of alternate function specification, see 4.3.3 (6) port 3 alternate function specifications . (6) port 3 alternate function specifications pfc39 specification of p39 pin alternate function 0 rxda2 input 1 scl00 input pfc38 specification of p38 pin alternate function 0 txda2 output 1 sda00 i/o chapter 4 port functions user?s manual u17728ej3v1ud 111 pfc37 specification of p37 pin alternate function 0 crxd0 input 1 ierx0 input pfc36 specification of p36 pin alternate function 0 ctxd0 output 1 ietx0 output pfc35 specification of p35 pin alternate function 0 tip11 input 1 top11 output pfc34 specification of p34 pin alternate function 0 tip10 input 1 top10 output pfc33 specification of p33 pin alternate function 0 tip01 input 1 top01 output pfce32 pfc32 specification of p32 pin alternate function 0 0 ascka0 input 0 1 sckb4 i/o 1 0 tip00 input 1 1 top00 output pfc31 specification of p31 pin alternate function 0 rxda0 input/intp7 note input 1 sib4 input pfc30 specification of p30 pin alternate function 0 txda0 output 1 sob4 output note the intp7 pin and rxda0 pin are alternate-function pins. when using the pin as the rxda0 pin, disable edge detection for the intp7 alternate-function pin. (clear the intf3.intf31 bit and the intr3.intr31 bit to 0.) when using the pin as th e intp7 pin, stop uarta0 reception. (clear the ua0ctl0.ua0rxe bit to 0.) chapter 4 port functions user?s manual u17728ej3v1ud 112 (7) port 3 function register (pf3) after reset: 0000h r/w address: pf3 fffffc66h, pf3l fffffc66h, pf3h fffffc67h pf37 pf36 pf35 pf34 pf33 pf32 pf31 pf30 0 0 0 0 0 0 pf39 pf38 8 9 10 11 12 13 14 15 normal output (cmos output) n-ch open-drain output pf3n 0 1 control of normal output or n-ch open-drain output (n = 0 to 9) pf3 (pf3h) (pf3l) caution when an output pin is pulled up at ev dd or higher, be sure to set the pf3n bit to 1. remarks 1. the pf3 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pf3 register as the pf3h register and the lower 8 bits as the pf3l register, pf3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of th e pf3 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pf3h register. chapter 4 port functions user?s manual u17728ej3v1ud 113 4.3.4 port 4 port 4 is a 3-bit port that controls i/o in 1-bit units. port 4 includes the following alternate-function pins. table 4-7. port 4 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p40 22 sib0/sda01 i/o g-6 p41 23 sob0/scl01 i/o g-12 p42 24 sckb0 i/o selectable as n-ch open-drain output e-3 caution the p40 to p42 pins have hysteresis characteri stics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. (1) port 4 register (p4) 0 outputs 0 outputs 1 p4n 0 1 output data control (in output mode) (n = 0 to 2) p4 0 0 0 0 p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h (2) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 i/o mode control (n = 0 to 2) pm4 1 1 1 1 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h chapter 4 port functions user?s manual u17728ej3v1ud 114 (3) port 4 mode control register (pmc4) 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 i/o port sckb0 i/o pmc42 0 1 specification of p42 pin operation mode i/o port sob0 output/scl01 i/o pmc41 0 1 specification of p41 pin operation mode i/o port sib0 input/sda01 i/o pmc40 0 1 specification of p40 pin operation mode after reset: 00h r/w address: fffff448h (4) port 4 function control register (pfc4) pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 sob0 output scl01 i/o pfc41 0 1 specification of p41 pin alternate function sib0 input sda01 i/o pfc40 0 1 specification of p40 pin alternate function chapter 4 port functions user?s manual u17728ej3v1ud 115 (5) port 4 function register (pf4) 0 normal output (cmos output) n-ch open-drain output pf4n 0 1 control of normal output or n-ch open-drain output (n = 0 to 2) pf4 0 0 0 0 pf42 pf41 pf40 after reset: 00h r/w address: fffffc68h caution when an output pin is pulled up at ev dd or higher, be sure to set the pf4n bit to 1. chapter 4 port functions user?s manual u17728ej3v1ud 116 4.3.5 port 5 port 5 is a 6-bit port that controls i/o in 1-bit units. port 5 includes the following alternate-function pins. table 4-8. port 5 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p50 37 tiq01/kr0/toq01/rtp00 i/o u-5 p51 38 tiq02/kr1/toq02/rtp01 i/o u-5 p52 39 tiq03/kr2/toq03/rtp02/ddi note i/o u-6 p53 40 sib2/kr3/tiq00/toq00/rtp03/ddo note i/o u-7 p54 41 sob2/kr4/rtp04/dck note i/o u-8 p55 42 sckb2/kr5/rtp05/dms note i/o selectable as n-ch open-drain output u-9 note the ddi, ddo, dck, and dms pins are for on-chip debugging. if on-chip debugging is not used, fix the p05/intp2/ drst pin to low level between when the reset signal of the reset pin is released and when the ocdm.ocdm0 bit is cleared (0). for details, see 4.6.3 cautions on on-chip debug pins . cautions 1. when the power is turned on, the p53 pin may mome ntarily output an undefined level. 2. the p50 to p55 pins have hysteresis characteristics in th e input mode of the alternate function, but do not have hysteresis characteristics in the port mode. (1) port 5 register (p5) 0 outputs 0 outputs 1 p5n 0 1 output data control (in output mode) (n = 0 to 5) p5 0 p55 p54 p53 p52 p51 p50 after reset: 00h (output latch) r/w address: fffff40ah chapter 4 port functions user?s manual u17728ej3v1ud 117 (2) port 5 mode register (pm5) 1 output mode input mode pm5n 0 1 i/o mode control (n = 0 to 5) pm5 1 pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah (3) port 5 mode control register (pmc5) 0 pmc5 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 i/o port sckb2 i/o/kr5 input/rtp05 output pmc55 0 1 specification of p55 pin operation mode i/o port sob2 output/kr4 input/rtp04 output pmc54 0 1 specification of p54 pin operation mode i/o port sib2 input/kr3 input/tiq00 input/toq00 output/rtp03 output pmc53 0 1 specification of p53 pin operation mode i/o port tiq03 input/kr2 input/toq03 output/rtp02 output pmc52 0 1 specification of p52 pin operation mode i/o port tiq02 input/kr1 input/toq02 output/rtp01 output pmc51 0 1 specification of p51 pin operation mode i/o port tiq01 input/kr0 input/toq01 output/rtp00 output pmc50 0 1 specification of p50 pin operation mode after reset: 00h r/w address: fffff44ah chapter 4 port functions user?s manual u17728ej3v1ud 118 (4) port 5 function control register (pfc5) 0 pfc5 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 after reset: 00h r/w address: fffff46ah remark for details of alternate function specification, see 4.3.5 (6) port 5 alternate function specifications . (5) port 5 function control expansion register (pfce5) 0 pfce5 0 pfce55 pfce54 pfce53 pfce52 pfce51 pfce50 after reset: 00h r/w address: fffff70ah remark for details of alternate function specification, see 4.3.5 (6) port 5 alternate function specifications . (6) port 5 alternate function specifications pfce55 pfc55 specification of p55 pin alternate function 0 0 sckb2 i/o 0 1 kr5 input 1 0 setting prohibited 1 1 rtp05 output pfce54 pfc54 specification of p54 pin alternate function 0 0 sob2 output 0 1 kr4 input 1 0 setting prohibited 1 1 rtp04 output pfce53 pfc53 specification of p53 pin alternate function 0 0 sib2 input 0 1 tiq00 input/kr3 note input 1 0 toq00 output 1 1 rtp03 output chapter 4 port functions user?s manual u17728ej3v1ud 119 pfce52 pfc52 specification of p52 pin alternate function 0 0 setting prohibited 0 1 tiq03 input/kr2 note input 1 0 toq03 input 1 1 rtp02 output pfce51 pfc51 specification of p51 pin alternate function 0 0 setting prohibited 0 1 tiq02 input/kr1 note input 1 0 toq02 output 1 1 rtp01 output pfce50 pfc50 specification of p50 pin alternate function 0 0 setting prohibited 0 1 tiq01 input/kr0 note input 1 0 toq01 output 1 1 rtp00 output note the krn pin and tiq0m pin are alternate-function pins. when using the pin as the tiq0m pin, disable krn pin key return detection, which is the al ternate function. (clear the krm.krmn bit to 0.) also, when using the pin as the krn pin, disable tiq0m pin edge detection, which is the alternate function (n = 0 to 3, m = 0 to 3). pin name use as tiq0m pin use as krn pin kr0/tiq01 krm.krm0 bit = 0 tq0ioc1. tq0tig2, tq0ioc1. tq0tig3 bits = 0 kr1/tiq02 krm.krm1 bit = 0 tq0ioc1.tq0tig4, tq0ioc1.tq0tig5 bits = 0 kr2/tiq03 krm.krm2 bit = 0 tq0ioc1.tq0tig6, tq0ioc1.tq0tig7 bits = 0 kr3/tiq00 krm.krm3 bit = 0 tq0ioc1.tq0tig0, tq0ioc1.tq0tig1 bits = 0 tq0ioc2.tq0ees0, tq0ioc2.tq0ees1 bits = 0 tq0ioc2.tq0ets0, tq0ioc2.tq0ets1 bits = 0 (7) port 5 function register (pf5) 0 normal output (cmos output) n-ch open-drain output pf5n 0 1 control of normal output or n-ch open-drain output (n = 0 to 5) pf5 0 pf55 pf54 pf53 pf52 pf51 pf50 after reset: 00h r/w address: fffffc6ah caution when an output pin is pulled up at ev dd or higher, be sure to set the pf5n bit to 1. chapter 4 port functions user?s manual u17728ej3v1ud 120 4.3.6 port 7 port 7 is a 12-bit port for which i/o settings can be controlled in 1-bit units. port 7 includes the following alternate-function pins. table 4-9. port 7 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p70 100 ani0 input a-1 p71 99 ani1 input a-1 p72 98 ani2 input a-1 p73 97 ani3 input a-1 p74 96 ani4 input a-1 p77 95 ani5 input a-1 p76 94 ani6 input a-1 p77 93 ani7 input a-1 p78 92 ani8 input a-1 p79 91 ani9 input a-1 p710 90 ani10 input a-1 p711 89 ani11 input ? a-1 chapter 4 port functions user?s manual u17728ej3v1ud 121 (1) port 7 register h, port 7 register l (p7h, p7l) outputs 0 outputs 1 p7n 0 1 output data control (in output mode) (n = 0 to 11) p7h p7l after reset: 00h (output latch) r/w address: p7l fffff40eh, p7h fffff40fh p77 p76 p75 p74 p73 p72 p71 p70 0 0 0 0 p711 p710 p79 p78 caution do not read/write the p7h and p7l re gisters during a/d conversion (see 13.6 (4) alternate i/o). remark these registers cannot be accessed in 16-bit units as the p7 register. they can be read or written in 8-bit or 1-bit units as the p7h and p7l registers. (2) port 7 mode register h, port 7 mode register l (pm7h, pm7l) 1 output mode input mode pm7n 0 1 i/o mode control (n = 0 to 11) pm7h pm7l 1 1 1 pm711 pm710 pm79 pm78 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 after reset: ffh r/w address: pm7l fffff42eh, pm7h fffff42fh caution when using the p7n pin as its alternate function (anin pin), set the pm7n bit to 1. remark these registers cannot be accessed in 16-bit units as the pm7 register. they can be read or written in 8-bit or 1-bit units as the pm7h and pm7l registers. chapter 4 port functions user?s manual u17728ej3v1ud 122 4.3.7 port 9 port 9 is a 16-bit port for which i/o settings can be controlled in 1-bit units. port 9 includes the following alternate-function pins. table 4-10. port 9 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p90 43 a0/kr6/txda1/sda02 i/o u-10 p91 44 a1/kr7/rxda1/scl02 i/o u-11 p92 45 a2/tip41/top41 i/o u-12 p93 46 a3/tip40/top40 i/o u-12 p94 47 a4/tip31/top31 i/o u-12 p95 48 a5/tip30/top30 i/o u-12 p96 49 a6/tip21/top21 i/o u-13 p97 50 a7/sib1/tip20/top20 i/o u-14 p98 51 a8/sob1 output g-3 p99 52 a9/sckb1 i/o g-5 p910 53 a10/sib3 i/o g-2 p911 54 a11/sob3 output g-3 p912 55 a12/sckb3 i/o g-5 p913 56 a13/intp4 i/o n-2 p914 57 a14/intp5/tip51/top51 i/o u-15 p915 58 a15/intp6/tip50/top50 i/o selectable as n-ch open-drain output u-15 caution the p90 to p97, p99, p910, and p912 to p 915 pins have hysteresis char acteristics in the input mode of the alternate-function pin, but do not ha ve the hysteresis characteristics in the port mode. chapter 4 port functions user?s manual u17728ej3v1ud 123 (1) port 9 register (p9) p915 outputs 0 outputs 1 p9n 0 1 output data control (in output mode) (n = 0 to 15) p914 p913 p912 p911 p910 p99 p98 after reset: 0000h (output latch) r/w address: p9 fffff412h, p9l fffff412h, p9h fffff413h p97 p96 p95 p94 p93 p92 p91 p90 8 9 10 11 12 13 14 15 p9 (p9h) (p9l) remarks 1. the p9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the p9 register as the p9h register and the lower 8 bits as the p9l register, p9 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the p9h register. (2) port 9 mode register (pm9) pm97 output mode input mode pm9n 0 1 i/o mode control (n = 0 to 15) pm96 pm95 pm94 pm93 pm92 pm91 pm90 after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h pm915 pm914 pm913 pm912 pm911 pm910 pm99 pm98 8 9 10 11 12 13 14 15 pm9 (pm9h) (pm9l) remarks 1. the pm9 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he pm9 register as the pm9h register and the lower 8 bits as the pm9l register, pm9 can be read or written in 8-bit and 1-bit units. 2. to read/write bits 8 to 15 of t he pm9 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pm9h register. chapter 4 port functions user?s manual u17728ej3v1ud 124 (3) port 9 mode control register (pmc9) (1/2) i/o port a15 output/intp6 input/tip50 input/top50 output pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 i/o port a14 output/intp5 input/tip51 input/top51 output pmc914 0 1 specification of p914 pin operation mode i/o port a11 output/sob3 output pmc911 0 1 specification of p911 pin operation mode i/o port a10 output/sib3 input pmc910 0 1 specification of p910 pin operation mode i/o port a9 output/sckb1 i/o pmc99 0 1 specification of p99 pin operation mode i/o port a13 output/intp4 input pmc913 0 1 specification of p913 pin operation mode i/o port a12 output/sckb3 i/o pmc912 0 1 specification of p912 pin operation mode 8 9 10 11 12 13 14 15 pmc9 (pmc9h) (pmc9l) remarks 1. the pmc9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmc9 register as the pmc9h register and the lower 8 bits as the pmc9l register, pmc9 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc9h register. chapter 4 port functions user?s manual u17728ej3v1ud 125 (2/2) i/o port a8 output/sob1 output pmc98 0 1 specification of p98 pin operation mode i/o port a7 output/sib1 input/tip20 input/top20 output pmc97 0 1 specification of p97 pin operation mode i/o port a6 output/tip21 input/top21 output pmc96 0 1 specification of p96 pin operation mode i/o port a5 output/tip30 input/top30 output pmc95 0 1 specification of p95 pin operation mode i/o port a4 output/tip31 input/top31 output pmc94 0 1 specification of p94 pin operation mode i/o port a3 output/tip40 input/top40 output pmc93 0 1 specification of p93 pin operation mode i/o port a2 output/tip41 input/top41 output pmc92 0 1 specification of p92 pin operation mode i/o port a1 output/kr7 input/rxda1 input/scl02 i/o pmc91 0 1 specification of p91 pin operation mode i/o port a0 output/kr6 input/txda1 output/sda02 i/o pmc90 0 1 specification of p90 pin operation mode caution port 9 pins cannot be used as port pins or other alternate-function pins if even one of the a0 to a15 pins is used in the separate bus mode. after setting the pfc9 and pfce9 registers to 0000h, therefore, set all 16 bits of the pmc9 register to ffffh at once. if even one of the a0 to a15 pins is not used in the separate bus mode, port 9 pins can be used as port pins or other alternate-function pins. chapter 4 port functions user?s manual u17728ej3v1ud 126 (4) port 9 function control register (pfc9) caution port 9 pins cannot be used as port pins or ot her alternate-function pins if even one of the a0 to a15 pins is used in the separate bus mode . after setting the pfc9 and pfce9 registers to 0000h, therefore, set all 16 bits of the pmc9 regi ster to ffffh at once. if even one of the a0 to a15 pins is not used in the separate bus m ode, port 9 pins can be used as port pins or other alternate-function pins. after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 8 9 10 11 12 13 14 15 pfc9 (pfc9h) (pfc9l) remarks 1. for details of alternate function specification, see 4.3.7 (6) port 9 alternate function specifications . 2. the pfc9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc9 register as the pfc9h register and the lower 8 bits as the pfc9l register, pfc9 c an be read or written in 8-bit or 1-bit units. 3. to read/write bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc9h register. (5) port 9 function control expansion register (pfce9) after reset: 0000h r/w address: pfce9 fffff712h, pfce9l fffff712h, pfce9h fffff713h pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 pfce915 pfce914 0 0 0 0 0 0 8 9 10 11 12 13 14 15 pfce9 (pfce9h) (pfce9l) remarks 1. for details of alternate function specification, see 4.3.7 (6) port 9 alternate function specifications . 2. the pfce9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfce9 register as the pfce9h register and the lower 8 bits as the pfce9l register, pf ce9 can be read or written in 8-bit or 1- bit units. 3. to read/write bits 8 to 15 of t he pfce9 register in 8-bit or 1- bit units, specify them as bits 0 to 7 of the pfce9h register. chapter 4 port functions user?s manual u17728ej3v1ud 127 (6) port 9 alternate function specifications pfce915 pfc915 specification of p915 pin alternate function 0 0 a15 output 0 1 intp6 input 1 0 tip50 input 1 1 top50 output pfce914 pfc914 specification of p914 pin alternate function 0 0 a14 output 0 1 intp5 input 1 0 tip51 input 1 1 top51 output pfc913 specification of p913 pin alternate function 0 a13 output 1 intp4 input pfc912 specification of p912 pin alternate function 0 a12 output 1 sckb3 i/o pfc911 specification of p911 pin alternate function 0 a11 output 1 sob3 output pfc910 specification of p910 pin alternate function 0 a10 output 1 sib3 input pfc99 specification of p99 pin alternate function 0 a9 output 1 sckb1 i/o pfc98 specification of p98 pin alternate function 0 a8 output 1 sob1 output pfce97 pfc97 specification of p97 pin alternate function 0 0 a7 output 0 1 sib1 input 1 0 tip20 input 1 1 top20 output chapter 4 port functions user?s manual u17728ej3v1ud 128 pfce96 pfc96 specification of p96 pin alternate function 0 0 a6 output 0 1 setting prohibited 1 0 tip21 input 1 1 top21 output pfce95 pfc95 specification of p95 pin alternate function 0 0 a5 output 0 1 tip30 input 1 0 top30 output 1 1 setting prohibited pfce94 pfc94 specification of p94 pin alternate function 0 0 a4 output 0 1 tip31 input 1 0 top31 output 1 1 setting prohibited pfce93 pfc93 specification of p93 pin alternate function 0 0 a3 output 0 1 tip40 input 1 0 top40 output 1 1 setting prohibited pfce92 pfc92 specification of p92 pin alternate function 0 0 a2 output 0 1 tip41 input 1 0 top41 output 1 1 setting prohibited pfce91 pfc91 specification of p91 pin alternate function 0 0 a1 output 0 1 kr7 input 1 0 rxda1 input/kr7 input note 1 1 scl02 i/o pfce90 pfc90 specification of p90 pin alternate function 0 0 a0 output 0 1 kr6 input 1 0 txda1 output 1 1 sda02 i/o note the rxda1 and kr7 pins must not be used at the same time. when us ing the rxda1 pin, do not use the kr7 pin. when using the kr7 pin, do not use the rx da1 pin (it is recommended to set the pfc91 bit to 1 and clear the pfce91 bit to 0). chapter 4 port functions user?s manual u17728ej3v1ud 129 (7) port 9 function register (pf9) after reset: 0000h r/w address: pf3 fffffc72h, pf9l fffffc72h, pf9h fffffc73h pf97 pf96 pf95 pf94 pf93 pf92 pf91 pf90 pf915 pf914 pf913 pf912 pf911 pf910 pf99 pf98 normal output (cmos output) n-ch open-drain output pf9n 0 1 control of normal output or n-ch open-drain output (n = 0 to 15) 8 9 10 11 12 13 14 15 pf9 (pf9h) (pf9l) caution when an output pin is pulled up at ev dd or higher, be sure to set the pf9n bit to 1. remarks 1. the pf9 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pf9 register as the pf9h register and the lower 8 bits as the pf9l register, pf9 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of th e pf9 register in 8-bit or 1-bi t units, specify them as bits 0 to 7 of the pf9h register. chapter 4 port functions user?s manual u17728ej3v1ud 130 4.3.8 port cm port cm is a 4-bit port for which i/o setti ngs can be controlled in 1-bit units. port cm includes the following alternate-function pins. table 4-11. port cm alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pcm0 61 wait input d-1 pcm1 62 clkout output d-2 pcm2 63 hldak output d-2 pcm3 64 hldrq input ? d-1 (1) port cm register (pcm) 0 outputs 0 outputs 1 pcmn 0 1 output data control (in output mode) (n = 0 to 3) pcm 0 0 0 pcm3 pcm2 pcm1 pcm0 after reset: 00h (output latch) r/w address: fffff00ch (2) port cm mode register (pmcm) 1 output mode input mode pmcmn 0 1 i/o mode control (n = 0 to 3) pmcm 1 1 1 pmcm3 pmcm2 pmcm1 pmcm0 after reset: ffh r/w address: fffff02ch chapter 4 port functions user?s manual u17728ej3v1ud 131 (3) port cm mode control register (pmccm) 0 pmccm 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 i/o port hldrq input pmccm3 0 1 specification of pcm3 pin operation mode i/o port hldak output pmccm2 0 1 specification of pcm2 pin operation mode i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode i/o port wait input pmccm0 0 1 specification of pcm0 pin operation mode after reset: 00h r/w address: fffff04ch chapter 4 port functions user?s manual u17728ej3v1ud 132 4.3.9 port ct port ct is a 4-bit port for which i/o setti ngs can be controlled in 1-bit units. port ct includes the following alternate-function pins. table 4-12. port ct alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pct0 65 wr0 output d-2 pct1 66 wr1 output d-2 pct4 67 rd output d-2 pct6 68 astb output ? d-2 (1) port ct register (pct) 0 outputs 0 outputs 1 pctn 0 1 output data control (in output mode) (n = 0, 1, 4, 6) pct pct6 0 pct4 0 0 pct1 pct0 after reset: 00h (output latch) r/w address: fffff00ah (2) port ct mode register (pmct) 1 output mode input mode pmctn 0 1 i/o mode control (n = 0, 1, 4, 6) pmct pmct6 1 pmct4 1 1 pmct1 pmct0 after reset: ffh r/w address: fffff02ah chapter 4 port functions user?s manual u17728ej3v1ud 133 (3) port ct mode control register (pmcct) 0 pmcct pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 i/o port astb output pmcct6 0 1 specification of pct6 pin operation mode i/o port rd output pmcct4 0 1 specification of pct4 pin operation mode i/o port wr1 output pmcct1 0 1 specification of pct1 pin operation mode i/o port wr0 output pmcct0 0 1 specification of pct0 pin operation mode after reset: 00h r/w address: fffff04ah chapter 4 port functions user?s manual u17728ej3v1ud 134 4.3.10 port dh port dh is a 6-bit port for which i/o settings can be controlled in 1-bit units. port dh includes the following alternate-function pins. table 4-13. port dh alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pdh0 87 a16 output d-2 pdh1 88 a17 output d-2 pdh2 59 a18 output d-2 pdh3 60 a19 output d-2 pdh4 6 a20 output d-2 pdh5 7 a21 output ? d-2 (1) port dh register (pdh) outputs 0 outputs 1 pdhn 0 1 output data control (in output mode) (n = 0 to 5) pdh after reset: 00h (output latch) r/w address: fffff006h 0 0 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 (2) port dh mode register (pmdh) 1 output mode input mode pmdhn 0 1 i/o mode control (n = 0 to 5) 1 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh chapter 4 port functions user?s manual u17728ej3v1ud 135 (3) port dh mode control register (pmcdh) i/o port am output (address bus output) (m = 16 to 21) pmcdhn 0 1 specification of pdhn pin operation mode (n = 0 to 5) 0 0 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h pmcdh chapter 4 port functions user?s manual u17728ej3v1ud 136 4.3.11 port dl port dl is a 16-bit port for which i/o se ttings can be controll ed in 1-bit units. port dl includes the following alternate-function pins. table 4-14. port dl alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pdl0 71 ad0 i/o d-3 pdl1 72 ad1 i/o d-3 pdl2 73 ad2 i/o d-3 pdl3 74 ad3 i/o d-3 pdl4 75 ad4 i/o d-3 pdl5 76 ad5/flmd1 note i/o d-3 pdl6 77 ad6 i/o d-3 pdl7 78 ad7 i/o d-3 pdl8 79 ad8 i/o d-3 pdldl 80 ad9 i/o d-3 pdl10 81 ad10 i/o d-3 pdl11 82 ad11 i/o d-3 pdl12 83 ad12 i/o d-3 pdl13 84 ad13 i/o d-3 pdl14 85 ad14 i/o d-3 pdl15 86 ad15 i/o ? d-3 note since this pin is set in the flash memory progra mming mode, it does not need to be manipulated with the port control register. for details, see chapter 30 flash memory . chapter 4 port functions user?s manual u17728ej3v1ud 137 (1) port dl register (pdl) pdl15 outputs 0 outputs 1 pdln 0 1 output data control (in output mode) (n = 0 to 15) pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 after reset: 0000h (output latch) r/w address: pdl fffff004h, pdll fffff004h, pdlh fffff005h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 pdl (pdlh) (pdll) remarks 1. the pdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pdl register as the pdlh register and the lower 8 bits as the pdll register, pdl can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of t he pdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pdlh register. (2) port dl mode register (pmdl) pmdl7 output mode input mode pmdln 0 1 i/o mode control (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: pmdl fffff024h, pmdll fffff024h, pmdlh fffff025h pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 pmdl (pmdlh) (pmdll) remarks 1. the pmdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmdl register as the pmdlh register and the lower 8 bits as the pmdll register, pmdl can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmdlh register. chapter 4 port functions user?s manual u17728ej3v1ud 138 (3) port dl mode control register (pmcdl) i/o port adn i/o (address/data bus i/o) pmcdln 0 1 specification of pdln pin operation mode (n = 0 to 15) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 after reset: 0000h r/w address: pmcdl fffff044h, pmcdll fffff044h, pmcdlh fffff045h pmcdl15 pmcdl14pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 pmcdl (pmcdlh) (pmcdll) caution when the smsel bit of the eximc regist er = 1 (separate mode) and the bs30 to bs00 bits of the bsc register = 0 (8-bit bus width ), do not specify the ad8 to ad15 pins. remarks 1. the pmcdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmcdl register as the pmcdlh register and the lower 8 bits as the pmcdll register, pmcdl can be read or written in 8-bit or 1- bit units. 2. to read/write bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcdlh register. chapter 4 port functions user?s manual u17728ej3v1ud 139 4.4 block diagrams figure 4-3. block diagram of type a-1 address rd a/d input signal wr pm pmmn wr port pmn pmn p-ch n-ch internal bus selector selector chapter 4 port functions user?s manual u17728ej3v1ud 140 figure 4-4. block diagram of type a-2 rd d/a output signal wr pm pmmn wr port pmn pmn p-ch n-ch internal bus selector selector address chapter 4 port functions user?s manual u17728ej3v1ud 141 figure 4-5. block diagram of type d-1 wr port pmn wr pm pmmn wr pmc pmcmn rd input signal when alternate function is used pmn internal bus selector selector address chapter 4 port functions user?s manual u17728ej3v1ud 142 figure 4-6. block diagram of type d-2 wr port pmn wr pm pmmn wr pmc pmcmn rd output signal when alternate function is used pmn internal bus selector selector selector address chapter 4 port functions user?s manual u17728ej3v1ud 143 figure 4-7. block diagram of type d-3 wr port pmn wr pm pmmn wr pmc pmcmn rd pmn output signal when alternate function is used input signal when alternate function is used output enable signal of address/data bus input enable signal of address/data bus output buffer off signal internal bus selector selector selector selector address chapter 4 port functions user?s manual u17728ej3v1ud 144 figure 4-8. block diagram of type e-3 rd wr port pmn wr pmc pmcmn wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch output signal when alternate function is used output enable signal when alternate function is used input signal when alternate function is used note internal bus selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 145 figure 4-9. block diagram of type g-1 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal when alternate function is used pmn ev dd ev ss p-ch n-ch note internal bus selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 146 figure 4-10. block diagram of type g-2 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal when alternate function is used pmn ev dd ev ss p-ch n-ch note internal bus selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 147 figure 4-11. block diagram of type g-3 output signal 2 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch internal bus selector selector selector selector address chapter 4 port functions user?s manual u17728ej3v1ud 148 figure 4-12. block diagram of type g-4 rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used input signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch note internal bus selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 149 figure 4-13. block diagram of type g-5 rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch input signal when alternate function is used note internal bus selector selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 150 figure 4-14. block diagram of type g-6 output signal when alternate function is used input signal 1 when alternate function is used input signal 2 when alternate function is used note internal bus selector selector selector selector address rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 151 figure 4-15. block diagram of type g-12 input signal when alternate function is used output signal 1 when alternate function is used output signal 2 when alternate function is used note internal bus selector address rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch selector selector selector note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 152 figure 4-16. block diagram of type l-1 input signal 1 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch edge detection noise elimination note 2 internal bus selector selector address notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 153 figure 4-17. block diagram of type n-1 input signal 1 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn input signal 2 when alternate function is used ev dd ev ss p-ch n-ch edge detection noise elimination note 2 internal bus selector selector selector address notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 154 figure 4-18. block diagram of type n-2 internal bus address input signal when alternate function is used selector selector selector rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn ev dd ev ss p-ch n-ch edge detection noise elimination note 2 output signal when alternate function is used notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 155 figure 4-19. block diagram of type n-3 input signal 1-1 when alternate function is used input signal 1-2 when alternate function is used input signal 2 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn ev dd ev ss p-ch n-ch note 2 internal bus selector selector selector address edge detection noise elimination notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 156 figure 4-20. block diagram of type u-1 input signal 2 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 1 when alternate function is used input signal 3 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 157 figure 4-21. block diagram of type u-5 input signal 1-1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 1-2 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 158 figure 4-22. block diagram of type u-6 input signal 1-1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 1-2 when alternate function is used input signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 159 figure 4-23. block diagram of type u-7 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 2-1 when alternate function is used input signal 2-2 when alternate function is used output signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 160 figure 4-24. block diagram of type u-8 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 161 figure 4-25. block diagram of type u-9 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used input signal when on-chip debugging output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 162 figure 4-26. block diagram of type u-10 internal bus address input signal 1 when alternate function is used selector selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used output signal 2 when alternate function is used output signal 3 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn noise elimination note selector note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 163 figure 4-27. block diagram of type u-11 internal bus address input signal 1 when alternate function is used selector selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 3 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn input signal 2 when alternate function is used ev dd ev ss p-ch n-ch wr pfce pfcemn noise elimination note selector note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 164 figure 4-28. block diagram of type u-12 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 165 figure 4-29. block diagram of type u-13 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 166 figure 4-30. block diagram of type u-14 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address selector note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 167 figure 4-31. block diagram of type u-15 input signal 1 when alternate function is used input signal 2 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn wr pfce pfcemn pmmn pmn ev dd ev ss p-ch n-ch output signal 2 when alternate function is used output signal 1 when alternate function is used note 2 internal bus selector selector selector selector address edge detection noise elimination selector notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 168 figure 4-32. block diagram of type aa-1 rd wr port pmn wr intf intfmn note 1 wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch n-ch wr intr intrmn note 1 ev ss input signal when on-chip debugging external reset signal input signal when alternate function is used note 2 internal bus selector selector address edge detection noise elimination notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u17728ej3v1ud 169 4.5 port register settings when alternate function is used table 4-15 shows the port register settings when each port is used for an alternate function. when using a port pin as an alternate-function pin, refer to the description of each pin. chapter 4 port functions user?s manual u17728ej3v1ud 170 table 4-15. using port pin as alternate-function pin (1/7) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) p02 = setting not required p03 = setting not required p03 = setting not required p04 = setting not required p05 = setting not required p05 = setting not required p06 = setting not required p10 = setting not required p11 = setting not required p30 = setting not required p30 = setting not required p31 = setting not required p31 = setting not required p31 = setting not required p32 = setting not required p32 = setting not required p32 = setting not required p32 = setting not required p33 = setting not required p33 = setting not required p34 = setting not required p34 = setting not required p35 = setting not required p35 = setting not required p02 p03 p04 p05 p06 p10 p11 p30 p31 p32 p33 p34 p35 nmi intp0 adtrg intp1 intp2 drst intp3 ano0 ano1 txda0 sob4 rxda0 intp7 sib4 ascka0 sckb4 tip00 top00 tip01 top01 tip10 top10 tip11 top11 input input input input input input input output output output output input input input input i/o input output input output input output input output ocdm0 (ocdm) = 1 pm02 = setting not required pm03 = setting not required pm03 = setting not required pm04 = setting not required pm05 = setting not required pm05 = setting not required pm06 = setting not required pm10 = 1 pm11 = 1 pm30 = setting not required pm30 = setting not required pm31 = setting not required pm31 = setting not required pm31 = setting not required pm32 = setting not required pm32 = setting not required pm32 = setting not required pm32 = setting not required pm33 = setting not required pm33 = setting not required pm34 = setting not required pm34 = setting not required pm35 = setting not required pm35 = setting not required ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmc02 = 1 pmc03 = 1 pmc03 = 1 pmc04 = 1 pmc05 = 1 pmc05 = setting not required pmc06 = 1 pmc30 = 1 pmc30 = 1 pmc31 = 1 pmc31 = 1 pmc31 = 1 pmc32 = 1 pmc32 = 1 pmc32 = 1 pmc32 = 1 pmc33 = 1 pmc33 = 1 pmc34 = 1 pmc34 = 1 pmc35 = 1 pmc35 = 1 pfc03 = 0 pfc03 = 1 pfc30 = 0 pfc30 = 1 note , pfc31 = 0 note , pfc31 = 0 pfc31 = 1 pfc32 = 0 pfc32 = 1 pfc32 = 0 pfc32 = 1 pfc33 = 0 pfc33 = 1 pfc34 = 0 pfc34 = 1 pfc35 = 0 pfc35 = 1 ? ? ? ? ? ? ? ? ? pfce32 = 0 pfce32 = 0 pfce32 = 1 pfce32 = 1 note the intp7 pin and rxda0 pin are alternate-function pins. when using the pin as the rxda0 pin, disable edge detection for the alternate-function intp7 pin (clear the intf3.intf31 bit and intr3.intr31 bit to 0). when us ing the pin as the intp7 pin, stop the uarta0 reception ope ration (clear the ua0ctl0.ua0rxe bit to 0). caution when using one of the p10 and p11 pins as an i/o port a nd the other as a d/a output pin (ano0, ano1), do so in an appli cation where the port i/o level does not change during d/a output. chapter 4 port functions user?s manual u17728ej3v1ud 171 table 4-15. using port pin as alternate-function pin (2/7) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? p36 p37 p38 p39 p40 p41 p42 p50 p51 ctxd0 note ietx0 crxd0 note ierx0 txda2 sda00 rxda2 scl00 sib0 sda01 sob0 scl01 sckb0 tiq01 kr0 toq01 rtp00 tiq02 kr1 toq02 rtp01 p36 = setting not required p36 = setting not required p37 = setting not required p37 = setting not required p38 = setting not required p38 = setting not required p39 = setting not required p39 = setting not required p40 = setting not required p40 = setting not required p41 = setting not required p41 = setting not required p42 = setting not required p50 = setting not required p50 = setting not required p50 = setting not required p50 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required pm36 = setting not required pm36 = setting not required pm37 = setting not required pm37 = setting not required pm38 = setting not required pm38 = setting not required pm39 = setting not required pm39 = setting not required pm40 = setting not required pm40 = setting not required pm41 = setting not required pm41 = setting not required pm42 = setting not required pm50 = setting not required pm50 = setting not required pm50 = setting not required pm50 = setting not required pm51 = setting not required pm51 = setting not required pm51 = setting not required pm51 = setting not required pmc36 = 1 pmc36 = 1 pmc37 = 1 pmc37 = 1 pmc38 = 1 pmc38 = 1 pmc39 = 1 pmc39 = 1 pmc40 = 1 pmc40 = 1 pmc41 = 1 pmc41 = 1 pmc42 = 1 pmc50 = 1 pmc50 = 1 pmc50 = 1 pmc50 = 1 pmc51 = 1 pmc51 = 1 pmc51 = 1 pmc51 = 1 pfc36 = 0 pfc36 = 1 pfc37 = 0 pfc37 = 1 pfc38 = 0 pfc38 = 1 pfc39 = 0 pfc39 = 1 pfc40 = 0 pfc40 = 1 pfc41 = 0 pfc41 = 1 pfc50 = 1 pfc50 = 1 pfc50 = 0 pfc50 = 1 pfc51 = 1 pfc51 = 1 pfc51 = 0 pfc51 = 1 output output input input output i/o input i/o input i/o output i/o i/o input input output output input input output output pfce50 = 0 pfce50 = 0 pfce50 = 1 pfce50 = 1 pfce51 = 0 pfce51 = 0 pfce51 = 1 pfce51 = 1 krm0 (krm) = 0 tq0tig2, tq0tig3 (tq0ioc1) = 0 krm1 (krm) = 0 tq0tig4, tq0tig5 (tq0ioc1) = 0 ? note can controller versions only chapter 4 port functions user?s manual u17728ej3v1ud 172 table 4-15. using port pin as alternate-function pin (3/7) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) input input output output input input input input input output output output input output input i/o input output input p52 p53 p54 p55 tiq03 kr2 toq03 rtp02 ddi sib2 tiq00 kr3 toq00 rtp03 ddo sob2 kr4 rtp04 dck sckb2 kr5 rtp05 dms p52 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p54 = setting not required p54 = setting not required p54 = setting not required p54 = setting not required p55 = setting not required p55 = setting not required p55 = setting not required p55 = setting not required pm52 = setting not required pm52 = setting not required pm52 = setting not required pm52 = setting not required pm52 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm54 = setting not required pm54 = setting not required pm54 = setting not required pm54 = setting not required pm55 = setting not required pm55 = setting not required pm55 = setting not required pm55 = setting not required pmc52 = 1 pmc52 = 1 pmc52 = 1 pmc52 = 1 pmc52 = setting not required pmc53 = 1 pmc53 = 1 pmc53 = 1 pmc53 = 1 pmc53 = 1 pmc53 = setting not required pmc54 = 1 pmc54 = 1 pmc54 = 1 pmc54 = setting not required pmc55 = 1 pmc55 = 1 pmc55 = 1 pmc55 = setting not required pfce52 = 0 pfce52 = 0 pfce52 = 1 pfce52 = 1 pfce52 = setting not required pfce53 = 0 pfce53 = 0 pfce53 = 0 pfce53 = 1 pfce53 = 1 pfce53 = setting not required pfce54 = 0 pfce54 = 0 pfce54 = 1 pfce54 = setting not required pfce55 = 0 pfce55 = 0 pfce55 = 1 pfce55 = setting not required pfc52 = 1 pfc52 = 1 pfc52 = 0 pfc52 = 1 pfc52 = setting not required pfc53 = 0 pfc53 = 1 pfc53 = 1 pfc53 = 0 pfc53 = 1 pfc53 = setting not required pfc54 = 0 pfc54 = 1 pfc54 = 1 pfc54 = setting not required pfc55 = 0 pfc55 = 1 pfc55 = 1 pfc55 = setting not required krm2 (krm) = 0 tq0tig6, tq0tig7 (tq0i0c1) = 0 ocdm0 (ocdm) = 1 krm3 (krm) = 0 tq0tig0, tq0tig1 (tq0ioc1) = 0, tq0ees0, tq0ees1 (tq0ioc2) = 0, tq0ets0, tq0ets1 (tq0ioc2) = 0 ocdm0 (ocdm) = 1 ocdm0 (ocdm) = 1 ocdm0 (ocdm) = 1 chapter 4 port functions user?s manual u17728ej3v1ud 173 table 4-15. using port pin as alternate-function pin (4/7) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? note 1 note 1 input input input input input input input input input input input input output input output i/o output input input i/o p70 p71 p72 p73 p74 p75 p76 p77 p78 p79 p710 p711 p90 p91 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 a0 kr6 txda1 sda02 a1 kr7 rxda1/kr7 note 2 scl02 p70 = setting not required p71 = setting not required p72 = setting not required p73 = setting not required p74 = setting not required p75 = setting not required p76 = setting not required p77 = setting not required p78 = setting not required p79 = setting not required p710 = setting not required p711 = setting not required p90 = setting not required p90 = setting not required p90 = setting not required p90 = setting not required p91 = setting not required p91 = setting not required p91 = setting not required p91 = setting not required pm70 = 1 pm71 = 1 pm72 = 1 pm73 = 1 pm74 = 1 pm75 = 1 pm76 = 1 pm77 = 1 pm78 = 1 pm79 = 1 pm710 = 1 pm711 = 1 pm90 = setting not required pm90 = setting not required pm90 = setting not required pm90 = setting not required pm91 = setting not required pm91 = setting not required pm91 = setting not required pm91 = setting not required pmc90 = 1 pmc90 = 1 pmc90 = 1 pmc90 = 1 pmc91 = 1 pmc91 = 1 pmc91 = 1 pmc91 = 1 pfce90 = 0 pfce90 = 0 pfce90 = 1 pfce90 = 1 pfce91 = 0 pfce91 = 0 pfce91 = 1 pfce91 = 1 pfc90 = 0 pfc90 = 1 pfc90 = 0 pfc90 = 1 pfc91 = 0 pfc91 = 1 pfc91 = 0 pfc91 = 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? notes 1. port 9 pins cannot be used as port pins or other alternate-func tion pins if even one of the a0 to a15 pins is used in the sepa rate bus mode. after setting the pfc9 and pfce9 registers to 0000h, th erefore, set all 16 bits of the pmc9 register to ffffh at once. 2. the rxda1 and kr7 pins must not be used at the same time. when using the rxda1 pin, do not use the kr7 pin. when using the kr 7 pin, do not use the rxda1 pin (it is recommended to set the pf c91 bit to 1 and clear the pfce91 bit to 0). chapter 4 port functions user?s manual u17728ej3v1ud 174 table 4-15. using port pin as alternate-function pin (5/7) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) note note note note note note note note output input output output input output output input output output input output output input output output input input output output output output i/o p92 p93 p94 p95 p96 p97 p98 p99 a2 tip41 top41 a3 tip40 top40 a4 tip31 top31 a5 tip30 top30 a6 tip21 top21 a7 sib1 tip20 top20 a8 sob1 a9 sckb1 p92 = setting not required p92 = setting not required p92 = setting not required p93 = setting not required p93 = setting not required p93 = setting not required p94 = setting not required p94 = setting not required p94 = setting not required p95 = setting not required p95 = setting not required p95 = setting not required p96 = setting not required p96 = setting not required p96 = setting not required p97 = setting not required p97 = setting not required p97 = setting not required p97 = setting not required p98 = setting not required p98 = setting not required p99 = setting not required p99 = setting not required pm92 = setting not required pm92 = setting not required pm92 = setting not required pm93 = setting not required pm93 = setting not required pm93 = setting not required pm94 = setting not required pm94 = setting not required pm94 = setting not required pm95 = setting not required pm95 = setting not required pm95 = setting not required pm96 = setting not required pm96 = setting not required pm96 = setting not required pm97 = setting not required pm97 = setting not required pm97 = setting not required pm97 = setting not required pm98 = setting not required pm98 = setting not required pm99 = setting not required pm99 = setting not required pmc92 = 1 pmc92 = 1 pmc92 = 1 pmc93 = 1 pmc93 = 1 pmc93 = 1 pmc94 = 1 pmc94 = 1 pmc94 = 1 pmc95 = 1 pmc95 = 1 pmc95 = 1 pmc96 = 1 pmc96 = 1 pmc96 = 1 pmc97 = 1 pmc97 = 1 pmc97 = 1 pmc97 = 1 pmc98 = 1 pmc98 = 1 pmc99 = 1 pmc99 = 1 pfce92 = 0 pfce92 = 0 pfce92 = 1 pfce93 = 0 pfce93 = 0 pfce93 = 1 pfce94 = 0 pfce94 = 0 pfce94 = 1 pfce95 = 0 pfce95 = 0 pfce95 = 1 pfce96 = 0 pfce96 = 1 pfce96 = 1 pfce97 = 0 pfce97 = 0 pfce97 = 1 pfce97 = 1 ? ? ? ? pfc92 = 0 pfc92 = 1 pfc92 = 0 pfc93 = 0 pfc93 = 1 pfc93 = 0 pfc94 = 0 pfc94 = 1 pfc94 = 0 pfc95 = 0 pfc95 = 1 pfc95 = 0 pfc96 = 0 pfc96 = 0 pfc96 = 1 pfc97 = 0 pfc97 = 1 pfc97 = 0 pfc97 = 1 pfc98 = 0 pfc98 = 1 pfc99 = 0 pfc99 = 1 note port 9 pins cannot be used as port pins or other alternate-function pins if even one of the a0 to a15 pins is used in the sepa rate bus mode. after setting the pfc9 and pfce9 registers to 0000h, therefore, set all 16 bits of the pmc9 register to ffffh at once. chapter 4 port functions user?s manual u17728ej3v1ud 175 table 4-15. using port pin as alternate-function pin (6/7) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) output input output output output i/o output input output input input output output input input output input output output input output output output output p910 p911 p912 p913 p914 p915 pcm0 pcm1 pcm2 pcm3 pct0 pct1 pct4 pct6 a10 sib3 a11 sob3 a12 sckb3 a13 intp4 a14 intp5 tip51 top51 a15 intp6 tip50 top50 wait clkout hldak hldrq wr0 wr1 rd astb p910 = setting not required p910 = setting not required p911 = setting not required p911 = setting not required p912 = setting not required p912 = setting not required p913 = setting not required p913 = setting not required p914 = setting not required p914 = setting not required p914 = setting not required p914 = setting not required p915 = setting not required p915 = setting not required p915 = setting not required p915 = setting not required pcm0 = setting not required pcm1 = setting not required pcm2 = setting not required pcm3 = setting not required pct0 = setting not required pct1 = setting not required pct4 = setting not required pct6 = setting not required pm910 = setting not required pm910 = setting not required pm911 = setting not required pm911 = setting not required pm912 = setting not required pm912 = setting not required pm913 = setting not required pm913 = setting not required pm914 = setting not required pm914 = setting not required pm914 = setting not required pm914 = setting not required pm915 = setting not required pm915 = setting not required pm915 = setting not required pm915 = setting not required pmcm0 = setting not required pmcm1 = setting not required pmcm2 = setting not required pmcm3 = setting not required pmct0 = setting not required pmct1 = setting not required pmct4 = setting not required pmct6 = setting not required pmc910 = 1 pmc910 = 1 pmc911 = 1 pmc911 = 1 pmc912 = 1 pmc912 = 1 pmc913 = 1 pmc913 = 1 pmc914 = 1 pmc914 = 1 pmc914 = 1 pmc914 = 1 pmc915 = 1 pmc915 = 1 pmc915 = 1 pmc915 = 1 pmccm0 = 1 pmccm1 = 1 pmccm2 = 1 pmccm3 = 1 pmcct0 = 1 pmcct1 = 1 pmcct4 = 1 pmcct6 = 1 pfce914 = 0 pfce914 = 0 pfce914 = 1 pfce914 = 1 pfce915 = 0 pfce915 = 0 pfce915 = 1 pfce915 = 1 pfc910 = 0 pfc910 = 1 pfc911 = 0 pfc911 = 1 pfc912 = 0 pfc912 = 1 pfc913 = 0 pfc913 = 1 pfc914 = 0 pfc914 = 1 pfc914 = 0 pfc914 = 1 pfc915 = 0 pfc915 = 1 pfc915 = 0 pfc915 = 1 note note note note note note ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? note port 9 pins cannot be used as port pins or other alternate-functi on pins if even one of the a0 to a15 pins is used in the sepa rate bus mode. after setting the pfc9 and pfce9 registers to 0000h, therefore, set all 16 bits of the pmc9 register to ffffh at once. chapter 4 port functions user?s manual u17728ej3v1ud 176 table 4-15. using port pin as alternate-function pin (7/7) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? output output output output output output i/o i/o i/o i/o i/o i/o input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o pdh0 pdh1 pdh2 pdh3 pdh4 pdh5 pdl0 pdl1 pdl2 pdl3 pdl4 pdl5 pdl6 pdl7 pdl8 pdl9 pdl10 pdl11 pdl12 pdl13 pdl14 pdl15 a16 a17 a18 a19 a20 a21 ad0 ad1 ad2 ad3 ad4 ad5 flmd1 note ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 pdh0 = setting not required pdh1 = setting not required pdh2 = setting not required pdh3 = setting not required pdh4 = setting not required pdh5 = setting not required pdl0 = setting not required pdl1 = setting not required pdl2 = setting not required pdl3 = setting not required pdl4 = setting not required pdl5 = setting not required pdl5 = setting not required pdl6 = setting not required pdl7 = setting not required pdl8 = setting not required pdl9 = setting not required pdl10 = setting not required pdl11 = setting not required pdl12 = setting not required pdl13 = setting not required pdl14 = setting not required pdl15 = setting not required pmdh0 = setting not required pmdh1 = setting not required pmdh2 = setting not required pmdh3 = setting not required pmdh4 = setting not required pmdh5 = setting not required pmdl0 = setting not required pmdl1 = setting not required pmdl2 = setting not required pmdl3 = setting not required pmdl4 = setting not required pmdl5 = setting not required pmdl5 = setting not required pmdl6 = setting not required pmdl7 = setting not required pmdl8 = setting not required pmdl9 = setting not required pmdl10 = setting not required pmdl11 = setting not required pmdl12 = setting not required pmdl13 = setting not required pmdl14 = setting not required pmdl15 = setting not required pmcdh0 = 1 pmcdh1 = 1 pmcdh2 = 1 pmcdh3 = 1 pmcdh4 = 1 pmcdh5 = 1 pmcdl0 = 1 pmcdl1 = 1 pmcdl2 = 1 pmcdl3 = 1 pmcdl4 = 1 pmcdl5 = 1 pmcdl5 = setting not required pmcdl6 = 1 pmcdl7 = 1 pmcdl8 = 1 pmcdl9 = 1 pmcdl10 = 1 pmcdl11 = 1 pmcdl12 = 1 pmcdl13 = 1 pmcdl14 = 1 pmcdl15 = 1 note since this pin is set in the flash memory programming mode, it does not need to be manipulated using the port control register . for details, see chapter 30 flash memory . chapter 4 port functions user?s manual u17728ej3v1ud 177 4.6 cautions 4.6.1 cautions on setting port pins (1) in the v850es/sg3, the general-pur pose port function and several periphera l function i/o pin share a pin. to switch between the genera l-purpose port (port mode) an d the peripheral function i/o pin (alternate-function mode), set by the pmcn register. in regards to this register setting sequence, note with caution the following. (a) cautions on switching from por t mode to alternate-function mode to switch from the port mode to alternat e-function mode in the following order. <1> set the pfn register note : n-ch open-drain setting <2> set the pfcn and pfcen regist ers: alternate-function selection <3> set the corresponding bit of the pmcn regist er to 1: switch to alternate-function mode if the pmcn register is set first, not e with caution that, at that moment or depending on the change of the pin states in accordance with the setting of the pf n, pfcn, and pfcen register s, unexpected operations may occur. a concrete example is shown as example below. note n-ch open-drain output pin only caution regardless of the port mo de/alternate-function mode, the pn register is read and written as follows. ? pn register read: read the port output latc h value (when pmn.pmnm bit = 0), or read the pin states (pmn.pmnm bit = 1). ? pn register write: write to the port output latch [example] scl01 pin setting example the scl01 pin is used alternately with the p41/ sob0 pin. select the valid pin functions with the pmc4, pfc4, and pf4 registers. pmc41 bit pfc41 bit pf41 bit valid pin functions 0 don?t care 1 p41 (in output port mode, n-ch open-drain output) 0 1 sob0 output (n-ch open-drain output) 1 1 1 scl01 i/o (n-ch open-drain output) chapter 4 port functions user?s manual u17728ej3v1ud 178 the order of setting in which malfunction ma y occur on switching from the p41 pin to the scl01 pin are shown below. setting order setting contents pin states pin level <1> initial value (pmc41 bit = 0, pfc41 bit = 0, pf41 bit = 0) port mode (input) hi-z <2> pmc41 bit 1 sob0 output low level (high level depending on the csib0 setting) <3> pfc41 bit 1 scl01 i/o high level (cmos output) <4> pf41 bit 1 scl01 i/o hi-z (n-ch open-drain output) in <2>, i 2 c communication may be affected since the alternate-function sob0 output is output to the pin. in the cmos output period of <2 > or <3>, unnecessary current may be generated. (b) cautions on alternate-function mode (input) the input signal to the alternate-function block is low level when the pmcn.pmcnm bit is 0 due to the and output of the pmcn register set value and the pin le vel. thus, depending on the port setting and alternate- function operation enable timing, unexpected operations may occur. therefore, switch between the port mode and alternate-function m ode in the following sequence. ? to switch from port mode to alternate-function mode (input) set the pins to the alternate-function mode usi ng the pmcn register and then enable the alternate- function operation. ? to switch from alternate-function mode (input) to port mode stop the alternate-function operation and then switch the pins to the port mode. the concrete examples are show n as example 1 and example 2. [example 1] switch from general-purpose por t (p02) to external interrupt pin (nmi) when the p02/nmi pin is pulled up as shown in figure 4-33 and the rising edge is specified in the nmi pin edge detection setting, even though hi gh level is input continuously to the nmi pin during switching from the p02 pin to the an nmi pin (pmc02 bit = 0 1), this is detected as a rising edge as if the low level changed to high level, and an nmi interrupt occurs. to avoid it, set the nmi pin?s valid edge after switching from the p02 pin to the nmi pin. chapter 4 port functions user?s manual u17728ej3v1ud 179 figure 4-33. example of switching from p02 to nmi (incorrect) pmc0 nmi interrupt occurrence 76543 2 p02/nmi 3 v 10 0 10 00 pmc0m bit = 0: port mode pmc0m bit = 1: alternate-function mode rising edge detector pmc02 bit = 0: low level pmc02 bit = 1: high level remark m = 2 to 6 [example 2] switch from external pin (nmi) to general-purpose port (p02) when the p02/nmi pin is pulled up as shown in figure 4-34 and the falling edge is specified in the nmi pin edge detection setting, even though hi gh level is input continuously to the nmi pin at switching from the nmi pin to the p02 pin (pmc02 bit = 1 0), this is detected as falling edge as if high level changed to low level, and nmi interrupt occurs. to avoid this, set the nmi pin edge detection as ?no edge detected? before switching to the p02 pin. figure 4-34. example of switching from nmi to p02 (incorrect) pmc0 76543 2 p02/nmi 3 v 10 nmi interrupt occurrence 1 0 pmc0m bit = 0: port mode pmc0m bit = 1: alternate-function mode falling edge detector pmc02 bit = 1: high level pmc02 bit = 0: low level 0 00 remark m = 2 to 6 (2) in port mode, the pfn.pfnm bit is valid only in t he output mode (pmn.pmnm bit = 0). in the input mode (pmnm bit = 1), the value of the pfnm bit is not reflected in the buffer. chapter 4 port functions user?s manual u17728ej3v1ud 180 4.6.2 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. chapter 4 port functions user?s manual u17728ej3v1ud 181 4.6.3 cautions on on-chip debug pins the drst, dck, dms, ddi, and ddo pins are on-chip debug pins. after reset by the reset pin, the p05/intp2/drst pin is in itialized to function as an on-chip debug pin (drst). if a high level is input to the drst pin at this time, the on-chip debug mode is set, and the dck, dms, ddi, and ddo pins can be used. the following action must be taken if on-chip debugging is not used. ? clear the ocdm0 bit of the ocdm register (special register) (0) at this time, fix the p05/intp2/drst pin to low level from when reset by the reset pin is released until the above action is taken. if a high level is input to the drst pin before the above ac tion is taken, it may cause a malfunction (cpu deadlock). handle the p05 pin with the utmost care. caution the p05/intp2/drst pin is not initialized to function as an on-chip debug pin (drst) when a reset signal (wdt2res) is generated due to a watc hdog timer overflow, a reset signal (lvires) is generated by the low-voltage detector (lvi), or a reset signal (clmres) is generated by the clock monitor (clm). the ocdm register holds the current value. 4.6.4 cautions on p05/intp2/drst pin the p05/intp2/drst pin has an internal pull-down resistor (30 k typ.). after a reset by the reset pin, a pull- down resistor is connected. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0). 4.6.5 cautions on p53 pin when power is turned on when the power is turned on, the following pins may momentarily output an undefined level. ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo pin 4.6.6 hysteresis characteristics in port mode, the following port pins do not have hysteresis characteristics. p02 to p06 p31 to p35, p37 to p39 p40 to p42 p50 to p55 p90 to p97, p99, p910, p912 to p915 4.6.7 cautions on separate bus mode port 9 pins cannot be used as port pins or other alternate-function pins if even one of the a0 to a15 pins is used in the separate bus mode. after setting the pfc9 and pfce9 registers to 0000h, ther efore, set all 16 bits of the pmc9 register to ffffh at once. if even on e of the a0 to a15 pins is not used in the separate bus mode, port 9 pins can be used as port pins or other alternate-function pins. user?s manual u17728ej3v1ud 182 chapter 5 bus control function the v850es/sg3 is provided with an external bus interface function by which external memories such as rom and ram, and i/o can be connected. 5.1 features output is selectable from a multiplexed bus with a mi nimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles. 8-bit/16-bit data bus selectable wait function ? programmable wait function of up to 7 states ? external wait function using wait pin idle state function bus hold function up to 4 mb of physical memory connectable the bus can be controlled at a voltage that is different from the operating voltage when bv dd ev dd = v dd . however, in separate bus mode or when the a20 and a21 pins are used, set bv dd = ev dd = v dd . chapter 5 bus control function user?s manual u17728ej3v1ud 183 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins (multiplexed bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus a16 to a21 pdh0 to pdh5 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control table 5-2. external control pins (separate bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o data bus a0 to a15 p90 to p915 output address bus a16 to a21 pdh0 to pdh5 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal hldrq pcm3 input hldak pcm2 output bus hold control 5.2.1 pin status when internal rom, intern al ram, or on-chip peripheral i/o is accessed when the internal rom, internal ram, or on-chip peripheral i/o are accessed, the status of each pin is as follows. table 5-3. pin statuses when internal rom, in ternal ram, or on-chip peripheral i/o is accessed separate bus mode multiplexed bus mode address bus (a21 to a0) undefined a ddress bus (a21 to a16) undefined data bus (ad15 to ad0) hi-z address/data bus (ad15 to ad0) undefined control signal (rd, wr0, wr1) high level control signal (rd, wr0, wr1, astb) high level caution when a write access is perfo rmed to the internal rom area, address, data, and control signals are activated in the same way as acce ss to the external memory area. 5.2.2 pin status in each operation mode for the pin status of the v850 es/sg3 in each operation mode, see 2.2 pin status . chapter 5 bus control function user?s manual u17728ej3v1ud 184 5.3 memory block function the 16 mb external memory space is divided into memory blocks of (lower) 2 mb, 2 mb, 4 mb, and 8 mb. the programmable wait function and bus cycl e operation mode for each of these bloc ks can be independen tly controlled in one-block units. figure 5-1. data memory map: physical address (80 kb) use prohibited memory block 3 (8 mb) internal rom area note 4 (1 mb) external memory area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) memory block 2 (4 mb) memory block 1 (2 mb) memory block 0 (2 mb) 03ffffffh 03fec000h 03febfffh 01000000h 00ffffffh 00800000h 007fffffh 00400000h 003fffffh 00200000h 001fffffh 00000000h 03ffffffh 03fff000h 03ffefffh 001fffffh 00100000h 000fffffh 00000000h use prohibited note 1 03ff0000h 03feffffh programmable peripheral i/o area note 2 or use prohibited note 3 03fef000h 03feefffh 03fec000h notes 1. use of addresses 03fef000h to 03feffffh is prohibited because these addresses are in the same area as the on-chip peripheral i/o area. 2. only the programmable peripheral i/o area is s een as images of 256 mb each in the 4 gb address space. 3. addresses 03fec000h to 03fec5ffh are alloca ted to addresses 03fec000h to 03feefffh of the can controller version as a programmable per ipheral i/o area. use of these addresses in a version without a can controller is prohibited. 4. this area is an external memory area in the case of a data write access. chapter 5 bus control function user?s manual u17728ej3v1ud 185 5.4 external bus interface mode control function the v850es/sg3 has the following two external bus interface modes. ? multiplexed bus mode ? separate bus mode these two modes can be selected by using the eximc register. (1) external bus interface mode control register (eximc) the eximc register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 multiplexed bus mode separate bus mode smsel 0 1 mode selection eximc 0 0 0 0 0 0 smsel after reset: 00h r/w address: ffffffbeh caution set the eximc register fr om the internal rom or internal ram area before making an external access. after setting the eximc register, be sure to insert a nop instruction. chapter 5 bus control function user?s manual u17728ej3v1ud 186 5.5 bus access 5.5.1 number of clocks for access the following table shows the number of basic clocks required for accessing each resource. area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 note 1 3 + n note 2 instruction fetch (branch) 2 2 note 1 3 + n note 2 operand data access 3 1 3 + n note 2 notes 1. increases by 1 if a conflict with a data access occurs. 2. 2 + n clocks (n: number of wait states ) when the separate bus mode is selected. remark unit: clocks/access 5.5.2 bus size setting function each external memory area selected by memory block n can be set by using the bsc register. however, the bus size can be set to 8 bits and 16 bits only. the external memory area of the v850es/sg3 is selected by memory blocks 0 to 3. (1) bus size configuration register (bsc) the bsc register can be read or written in 16-bit units. reset input sets this register to 5555h. caution write to the bsc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the bsc register are complete. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits bsc 1 bs30 0 0 1 bs20 0 0 1 bs10 0 0 1 bs00 8 9 10 11 12 13 data bus width of m emory block n space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block 2 memory block 1 caution be sure to set bits 14, 12, 10, and 8 to ?1?, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to ?0?. chapter 5 bus control function user?s manual u17728ej3v1ud 187 5.5.3 access by bus size the v850es/sg3 accesses the on-chip peripheral i/o and extern al memory in 8-bit, 16-bit, or 32-bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is described below. all data is accessed starting from the lower side. the v850es/sg3 supports only the little-endian format. figure 5-2. little-endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) data space the v850es/sg3 has an address misalign function. with this function, data can be placed at all addresse s, regardless of the format of the data (word data or halfword data). however, if the word data or halfwor d data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (a) halfword-length data access a byte-length bus cycle is generated twice if t he least significant bit of the address is 1. (b) word-length data access (i) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) a halfword-length bus cycle is generated twic e if the lower 2 bits of the address are 10. chapter 5 bus control function user?s manual u17728ej3v1ud 188 (2) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus chapter 5 bus control function user?s manual u17728ej3v1ud 189 (3) halfword access (16 bits) (a) with 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus first access second access 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 halfword data external data bus 2n address halfword data external data bus address 2n + 1 (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus first access second access 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus chapter 5 bus control function user?s manual u17728ej3v1ud 190 (4) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u17728ej3v1ud 191 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u17728ej3v1ud 192 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u17728ej3v1ud 193 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access word data external data bus address word data external data bus address word data external data bus address word data external data bus address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u17728ej3v1ud 194 5.6 wait function 5.6.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each memory block space. the number of wait states can be pr ogrammed by using the dwc0 register . immediately after system reset, 7 data wait states are inserted for all the blocks. the dwc0 register can be read or written in 16-bit units. reset input sets this register to 7777h. cautions 1. the internal rom and internal ram areas are not subj ect to programmable wait, and are always accessed without a wait state. the on- chip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, and then do not change the set values. also, do not access an external memory area until the in itial settings of the dwc0 register are complete. 3. when v850es/sg3 is used in separate bus mode an d operated at f xx > 20 mhz, be sure to insert one or more wait. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 none f xx 20 mhz f xx > 20 mhz setting prohibited multiplexed bus separate bus dwc0 dw32 dw12 dw31 dw11 dw30 dw10 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 number of wait states inserted in memory block n space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block 2 memory block 1 caution be sure to clear bits 15, 11, 7, and 3 to ?0?. chapter 5 bus control function user?s manual u17728ej3v1ud 195 5.6.2 external wait function to synchronize an extremely slow external memory, i/o, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). when the pcm0 pin is set to alternate function, the external wait function is enabled. access to each area of the internal rom, internal ram, a nd on-chip peripheral i/o is not subject to control by the external wait function, in the same man ner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle in the multiplexed bus mode. in the separate bus mode, it is sampled at the rising edge of the clock immediately after the t1 and tw states of the bus cycle. if the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. chapter 5 bus control function user?s manual u17728ej3v1ud 196 5.6.3 relationship between programm able wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specifi ed by the set value of the programmable wait and the wait cycles controlled by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the programmable wait and the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-3. inserting wait example (a) multiplexed bus clkout t1 t2 tw tw tw t3 wait pin wait via wait pin programmable wait wait control (b) separate bus t1 tw tw tw t2 clkout wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. chapter 5 bus control function user?s manual u17728ej3v1ud 197 5.6.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be set by using the awc register. address wait insertion is set for each memory block area (memory blocks 0 to 3). if an address setup wait is inserted, it seem s that the high-clock period of the t1 state is extended by 1 clock. if an address hold wait is inserted, it seems that the low-cl ock period of the t1 state is extended by 1 clock. (1) address wait control register (awc) the awc register can be read or written in 16-bit units. reset input sets this register to ffffh. cautions 1. address setup wait and address hold wait cycles are not inserted when the internal rom area, internal ram area, and on-ch ip peripheral i/o areas are accessed. 2. write to the awc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the awc register are complete. 3. when v850es/sg3 is operated at f xx > 20 mhz, be sure to insert the address hold wait and the address setup wait. after reset: ffffh r/w address: fffff488h 1 ahw3 awc 1 asw3 1 ahw2 1 asw2 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted setting prohibited inserted specifies insertion of address setup wait (n = 0 to 3) memory block 0 memory block 3 memory block 2 memory block 1 f xx 20 mhz f xx > 20 mhz ahwn 0 1 not inserted inserted setting prohibited inserted specifies insertion of address hold wait (n = 0 to 3) f xx 20 mhz f xx > 20 mhz caution be sure to set bits 15 to 8 to ?1?. chapter 5 bus control function user?s manual u17728ej3v1ud 198 5.7 idle state insertion function to facilitate interfacing with low-speed memories, one idle state (ti) can be inserted afte r the t3 state in the bus cycle that is executed for each space selected by the memory block in the multiplex address/data bus mode. in the separate bus mode, one idle state (ti) can be inserted after t he t2 state. by inserting an idle state, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access). whether the idle state is to be inserted c an be programmed by using the bcc register. an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control register (bcc) the bcc register can be read or written in 16-bit units. reset input sets this register to aaaah. cautions 1. the internal rom, internal ram, a nd on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the bcc register are complete. after reset: aaaah r/w address: fffff48ah 1 bc31 bcn1 0 1 not inserted i nserted bcc 0 0 1 bc21 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block 2 memory block 1 caution be sure to set bits 15, 13, 11, and 9 to ?1?, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to ?0?. chapter 5 bus control function user?s manual u17728ej3v1ud 199 5.8 bus hold function 5.8.1 functional outline the hldrq and hldak functions are valid if the pc m2 and pcm3 pins are set to alternate function. when the hldrq pin is asserted (low level), indicating th at another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status ). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in the internal rom and internal ram is continued until an on-chip peripheral i/o register or t he external memory is accessed. the bus hold status is indicated by a ssertion of the hldak pin (low level). the bus hold function enables the configuration of mult i-processor type systems in which two or more bus masters exist. note that the bus hold request is not acknowledged during a multiple-acce ss cycle initiated by the bus sizing function or a bit manipulation instruction. status data bus width access type timing at which bus hold request is not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ? ? between read access and write access chapter 5 bus control function user?s manual u17728ej3v1ud 200 5.8.2 bus hold procedure the bus hold status transition procedure is shown below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.8.3 operation in power save mode because the internal system clock is stopped in the stop , idle1, and idle2 modes, t he bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asserted, and the bus hold status is entered. when the hldrq pin is later deasserted, the hldak pin is also deasserted, and the bus hold status is cleared. chapter 5 bus control function user?s manual u17728ej3v1ud 201 5.9 bus priority bus hold, dma transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. bus hold has the highest priority, followed by dma transfer, operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-4. bus priority priority external bus cycle bus master bus hold external device dma transfer dmac operand data access cpu instruction fetch (branch) cpu high low instruction fetch (successive) cpu chapter 5 bus control function user?s manual u17728ej3v1ud 202 5.10 bus timing figure 5-4. multiplexed bus read timing (bus size: 16 bits, 16-bit access) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a21 to a16 astb wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-5. multiplexed bus r ead timing (bus size: 8 bits) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a21 to a16, ad15 to ad8 astb wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function user?s manual u17728ej3v1ud 203 figure 5-6. multiplexed bus write timi ng (bus size: 16 bits, 16-bit access) a1 11 00 11 11 00 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a21 to a16 astb wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active figure 5-7. multiplexed bus wr ite timing (bus size: 8 bits) a1 11 10 11 11 10 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a21 to a16, ad15 to ad8 astb wait ad7 to ad0 wr1, wr0 chapter 5 bus control function user?s manual u17728ej3v1ud 204 figure 5-8. multiplexed bus hold timing (bus si ze: 16 bits, 16-bit access) t1 a1 undefined a1 a2 t2 t3 ti note th th th th ti note t1 t2 t3 d1 clkout hldrq hldak a21 to a16 astb ad15 to ad0 rd undefined undefined undefined a2 d2 note this idle state (ti) does not de pend on the bcc register settings. remarks 1. see table 2-2 for the pin statuses in the bus hold mode. 2. the broken lines indicate high impedance. chapter 5 bus control function user?s manual u17728ej3v1ud 205 figure 5-9. separate bus read timi ng (bus size: 16 bits, 16-bit access) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a21 to a0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-10. separate bus r ead timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a21 to a0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function user?s manual u17728ej3v1ud 206 figure 5-11. separate bus write timi ng (bus size: 16 bits, 16-bit access) t1 a1 11 00 00 00 11 11 11 11 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a21 to a0 wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active remark the broken lines indicate high impedance. figure 5-12. separate bus writ e timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a21 to a0 wait ad7 to ad0 wr1, wr0 11 10 10 10 11 11 11 11 remark the broken lines indicate high impedance. chapter 5 bus control function user?s manual u17728ej3v1ud 207 figure 5-13. separate bus hold ti ming (bus size: 8 bits, write) clkout t1 t2 a1 d1 d2 undefined a2 undefined 11 11 10 d3 a3 t1 t2 th ti note ti note th th th t1 t2 hldrq hldak a21 to a0 ad7 to ad0 wr1, wr0 11 10 11 10 11 note this idle state (ti) does not de pend on the bcc register settings. remark the broken lines indicate high impedance. figure 5-14. address wait timing (separate bus read, bus size: 16 bits, 16-bit access) tasw t1 tahw t2 clkout astb a21 to a0 wait ad15 to ad0 rd d1 a1 t1 t2 clkout astb a21 to a0 wait ad15 to ad0 rd d1 a1 remarks 1. tasw (address setup wait): image of hi gh-level width of t1 state expanded. 2. tahw (address hold wait): image of lo w-level width of t1 state expanded. 3. the broken lines indicate high impedance. user?s manual u17728ej3v1ud 208 chapter 6 clock generation function 6.1 overview the following clock generation functions are available. { main clock oscillator ? in clock-through mode f x = 2.5 to 10 mhz (f xx = 2.5 to 10 mhz) ? in pll mode f x = 2.5 to 5 mhz ( 4: f xx = 10 to 20 mhz) f x = 2.5 to 4 mhz ( 8: f xx = 20 to 32 mhz) { subclock oscillator ? f xt =32.768 khz { multiply ( 4/ 8) function by pll (phase locked loop) ? clock-through mode/pll mode selectable { internal oscillator ? f r = 220 khz (typ.) { internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) { peripheral clock generation { clock output function remark f x : main clock oscillation frequency f xx : main clock frequency f xt : subclock frequency f r : internal oscillation clock frequency chapter 6 clock generation function user?s manual u17728ej3v1ud 209 6.2 configuration figure 6-1. clock generator selector selector note frc bit mfrc bit mck bit ck2 to ck0 bits selpll bit pllon bit cls, ck3 bits stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock watch timer clock timer m clock watch timer clock, watchdog timer 2 clock peripheral clock, watchdog timer 2 clock watchdog timer 2 clock, timer m clock internal system clock prescaler 3 main clock oscillator main clock oscillator stop control rstp bit internal oscillator 1/8 divider xt1 xt2 clkout x1 x2 idle mode pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1,024 can controller f can f brg = f x /2 to f x /2 12 f xt f xt f xx f x f r f r /8 idle control selector selector note the internal oscillation clock is selected when t he watchdog timer 2 overflows during the oscillation stabilization time. remark f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f brg : watch timer clock frequency f r : internal oscillation clock frequency f can : can clock frequency chapter 6 clock generation function user?s manual u17728ej3v1ud 210 (1) main clock oscillator the main resonator oscillates the following frequencies (f x ). ? in clock-through mode f x = 2.5 to 10 mhz ? in pll mode f x = 2.5 to 5 mhz ( 4) f x = 2.5 to 4 mhz ( 8) (2) subclock oscillator the sub-resonator oscillates a frequency of 32.768 khz (f xt ). (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscillator is stopped in the stop mode or when the pcc.mck bit = 1 (valid only when the pcc.cls bit = 1). (4) internal oscillator oscillates a frequency (f r ) of 220 khz (typ.). (5) prescaler 1 this prescaler generates the clock (f xx to f xx /1,024) to be supplied to the follo wing on-chip peripheral functions: tmp0 to tmp5, tmq0, tmm0, csib0 to csib4, uarta0 to uarta2, i 2 c00 to i 2 c02, adc, wdt2, can0 note and iebus. note can controller version only (6) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, rom correction, rom, and ram blocks, and can be output from the clkout pin. (7) prescaler 3 this circuit divides the clock generated by the main clock oscillator (f x ) to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. for details, see chapter 10 watch timer functions . (8) pll this circuit multiplies the clock generated by the main clock oscillator (f x ) by 4 or 8. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be sele cted by using the pllctl.selpll bit. whether the clock is multiplied by 4 or 8 is selected by the ckc.ckdi v0 bit, and pll is started or stopped by the pllctl.pllon bit. chapter 6 clock generation function user?s manual u17728ej3v1ud 211 6.3 registers (1) processor clock control register (pcc) the pcc register is a special register. data can be wr itten to this register only in combination of specific sequences (see 3.4.8 special registers ). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 03h. chapter 6 clock generation function user?s manual u17728ej3v1ud 212 frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 main clock oscillator control used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w address: fffff828h main clock operation subclock operation cls note 0 1 status of cpu clock (f cpu ) < > < > < > f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 even if the mck bit is set (1) while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. before setting the mck bit from 0 to 1, stop the on-chip peripheral functions operating with the main clock. when the main clock is stopped and the device is operating with the subclock, clear (0) the mck bit and secure the oscillation stabilization time by software before switching the cpu clock to the main clock or operating the on-chip peripheral functions. ? ? ? note the cls bit is a read-only bit. cautions 1. do not change the cpu clock (by using the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation instruction to ma nipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. remark : don?t care chapter 6 clock generation function user?s manual u17728ej3v1ud 213 (a) example of setting main clock operation subclock operation <1> ck3 bit 1: use of a bit manipulation instructi on is recommended. do not change the ck2 to ck0 bits. <2> subclock operation: read the cls bit to check if subclock operation has started. it takes the following time after the ck3 bit is se t until subclock operation is started. max.: 1/f xt (1/subclock frequency) <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. cautions 1. when stopping the ma in clock, stop the pll. also stop the operations of the on-chip peripheral functions operati ng with the main clock. 2. if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied, then change to the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 remark internal system clock (f clk ): clock generated from the main clock (f xx ) by setting bits ck2 to ck0 [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit 1 <2> _check_cls : tst1 4, pcc[r0] -- wait until subclock operation starts. bz _check_cls <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit 1, main clock is stopped. _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. no te that in <2> above, the cls bit is read in a closed loop. chapter 6 clock generation function user?s manual u17728ej3v1ud 214 (b) example of setting subclock operation main clock operation <1> mck bit 1: main clock starts oscillating <2> insert waits by the program and wait until the oscillation stabilizat ion time of the main clock elapses. <3> ck3 bit 1: use of a bit manipulation instruct ion is recommended. do not change the ck2 to ck0 bits. <4> main clock operation: it takes the following time after the ck3 bit is set until main clock operation is started. max.: 1/f xt (1/subclock frequency) therefore, insert one nop instructi on immediately after setting the ck3 bit to 0 or read the cls bit to check if main clock operation has started. caution enable operation of the on-chip peripher al functions operating with the main clock only after the oscillation of the main clock stabilizes. if their operations are enabled before the lapse of the oscillation stabilizat ion time, a malfunction may occur. [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _start_main_osc : st.b r0, prcmd[r0] -- release of protection of special registers clr1 6, pcc[r0] -- main clock starts oscillating. <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time. _wait_ost : nop nop nop addi -1, r11, r11 cmp r0, r11 bne _wait_ost <3> st.b r0, prcmd[r0] clr1 3, pcc[r0] -- ck3 0 <4> _check_cls : tst1 4, pcc[r0] -- wait until main clock operation starts. bnz _check_cls _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. no te that in <4> above, the cls bit is read in a closed loop. chapter 6 clock generation function user?s manual u17728ej3v1ud 215 (2) internal oscillati on mode register (rcm) the rcm register is an 8-bit register that sets the operation mode of the internal oscillator. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 rcm 0 0 0 00 0 rstop internal oscillator oscillation internal oscillator stopped rstop 0 1 oscillation/stop of internal oscillator after reset: 00h r/w address: fffff80ch < > cautions 1. the internal oscilla tor cannot be stopped while the cpu is operating on the internal oscillation clock (ccls.cclsf bit = 1). do not set the rstop bit to 1. 2. the internal oscillator o scillates if the ccls.cclsf bit is set to 1 (when wdt overflow occurs during oscillation stabilizat ion) even when the rstop bit is set to 1. at this time, the rstop bit remains being set to 1. (3) cpu operation clock status register (ccls) the ccls register indicates the stat us of the cpu operation clock. this register is read-only, in 8-bit or 1-bit units. reset input clears this register to 00h. 0 ccls 0 0 0 0 0 0 cclsf after reset: 00h note r address: fffff82eh operating on main clock (f x ) or subclock (f xt ). operating on internal oscillation clock (f r ). cclsf 0 1 cpu operation clock status note if wdt overflow occurs during oscillation stabilizati on after a reset is released, the cpu operates on the internal oscillation clock (f r ). at this time, the cclsf bit is set to 1 and the reset value is 01h. chapter 6 clock generation function user?s manual u17728ej3v1ud 216 6.4 operation 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock pcc register clk bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 register setting and operation status target clock during reset during oscillation stabilization time count halt mode idle1, idle2 mode stop mode subclock mode sub-idle mode subclock mode sub-idle mode main clock oscillator (f x ) { { { { { subclock oscillator (f xt ) { { { { { { { { { cpu clock (f cpu ) { { internal system clock (f clk ) { { { main clock (in pll mode, f xx ) { note { { { peripheral clock (f xx to f xx /1,024) { { wt clock (main) { { { { wt clock (sub) { { { { { { { { { wdt2 clock (internal oscillation) { { { { { { { { wdt2 clock (main) { { wdt2 clock (sub) { { { { { { { { { note lockup time remark o : operable : stopped 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the pcc.ck3 to pcc.ck0 bits. the clkout pin functions alte rnately as the pcm1 pin and functions as a clock output pin if so specified by the control register of port cm. the status of the clko ut pin is the same as the in ternal system clock in table 6-1 and the pin can output the clock when it is in the operable status. it outputs a low level in the stopped stat us. however, the clkout pin is in the port mode (pcm1 pin: input mode) after reset and until it is set in the output mode. ther efore, the stat us of the pin is hi-z. chapter 6 clock generation function user?s manual u17728ej3v1ud 217 6.5 pll function 6.5.1 overview in the v850es/sg3, an operating clock that is 4 or 8 time s higher than the oscillation frequency output by the pll function or the clock-through mode can be selected as the operating clock of the cpu and on-chip peripheral functions. when pll function is used ( 4): input clock = 2.5 to 5 mhz (output: 10 to 20 mhz) when pll function is used ( 8): input clock = 2.5 to 4 mhz (output: 20 to 32 mhz) clock-through mode: input clock = 2.5 to 10 mhz (output: 2.5 to 10 mhz) 6.5.2 registers (1) pll control register (pllctl) the pllctl register is an 8-bit regi ster that controls the pll function. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. 0 pllctl 0 0 0 00 selpll pllon pll stopped pll operating (after pll operation starts, a lockup time is required for frequency stabilization) pllon 0 1 pll operation stop register clock-through mode pll mode selpll 0 1 cpu operation clock selection register after reset: 01h r/w address: fffff82ch < > < > cautions 1. to stop the pll operation, first set the clock through mode (selpll bit = 0), wait for at least 8 clocks, and then stop the pll (pllon bit = 0). when the pllo n bit is cleared to 0, the selpll bit is automatically cleared to 0 (clock-through mode ), but be sure to stop the pll in the above procedure. 2. the selpll bit can be set to 1 only when the pll clock frequency is stabilized. if not (unlocked), ?0? is written to the sel pll bit if data is written to it. chapter 6 clock generation function user?s manual u17728ej3v1ud 218 (2) clock control register (ckc) the ckc register is a special register . data can be written to this regist er only in a combination of specific sequence (see 3.4.8 special registers ). the ckc register controls the inte rnal system clock in the pll mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 0ah. 0 ckc 0 0 0 1 0 1 ckdiv0 after reset: 0ah r/w address: fffff822h f xx = 4 f x (f x = 2.5 to 5.0 mhz) f xx = 8 f x (f x = 2.5 to 4.0 mhz) ckdiv0 0 1 internal system clock (f xx ) in pll mode cautions 1. the pll mode cannot be used at f x = 5.0 to 10.0 mhz. 2. before changing the multip lication factor between 4 and 8 by using the ckc register, set the clock-through mode and stop the pll. 3. be sure to set bits 3 and 1 to ?1 ? and clear bits 7 to 4 and 2 to ?0?. remark both the cpu clock and peripheral clock are divid ed by the ckc register, but only the cpu clock is divided by the pcc register. chapter 6 clock generation function user?s manual u17728ej3v1ud 219 (3) lock register (lockr) phase lock occurs at a given frequency following powe r application or immediately after the stop mode is released, and the time required for stabilization is the lockup time (frequency stabilizat ion time). this state until stabilization is called the lock up status, and the stabilized state is called the locked status. the lockr register includes a lock bit that re flects the pll frequency stabilization status. this register is read-only, in 8-bit or 1-bit units. reset input clears this register to 00h. 0 lockr 0 0 0 00 0 lock locked status unlocked status lock 0 1 pll lock status check after reset: 00h r address: fffff824h < > caution the lock register does not reflect the lock status of the p ll in real time. the set/clear conditions are as follows. [set conditions] ? upon system reset note ? in idle2 or stop mode ? upon setting of pll stop (clearing of pllctl.pllon bit to 0) ? upon stopping main clock and using cpu with subc lock (setting of pcc.ck3 bit to 1 and setting of pcc.mck bit to 1) note this register is set to 01h by reset and cleared to 00h after the reset has been released and the oscillation stabilization time has elapsed. [clear conditions] ? upon overflow of oscillation stabilization time fo llowing reset release (osts register default time (see 24.2 (3) oscillation stabilization time select register (osts) )) ? upon oscillation stabilization timer overflow (tim e set by osts register) following stop mode release, when the stop mode was set in the pll operating status ? upon pll lockup time timer overflow (time set by plls register) when the pllctl.pllon bit is changed from 0 to 1 ? after the setup time inserted upon release of the id le2 mode is released (time set by the osts register) when the idle2 mode is set during pll operation. chapter 6 clock generation function user?s manual u17728ej3v1ud 220 (4) pll lockup time specification register (plls) the plls register is an 8-bit regist er used to select the pll lockup time when the pllctl.pllon bit is changed from 0 to 1. this register can be read or written in 8-bit units. reset input sets this register to 03h. 0 2 10 /f x 2 11 f x 2 12 /f x 2 13 /f x (default value) plls1 0 0 1 1 plls0 0 1 0 1 selection of pll lockup time plls 0 0 0 0 0 plls1 plls0 after reset: 03h r/w address: fffff6c1h cautions 1. set so that the lockup time is 800 s or longer. 2. do not change the plls regi ster setting during the lockup period. chapter 6 clock generation function user?s manual u17728ej3v1ud 221 6.5.3 usage (1) when pll is used ? after the reset signal has been released, the pll operates (pllctl.pllon bit = 1), but because the default mode is the clock-through mode (pllctl.selpll bi t = 0), select the pll mode (selpll bit = 1). ? to enable pll operation, first set the pllon bit to 1, and then set the selpll bit to 1 after the lockr.lock bit = 0. to stop the pll, first select the clock-through mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0). ? the pll stops during transition to idle2 or stop mode regardless of the setting and is restored from idle2 or stop mode to the status before transition. the time requir ed for restoration is as follows. (a) when transiting to idle2 or stop mode from the clock through mode ? stop mode: set the osts register so that the o scillation stabilization time is 1 ms (min.) or longer. ? idle2 mode: set the osts register so that the setup time is 350 s (min.) or longer. (b) when shifting to the idle 2 or stop mode while remaining in the pll operation mode ? stop mode: set the osts register so that the o scillation stabilization time is 1 ms (min.) or longer. ? idle2 mode: set the osts register so that the setup time is 800 s (min.) or longer. when shifting to the idle1 mode, the pll does not stop. stop the pll if necessary. (2) when pll is not used ? the clock-through mode (selpll bit = 0) is selected a fter the reset signal has been released, but the pll is operating (pllon bit = 1) and must t herefore be stopped (pllon bit = 0). user?s manual u17728ej3v1ud 222 chapter 7 16-bit timer/event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. the v850es/sg3 has six timer/event counter channels, tmp0 to tmp5. 7.1 overview an outline of tmpn is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 2 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? overflow interrupt request signals: 1 ? timer output pins: 2 remark n = 0 to 5 7.2 functions tmpn has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 223 7.3 configuration tmpn includes the following hardware. table 7-1. configuration of tmpn item configuration timer register 16-bit counter registers tmpn capture/compare registers 0, 1 (tpnccr0, tpnccr1) tmpn counter read buffer register (tpncnt) ccr0, ccr1 buffer registers timer inputs 2 (tipn0 note 1 , tipn1 pins) timer outputs 2 (topn0, topn1 pins) control registers note 2 tmpn control registers 0, 1 (tpnctl0, tpnctl1) tmpn i/o control registers 0 to 2 (tpnioc0 to tpnioc2) tmpn option register 0 (tpnopt0) notes 1. the tipn0 pin functions alternately as a capt ure trigger input signal, external event count input signal, and external trigger input signal. 2. when using the functions of the tipn0, tipn1, topn0, and topn1 pins, refer to table 4-15 using port pin as alternate-function pin . remark n = 0 to 5 figure 7-1. block diagram of tmpn f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 note 1 , f xx /256 note 2 f xx /128 note 1 , f xx /512 note 2 selector internal bus internal bus topn0 topn1 tipn0 tipn1 selector edge detector ccr0 buffer register ccr1 buffer register tpnccr0 tpnccr1 16-bit counter tpncnt inttpnov inttpncc0 inttpncc1 output controller clear notes 1. tmp0, tmp2, tmp4 2. tmp1, tmp3, tmp5 remark f xx : main clock frequency chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 224 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tpncnt register. when the tpnctl0.tpnce bit = 0, the va lue of the 16-bit counter is ffffh. if the tpncnt register is read at this time, 0000h is read. reset sets the tpnce bit to 0. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tpnccr0 register is used as a compare regist er, the value written to the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tpnccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tpnccr1 register is used as a compare regist er, the value written to the tpnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tpnccr1 register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the tipn0 and tipn1 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tpnioc1 and tpnioc2 registers. (5) output controller this circuit controls the output of the topn0 and topn 1 pins. the output contro ller is controlled by the tpnioc0 register. (6) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 225 7.4 registers the registers that control tmpn are as follows. ? tmpn control register 0 (tpnctl0) ? tmpn control register 1 (tpnctl1) ? tmpn i/o control register 0 (tpnioc0) ? tmpn i/o control register 1 (tpnioc1) ? tmpn i/o control register 2 (tpnioc2) ? tmpn option register 0 (tpnopt0) ? tmpn capture/compare register 0 (tpnccr0) ? tmpn capture/compare register 1 (tpnccr1) ? tmpn counter read buffer register (tpncnt) remarks 1. when using the functions of the tipn0, tipn1,topn0, and topn1 pins, refer to table 4-15 using port pin as alternate-function pin . 2. n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 226 (1) tmpn control register 0 (tpnctl0) the tpnctl0 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tpnctl0 register by software. tpnce tmpn operation disabled (tmpn reset asynchronously note ). tmpn operation enabled. tmpn operation started. tpnce 0 1 tmpn operation control tpnctl0 (n = 0 to 5) 0 0 0 0 tpncks2 tpncks1 tpncks0 654321 after reset: 00h r/w address: tp0ctl0 fffff590h, tp1ctl0 fffff5a0h, tp2ctl0 fffff5b0h, tp3ctl0 fffff5c0h, tp4ctl0 fffff5d0h, tp5ctl0 fffff5e0h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 tpncks2 0 0 0 0 1 1 1 1 internal count clock selection n = 0, 2, 4 n = 1, 3, 5 tpncks1 0 0 1 1 0 0 1 1 tpncks0 0 1 0 1 0 1 0 1 note the tpnopt0.tpnovf bit and 16-bit count er are reset at the same time. in addition, the timer output pins (topn0 and topn1 pins) are reset to the status set by the tpnioc0 register when the 16-bit counter is reset. cautions 1. set the tpncks2 to tpncks0 bits when the tpnce bit = 0. when the value of the tpnce bi t is changed from 0 to 1, the tpncks2 to tpncks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency (2) tmpn control register 1 (tpnctl1) the tpnctl1 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 227 0 tpnest 0 1 software trigger control tpnctl1 (n = 0 to 5) tpnest tpneee 0 0 tpnmd2 tpnmd1 tpnmd0 <6> <5> 4 3 2 1 after reset: 00h r/w address: tp0ctl1 fffff591h, tp1ctl1 fffff5a1h, tp2ctl1 fffff5b1h, tp3ctl1 fffff5c1h, tp4ctl1 fffff5d1h, tp5ctl1 fffff5e1h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tpnest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tpnest bit as the trigger. disable operation with external event count input (tipn0 pin). (perform counting with the count clock selected by the tpnctl0.tpncks0 to tpncks2 bits.) tpneee 0 1 count clock selection the tpneee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tpnmd2 0 0 0 0 1 1 1 1 timer mode selection tpnmd1 0 0 1 1 0 0 1 1 tpnmd0 0 1 0 1 0 1 0 1 enable operation with external event count input (tipn0 pin). (perform counting at the valid edge of the external event count input signal (tipn0 pin).) ? the read value of the tpnest bit is always 0. cautions 1. the tpnest bit is valid only in the external trigger pulse output mode or the one-shot pulse output mode. in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tpneee bit. 3. set the tpneee and tpnmd2 to tpnmd0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) the operation is not guaranteed when rewriting is performed with the tpnce bit = 1. if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 4. be sure to clear bits 3, 4, and 7 to ?0?. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 228 (3) tmpn i/o control register 0 (tpnioc0) the tpnioc0 register is an 8-bit register that controls the timer output (topn0, topn1 pins). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 229 0 tpnol1 0 1 topn1 pin output level setting note topn1 pin output starts at high level topn1 pin output starts at low level tpnioc0 (n = 0 to 5) 0 0 0 tpnol1 tpnoe1 tpnol0 tpnoe0 6543<2>1 after reset: 00h r/w address: tp0ioc0 fffff592h, tp1ioc0 fffff5a2h, tp2ioc0 fffff5b2h, tp3ioc0 fffff5c2h, tp4ioc0 fffff5d2h, tp5ioc0 fffff5e2h tpnoe1 0 1 topn1 pin output setting timer output disabled ? when tpnol1 bit = 0: low level is output from the topn1 pin ? when tpnol1 bit = 1: high level is output from the topn1 pin tpnol0 0 1 topn0 pin output level setting note topn0 pin output starts at high level topn0 pin output starts at low level tpnoe0 0 1 topn0 pin output setting timer output disabled ? when tpnol0 bit = 0: low level is output from the topn0 pin ? when tpnol0 bit = 1: high level is output from the topn0 pin 7 <0> timer output enabled (a pulse is output from the topn1 pin). timer output enabled (a pulse is output from the topn0 pin). note the output level of the timer output pin (topnm) specified by the tpnolm bit is shown below (m = 0, 1). tpnce bit topnm pin output 16-bit counter ? when tpnolm bit = 0 tpnce bit topnm pin output 16-bit counter ? when tpnolm bit = 1 cautions 1. the pin output changes if the setting of the tpnioc0 register is rewritten when the port is set to topn0 and topn1 outputs. therefore, note changes in the pin status by setting the port to the input mode and making the output status of the pins a high- impedance state. 2. rewrite the tpnol1, tpnoe1, tpnol0, and tpnoe0 bits when the tpnctl0.tpnce bit = 0. ( the same value can be written when the tpnce bit = 1.) if rewr iting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 3. even if the tpnolm bit is manipulated when the tpnce and tpnoem bits are 0, the topnm pin output level varies (m = 0, 1). chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 230 (4) tmpn i/o control register 1 (tpnioc1) the tpnioc1 register is an 8-bit regist er that controls the valid edge of the capture trig ger input signals (tipn0, tipn1 pins). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnis3 0 0 1 1 tpnis2 0 1 0 1 capture trigger input signal (tipn1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tpnioc1 (n = 0 to 5) 0 0 0 tpnis3 tpnis2 tpnis1 tpnis0 654321 after reset: 00h r/w address: tp0ioc1 fffff593h, tp1ioc1 fffff5a3h, tp2ioc1 fffff5b3h, tp3ioc1 fffff5c3h, tp4ioc1 fffff5d3h, tp5ioc1 fffff5e3h tpnis1 0 0 1 1 tpnis0 0 1 0 1 capture trigger input signal (tipn0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnis3 to tpnis0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnis3 to tpnis0 bits are valid only in the free-running timer mode (only when tpnopt 0.tpnccs1, tpnccs0 bits = 11) and the pulse width measur ement mode. in all other modes, a capture operation is not possible. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 231 (5) tmpn i/o control register 2 (tpnioc2) the tpnioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tipn0 pin) and external trigger input signal (tipn0 pin). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnees1 0 0 1 1 tpnees0 0 1 0 1 external event count input signal (tipn0 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tpnioc2 (n = 0 to 5) 0 0 0 tpnees1 tpnees0 tpnets1 tpnets0 654321 after reset: 00h r/w address: tp0ioc2 fffff594h, tp1ioc2 fffff5a4h, tp2ioc2 fffff5b4h, tp3ioc2 fffff5c4h, tp4ioc2 fffff5d4h, tp5ioc2 fffff5e4h tpnets1 0 0 1 1 tpnets0 0 1 0 1 external trigger input signal (tipn0 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnees1, tpnees0, tpnets1, and tpnets0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnees1 and tpnees0 bits are valid only when the tpnctl1.tpneee bit = 1 or when the external event count mode (tpnctl1.tpnmd 2 to tpnctl1.tpnmd0 bits = 001) has been set. 3. the tpnets1 and tpnets0 bits are valid only when the external trigger pulse output mode (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 bits = 010) or the one-shot pulse output mode (tpnctl1.tpn md2 to tpnctl1.tpnmd0 = 011) is set. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 232 (6) tmpn option register 0 (tpnopt0) the tpnopt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnccs1 0 1 tpnccr1 register capture/compare selection the tpnccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by setting tpnctl0.tpnce bit = 0) tpnopt0 (n = 0 to 5) 0 tpnccs1 tpnccs0 0 0 0 tpnovf 654321 after reset: 00h r/w address: tp0opt0 fffff595h, tp1opt0 fffff5a5h, tp2opt0 fffff5b5h, tp3opt0 fffff5c5h, tp4opt0 fffff5d5h, tp5opt0 fffff5e5h tpnccs0 0 1 tpnccr0 register capture/compare selection the tpnccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by setting tpnctl0.tpnce bit = 0) tpnovf set (1) reset (0) tmpn overflow detection flag ? the tpnovf bit is set to 1 when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an overflow interrupt request signal (inttpnov) is generated at the same time that the tpnovf bit is set to 1. the inttpnov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tpnovf bit is not cleared to 0 even when the tpnovf bit or the tpnopt0 register are read when the tpnovf bit = 1. ? before clearing the tpnovf bit to 0 after the inttpnov signal has been generated, be sure to confirm (read) that the tpnovf bit is set to 1. ? the tpnovf bit can be both read and written, but the tpnovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmpn. overflow occurred tpnovf bit 0 written or tpnctl0.tpnce bit = 0 7 <0> cautions 1. rewrite the tpnccs1 and tpnccs0 bits when the tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mi stakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3, 6, and 7 to ?0?. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 233 (7) tmpn capture/compare register 0 (tpnccr0) the tpnccr0 register is a 16-bit re gister that can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs0 bit. in the pulse width measurement mode, the tpnccr0 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tpnccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution accessing the tpnccr0 register is prohibited in the following st atuses. for details, refer to 3.4.9 (2) accessing sp ecific on-chip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tpnccr0 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr0 fffff596h, tp1ccr0 fffff5a6h, tp2ccr0 fffff5b6h, tp3ccr0 fffff5c6h, tp4ccr0 fffff5d6h, tp5ccr0 fffff5e6h 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 234 (a) function as compare register the tpnccr0 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. if topn0 pin output is ena bled at this time, the output of the topn0 pin is inverted. when the tpnccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. the compare register is not cleared when the tpnctl0.tpnce bit = 0. (b) function as capture register when the tpnccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tpnccr0 register if the valid ed ge of the capture trigger input pin (tipn0 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tpnccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tipn0) is detected. even if the capture operation and reading the tpn ccr0 register conflict, the correct value of the tpnccr0 register can be read. the capture register is cleared when the tpnctl0.tpnce bit = 0. remark n = 0 to 5 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note triggered by writing to the tpnccr1 register remark for details of anytime write and batch write, see 7.6 (2) anytime write and batch write . chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 235 (8) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is a 16-bit re gister that can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs1 bit. in the pulse width measurement mode, the tpnccr1 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tpnccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution accessing the tpnccr1 register is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock tpnccr1 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr1 fffff598h, tp1ccr1 fffff5a8h, tp2ccr1 fffff5b8h, tp3ccr1 fffff5c8h, tp4ccr1 fffff5d8h, tp5ccr1 fffff5e8h 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 236 (a) function as compare register the tpnccr1 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. if topn1 pin output is ena bled at this time, the output of the topn1 pin is inverted. the compare register is not cleared when the tpnctl0.tpnce bit = 0. (b) function as capture register when the tpnccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tpnccr1 register if the valid ed ge of the capture trigger input pin (tipn1 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tpnccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tipn1) is detected. even if the capture operation and reading the tpn ccr1 register conflict, the correct value of the tpnccr1 register can be read. the capture register is cleared when the tpnctl0.tpnce bit = 0. remark n = 0 to 5 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note triggered by writing to the tpnccr1 register remark for details of anytime write and batch write, see 7.6 (2) anytime write and batch write . chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 237 (9) tmpn counter read bu ffer register (tpncnt) the tpncnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tpnctl0.tpnce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tpncnt register is cleared to 0000h when the tpnce bit = 0. if the tpncnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tpncnt register is cleared to 000 0h after reset, as the tpnce bit is cleared to 0. caution accessing the tpncnt register is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tpncnt (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r address: tp0cnt fffff59ah, tp1cnt fffff5aah, tp2cnt fffff5bah, tp3cnt fffff5cah, tp4cnt fffff5dah, tp5cnt fffff5eah 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 238 7.5 timer output operations the following table shows the operations and out put levels of the topn0 and topn1 pins. table 7-4. timer output control in each mode operation mode topn1 pin topn0 pin interval timer mode square wave output external event count mode none external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output square wave output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode none remark n = 0 to 5 table 7-5. truth table of topn0 and topn1 pins under control of timer output control bits tpnioc0.tpnolm bit tpnioc0.tpnoem bit tpnctl0.tpnce bit level of topnm pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 239 7.6 operation tmpn can perform the following operations. operation tpnctl1.tpnest bit (software trigger bit) tipn0 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count mode, specify that t he valid edge of the tipn0 pin capture trigger input is not detected (by clearing the tpnioc1.tpni s1 and tpnioc1.tpnis0 bits to ?00?). 2. when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tpnctl1.tpneee bit to 0). remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 240 (1) counter basic operation this section explains the basic oper ation of the 16-bit counter. for details, refer to the description of the operation in each mode. remark n = 0 to 5 (a) counter start operation the 16-bit counter of tmpn starts countin g from the default value ffffh in all modes. it counts up from ffffh to 0000h, 0001h, 0002h, 0003h, and so on. (b) clear operation the 16-bit counter is cleared to 0000h when its value matches the value of the compare register and is cleared, and when its value is captured and cleared. the counting operation fr om ffffh to 0000h that takes place immediately after the counter has start ed counting or when the counter overflows is not a clearing operation. therefore, the inttpncc0 and inttpncc1 interrupt signals are not generated. (c) overflow operation the 16-bit counter overflows when the counter counts up from ffffh to 0000h in the free-running timer mode or pulse width measurement mode . if the counter overflows, the tpnopt0.tpnovf bit is set to 1 and an interrupt request signal (inttpnov) is generate d. note that the inttpnov signal is not generated under the following conditions. ? immediately after a counti ng operation has been started ? if the counter value matches the compare value ffffh and is cleared ? when ffffh is captured and cleared in the pulse width measurement mode and the counter counts up from ffffh to 0000h caution after the overflow interrupt request signa l (inttpnov) has been generated, be sure to check that the overflow flag (tpnovf bit) is set to 1. (d) counter read operation during counting operation the value of the 16-bit counter of tmpn can be re ad by using the tpncnt register during the count operation. when the tpnctl0.tpnce bit = 1, the val ue of the 16-bit counter can be read by reading the tpncnt register. when the tpnctl0.tpnce bit = 0, the 16-bit counter is ffffh and the tpncnt register is 0000h. (e) interrupt operation tmpn generates the following three types of interrupt request signals. ? inttpncc0 interrupt: this signal functions as a match interrupt request signal of the ccr0 buffer register and as a capture interrupt request signal to the tpnccr0 register. ? inttpncc1 interrupt: this signal functions as a match interrupt request signal of the ccr1 buffer register and as a capture interrupt request signal to the tpnccr1 register. ? inttpnov interrupt: this signal functions as an overflow interrupt request signal. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 241 (2) anytime write and batch write the tpnccr0 and tpnccr1 registers in tmpn can be re written during timer operation (tpnctl0.tpnce bit = 1), but the write method (anytime write, batch wr ite) of the ccr0 and ccr1 buffer registers differs depending on the mode. (a) anytime write in this mode, data is transferred at any time from the tpnccr0 and tpnccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. (n = 0 to 5). figure 7-2. flowchart of basic operation for anytime write start initial settings ? set values to tpnccrm register ? timer operation enable (tpnce bit = 1) transfer values of tpnccrm register to ccrm buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start inttpncc1 signal output tpnccrm register rewrite transfer to ccrm buffer register inttpncc0 signal output note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. remarks 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 242 figure 7-3. timing of anytime write d 01 d 01 d 01 d 01 0000h tpnce bit = 1 d 02 d 02 d 11 d 11 d 11 d 12 d 12 d 12 d 02 d 11 0000h d 12 16-bit counter tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal ccr0 buffer register ccr1 buffer register 0000h ffffh remarks 1. d 01 , d 02 : setting values of tpnccr0 register d 11 , d 12 : setting values of tpnccr1 register 2. the above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 243 (b) batch write in this mode, data is transferred all at once from the tpnccr0 and tpnccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. this data is transferred upon a match between the value of the ccr0 buffer register and the value of the 16-bit counter. transfer is enabled by writing to the tpnccr1 register. whether to enable or disable the next transfer timing is controlled by writing or not writing to the tpnccr1 register. in order for the setting value when the tpnccr0 and tpnccr1 registers are rewritten to become the 16- bit counter comparison value (in other words, in or der for this value to be transferred to the ccr0 and ccr1 buffer registers), it is necessary to rewrite the tpnccr0 register and then write to the tpnccr1 register before the 16-bit counter value and the ccr0 buff er register value match. therefore, the values of the tpnccr0 and tpnccr1 registers are transferr ed to the ccr0 and ccr1 buffer registers upon a match between the count value of the 16-bit counter and the value of the ccr0 buffer register. thus even when wishing only to rewrite the value of the tpnccr 0 register, also write the same value (same as preset value of the tpnccr1 regi ster) to the tpnccr1 register. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 244 figure 7-4. flowchart of basic operation for batch write start initial settings ? set values to tpnccrm register ? timer operation enable (tpnce bit = 1) transfer values of tpnccrm register to ccrm buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start ? transfer of values of tpnccrm register to ccrm buffer register inttpncc1 signal output tpnccr0 register rewrite tpnccr1 register rewrite inttpncc0 signal output batch write enable note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. caution writing to the tpnccr1 regi ster includes enabling of batch wr ite. thus, rewrite the tpnccr1 register after rewriting the tpnccr0 register. remarks 1. the above flowchart illustrates an example of the operation in the pwm output mode. 2. n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 245 figure 7-5. timing of batch write d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 0000h d 11 tpnce bit = 1 note 1 d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output topn0 pin output ccr0 buffer register ccr1 buffer register note 1 note 1 note 1 same value write d 02 d 12 0000h d 03 d 12 note 2 note 3 ffffh notes 1. because the tpnccr1 register was not rewritten, d 03 is not transferred. 2. because the tpnccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of t he 16-bit counter and the value of the tpnccr0 register (d 01 ). 3. because the tpnccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of t he 16-bit counter and the value of the tpnccr0 register (d 02 ). remarks 1. d 01 , d 02 , d 03 : setting values of tpnccr0 register d 11 , d 12 : setting values of tpnccr1 register 2. the above timing chart illustrates the opera tion in the pwm output mode as an example. 3. n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 246 7.6.1 interval timer mode (t pnmd2 to tpnmd0 bits = 000) in the interval timer mode, an interrupt request signal (inttpncc0) is generated at the interval set by the tpnccr0 register if the tpnctl0.tpnce bit is set to 1. a square wave with a duty factor of 50% whose half cycle is equal to the interval can be output from the topn0 pin. the tpnccr1 register is not used in the interval timer m ode. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register, and when the count va lue of the 16-bit counter ma tches the value of the ccr1 buffer register, a compare match interrupt request signal (i nttpncc1) is generated. in addition, a square wave with a duty factor of 50%, which is inverted when the inttpncc1 signal is generated, can be ou tput from the topn1 pin. the value of the tpnccr0 and tpnccr1 registers c an be rewritten even while the timer is operating. figure 7-6. configuration of interval timer 16-bit counter output controller ccr0 buffer register tpnce bit tpnccr0 register count clock selection clear match signal topn0 pin inttpncc0 signal remark n = 0 to 5 figure 7-7. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 247 when the tpnce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the out put of the topn0 pin is inverted. additionally, the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, the output of the topn0 pin is in verted, and a compare match interrupt request signal (inttpncc0) is generated. the interval can be calculated by the following expression. interval = (set value of tpnccr0 register + 1) count clock cycle remark n = 0 to 5 figure 7-8. register setting for in terval timer mode operation (1/3) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0 0/1 note 00 tpnctl1 0, 0, 0: interval timer mode 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count with external event count input signal 000 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest note the tpneee bit can be set to 1 only when the timer output (topn1) is used. however, set the tpnccr0 and tpnccr1 registers to the same value. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 248 figure 7-8. register setting for in terval timer mode operation (2/3) (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of topn0 pin output level before count operation 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of topn1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 note tpnioc2 select valid edge of external event count input (tipn0 pin). 0/1 note 00 tpnees0 tpnets1 tpnets0 tpnees1 note the tpnees1 and tpnees0 bits can be set only when the timer output (topn1) is used. however, set the tpnccr0 and tpnccr1 registers to the same value. (e) tmpn counter read bu ffer register (tpncnt) by reading the tpncnt register, the count va lue of the 16-bit counter can be read. (f) tmpn capture/compare register 0 (tpnccr0) if the tpnccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 249 figure 7-8. register setting for in terval timer mode operation (3/3) (g) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is not used in the interval timer mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer regi ster, the topn1 pin output is inverted and a compare match interrupt request signal (inttpncc1) is generated. by setting this register to the same value as the va lue set in the tpnccr0 register, a square wave with a duty factor of 50% can be output from the topn1 pin. when the tpnccr1 register is not used, it is recommended to set its value to ffffh. also mask the register by the interrupt mask flag (tpnccic1.tpnccmk1). remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the interval timer mode. 2. n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 250 (1) interval timer mode operation flow figure 7-9. software processing flow in interval timer mode tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register note , tpnccr0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. the output level of the topn0 pin is as specified by the tpnioc0 register. start stop <1> count operation start flow <2> count operation stop flow d 0 <1> <2> d 0 d 0 d 0 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal note the tpnees1 and tpnees0 bits can be set only when timer output (topn1) is used. however, set the tpnccr0 and tpnccr1 registers to the same value. remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 251 (2) interval timer mode operation timing (a) operation if tpnccr0 re gister is set to 0000h if the tpnccr0 register is set to 0000h, the inttpn cc0 signal is generated at each count clock, and the output of the topn0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 252 (b) operation if tpnccr0 register is set to ffffh if the tpnccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. t he counter is cleared to 0000h in synchronization with the next count-up timing. the inttpncc0 signal is generated and the output of the topn0 pin is inverted. at this time, an overflow interrupt request signal (inttpnov) is not generated, nor is the overflow flag (tpnopt0.tpnovf bit) set to 1. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 253 (c) notes on rewriting tpnccr0 register when the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. if there is a possibility of ov erflow, stop counting and then change the set value. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register tpnol0 bit topn0 pin output inttpncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. n = 0 to 5 if the value of the tpnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tpnccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttpncc0 signal is generated and the output of the topn0 pin is inverted. therefore, the inttpncc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 254 (d) operation of tpnccr1 register figure 7-10. configuration of tpnccr1 register ccr0 buffer register tpnccr0 register tpnccr1 register ccr1 buffer register topn0 pin inttpncc0 signal topn1 pin inttpncc1 signal 16-bit counter output controller tpnce bit count clock selection clear match signal output controller match signal remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 255 when the tpnccr1 register is set to the same val ue as the tpnccr0 register, the inttpncc1 signal is generated at the same timing as the inttpncc0 signa l and the topn1 pin output is inverted. in other words, a square wave with a duty factor of 50% can be output from the topn1 pin. the following shows the operation when the tpnccr1 re gister is set to other than the value set in the tpnccr0 register. if the set value of the tpnccr1 register is less than the set value of the tpnccr0 register, the inttpncc1 signal is generated once per cycle. at the same time, the output of the topn1 pin is inverted. the topn1 pin outputs a square wave with a duty fact or of 50% after outputting a short-width pulse. figure 7-11. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal tpnccr1 register topn1 pin output inttpncc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 256 if the set value of the tpnccr1 register is greater than the set value of the tpnccr0 register, the count value of the 16-bit counter does not match the va lue of the tpnccr1 register. consequently, the inttpncc1 signal is not generated, nor is the output of the topn1 pin changed. when the tpnccr1 register is not used, it is recommended to set it s value to ffffh. figure 7-12. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal tpnccr1 register topn1 pin output inttpncc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 257 (3) operation by external event count input (tipn0) (a) operation to count the 16-bit counter at the va lid edge of external event count input (tipn0) in the interval timer mode, the valid edge of the external event count input is necessary once because the 16-bit counter is cleared from ffffh to 0000h immediately afte r the tpnce bit is set from 0 to 1. when 0001h is set to both the tpnccr0 and tpnccr1 r egisters, the topn1 pin output is inverted each time the 16-bit counter counts twice. the tpnctl1.tpneee bit can be set to 1 in the interval timer mode only when the timer output (topn1) is used with the external event count input. tpnce bit external event count input tpnccr0 register tpnccr1 register topn1 pin output 16-bit counter ffffh 0000h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h number of external event count: 3 number of external event count: 2 number of external event count: 2 2-count width 2-count width 2-count width (tipn0 pin input) remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 258 7.6.2 external event count mode (tpnmd2 to tpnmd0 bits = 001) in the external event count mode, the valid edge of the external event count input (tipn0) is counted when the tpnctl0.tpnce bit is set to 1, and an interrupt request signal (inttpncc0) is generated each time the number of edges set by the tpnccr0 register have been counted. the topn0 and topn1 pins cannot be used. when using the topn1 pin for external event count input, set the tp nctl1.tpneee bit to 1 in the interval timer mode (see 7.6.1 (3) operation by external event count input (tipn0) ). the tpnccr1 register is not used in the external event count mode. caution in the external event count mode, the tpnccr0 and tpnccr1 registers must not be cleared to 0000h. figure 7-13. configuration in external event count mode 16-bit counter ccr0 buffer register tpnce bit tpnccr0 register edge detector clear match signal inttpncc0 signal tipn0 pin (external event count input) remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 259 figure 7-14. basic timing in external event count mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 0 d 0 d 0 d 0 16-bit counter tpnccr0 register inttpncc0 signal external event count input (tipn0 pin input) d 0 number of external event count (d 0 ) note times number of external event count (d 0 + 1) times number of external event count (d 0 + 1) times d 0 ? 1d 0 0000 0001 note in the external event count mode, when the tpnct l0.tpnce bit is set to 1 (operation starts), the 16-bit counter is cleared from ffffh to 0000h at the same time. the first count operation starts from 0001h each time the valid edge of the external event count input is detected. therefore, the count of the fi rst count operation is one number smaller than the count of the second or subsequent count operation. remarks 1. this figure shows the basic timing when the ri sing edge is specified as the valid edge of the external event count input. 2. n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 260 when the tpnce bit is set to 1, the value of the 16-bit counter is clea red from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttpncc0) is generated. the inttpncc0 signal is generated for the first time wh en the valid edge of the exte rnal event count input has been detected ?value set to tpnccr0 register? times. after that, the inttpncc0 signal is generated each time the valid edge of the external event count input has been det ected ?value set to tpnccr0 register + 1? times. figure 7-15. register setting for operati on in external event count mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 0: stop counting 1: enable counting 000 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 00000 tpnctl1 0, 0, 1: external event count mode 001 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest (c) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input (tipn0 pin) 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 261 figure 7-15. register setting for operati on in external event count mode (2/2) (d) tmpn counter read bu ffer register (tpncnt) the count value of the 16-bit counter can be read by reading the tpncnt register. (e) tmpn capture/compare register 0 (tpnccr0) if the tpnccr0 register is set to d 0 , the count is cleared when the number of external events has reached (d 0 ) and the first compare match interrupt request signal (inttpncc0) is generated. the second compare match interrupt request signal (inttpncc0) is generated when the number of external events has reached (d 0 + 1). (f) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is not used in the external event count mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buff er register. when the c ount value of the 16-bit counter matches the value of the ccr1 buffer regi ster, a compare match interrupt request signal (inttpncc1) is generated. when the tpnccr1 registers are not used, it is recommended to set their value to ffffh. also mask the register by the interrupt mask flag (tpnccic1.tpnccmk1). cautions 1. set 00h to the tpnioc0 register. 2. when an external clock is used as the count clock, the external clock can be input only from the tipn0 pin. at this time, set the tpnioc1.tpnis1 and tpnioc1.tpnis0 bits to 00 (capture trigger input (tipn0 pin): no edge detection). remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the external event count mode. 2. n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 262 (1) external event count mode operation flow figure 7-16. flow of software processing in external event count mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 0 d 0 d 0 d 0 <1> <2> tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl1 register, tpnioc2 register, tpnccr0, tpnccr1 registers initial setting of these registers is performed before the tpnce bit is set to 1. the counter is initialized and counting is stopped by clearing the tpnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 263 (2) operation timing in external event count mode cautions 1. in the external event count mode, do not set the tpnccr0 and tpnccr1 registers to 0000h. 2. in the external event count mode, use of th e timer output (topn0, topn1) is disabled. if performing timer output (topn1) using external event count input (tipn0), set the interval timer mode, and set the operation enabled (tpnctl1.tpneee bit = 1) by the external event count input for the count clock (refer to 7.6.1 (3) operation by external event count input (tipn0)). (a) operation if tpnccr0 register is set to ffffh if the tpnccr0 register is set to ffffh, the 16-bit co unter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the inttpncc0 signal is generated. at this time, the tpnopt0.tpnovf bit is not set. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal ffffh number of external event count ffffh times number of external event count 10000h times number of external event count 10000h times remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 264 (b) notes on rewriting the tpnccr0 register when the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. if there is a possibility of over flow, stop counting and then change the set value. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 number of external event count (1) (d 1 ) times number of external event count (ng) (10000h + d 2 + 1) times number of external event count (2) (d 2 + 1) times remark n = 0 to 5 if the value of the tpnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tpnccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttpncc0 signal is generated. therefore, the inttpncc0 signal may not be generated at the va lid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 265 (c) operation of tpnccr1 register figure 7-17. configuration of tpnccr1 register ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal inttpncc1 signal edge detector tipn0 pin (external event count input) remark n = 0 to 5 if the set value of the tpnccr1 register is smalle r than the set value of the tpnccr0 register, the inttpncc1 signal is generated once per cycle. figure 7-18. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 266 if the set value of the tpnccr1 register is greater than the set value of the tpnccr0 register, the inttpncc1 signal is not generated because the count va lue of the 16-bit counte r and the value of the tpnccr1 register do not match. it is recommended to set ffffh to the tpnccr1 register when the tpnccr1 register is not used. figure 7-19. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 267 7.6.3 external trigger pulse output m ode (tpnmd2 to tpnmd0 bits = 010) in the external trigger pulse output mode, 16-bit timer/event counter p waits for a trigger when the tpnctl0.tpnce bit is set to 1. when the valid edge of an ex ternal trigger input signal is detected, 16-bit timer/event counter p starts counting, and outputs a pwm waveform from the topn1 pin. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the topn0 pin. figure 7-20. configuration in external trigger pulse output mode ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) output controller topn1 pin inttpncc1 signal topn0 pin note count clock selection count start control edge detector software trigger generation tipn0 pin note (external trigger input) transfer transfer s r note external trigger input pin (tipn0) and timer output pin (topn0) share the same alternate- function pin, two functions cannot be used at the same time. caution in external trigger pulse output mode , select the internal cl ock (set tpnctl1.tpneee bit = 0) as the count clock. remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 268 figure 7-21. basic timing in exte rnal trigger pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) 16-bit timer/event counter p waits for a trigger when the tpnc e bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counti ng at the same time, and outputs a pwm wave\form from the topn1 pin. if the trigger is generated again while the counter is operating, the counter is cleared to 0000h and restarted. (the output of th e topn0 pin is inverted. the topn1 pin ou tputs a high-level regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 regist er)/(set value of tpnccr0 register + 1) the compare match request signal inttpncc0 is generat ed when the 16-bit counter counts next time after its count value matches the value of the c cr0 buffer register, and the 16-bit count er is cleared to 0000h. the compare match interrupt request signal inttpncc1 is generated when t he count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tpnccrm register is transferred to the ccrm buffer register when the count value of the 16- bit counter matches the value of the ccrm buffer re gister and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input (tipn0) signal, or setting the software trigger (tpnctl1.tpnest bit) to 1 is used as the trigger. remark n = 0 to 5, m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 269 figure 7-22. setting of registers in exte rnal trigger pulse output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0/1 0 0 0 tpnctl1 0: operate on count clock selected by tpncks0 to tpncks2 bits generate software trigger when 1 is written 010 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 0, 1, 0: external trigger pulse output mode (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of topn1 pin output level in status of waiting for external trigger 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of topn1 pin output level in status of waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 note tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 note clear this bit to 0 when the topn0 pin is not used in the external trigger pulse output mode. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 270 figure 7-22. setting of registers in exte rnal trigger pulse output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 00000 tpnioc2 select valid edge of external trigger input (tipn0 pin) 0 0/1 0/1 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the external trigger pulse output mode. 2. n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 271 (1) operation flow in extern al trigger pulse output mode figure 7-23. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 272 figure 7-23. software processing flow in ex ternal trigger pulse output mode (2/2) tpnce bit = 1 setting of tpnccr0 register register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting is enabled (tpnce bit = 1). trigger wait status writing the same value (same as the tpnccr1 register already set) to the tpnccr1 register is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. start setting of tpnccr1 register <1> count operation start flow <2> tpnccr0 and tpnccr1 register setting change flow setting of tpnccr0 register when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. setting of tpnccr1 register <4> pnccr0, tpnccr1 register setting change flow only writing of the tpnccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. setting of tpnccr1 register <3> pnccr0, tpnccr1 register setting change flow tpnce bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 273 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccrm register after writing the tpnccr 1 register after the inttpncc0 signal is detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) topn0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 274 in order to transfer data from the tpnccrm register to the ccrm buffer register, the tpnccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tpnccr0 register and then set the active level width to the tpnccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tpnccr0 register, and then write the same value (same as the tpnccr1 regist er already set) to the tpnccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. after data is written to the tpnccr1 register, the val ue written to the tpnccrm register is transferred to the ccrm buffer register in synchronization with clear ing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tpnccr0 or tpnccr1 register again after writing the tpnccr1 register once, do so after the inttpncc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the tpn ccrm register to the ccrm buffer register conflicts with writing the tpnccrm register. remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 275 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. the 16-bit counter is cleared to 0000h and the inttpnco0 and inttpncc1 signals are generated at the next timing after a match between the count value of the 16-bit counter and t he value of the ccr0 buffer register. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) d 0 l 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark n = 0 to 5 to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 0 ? 1d 0 ? 1 external trigger input (tipn0 pin input) remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 276 (c) conflict between trigger detection and match with ccr1 buffer register if the trigger is detected immediately after the inttp ncc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the topn1 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccr1 buffer register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened remark n = 0 to 5 if the trigger is detected immediately before the inttp ncc1 signal is generated, the inttpncc1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. t he output signal of the topn1 pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter ccr1 buffer register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 277 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the inttp ncc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the topn1 pin is extended by time from generation of the inttpncc0 signal to trigger detection. 16-bit counter ccr0 buffer register inttpncc0 signal topn1 pin output external trigger input (tipn0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark n = 0 to 5 if the trigger is detected immediately before the inttp ncc0 signal is generated, the inttpncc0 signal is not generated. the 16-bit counter is cleared to 0000h, the topn1 pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter ccr0 buffer register inttpncc0 signal topn1 pin output external trigger input (tipn0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 278 (e) generation timing of compare match interrupt request signal (inttpncc1) the timing of generation of the inttpncc1 signal in the external trigger pulse output mode differs from the timing of other mode inttpncc1 signals; the in ttpncc1 signal is generated when the count value of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 1d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5 usually, the inttpncc1 signal is generated in synch ronization with the next count up, after the count value of the 16-bit counter matches the value of the tpnccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the topn1 pin. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 279 7.6.4 one-shot pulse output mode (tpnmd2 to tpnmd0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter p waits for a trigger when the tpnctl0.tpnce bit is set to 1. when the valid edge of an external trigger inpu t (tipn0) is detected, 16-bit timer/event counter p starts counting, and outputs a one-shot pulse from the topn1 pin. instead of the external trigger input (tipn0), a software tr igger can also be generated to output the pulse. when the software trigger is used, the topn0 pin outputs the acti ve level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 7-24. configuration in one-shot pulse output mode ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) output controller (rs-ff) topn1 pin inttpncc1 signal topn0 pin note count clock selection count start control edge detector software trigger generation tipn0 pin note (external trigger input) transfer transfer s r s r note because the external trigger input pin (tipn0) and timer output pin (topn0) share the same alternate-function pin, two functions cannot be used at the same time. caution in one-shot pulse output mode, select th e internal clock (set tpnctl1.tpneee bit = 0) as the count clock. remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 280 figure 7-25. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output topn0 pin output (only when software trigger is used) external trigger input (tipn0 pin input) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) when the tpnce bit is set to 1, 16-bit timer/event counter p waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counti ng, and outputs a one-shot pul se from the topn1 pin. after the one-shot pulse is output, the 16-bit counter is set to 0000h, stops counting, and waits for a trigger. when the trigger is generated again, the 16-bit counter starts counting from 0000h. if a trigger is generated again while the one-shot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tpnccr1 register) count clock cycle active level width = (set value of tpnccr0 register ? set value of tpnccr1 register + 1) count clock cycle the compare match interrupt request signal inttpncc0 is generated when the 16-bit counter counts after its count value matches the value of the c cr0 buffer register. the compare match interrupt request signal inttpncc1 is generated when the count value of the 16-bit counter matches the va lue of the ccr1 buffer register. the valid edge of an external trigger i nput (tipn0 pin) or setting the software tr igger (tpnctl1.tpnest bit) to 1 is used as the trigger. remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 281 figure 7-26. setting of registers in one-shot pulse output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0/1 0 0 0 tpnctl1 0: operate on count clock selected by tpncks0 to tpncks2 bits generate software trigger when 1 is written 011 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 0, 1, 1: one-shot pulse output mode (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of topn0 pin output level in status of waiting for external trigger 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of topn1 pin output level in status of waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 note tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 note clear this bit to 0 when the topn0 pin is not used in the one-shot pulse output mode. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 282 figure 7-26. setting of registers in one-shot pulse output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 00000 tpnioc2 select valid edge of external trigger input (tipn0 pin) 0 0/1 0/1 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 0 ? d 1 + 1) count clock cycle output delay period = d 1 count clock cycle caution one-shot pulses are not output even in the one-shot pulse outpu t mode, if the value set in the tpnccr1 register is greater than that set in the tpnccr0 register. remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the one-shot pulse output mode. 2. n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 283 (1) operation flow in one-shot pulse output mode figure 7-27. software processing flow in one-shot pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output external trigger input (tipn0 pin input) <1> <3> tpnce bit = 1 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). trigger wait status start <1> count operation start flow tpnce bit = 0 count operation is stopped stop <3> count operation stop flow d 10 d 00 d 11 d 01 d 00 d 10 d 11 <2> d 01 setting of tpnccr0, tpnccr1 registers as rewriting the tpnccrm register immediately forwards to the ccrm buffer register, rewriting immediately after the generation of the inttpncc0 signal is recommended. <2> tpnccr0, tpnccr1 register setting change flow remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 284 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tpnccrm register when the value of the tpnccrm register is rewritten to a smaller value during counting, the 16-bit counter may overflow. if there is a possibility of over flow, stop counting and then change the set value. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal tpnccr1 register inttpncc1 signal topn1 pin output topn0 pin output (only when software trigger is used) external trigger input (tipn0 pin input) d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) when the tpnccr0 register is rewritten from d 00 to d 01 and the tpnccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the tpnccr1 register is rewritten when the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the tpnccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter count s up to ffffh and then counts up again from 0000h. when the count value matches d 11 , the counter generates the inttpncc1 signal and asserts the topn1 pin. when the count value matches d 01 , the counter generates the in ttpncc0 signal, deasserts the topn1 pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 285 (b) generation timing of compare match interrupt request signal (inttpncc1) the generation timing of the inttpncc1 signal in the one-shot pulse output mode is different from other mode inttpncc1 signals; the inttpncc1 signal is gen erated when the count val ue of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5 usually, the inttpncc1 signal is generated when the 16- bit counter counts up next time after its count value matches the value of the tpnccr1 register. in the one-shot pulse output mode, howe ver, it is generated one clock earlier. this is because the timing is changed to match the change timing of the topn1 pin. remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 286 7.6.5 pwm output mode (tpnmd 2 to tpnmd0 bits = 100) in the pwm output mode, a pwm waveform is output from the topn1 pin when the tpnctl0.tpnce bit is set to 1. in addition, a square wave with a duty factor of 50% with th e set value of the tpnccr0 register + 1 as half its cycle is output from the topn0 pin. figure 7-28. configuration in pwm output mode ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal inttpncc0 signal output controller (rs-ff) output controller topn1 pin inttpncc1 signal topn0 pin note transfer transfer s r count clock selection internal count clock tipn0 pin note (external event count input) edge detector remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 287 figure 7-29. basic timing in pwm output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal topn0 pin output tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 - d 10 + 1) when the tpnce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts count ing, and outputs a pwm waveform from the topn1 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register ) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 regist er)/(set value of tpnccr0 register + 1) the pwm waveform can be changed by rewriting the tpnccrm register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttpncc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttpncc1 is gener ated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tpnccrm register is transferred to the ccrm buffer register when the count value of the 16- bit counter matches the value of the ccrm buffer re gister and the 16-bit counter is cleared to 0000h. remark n = 0 to 5, m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 288 figure 7-30. setting of registers in pwm output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note the setting is invalid when the tpnctl1.tpneee bit = 1. (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 100 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 0, 0: pwm output mode 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count external event input signal (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of topn0 pin output level before count operation 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of topn1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 note tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 note clear this bit to 0 when the topn0 pi n is not used in the pwm output mode. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 289 figure 7-30. register setting in pwm output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input (tipn0 pin). 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the pwm output mode. 2. n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 290 (1) operation flow in pwm output mode figure 7-31. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register inttpncc0 signal topn0 pin output tpnccr1 register ccr1 buffer register inttpncc1 signal topn1 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 291 figure 7-31. software processing flow in pwm output mode (2/2) tpnce bit = 1 setting of tpnccr0 register register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting is enabled (tpnce bit = 1). writing the same value (same as preset value of the tpnccr1 register) to the tpnccr1 register is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. start setting of tpnccr1 register <1> count operation start flow <2> tpnccr0, tpnccr1 register setting change flow (frequency only) setting of tpnccr0 register when the counter is cleared after setting, the value of the tpnccrm register is transferred to the ccrm buffer register. setting of tpnccr1 register <4> tpnccr0, tpnccr1 register setting change flow (frequency and duty) only writing of the tpnccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of compare register m is transferred to the ccrm buffer register. setting of tpnccr1 register <3> tpnccr0, tpnccr1 register setting change flow (duty only) tpnce bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 292 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccrm register after writing the tpnccr 1 register after the inttpncc0 signal is detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register tpnccr1 register ccr1 buffer register topn1 pin output inttpncc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the tpnccrm register to the ccrm buffer register, the tpnccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tpnccr0 register and then set the active level to the tpnccr1 register. o change only the cycle of the pwm waveform, first set the cycle to the tpnccr0 register, and then write the same value (same as the tpnccr1 register value already set) to the tpnccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. after data is written to the tpnccr1 register, the val ue written to the tpnccrm register is transferred to the ccrm buffer register in synchronization with clear ing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tpnccr0 or tpnccr1 register again after writing the tpnccr1 register once, do so after the inttpncc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the tpn ccrm register to the ccrm buffer register conflicts with writing the tpnccrm register. remark n = 0 to 5, m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 293 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. the 16-bit counter is cleared to 0000h and the inttpncc0 and inttpncc1 signals are generate d at the next timing after a match between the count value of the 16-bit counter and t he value of the ccr0 buffer register. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 l remark n = 0 to 5 to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 0000 ffff 0000 d 00 0000 0001 count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output d 00 ? 1d 00 ? 1 l remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 294 (c) generation timing of compare match interrupt request signal (inttpncc1) the timing of generation of the inttpncc1 signal in the pwm output mode differs from the timing of other mode inttpncc1 signals; the inttpncc1 signal is gen erated when the count val ue of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output inttpncc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5 usually, the inttpncc1 signal is generated in synch ronization with the next counting up after the count value of the 16-bit counter matches the value of the tpnccr1 register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the topn1 pin. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 295 7.6.6 free-running timer mode (t pnmd2 to tpnmd0 bits = 101) in the free-running timer mode, 16-bit timer/event counter p starts counting when the tpnctl0.tpnce bit is set to 1. at this time, the tpnccrm register can be used as a compare register or a capt ure register, depending on the setting of the tpnopt0.tpnccs 0 and tpnopt0.tpnccs1 bits. figure 7-32. configuration in free-running timer mode tpnccr0 register (capture) tpnce bit tpnccr1 register (compare) 16-bit counter tpnccr1 register (compare) tpnccr0 register (capture) output controller tpnccs0, tpnccs1 bits (capture/compare selection) topn0 pin note 1 output controller topn1 pin note 2 edge detector count clock selection edge detector edge detector tipn0 pin note 1 (external event count input/ capture trigger input) tipn1 pin note 2 (capture trigger input) internal count clock 0 1 0 1 inttpnov signal inttpncc1 signal inttpncc0 signal notes 1. because the external event count input pin (tipn0), capture trigger input pin (tipn0), and timer output pin (topn0) share the same alte rnate-function pin, two or more functions cannot be used at the same time. 2. because the capture trigger input pin (tipn1) and timer output pin (topn1) are the same alternate-function pin, two functions cannot be used at the same time. remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 296 ? compare operation when the tpnce bit is set to 1, 16-bit timer/event counter p starts counting, and the output signals of the topn0 and topn1 pins are inverted. when the count value of the 16-bit counter later matches the set value of the tpnccrm register, a compare match interrupt request signal (inttpnccm) is generated, and the output signals of the topnm pins are inverted. the 16-bit counter continues counting in synchronization with the count cloc k. when it counts up to ffffh, it generates an overflow interrupt request signal (inttpnov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bi t) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. the tpnccrm register can be rewritten while the counter is operating. if it is rewritten, the new value is reflected at that time by anytime write, and compared with the count value. figure 7-33. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn0 pin output tpnccr1 register inttpncc1 signal topn1 pin output inttpnov signal tpnovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 297 ? capture operation when the tpnce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tipnm pin is detected, the count value of the 16-bi t counter is stored in the tpnccrm register, and a capture interrupt request signal (inttpnccm) is generated. the 16-bit counter continues counting in synchronization with the count cloc k. when it counts up to ffffh, it generates an overflow interrupt request signal (inttpnov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bi t) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. figure 7-34. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal tipn1 pin input tpnccr1 register inttpncc1 signal inttpnov signal tpnovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 298 figure 7-35. register setting in free-running timer mode (1/3) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note the setting is invalid when the tpnctl1.tpneee bit = 1 (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 101 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 0, 1: free-running timer mode 0: operate with count clock selected by tpncks0 to tpncks2 bits 1: count on external event count input signal (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of topn0 pin output level before count operation 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of topn1 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 299 figure 7-35. register setting in free-running timer mode (2/3) (d) tmpn i/o control register 1 (tpnioc1) 0 0 0 0 0/1 tpnioc1 select valid edge of tipn0 pin input note select valid edge of tipn1 pin input 0/1 0/1 0/1 tpnis2 tpnis1 tpnis0 tpnis3 note set the valid edge selection of the unused alternat e external input signals to ?no edge detection?. (e) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input (tipn0 pin) note 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 note set the valid edge selection of the unused alternat e external input signals to ?no edge detection?. (f) tmpn option register 0 (tpnopt0) 0 0 0/1 0/1 0 tpnopt0 overflow flag specifies if tpnccr0 register functions as capture or compare register 0: compare register 1: capture register specifies if tpnccr1 register functions as capture or compare register 0: compare register 1: capture register 0 0 0/1 tpnccs0 tpnovf tpnccs1 (g) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 300 figure 7-35. register setting in free-running timer mode (3/3) (h) tmpn capture/compare regist ers 0 and 1 (tpnccr0 and tpnccr1) these registers function as captur e registers or compare registers depending on the setting of the tpnopt0.tpnccsm bit. when the registers function as captur e registers, they store the count value of the 16-bit counter when the valid edge input to the tipnm pin is detected. when the registers function as compare registers and when d m is set to the tpnccrm register, the inttpnccm signal is generated when the counter reaches (d m + 1), and the output signal of the topnm pin is inverted. remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 301 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 7-36. software processing flow in fr ee-running timer mode (c ompare function) (1/2) d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3> ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn0 pin output tpnccr1 register inttpncc1 signal topn1 pin output inttpnov signal tpnovf bit remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 302 figure 7-36. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tpnce bit = 1 read tpnopt0 register (check overflow flag). register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnopt0 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before the tpnce bit is set to 1. the tpncks0 to tpncks2 bits can be set when counting starts (tpnce bit = 1). start execute instruction to clear tpnovf bit (clr tpnovf). <1> count operation start flow <2> overflow flag clear flow tpnce bit = 0 counter is initialized and counting is stopped by clearing tpnce bit to 0. stop <3> count operation stop flow tpnovf bit = 1 no yes remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 303 (b) when using capture/compare register as capture register figure 7-37. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal tipn1 pin input tpnccr1 register inttpncc1 signal inttpnov signal tpnovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 304 figure 7-37. software processing flow in fr ee-running timer mode (c apture function) (2/2) tpnce bit = 1 read tpnopt0 register (check overflow flag). register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc1 register, tpnopt0 register initial setting of these registers is performed before the tpnce bit is set to 1. the tpncks0 to tpncks2 bits can be set when counting starts (tpnce bit = 1). start execute instruction to clear tpnovf bit (clr tpnovf). <1> count operation start flow <2> overflow flag clear flow tpnce bit = 0 counter is initialized and counting is stopped by clearing tpnce bit to 0. stop <3> count operation stop flow tpnovf bit = 1 no yes remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 305 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter p is used as an in terval timer with the tpnccrm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttpnccm signal has been detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register inttpncc0 signal topn0 pin output tpnccr1 register inttpncc1 signal topn1 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the corresponding tpnccr m register must be re-set in the interrupt servicing that is executed when the inttpnccm signal is detected. the set value for re-setting the tpnccrm register c an be calculated by the following expression, where ?d m ? is the interval period. compare register default value: d m ? 1 value set to compare register second and subsequent time: previous set value + d m (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 306 (b) pulse width measurement with capture register when pulse width measurement is performed with the tpnccrm register used as a capture register, software processing is necessary for reading the capt ure register each time the inttpnccm signal has been detected and for calculating an interval. ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal tipn1 pin input tpnccr1 register inttpncc1 signal inttpnov signal tpnovf bit 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 pulse interval (d 00 ) pulse interval (10000h + d 01 ? d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the fr ee-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pu lse width can be calculated by reading the value of the tpnccrm register in synchronization with the inttpnccm si gnal, and calculat ing the difference between the read value and the previously read value. remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 307 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register tipn1 pin input tpnccr1 register inttpnov signal tpnovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tpnccr0 register (setting of t he default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the tipn1 pin input). <3> read the tpnccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tpnccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). remark n = 0 to 5 when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 308 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tpnce bit inttpnov signal tpnovf bit tpnovf0 flag note tipn0 pin input tpnccr0 register tpnovf1 flag note tipn1 pin input tpnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> read the tpnccr0 register (setting of t he default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the tipn1 pin input). <3> an overflow occurs. set the tpnovf0 and tpnovf 1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tpnccr0 register. read the tpnovf0 flag. if the tpnovf0 flag is 1, clear it to 0. because the tpnovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tpnccr1 register. read the tpnovf1 flag. if the tpnovf1 flag is 1, clear it to 0 (the tpnovf0 flag is cleared in <4>, and the tpnovf1 flag remains 1). because the tpnovf1 flag is 1, the puls e width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 309 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tpnce bit inttpnov signal tpnovf bit tpnovf0 flag note tipn0 pin input tpnccr0 register tpnovf1 flag note tipn1 pin input tpnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 l note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> read the tpnccr0 register (setting of t he default value of the tipn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the tipn1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tpnccr0 register. read the overflow flag. if the overflow flag is 1, set only the tpnovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tpnccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tpnovf1 flag. if the tpnovf1 flag is 1, clear it to 0. because the tpnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 310 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16- bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tpnce bit tipnm pin input tpnccrm register inttpnov signal tpnovf bit d m0 d m1 d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the tpnccrm register (setting of t he default value of the tipnm pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tpnccrm register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d m1 ? d m0 ) (incorrect). actually, the pulse width must be (20000h + d m1 ? d m0 ) because an overflow occurs twice. remark n = 0 to 5, m = 0, 1 if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 311 example when capture trigger interval is long ffffh 16-bit counter 0000h tpnce bit tipnm pin input tpnccrm register inttpnov signal tpnovf bit overflow counter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tpnccrm register (setting of t he default value of the tipnm pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tpnccrm register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d m1 ? d m0 ). in this example, the pulse width is (20000h + d m1 ? d m0 ) because an overflow occurs twice. clear the overflow counter (0h). remark n = 0 to 5, m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 312 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing t he tpnovf bit to 0 with the clr instruction after reading the tpnovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to t he tpnopt0 register after reading the tpnovf bit when it is 1. (3) note on capture operation when the capture operation is used and a slow clock is selected as the count clock, ffffh, not 0000h, may be captured in the tpnccrm register , or the capture operation may no t be performed (capture interrupt does not occur) if the capture trigger is input immedi ately after the tpnctl0.tpnce bit is set to 1. the same operation results during the period in which no external event counts are input while the capture operation is used and an external event count input is used as a count clock. count clock 0000h ffffh tpnce bit tpnccr0 register ffffh 0001h 0000h tipn0 pin input capture trigger input 16-bit counter sampling clock capture trigger input remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 313 7.6.7 pulse width measurement mode (tpnmd2 to tpnmd0 bits = 110) in the pulse width measurement mode, 16-bit timer/event counter p starts counting when the tpnctl0.tpnce bit is set to 1. each time the valid edge input to the tipnm pin has been detected, the count value of the 16-bit counter is stored in the tpnccrm register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by reading the tpnccrm register after a capture interrupt request signal (inttpnccm) occurs. for example, in case of figure 7-39, select either t he tipn0 or tipn1 pin as the capture trigger input pin, and specify ?no edge detected? by using the tpnioc1 register for the unused pins. figure 7-38. configuration in pulse width measurement mode tpnccr0 register (capture) tpnce bit tpnccr1 register (capture) count clock selection edge detector edge detector tipn0 pin (capture trigger input) tipn1 pin (capture trigger input) clear inttpnov signal inttpncc0 signal inttpncc1 signal 16-bit counter caution when in pulse width measurement mode, select the internal clock (set tpnctl1.tpneee bit = 0) as the count clock. remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 314 figure 7-39. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tpnce bit tipnm pin input tpnccrm register inttpnccm signal inttpnov signal tpnovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark n = 0 to 5 m = 0, 1 when the tpnce bit is set to 1, the 16- bit counter starts counting. when the valid edge input to the tipnm pin is later detected, the count value of the 16-bit counter is stored in the tpnccrm register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttpnccm) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tipnm pin even wh en the 16-bit counter counted up to ffffh, an overflow interrupt request signal (inttpnov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tpnopt0.t pnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tpnovf bit set (1) count + captured value) count clock cycle remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 315 figure 7-40. register setting in pu lse width measurement mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 00000 tpnctl1 110 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tpncks0 to tpncks2 bits (c) tmpn i/o control register 1 (tpnioc1) 0 0 0 0 0/1 tpnioc1 select valid edge of tipn0 pin input select valid edge of tipn1 pin input 0/1 0/1 0/1 tpnis2 tpnis1 tpnis0 tpnis3 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 316 figure 7-40. register setting in pu lse width measurement mode (2/2) (d) tmpn option register 0 (tpnopt0) 00000 tpnopt0 overflow flag 0 0 0/1 tpnccs0 tpnovf tpnccs1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) these registers store the count va lue of the 16-bit counter when the valid edge input to the tipnm pin is detected. remarks 1. tmpn i/o control register 0 (tpnioc0) and tmpn i/o control register 2 (tpnioc2) are not used in the pulse width measurement mode. 2. n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 317 (1) operation flow in pul se width measurement mode figure 7-41. software processing flow in pulse width measurement mode <1> <2> tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits), tpnctl1 register, tpnioc1 register, tpnopt0 register initial setting of these registers is performed before the tpnce bit is set to 1. the tpncks0 to tpncks2 bits can be set when counting starts (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tpnce bit tipn0 pin input tpnccr0 register inttpncc0 signal d 0 0000h 0000h d 1 d 2 remark n = 0 to 5 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 318 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing t he tpnovf bit to 0 with the clr instruction after reading the tpnovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to t he tpnopt0 register after reading the tpnovf bit when it is 1. (3) notes if a slow clock is selected as the count clock, ffffh , not 0000h, may be captured to the tpnccrm register, or the capture operation may not be per formed (capture interrupt does not occu r) if the capture trigger is input immediately after the tpnctl0.tpnce bit has been set to 1. count clock 0000h ffffh tpnce bit tpnccr0 register ffffh 0002h 0000h tipn0 pin input capture trigger input 16-bit counter sampling clock capture trigger input remark n = 0 to 5 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 319 7.7 selector function in the v850es/sg3, the tip input/rxd a input and the tiq input/tsout signal can be selected as the capture trigger input of tmp and tmq, respectively. by using this function, the following is possible. ? the tiq02 input signal of tmq0 c an be selected from the port/timer alter nate-function pins (tiq02 pin) and the tsout signal of the can controller. if the tsout signal of can0 is selected, the time stamp function of the can controller can be used. ? the tip10 and tip11 input signals of tmp1 can be sele cted from the port/timer alte rnate-function pins (tip10 and tip11 pins) and the uarta reception alter nate-function pins (rxda0 and rxda1). when the rxda0 or rxda1 signal of uart0 or uart1 is selected, the lin reception transfer rate and baud rate error of uarta can be calculated. cautions 1. when using the selector function, set the capture trigger input of tmp or tmq before connecting the timer. 2. when setting the selector function, firs t disable the peripheral i/o to be connected (tmp/uarta or tmq/can controller). the capture input for the selector functi on is specified by the following register. chapter 7 16-bit timer/event counter p (tmp) user?s manual u17728ej3v1ud 320 (1) selector operation control register 0 (selcnt0) the selcnt0 register is an 8-bit register that se lects the capture trigger for tmp1, tmp3, and tmq0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 selcnt0 0 0 isel4 isel3 0 0 isel0 tip11 pin input rxda1 pin input isel4 0 1 selection of tip11 input signal (tmp1) tip10 pin input rxda0 pin input isel3 0 1 selection of tip10 input signal (tmp1) tiq02 pin input tsout signal of can0 isel0 note 0 1 selection of tiq02 input signal (tmq0) after reset: 00h r/w address: fffff308h < > < > < > note the isel0 bit is valid only for the can controller version. cautions 1. to set the isel0, isel3, and isel4 bits to 1, set the corresponding pin in the capture input mode. 2. be sure to clear bits 7 to 5 and 2 and 1 to ?0?. user?s manual u17728ej3v1ud 321 chapter 8 16-bit timer/event counter q (tmq) timer q (tmq) is a 16-bit timer/event counter. the v850es/sg3 incorporates tmq0. 8.1 overview an outline of tmq0 is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 4 ? external event count input pin: 1 ? external trigger input pin: 1 ? timer/counter: 1 ? capture/compare registers: 4 ? capture/compare match interrupt request signals: 4 ? overflow interrupt request signal: 1 ? timer output pins: 4 8.2 functions tmq0 has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 322 8.3 configuration tmq0 includes the following hardware. table 8-1. configuration of tmq0 item configuration timer register 16-bit counter registers tmq0 capture/compare registers 0 to 3 (tq0ccr0 to tq0ccr3) tmq0 counter read buffer register (tq0cnt) ccr0 to ccr3 buffer registers timer inputs 4 (tiq00 note 1 to tiq03 pins) timer outputs 4 (toq00 to toq03 pins) control registers note 2 tmq0 control registers 0, 1 (tq0ctl0, tq0ctl1) tmq0 i/o control registers 0 to 2 (tq0ioc0 to tq0ioc2) tmq0 option register 0 (tq0opt0) notes 1. the tiq00 pin functions alternately as a capt ure trigger input signal, external event count input signal, and external trigger input signal. 2. when using the functions of the tiq00 to tiq03 and toq00 to toq03 pins, refer to table 4- 15 using port pin as alternate-function pin . figure 8-1. block diagram of tmq0 tq0cnt tq0ccr0 tq0ccr1 tq0ccr2 toq00 inttq0ov ccr2 buffer register tq0ccr3 ccr3 buffer register toq01 toq02 toq03 inttq0cc0 inttq0cc1 inttq0cc2 inttq0cc3 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tiq00 tiq01 tiq02 tiq03 selector internal bus internal bus selector edge detector ccr0 buffer register ccr1 buffer register 16-bit counter output controller clear remark f xx : main clock frequency chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 323 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tq0cnt register. when the tq0ctl0.tq0ce bit = 0, the va lue of the 16-bit counter is ffffh. if the tq0cnt register is read at this time, 0000h is read. reset sets the tq0ce bit to 0. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr0 register is used as a compare regist er, the value written to the tq0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttq0cc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tq0ccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr1 register is used as a compare regist er, the value written to the tq0ccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttq0cc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tq0ccr1 register is cleared to 0000h. (4) ccr2 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr2 register is used as a compare regist er, the value written to the tq0ccr2 register is transferred to the ccr2 buffer register. when the count value of the 16-bit counter matches the value of the ccr2 buffer register, a compare match interrupt request signal (inttq0cc2) is generated. the ccr2 buffer register cannot be read or written directly. the ccr2 buffer register is cleared to 0000h after reset, as the tq0ccr2 register is cleared to 0000h. (5) ccr3 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr3 register is used as a compare regist er, the value written to the tq0ccr3 register is transferred to the ccr3 buffer register. when the count value of the 16-bit counter matches the value of the ccr3 buffer register, a compare match interrupt request signal (inttq0cc3) is generated. the ccr3 buffer register cannot be read or written directly. the ccr3 buffer register is cleared to 0000h after reset, as the tq0ccr3 register is cleared to 0000h. (6) edge detector this circuit detects the valid edges input to the tiq 00 and tiq03 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tq0ioc1 and tq0ioc2 registers. (7) output controller this circuit controls the output of the toq00 to toq 03 pins. the output contro ller is controlled by the tq0ioc0 register. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 324 (8) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 325 8.4 registers the registers that control tmq0 are as follows. ? tmq0 control register 0 (tq0ctl0) ? tmq0 control register 1 (tq0ctl1) ? tmq0 i/o control register 0 (tq0ioc0) ? tmq0 i/o control register 1 (tq0ioc1) ? tmq0 i/o control register 2 (tq0ioc2) ? tmq0 option register 0 (tq0opt0) ? tmq0 capture/compare register 0 (tq0ccr0) ? tmq0 capture/compare register 1 (tq0ccr1) ? tmq0 capture/compare register 2 (tq0ccr2) ? tmq0 capture/compare register 3 (tq0ccr3) ? tmq0 counter read buffer register (tq0cnt) remark when using the functions of the tiq00 to tiq03 and toq00 to toq03 pins, refer to table 4-15 using port pin as alternate-function pin . chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 326 (1) tmq0 control register 0 (tq0ctl0) the tq0ctl0 register is an 8-bit register that controls the operation of tmq0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tq0ctl0 register by software. tq0ce tmq0 operation disabled (tmq0 reset asynchronously note ). tmq0 operation enabled. tmq0 operation started. tq0ce 0 1 tmq0 operation control tq0ctl0 0 0 0 0 tq0cks2 tq0cks1 tq0cks0 654321 after reset: 00h r/w address: fffff540h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tq0cks2 0 0 0 0 1 1 1 1 internal count clock selection tq0cks1 0 0 1 1 0 0 1 1 tq0cks0 0 1 0 1 0 1 0 1 note the tq0opt0.tq0ovf bit and 16-bit c ounter are reset at the same time. in addition, the timer output pins (toq00 to toq03 pins) are reset to the status set by the tq0ioc0 register when the 16-bit counter is reset. cautions 1. set the tq0cks2 to tq0 cks0 bits when the tq0ce bit = 0. when the value of the tq0ce bi t is changed from 0 to 1, the tq0cks2 to tq0cks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 327 (2) tmq0 control register 1 (tq0ctl1) the tq0ctl1 register is an 8-bit register that controls the operation of tmq0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 328 0 tq0est 0 1 software trigger control tq0ctl1 tq0est tq0eee 0 0 tq0md2 tq0md1 tq0md0 <6> <5> 4 3 2 1 after reset: 00h r/w address: fffff541h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tq0est bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tq0est bit as the trigger. disable operation with external event count input (tiq00 pin). (perform counting with the count clock selected by the tq0ctl0.tq0cks0 to tq0cks2 bits.) tq0eee 0 1 count clock selection the tq0eee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tq0md2 0 0 0 0 1 1 1 1 timer mode selection tq0md1 0 0 1 1 0 0 1 1 tq0md0 0 1 0 1 0 1 0 1 enable operation with external event count input (tiq00 pin). (perform counting at the valid edge of the external event count input signal.) ? the read value of tq0est bit is always 0. cautions 1. the tq0est bit is valid on ly in the external trigger pulse output mode or one-shot pulse output mode . in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tq0eee bit. 3. set the tq0eee and tq0md2 to tq0md0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) the op eration is not guaranteed when rewriting is performed with the tq0ce bit = 1. if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 4. be sure to clear bits 3, 4, and 7 to ?0?. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 329 (3) tmq0 i/o control register 0 (tq0ioc0) the tq0ioc0 register is an 8-bit register that controls the timer output (toq00 to toq03 pins). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tq0ol3 tq0olm 0 1 toq0m pin output level setting (m = 0 to 3) note toq0m pin high level start toq0m pin low level start tq0ioc0 tq0oe3 tq0ol2 tq0oe2 tq0ol1 tq0oe1 tq0ol0 tq0oe0 <6> 5 <4> 3 <2> 1 after reset: 00h r/w address: fffff542h tq0oem 0 1 toq0m pin output setting (m = 0 to 3) timer output disabled ? when tq0olm bit = 0: low level is output from the toq0m pin ? when tq0olm bit = 1: high level is output from the toq0m pin 7 <0> timer output enabled (a pulse is output from the toq0m pin). note the output level of the timer out put pin (toq0m) specified by the tq0olm bit is shown below. tq0ce bit toq0m pin output 16-bit counter ? when tq0olm bit = 0 tq0ce bit toq0m pin output 16-bit counter ? when tq0olm bit = 1 cautions 1. the pin output changes if the setting of the tq0ioc0 register is rewritten when the port is set to output toq0m. therefore, note changes in the pin status by setting the port in the input mode and making the output status of the pins a high- impedance state. 2. rewrite the tq0olm and tq0oem bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 3. even if the tq0olm bit is manipulated when the tq0ce and tq0oem bits are 0, the toq0 m pin output level varies. remark m = 0 to 3 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 330 (4) tmq0 i/o control register 1 (tq0ioc1) the tq0ioc1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (tiq00 to tiq03 pins). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tq0is7 tq0is7 0 0 1 1 tq0is6 0 1 0 1 capture trigger input signal (tiq03 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0ioc1 tq0is6 tq0is5 tq0is4 tq0is3 tq0is2 tq0is1 tq0is0 654321 after reset: 00h r/w address: fffff543h tq0is5 0 0 1 1 tq0is4 0 1 0 1 capture trigger input signal (tiq02 pin) valid edge detection no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 tq0is3 0 0 1 1 tq0is2 0 1 0 1 capture trigger input signal (tiq01 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0is1 0 0 1 1 tq0is0 0 1 0 1 capture trigger input signal (tiq00 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges cautions 1. rewrite the tq0is7 to tq0is0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. the tq0is7 to tq0is0 bi ts are valid only in the free- running timer mode (tq0opt0.tq0ccsm bit = 1 only) and the pulse width measurement mode (m = 0 to 3). in all other modes, a capture operation is not possible. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 331 (5) tmq0 i/o control register 2 (tq0ioc2) the tq0ioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tiq00 pin) and external trigger input signal (tiq00 pin). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tq0ees1 0 0 1 1 tq0ees0 0 1 0 1 external event count input signal (tiq00 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tq0ioc2 0 0 0 tq0ees1 tq0ees0 tq0ets1 tq0ets0 654321 after reset: 00h r/w address: fffff544h tq0ets1 0 0 1 1 tq0ets0 0 1 0 1 external trigger input signal (tiq00 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tq0ees1, tq0ees0, tq0ets1, and tq0ets0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. the tq0ees1 and tq0ees0 bits are valid only when the tq0ctl1.tq0eee bit = 1 or when the external event count mode (tq0ctl1.tq0md 2 to tq0ctl1.tq0md0 bits = 001) has been set. 3. the tq0ets1 and tq0ets0 bits are valid only when the external trigger pulse output mode (tq0ctl1.tq0md2 to tq0ctl1.tq0md0 bits = 010) or the one-shot pulse output mode (tq0ctl1.tq0 md2 to tq0ctl1.tq0md0 = 011) is set. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 332 (6) tmq0 option register 0 (tq0opt0) the tq0opt0 register is an 8-bit register used to set the capture/co mpare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tq0ccs3 tq0ccsm 0 1 tq0ccrm register capture/compare selection the tq0ccsm bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by setting the tq0ctl0.tq0ce bit = 0) tq0opt0 tq0ccs2 tq0ccs1 tq0ccs0 0 0 0 tq0ovf 654321 after reset: 00h r/w address: fffff545h tq0ovf set (1) reset (0) tmq0 overflow detection flag ? the tq0ovf bit is set to 1 when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an overflow interrupt request signal (inttq0ov) is generated at the same time that the tq0ovf bit is set to 1. the inttq0ov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tq0ovf bit is not cleared to 0 even when the tq0ovf bit or the tq0opt0 register are read when the tq0ovf bit = 1. ? before clearing the tq0ovf bit to 0 after the inttq0ov signal has been generated, be sure to confirm (read) that the tq0ovf bit is set to 1. ? the tq0ovf bit can be both read and written, but the tq0ovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmq0. overflow occurred tq0ovf bit 0 written or tq0ctl0.tq0ce bit = 0 7 <0> cautions 1. rewrite the tq0ccs 3 to tq0ccs0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3 to ?0?. remark m = 0 to 3 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 333 (7) tmq0 capture/compare register 0 (tq0ccr0) the tq0ccr0 register is a 16-bit r egister that can be used as a captur e register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tq0o pt0.tq0ccs0 bit. in the pulse width measurement mode, the tq0ccr0 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tq0ccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution accessing the tq0ccr0 register is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock tq0ccr0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff546h 14 0 13 11 9 7 5 3 15 1 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 334 (a) function as compare register the tq0ccr0 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttq0cc0) is generated. if toq00 pin output is e nabled at this time, the output of the toq00 pin is inverted. when the tq0ccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. the compare register is not cleared when the tq0ctl0.tq0ce bit = 0. (b) function as capture register when the tq0ccr0 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tq0ccr0 register if the valid ed ge of the capture trigger input pin (tiq00 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tq0ccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiq00 pin) is detected. even if the capture operation and reading the tq0c cr0 register conflict, the correct value of the tq0ccr0 register can be read. the capture register is cleared when the tq0ctl0.tq0ce bit = 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note triggered by writing to the tq0ccr1 register remark for anytime write and batch write, refer to 8.6 (2) anytime write and batch write . chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 335 (8) tmq0 capture/compare register 1 (tq0ccr1) the tq0ccr1 register is a 16-bit r egister that can be used as a captur e register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tq0o pt0.tq0ccs1 bit. in the pulse width measurement mode, the tq0ccr1 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tq0ccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution accessing the tq0ccr1 register is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock tq0ccr1 12 10 8 6 4 2 after reset: 0000h r/w address: fffff548h 14 0 13 11 9 7 5 3 15 1 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 336 (a) function as compare register the tq0ccr1 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttq0cc1) is generated. if toq01 pin output is e nabled at this time, the output of the toq01 pin is inverted. the compare register is not cleared when the tq0ctl0.tq0ce bit = 0. (b) function as capture register when the tq0ccr1 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tq0ccr1 register if the valid ed ge of the capture trigger input pin (tiq01 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tq0ccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiq01 pin) is detected. even if the capture operation and reading the tq0c cr1 register conflict, the correct value of the tq0ccr1 register can be read. the capture register is cleared when the tq0ctl0.tq0ce bit = 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note triggered by writing to the tq0ccr1 register remark for anytime write and batch write, refer to 8.6 (2) anytime write and batch write . chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 337 (9) tmq0 capture/compare register 2 (tq0ccr2) the tq0ccr2 register is a 16-bit r egister that can be used as a captur e register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tq0o pt0.tq0ccs2 bit. in the pulse width measurement mode, the tq0ccr2 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tq0ccr2 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution accessing the tq0ccr2 register is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock tq0ccr2 12 10 8 6 4 2 after reset: 0000h r/w address: fffff54ah 14 0 13 11 9 7 5 3 15 1 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 338 (a) function as compare register the tq0ccr2 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr2 register is transferred to the ccr2 buffer register. when the value of the 16-bit counter matches the value of the ccr2 buffer register, a compare match interrupt request signal (inttq0cc2) is generated. if toq02 pin output is e nabled at this time, the output of the toq02 pin is inverted. the compare register is not cleared when the tq0ctl0.tq0ce bit = 0. (b) function as capture register when the tq0ccr2 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tq0ccr2 register if the valid ed ge of the capture trigger input pin (tiq02 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tq0ccr2 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiq02 pin) is detected. even if the capture operation and reading the tq0c cr2 register conflict, the correct value of the tq0ccr2 register can be read. the capture register is cleared when the tq0ctl0.tq0ce bit = 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note triggered by writing to the tq0ccr1 register remark for anytime write and batch write, refer to 8.6 (2) anytime write and batch write . chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 339 (10) tmq0 capture/compare register 3 (tq0ccr3) the tq0ccr3 register is a 16-bit r egister that can be used as a captur e register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tq0o pt0.tq0ccs3 bit. in the pulse width measurement mode, the tq0ccr3 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tq0ccr3 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution accessing the tq0ccr3 register is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock tq0ccr3 12 10 8 6 4 2 after reset: 0000h r/w address: fffff54ch 14 0 13 11 9 7 5 3 15 1 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 340 (a) function as compare register the tq0ccr3 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr3 register is transferred to the ccr3 buffer register. when the value of the 16-bit counter matches the value of the ccr3 buffer register, a compare match interrupt request signal (inttq0cc3) is generated. if toq03 pin output is e nabled at this time, the output of the toq03 pin is inverted. the compare register is not cleared when the tq0ctl0.tq0ce bit = 0. (b) function as capture register when the tq0ccr3 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tq0ccr3 register if the valid ed ge of the capture trigger input pin (tiq03 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tq0ccr3 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tiq03 pin) is detected. even if the capture operation and reading the tq0c cr3 register conflict, the correct value of the tq0ccr3 register can be read. the capture register is cleared when the tq0ctl0.tq0ce bit = 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-5. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note triggered by writing to the tq0ccr1 register remark for anytime write and batch write, refer to 8.6 (2) anytime write and batch write . chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 341 (11) tmq0 counter read buffer register (tq0cnt) the tq0cnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tq0ctl0.tq0ce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tq0cnt register is cleared to 0000h wh en the tq0ce bit = 0. if the tq0cnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tq0cnt register is cleared to 000 0h after reset, as the tq0ce bit is cleared to 0. caution accessing the tq0cnt register is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock tq0cnt 12 10 8 6 4 2 after reset: 0000h r address: fffff54eh 14 0 13 11 9 7 5 3 15 1 8.5 timer output operations the following table shows the operations and out put levels of the toq00 to toq03 pins. table 8-6. timer output control in each mode operation mode toq00 pin toq 01 pin toq02 pin toq03 pin interval timer mode square wave output external event count mode none external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output pwm output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode none chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 342 table 8-7. truth table of toq00 to toq03 pins under control of timer output control bits tq0ioc0.tq0olm bit tq0ioc0.tq0oem bit tq0ctl0.tq0ce bit level of toq0m pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark m = 0 to 3 8.6 operation tmq0 can perform the following operations. operation tq0ctl1.tq0est bit (software trigger bit) tiq00 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count m ode, specify that the valid edge of the tiq00 pin capture trigger input is not detected (by clearing the tq0ioc1.tq 0is1 and tq0ioc1.tq0is0 bits to ?00?). 2. when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by cleari ng the tq0ctl1.tq0eee bit to 0). chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 343 (1) counter basic operation this section explains the basic oper ation of the 16-bit counter. for details, refer to the description of the operation in each mode. (a) counter start operation the 16-bit counter of tmq0 starts counti ng from the default value ffffh in all modes. it counts up from ffffh to 0000h, 0001h, 0002h, 0003h, and so on. (b) clear operation the 16-bit counter is cleared to 0000h when its value matches the value of the compare register and when its value is captured. the counting operation from ff ffh to 0000h that takes place immediately after the counter has started counting or when the counter overflows is not a clearing operation. therefore, the inttq0ccm interrupt signal is not generated (m = 0 to 3). (c) overflow operation the 16-bit counter overflows when the counter counts up from ffffh to 0000h in the free-running timer mode or pulse width measurement mode . if the counter overflows, the tq0opt0.tq0ovf bit is set to 1 and an interrupt request signal (inttq0ov) is generat ed. note that the inttq0ov signal is not generated under the following conditions. ? immediately after a count operation has been started ? if the counter value matches the compare value ffffh and is cleared ? when ffffh is captured in the pulse width measur ement mode and the counter counts up from ffffh to 0000h caution after the overflow interrupt request signa l (inttq0ov) has been generated, be sure to check that the overflow flag (tq0ovf bit) is set to 1. (d) counter read operation during counting operation the value of the 16-bit counter of tmq0 can be r ead by using the tq0cnt register during the count operation. when the tq0ctl0.tq0ce bit = 1, the val ue of the 16-bit counter c an be read by reading the tq0cnt register. when the tq0ce bit = 0, the 16- bit counter is ffffh and the tq0cnt register is 0000h. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 344 (e) interrupt operation tmq0 generates the following five interrupt request signals. ? inttq0cc0 interrupt: this signal functions as a match interrupt request signal of the ccr0 buffer register and as a capture interrupt re quest signal to the tq0ccr0 register. ? inttq0cc1 interrupt: this signal functions as a match interrupt request signal of the ccr1 buffer register and as a capture interrupt re quest signal to the tq0ccr1 register. ? inttq0cc2 interrupt: this signal functions as a match interrupt request signal of the ccr2 buffer register and as a capture interrupt re quest signal to the tq0ccr2 register. ? inttq0cc3 interrupt: this signal functions as a match interrupt request signal of the ccr3 buffer register and as a capture interrupt re quest signal to the tq0ccr3 register. ? inttq0ov interrupt: this signal functions as an overflow interrupt request signal. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 345 (2) anytime write and batch write the tq0ccr0 to tq0ccr3 registers can be rewritten in the tmq0 during timer operation (tq0ctl0.tq0ce bit = 1), but the write method (anytime write, batch wr ite) of the ccr0 to ccr3 buffer registers differs depending on the mode. (a) anytime write in this mode, data is transferred at any time from the tq0ccr0 to tq0ccr3 registers to the ccr0 to ccr3 buffer registers during the timer operation. figure 8-2. flowchart of basic operation for anytime write start initial settings ? set values to tq0ccrm register ? timer operation enable (tq0ce bit = 1) transfer values of tq0ccrm register to ccrm buffer register timer operation ? match between 16-bit counter and ccrk buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start inttq0cc0 signal output tq0ccrm register rewrite transfer to ccrm buffer register inttq0cck signal output note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccrk buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. remarks 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. k = 1 to 3 m = 0 to 3 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 346 figure 8-3. timing of anytime write tq0ce bit = 1 16-bit counter tq0ccr0 register tq0ccr1 register tq0ccr2 register tq0ccr3 register inttq0cc0 signal inttq0cc1 signal inttq0cc2 signal inttq0cc3 signal ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 11 d 11 d 12 d 11 d 11 d 12 d 12 d 21 d 21 d 21 d 01 d 01 d 02 d 02 d 01 d 12 d 21 0000h d 01 d 02 0000h d 21 d 31 0000h d 31 d 31 d 31 d 31 d 31 0000h ffffh remarks 1. d 01 , d 02 : setting values of tq0ccr0 register d 11 , d 12 : setting values of tq0ccr1 register d 21 : setting value of tq0ccr2 register d 31 : setting value of tq0ccr3 register 2. the above timing chart illustrates an example of the operation in the interval timer mode. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 347 (b) batch write in this mode, data is transferred all at once from the tq0ccr0 to tq0ccr3 registers to the ccr0 to ccr3 buffer registers during timer operation. this data is transferred upon a match between the value of the ccr0 buffer register and the value of the 16-bit counter. transfer is enabled by writing to the tq0ccr1 register. whether to enable or disable the next transfer timing is controlled by writing or not writing to the tq0ccr1 register. in order for the setting value when the tq0ccr0 to tq 0ccr3 registers are rewritten to become the 16-bit counter comparison value (in other words, in order fo r this value to be transferred to the ccr0 to ccr3 buffer registers), it is necessary to rewrite tq0ccr0 and finally write to the tq0ccr1 register before the 16-bit counter value and the ccr0 buffer register val ue match. the values of the tq0ccr0 to tq0ccr3 registers are transferred to the ccr0 to ccr3 buff er registers upon a match bet ween the count value of the 16-bit counter and the value of the ccr0 buffer register. thus, even when wishing only to rewrite the value of the tq0ccr0, tq0ccr2, or tq0ccr3 register, also write the same value (same as preset value of the tq0ccr1 register) to the tq0ccr1 register. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 348 figure 8-4. flowchart of basic operation for batch write start initial settings ? set values to tq0ccrm register ? timer operation enable (tq0ce bit = 1) transfer of values of tq0ccrm register to ccrm buffer register timer operation ? match between 16-bit counter and ccrk buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start ? transfer of values of tq0ccrk register to ccrk buffer register inttq0cck signal output tq0ccr0, tq0ccr2, tq0ccr3 register rewrite tq0ccr1 register rewrite inttq0cc0 signal output batch write enable note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccrk buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. caution writing to the tq0ccr1 regi ster includes enabling of batch wr ite. thus, rewrite the tq0ccr1 register after rewriting the tq0ccr0 , tq0ccr2, and tq0ccr3 registers. remarks 1. the above flowchart illustrates an example of the operation in the pwm output mode. 2. k = 1 to 3 m = 0 to 3 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 349 figure 8-5. timing of batch write tq0ce bit = 1 16-bit counter tq0ccr0 register tq0ccr1 register tq0ccr2 register tq0ccr3 register inttq0cc0 signal inttq0cc1 signal inttq0cc2 signal inttq0cc3 signal ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 d 02 d 03 0000h d 11 0000h d 21 d 12 d 21 d 12 0000h d 31 d 32 d 33 d 31 d 32 d 33 d 01 d 02 d 03 d 11 d 12 d 12 d 21 d 31 d 11 d 01 d 21 d 21 d 12 d 12 d 12 d 12 d 32 d 32 d 32 d 02 d 02 d 03 toq00 pin output toq01 pin output toq02 pin output toq03 pin output d 21 d 21 note 1 note 1 same value write 0000h ffffh note 1 note 1 note 1 note 1 note 1 note 1 note 2 note 3 d 21 d 21 notes 1. because the tq0ccr1 register was not rewritten, d 02 is not transferred. 2. because tq0ccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of the 16-bit ti mer and the value of the tq0ccr0 register (d 01 ). 3. because tq0ccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of the 16-bit ti mer and the value of the tq0ccr0 register (d 12 ). remarks 1. d 01 , d 02 , d 03 : setting values of tq0ccr0 register d 11 , d 12 : setting values of tq0ccr1 register d 21 : setting value of tq0ccr2 register d 31 , d 32 , d 33 : setting values of tq0ccr3 register 2. the above timing chart illustrates the opera tion in the pwm output mode as an example. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 350 8.6.1 interval timer mode (t q0md2 to tq0md0 bits = 000) in the interval timer mode, an interrupt request signal (inttq0cc0) is generated at the interval set by the tq0ccr0 register if the tq0c tl0.tq0ce bit is set to 1. a square wave with a duty factor of 50% whose half cycle is equal to the interval can be output from the toq00 pin. the tq0ccr1 to tq0ccr3 registers are not used in the interval timer mode. however, the set value of the tq0ccr1 to tq0ccr3 registers is transferred to the ccr1 to ccr3 buffer registers and, when the count value of the 16-bit counter matches the value of the ccr1 to ccr3 bu ffer registers, compare match interrupt request signals (inttq0cc1 to inttq0cc3) are generated. in addition, a square wave with a duty factor of 50%, which is inverted when the inttq0cc1 to inttq0cc3 signals are generat ed, can be output from the toq01 to toq03 pins. the value of the tq0ccr1 to tq0ccr3 registers c an be rewritten even while the timer is operating. figure 8-6. configuration of interval timer 16-bit counter output controller ccr0 buffer register tq0ce bit tq0ccr0 register count clock selection clear match signal toq00 pin inttq0cc0 signal figure 8-7. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 351 when the tq0ce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and the counter starts counting. at this time, the output of the toq00 pin is inverted. additionally, the set value of the tq0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, the output of the toq00 pin is in verted, and a compare match interrupt request signal (inttq0cc0) is generated. the interval can be calculated by the following expression. interval = (set value of tq0ccr0 register + 1) count clock cycle figure 8-8. register setting for in terval timer mode operation (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 note 00 tq0ctl1 0, 0, 0: interval timer mode 000 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0: operate on count clock selected by tq0cks0 to tq0cks2 bits 1: count with external event count input signal note the tq0eee bit can be set to 1 only when the time r output (toq0k) is used. however, the tq0ccr0 and tq0ccrk registers must be set to the same value (k = 1 to 3). chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 352 figure 8-8. register setting for in terval timer mode operation (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output 1: enable toq00 pin output setting of toq00 pin output before count operation 0: low level 1: high level 0: disable toq01 pin output 1: enable toq01 pin output setting of toq01 pin output before count operation 0: low level 1: high level 0/1 0/1 0/1 tq0oe1 tq0ol0 tq0oe0 tq0ol1 0: disable toq02 pin output 1: enable toq02 pin output setting of toq02 pin output before count operation 0: low level 1: high level 0: disable toq03 pin output 1: enable toq03 pin output setting of toq03 pin output before count operation 0: low level 1: high level tq0oe3 tq0ol2 tq0oe2 tq0ol3 (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 note tq0ioc2 0/1 note 00 tq0ees0 tq0ets1 tq0ets0 tq0ees1 select valid edge of external event count input (tiq00 pin). note the tq0ees1 and tq0ees0 bits can be set onl y when timer outputs (toq01 to toq03) are used. however, set the tq0ccr0 to tq0ccr3 registers to the same value. (e) tmq0 counter read buffer register (tq0cnt) by reading the tq0cnt register, the count va lue of the 16-bit counter can be read. (f) tmq0 capture/compare register 0 (tq0ccr0) if the tq0ccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 353 figure 8-8. register setting for in terval timer mode operation (3/3) (g) tmq0 capture/compare regist ers 1 to 3 (tq0ccr1 to tq0ccr3) the tq0ccr1 to tq0ccr3 registers ar e not used in the interval timer mode. however, the set value of the tq0ccr1 to tq0ccr3 registers are transferred to the ccr1 to ccr3 buffer registers. the toq01 to toq03 pin outputs are inverted and compare ma tch interrupt request signals (inttq0cc1 to inttq0cc3) are generated when the count value of t he 16-bit counter matches the value of the ccr1 to ccr3 buffer registers. when the tq0ccr1 to tq0ccr3 registers are not us ed, it is recommended to set their values to ffffh. also mask the registers by the in terrupt mask flags (tq0ccic1.tq0ccmk1 to tq0ccic3.tq0ccmk3). remark tmq0 i/o control register 1 (tq0ioc1) and tm q0 option register 0 (tq0opt0) are not used in the interval timer mode. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 354 (1) interval timer mode operation flow figure 8-9. software processing flow in interval timer mode tq0ce bit = 1 tq0ce bit = 0 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register note , tq0ccr0 register initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). the counter is initialized and counting is stopped by clearing the tq0ce bit to 0. the output level of the toq00 pin is as specified by the tq0ioc0 register. start stop <1> count operation start flow <2> count operation stop flow d 0 <1> <2> d 0 d 0 d 0 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal note the tq0ees1 and tq0ees0 bits can be set only when timer output (toq0k) is used. however, set the tq0ccr0 and tq0ccrk registers to the same value (k = 1 to 3). chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 355 (2) interval timer mode operation timing (a) operation if tq0ccr0 re gister is set to 0000h if the tq0ccr0 register is set to 0000h, the inttq0cc0 signal is generated at each count clock, and the output of the toq00 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h (b) operation if tq0ccr0 re gister is set to ffffh if the tq0ccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing. the inttq0cc0 signal is generated and the output of the toq00 pin is inverted. at this time, an overflow interrupt request signal (inttq0ov) is not generated, nor is the overflow flag (tq0opt0.tq0ovf bit) set to 1. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 356 (c) notes on rewriting tq0ccr0 register if the value of the tq0ccr0 register is rewritten to a smaller value duri ng counting, the 16-bit counter may overflow. if there is a possibility of overfl ow, stop counting and then change the set value. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register tq0ol0 bit toq00 pin output inttq0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remark interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle if the value of the tq0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tq0ccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttq0cc0 signal is generated and the output of the toq00 pin is inverted. therefore, the inttq0cc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 357 (d) operation of tq0ccr1 to tq0ccr3 registers figure 8-10. configuration of tq0ccr1 to tq0ccr3 registers ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal tq0ccr3 register ccr3 buffer register match signal toq02 pin inttq0cc2 signal tq0ccr2 register ccr2 buffer register match signal output controller count clock selection output controller output controller output controller 16-bit counter chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 358 if the same value as the set value of the tq0ccr0 register is set to the tq0ccrk register, the inttq0cck signal is generated together with the inttq 0cc0 signal, and the output of the toq0k pin is inverted. this means that a square wave with a dut y factor of 50% can be output from the toq0k pin. if a value different from the set value of the tq0c cr0 register is set to the tq0ccrk register, the operation is as follows. if the set value of the tq0ccrk register is less than the set value of the tq0ccr0 register, the inttq0cck signal is generated once per cycle. at t he same time, the output of the topq0k pin is inverted. the toq0k pin outputs a square wave with a duty factor of 50% after it first outputs a short-width pulse. remark k = 1 to 3 figure 8-11. timing chart when d 01 d k1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal tq0ccr1 register toq01 pin output inttq0cc1 signal tq0ccr2 register toq02 pin output inttq0cc2 signal tq0ccr3 register toq03 pin output inttq0cc3 signal chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 359 if the set value of the tq0ccrk regi ster is greater than the set value of the tq0ccr0 register, the count value of the 16-bit counter does not match the value of the tq0ccr k register. consequently, the inttq0cck signal is not generated, nor is the output of the toq0k pin changed. it is recommended to set ffffh to t he tq0ccrk register when the tq0ccrk register is not used. remark k = 1 to 3 figure 8-12. timing chart when d 01 < d k1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq00 pin output inttq0cc0 signal tq0ccr1 register toq01 pin output inttq0cc1 signal tq0ccr2 register toq02 pin output inttq0cc2 signal tq0ccr3 register toq03 pin output inttq0cc3 signal chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 360 (3) operation by external event count input (tiq00) (a) operation to count the 16-bit counter at the va lid edge of external event count input (tiq00) in the interval timer mode, the valid edge of the external event count input is necessary once because the 16-bit counter is cleared from ffffh to 0000h immediately afte r the tq0ce bit is set from 0 to 1. when 0001h is set to both the tq0ccr0 and tq0ccrk registers, the output of the toq0k pins is inverted each time the 16-bit counter counts twice (k = 1 to 3). the tq0ctl0.tq0eee bit can be set to 1 in the inte rval timer mode only when the timer output (toq0k) is used with the external event count input. tq0ce bit 16-bit counter tq0ccr0 register toq01 pin output tq0ccr1 register toq02 pin output tq0ccr2 register toq03 pin output tq0ccr3 register ffffh 0000h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h external event count input (tiq00 pin input) number of external event count: 3 number of external event count: 2 number of external event count: 2 2-count width 2-count width 2-count width chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 361 8.6.2 external event count mode (tq0md2 to tq0md0 bits = 001) in the external event count mode, t he valid edge of the external event c ount input (tiq00) is counted when the tq0ctl0.tq0ce bit is set to 1, and an interrupt request signal (inttq0cc0) is generated each time the specified number of edges set by the tq0ccr0 register have be en counted. the toq00 to toq03 pins cannot be used. when using the toq01 and toq03 pins for external event count input, set the tq0ctl1.tq0eee bit to 1 in the interval timer mode (see 8.6.1 (3) operation by external event count input (tiq00) ). the tq0ccr1 to tq0ccr3 registers are not used in the external event count mode. caution in the external event count mode, the tq0 ccr0 to tq0ccr3 registers must not be cleared to 0000h. figure 8-13. configuration in external event count mode 16-bit counter ccr0 buffer register tq0ce bit tq0ccr0 register edge detector clear match signal inttq0cc0 signal tiq00 pin (external event count input) chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 362 figure 8-14. basic timing in external event count mode ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal d 0 d 0 d 0 d 0 16-bit counter tq0ccr0 register nttq0cc0 signal external event count input (tiq00 pin input) d 0 number of external event count (d 0 ) times note d 0 ? 1d 0 0000 0001 number of external event count (d 0 + 1) times number of external event count (d 0 + 1) times note in the external event count mode, the 16-bit c ounter is cleared from ffffh to 0000h as soon as the tq0ctl0.tq0ce bit has been set (1) (operation is started). the first counting operation is started from 0001h each time the valid edge of t he external event count input has been detected. therefore, the number of counts of the first counting operation is one less than that of the second counting operation. remark this figure shows the basic timing when the risi ng edge is specified as the valid edge of the external event count input. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 363 when the tq0ce bit is set to 1, the value of the 16-bit count er is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detec ted. additionally, the set value of the tq0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttq0cc0) is generated. the inttq0cc0 signal is generated for the first time when the valid edge of the external event count input has been detected ?value set to tq0ccr0 register? times. a fter that, the inttq0cc0 signal is generated each time the valid edge of the external event count has been detec ted ?value set to tq0ccr0 register + 1? times. figure 8-15. register setting for operati on in external event count mode (1/2) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 0: stop counting 1: enable counting 000 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 00000 tq0ctl1 0, 0, 1: external event count mode 001 tq0md2 tq0md1 tq0md0 tq0eee tq0est (c) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input (tiq00 pin) 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 364 figure 8-15. register setting for operati on in external event count mode (2/2) (d) tmq0 counter read buffer register (tq0cnt) the count value of the 16-bit counter can be read by reading the tq0cnt register. (e) tmq0 capture/compare register 0 (tq0ccr0) if the tq0ccr0 register is set to d 0 , the count is cleared when the number of external events has reached (d 0 ) and the first compare match interrupt request signal (inttq0cc0) is generated. the second compare match interrupt request signal (inttq0cc0) is generated when the number of external events has reached (d 0 + 1). (f) tmq0 capture/compare register s 1 to 3 (tq0ccr1 to tq0ccr3) usually, the tq0ccr1 to tq0ccr3 registers are not us ed in the external event count mode. however, the set value of the tq0ccr1 to tq0ccr3 regist ers are transferred to the ccr1 to ccr3 buffer registers. when the count value of the 16-bit counter matches the value of the ccr1 to ccr3 buffer registers, compare match interrupt request si gnals (inttq0cc1 to inttq0cc3) are generated. when the tq0ccr1 to tq0ccr3 registers are not us ed, it is recommended to set their values to ffffh. also mask the interrupt signal by using the interrupt mask flags (tq0ccic1.tq0ccmk1 to tq0ccic3.tq0ccmk3). cautions 1. set the tq0ioc0 register to 00h. 2. when an external clock is used as the count clock, the external clock can be input only from the tiq00 pin. at this time, set the tq0ioc1.tq0is1 and tq0ioc1.tq0is0 bits to 00 (capture trigger input (tiq00 pin): no edge detection). remark the tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the external event count mode. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 365 (1) external event count mode operation flow figure 8-16. flow of software processing in external event count mode ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal d 0 d 0 d 0 d 0 <1> <2> tq0ce bit = 1 tq0ce bit = 0 initial setting of tq0ctl1 register, tq0ioc2 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. the counter is initialized and counting is stopped by clearing the tq0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 366 (2) operation timing in external event count mode cautions 1. in the external e vent count mode, setting the tq0ccr0 to tq0ccr3 registers to 0000h is disabled. 2. in the external event count mode, use of th e timer output (toq00 to toq03) is disabled. if performing external event count input (tiq00) using the timer outputs (toq01 to toq03), set the interval timer mode to enable the count clock operation (tq0ctl1.tq0eee bit = 1) for the external event count input (refer to 8.6.1 (3) operation by external event count input (tiq00)). (a) operation if tq0ccr0 re gister is set to ffffh if the tq0ccr0 register is set to ffffh, the 16-bit counter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the in ttq0cc0 signal is generated. at this time, the tq0opt0.tq0ovf bit is not set. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal ffffh number of external event count ffffh times number of external event count 10000h times number of external event count 10000h times chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 367 (b) notes on rewriting the tq0ccr0 register if the value of the tq0ccr0 register is rewritten to a smaller value duri ng counting, the 16-bit counter may overflow. if there is a possibility of overfl ow, stop counting and then change the set value. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 number of external event count (1) (d 1 ) times number of external event count (ng) (10000h + d 2 + 1) times number of external event count (2) (d 2 + 1) times if the value of the tq0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tq0ccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttq0cc0 signal is generated. therefore, the inttq0cc0 signal may not be generated at the valid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 368 (c) operation of tq0ccr1 to tq0ccr3 registers figure 8-17. configuration of tq0ccr1 to tq0ccr3 registers ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal inttq0cc3 signal tiq00 pin (external event count input) tq0ccr1 register ccr1 buffer register match signal inttq0cc1 signal tq0ccr3 register ccr3 buffer register match signal inttq0cc2 signal tq0ccr2 register ccr2 buffer register match signal 16-bit counter edge detector chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 369 if the set value of the tq0ccrk register is smalle r than the set value of the tq0ccr0 register, the inttq0cck signal is generated once per cycle. remark k = 1 to 3 figure 8-18. timing chart when d 01 d k1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal tq0ccr1 register inttq0cc1 signal tq0ccr2 register inttq0cc2 signal tq0ccr3 register inttq0cc3 signal chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 370 if the set value of the tq0ccrk regi ster is greater than the set va lue of the tq0ccr0 register, the inttq0cck signal is not generated because the count va lue of the 16-bit counter and the value of the tq0ccrk register do not match. it is recommended to set ffffh to the tq0ccrk register when the tq 0ccrk register is not used. remark k = 1 to 3 figure 8-19. timing chart when d 01 < d k1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal tq0ccr1 register inttq0cc1 signal tq0ccr2 register inttq0cc2 signal tq0ccr3 register inttq0cc3 signal chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 371 8.6.3 external trigger pulse output m ode (tq0md2 to tq0md0 bits = 010) in the external trigger pulse output mode, 16-bit ti mer/event counter q waits for a trigger when the tq0ctl0.tq0ce bit is set to 1. when the valid edge of an external trigger i nput signal (tiq00) is detected, 16-bit timer/event counter q starts counting, and output s a pwm waveform from the toq01 to toq03 pins. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a square wave with a duty factor of 50% wh ose half cycle is the set val ue of the tq0ccr0 register + 1 can also be output from the toq00 pin. figure 8-20. configuration in external trigger pulse output mode ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin note tiq00 pin note (external trigger input) transfer s r tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal transfer transfer s r tq0ccr3 register ccr3 buffer register match signal transfer toq02 pin inttq0cc2 signal s r tq0ccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control edge detector software trigger generation output controller (rs-ff) output controller output controller (rs-ff) output controller note because the external trigger input pin (tiq00) and timer output pin (toq00) share the same alternate- function pin, two functions cannot be used at the same time. caution in external trigger pulse output mode, select the internal clock (set the tq0ctl1.tq0eee bit = 0) as the count clock. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 372 figure 8-21. basic timing in exte rnal trigger pulse output mode d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 1 d 2 d 3 active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 3 ) active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) wait for trigger active level width (d 3 ) cycle (d 0 + 1) ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register inttq0cc0 signal toq00 pin output (only when software trigger is used) tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) d 0 d 1 d 3 d 2 d 0 d 0 d 0 d 0 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 373 16-bit timer/event counter q waits for a trigger when the tq0ce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing at the same time, and out puts a pwm waveform from the toq0k pin. if the trigger is generated again while the counter is operating, the c ounter is cleared to 0000h and restarted. (the output of th e toq00 pin is inverted. the toq0k pin out puts a high-level regardless of low-level output period and high-level output per iod statuses when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tq0ccrk register) count clock cycle cycle = (set value of tq0ccr0 register + 1) count clock cycle duty factor = (set value of tq0ccrk regist er)/(set value of tq0ccr0 register + 1) the compare match request signal inttq0 cc0 is generated when the 16-bit c ounter counts next time after its count value matches the value of the c cr0 buffer register, and the 16-bit count er is cleared to 0000h. the compare match interrupt request signal inttq0cck is generated when the count value of the 16-bit counter matches the value of the ccrk buffer register. the value set to the tq0ccrm register is transferred to the ccrm buffer register w hen the count value of the 16- bit counter matches the value of the ccr0 buffer re gister and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal (tiq00), or setting the software trigger (tq0ctl1.tq0est bit) to 1 is used as the trigger. remark k = 1 to 3 m = 0 to 3 figure 8-22. setting of registers in exte rnal trigger pulse output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 374 figure 8-22. setting of registers in exte rnal trigger pulse output mode (2/3) (b) tmq0 control register 1 (tq0ctl1) 0 0/1 0 0 0 tq0ctl1 0: operate on count clock selected by tq0cks0 to tq0cks2 bits generate software trigger when 1 is written 010 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0, 1, 0: external trigger pulse output mode (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output 1: enable toq00 pin output setting of toq00 pin output level in status of waiting for external trigger 0: low level 1: high level 0: disable toq01 pin output 1: enable toq01 pin output setting of toq01 pin output level in status of waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 toq0k pin output 16-bit counter ? when tq0olk bit = 0 toq0k pin output 16-bit counter ? when tq0olk bit = 1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 setting of toq03 pin output level in status of waiting for external trigger 0: low level 1: high level 0: disable toq02 pin output 1: enable toq02 pin output setting of toq02 pin output level in status of waiting for external trigger 0: low level 1: high level 0: disable toq03 pin output 1: enable toq03 pin output note clear this bit to 0 when the toq00 pin is not used in the external trigger pulse output mode. chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 375 figure 8-22. setting of registers in exte rnal trigger pulse output mode (3/3) (d) tmq0 i/o control register 2 (tq0ioc2) 00000 tq0ioc2 select valid edge of external trigger input (tiq00 pin) 0 0/1 0/1 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) if d 0 is set to the tq0ccr0 register, d 1 to the tq0ccr1 register, d 2 to the tq0ccr2 register, and d 3 , to the tq0ccr3 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle toq01 pin pwm waveform active level width = d 1 count clock cycle toq02 pin pwm waveform active level width = d 2 count clock cycle toq03 pin pwm waveform active level width = d 3 count clock cycle remarks 1. tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the external trigger pulse output mode. 2. updating tmq0 capture/compare register 2 (tq0ccr2) and tmq0 capture/compare register 3 (tq0ccr3) is validated by writing tmq0 capture/compare register 1 (tq0ccr1). chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 376 (1) operation flow in extern al trigger pulse output mode figure 8-23. software processing flow in ex ternal trigger pulse output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register ccr0 buffer register inttq0cc0 signal toq00 pin output (only when software trigger is used) tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 11 d 20 d 10 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 377 figure 8-23. software processing flow in ex ternal trigger pulse output mode (2/2) start <1> count operation start flow tq0ce bit = 1 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. writing of the tq0ccr1 register must be performed when the set duty factor is only changed after writing the tq0ccr2 and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. tq0ccr1 register writing of the same value (same as the tq0ccr1 register already set) is necessary only when the set duty factor of toq02 and toq03 pin outputs is changed. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. only writing of the tq0ccr1 register must be performed when the set duty factor is only changed. when counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. counting is stopped. the tq0cks0 to tq0cks2 bits can be set at the same time when counting is enabled (tq0ce bit = 1). trigger wait status writing of the tq0ccr1 register must be performed after writing the tq0ccr0, tq0ccr2, and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer registers. tq0ccr1 register writing of the same value (same as the tq0ccr1 register already set) is necessary only when the set cycle is changed. <2> tq0ccr0 to tq0ccr3 register setting change flow <3> tq0ccr0 register setting change flow <4> tq0ccr1 to tq0ccr3 register setting change flow <5> tq0ccr2, tq0ccr3 register setting change flow <6> tq0ccr1 register setting change flow <7> count operation stop flow tq0ce bit = 0 setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register stop setting of tq0ccr1 register setting of tq0ccr0 register setting of tq0ccr1 register setting of tq0ccr0, tq0ccr2, and tq0ccr3 registers tq0ccr1 register when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. remark m = 0 to 3 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 378 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tq0ccr1 register last. rewrite the tq0ccrk register after writing the tq0ccr1 register after the inttq0cc0 signal is detected. ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tq0ccr0 register ccr0 buffer register inttq0cc0 signal tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output toq00 pin output (only when software trigger is used) d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 379 in order to transfer data from the tq0ccrm register to the ccrm buffer register, the tq0ccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tq0ccr0 register, set the active level width to t he tq0ccr2 and tq0ccr3 registers, and then set an active level to the tq0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tq0ccr0 register, and then write the same value (same as the tq0ccr1 regist er already set) to the tq0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, first set an active level to the tq0ccr2 and tq0ccr3 registers and then set an active level to the tq0ccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the toq01 pin, only the tq0ccr1 register has to be set. to change only the active level width (duty factor) of the pwm waveform output by the toq02 and toq03 pins, first set an active level width to the tq0 ccr2 and tq0ccr3 registers, and then write the same value (same as the tq0ccr1 register already set) to the tq0ccr1 register. after data is written to the tq0ccr1 register, the value written to the tq0ccrm register is transferred to the ccrm buffer register in synchronization with clear ing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tq0ccr0 to tq0ccr3 registers again afte r writing the tq0ccr1 register once, do so after the inttq0cc0 signal is generated. otherwise, t he value of the ccrm buffer register may become undefined because timing of transferring data from t he tq0ccrm register to the ccrm buffer register conflicts with writing the tq0ccrm register. remark m = 0 to 3 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 380 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tq0ccrk register to 0000h. the 16-bit counter is cleared to 0000h and the inttq0cc0 and inttq0cck signals are generated at the next timing after a match between the count value of the 16-bit counter and t he value of the ccr0 buffer register. count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output external trigger input (tiq00 pin input) d 0 l 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3 to output a 100% waveform, set a value of (set value of tq0ccr0 register + 1) to the tq0ccrk register. if the set value of the tq0ccr0 register is ffffh, 100% output cannot be produced. d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 ? 1d 0 ? 1 external trigger input (tiq00 pin input) l remark k = 1 to 3 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 381 (c) conflict between trigger detection and match with ccrk buffer register if the trigger is detected immediately after the inttq 0cck signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of t he toq0k pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccrk buffer register inttq0cck signal toq0k pin output external trigger input (tiq00 pin input) d k d k ? 1 0000 ffff 0000 shortened d k remark k = 1 to 3 if the trigger is detected immediately before the in ttq0cck signal is generated, the inttq0cck signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. t he output signal of the toq0k pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter ccrk buffer register inttq0cck signal toq0k pin output external trigger input (tiq00 pin input) d k d k ? 2d k ? 1d k 0000 ffff 0000 0001 extended remark k = 1 to 3 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 382 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the inttq 0cc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the toq0k pin is extended by time from generation of the inttq0cc0 signal to trigger detection. 16-bit counter ccr0 buffer register inttq0cc0 signal toq0k pin output external trigger input (tiq00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark k = 1 to 3 if the trigger is detected immediately before the in ttq0cc0 signal is generated, the inttq0cc0 signal is not generated. the 16-bit counter is cleared to 0000h, the toq0k pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter ccr0 buffer register inttq0cc0 signal toq0k pin output external trigger input (tiq00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark k = 1 to 3 chapter 8 16-bit timer/event counter q (tmq) user?s manual u17728ej3v1ud 383 (e) generation timing of compare match interrupt request signal (inttq0cck) the timing of generation of the inttq0cck signal in the external trigger pulse output mode differs from the timing of other mode inttq0cck signals; the inttq 0cck signal is generated when the count value of the 16-bit counter matches the value of the ccrk buffer register. count clock 16-bit counter ccrk buffer register toq0k pin output inttq0cck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 remark k = 1 to 3 usually, the inttq0cck signal is generated in synchro nization with the next count up after the count value of the 16-bit counter matches the va lue of the ccrk buffer register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the toq0k pin. chapter 8 16-bit timer/event counter q (tmq) 8.6.4 one-shot pulse output mode (tq0md2 to tq0md0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter q waits for a trigger when the tq0ctl0.tq0ce bit is set to 1. when the valid edge of an external trigger in put (tiq00) is detected, 16-bit timer/event counter q starts counting, and outputs a one-shot pulse from the toq01 to toq03 pins. instead of the external trigger input (tiq00), a software trigger can also be generated to output the pulse. when the software trigger is used, the toq 00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 8-24. configuration in one-shot pulse output mode s r s r s r s r ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin note transfer tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal transfer transfer tq0ccr3 register ccr3 buffer register match signal transfer toq02 pin inttq0cc2 signal tq0ccr2 register ccr2 buffer register match signal 16-bit counter count start control edge detector software trigger generation output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) tiq00 pin note (external trigger input) count clock selection note because the external trigger input pin (tiq00) and timer output pin (toq00) share the same alternate- function pin, two functions cannot be used at the same time. caution in one-shot pulse output m ode, select the internal clock (set the tq0ctl1.tq0eee bit = 0) as the count clock. chapter 8 16-bit timer/event counter q (tmq) figure 8-25. basic timing in one-shot pulse output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register inttq0cc0 signal tq0ccr1 register inttq0cc1 signal toq01 pin output toq00 pin output (only when software trigger is used) tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output user?s manual u17728ej3v1ud 385 chapter 8 16-bit timer/event counter q (tmq) when the tq0ce bit is set to 1, 16-bit timer/event counter q waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counti ng, and outputs a o ne-shot pulse from the toq0k pin. after the one-shot pulse is output, the 16 -bit counter is set to 0000h, stops count ing, and waits for a trigger. after the one-shot pulse is output, the 16-bit counter is set to 0000h, stops counting, and waits for a trigger. when the trigger is generated again, the 16-bit counter starts counting from 0000h. if a trigger is generated again while the one-shot pulse is being output, it is ignored. chapter 8 16-bit timer/event counter q (tmq) figure 8-26. register setting in one-shot pulse output mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) toq0k pin output 16-bit counter ? when tq0olk bit = 0 toq0k pin output 16-bit counter ? when tq0olk bit = 1 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output 1: enable toq00 pin output setting of toq00 pin output level in status of waiting for external trigger 0: low level 1: high level 0: disable toq01 pin output 1: enable toq01 pin output setting of toq01 pin output level in status of waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 setting of toq03 pin output level in status of waiting for external trigger 0: low level 1: high level 0: disable toq02 pin output 1: enable toq02 pin output setting of toq02 pin output level in status of waiting for external trigger 0: low level 1: high level 0: disable toq03 pin output 1: enable toq03 pin output note clear this bit to 0 when the toq00 pin is not used in the one-shot pulse output mode. (d) tmq0 i/o control register 2 (tq0ioc2) 00000 tq0ioc2 select valid edge of external trigger input (tiq00 pin) 0 0/1 0/1 tq0ees0 tq0ets1 tq0ets0 tq0ees1 chapter 8 16-bit timer/event counter q (tmq) figure 8-26. register setting in one-shot pulse output mode (3/3) (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) if d 0 is set to the tq0ccr0 register and d k to the tq0ccrk register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 0 ? d k + 1) count clock cycle output delay period = d k count clock cycle caution one-shot pulses are not output even in the one-shot pulse outpu t mode, if the value set in the tq0ccrk register is greater than that set in the tq0ccr0 register. remarks 1. tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the one-shot pulse output mode. 2. k = 1 to 3 user?s manual u17728ej3v1ud 388 chapter 8 16-bit timer/event counter q (tmq) (1) operation flow in one-shot pulse output mode figure 8-27. software processing flow in one-shot pulse output mode (1/2) ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register inttq0cc0 signal tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output toq00 pin output (only when software trigger is used) d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30 d 10 d 20 d 30 d 11 d 21 d 31 d 00 d 01 <3> <1> <2> user?s manual u17728ej3v1ud 389 chapter 8 16-bit timer/event counter q (tmq) figure 8-27. software processing flow in one-shot pulse output mode (2/2) tq0ce bit = 1 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). trigger wait status start <1> count operation start flow tq0ce bit = 0 count operation is stopped stop <3> count operation stop flow setting of tq0ccr0 to tq0ccr3 registers as rewriting the tq0ccrm register immediately forwards to the ccrm buffer register, rewriting immediately after the generation of the inttq0cc0 signal is recommended. <2> tq0ccr0 to tq0ccr3 register setting change flow remark m = 0 to 3 user?s manual u17728ej3v1ud 390 chapter 8 16-bit timer/event counter q (tmq) (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tq0ccrm register if the value of the tq0ccr0 register is rewritten to a smaller value duri ng counting, the 16-bit counter may overflow. if there is a possibility of overfl ow, stop counting and then change the set value. d k0 d k1 d 01 d 01 d 00 d k1 d 01 d k0 d k0 d k1 d 00 d 00 ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq00 pin input) tq0ccr0 register inttq0cc0 signal tq0ccrk register inttq0cck signal toq0k pin output toq00 pin output (only when software trigger is used) delay (d k0 ) active level width (d 0 - d k0 + 1) active level width (d 01 - d k1 + 1) active level width (d 01 - d k1 + 1) delay (d k1 ) delay (10000h + d k1 ) when the tq0ccr0 register is rewritten from d 00 to d 01 and the tq0ccrk register from d k0 to d k1 where d 00 > d 01 and d k0 > d k1 , if the tq0ccrk register is rewritten when the count value of the 16-bit counter is greater than d k1 and less than d k0 and if the tq0ccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter counts up to ffffh and then counts up again from 0000h. when the count value matches d k1 , the counter generates the inttq0cck signal and asserts the toq0k pin. when the count value matches d 01 , the counter generates the inttq0cc0 signal, deasserts the toq0k pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark m = 0 to 3 k = 1 to 3 user?s manual u17728ej3v1ud 391 chapter 8 16-bit timer/event counter q (tmq) (b) generation timing of compare match interrupt request signal (inttq0cck) the generation timing of the inttq0cck signal in the one-shot pulse out put mode is different from other mode inttq0cck signals; the inttq0cck signal is genera ted when the count val ue of the 16-bit counter matches the value of the tq0ccrk register. count clock 16-bit counter tq0ccrk register toq0k pin output inttq0cck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 usually, the inttq0cck signal is generated when the 16- bit counter counts up next time after its count value matches the value of the tq0ccrk register. in the one-shot pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the toq0k pin. remark k = 1 to 3 user?s manual u17728ej3v1ud 392 chapter 8 16-bit timer/event counter q (tmq) 8.6.5 pwm output mode (tq0md 2 to tq0md0 bits = 100) in the pwm output mode, a pwm waveform is output fr om the toq01 to toq03 pi ns when the tq0ctl0.tq0ce bit is set to 1. in addition, a square wave with a duty factor of 50% with the set value of the tq0ccr0 register + 1 as half its cycle is output from the toq00 pin. figure 8-28. configuration in pwm output mode ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal inttq0cc0 signal toq03 pin inttq0cc3 signal toq00 pin note transfer s r tq0ccr1 register ccr1 buffer register match signal toq01 pin inttq0cc1 signal transfer transfer s r tq0ccr3 register ccr3 buffer register match signal transfer toq02 pin inttq0cc2 signal s r tq0ccr2 register ccr2 buffer register match signal 16-bit counter output controller (rs-ff) output controller output controller (rs-ff) output controller (rs-ff) tiq00 pin note (external event count input) internal count clock edge detector count clock selection chapter 8 16-bit timer/event counter q (tmq) figure 8-29. basic timing in pwm output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal toq00 pin output tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 3 ) active level width (d 3 ) active level width (d 3 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) user?s manual u17728ej3v1ud 394 chapter 8 16-bit timer/event counter q (tmq) when the tq0ce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts counting, and outputs pwm waveform from the toq0k pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tq0ccrk register ) count clock cycle cycle = (set value of tq0ccr0 register + 1) count clock cycle duty factor = (set value of tq0ccrk regist er)/(set value of tq0ccr0 register + 1) the pwm waveform can be changed by rewriting the tq0ccrm register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttq0cc0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttq0cck is ge nerated when the count value of the 16-bit counter matches the value of the ccrk buffer register. remark k = 1 to 3 m = 0 to 3 figure 8-30. setting of registers in pwm output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce note the setting is invalid when the tq0ctl1.tq0eee bit = 1. (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 0 0 tq0ctl1 100 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 0, 0: pwm output mode 0: operate on count clock selected by tq0cks0 to tq0cks2 bits 1: count external event input signal user?s manual u17728ej3v1ud 395 chapter 8 16-bit timer/event counter q (tmq) figure 8-30. setting of registers in pwm output mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) toq0k pin output 16-bit counter ? when tq0olk bit = 0 toq0k pin output 16-bit counter ? when tq0olk bit = 1 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output 1: enable toq00 pin output setting of toq00 pin output level before count operation 0: low level 1: high level 0: disable toq01 pin output 1: enable toq01 pin output setting of toq01 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 setting of toq03 pin output level before count operation 0: low level 1: high level 0: disable toq02 pin output 1: enable toq02 pin output setting of toq02 pin output level before count operation 0: low level 1: high level 0: disable toq03 pin output 1: enable toq03 pin output note clear this bit to 0 when the toq00 pin is not used in the pwm output mode. (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input (tiq00 pin). 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. user?s manual u17728ej3v1ud 396 chapter 8 16-bit timer/event counter q (tmq) figure 8-30. register setting in pwm output mode (3/3) (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 and tq0ccr3) if d 0 is set to the tq0ccr0 register and d k to the tq0ccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d k count clock cycle remarks 1. tmq0 i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the pwm output mode. 2. updating the tmq0 capture/ compare register 2 (tq0ccr2) and tmq0 capture/compare register 3 (tq0ccr3) is validated by writ ing the tmq0 capture/compare register 1 (tq0ccr1). user?s manual u17728ej3v1ud 397 chapter 8 16-bit timer/event counter q (tmq) (1) operation flow in pwm output mode figure 8-31. software processing flow in pwm output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register ccr0 buffer register inttq0cc0 signal toq00 pin output tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 10 d 20 user?s manual u17728ej3v1ud 398 chapter 8 16-bit timer/event counter q (tmq) figure 8-31. software processing flow in pwm output mode (2/2) start <1> count operation start flow tq0ce bit = 1 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. only writing of the tq0ccr1 register must be performed when the set duty factor is only changed after writing the tq0ccr2 and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. writing the same value (same as the tq0ccr1 register already set) to the tq0ccr1 register is necessary only when the set duty factor of the toq02 and toq03 pin outputs is changed. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. only writing of the tq0ccr1 register must be performed when the set duty factor is only changed. when counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. counting is stopped. the tq0cks0 to tq0cks2 bits can be set at the same time when counting is enabled (tq0ce bit = 1). writing of the tq0ccr1 register must be performed after writing the tq0ccr0, tq0ccr2, and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer registers. writing the same value (same as the tq0ccr1 register already set) to the tq0ccr1 register is necessary only when the set cycle is changed. <2> tq0ccr0 to tq0ccr3 register setting change flow <3> tq0ccr0 register setting change flow <4> tq0ccr1 to tq0ccr3 register setting change flow <5> tq0ccr2 and tq0ccr3 register setting change flow <6> tq0ccr1 register setting change flow <7> count operation stop flow tq0ce bit = 0 setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register stop setting of tq0ccr1 register setting of tq0ccr0 register setting of tq0ccr1 register setting of tq0ccr0, tq0ccr2, and tq0ccr3 registers tq0ccr1 register when the counter is cleared after setting, the value of the tq0ccrm register is transferred to the ccrm buffer register. remark m = 0 to 3 user?s manual u17728ej3v1ud 399 chapter 8 16-bit timer/event counter q (tmq) (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tq0ccr1 register last. rewrite the tq0ccrm register after writing the tq0ccr1 register after the inttq0cc0 signal is detected. ffffh 16-bit counter 0000h tq0ce bit d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tq0ccr0 register ccr0 buffer register inttq0cc0 signal tq0ccr1 register ccr1 buffer register inttq0cc1 signal toq01 pin output tq0ccr2 register ccr2 buffer register inttq0cc2 signal toq02 pin output tq0ccr3 register ccr3 buffer register inttq0cc3 signal toq03 pin output toq00 pin output d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01 user?s manual u17728ej3v1ud 400 chapter 8 16-bit timer/event counter q (tmq) to transfer data from the tq0ccrm register to the ccrm buffer register, the tq0ccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tq0ccr0 register, set the active level width to t he tq0ccr2 and tq0ccr3 registers, and then set an active level width to the tq0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tq0ccr0 register, and then write the same value (same as the tq0ccr1 regist er already set) to the tq0ccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the toq01 pin, only the tq0ccr1 register has to be set. to change only the active level width (duty factor) of the pwm waveform output by the toq02 and toq03 pins, first set an active level width to the tq0 ccr2 and tq0ccr3 registers, and then write the same value (same as the tq0ccr1 register already set) to the tq0ccr1 register. after the tq0ccr1 register is written, the value wr itten to the tq0ccrm register is transferred to the ccrm buffer register in synchronization with the timi ng of clearing the 16-bit counter, and is used as a value to be compared with the value of the 16-bit counter. to change only the cycle of the pwm waveform, first set a cycle to the tq0ccr0 register, and then write the same value to the tq0ccr1 register. to write the tq0ccr0 to tq0ccr3 registers again afte r writing the tq0ccr1 register once, do so after the inttq0cc0 signal is generated. otherwise, t he value of the ccrm buffer register may become undefined because the timing of transferring data from the tq0ccrm register to the ccrm buffer register conflicts with writing the tq0ccrm register. remark m = 0 to 3 user?s manual u17728ej3v1ud 401 chapter 8 16-bit timer/event counter q (tmq) (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tq0ccrk register to 0000h. the 16-bit counter is cleared to 0000h and the inttq0cc0 and inttq0cck signals are generate d at the timing following the clock in which the count value of the 16-bit counter matches the value of the ccr0 buffer register. count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrk register inttq0cc0 signal inttq0cck signal toq0k pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 chapter 8 16-bit timer/event counter q (tmq) (c) generation timing of compare match interrupt request signal (inttq0cck) the timing of generation of the inttq0cck signal in the pwm output mode differs from the timing of other mode inttq0cck signals; the inttq0cck signal is genera ted when the count val ue of the 16-bit counter matches the value of the tq0ccrk register. count clock 16-bit counter ccrk buffer register toq0k pin output inttq0cck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 remark k = 1 to 3 usually, the inttq0cck signal is generated in synch ronization with the next counting up after the count value of the 16-bit counter matches the value of the tq0ccrk register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the toq0k pin. user?s manual u17728ej3v1ud 403 chapter 8 16-bit timer/event counter q (tmq) 8.6.6 free-running timer mode (t q0md2 to tq0md0 bits = 101) in the free-running timer mode, 16-bit timer/event counter q starts counting when the tq0ctl0.tq0ce bit is set to 1. at this time, the tq0ccrm register can be used as a compare register or a captur e register, depending on the setting of the tq0opt0.tq0ccsm bit. remark m = 0 to 3 user?s manual u17728ej3v1ud 404 chapter 8 16-bit timer/event counter q (tmq) figure 8-32. configuration in free-running timer mode toq03 pin note 2 toq02 pin note 2 toq01 pin note 2 toq00 pin note 1 inttq0ov signal tq0ccsm bit (capture/compare selection) inttq0cc3 signal inttq0cc2 signal inttq0cc1 signal inttq0cc0 signal tiq03 pin note 2 (capture trigger input) tq0ccr3 register (capture) tiq00 pin note 1 (external event count input/ capture trigger input) internal count clock tq0ce bit tiq01 pin note 2 (capture trigger input) tiq02 pin note 2 (capture trigger input) tq0ccr0 register (capture) tq0ccr1 register (capture) tq0ccr2 register (capture) tq0ccr3 register (compare) tq0ccr2 register (compare) tq0ccr1 register (compare) 0 1 0 1 0 1 0 1 16-bit counter tq0ccr0 register (compare) output controller output controller output controller output controller count clock selection edge detector edge detector edge detector edge detector edge detector notes 1. because the external event count input pin (t iq00), capture trigger in put pin (tiq00), and timer output pin (toq00) share the same alternate-function pin, two or more functions cannot be used at the same time. 2. because the capture trigger input pin (tiq0k) and external output pin (toq0k) share the same alternate-function pin, two functions cannot be used at the same time (k = 1 to 3). chapter 8 16-bit timer/event counter q (tmq) ? compare operation when the tq0ce bit is set to 1, 16-bit timer/event co unter q starts counting, an d the output signals of the toq00 to toq03 pins are inverted. when the count value of the 16-bit count er later matches the set value of the tq0ccrm register, a compare match interrupt r equest signal (inttq0ccm) is generated, and the output signal of the toq0m pin is inverted. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttq0ov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tq0opt0.tq0ovf bit) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by ex ecuting the clr instruction via software. the tq0ccrm register can be rewritten while the counter is operating. if it is rewritten, the new value is reflected immediately and compared with the count value. remark m = 0 to 3 figure 8-33. basic timing in free-r unning timer mode (compare function) d 10 d 20 d 30 d 00 d 20 d 31 d 31 d 30 d 00 d 11 d 11 d 21 d 01 d 11 d 21 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output inttq0ov signal tq0ovf bit toq00 pin output tq0ccr1 register inttq0cc1 signal tq0ce bit tq0ccr0 register inttq0cc0 signal d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30 user?s manual u17728ej3v1ud 406 chapter 8 16-bit timer/event counter q (tmq) ? capture operation when the tq0ce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the tiq0m pin is detected, the count valu e of the 16-bit counter is stored in t he tq0ccrm register, and a capture interrupt request signal (inttq0ccm) is generated. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttq0ov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tq0opt0.tq0ovf bit) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by ex ecuting the clr instruction via software. remark m = 0 to 3 figure 8-34. basic timing in free-r unning timer mode (capture function) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tiq02 pin input tq0ccr2 register inttq0cc2 signal tiq03 pin input tq0ccr3 register inttq0cc3 signal inttq0ov signal tq0ovf bit tiq01 pin input tq0ccr1 register inttq0cc1 signal tq0ce bit tiq00 pin input tq0ccr0 register inttq0cc0 signal user?s manual u17728ej3v1ud 407 chapter 8 16-bit timer/event counter q (tmq) figure 8-35. register setting in free-running timer mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce note the setting is invalid when the tq0ctl1.tq0eee bit = 1 (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 0 0 tq0ctl1 101 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 0, 1: free-running timer mode 0: operate with count clock selected by tq0cks0 to tq0cks2 bits 1: count on external event count input signal user?s manual u17728ej3v1ud 408 chapter 8 16-bit timer/event counter q (tmq) figure 8-35. register setting in free-running timer mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq00 pin output 1: enable toq00 pin output 0: disable toq01 pin output 1: enable toq01 pin output setting of toq01 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 setting of toq03 pin output level before count operation 0: low level 1: high level 0: disable toq02 pin output 1: enable toq02 pin output setting of toq02 pin output level before count operation 0: low level 1: high level 0: disable toq03 pin output 1: enable toq03 pin output setting of toq00 pin output level before count operation 0: low level 1: high level (d) tmq0 i/o control register 1 (tq0ioc1) 0/1 0/1 0/1 0/1 0/1 tq0ioc1 select valid edge of tiq00 pin input note select valid edge of tiq01 pin input 0/1 0/1 0/1 tq0is2 tq0is1 tq0is0 tq0is3 tq0is6 tq0is5 tq0is4 tq0is7 select valid edge of tiq02 pin input select valid edge of tiq03 pin input note set the valid edge selection of the unused alternat e external input signals to ?no edge detection?. chapter 8 16-bit timer/event counter q (tmq) figure 8-35. register setting in free-running timer mode (3/3) (e) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input (tiq00 pin) note 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1 note set the valid edge selection of the unused alternat e external input signals to ?no edge detection?. (f) tmq0 option register 0 (tq0opt0) 0/1 0/1 0/1 0/1 0 tq0opt0 overflow flag specifies if tq0ccr0 register functions as capture or compare register 0: compare register 1: capture register specifies if tq0ccr1 register functions as capture or compare register 0: compare register 1: capture register 0 0 0/1 tq0ccs0 tq0ovf tq0ccs1 tq0ccs2 tq0ccs3 specifies if tq0ccr2 register functions as capture or compare register 0: compare register 1: capture register specifies if tq0ccr3 register functions as capture or compare register 0: compare register 1: capture register (g) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. (h) tmq0 capture/compare regist ers 0 to 3 (tq0ccr0 to tq0ccr3) these registers function as captur e registers or compare registers depending on the setting of the tq0opt0.tq0ccsm bit. when the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the tiq0m pin is detected. when the registers function as compare registers and when d m is set to the tq0ccrm register, the inttq0ccm signal is generated when the counter reaches (d m + 1), and the output signal of the toq0m pin is inverted. remark m = 0 to 3 chapter 8 16-bit timer/event counter q (tmq) (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 8-36. software processing flow in fr ee-running timer mode (compare function) (1/2) d 10 d 20 d 30 d 00 d 10 d 20 d 30 d 00 d 11 d 31 d 01 d 21 d 21 d 11 d 11 d 31 d 01 d 00 d 10 d 20 d 30 d 01 d 11 d 21 d 31 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal toq00 pin output tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output inttq0ov signal tq0ovf bit user?s manual u17728ej3v1ud 411 chapter 8 16-bit timer/event counter q (tmq) figure 8-36. software processing flow in fr ee-running timer mode (compare function) (2/2) tq0ce bit = 1 read tq0opt0 register (check overflow flag). register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0opt0 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). start execute instruction to clear tq0ovf bit (clr tq0ovf). <1> count operation start flow <2> overflow flag clear flow tq0ce bit = 0 counter is initialized and counting is stopped by clearing tq0ce bit to 0. stop <3> count operation stop flow tq0ovf bit = 1 no yes user?s manual u17728ej3v1ud 412 chapter 8 16-bit timer/event counter q (tmq) (b) when using capture/compare register as capture register figure 8-37. software processing flow in fr ee-running timer mode (c apture function) (1/2) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 0000 0000 0000 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> ffffh 16-bit counter 0000h tq0ce bit tiq02 pin input tq0ccr2 register inttq0cc2 signal tiq03 pin input tq0ccr3 register inttq0cc3 signal inttq0ov signal tq0ovf bit tiq01 pin input tq0ccr1 register inttq0cc1 signal tiq00 pin input tq0ccr0 register inttq0cc0 signal user?s manual u17728ej3v1ud 413 chapter 8 16-bit timer/event counter q (tmq) figure 8-37. software processing flow in fr ee-running timer mode (c apture function) (2/2) tq0ce bit = 1 read tq0opt0 register (check overflow flag). register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc1 register, tq0opt0 register initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). start execute instruction to clear tq0ovf bit (clr tq0ovf). <1> count operation start flow <2> overflow flag clear flow tq0ce bit = 0 counter is initialized and counting is stopped by clearing tq0ce bit to 0. stop <3> count operation stop flow tq0ovf bit = 1 no yes user?s manual u17728ej3v1ud 414 chapter 8 16-bit timer/event counter q (tmq) (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter q is used as an in terval timer with the tq0ccrm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time t he inttq0ccm signal has been detected. remark m = 0 to 3 user?s manual u17728ej3v1ud 415 chapter 8 16-bit timer/event counter q (tmq) d 00 d 10 d 20 d 01 d 30 d 12 d 03 d 22 d 31 d 21 d 23 d 02 d 13 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register inttq0cc0 signal toq00 pin output tq0ccr1 register inttq0cc1 signal toq01 pin output tq0ccr2 register inttq0cc2 signal toq02 pin output tq0ccr3 register inttq0cc3 signal toq03 pin output interval period (d 00 + 1) interval period (10000h + d 02 ? d 01 ) interval period (d 01 ? d 00 ) interval period (d 03 ? d 02 ) interval period (d 04 ? d 03 ) d 00 d 01 d 02 d 03 d 04 d 05 interval period (d 10 + 1) interval period (10000h + d 12 ? d 11 ) interval period (d 11 ? d 10 ) interval period (d 13 ? d 12 ) d 10 d 11 d 12 d 13 d 14 interval period (d 20 + 1) interval period (10000h + d 21 ? d 20 ) interval period (10000h + d 23 ? d 22 ) interval period (d 22 ? d 21 ) interval period (d 30 + 1) interval period (10000h + d 31 ? d 30) d 20 d 21 d 22 d 23 d 31 d 30 d 32 d 04 d 11 user?s manual u17728ej3v1ud 416 chapter 8 16-bit timer/event counter q (tmq) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the co rresponding tq0ccrm register must be re-set in the interrupt servicing that is executed when the inttq0ccm signal is detected. the set value for re-setting the tq0ccrm register c an be calculated by the following expression, where ?d m ? is the interval period. compare register default value: d m ? 1 value set to compare register second and subsequent time: previous set value + d m (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark m = 0 to 3 user?s manual u17728ej3v1ud 417 chapter 8 16-bit timer/event counter q (tmq) (b) pulse width measurement with capture register when pulse width measurement is performed with the tq0ccrm register used as a capture register, software processing is necessary for reading the capt ure register each time the inttq0ccm signal has been detected and for calculating an interval. remark m = 0 to 3 d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 32 d 13 d 03 d 22 d 33 d 23 0000 pulse interval (10000h + d 01 ? d 00 ) pulse interval (10000h + d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) d 00 d 01 d 02 d 03 pulse interval (d 00 + 1) 0000 pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (d 13 ? d 12 ) d 10 d 11 d 12 d 13 pulse interval (d 10 + 1) 0000 pulse interval (10000h + d 21 ? d 20 ) pulse interval (20000h + d 22 ? d 21 ) pulse interval (d 23 ? d 22 ) d 20 d 21 d 23 d 22 pulse interval (d 20 + 1) 0000 pulse interval (10000h + d 31 ? d 30 ) pulse interval (10000h + d 32 ? d 31 ) pulse interval (10000h + d 33 ? d 32 ) d 30 d 31 d 32 d 33 pulse interval (d 30 + 1) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tq0ce bit tiq00 pin input tq0ccr0 register inttq0cc0 signal tiq02 pin input tq0ccr2 register inttq0cc2 signal tiq03 pin input tq0ccr3 register inttq0cc3 signal inttq0ov signal tq0ovf bit tiq01 pin input tq0ccr1 register inttq0cc1 signal user?s manual u17728ej3v1ud 418 chapter 8 16-bit timer/event counter q (tmq) when executing pulse width measurement in the fr ee-running timer mode, four pulse widths can be measured with one channel. to measure a pulse width, the pu lse width can be calculated by re ading the value of the tq0ccrm register in synchronization with the inttq0ccm si gnal, and calculatin g the difference between the read value and the previously read value. remark m = 0 to 3 user?s manual u17728ej3v1ud 419 chapter 8 16-bit timer/event counter q (tmq) (c) processing of overflow when two or more capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two or more capture registers are used ffffh 16-bit counter 0000h tq0ce bit tiq00 pin input tq0ccr0 register tiq01 pin input tq0ccr1 register inttq0ov signal tq0ovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tq0ccr0 register (setting of t he default value of t he tiq00 pin input). <2> read the tq0ccr1 register (setting of t he default value of t he tiq01 pin input). <3> read the tq0ccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tq0ccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below. user?s manual u17728ej3v1ud 420 chapter 8 16-bit timer/event counter q (tmq) (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tq0ce bit inttq0ov signal tq0ovf bit tq0ovf0 flag note tiq00 pin input tq0ccr0 register tq0ovf1 flag note tiq01 pin input tq0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tq0ovf0 and tq0ovf1 flags are set on the internal ram by software. <1> read the tq0ccr0 register (setting of t he default value of t he tiq00 pin input). <2> read the tq0ccr1 register (setting of t he default value of t he tiq01 pin input). <3> an overflow occurs. set the tq0ovf0 and tq0ovf1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tq0ccr0 register. read the tq0ovf0 flag. if the tq0o vf0 flag is 1, clear it to 0. because the tq0ovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tq0ccr1 register. read the tq0ovf1 flag. if the tq0ovf1 flag is 1, clear it to 0 (the tq0ovf0 flag is cleared in <4>, and the tq0ovf1 flag remains 1). because the tq0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> user?s manual u17728ej3v1ud 421 chapter 8 16-bit timer/event counter q (tmq) (2/2) example when two capture registers are used (without using overflow interrupt) ffffh 16-bit counter 0000h tq0ce bit inttq0ov signal tq0ovf bit tq0ovf0 flag note tiq00 pin input tq0ccr0 register tq0ovf1 flag note tiq01 pin input tq0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 l note the tq0ovf0 and tq0ovf1 flags are set on the internal ram by software. <1> read the tq0ccr0 register (setting of t he default value of t he tiq00 pin input). <2> read the tq0ccr1 register (setting of t he default value of t he tiq01 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tq0ccr0 register. read the overflow flag. if the overflow flag is 1, set only the tq0ovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tq0ccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tq0ovf1 flag. if the tq0o vf1 flag is 1, clear it to 0. because the tq0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> user?s manual u17728ej3v1ud 422 chapter 8 16-bit timer/event counter q (tmq) (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16- bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tq0ce bit tiq0m pin input tq0ccrm register inttq0ov signal tq0ovf bit d m0 d m1 d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when a long pulse width in the free-running timer mode. <1> read the tq0ccrm register (setting of t he default value of the tiq0m pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tq0ccrm register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d m1 ? d m0 ) (incorrect). actually, the pulse width must be (20000h + d m1 ? d m0 ) because an overflow occurs twice. remark m = 0 to 3 if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next. user?s manual u17728ej3v1ud 423 chapter 8 16-bit timer/event counter q (tmq) example when capture trigger interval is long ffffh 16-bit counter 0000h tq0ce bit tiq0m pin input tq0ccrm register inttq0ov signal tq0ovf bit overflow counter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tq0ccrm register (setting of t he default value of the tiq0m pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tq0ccrm register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d m1 ? d m0 ). in this example, the pulse width is (20000h + d m1 ? d m0 ) because an overflow occurs twice. clear the overflow counter (0h). remark m = 0 to 3 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tq0ovf bit to 0 with t he clr instruction after reading tq0ovf bit = 1 and by writing 8-bit data (bit 0 is 0) to the tq0opt 0 register after reading tq0ovf bit = 1. user?s manual u17728ej3v1ud 424 chapter 8 16-bit timer/event counter q (tmq) (3) note on capture operation chapter 8 16-bit timer/event counter q (tmq) 8.6.7 pulse width measurement mode (tq0md2 to tq0md0 bits = 110) in the pulse width measurement mode, 16-bit timer/even t counter q starts counting when the tq0ctl0.tq0ce bit is set to 1. each time the valid edge input to the tiq0m pi n has been detected, the count value of t he 16-bit counter is stored in the tq0ccrm register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by reading the tq0ccrm register after a capture interrupt request signal (inttq0ccm) occurs. select either of the tiq00 to tiq03 pins as the capture trigger input pi n. specify ?no edge detected? by using the tq0ioc1 register for the unused pins. in case of figure 8-39 , select either of the tiq00 to tiq03 pins as the capture trigger input pin. specify ?no edge detected? by using the tq0ioc1 register for the unused pins. remark m = 0 to 3 k = 1 to 3 figure 8-38. configuration in pulse width measurement mode chapter 8 16-bit timer/event counter q (tmq) figure 8-39. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tq0ce bit tiq0m pin input tq0ccrm register inttq0ccm signal inttq0ov signal tq0ovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark m = 0 to 3 when the tq0ce bit is set to 1, the 16-bit counter starts c ounting. when the valid edge input to the tiq0m pin is later detected, the count value of the 16-bit counter is stored in the tq0ccrm register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttq0ccm) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tiq0m pin even when the 16-bit counter coun ted up to ffffh, an overflow interrupt request signal (inttq0ov) is generated at the next c ount clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tq0opt0.t q0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tq0ovf bit set (1) count + captured value) count clock cycle remark m = 0 to 3 user?s manual u17728ej3v1ud 427 chapter 8 16-bit timer/event counter q (tmq) figure 8-40. register setting in pu lse width measurement mode (1/2) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 00000 tq0ctl1 110 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tq0cks0 to tq0cks2 bits (c) tmq0 i/o control register 1 (tq0ioc1) 0/1 0/1 0/1 0/1 0/1 tq0ioc1 select valid edge of tiq00 pin input select valid edge of tiq01 pin input 0/1 0/1 0/1 tq0is2 tq0is1 tq0is0 tq0is3 tq0is6 tq0is5 tq0is4 tq0is7 select valid edge of tiq02 pin input select valid edge of tiq03 pin input chapter 8 16-bit timer/event counter q (tmq) figure 8-40. register setting in pu lse width measurement mode (2/2) (d) tmq0 option register 0 (tq0opt0) 00000 tq0opt0 overflow flag 0 0 0/1 tq0ccs0 tq0ovf tq0ccs1 tq0ccs2 tq0ccs3 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) these registers store the count va lue of the 16-bit counter when the valid edge input to the tiq0m pin is detected. remarks 1. tmq0 i/o control register 0 (tq0ioc0) and tmq0 i/o control register 2 (tq0ioc2) are not used in the pulse width measurement mode. 2. m = 0 to 3 chapter 8 16-bit timer/event counter q (tmq) (1) operation flow in pul se width measurement mode figure 8-41. software processing flow in pulse width measurement mode tq0ce bit = 1 tq0ce bit = 0 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits), tq0ctl1 register, tq0ioc1 register, tq0opt0 register initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). the counter is initialized and counting is stopped by clearing the tq0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow <1> <2> ffffh 16-bit counter 0000h tq0ce bit tiq00 pin input tq0ccr0 register inttq0cc0 signal d 0 0000h 0000h d 1 d 2 chapter 8 16-bit timer/event counter q (tmq) (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tq0ovf bit to 0 with t he clr instruction after reading the tq0ovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to t he tq0opt0 register after reading the tq0ovf bit when it is 1. (3) note user?s manual u17728ej3v1ud 432 chapter 9 16-bit interval timer m (tmm) timer m (tmm) is a 16-bit interval timer. the v850es/sg3 incorporates tmm0. 9.1 overview the tmm0 has the following functions. ? interval function ? 8 clocks selectable ? 16-bit counter 1 (the 16-bit counter cannot be read during timer count operation.) ? compare register 1 (the compare register cannot be written during timer counter operation.) ? compare match interrupt 1 timer m supports only the clear & start mode. t he free-running timer mode is not supported. chapter 9 16-bit interval timer m (tmm) user?s manual u17728ej3v1ud 433 9.2 configuration tmm0 includes the following hardware. table 9-1. configuration of tmm0 item configuration timer register 16-bit counter register tmm0 compare register 0 (tm0cmp0) control register tmm0 control register 0 (tm0ctl0) figure 9-1. block diagram of tmm0 tm0ctl0 internal bus f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt controller 16-bit counter match clear inttm0eq0 tm0cmp0 tm0ce tm0cks2 tm0cks1tm0cks0 selector remark f xx : main clock frequency f r : internal oscillation clock frequency f xt : subclock frequency intwt: watch timer interrupt request signal (1) 16-bit counter this is a 16-bit counter that counts the internal clock. the 16-bit counter cannot be read or written. (2) tmm0 compare register 0 (tm0cmp0) the tm0cmp0 register is a 16-bit compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. the same value can always be written to the tm0cmp0 register by software. during the tmm0 operation (tm0ctl0.tm0ce bit = 1), rewriting the tm0cmp0 register is prohibited. tm0cmp0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff694h 14 0 13 11 9 7 5 3 15 1 chapter 9 16-bit interval timer m (tmm) user?s manual u17728ej3v1ud 434 9.3 register (1) tmm0 control register 0 (tm0ctl0) the tm0ctl0 register is an 8-bit regist er that controls the tmm0 operation. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tm0ctl0 register by software. tm0ce tmm0 operation disabled (16-bit counter reset asynchronously). operation clock application stopped. tmm0 operation enabled. operation clock application started. tmm0 operation started. tm0ce 0 1 internal clock operation enable/disable specification tm0ctl0 0 0 0 0 tm0cks2 tm0cks1 tm0cks0 654321 after reset: 00h r/w address: fffff690h the internal clock control and internal circuit reset for tmm0 are performed asynchronously with the tm0ce bit. when the tm0ce bit is cleared to 0, the internal clock of tmm0 is disabled (fixed to low level) and 16-bit counter is reset asynchronously. <7> 0 f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt tm0cks2 0 0 0 0 1 1 1 1 count clock selection tm0cks1 0 0 1 1 0 0 1 1 tm0cks0 0 1 0 1 0 1 0 1 cautions 1. set the tm0cks2 to tm 0cks0 bits when tm0ce bit = 0. when changing the value of tm0ce from 0 to 1, it is not possible to set the value of the tm0cks2 to tm0cks0 bits simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency f r : internal oscillation clock frequency f xt : subclock frequency chapter 9 16-bit interval timer m (tmm) user?s manual u17728ej3v1ud 435 9.4 operation caution do not set the tm0cmp0 register to ffffh. 9.4.1 interval timer mode in the interval timer mode, an interrupt request signal (inttm0eq0) is generated at the interval set by the tm0cm0p register if the tm0ctl0.tm0ce bit is set to 1. figure 9-2. configuration of interval timer 16-bit counter tm0cmp0 register tm0ce bit count clock selection clear match signal inttm0eq0 signal figure 9-3. basic timing of operation in interval timer mode d 0 d 0 d 0 d 0 d 0 interval (d 0 + 2) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal when the tm0ce bit is set to 1, the value of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and the c ounter starts counting. when the count value of the 16-bit counter matches the value of the tm0cmp0 register, the 16-bit counter is cleared to 0000h and a compare match interrupt request signal (inttm0eq0) is generated. the interval can be calculated by the following expression. interval = (set value of tm0cmp0 register + 1) count clock cycle chapter 9 16-bit interval timer m (tmm) user?s manual u17728ej3v1ud 436 figure 9-4. register setting for interval timer mode operation (a) tmm0 control register 0 (tm0ctl0) 0/1 0 0 0 0 tm0ctl0 0/1 0/1 0/1 tm0cks2 tm0cks1 tm0cks0 tm0ce 0: stop counting 1: enable counting select count clock (b) tmm0 compare register 0 (tm0cmp0) if the tm0cmp0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle chapter 9 16-bit interval timer m (tmm) user?s manual u17728ej3v1ud 437 (1) interval timer mode operation flow figure 9-5. software processing flow in interval timer mode <1> <2> tm0ce bit = 1 tm0ce bit = 0 register initial setting tm0ctl0 register (tm0cks0 to tm0cks2 bits) tm0cmp0 register initial setting of these registers is performed before the tm0ce bit is set to 1. the tm0cks0 to tm0cks2 bits cannot be set when counting starts (tm0ce bit = 1). the counter is initialized and counting is stopped by clearing the tm0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow d 0 d 0 d 0 d 0 ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal chapter 9 16-bit interval timer m (tmm) user?s manual u17728ej3v1ud 438 (2) interval timer mode operation timing caution do not set the tm0cmp0 register to ffffh. (a) operation if tm0cmp0 register is set to 0000h if the tm0cmp0 register is set to 0000h, the inttm 0eq0 signal is generated at each count clock. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tm0ce bit tm0cmp0 register inttm0eq0 signal 0000h ffffh 0000h 0000h 0000h 0000h interval time count clock cycle 2 interval time count clock cycle interval time count clock cycle (b) operation if tm0cmp0 register is set to n if the tm0cmp0 register is set to n, the 16-bit counter counts up to n. the counter is cleared to 0000h in synchronization with the next count-up timing and the inttm0eq0 signal is generated. ffffh 16-bit counter 0000h tm0ce bit tm0cmp0 register inttm0eq0 signal n interval time (n + 2) count clock cycle interval time (n + 1) count clock cycle interval time (n + 1) count clock cycle n remark 0000h < n < ffffh chapter 9 16-bit interval timer m (tmm) user?s manual u17728ej3v1ud 439 9.4.2 cautions (1) it takes the 16-bit counter up to the following time to start counting after the tm0ctl0.tm0ce bit is set to 1, depending on the count clock selected. selected count clock maximum time before counting start f xx 2/f xx f xx /2 6/f xx f xx /4 24/f xx f xx /64 128/f xx f xx /512 1024/f xx intwt second rising edge of intwt signal f r /8 16/f r f xt 2/f xt (2) rewriting the tm0cmp0 and tm0ctl0 regist ers is prohibited while tmm0 is operating. if these registers are rewritten while the tm0c e bit is 1, the operation cannot be guaranteed. if they are rewritten by mistake, clear the tm 0ctl0.tm0ce bit to 0, and re-set the registers. (3) do not set the tm0cmp0 register to ffffh. user?s manual u17728ej3v1ud 440 chapter 10 watch timer functions 10.1 functions the watch timer has the following functions. ? watch timer: an interrupt request signal (intwt) is gene rated at intervals of 0.5 or 0.25 seconds by using the main clock or subclock. ? interval timer: an interrupt request sig nal (intwti) is generated at set intervals. the watch timer and interval timer functions can be used at the same time. chapter 10 watch timer functions user?s manual u17728ej3v1ud 441 10.2 configuration the block diagram of the watch timer is shown below. figure 10-1. block diagram of watch timer internal bus watch timer operation mode register (wtm) f brg f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 f x f x /8 f x /4 f x /2 f x bgcs00 bgcs01 bgce0 3-bit prescaler 8-bit counter clear match f bgcs prsm0 register prscm0 register 2 internal bus clock control selector selector selector selector selector 1/2 remark f x : main clock oscillation frequency f bgcs : watch timer source clock frequency f brg : watch timer count clock frequency f xt : subclock frequency f w : watch timer clock frequency intwt: watch timer interrupt request signal intwti: interval timer interrupt request signal chapter 10 watch timer functions user?s manual u17728ej3v1ud 442 (1) clock control this block controls supplying and stopping the operating clock (f x ) when the watch timer operates on the main clock. (2) 3-bit prescaler this prescaler divides f x to generate f x /2, f x /4, or f x /8. (3) 8-bit counter this 8-bit counter counts the source clock (f bgcs ). (4) 11-bit prescaler this prescaler divides f w to generate a clock of f w /2 4 to f w /2 11 . (5) 5-bit counter this counter counts f w or f w /2 9 , and generates a watch timer interrupt request signal at intervals of 2 4 /f w , 2 5 /f w , 2 13 /f w , or 2 14 /f w . (6) selector the watch timer has the following five selectors. ? selector that selects one of f x , f x /2, f x /4, or f x /8 as the source clock of the watch timer ? selector that selects the main clock (f x ) or subclock (f xt ) as the clock of the watch timer ? selector that selects f w or f w /2 9 as the count clock frequency of the 5-bit counter ? selector that selects 2 4 /f w , 2 13 /f w , 2 5 /f w , or 2 14 /f w as the intwt signal generation time interval ? selector that selects 2 4 /f w to 2 11 /f w as the interval timer interrupt re quest signal (intwti) generation time interval (7) prscm register this is an 8-bit compare register that sets the interval time. (8) prsm register this register controls clock supply to the watch timer. (9) wtm register this is an 8-bit register that contro ls the operation of the watch timer/in terval timer, and sets the interrupt request signal generation interval. chapter 10 watch timer functions user?s manual u17728ej3v1ud 443 10.3 control registers the following registers are provided for the watch timer. ? prescaler mode register 0 (prsm0) ? prescaler compare register 0 (prscm0) ? watch timer operation mode register (wtm) (1) prescaler mode register 0 (prsm0) the prsm0 register controls the generat ion of the watch timer count clock. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 prsm0 0 0 bgce0 0 0 bgcs01 bgcs00 disabled enabled bgce0 0 1 main clock operation enable f x f x /2 f x /4 f x /8 5 mhz 200 ns 400 ns 800 ns 1.6 s 4 mhz 250 ns 500 ns 1 s 2 s bgcs01 0 0 1 1 bgcs00 0 1 0 1 selection of watch timer source clock (f bgcs ) after reset: 00h r/w address: fffff8b0h < > cautions 1. do not change the values of the bgcs00 and bgcs01 bits during watch timer operation. 2. set the prsm0 register befo re setting the bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz. chapter 10 watch timer functions user?s manual u17728ej3v1ud 444 (2) prescaler compare register 0 (prscm0) the prscm0 register is an 8-bit compare register. this register can be read or written in 8-bit units. reset sets this register to 00h. prscm07 prscm0 prscm06 prscm05 prscm04 prscm03 prscm02 prscm01 prscm00 after reset: 00h r/w address: fffff8b1h cautions 1. do not rewrite the prscm0 register during watc h timer operation. 2. set the prscm0 register before setting the prsm0.bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock fr equency that is used so as to obtain an f brg frequency of 32.768 khz. the calculation for f brg is shown below. f brg = f bgcs /2n remark f bgcs : watch timer source clock set by the prsm0 register n: set value of the prscm0 register = 1 to 256 however, n = 256 when the prscm0 register is set to 00h. chapter 10 watch timer functions user?s manual u17728ej3v1ud 445 (3) watch timer operation mode register (wtm) the wtm register enables or di sables the count clock and operation of t he watch timer, sets the interval time of the prescaler, controls the operat ion of the 5-bit counter, and sets the set time of the watch flag. set the prsm0 register before setting the wtm register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.91 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.3 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of interval time of prescaler wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h < > < > chapter 10 watch timer functions user?s manual u17728ej3v1ud 446 (2/2) 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of set time of watch flag clears after operation stops starts wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stops operation (clears both prescaler and 5-bit counter) enables operation wtm0 0 1 watch timer operation enable caution rewrite the wtm2 to wtm7 bits wh ile both the wtm0 and wtm1 bits are 0. remarks 1. f w : watch timer clock frequency 2. values in parentheses apply to operation with f w = 32.768 khz chapter 10 watch timer functions user?s manual u17728ej3v1ud 447 10.4 operation 10.4.1 operation as watch timer the watch timer generates an interrupt request signal (int wt) at fixed time intervals. the watch timer operates using time intervals of 0.25 or 0.5 seconds wi th the subclock (32.768 khz) or main clock. the count operation starts when the wtm.wtm1 and wtm.wtm0 bits are set to 11. when the wtm0 bit is cleared to 0, the 11-bit prescaler and 5-bit co unter are cleared and the count operation stops. the time of the watch timer can be adjusted by clearin g the wtm1 bit to 0 and then the 5-bit counter when operating at the same time as the interval timer. at this time, an error of up to 15.6 ms may occur for the watch timer, but the interval timer is not affected. if the main clock is used as the count clock of the watc h timer, set the count clock using the prsm0.bgcs01 and bgcs00 bits, the 8-bit comparison value using the prscm0 register, and the count clock frequency (f brg ) of the watch timer to 32.768 khz. when the prsm0.bgce0 bit is set (1), f brg is supplied to the watch timer. f brg can be calculated by the following expression. f brg = f x /(2 m+1 n) to set f brg to 32.768 khz, perform the following calculat ion and set the bgcs01 and bgcs00 bits and the prscm0 register. <1> set n = f x /65,536. set m = 0. <2> when the value resulting from rounding up the first dec imal place of n is even, set n before the roundup as n/2 and m as m + 1. <3> repeat <2> until n is odd or m = 3. <4> set the value resulting from rounding up the first dec imal place of n to the prscm0 register and m to the bgcs01 and bgcs00 bits. example: when f x = 4.00 mhz <1> n = 4,000,000/65,536 = 61.03?, m = 0 <2>, <3> because n (round up the first decimal place) is odd, n = 61, m = 0. <4> set value of prscm0 register: 3dh (61), set value of bgcs01 and bgcs00 bits: 00 at this time, the actual f brg frequency is as follows. f brg = f x /(2 m+1 n) = 4,000,000/(2 61) = 32.787 khz remark m: division value (set value of bgcs01 and bgcs00 bits) = 0 to 3 n: set value of prscm0 register = 1 to 256 however, n = 256 when prscm0 register is set to 00h. f x : main clock oscillation frequency chapter 10 watch timer functions user?s manual u17728ej3v1ud 448 10.4.2 operation as in terval timer the watch timer can also be used as an interval time r that repeatedly generates an interrupt request signal (intwti) at intervals specifie d by a preset count value. the interval time can be selected by the wtm.wtm4 to wtm7 bits. table 10-1. interval time of interval timer wtm7 wtm6 wtm5 wtm4 interval time 0 0 0 0 2 4 1/fw 488 s (operating at f w = f xt = 32.768 khz) 0 0 0 1 2 5 1/fw 977 s (operating at f w = f xt = 32.768 khz) 0 0 1 0 2 6 1/fw 1.95 ms (operating at f w = f xt = 32.768 khz) 0 0 1 1 2 7 1/fw 3.91 ms (operating at f w = f xt = 32.768 khz) 0 1 0 0 2 8 1/fw 7.81 ms (operating at f w = f xt = 32.768 khz) 0 1 0 1 2 9 1/fw 15.6 ms (operating at f w = f xt = 32.768 khz) 0 1 1 0 2 10 1/fw 31.3 ms (operating at f w = f xt = 32.768 khz) 0 1 1 1 2 11 1/fw 62.5 ms (operating at f w = f xt = 32.768 khz) 1 0 0 0 2 4 1/fw 488 s (operating at f w = f brg = 32.768 khz) 1 0 0 1 2 5 1/fw 977 s (operating at f w = f brg = 32.768 khz) 1 0 1 0 2 6 1/fw 1.95 ms (operating at f w = f brg = 32.768 khz) 1 0 1 1 2 7 1/fw 3.91 ms (operating at f w = f brg = 32.768 khz) 1 1 0 0 2 8 1/fw 7.81 ms (operating at f w = f brg = 32.768 khz) 1 1 0 1 2 9 1/fw 15.6 ms (operating at f w = f brg = 32.768 khz) 1 1 1 0 2 10 1/fw 31.3 ms (operating at f w = f brg = 32.768 khz) 1 1 1 1 2 11 1/fw 62.5 ms (operating at f w = f brg = 32.768 khz) remark f w : watch timer clock frequency chapter 10 watch timer functions user?s manual u17728ej3v1ud 449 figure 10-2. operation timing of watch timer/interval timer start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti remarks 1. when 0.5 seconds of the watch timer interrupt time is set. 2. f w : watch timer clock frequency values in parentheses apply to operation with f w = 32.768 khz. n: number of interval timer operations 10.4.3 cautions some time is required before the first watch timer interr upt request signal (intwt) is generated after operation is enabled (wtm.wtm1 and wtm.wtm0 bits = 1). figure 10-3. example of generation of watc h timer interrupt request signal (intwt) (when interrupt cycle = 0.5 s) it takes 0.515625 seconds (max.) for the first intwt signal to be generated (2 9 1/32768 = 0.015625 seconds longer (max.)). the intwt signal is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt user?s manual u17728ej3v1ud 450 chapter 11 functions of watchdog timer 2 11.1 functions watchdog timer 2 has the following functions. ? default-start watchdog timer note 1 reset mode: reset operation upon overflow of wa tchdog timer 2 (generation of wdt2res signal) non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2 signal) note 2 ? input selectable from main clock, internal os cillation clock, and subclock as the source clock notes 1. watchdog timer 2 automatically starts in the reset mode following reset release. when watchdog timer 2 is not used, either stop its operation before reset is executed via this function, or clear watchdog timer 2 once and stop it within the next interval time. also, write to the wdtm2 register for verifi cation purposes only once, even if the default settings (reset mode, interval time: f r /2 19 ) do not need to be changed. 2. for the non-maskable interrupt servicing due to a non-maskable interrupt request signal (intwdt2), see 22.2.2 (2) intwdt2 signal . chapter 11 functions of watchdog timer 2 user?s manual u17728ej3v1ud 451 11.2 configuration the following shows the block diagram of watchdog timer 2. figure 11-1. block diag ram of watchdog timer 2 f xx /2 9 clock input controller output controller wdt2res (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 f xt wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f xx /2 18 to f xx /2 25 , f xt /2 9 to f xt /2 16 , f r /2 12 to f r /2 19 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 2 2 clear f r /2 3 remark f xx : main clock frequency f xt : subclock frequency f r : internal oscillation clock frequency intwdt2: non-maskable interrupt request signal from watchdog timer 2 wdtres2: watchdog timer 2 reset signal watchdog timer 2 consists of the following hardware. table 11-1. configuration of watchdog timer 2 item configuration control registers watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) chapter 11 functions of watchdog timer 2 user?s manual u17728ej3v1ud 452 11.3 registers (1) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time and operation clock of watchdog timer 2. this register can be read or written in 8-bit units. this register can be read any number of times, but it can be written only once following reset release. reset input sets this register to 67h. caution accessing the wdtm2 register is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2 signal) reset mode (generation of wdt2res signal) wdm21 0 0 1 wdm20 0 1 ? selection of operation mode of watchdog timer 2 cautions 1. for details of the wdcs20 to w dcs24 bits, see table 11-2 watchdog timer 2 clock selection. 2. although watchdog timer 2 can be stopped just by stopping operation of the internal oscillator, clear the wdtm2 re gister to 00h to securely st op the timer (to avoid selection of the main clock or subclock due to an erroneous write operation). 3. if the wdtm2 register is rewritten twice after reset, an overflow signal is forcibly generated and the counter is reset. 4. to intentionally generate an overflow sign al, write to the wdtm2 register only twice or write a value other than ?ach? to the wdte register once. however, when watchdog timer 2 is set to st op operation, an overflow signal is not generated even if data is written to the wdtm2 register only twice, or a value other than ?ach? is written to the wdte register only once. 5. to stop the operation of watchdog timer 2, set the rcm.rstop bit to 1 (to stop the internal oscillator) and write 00h in the wdtm 2 register. if the rcm.rstop bit cannot be set to 1, set the wdcs23 bit to 1 (2 n /f xx is selected and the clock can be stopped in the idle1, idlw2, sub-idle, an d subclock operation modes). chapter 11 functions of watchdog timer 2 user?s manual u17728ej3v1ud 453 table 11-2. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs 20 selected clock 100 khz (min.) 220 khz (typ.) 400 khz (max.) 0 0 0 0 0 2 12 /f r 41.0 ms 18.6 ms 10.2 ms 0 0 0 0 1 2 13 /f r 81.9 ms 37.2 ms 20.5 ms 0 0 0 1 0 2 14 /f r 163.8 ms 74.5 ms 41.0 ms 0 0 0 1 1 2 15 /f r 327.7 ms 148.9 ms 81.9 ms 0 0 1 0 0 2 16 /f r 655.4 ms 297.9 ms 163.8 ms 0 0 1 0 1 2 17 /f r 1,310.7 ms 595.8 ms 327.7 ms 0 0 1 1 0 2 18 /f r 2,621.4 ms 1,191.6 ms 655.4 ms 0 0 1 1 1 2 19 /f r 5,242.9 ms 2,383.1 ms 1,310.7 ms f xx = 32 mhz f xx = 20 mhz f xx = 10 mhz 0 1 0 0 0 2 18 /f xx 8.2 ms 13.1 ms 26.2 ms 0 1 0 0 1 2 19 /f xx 16.4 ms 26.2 ms 52.4 ms 0 1 0 1 0 2 20 /f xx 32.8 ms 52.4 ms 104.9 ms 0 1 0 1 1 2 21 /f xx 65.5 ms 104.9 ms 209.7 ms 0 1 1 0 0 2 22 /f xx 131.1 ms 209.7 ms 419.4 ms 0 1 1 0 1 2 23 /f xx 262.1 ms 419.4 ms 838.9 ms 0 1 1 1 0 2 24 /f xx 524.3 ms 838.9 ms 1,677.7 ms 0 1 1 1 1 2 25 /f xx 1,048.6 ms 1,677.7 ms 3,355.4 ms f xt = 32.768 khz 1 0 0 0 2 9 /f xt 15.625 ms 1 0 0 1 2 10 /f xt 31.25 ms 1 0 1 0 2 11 /f xt 62.5 ms 1 0 1 1 2 12 /f xt 125 ms 1 1 0 0 2 13 /f xt 250 ms 1 1 0 1 2 14 /f xt 500 ms 1 1 1 0 2 15 /f xt 1,000 ms 1 1 1 1 2 16 /f xt 2,000 ms chapter 11 functions of watchdog timer 2 user?s manual u17728ej3v1ud 454 (2) watchdog timer enable register (wdte) the counter of watchdog timer 2 is cleared and counting restarted by wr iting ?ach? to the wdte register. the wdte register can be read or written in 8-bit units. reset input sets this register to 9ah. wdte after reset: 9ah r/w address: fffff6d1h cautions 1. when a value other than ?ach? is writ ten to the wdte register , an overflow signal is forcibly output. 2. when a 1-bit memory mani pulation instruction is execute d for the wdte register, an overflow signal is forcibly output. 3. to intentionally generate an overflow sign al, write to the wdtm2 register only twice or write a value other than ?ach? to the wdte register once. however, when the watch dog timer 2 is set to stop opera tion, an overflow signal is not generated even if data is written to the wdtm2 register only twice, or a value other than ?ach? is written to the wdte register only once. 4. the read value of the wdte register is ?9ah? (which differs from written value ?ach?). chapter 11 functions of watchdog timer 2 user?s manual u17728ej3v1ud 455 11.4 operation watchdog timer 2 automatically starts in t he reset mode following reset release. the wdtm2 register can be written to only once following re set using byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm2 register using an 8-bit me mory manipulation instruction. after this, the operation of watchdog timer 2 cannot be stopped. the wdcs24 to wdcs20 bits of the wdtm 2 register are used to select the watchdog timer 2 loop detection time interval. writing ach to the wdte register cl ears the counter of watchdog timer 2 an d starts the count operation again. after the count operation has start ed, write ach to wdte within the loop detection time interval. if the time interval expires without ach being written to the wdte register, a reset signal (wdt2res) or a non- maskable interrupt request signal (intwdt2) is gener ated, depending on the set values of the wdm21 and wdtm2.wdm20 bits. when the wdtm2.wdm21 bit is set to 1 (reset mode), if a wdt overflow occurs during oscillation stabilization after a reset or standby is released, no internal reset will oc cur and the cpu clock will switch to the internal oscillation clock. to not use watchdog timer 2, write 00h to the wdtm2 register. for the non-maskable interrupt servicing while t he non-maskable interrupt request mode is set, see 22.2.2 (2) intwdt2 signal . user?s manual u17728ej3v1ud 456 chapter 12 real-time output function (rto) 12.1 function the real-time output function transfers preset data to the rtbl0 and rtbh 0 registers, and then transfers this data by hardware to an external device via the output latches, upon occurrence of a timer interrupt. the pins through which the data is output to an external device constitute a port called the real-tim e output function (rto). because rto can output signals without jitter, it is suitable for controlling a stepper motor. in the v850es/sg3, one 6-bit real-tim e output port channel is provided. the real-time output port can be se t to the port mode or real-time output port mode in 1-bit units. chapter 12 real-time output function (rto) user?s manual u17728ej3v1ud 457 12.2 configuration the block diagram of rto is shown below. figure 12-1. block diagram of rto inttp0cc0 inttp5cc0 inttp4cc0 rtpoe0 rtpeg0 byte0 extr0 rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 4 2 2 4 rtp04, rtp05 rtp00 to rtp03 real-time output buffer register 0h (rtbh0) real-time output latch 0h selector real-time output latch 0l real-time output port control register 0 (rtpc0) transfer trigger (h) transfer trigger (l) real-time output port mode register 0 (rtpm0) internal bus real-time output buffer register 0l (rtbl0) rto consists of the following hardware. table 12-1. configuration of rto item configuration registers real-time output buffer r egisters 0l, 0h (rtbl0, rtbh0) control registers real-time output port mode register 0 (rtpm0) real-time output port control register 0 (rtpc0) chapter 12 real-time output function (rto) user?s manual u17728ej3v1ud 458 (1) real-time output buffer regi sters 0l, 0h (rtbl0, rtbh0) the rtbl0 and rtbh0 registers are 4-bit registers that hold preset output data. these registers are mapped to independent addresses in the peripheral i/o register area. these registers can be read or wr itten in 8-bit or 1-bit units. reset input clears these registers to 00h. if an operation mode of 4 bits 1 channel or 2 bits 1 channel is specified (rtpc0.byte0 bit = 0), data can be individually set to the rtbl0 and rtbh0 registers. the data of both these r egisters can be read at once by specifying the address of either of these registers. if an operation mode of 6 bits 1 channel is specified (byte0 bit = 1), 8-bit data can be set to both the rtbl0 and rtbh0 registers by writing the da ta to either of these registers. moreover, the data of both these registers can be read at once by specifying the address of either of these registers. table 12-2 shows the operation when the rt bl0 and rtbh0 register s are manipulated. 0 rtbl0 rtbh0 0 rtbh05 rtbh04 rtbl03 rtbl02 rtbl01 rtbl00 after reset: 00h r/w address: rtbl0 fffff6e0h, rtbh0 fffff6e2h cautions 1. when writing to bits 6 and 7 of the rtbh0 register, always write 0. 2. accessing the rtbl0 and rtbh0 regi sters is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclo ck and the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock table 12-2. operation during manipul ation of rtbl0 and rtbh0 registers read write note operation mode register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl0 rtbh0 rtbl0 invalid rtbl0 4 bits 1 channel, 2 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 invalid rtbl0 rtbh0 rtbl0 rtbh0 rtbl0 6 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 rtbl0 note after setting the real-time output port, set output data to the rtbl0 and rtbh0 registers by the time a real- time output trigger is generated. chapter 12 real-time output function (rto) user?s manual u17728ej3v1ud 459 12.3 registers rto is controlled using the following two registers. ? real-time output port mode register 0 (rtpm0) ? real-time output port control register 0 (rtpc0) (1) real-time output port mode register 0 (rtpm0) the rtpm0 register selects t he real-time output port mode or port mode in 1-bit units. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 rtpm0m 0 1 real-time output disabled real-time output enabled control of real-time output port (m = 0 to 5) rtpm0 0 rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 after reset: 00h r/w address: fffff6e4h cautions 1. by enabling the real-time output operation (rtpc0.rtpoe0 bit = 1), the bits enabled to real-time output among the rt p00 to rtp05 signa ls perform real- time output, and the bits set to port mode output 0. 2. if real-time output is disabled (rtpoe0 bit = 0), the real-time output pins (rtp00 to rtp05) all output 0, regard less of the rtpm0 register setting. 3. in order to use this register as the real-time output pins (rtp00 to rtp05), set these pins as real-time output port pins using the pmc and pfc registers. chapter 12 real-time output function (rto) user?s manual u17728ej3v1ud 460 (2) real-time output port control register 0 (rtpc0) the rtpc0 register is a register that sets the operat ion mode and output trigger of the real-time output port. the relationship between the operation mo de and output trigger of the real -time output port is as shown in table 12-3. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. rtpoe0 disables operation note 1 enables operation rtpoe0 0 1 control of real-time output operation rtpc0 rtpeg0 byte0 extr0 0 0 0 0 falling edge note 2 rising edge valid edge of inttp0cc0 signal 4 bits 2 channels, 2 bits 2 channels 6 bits 2 channels byte0 0 1 rtpeg0 0 1 specification of channel configuration for real-time output after reset: 00h r/w address: fffff6e5h < > notes 1. when the real-time output oper ation is disabled (rtpoe0 bit = 0), all the bits of the real-time output signals (rtp00 to rtp05) output ?0?. 2. the inttp0cc0 signal is output for 1 cl ock of the count clock selected by tmp0. caution set the rtpeg0, byte0, and ext r0 bits only when rtpoe0 bit = 0. table 12-3. operation modes and output triggers of real-time output port byte0 extr0 operation mode rtbh0 (rtp 04, rtp05) rtbl0 (rtp00 to rtp03) 0 inttp5cc0 inttp4cc0 0 1 4 bits 1 channel, 2 bits 1 channel inttp4cc0 inttp0cc0 0 inttp4cc0 1 1 6 bits 1 channel inttp0cc0 chapter 12 real-time output function (rto) user?s manual u17728ej3v1ud 461 12.4 operation if the real-time output operation is enabled by setting the rtpc0.rtpoe0 bi t to 1, the data of the rtbh0 and rtbl0 registers is transferred to the real-time output latch in synchronizati on with the generation of the selected transfer trigger (set by the rtpc0.extr0 and rtpc0.byte0 bits). of the trans ferred data, only the data of the bits for which real-time output is enabled by the rtpm0 register is output from t he rtp00 to rtp05 bits. the bits for which real-time output is disabled by the rtpm0 register output 0. if the real-time output operatio n is disabled by clearing the rtpoe0 bit to 0, the rtp00 to rtp05 signals output 0 regardless of the setting of the rtpm0 register. figure 12-2. example of operation timing of rto0 (when extr0 bit = 0, byte0 bit = 0) abababab d01 d02 d03 d04 d11 d12 d13 d14 d11 d12 d13 d14 d01 d02 d03 d04 inttp5cc0 (internal) inttp4cc0 (internal) cpu operation rtbh0 rtbl0 rt output latch 0 (h) rt output latch 0 (l) a: software processing by inttp5cc0 interrupt request (rtbh0 write) b: software processing by inttp4cc0 interrupt request (rtbl0 write) remark for the operation during standby, see chapter 24 standby function . chapter 12 real-time output function (rto) user?s manual u17728ej3v1ud 462 12.5 usage (1) disable real-time output. clear the rtpc0.rtpoe0 bit to 0. (2) perform initialization as follows. ? set the alternate-function pins of port 5 set the pfc5.pfc5m bit and pfce5.pfce5m bit to 1, and then set the pmc5.pmc5m bit to 1 (m = 0 to 5). ? specify the real-time output port mode or port mode in 1-bit units. set the rtpm0 register. ? channel configuration: select the trigger and valid edge. set the rtpc0.extr0, rtpc0. byte0, and rtpc0.rtpeg0 bits. ? set the initial values to the rtbh0 and rtbl0 registers note 1 . (3) enable real-time output. set the rtpoe0 bit = 1. (4) set the next output value to the rtbh0 and rtbl0 registers by the time the selected transfer trigger is generated note 2 . (5) set the next real-time output value to the rtbh0 and rt bl0 registers via interrupt servicing corresponding to the selected trigger. notes 1. if the rtbh0 and rtbl0 registers are written when the rtpoe0 bit = 0, that value is transferred to real-time output latches 0h and 0l, respectively. 2. even if the rtbh0 and rtbl0 r egisters are written when the rt poe0 bit = 1, data is not transferred to real-time output latches 0h and 0l. 12.6 cautions (1) prevent the following conflicts by software. ? conflict between real-time output disable/enable switching (rtpoe0 bi t) and selected real-time output trigger. ? conflict between writing to the rtbh0 and rtbl0 regist ers in the real-time output enabled status and the selected real-time output trigger. (2) before performing initialization, disable real-time output (rtpoe0 bit = 0). (3) once real-time output has been disabled (rtpoe0 bit = 0), be sure to initialize the rtbh0 and rtbl0 registers before enabling real-time output again (rtpoe0 bit = 0 1). user?s manual u17728ej3v1ud 463 chapter 13 a/d converter 13.1 overview the a/d converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 analog input signal channels (ani0 to ani11). the a/d converter has the following features. { 10-bit resolution { 12 channels { successive approximation method { operating voltage: av ref0 = 3.0 to 3.6 v { analog input voltage: 0 v to av ref0 { the following functions are provided as operation modes. ? continuous select mode ? continuous scan mode ? one-shot select mode ? one-shot scan mode { the following functions are provided as trigger modes. ? software trigger mode ? external trigger mode (external, 1) ? timer trigger mode { power-fail monitor function (conversion result compare function) 13.2 functions (1) 10-bit resolution a/d conversion an analog input channel is selected from ani0 to an i11, and an a/d conversion op eration is repeated at a resolution of 10 bits. each time a/d conversion has been completed, an interrupt request signal (intad) is generated. (2) power-fail detection function this function is used to detect a drop in the battery volt age. the result of a/d conversion (the value of the ada0crnh register) is compared with the value of t he ada0pft register, and the intad signal is generated only when a specified comparison condition is satisfied (n = 0 to 11). chapter 13 a/d converter user?s manual u17728ej3v1ud 464 13.3 configuration the block diagram of the a/d converter is shown below. figure 13-1. block diagram of a/d converter ani0 : : ani1 ani2 ani9 ani10 ani11 ada0m2 ada0m1 ada0m0 ada0s ada0pft controller voltage comparator ada0pfm ada0cr0 ada0cr1 : : ada0cr2 ada0cr10 ada0cr11 internal bus av ref0 ada0ce bit av ss intad edge detection adtrg controller sample & hold circuit ada0ets0 bit inttp2cc0 inttp2cc1 ada0ets1 bit ada0ce bit ada0tmd1 bit ada0tmd0 bit selector selector ada0pfe bit ada0pfc bit sar voltage comparator & compare voltage generation dac the a/d converter includes the following hardware. table 13-1. configuration of a/d converter item configuration analog inputs 12 channels (ani0 to ani11 pins) registers successive approximation register (sar) a/d conversion result registers 0 to 11 (ada0cr0 to ada0cr11) a/d conversion result registers 0h to 11h (adcr0h to adcr11h): only higher 8 bits can be read control registers a/d converter mode registers 0 to 2 (ada0m0 to ada0m2) a/d converter channel specification register (ada0s) power fail compare mode register (ada0pfm) power fail compare threshold value register (ada0pft) chapter 13 a/d converter user?s manual u17728ej3v1ud 465 (1) successive approximation register (sar) the sar register compares the voltage value of the analog input sign al with the output vo ltage of the compare voltage generation dac (compare voltage), and holds the co mparison result starting fr om the most significant bit (msb). when the comparison result has been held down to the le ast significant bit (lsb) (i.e., when a/d conversion is complete), the contents of the sar register are transferred to the ada0crn register. remark n = 0 to 11 (2) a/d conversion result register n (ada0crn), a/d conversion result register nh (ada0crnh) the ada0crn register is a 16-bit regi ster that stores the a/d conversi on result. ada0arn consist of 12 registers and the a/d conversion result is stored in the 10 higher bits of the ad0crn register corresponding to analog input. (the lower 6 bits are fixed to 0.) (3) a/d converter mode register 0 (ada0m0) this register specifies the operation mode and cont rols the conversion operation by the a/d converter. (4) a/d converter mode register 1 (ada0m1) this register sets the conversion time of the analog input signal to be converted. (5) a/d converter mode register 2 (ada0m2) this register sets the hardware trigger mode. (6) a/d converter channel specification register (ada0s) this register sets the input port that inputs the analog voltage to be converted. (7) power-fail compare m ode register (ada0pfm) this register sets the power-fail monitor mode. (8) power-fail compare threshol d value register (ada0pft) the ada0pft register sets a threshold value that is co mpared with the value of a/d conversion result register nh (ada0crnh). the 8-bit data set to the ada0pft regi ster is compared with the hi gher 8 bits of the a/d conversion result register (ada0crnh). (9) controller the controller compares the result of the a/d conversion (the value of the ada0crnh register) with the value of the ada0pft register when a/d conversion is comp leted or when the power-fail detection function is used, and generates the intad signal only when a spec ified comparison condition is satisfied. (10) sample & hold circuit the sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (11) voltage comparator the voltage comparator compares a voltage value that has been sample d and held with the voltage value of the compare voltag e generation dac. chapter 13 a/d converter user?s manual u17728ej3v1ud 466 (12) compare voltage generation dac this compare voltage generation dac is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (13) ani0 to ani11 pins these are analog input pins for the 12 a/d converter channels and are used to input analog signals to be converted into digital signals. pins other than the one selected as the analog input by the ada0s register can be used as input port pins. caution make sure that the voltag es input to the ani0 to ani11 pins do not exceed the rated values. in particular if a voltage of av ref0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conver sion values of the other channels may also be affected. (14) av ref0 pin this is the pin used to input the reference voltage of t he a/d converter. always make the potential at this pin the same as that at the v dd pin even when the a/d converter is not us ed. the signals input to the ani0 to ani11 pins are converted to digital signal s based on the voltage applied between the av ref0 and av ss pins. (15) av ss pin this is the ground pin of t he a/d converter. always make the potential at this pin the same as that at the v ss pin even when the a/d converter is not used. chapter 13 a/d converter user?s manual u17728ej3v1ud 467 13.4 registers the a/d converter is controlled by the following registers. ? a/d converter mode registers 0, 1, 2 (ada0m0, ada0m1, ada0m2) ? a/d converter channel specification register 0 (ada0s) ? power-fail compare mode register (ada0pfm) the following registers are also used. ? a/d conversion result register n (ada0crn) ? a/d conversion result register nh (ada0crnh) ? power-fail compare threshold value register (ada0pft) (1) a/d converter mode register 0 (ada0m0) the ada0m0 register is an 8-bit register that specif ies the operation mode and controls conversion operations. this register can be read or written in 8-bit or 1-bit units. however, ada0ef bit is read-only. reset sets this register to 00h. caution accessing the ada0m0 register is prohibited in the following st atuses. for details, refer to 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock (1/2) ada0ce ada0ce 0 1 stops a/d conversion enables a/d conversion a/d conversion control ada0m0 0 ada0md1 ada0md0 ada0ets1 ada0ets0 ada0tmd ada0ef ada0md1 0 0 1 1 ada0md0 0 1 0 1 continuous select mode continuous scan mode one-shot select mode one-shot scan mode specification of a/d converter operation mode after reset: 00h r/w address: fffff200h < > < > chapter 13 a/d converter user?s manual u17728ej3v1ud 468 (2/2) ada0tmd 0 1 software trigger mode external trigger mode/timer trigger mode trigger mode specification ada0ef 0 1 a/d conversion stopped a/d conversion in progress a/d converter status display ada0ets1 0 0 1 1 ada0ets0 0 1 0 1 no edge detection falling edge detection rising edge detection detection of both rising and falling edges specification of external trigger (adtrg pin) input valid edge cautions 1. if bit 0 is wr itten, this is ignored. 2. changing the ada0m1.ada0fr2 to ada0 m1.ada0fr0 bits is prohibited while a/d conversion is enabled (ada0ce bit = 1). 3. in the following modes, write data to the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers while a/d conversion is stopped (ada0ce bit = 0), and then enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mode of high-speed conversion mode if data is written to the ada0m0, ada0 m2, ada0s, ada0pfm, and ada0pft registers in any other modes during a/d conversion (a da0ef bit = 1), the operation is performed as follows, depending on the mode. ? in software trigger mode a/d conversion is stopped and started again from the beginning. ? in hardware trigger mode a/d conversion is stopped, and the trigger standby state is set. 4. to select the external trigger mode/timer trigger mode (ada0tmd bit = 1), set the high- speed conversion mode (ada0m1.ada0hs1 bi t = 1). do not input a trigger during stabilization time that is inserted once af ter the a/d conversion operation is enabled (ada0ce bit = 1). 5. when not using the a/d converter, stop the operation by setting the ada0ce bit to 0 to reduce the power consumption. chapter 13 a/d converter user?s manual u17728ej3v1ud 469 (2) a/d converter mode register 1 (ada0m1) the ada0m1 register is an 8-bit regist er that specifies the conversion time. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0hs1 ada0m1 0 00 ada0fr3 ada0fr2 ada0fr1 ada0fr0 after reset: 00h r/w address: fffff201h ada0hs1 0 1 normal conversion mode high-speed conversion mode specification of normal conversion mode/high-speed mode (a/d conversion time) cautions 1. changing the ada0m1 register is prohibited while a/d conversion is enabled (ada0m0.ada0ce bit = 1). 2. to select the external trigger mode/timer trigger mode (ada0m0.ada0tmd bit = 1), set the high-speed conversion mode (ada0m1.ada0 hs1 bit = 1). do not input a trigger during stabilization time that is inserted only once after the a/d conversion operation is enabled (ada0ce bit = 1). 3. be sure to clear bits 6 to 4 to ?0?. remark for a/d conversion time setting examples, see tables 13-2 and 13-3 . chapter 13 a/d converter user?s manual u17728ej3v1ud 470 table 13-2. conversion time selection in normal conversion mode (ada0hs1 bit = 0) a/d conversion time ada0fr3 to ada0fr0 bits stabilization time + conversion time + wait time f xx = 32 mhz f xx = 20 mhz f xx = 16 mhz f xx = 4 mhz trigger response time 0000 66/f xx (13/f xx + 26/f xx + 27/f xx ) setting prohibited setting prohibited setting prohibited 16.5 s 3/f xx 0001 131/f xx (26/f xx + 52/f xx + 53/f xx ) setting prohibited 6.55 s 8.19 s setting prohibited 3/f xx 0010 196/f xx (39/f xx + 78/f xx + 79/f xx ) setting prohibited 9.80 s 12.25 s setting prohibited 3/f xx 0011 259/f xx (50/f xx + 104/f xx + 105/f xx ) 8.09 s 12.95 s 16.19 s setting prohibited 3/f xx 0100 311/f xx (50/f xx + 130/f xx + 131/f xx ) 9.72 s 15.55 s 19.44 s setting prohibited 3/f xx 0101 363/f xx (50/f xx + 156/f xx + 157/f xx ) 11.34 s 18.15 s 22.69 s setting prohibited 3/f xx 0110 415/f xx (50/f xx + 182/f xx + 183/f xx ) 12.97 s 20.75 s setting prohibited setting prohibited 3/f xx 0111 467/f xx (50/f xx + 208/f xx + 209/f xx ) 14.59 s 23.35 s setting prohibited setting prohibited 3/f xx 1000 519/f xx (50/f xx + 234/f xx + 235/f xx ) 16.22 s setting prohibited setting prohibited setting prohibited 3/f xx 1001 571/f xx (50/f xx + 260/f xx + 261/f xx ) 17.84 s setting prohibited setting prohibited setting prohibited 3/f xx 1010 623/f xx (50/f xx + 286/f xx + 287/f xx ) 19.47 s setting prohibited setting prohibited setting prohibited 3/f xx 1011 675/f xx (50/f xx + 312/f xx + 313/f xx ) 21.09 s setting prohibited setting prohibited setting prohibited 3/f xx others setting prohibited remark stabilization time: a/d converter setup time (1 s or longer) conversion time: actual a/d conversion time (2.6 to 10.4 s) wait time: wait time inserted before the next conversion trigger response time: if a software trigger, exter nal trigger, or timer trigger is generated after the stabilization time, it is inserted before the conversion time. in the normal conversion mode, the conversion is st arted after the stabilization time elapsed from the ada0m0.ada0ce bit is set to 1, and a/d conversion is performed only during the conversion time (2.6 to 10.4 s). operation is stopped after the conversion ends and the a/d conversion end interrupt request signal (intad) is generated after the wait time is elapsed. because the conversion operation is stopped during the wait time, operation current can be reduced. caution set as 2.6 s conversion time 10.4 s. chapter 13 a/d converter user?s manual u17728ej3v1ud 471 table 13-3. conversion time selection in hi gh-speed conversion mode (ada0hs1 bit = 1) a/d conversion time ada0fr3 to ada0fr0 bits conversion time (+ stabilization time) f xx = 32 mhz f xx = 20 mhz f xx = 16 mhz f xx = 4 mhz trigger response time 0000 26/f xx (+ 13/f xx ) setting prohibited setting prohibited setting prohibited 6.5 s (+ 3.25 s) 3/f xx 0001 52/f xx (+ 26/f xx ) setting prohibited 2.6 s (+ 1.3 s) 3.25 s (+ 1.625 s) setting prohibited 3/f xx 0010 78/f xx (+ 39/f xx ) setting prohibited 3.9 s (+ 1.95 s) 4.875 s (+ 2.4375 s) setting prohibited 3/f xx 0011 104/f xx (+ 50/f xx ) 3.25 s (+ 1.5625 s) 5.2 s (+ 2.5 s) 6.5 s (+ 3.125 s) setting prohibited 3/f xx 0100 130/f xx (+ 50/f xx ) 4.0625 s (+ 1.5625 s) 6.5 s (+ 2.5 s) 8.125 s (+ 3.125 s) setting prohibited 3/f xx 0101 156/f xx (+ 50/f xx ) 4.875 s (+ 1.5625 s) 7.8 s (+ 2.5 s) 9.75 s (+ 3.125 s) setting prohibited 3/f xx 0110 182/f xx (+ 50/f xx ) 5.6875 s (+ 1.5625 s) 9.1 s (+ 2.5 s) setting prohibited setting prohibited 3/f xx 0111 208/f xx (+ 50/f xx ) 6.5 s (+ 1.5625 s) 10.4 s (+ 2.5 s) setting prohibited setting prohibited 3/f xx 1000 234/f xx (+ 50/f xx ) 7.3125 s (+ 1.5625 s) setting prohibited setting prohibited setting prohibited 3/f xx 1001 260/f xx (+ 50/f xx ) 8.125 s (+ 1.5625 s) setting prohibited setting prohibited setting prohibited 3/f xx 1010 286/f xx (+ 50/f xx ) 8.9375 s (+ 1.5625 s) setting prohibited setting prohibited setting prohibited 3/f xx 1011 312/f xx (+ 50/f xx ) 9.75 s (+ 1.5625 s) setting prohibited setting prohibited setting prohibited 3/f xx others setting prohibited remark conversion time: actual a/d co nversion time (2.6 to 10.4 s) stabilization time: a/d converter setup time (1 s or longer) trigger response time: if a software trigger, exter nal trigger, or timer trigger is generated after the stabilization time, it is inserted before the conversion time. in the high-speed conversion mode, the conversion is started after the stabilization time elapsed from the ada0m0.ada0ce bit is set to 1, and a/d conversion is performed only during the conversion time (2.6 to 10.4 s). the a/d conversion end interrupt request sig nal (intad) is generated immediately after the conversion ends. in continuous conversion mode, the stabilization time is inserted only before the first conversion, and not inserted after the second conversion (the a/d converter remains running). caution set as 2.6 s conversion time 10.4 s. chapter 13 a/d converter user?s manual u17728ej3v1ud 472 (3) a/d converter mode register 2 (ada0m2) the ada0m2 register specifies the hardware trigger mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ada0m2 0 0 0 00 ada0tmd1 ada0tmd0 ada0tmd1 0 0 1 1 ada0tmd0 0 1 0 1 specification of hardware trigger mode external trigger mode (when adtrg pin valid edge detected) timer trigger mode 0 (when inttp2cc0 interrupt request generated) timer trigger mode 1 (when inttp2cc1 interrupt request generated) setting prohibited after reset: 00h r/w address: fffff203h 6543210 7 cautions 1. in the following modes, write data to the ada0m2 register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and th en enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mo de of the high-speed conversion mode 2. be sure to clear bits 7 to 2 to ?0?. chapter 13 a/d converter user?s manual u17728ej3v1ud 473 (4) a/d converter channel specification register (ada0s) the ada0s register specifies the pin that inputs the analog voltage to be converted into a digital signal. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ada0s 0 0 0 ada0s3 ada0s2 ada0s1 ada0s0 after reset: 00h r/w address: fffff202h ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 setting prohibited setting prohibited setting prohibited setting prohibited ani0 ani0, ani1 ani0 to ani2 ani0 to ani3 ani0 to ani4 ani0 to ani5 ani0 to ani6 ani0 to ani7 ani0 to ani8 ani0 to ani9 ani0 to ani10 ani0 to ani11 setting prohibited setting prohibited setting prohibited setting prohibited ada0s3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ada0s2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ada0s1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ada0s0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 select mode scan mode cautions 1. in the following modes, write data to the ada0s register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and th en enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mo de of the high-speed conversion mode 2. be sure to clear bits 7 to 4 to ?0?. chapter 13 a/d converter user?s manual u17728ej3v1ud 474 (5) a/d conversion result regist ers n, nh (ada0crn, ada0crnh) the ada0crn and ada0crnh registers st ore the a/d conversion results. these registers are read-only, in 16-bit or 8-bit units. however, specify the ada0crn register for 16-bit access and the ada0crnh register for 8-bit access. the 10 bits of the conversion result are read from the higher 10 bits of the ada0crn register, and 0 is read from the lower 6 bits. the higher 8 bits of the conversion result are read from the ada0crnh register. caution accessing the ada0crn and ada0crnh regist ers is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock after reset: undefined r address: ada0cr0 fffff210h, ada0cr1 fffff212h, ada0cr2 fffff214h, ada0cr3 fffff216h, ada0cr4 fffff218h, ada0cr5 fffff21ah, ada0cr6 fffff21ch, ada0cr7 fffff21eh, ada0cr8 fffff220h, ada0cr9 fffff222h, ada0cr10 fffff224h, ada0cr11 fffff226h ada0crn (n = 0 to 11) ad9 ad8 ad7 ad6 ad0000000 ad1 ad2 ad3 ad4 ad5 ad9 ada0crnh (n = 0 to 11) ad8 ad7 ad6 ad5 ad4 ad3 ad2 76 54 32 1 0 after reset: undefined r address: ada0cr0h fffff211h, ada0cr1h fffff213h, ada0cr2h fffff215h, ada0cr3h fffff217h, ada0cr4h fffff219h, ada0cr5h fffff21bh, ada0cr6h fffff21dh, ada0cr7h fffff21fh, ada0cr8h fffff221h, ada0cr9h fffff223h, ada0cr10h fffff225h, ada0cr11h fffff227h caution a write operation to the ada0m0 and ad a0s registers may cause the contents of the ada0crn register to become undefined. afte r the conversion, read the conversion result before writing to the ada0m0 and ada0s regi sters. correct conversion results may not be read if a sequence othe r than the above is used. chapter 13 a/d converter user?s manual u17728ej3v1ud 475 the relationship between the analog volt age input to the analog input pins (a ni0 to ani11) and the a/d conversion result (ada0crn register) is as follows. v in ada0cr = int ( av ref0 1,024 + 0.5) ada0cr note = sar 64 or, av ref0 av ref0 (sar ? 0.5) 1,024 v in < (sar + 0.5) 1,024 int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref0 : av ref0 pin voltage ada0cr: value of ada0crn register note the lower 6 bits of the ada0crn register are fixed to 0. the following shows the relationship between the analo g input voltage and the a/d conversion results. figure 13-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ref0 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion results ada0crn sar ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h chapter 13 a/d converter user?s manual u17728ej3v1ud 476 (6) power-fail compare m ode register (ada0pfm) the ada0pfm register is an 8-bit register that sets the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0pfe power-fail compare disabled power-fail compare enabled ada0pfe 0 1 selection of power-fail compare enable/disable ada0pfm ada0pfc 00 00 0 0 generates an interrupt request signal (intad) when ada0crnh ada0pft generates an interrupt request signal (intad) when ada0crnh < ada0pft ada0pfc 0 1 selection of power-fail compare mode after reset: 00h r/w address: fffff204h <7>6543210 cautions 1. in the select mode, the 8-bit data set to the ada0pft regist er is compared with the value of the ada0crnh register specified by the ada0s register. if the result matches the condition specified by th e ada0pfc bit, the conversion result is stored in the ada0crn register and the intad signal is ge nerated. if it does not match, however, the interrupt signal is not generated. 2. in the scan mode, the 8-bit data set to the ada0pft register is compared with the contents of the ada0cr0h register. if th e result matches the c ondition specified by the ada0pfc bit, the conversion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, however, the intad signal is not generated. regardless of the comparison r esult, the scan operati on is continued and the conversion result is st ored in the ada0crn register until the scan operation is completed. however, the intad signal is not generated after th e scan operation has been completed. 3. in the following modes, write data to the ada0pfm register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and th en enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mo de of the high-speed conversion mode chapter 13 a/d converter user?s manual u17728ej3v1ud 477 (7) power-fail compare thres hold value register (ada0pft) the ada0pft register sets the compare value in the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0pft after reset: 00h r/w address: fffff205h 76 54 321 0 caution in the following modes, write data to the ada0pft register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and then enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mo de of the high-speed conversion mode chapter 13 a/d converter user?s manual u17728ej3v1ud 478 13.5 operation 13.5.1 basic operation <1> set the operation mode, trigger mode, and conversion time for executing a/d conversion by using the ada0m0, ada0m1, ada0m2, and ada0s registers. when the ada0ce bit of the ada0m0 register is set, conversion is started in the software trigger mode and the a/d converter waits for a trigger in the external or timer trigger mode. <2> when a/d conversion is started, the voltage input to the selected anal og input channel is sampled by the sample & hold circuit. <3> when the sample & hold circuit samples the input cha nnel for a specific time, it enters the hold status, and holds the input analog voltage until a/d conversion is complete. <4> set bit 9 of the successive approximation register (sar) to set the compare voltage generation dac to (1/2) av ref0 . <5> the voltage difference between the compare volt age generation dac and the analog input voltage is compared by the voltage comparator. if th e analog input voltage is higher than (1/2) av ref0 , the msb of the sar register remains set. if it is lower than (1/2) av ref0 , the msb is reset. <6> next, bit 8 of the sar register is automatically set and the next comparison is started. depending on the value of bit 9, to which a result has been already set, the compare voltage generation dac is selected as follows. ? bit 9 = 1: (3/4) av ref0 ? bit 9 = 0: (1/4) av ref0 this compare voltage and the analog input voltage are compared and, depending on the result, bit 8 is manipulated as follows. analog input voltage compare voltage: bit 8 = 1 analog input voltage compare voltage: bit 8 = 0 <7> this comparison is continued to bit 0 of the sar register. <8> when comparison of the 10 bits is complete, the valid di gital result is stored in t he sar register, which is then transferred to and stored in the ada0crn register. after that, an a/d conversion end interrupt request signal (intad) is generated. <9> in one-shot select mode, conversion is stopped note . in one-shot scan mode, conversion is stopped after scanning once note . in continuous select mode, repeat steps <2> to <8> until the ada0m0.ada0ce bit is cleared to 0. in continuous scan mode, repeat steps <2> to <8> for each channel. note in the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status is entered. remark the trigger standby status me ans the status after the st abilization time has elapsed. chapter 13 a/d converter user?s manual u17728ej3v1ud 479 13.5.2 conversion op eration timing figure 13-3. conversion operation timing (continuous conversion) (1) operation in normal conversion mode (ada0hs1 bit = 0) ada0m0.ada0ce bit processing state setup stabilization time conversion time wait time sampling first conversion second conversion setup sampling wait a/d conversion intad signal 2/f xx (max.) 0.5/f xx sampling time (2) operation in high-speed con version mode (ada0hs1 bit = 1) ada0m0.ada0ce bit processing state setup conversion time sampling first conversion second conversion sampling a/d conversion a/d conversion intad signal 0.5/f xx stabilization time 2/f xx (max.) sampling time ada0fr3 to ada0fr0 bits stabilization time conversion time (sampling time) wait time trigger response time 0000 13/f xx 26/f xx (8/f xx ) 27/f xx 3/f xx 0001 26/f xx 52/f xx (16/f xx ) 53/f xx 3/f xx 0010 39/f xx 78/f xx (24/f xx ) 79/f xx 3/f xx 0011 50/f xx 104/f xx (32/f xx ) 105/f xx 3/f xx 0100 50/f xx 130/f xx (40/f xx ) 131/f xx 3/f xx 0101 50/f xx 156/f xx (48/f xx ) 157/f xx 3/f xx 0110 50/f xx 182/f xx (56/f xx ) 183f xx 3/f xx 0111 50/f xx 208/f xx (64/f xx ) 209/f xx 3/f xx 1000 50/f xx 234/f xx (72/f xx ) 235/f xx 3/f xx 1001 50/f xx 260/f xx (80/f xx ) 261/f xx 3/f xx 1010 50/f xx 286/f xx (88/f xx ) 287/f xx 3/f xx 1011 50/f xx 312/f xx (96/f xx ) 313/f xx 3/f xx others setting prohibited remark the above timings are when a trigger generates within the stabilization time. if the trigger generates after the stabilization time, a trigger response time is inserted. chapter 13 a/d converter user?s manual u17728ej3v1ud 480 13.5.3 trigger mode the timing of starting the conversion oper ation is specified by setting a trigger mode. the trigger mode includes a software trigger mode and hardware trigger modes. the hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. the ada0m0.ada0tmd bit is us ed to set the trigger mode. the hardware trigger modes are set by the ada0m2.ada0tmd1 and ada0m2.ada0tmd0 bits. (1) software trigger mode when the ada0m0.ada0ce bit is set to 1, the signal of the analog input pin (ani0 to ani11 pin) specified by the ada0s register is converted. when conversion is co mplete, the result is stored in the ada0crn register. at the same time, the a/d conversion end in terrupt request signal (intad) is generated. if the operation mode specified by the ada0m0.ada0md1 and ada0m0.ada0md0 bits is the continuous select/scan mode, the next conversion is started, unless the ada0ce bit is cleared to 0 after completion of the first conversion. conversion is performed once and ends if the operation mode is the one-shot select/scan mode. when conversion is started, the ada0m0.ada0ef bit is set to 1 (indicating that conversion is in progress). if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0 pft register is written during conversion, the conversion is aborted and started agai n from the beginning. however, writing these registers is prohibited in the normal conversion mode and one-shot select m ode/one-shot scan mode of the high-speed conversion mode. (2) external trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani11) specified by the ada0s register is started when an external trigger is input (to the adtrg pin). which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both ri sing and falling edges) can be specified by using the ada0m0.ada0ets1 and ada0m0.ata0ets0 bits. when the ad a0ce bit is set to 1, the a/d converter waits for the trigger, and starts conversion after the external trigger has been input. when conversion is completed, the re sult of conversion is stored in t he ada0crn register, regardless of whether the continuous select, c ontinuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ada0md1 and ada0md0 bits. at the same time, the intad signal is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conver sion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft r egister is written during the conversion operation, the conversion is not aborted, and the a/d converter waits for the trigger again. however, writing these registers is prohibited in the one- shot select mode/one-shot scan mode. caution to select the external trigger mode, set the high-speed conversion mode. do not input a trigger during stabilization time that is inser ted once after the a/d conversion operation is enabled (ada0m0.ada0ce bit = 1). remark the trigger standby status me ans the status after the st abilization time has elapsed. chapter 13 a/d converter user?s manual u17728ej3v1ud 481 (3) timer trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani11) specified by the ada0s register is started by the compare match interrupt request signal (inttp2cc0 or inttp2cc1) of the capture/compare register connected to the timer. the inttp2cc0 or inttp2cc1 signal is selected by the ada0tmd1 and ada0tmd0 bits, and conversion is started at the rising edge of the specified compare match interrupt request signal. when the ada0ce bit is set to 1, the a/d co nverter waits for a trigger, and starts conversion when the compare match interrupt request signal of the timer is input. when conversion is completed, regardless of whether the continuous select, continuous scan, one-shot select, or one-shot scan mode is set as t he operation mode by the ada0md1 and ada0md0 bits, the result of the conversion is stored in the ada0crn register. at the same time, the intad signal is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conver sion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0 pft register is written during conversion, the conversion is stopped and the a/d converter waits for the trigger again. however, writing these registers is prohibited in the one-shot select mode/one-shot scan mode. caution to select the timer trigger mode, set the hi gh-speed conversion mode. do not input a trigger during stabilization time that is inserted once after the a/d co nversion operation is enabled (ada0m0.ada0ce bit = 1). remark the trigger standby status me ans the status after the st abilization time has elapsed. chapter 13 a/d converter user?s manual u17728ej3v1ud 482 13.5.4 operation mode four operation modes are available as t he modes in which to set the ani0 to ani11 pins: continuous select mode, continuous scan mode, one-shot sele ct mode, and one-shot scan mode. the operation mode is selected by the ad a0m0.ada0md1 and ada0m0.ada0md0 bits. (1) continuous select mode in this mode, the voltage of one analog input pin selected by the ada0s register is continuously converted into a digital value. the conversion result is stored in the ada0crn register corresponding to the analog input pin. in this mode, an analog input pin corresponds to an ada0crn register on a one-to-one basis. each time a/d conversion is completed, the a/d conversion end interrupt reques t signal (intad) is generated. after completion of conversion, the next conversion is started, unless the ada0m0.ada0ce bit is cleared to 0 (n = 0 to 11). figure 13-4. timing example of continuous se lect mode operation (ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 (ani1) data 7 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 6 (ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 (2) continuous scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values. the result of each conversion is stored in the ada0cr n register corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0 s register is complete, the intad signal is generated, and a/d conversion is started again from the ani0 pin, unless the ada0ce bit is cleared to 0 (n = 0 to 11). chapter 13 a/d converter user?s manual u17728ej3v1ud 483 figure 13-5. timing example of continuous s can mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) data 7 (ani2) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . . chapter 13 a/d converter user?s manual u17728ej3v1ud 484 (3) one-shot select mode in this mode, the voltage on the analog input pin specifie d by the ada0s register is converted into a digital value only once. the conversion result is stored in the ada0crn register corresponding to the analog input pin. in this mode, an analog input pin and an ada0crn register correspond on a one-to-one basis. when a/d conversion has been completed once, the intad signal is generated. the a/d conversion operation is stopped after it has been completed (n = 0 to 11). figure 13-6. timing example of one-shot sel ect mode operation (ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 6 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 conversion end conversion end (4) one-shot scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values . each conversion result is stored in the ada0crn regi ster corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0s register is complete, the intad signal is generated. a/d conversion is stopped after it has been completed (n = 0 to 11). chapter 13 a/d converter user?s manual u17728ej3v1ud 485 figure 13-7. timing example of one-shot s can mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 (ani2) data 4 ( ani3) data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) ada0crn intad conversion start set ada0ce bit = 1 conversion end ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . . chapter 13 a/d converter user?s manual u17728ej3v1ud 486 13.5.5 power-fail compare mode the a/d conversion end interrupt re quest signal (intad) c an be controlled as foll ows by the ada0pfm and ada0pft registers. ? when the ada0pfm.ada0pfe bit = 0, the intad signal is generated each time conversion is completed (normal use of the a/d converter). ? when the ada0pfe bit = 1 and when t he ada0pfm.ada0pfc bit = 0, the va lue of the ada0crnh register is compared with the value of the ada0pft register wh en conversion is completed, and the intad signal is generated only if ada0crnh ada0pft. ? when the ada0pfe bit = 1 and when the ada0pfc bit = 1, the value of the ada0cr nh register is compared with the value of the ada0pft register when conversion is completed, and the intad signal is generated only if ada0crnh < ada0pft. remark n = 0 to 11 in the power-fail compare mode, four modes are availabl e as modes in which to set the ani0 to ani11 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. chapter 13 a/d converter user?s manual u17728ej3v1ud 487 (1) continuous select mode in this mode, the result of converting the voltage of t he analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conver sion result is stored in the ada0crn register, and the intad signal is not generated. after completion of the fi rst conversion, the next conversion is started, unless the ada0m0.ada0ce bit is cleared to 0 (n = 0 to 11). figure 13-8. timing example of continuous select mode operation (when power-fail comparison is made: ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 ( ani1) data 7 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 2 ( ani1) data 3 ( ani1) data 4 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 ada0pft unmatch ada0pft unmatch ada0pft match ada0pft match ada0pft match conversion start set ada0ce bit = 1 (2) continuous scan mode in this mode, the results of converting the voltages of the analog input pins sequentially selected from the ani0 pin to the pin specified by the ada0s register are st ored, and the set value of the ada0cr0h register of channel 0 is compared with the value of the ada0pft regi ster. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion resu lt is stored in the ada0cr0 register, and the intad signal is generated. if it does not match, the conver sion result is stored in the ada0cr0 register, and the intad signal is not generated. after the result of the first conversion has been stored in the ada0cr0 register, the results of sequentially converting the voltages on the analog input pins up to t he pin specified by the ada0 s register are continuously stored. after completion of conversion, the next conv ersion is started from the ani0 pin again, unless the ada0ce bit is cleared to 0. chapter 13 a/d converter user?s manual u17728ej3v1ud 488 figure 13-9. timing example of continuous scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) data 7 ( ani2) data 1 ( ani0) data 2 (ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ada0pft match ada0pft unmatch ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . . chapter 13 a/d converter user?s manual u17728ej3v1ud 489 (3) one-shot select mode in this mode, the result of converting the voltage of t he analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conver sion result is stored in the ada0crn register, and the intad signal is not generated. conversion is stopped after it has been completed. figure 13-10. timing example of on e-shot select mode operation (when power-fail comparison is made: ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 6 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 ada0pft match conversion end ada0pft unmatch conversion end (4) one-shot scan mode in this mode, the results of converting the voltages of the analog input pins sequentially selected from the ani0 pin to the pin specified by the ada0s register are st ored, and the set value of the ada0cr0h register of channel 0 is compared with the set value of the ada0p ft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conver sion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, the conversion result is stored in the ada0cr0 register, and the intad0 signal is not generated. after the re sult of the first conversion has been stored in the ada0cr0 register, the results of converting the si gnals on the analog input pins specified by the ada0s register are sequentially stored. the conver sion is stopped after it has been completed. chapter 13 a/d converter user?s manual u17728ej3v1ud 490 figure 13-11. timing example of one-shot scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) ada0crn intad conversion start set ada0ce bit = 1 conversion end ada0pft match ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . . chapter 13 a/d converter user?s manual u17728ej3v1ud 491 13.6 cautions (1) when a/d converter is not used when the a/d converter is not used, the power consumption can be reduced by clearing the ada0m0.ada0ce bit to 0. (2) input range of ani0 to ani11 pins input the voltage within the specified range to the ani0 to ani11 pi ns. if a voltage equal to or higher than av ref0 or equal to or lower than av ss (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion valu e of that channel is u ndefined, and the conversi on value of the other channels may also be affected. (3) countermeasures against noise to maintain the 10-bit resolution, the ani0 to ani11 pins must be effectively protected from noise. the influence of noise increases as the output impedance of the analog input sour ce becomes higher. to lower the noise, connecting an external capacitor as shown in figure 13-12 is recommended. figure 13-12. processing of analog input pin av ref0 v dd v ss av ss clamp with a diode with a low v f (0.3 v or less) if noise equal to or higher than av ref0 or equal to or lower than av ss may be generated. ani0 to ani11 chapter 13 a/d converter user?s manual u17728ej3v1ud 492 (4) alternate i/o the analog input (ani0 to ani11) pins are multiplexed with port pins. the av ref0 power pin is multiplexed with the reference power supply to the a/d converter and the i/o buffer power supply of port 7. if any of the following processings is performed during a/d conversion, therefore, the expected a/d conversion value may not be obtained. (a) if a digital pulse is applied to a pin adjacent to a pin whose input analog signal is converted into a digital signal (for example, p72 and p74 pins during ani3 conversion) (cause: influence of coupling noise) (b) if av ref0 power supply fluctuates as a result of executing an instruction to read the p7h or p7l register to the input port during a/d conversion or an instruction to write data to the output port (cause: influence on the av ref0 power supply) (c) if a current flows through a pin of port 7 (p70 to p 711) that is set in the output mode because of the influence of the external circuit connect ed to the port pin and, as a result, the av ref0 power supply fluctuates (cause: influence on the av ref0 power supply) if there is a possibility that any of the above processings may be executed during a/d conversion, be sure to execute a/d conversion more than once, check the a/d conversion value, and eliminate any abnormal value by program. chapter 13 a/d converter user?s manual u17728ej3v1ud 493 (5) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the ada0s regi ster are changed. if the analog input pin is changed during a/d co nversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ada0s register is rewritten. if the adif flag is read immediately after the ada0s register is rewritten, the adif flag may be set even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d conversion is stopped, cl ear the adif flag before resuming conversion. figure 13-13. generation timing of a/d conversion end interrupt request ada0s rewriting (anin conversion start) ada0s rewriting (anim conversion start) adif is set, but anim conversion does not end a/d conversion ada0crn intad anin anin anim anim anim anin anin anim remark n = 0 to 11 m = 0 to 11 (6) internal equivalent circuit the following shows the equivalent circuit of the analog input block. figure 13-14. internal equi valent circuit of anin pin anin c in r in r in c in 14 k 8.0 pf remarks 1. the above values are reference values. 2. n = 0 to 11 chapter 13 a/d converter user?s manual u17728ej3v1ud 494 (7) av ref0 pin (a) the av ref0 pin is used as the power supply pin of the a/d converter and also supplies power to the alternate-function ports. in an application where a backup power supply is used, be sure to supply the same voltage as v dd to the av ref0 pin as shown in figure 13-15. (b) the av ref0 pin is also used as the reference voltage pin of the a/d converter. if the source supplying power to the av ref0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the current that flows during conversion (especially, immediately after the conversion operation enable bit ada0ce has been set to 1). as a result, the conversion accuracy may drop. to avoid this, it is recommended to connect a capacitor across the av ref0 and av ss pins to suppress the reference voltage fluctuation as shown in figure 13-15. (c) if the source supplying power to the av ref0 pin has a high dc resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the a/d conversion current. figure 13-15. av ref0 pin processing example av ref0 note av ss main power supply note parasitic inductance (8) reading ada0crn register when the ada0m0 to ada0m2, ada0s, ada0pfm, or ad a0pft register is written, the contents of the ada0crn register may be undefined. read the conversi on result after completion of conversion and before writing to the ada0m0 to ada0m2, ada0s, ada0pfm, or ada0pft register. also, when an external/timer trigger is acknowledged, the content s of the ada0crn register may be undef ined. read the conversion result after completion of conversion and before the next external/timer trigger is acknowledged. the correct conversion result may not be read at a timing different from the above. (9) standby mode because the a/d converter stops oper ating in the stop mode, conversion results are invalid, so power consumption can be reduced. operations are resu med after the stop mode is released, but the a/d conversion results after the stop mode is released are invalid. when using the a/d converter after the stop mode is released, before setting the stop mode or rele asing the stop mode, clear the ada0m0.ada0ce bit to 0 then set the ada0ce bit to 1 after releasing the stop mode. in the idle1, idle2, or subclock operation mode, oper ation continues. to lower the power consumption, therefore, clear the ada0m0.ada0ce bit to 0. in the idle1 and idle2 modes, since the analog input voltage value cannot be retained, the a/d conversion results a fter the idle1 and idle2 modes are released are invalid. the results of conversions before the id le1 and idle2 modes were set are valid. chapter 13 a/d converter user?s manual u17728ej3v1ud 495 (10) restriction for each mode (a) to select the external trigger mode/timer trigger mode, set the high-speed conversion mode. do not input a trigger during stabilization time that is insert ed once after the a/d conversion operation is enabled (ada0m0.ada0ce bit = 1). (b) in the following modes, write data to the a/d cont rol register while a/d conversion is stopped (ada0ce bit = 0), and then enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot sc an mode of high-speed conversion mode remark a/d control registers: ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers (11) variation of a/d conversion results the results of the a/d conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. to reduce the vari ation, take counteractive measures with the program such as averaging the a/d conversion results. (12) a/d conversion result hysteresis characteristics the successive comparison type a/d converter holds t he analog input voltage in the internal sample & hold capacitor and then performs a/d conversi on. after the a/d conversion ha s finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur. ? when the same channel is used for a/d conversions, if th e voltage is higher or lower than the previous a/d conversion, then hysteresis characteristics may appear where the conversion result is affected by the previous value. thus, even if t he conversion is performed at the same potential, the result may vary. ? when switching the analog input channel, hysteres is characteristics may appear where the conversion result is affected by the previous channel value. this is because one a/d converter is used for the a/d conversions. thus, even if the conversion is perfo rmed at the same potential, the result may vary. chapter 13 a/d converter user?s manual u17728ej3v1ud 496 13.7 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that c an be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit). the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref0 ? 0)/100 = av ref0 /100 when the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between an actually measured value and a theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. the overall error in the characteristics ta ble does not include the quantization error. figure 13-16. overall error ideal line overall error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output chapter 13 a/d converter user?s manual u17728ej3v1ud 497 (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. because the a/d converter converts analog input voltages in a range of 1/2 lsb into the same digital codes, a quantization error is unavoidable. this error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. figure 13-17. quantization error quantization error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 0?000 to 0?001 (1/2 lsb). figure 13-18. zero-scale error av ref0 analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10123 100 011 010 001 000 zero-scale error chapter 13 a/d converter user?s manual u17728ej3v1ud 498 (5) full-scale error this is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1?110 to 1?111 (full scale ? 3/2 lsb). figure 13-19. full-scale error av ref0 analog input (lsb) digital output (lower 3 bits) 111 av ref0 ? 3 0 av ref0 ? 2av ref0 ? 1 100 011 010 000 full-scale error (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error indicates the difference between the actually measured value and its theoretical value when a sp ecific code is output. this indicates the basic characteristics of the a/d conversion when the voltage applied to the analog input pins of the same channel is consistently increased bit by bit from av ss to av ref0 . when the input voltage is increased or decreased, or when two or more channels are used, refer to 13.7 (2) overall error . figure 13-20. differential linearity error ideal width of 1 lsb differential linearity error 1 ...... 1 0 ...... 0 av ref0 analog input digital output chapter 13 a/d converter user?s manual u17728ej3v1ud 499 (7) integral linearity error this error indicates the extent to which the conversion char acteristics differ from the ideal linear relationship. it indicates the maximum value of the difference between t he actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. figure 13-21. integral linearity error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output ideal line integral linearity error (8) conversion time this is the time required to obtain a digital output after each trigger has been generated. the conversion time in the characteristics table includes the sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 13-22. sampling time sampling time conversion time user?s manual u17728ej3v1ud 500 chapter 14 d/a converter 14.1 functions the d/a converter has the following functions. { 8-bit resolution 2 channels (da0cs0, da0cs1) { r-2r ladder method { settling time: 3 s max. (when av ref1 is 3.0 to 3.6 v and external load is 20 pf) { analog output voltage: av ref1 m/256 (m = 0 to 255; value set to da0csn register) { operation modes: normal mo de, real-time output mode remark n = 0, 1 14.2 configuration the d/a converter configur ation is shown below. figure 14-1. block diagram of d/a converter da0cs0 register selector selector da0cs1 register ano0 pin ano1 pin da0m.da0ce0 bit da0m.da0ce1 bit da0cs0 register write da0m.da0md0 bit inttp2cc0 signal da0cs1 register write da0m.da0md1 bit inttp3cc0 signal av ref1 pin av ss pin cautions 1. da converters 0 and 1 share the av ref1 pin. 2. da converters 0 and 1 share the av ss pin. the av ss pin is also shared by the a/d converter. chapter 14 d/a converter user?s manual u17728ej3v1ud 501 the d/a converter consists of the following hardware. table 14-1. configuration of d/a converter item configuration control registers d/a converter mode register (da0m) d/a converter conversion value se tting registers 0, 1 (da0cs0, da0cs1) 14.3 registers the registers that control the d/ a converter are as follows. ? d/a converter mode register (da0m) ? d/a converter conversion value setting registers 0, 1 (da0cs0, da0cs1) (1) d/a converter mode register (da0m) the da0m register controls the operation of the d/a converter. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 normal mode real-time output mode note da0mdn 0 1 selection of d/a converter operation mode (n = 0, 1) da0m 0 da0ce1 da0ce0 0 0 da0md1 da0md0 after reset: 00h r/w address: fffff282h disables operation enables operation da0cen 0 1 control of d/a converter operation enable/disable (n = 0, 1) < > < > note the output trigger in the real-time outpu t mode (da0mdn bit = 1) is as follows. ? when n = 0: inttp2cc0 signal (see chapter 7 16-bit timer/event counter p (tmp) ) ? when n = 1: inttp3cc0 signal (see chapter 7 16-bit timer/event counter p (tmp) ) chapter 14 d/a converter user?s manual u17728ej3v1ud 502 (2) d/a converter conversion value setti ng registers 0, 1 (da0cs0, da0cs1) the da0cs0 and da0cs1 registers set the analog volt age value output to the ano0 and ano1 pins. these registers can be read or written in 8-bit units. reset sets these registers to 00h. da0csn7 da0csn da0csn6 da0csn5 da0csn4 da0csn3 da0csn2 da0csn1 da0csn0 after reset: 00h r/w address: da0cs0 fffff280h, da0cs1 fffff281h caution in the real-time output mode (da0m.da0mdn bit = 1), set the da0csn register before the inttp2cc0/inttp3cc0 signals are generated. d/a conversion starts when the inttp2cc0/inttp3cc0 signa ls are generated. remark n = 0, 1 chapter 14 d/a converter user?s manual u17728ej3v1ud 503 14.4 operation 14.4.1 operation in normal mode d/a conversion is performed using a write operation to the da0csn register as the trigger. the setting method is described below. <1> set the da0m.da0mdn bit to 0 (normal mode). <2> set the analog voltage value to be output to the anon pin to the da0csn register. steps <1> and <2> above constitute the initial settings. <3> set the da0m.da0cen bit to 1 (d/a conversion enable). d/a conversion starts when this setting is performed. <4> to perform subsequent d/a conversions, write to the da0csn register. the previous d/a conversion result is held until the next d/a conversion is performed. remarks 1. for the alternate-function pin settings, see table 4-15 using port pin as alternate-function pin . 2. n = 0, 1 14.4.2 operation in real-time output mode d/a conversion is performed using the interrupt reques t signals (inttp2cc0 and inttp3cc0) of tmp2 and tmp3 as triggers. the setting method is described below. <1> set the da0m.da0mdn bit to 1 (real-time output mode). <2> set the analog voltage value to be output to the anon pin to the da0csn register. <3> set the da0m.da0cen bit to 1 (d/a conversion enable). steps <1> to <3> above consti tute the initial settings. <4> operate tmp2 and tmp3. <5> d/a conversion starts when the inttp2cc0 and inttp3cc0 signals are generated. <6> after that, the value set in da0csn register is out put every time the inttp2cc0 and inttp3cc0 signals are generated. remarks 1. the output values of the ano0 and ano1 pins up to <5> above are undefined. 2. for the output values of the ano0 and ano1 pi ns in the halt, idle1, idle2, and stop modes, see chapter 24 standby function . 3. for the alternate-function pin settings, see table 4-15 using port pin as alternate-function pin . chapter 14 d/a converter user?s manual u17728ej3v1ud 504 14.4.3 cautions observe the following cautions when using the d/a converter of the v850es/sg3. (1) do not change the set value of the da0csn register while the trigger signal is being issued in the real-time output mode. (2) before changing the operation mode, be sure to clear the da0m.da0cen bit to 0. (3) when using one of the p10/an00 and p11/an01 pins as an i/o port and the other as a d/ a output pin, do so in an application where the port i/o level does not change during d/a output. (4) make sure that av ref0 = v dd = av ref1 = 3.0 to 3.6 v. if this range is exceeded, the operation is not guaranteed. (5) apply power to av ref1 at the same timing as av ref0 . (6) no current can be output from the anon pin (n = 0, 1) because the output impedanc e of the d/a converter is high. when connecting a resistor of 2 m or less, insert a jfet input operational amplifier between the resistor and the anon pin. figure 14-2. external pin connection example av ref1 v dd output 10 f 0.1 f 10 f 0.1 f av ref0 anon av ss ? + jfet input operational amplifier (7) because the d/a converter stops operation in the stop mode, the ano0 and ano1 pins go into a high- impedance state, and the power consumption can be reduced. in the idle1, idle2, or subclock operation mode, however, the operation continues. to lower the power consumption, therefore, clear the da0m.da0cen bit to 0. user?s manual u17728ej3v1ud 505 chapter 15 asynchronous ser ial interface a (uarta) 15.1 mode switching of uarta and other serial interfaces 15.1.1 csib4 and uarta0 mode switching in the v850es/sg3, csib4 and uarta0 are alternate f unctions of the same pin and therefore cannot be used simultaneously. set uarta0 in advance, using the pmc3 and pfc3 registers, before use. caution the transmit/receive operation of csib4 and uarta0 is not guaranteed if these functions are switched during transmission or reception. be su re to disable the one that is not used. figure 15-1. csib4 and uarta0 mode switch settings pmc3 after reset: 0000h r/w address: fffff446h, fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, fffff467h 0 0 0 0 0 0 pfc39 pfc38 pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfce3l after reset: 00h r/w address: fffff706h 0 0 0 0 0 pfce32 0 0 port i/o mode ascka0 mode sckb4 mode port i/o mode uarta0 mode csib4 mode pmc32 0 1 1 pmc3n 0 1 1 operation mode operation mode pfce32 0 0 pfc32 0 1 pfc3n 0 1 remarks 1. n = 0, 1 2. = don?t care chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 506 15.1.2 uarta2 and i 2 c00 mode switching in the v850es/sg3, uarta2 and i 2 c00 are alternate functions of the same pin and therefore cannot be used simultaneously. set uarta2 in advance, using the pmc3 and pfc3 registers, before use. caution the transmit/receive operation of uarta2 and i 2 c00 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 15-2. uarta2 and i 2 c00 mode switch settings pmc3 after reset: 0000h r/w address: fffff446h, fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, fffff467h 0 0 0 0 0 0 pfc39 pfc38 pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 port i/o mode uarta2 mode i 2 c00 mode pmc3n 0 1 1 operation mode pfc3n 0 1 remarks 1. n = 8, 9 2. = don?t care chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 507 15.1.3 uarta1 and i 2 c02 mode switching in the v850es/sg3, uarta1 and i 2 c02 are alternate functions of the same pin and therefore cannot be used simultaneously. set uarta1 in advance, using the pmc9, pfc9, and pmce9 registers, before use. caution the transmit/receive operation of uarta1 and i 2 c02 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 15-3. uarta1 and i 2 c02 mode switch settings pmc9 after reset: 0000h r/w address: fffff452h, fffff453h pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 pfc9 after reset: 0000h r/w address: fffff472h, fffff473h pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 0 0 0 0 0 0 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 pfce9 after reset: 0000h r/w address: fffff712h, fffff713h uarta1 mode i 2 c02 mode pmc9n 1 1 operation mode pfce9n 1 1 pfc9n 0 1 remark n = 0, 1 chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 508 15.2 features { transfer rate: 300 bps to 625 kbps (using internal system clock of 32 mhz and dedicated baud rate generator) { full-duplex communication: internal uartan receive data register (uanrx) internal uartan transmit data register (uantx) { 2-pin configuration: txdan: transmit data output pin rxdan: receive data input pin { reception error output function ? parity error ? framing error ? overrun error { interrupt sources: 2 ? reception complete interrupt (intuanr): this inte rrupt occurs upon transfer of receive data from the receive shift register to the uanr x register after serial transfer completion, in the reception enabled status. ? transmission enable interrupt (intuant): this interr upt occurs upon transfer of transmit data from the uantx register to the transmit shift register in the transmission enabled status. { character length: 7, 8 bits { parity function: odd, even, 0, none { transmission stop bit: 1, 2 bits { on-chip dedicated baud rate generator { msb-/lsb-first transfer selectable { transmit/receive data inverted input/output possible { sbf (sync break field) transmission/reception in the li n (local interconnect network) communication format ? 13 to 20 bits selectable for the sbf transmission ? recognition of 11 bits or more possible for sbf reception ? sbf reception flag provided remark n = 0 to 2 chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 509 15.3 configuration the block diagram of the uartan is shown below. figure 15-4. block diagram of a synchronous serial interface an internal bus internal bus uanopt0 uanctl0 uanstr uanctl1 uanctl2 receive shift register uanrx filter selector uantx transmit shift register transmission controller reception controller selector baud rate generator baud rate generator intuanr intuant txdan rxdan f xx to f xx /2 10 ascka0 note reception unit transmission unit clock selector note uarta0 only remarks 1. n = 0 to 2 2. for the configuration of the baud rate generator, see figure 15-16 . uartan consists of the following hardware units. table 15-1. configuration of uartan item configuration registers uartan control register 0 (uanctl0) uartan control register 1 (uanctl1) uartan control register 2 (uanctl2) uartan option control register 0 (uanopt0) uartan status register (uanstr) uartan receive shift register uartan receive data register (uanrx) uartan transmit shift register uartan transmit data register (uantx) chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 510 (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register used to specify the uartan operation. (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register used to select the input clock for the uartan. (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register us ed to control the baud rate for the uartan. (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit register used to control serial transfer for the uartan. (5) uartan status register (uanstr) the uanstrn register consists of fl ags indicating the error contents when a reception error occurs. each one of the reception error flags is set (to 1) upon occurrence of a reception error. (6) uartan receive shift register this is a shift register used to convert the serial data input to the rxdan pin into parallel data. upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the uanrx register. this register cannot be manipulated directly. (7) uartan receive data register (uanrx) the uanrx register is an 8-bit register that holds receiv e data. when 7 characters are received, 0 is stored in the highest bit (when data is received lsb first). in the reception enabled status, receive data is transfe rred from the uartan receive shift register to the uanrx register in synchronization with the comple tion of shift-in processing of 1 frame. transfer to the uanrx register also causes the recept ion complete interrupt request signal (intuanr) to be output. (8) uartan transmit shift register the transmit shift register is a shift register used to convert the parallel data transferred from the uantx register into serial data. when 1 byte of data is transferred from the uantx register, the shift register data is output from the txdan pin. this register cannot be manipulated directly. (9) uartan transmit data register (uantx) the uantx register is an 8-bit transmit data buffer. tr ansmission starts when transmit data is written to the uantx register. when data can be wri tten to the uantx register (when dat a of one frame is transferred from the uantx register to the uartan transmit shift regi ster), the transmission enable interrupt request signal (intuant) is generated. chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 511 15.4 registers (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register that c ontrols the uartan serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 10h. (1/2) uanpwr disable uartan operation (uartan reset asynchronously) enable uartan operation uanpwr 0 1 uartan operation control uanctl0 (n = 0 to 2) uantxe uanrxe uandir uanps1 uanps0 uancl uansl <6> <5> <4> 3 2 1 after reset: 10h r/w address: ua0ctl0 fffffa00h, ua1ctl0 fffffa10h, ua2ctl0 fffffa20h the uartan operation is controlled by the uanpwr bit. the txdan pin output is fixed to high level by clearing the uanpwr bit to 0 (fixed to low level if uanopt0.uantdl bit = 1). disable transmission operation enable transmission operation uantxe 0 1 transmission operation enable <7> 0 ? to start transmission, set the uanpwr bit to 1 and then set the uantxe bit to 1. ? to initialize the transmission unit, clear the uantxe bit to 0, wait for two cycles of the base clock (f uclk ), and then set the uantxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 15.7 (1) (a) base clock ). ? when the operation is enabled (uanpwr bit = 1), the transmission operation is enabled after two or more cycles of the base clock (f uclk ) have elapsed since uantxe = 1. ? when the uanpwr bit is cleared to 0, the status of the internal circuit becomes the same status as uantxe bit = 0 by the uanpwr bit even if the uantxe bit is 1. the transmission operation is enabled when the uanpwr bit is set to 1 again. chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 512 (2/2) 7 bits 8 bits uancl note 0 1 specification of data character length of 1 frame of transmit/receive data 1 bit 2 bits uansl note 0 1 specification of length of stop bit for transmit data only the first bit of the receive data stop bits is checked, regardless of the value of the uansl bit. ? if ?reception with 0 parity? is selected during reception, a parity check is not performed. therefore, the uanstr.uanpe bit is not set. ? when transmission and reception are performed in the lin format, clear the uanps1 and uanps0 bits to 00. no parity output 0 parity output odd parity output even parity output reception with no parity reception with 0 parity odd parity check even parity check uanps1 note 0 0 1 1 parity selection during transmission parity selection during reception uanps0 note 0 1 0 1 msb-first transfer lsb-first transfer uandir note 0 1 transfer direction selection disable reception operation enable reception operation uanrxe 0 1 reception operation enable ? to start reception, set the uanpwr bit to 1 and then set the uanrxe bit to 1. ? to initialize the reception unit, clear the uanrxe bit to 0, wait for two cycles of the base clock, and then set the uanrxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 15.7 (1) (a) base clock ). ? when the operation is enabled (uanpwr bit = 1), the reception operation is enabled after two or more cycles of the base clock (f uclk ) have elapsed since uanrxe = 1. if the start bit is received before the reception operation is enabled, the start bit is ignored. ? when the uanpwr bit is cleared to 0, the status of the internal circuit becomes the same status as uanrxe bit = 0 by the uanpwr bit even if the uanrxe bit is 1. the reception operation is enabled when the uanpwr bit is set to 1 again. note this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = uanrxe bit = 0. however, setting any or all of the uanpwr, uantxe, and uanrxe bits to 1 at the same time is possible. remark for details of parity, see 15.6.9 parity types and operations . chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 513 (2) uartan control register 1 (uanctl1) for details, see 15.7 (2) uartan control register 1 (uanctl1) . (3) uartan control register 2 (uanctl2) for details, see 15.7 (3) uartan control register 2 (uanctl2) . (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit regist er that controls the serial transfer operation of the uartan register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 14h. caution do not set the uansrt and uanstt bits (to 1) during sbf reception (uansrf bit = 1). (1/2) uansrf when the uanctl0.uanpwr bit = uanctl0.uanrxe bit = 0 are set. also upon normal end of sbf reception. during sbf reception uansrf 0 1 sbf reception flag uanopt0 (n = 0 to 2) uansrt uanstt uansls2 uansls1 uansls0 uantdl uanrdl 654321 after reset: 14h r/w address: ua0opt0 fffffa03h, ua1opt0 fffffa13h, ua2opt0 fffffa23h sbf reception trigger uansrt 0 1 sbf reception trigger ? sbf (sync brake field) reception is judged during lin communication. ? the uansrf bit is held at 1 when an sbf reception error occurs, and then sbf reception is started again. ? this is the sbf reception trigger bit during lin communication, and when read, ?0? is always read. for sbf reception, set the uansrt bit (to 1) to enable sbf reception. ? set the uansrt bit after setting both the uanpwr bit and uanrxe bit to 1. ? set the uansrt bit (to 1) during a period of 1 bit after the reception end interrupt request signal (intuanr) has been generated. (if this bit is set (to 1) during reception operation, the uansrf bit is cleared when reception of the current data is completed, even if sbf is not received.) ? writing 0 to the uansrt bit is valid. if 0 is written to the uansrt bit before sbf reception is started, therefore, sbf is not received but normal uart reception is executed. if 0 is written to the uanopt0 register during sbf reception, data that has already been received is received as sbf. if the data being received is not sbf, however, the following data operate as the receive data of uart, starting from the next receive data. the uansrf bit is cleared when 0 is written to the uansrt bit. <7> 0 ? chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 514 (2/2) uansls2 1 1 1 0 0 0 0 1 uansls1 0 1 1 0 0 1 1 0 uansls0 1 0 1 0 1 0 1 0 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output sbf transmit length selection ? the output level of the txdan pin can be inverted using the uantdl bit. ? this register can be set when the uanpwr bit = 0 or when the uantxe bit = 0. this register can be set when the uanpwr bit = 0 or when the uantxe bit = 0. normal output of transfer data inverted output of transfer data uantdl 0 1 transmit data level bit ? the input level of the rxdan pin can be inverted using the uanrdl bit. ? this register can be set when the uanpwr bit = 0 or the uanrxe bit = 0. ? when the uanrdl bit is set to 1 (inverted input of receive data), reception must be enabled (uanctl0.uanrxe bit = 1) after setting the data reception pin to the uart reception pin (rxdan) when reception is started. when the pin mode is changed after reception is enabled, the start bit will be mistakenly detected if the pin level is high. normal input of transfer data inverted input of transfer data uanrdl 0 1 receive data level bit ? this is the sbf transmission trigger bit during lin communication, and when read, ?0? is always read. ? set the uanstt bit after setting the uanpwr bit = uantxe bit = 1. ? writing 0 to the uanstt bit is valid. if 0 is written to this bit after 1 has been written to it and before it is sampled with the base clock, sbf transmission is therefore not executed. if 0 is written to the uanstt bit during sbf transmission, the uanstr.uantsf bit is cleared to 0 even though sbf transmission is executed. sbf transmission trigger uanstt 0 1 sbf transmission trigger ? chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 515 (5) uartan status register (uanstr) the uanstr register is an 8-bit register that displays t he uartan transfer status and reception error contents. this register can be read or written in 8-bit or 1-bi t units, but the uantsf bit is a read-only bit, while the uanpe, uanfe, and uanove bits can both be read and written. however, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained). the initialization conditions are shown below. register/bit initialization conditions uanstr register ? reset ? uanctl0.uanpwr = 0 uantsf bit ? uanctl0.uantxe = 0 uanpe, uanfe, uanove bits ? 0 write ? uanctl0.uanrxe = 0 caution be sure to read the er ror flags of the uanpe, uanfe, an d uanove bits to check the flag status, and then clear the flags by writing ?0? to them. chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 516 uantsf ? when the uanpwr bit = 0 or the uantxe bit = 0 has been set. ? when, following transfer completion, there was no next data transfer from uantx register write to uantx register uantsf 0 1 transfer status flag uanstr (n = 0 to 2) 0 0 0 0 uanpe uanfe uanove 6 5 4 3 <2> <1> after reset: 00h r/w address: ua0str fffffa04h, ua1str fffffa14h, ua2str fffffa24h the uantsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the uantsf bit = 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the uantsf bit = 1. ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. ? when 0 has been written when parity of data and parity bit do not match during reception. uanpe 0 1 parity error flag ? the operation of the uanpe bit is controlled by the settings of the uanctl0.uanps1 and uanctl0.uanps0 bits. ? the uanpe bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained. ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set ? when 0 has been written when no stop bit is detected during reception uanfe 0 1 framing error flag ? only the first bit of the receive data stop bits is checked, regardless of the value of the uanctl0.uansl bit. ? the uanfe bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained . ? when the uanpwr bit = 0 or the uanrxe bit = 0 has been set. ? when 0 has been written when receive data has been set to the uanrx register and the next receive operation is completed before that receive data has been read uanove 0 1 overrun error flag ? when an overrun error occurs, the data is discarded without the next receive data being written to the uanrx register. ? the uanove bit can be both read and written, but it can only be cleared by writing 0 to it. when 1 is written to this bit, the value is retained . <7> <0> chapter 15 asynchronous serial interface a (uarta) user?s manual u17728ej3v1ud 517 (6) uartan receive data register (uanrx) the uanrx register is an 8-bit buffer r egister that stores parallel data conver ted by the receive shift register. the data stored in the receive shift register is transfe rred to the uanrx register upon completion of reception of 1 byte of data. the reception end interrupt r equest signal (intuanr) is generated in this timing. during lsb-first reception when the data length has been s pecified as 7 bits, the receive data is transferred to bits 6 to 0 of the uanrx register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the uanrx register and the lsb always becomes 0. when an overrun error (uanove) occurs, the receive data at this time is not transferred to the uanrx register and is discarded. this register is read-only, in 8-bit units. in addition to reset input, the uanrx register can be set to ffh by clearing the uanctl0.uanpwr bit to 0. uanrx (n = 0 to 2) 654321 after reset: ffh r address: ua0rx fffffa06h, ua1rx fffffa16h, ua2rx fffffa26h 7 0 (7) uartan transmit data register (uantx) the uantx register is an 8-bit register used to set transmit data. transmission starts when transmit data is written to t he uantx register in the transmission enabled status (uanctl0.uantxe bit = 1). when the data of the uantx register has been transferred to the transmit shift register, the transmission enable interr upt request signal (intuant) is generated. this register can be read or written in 8-bit units. reset sets this register to ffh. uantx (n = 0 to 2) 654321 after reset: ffh r/w address: ua0tx fffffa07h, ua1tx fffffa17h, ua2tx fffffa27h 7 0 |