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| ? 2010 microchip technology inc. ds41326e pic16f526 data sheet 14-pin, 8-bit flash microcontroller
ds41326e-page 2 ? 2010 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2010, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-355-4 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ? 2010 microchip technology inc. ds41326e-page 3 pic16f526 high-performance risc cpu: ? only 33 single-word instructions ? all single-cycle instructions except for program branches which are two-cycle ? two-level deep hardware stack ? direct, indirect and relative addressing modes for data and instructions ? operating speed: - dc ? 20 mhz crystal oscillator - dc ? 200 ns instruction cycle ? on-chip flash program memory: - 1024 x 12 ? general purpose registers (sram): -67 x 8 ? flash data memory: -64 x 8 special microcontroller features: ? 8 mhz precision internal oscillator: - factory calibrated to 1% ? in-circuit serial programming? (icsp?) ? in-circuit debugging (icd) support ? power-on reset (por) ? device reset timer (drt) ? watchdog timer (wdt) with dedicated on-chip rc oscillator for reliable operation ? programmable code protection ? multiplexed mclr input pin ? internal weak pull-ups on i/o pins ? power-saving sleep mode ? wake-up from sleep on pin change ? selectable oscillator options: - intrc: 4 mhz or 8 mhz precision internal rc oscillator - extrc: external low-cost rc oscillator - xt: standard crystal/resonator - hs: high-speed crystal/resonator - lp: power-saving, low-frequency crystal - ec: high-speed external clock input low-power features/cmos technology: ? standby current: - 100 na @ 2.0v, typical ? operating current: -11 ? a @ 32 khz, 2.0v, typical -175 ? a @ 4 mhz, 2.0v, typical ? watchdog timer current: -1 ? a @ 2.0v, typical -7 ? a @ 5.0v, typical ? high endurance program and flash data memory cells: - 100,000 write program memory endurance - 1,000,000 write flash data memory endurance - program and flash data retention: >40 years ? fully static design ? wide operating voltage range: 2.0v to 5.5v: - wide temperature range - industrial: -40 ? c to +85 ? c - extended: -40 ? c to +125 ? c peripheral features: ? 12 i/o pins: - 11 i/o pins with individual direction control - 1 input-only pin - high current sink/source for direct led drive - wake-up on change - weak pull-ups ? 8-bit real-time clock/counter (tmr0) with 8-bit programmable prescaler ? two analog comparators: - comparator inputs and output accessible externally - one comparator with 0.6v fixed on-chip absolute voltage reference (v ref ) - one comparator with programmable on-chip voltage reference (v ref ) ? analog-to-digital (a/d) converter: - 8-bit resolution - 3-channel external programmable inputs - 1-channel internal input to internal absolute 0.6 voltage reference device program memory data memory i/o comparators timers 8-bit 8-bit a/d channels flash (words) sram (bytes) flash (bytes) pic16f526 1024 67 64 12 2 1 3 14-pin, 8-bit flas h microcontroller pic16f526 ds41326e-page 4 ? 2010 microchip technology inc. figure 1-1: 14-pin pdip , soic, tssop diagram figure 1-2: 16-pin qfn diagram v dd rb5/osc1/clkin rb4/osc2/clkout rb3/mclr /v pp rc5/t0cki rc4/c2out rc3 v ss rb0/c1in+/an0/icspdat rb1/c1in-/an1/icspclk rb2/c1out/an2 rc0/c2in+ rc1/c2in- rc2/cv ref pic16f526 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pic16f526 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd nc nc gnd rc5/t0cki rb4/osc2/clkout rb3/mclr /v pp rb5/osc1/clkin rb0/c1in+/an0/icspdat rb1/c1in-/an1/icspclk rb2/c1out/an2 rc0/c2in+ rc4/c2out rc3 rc2/cv ref rc1/c2in- ? 2010 microchip technology inc. ds41326e-page 5 pic16f526 table of contents 1.0 general description......................................................................................................... ............................................................ 7 2.0 pic16f526 device varieties .................................................................................................. .................................................... 9 3.0 architectural overview ...................................................................................................... ........................................................ 11 4.0 memory organization ......................................................................................................... ....................................................... 15 5.0 flash data memory control ................................................................................................... ................................................... 23 6.0 i/o port .................................................................................................................... .................................................................. 27 7.0 timer0 module and tmr0 register ............................................................................................. ............................................. 37 8.0 special features of the cpu................................................................................................. .................................................... 43 9.0 analog-to-digital (a/d) converter........................................................................................... ................................................... 59 10.0 comparator(s) .............................................................................................................. ............................................................. 63 11.0 comparator voltage reference module........................................................................................ ............................................ 69 12.0 instruction set summary .................................................................................................... ....................................................... 71 13.0 development support........................................................................................................ ........................................................ 79 14.0 electrical characteristics ................................................................................................. .......................................................... 83 15.0 dc and ac characteristics graphs and charts ................................................................................ ........................................ 97 16.0 packaging information...................................................................................................... ....................................................... 107 the microchip web site ......................................................................................................... ........................................................... 115 customer change notification service ........................................................................................... .................................................. 115 customer support............................................................................................................... .............................................................. 115 reader response ................................................................................................................ ............................................................. 116 index .......................................................................................................................... ........................................................................ 117 product identification system................ .................................................................................. ......................................................... 119 to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro - chip products. to this end, we will continue to improve our pub lications to better suit your needs. our publications will be re fined and enhanced as new volumes and updates are introduced. if you have any questions or comments regard ing this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this dat a sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de lit- erature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products. pic16f526 ds41326e-page 6 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds41326e-page 7 pic16f526 1.0 general description the pic16f526 device from microchip technology is low-cost, high-performance, 8-bit, fully-static, flash- based cmos microcontrollers. it employs a risc architecture with only 33 single-word/single-cycle instructions. all instructions are single cycle (200 ? s) except for program branches, which take two cycles. the pic16f526 device delivers performance an order of magnitude higher than their competitors in the same price category. the 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. the easy-to-use and easy to remember instruction set reduces development time significantly. the pic16f526 product is equipped with special features that reduce system cost and power requirements. the power-on reset (por) and device reset timer (drt) eliminate the need for external reset circuitry. there are four oscillator configurations to choose from, including intrc internal oscillator mode and the power-saving lp (low-power) oscillator mode. power-saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the pic16f526 device is available in the cost-effective flash programmable version, which is suitable for production in any volume. the customer can take full advantage of microchip?s price leadership in flash programmable microcontrollers, while benefiting from the flash programmable flexibility. the pic16f526 product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ?c? compiler, a low-cost development programmer and a full featured programmer. all the tools are supported on ibm ? pc and compatible machines. 1.1 applications the pic16f526 device fits in applications ranging from personal care appliances and security systems to low- power remote transmitters/receivers. the flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. the small footprint packages, for through hole or surface mounting, make these microcontrollers perfect for applications with space limitations. low cost, low power, high performance, ease of use and i/o flexibility make the pic16f526 device very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, logic and plds in larger systems and coprocessor applications). table 1-1: features and memory of pic16f526 pic16f526 clock maximum frequency of operation (mhz) 20 memory flash program memory 1024 sram data memory (bytes) 67 flash data memory (bytes) 64 peripherals timer module(s) tmr0 wake-up from sleep on pin change yes features i/o pins 11 input pins 1 internal pull-ups yes in-circuit serial programming tm yes number of instructions 33 packages 14-pin pdip, soic, tssop, qfn the pic16f526 device has power-on reset, selectable watchdog timer, selectable code-protect, high i/o current capability and precision internal oscillator. the pic16f526 device uses serial program ming with data pin rb0 and clock pin rb1. pic16f526 ds41326e-page 8 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds41326e-page 9 pic16f526 2.0 pic16f526 device varieties a variety of packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic16f526 product identification system at the back of this data sheet to specify the correct part number. 2.1 quick turn programming (qtp) devices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. the devices are identical to the flash devices but with all flash locations and fuse options already programmed by the factory. certain code and prototype verification procedures do apply before production shipments are available. please contact your local microchip technology sales office for more details. 2.2 serialized quick turn programming sm (sqtp sm ) devices microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number, which can serve as an entry code, password or id number. pic16f526 ds41326e-page 10 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds41326e-page 11 pic16f526 3.0 architectural overview the high performance of the pic16f526 device can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic16f526 device uses a harvard architecture in which program and data are accessed on separate buses. this improves bandwidth over traditional von neumann architectures where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. a 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions. consequently, all instructions (33) execute in a single cycle (200 ns @ 20 mhz, 1 ? s @ 4 mhz) except for program branches. table 3-1 below lists memory supported by the pic16f526 device. table 3-1: pic16f526 memory the pic16f526 device can directly or indirectly address its register files and data memory. all special function registers (sfr), including the pc, are mapped in the data memory. the pic16f526 device has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. this sym- metrical nature and lack of ?special optimal situations? make programming with the pic16f526 device simple, yet efficient. in addition, the learning curve is reduced significantly. the pic16f526 device contains an 8-bit alu and working register. the alu is a general purpose arith- metic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8 bits wide and capable of addition, subtrac- tion, shift and logical operations. unless otherwise mentioned, arithmetic operations are two?s comple- ment in nature. in two-operand instructions, one operand is typically the w (working) register. the other operand is either a file register or an immediate constant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc) and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the subwf and addwf instructions for examples. a simplified block diagram is shown in figure 3-2, with the corresponding device pins described in table 3-2. device program memory data memory flash (words) sram (bytes) flash (bytes) pic16f526 1024 67 64 pic16f526 ds41326e-page 12 ? 2010 microchip technology inc. figure 3-1: pic16f 526 block diagram 11 data bus 8 12 program bus instruction reg program counter ram file registers direct addr 5 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg device reset power-on reset watchdog timer instruction decode and control timing generation osc1/clkin osc2/clkout mclr v dd , v ss timer0 portb 8 8 rb4/osc2/clkout rb3/mclr/v pp rb2 rb1/icspclk rb0/icspdat 5-7 3 rb5/osc1/clkin stack1 stack2 67 internal rc clock bytes timer portc rc4 rc3 rc2 rc1 rc0 rc5/t0cki comparator 2 c1in+ c1in- c1out c2in+ c2in- c2out an0 an1 an2 v ref 8-bit adc cv ref cv ref cv ref v ref comparator 1 flash program memory 1k x 12 memory 64x8 flash data ? 2010 microchip technology inc. ds41326e-page 13 pic16f526 table 3-2: pic16f526 pinout description name function input type output type description rb0//c1in+/an0/ icspdat rb0 ttl cmos bidirectional i/o pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. c1in+ an ? comparator 1 input. an0 an ? adc channel input. icspdat st cmos icsp? mode schmitt trigger. rb1/c1in-/an1/ icspclk rb1 ttl cmos bidirectional i/o pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. c1in- an ? comparator 1 input. an1 an ? adc channel input. icspclk st cmos icsp mode schmitt trigger. rb2/c1out/an2 rb2 ttl cmos bidirectional i/o pin. c1out ? cmos comparator 1 output. an2 an ? adc channel input. rb3/mclr /v pp rb3 ttl ? input pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. mclr st ? master clear (reset). when configured as mclr , this pin is an active-low reset to the device. voltage on mclr /v pp must not exceed v dd during normal device operation or the device will enter programming mode. weak pull-up always on if configured as mclr . v pp hv ? programming voltage input. rb4/osc2/clkout rb4 ttl cmos bidirectional i/o pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. osc2 ? xtal oscillator crystal output. connections to crystal or resonator in crystal oscillator mode (xt, hs and lp modes only, portb in other modes). clkout ? cmos extrc/intrc clkout pin (f osc /4). rb5/osc1/clkin rb5 ttl cmos bidirectional i/o pin. osc1 xtal ? oscillator crystal input. clkin st ? external clock source input. rc0/c2in+ rc0 ttl cmos bidirectional i/o port. c2in+ an ? comparator 2 input. rc1/c2in- rc1 ttl cmos bidirectional i/o port. c2in- an ? comparator 2 input. rc2/cv ref rc2 ttl cmos bidirectional i/o port. cv ref ? an programmable voltage reference output. rc3 rc3 ttl cmos bidirectional i/o port. rc4/c2out rc4 ttl cmos bidirectional i/o port. c2out ? cmos comparator 2 output. rc5/t0cki rc5 ttl cmos bidirectional i/o port. t0cki st ? timer0 schmitt trigger input pin. v dd v dd ? p positive supply for logic and i/o pins. v ss v ss ? p ground reference for logic and i/o pins. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input, hv = high voltage pic16f526 ds41326e-page 14 ? 2010 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pc is incremented every q1 and the instruction is fetched from program memory and latched into the instruction register in q4. it is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-2 and example 3-1. 3.2 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the pc to change (e.g., goto ), then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the pc incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock /instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc pc pc + 1 pc + 2 fetch inst (pc) execute inst (pc ? 1) fetch inst (pc + 1) execute inst (pc) fetch inst (pc + 2) execute inst (pc + 1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles, since the fetch instruction is ?flushed? from the pipeline, while the new instruction is being fetched and then executed. 1. movlw 03h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf portb, bit1 fetch 4 flush fetch sub_1 execute sub_1 ? 2010 microchip technology inc. ds41326e-page 15 pic16f526 4.0 memory organization the pic16f526 memories are organized into program memory and data memory (sram).the self-writable portion of the program memory called flash data memory is located at addresses at 400h-43fh. all program mode commands that work on the normal flash memory work on the flash data memory. this includes bulk erase, row/column/cycling toggles, load and read data commands (refer to section 5.0 ?flash data memory control? for more details). for devices with more than 512 bytes of program memory, a paging scheme is used. program memory pages are accessed using one status register bit. for the pic16f526, with data memory register files of more than 32 registers, a banking scheme is used. data memory banks are accessed using the file select register (fsr). 4.1 program memory organization for the pic16f526 the pic16f526 device has an 11-bit program counter (pc) capable of addressing a 2k x 12 program memory space. program memory is partitioned into user memory, data memory and configuration memory spaces. the user memory space is the on-chip user program memory. as shown in figure 4-1, it extends from 0x000 to 0x3ff and partitions into pages, including reset vector at address 0x3ff. the data memory space is the flash data memory block and is located at addresses pc = 400h-43fh. all program mode commands that work on the normal flash memory work on the flash data memory block. this includes bulk erase, load and read data commands. the configuration memory space extends from 0x440 to 0x7ff. locations from 0x448 through 0x49f are reserved. the user id locations extend from 0x440 through 0x443. the backup osccal locations extend from 0x444 through 0x447. the configuration word is physically located at 0x7ff. refer to ? pic16f526 memory programming specification ? (ds41317) for more details. figure 4-1: memory map 000h 1ffh reset vector on-chip user program memory (page 0) 200h 3ffh 3feh user id locations reserved configuration word 400h 443h 444h 7feh 7ffh 43fh 440h unimplemented on-chip user program memory (page 1) data memory flash data memory 448h 49fh backup osccal locations 447h 4a0h configuration memory space space user memory space pic16f526 ds41326e-page 16 ? 2010 microchip technology inc. 4.2 data memory (sram and fsrs) data memory is composed of registers or bytes of sram. therefore, data memory for a device is specified by its register file. the register file is divided into two functional groups: special function registers (sfr) and general purpose registers (gpr). the special function registers are registers used by the cpu and peripheral functions for controlling desired operations of the pic16f526. see figure 4-1 for details. the pic16f526 register file is composed of 16 special function registers and 67 general purpose registers. 4.2.1 general purpose register file the general purpose register file is accessed, either directly or indirectly, through the file select register (fsr). see section 4.8 ?indirect data addressing: indf and fsr registers? . 4.2.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral functions to control the operation of the device (table 4-1). the special function registers can be classified into two sets. the special function registers associated with the ?core? functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. figure 4-2: register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal portb 10h bank 0 bank 1 bank 2 bank 3 3fh 30h 20h 5fh 50h 40h 7fh 70h 60h general purpose registers general purpose registers general purpose registers general purpose registers general purpose registers portc 08h note 1: not a physical register. see section 4.8 ?indirect data addressing: indf and fsr registers? . fsr<6:5> 00 01 10 11 2fh 4fh 6fh 0dh cm1con0 cm2con0 vrcon 09h 0ah 0bh adres adcon0 0ch 0fh indf (1) eecon pcl status fsr eedata eeadr cm1con0 cm2con0 vrcon adres adcon0 indf (1) tmr0 pcl status fsr osccal portb portc vrcon adres adcon0 indf (1) eecon pcl status fsr eedata eeadr vrcon adres adcon0 cm1con0 cm1con0 cm2con0 cm2con0 portc portc addresses map back to addresses in bank 0. ? 2010 microchip technology inc. ds41326e-page 17 pic16f526 table 4-1: special function register (sfr) summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset page # n/a tris ? ? i/o control register (portb, portc) --11 1111 27 n/a option contains control bits to configure timer0 and timer0/wdt prescaler 1111 1111 19 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22 01h/41h tmr0 timer0 module register xxxx xxxx 37 02h (1) pcl low order 8 bits of pc 1111 1111 21 03h status rbwuf cwuf pa0 to pd zdcc 0001 1xxx 18 04h fsr indirect data memory address pointer 100x xxxx 22 05h/45h osccal cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? 1111 111- 20 06h/46h portb ? ? rb5 rb4 rb3 rb2 rb1 rb0 --xx xxxx 27 07h portc ? ? rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx 28 08h cm1con0 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu q111 1111 63 09h adcon0 ans1 ans0 adcs1 adcs0 chs1 chs0 go/done adon 1111 1100 61 0ah adres adc conversion result xxxx xxxx 62 0bh cm2con0 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu q111 1111 64 0ch vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 001- 1111 69 21h/61h eecon ? ? ? free wrerr wren wr rd ---0 x000 23 25h/65h eedata self read/write data xxxx xxxx 23 26h/66h eeadr ? ? self read/write address --xx xxxx 23 legend: x = unknown, u = unchanged, ? = unimplemented, read as ' 0 ' (if applicable), q = value depends on condition. shaded cells = unimplemented or unused note 1: the upper byte of the program counter is not directly accessible. see section 4.6 ?program counter? for an explanation of how to access these bits. pic16f526 ds41326e-page 18 ? 2010 microchip technology inc. 4.3 status register this register contains the arithmetic status of the alu, the reset status and the page preselect bit. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status, will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). therefore, it is recommended that only bcf , bsf and movwf instructions be used to alter the status register. these instructions do not affect the z, dc or c bits from the status register. for other instructions which do affect status bits, see section 12.0 ?instruction set summary? . register 4-1: status: status register r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x rbwuf cwuf pa0 to pd zdcc bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbwuf : wake-up from sleep on pin change bit 1 = reset due to wake-up from sleep on pin change 0 = after power-up or other reset bit 6 cwuf: wake-up from sleep on comparator change bit 1 = reset due to wake-up from sleep on comparator change 0 = after power-up or other reset bit 5 pa0 : program page preselect bit 1 = page 1 (000h-1ffh) 0 = page 0 (200h-3ffh) bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit (for addwf and subwf instructions) addwf: 1 = a carry from the 4th low-order bit of the result occurred 0 = a carry from the 4th low-order bit of the result did not occur subwf: 1 = a borrow from the 4th low-order bit of the result did not occur 0 = a borrow from the 4th low-order bit of the result occurred bit 0 c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf: subwf: rrf or rlf: 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred ? 2010 microchip technology inc. ds41326e-page 19 pic16f526 4.4 option register the option register is a 8-bit wide, write-only register, which contains various control bits to configure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option register. a reset sets the option <7:0> bits. note: if tris bit is set to ? 0 ?, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that tris overrides option control of rbpu and rbwu ). register 4-2: option: option register w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 rbwu rbpu t0cs (1) t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbwu : enable wake-up on pin change bit (rb0, rb1, rb3, rb4) 1 = disabled 0 = enabled bit 6 rbpu : enable weak pull-ups bit (rb0, rb1, rb3, rb4) 1 = disabled 0 = enabled bit 5 t0cs: timer0 clock source select bit (1) 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0 ps<2:0>: prescaler rate select bits note 1: if the t0cs bit is set to ? 1 ?, it will override the tris function on the t0cki pin. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate pic16f526 ds41326e-page 20 ? 2010 microchip technology inc. 4.5 osccal register the oscillator calibration (osccal) register is used to calibrate the 8 mhz internal oscillator macro. it contains 7 bits of calibration that uses a two?s complement scheme for controlling the oscillator speed. see register 4-3 for details. register 4-3: osccal: osci llator calibration register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u-0 cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 cal<6:0> : oscillator calibration bits 0111111 = maximum frequency ? ? ? 0000001 0000000 = center frequency 1111111 ? ? ? 1000000 = minimum frequency bit 0 unimplemented : read as ? 0 ? ? 2010 microchip technology inc. ds41326e-page 21 pic16f526 4.6 program counter as a program instruction is executed, the program counter (pc) will contain the address of the next program instruction to be executed. the pc value is increased by one every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. the program counter (pcl) is mapped to pc<7:0>. bit 5 of the status register provides page information to bit 9 of the pc (figure 4-3). for a call instruction, or any instruction where the pcl is the destination, bits 7:0 of the pc again are provided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 4-3). instructions where the pcl is the destination, or modify pcl instructions, include movwf pcl, addwf pcl and bsf pcl,5. figure 4-3: loading of pc branch instructions 4.6.1 effects of reset the pc is set upon a reset, which means that the pc addresses the last location in the last page (i.e., the oscillator calibration instruction). after executing movlw xx , the pc will roll over to location 00h and begin executing user code. the status register page preselect bits are cleared upon a reset, which means that page 0 is pre-selected. therefore, upon a reset, a goto instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 4.7 stack the pic16f526 device has a 2-deep, 12-bit wide hardware push/pop stack. a call instruction will push the current value of stack 1 into stack 2 and then push the current pc value, incre- mented by one, into stack level 1. if more than two sequential call s are executed, only the most recent two return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the pc and then copy stack level 2 contents into stack level 1. if more than two sequential retlw s are executed, the stack will be filled with the address previously stored in stack level 2. note that the w register will be loaded with the literal value specified in the instruction. this is particularly useful for the implementation of data look-up tables within the program memory. note: because bit 8 of the pc is cleared in the call instruction or any modify pcl instruction, all subroutine calls or com- puted jumps are limited to the first 256 locations of any program memory page (512 words long). pa0 status pc 87 0 pcl 9 10 instruction word 7 0 goto instruction call or modify pcl instruction pa0 status pc 87 0 pcl 9 10 instruction word 7 0 reset to ? 0 ? note 1: there are no status bits to indicate stack overflows or stack underflow conditions. 2: there are no instruction mnemonics called push or pop. these are actions that occur from the execution of the call and retlw instructions. pic16f526 ds41326e-page 22 ? 2010 microchip technology inc. 4.8 indirect data addressing: indf and fsr registers the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. reading indf itself indirectly (fsr = 0 ) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). the fsr is an 8-bit wide register. it is used in conjunction with the indf register to indirectly address the data memory area. the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. fsr<6:5> are the bank select bits and are used to select the bank to be addressed ( 00 = bank 0, 01 =bank 1, 10 = bank 2, 11 = bank 3). fsr<7> is unimplemented and read as ? 1 ?. a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-1. example 4-1: how to clear ram using indirect addressing figure 4-4: direct/indirect addressing movlw 0x10 ;initialize p ointer movwf fsr ;to ram next clrf indf ;clear indf ;register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue : note 1: for register map detail see figure 4-1. bank select location select location select bank select indirect addressing direct addressing data memory (1) 0ch 0dh 0 4 5 6 (fsr) 10 00 01 11 00h 0fh 2fh 4fh 6fh (opcode) 0 4 5 6 (fsr) addresses map back to addresses in bank 0. 3 2 1 3 2 1 10h bank 0 bank 1 bank 2 bank 3 1fh 3fh 5fh 7fh ? 2010 microchip technology inc. ds41326e-page 23 pic16f526 5.0 flash data memory control the flash data memory is readable and writable during normal operation (full v dd range). this memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers (sfrs). 5.1 reading flash data memory to read a flash data memory location the user must: ? write the eeadr register ? set the rd bit of the eecon register the value written to the eeadr register determines which flash data memory location is read. setting the rd bit of the eecon register initiates the read. data from the flash data memory read is available in the eedata register immediately. the eedata register will hold this value until another read is initiated or it is modified by a write operation. program execution is suspended while the read cycle is in progress. execution will continue with the instruction following the one that sets the wr bit. see example 1 for sample code. example 1: reading from flash data memory 5.2 writing and erasing flash data memory flash data memory is erased one row at a time and written one byte at a time. the 64-byte array is made up of eight rows. a row contains eight sequential bytes. row boundaries exist every eight bytes. generally, the procedure to write a byte of data to flash data memory is: 1. identify the row containing the address where the byte will be written. 2. if there is other information in that row that must be saved, copy those bytes from flash data memory to ram. 3. perform a row erase of the row of interest. 4. write the new byte of data and any saved bytes back to the appropriate addresses in flash data memory. to prevent accidental corruption of the flash data memory, an unlock sequence is required to initiate a write or erase cycle. this sequence requires that the bit set instructions used to configure the eecon register happen exactly as shown in example 2 and example 3, depending on the operation requested. 5.2.1 erasing flash data memory a row must be manually erased before writing new data. the following sequence must be performed for a single row erase. 1. load eeadr with an address in the row to be erased. 2. set the free bit to enable the erase. 3. set the wren bit to enable write access to the array. 4. set the wr bit to initiate the erase cycle. if the wren bit is not set in the instruction cycle after the free bit is set, the free bit will be cleared in hardware. if the wr bit is not set in the instruction cycle after the wren bit is set, the wren bit will be cleared in hardware. sample code that follows this procedure is included in example 2. program execution is suspended while the erase cycle is in progress. execution will continue with the instruction following the one that sets the wr bit. example 2: erasing a flash data memory row note: only a bsf command will work to enable the flash data memory read documented in example 1. no other sequence of commands will work, no exceptions. banksel eeadr ; movf data_ee_addr, w ; movwf eeadr ;data memory ;address to read banksel eecon1 ; bsf eecon, rd ;ee read movf eedata, w ;w = eedata note 1: the free bit may be set by any com- mand normally used by the core. how- ever, the wren and wr bits can only be set using a series of bsf commands, as documented in example 1. no other sequence of commands will work, no exceptions. 2: bits <5:3> of the eeadr register indicate which row is to be erased. banksel eeadr movlw ee_adr_erase ; load address of row to ; erase movwf eeadr ; bsf eecon,free ; select erase bsf eecon,wren ; enable writes bsf eecon,wr ; inititate erase pic16f526 ds41326e-page 24 ? 2010 microchip technology inc. 5.2.2 writing to flash data memory once a cell is erased, new data can be written. program execution is suspended during the write cycle. the following sequence must be performed for a single byte write. 1. load eeadr with the address. 2. load eedata with the data to write. 3. set the wren bit to enable write access to the array. 4. set the wr bit to initiate the erase cycle. if the wr bit is not set in the instruction cycle after the wren bit is set, the wren bit will be cleared in hardware. sample code that follows this procedure is included in example 3. example 3: writing a flash data memory row 5.3 write verify depending on the application, good programming practice may dictate that data written to the flash data memory be verified. example 4 is an example of a write verify. example 4: write verify of flash data memory register 5-1: eedata: flash data register register 5-2: eeadr: flash address register banksel eeadr movlw ee_adr_write ; load address movwf eeadr ; movlw ee_data_to_write ; load data movwf eedata ; into eedata register bsf eecon,wren ; enable writes bsf eecon,wr ; inititate erase note 1: only a series of bsf commands will work to enable the memory write sequence documented in example 2. no other sequence of commands will work, no exceptions. 2: for reads, erases and writes to the flash data memory, there is no need to insert a nop into the user code as is done on mid- range devices. the instruction immediately following the ? bsf eecon,wr/rd ? will be fetched and executed properly. movf eedata, w ;eedata has not changed ;from previous write bsf eecon, rd ;read the value written xorwf eedata, w ; btfss status, z ;is data the same goto write_err ;no, handle error ;yes, continue r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eedata7 eedata6 eedata5 eedata4 eedata3 eedata2 eedata1 eedata0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 eedata<7:0> : 8-bits of data to be read from/written to data flash u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? eeadr5 eeadr4 eeadr3 eeadr2 eeadr1 eeadr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ?. bit 5-0 eeadr<5:0> : 6-bits of data to be read from/written to data flash ? 2010 microchip technology inc. ds41326e-page 25 pic16f526 register 5-3: eecon: flash control register 5.4 code protection code protection does not prevent the cpu from performing read or write operations on the flash data memory. refer to the code protection chapter for more information. u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? free wrerr wren wr rd bit 7 bit 0 legend: s = bit can only be set r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ?. bit 4 free: flash data memory row erase enable bit 1 = program memory row being pointed to by eeadr will be erased on the next write cycle. no write will be performed. this bit is cleared at the completion of the erase operation. 0 = perform write only bit 3 wrerr: write error flag bit 1 = a write operation terminated prematurely (by device reset) 0 = write operation completed successfully bit 2 wren: write enable bit 1 = allows write cycle to flash data memory 0 = inhibits write cycle to flash data memory bit 1 wr: write control bit 1 = initiate a erase or write cycle 0 = write/erase cycle is complete bit 0 rd: read control bit 1 = initiate a read of flash data memory 0 = do not read flash data memory pic16f526 ds41326e-page 26 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds41326e-page 27 pic16f526 6.0 i/o port as with any other register, the i/o register(s) can be written and read under program control. however, read instructions (e.g., movf portb,w ) always read the i/o pins independent of the pin?s input/output modes. on reset, all i/o ports are defined as input (inputs are at high- impedance) since the i/o control registers are all set. 6.1 portb portb is a 6-bit i/o register. only the low-order 6 bits are used (rb<5:0>). bits 7 and 6 are unimplemented and read as ? 0 ?s. please note that rb3 is an input-only pin. the configuration word can set several i/o?s to alternate functions. when acting as alternate functions, the pins will read as ? 0 ? during a port read. pins rb0, rb1, rb3 and rb4 can be configured with weak pull- ups and also for wake-up on change. the wake-up on change and weak pull-up functions are not pin selectable. if rb3/mclr is configured as mclr , weak pull-up is always on and wake-up on change for this pin is not enabled. 6.2 portc portc is a 6-bit i/o register. only the low-order 6 bits are used (rc<5:0>). bits 7 and 6 are unimplemented and read as ? 0 ?s. 6.3 tris register the output driver control register is loaded with the contents of the w register by executing the tris f instruction. a ? 1 ? from a tris register bit puts the corresponding output driver in a high-impedance mode. a ? 0 ? puts the contents of the output data latch on the selected pins, enabling the output buffer. the exceptions are rb3, which is input-only and the t0cki pin, which may be controlled by the option register. see register 4-2. tris registers are ?write-only?. active bits in these registers are set (output drivers disabled) upon reset. table 6-1: weak pull-up enabled pins device rb0 weak pull-up rb1 weak pull-up rb3 weak pull-up (1) rb4 weak pull-up pic16f526 yes yes yes yes note 1: when mclren = 1 , the weak pull-up on rb3/mclr is always enabled. register 6-1: port b: portb register u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? rb5 rb4 rb3 rb2 rb1 rb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-0 rb<5:0> : portb i/o pin bits 1 = port pin is >v ih min. 0 = port pin is pic16f526 ds41326e-page 30 ? 2010 microchip technology inc. figure 6-2: block diag ram of rb2 figure 6-3: block diagram of rb3 (with weak pull-up and wake-up on change) data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . 0 1 c1outen adc c1out adc pin enable i/o pin (1) data bus rd port note 1: rb3/mclr pin has a protection diode to v ss only. gppu d ck q pin change mclre rbpu reset input pin ? 2010 microchip technology inc. ds41326e-page 31 pic16f526 figure 6-4: block diagram of rb4 (with weak pull-up and wake-up on change) figure 6-5: block diagram of rb5 data bus q d q ck q d q ck wr port tris ?f? data tris w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . 2: input mode is disabled when pin is used for oscillator. 3: pin is not used for oscillator. 1 0 intosc/rc/ec clkout enable f osc /4 oscillator circuit osc1 rbpu i/o pin (1) (note 2) d ck q rd port pin change (note 3) data bus q d q ck q d q ck wr port tris ?f? data tris rd port i/o pin (1) w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . 2: input mode is disabled when pin is used for oscillator. oscillator circuit osc2 (note 2) pic16f526 ds41326e-page 32 ? 2010 microchip technology inc. figure 6-6: blo ck diagram of rc0/rc1 figure 6-7: block diagram of rc2 data bus q d q ck q d q ck wr port tris ?f? data tris rd port i/o pin (1) w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . comp pin enable comp2 data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . 0 1 vroe i/o pin (1) cv ref ? 2010 microchip technology inc. ds41326e-page 33 pic16f526 figure 6-8: block diag ram of rc3 figure 6-9: block diagram of rc4 data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . i/o pin (1) data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset 0 1 c2outen c2out note 1: i/o pins have protection diodes to v dd and v ss . i/o pin (1) pic16f526 ds41326e-page 34 ? 2010 microchip technology inc. figure 6-10: blo ck diagram of rc5 data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . t0cs t0cki i/o pin (1) ? 2010 microchip technology inc. ds41326e-page 35 pic16f526 table 6-2: summary of port registers table 6-3: i/o pins order of precedence addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a tris ? ? i/o control register (portb, portc) --11 1111 --11 1111 n/a option rbwu rbpu tocs tose psa ps2 ps1 ps0 1111 1111 1111 1111 03h status rbwuf cwuf pa0 to pd z dc c 0001 1xxx qq0q quuu (1) 06h portb ? ? rb5 rb4 rb3 rb2 rb1 rb0 --xx xxxx --uu uuuu 07h portc ? ? rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx --uu uuuu legend: shaded cells are not used by port registers, read as ? 0 ?. ? = unimplemented, read as ? 0 ?, x = unknown, u = unchanged, q = depends on condition. note 1: if reset was due to wake-up on pin change, then bit 7 = 1 . all other resets will cause bit 7 = 0 . priority rb0 rb1 rb2 rb3 rc0 rc1 rc2 rc4 rc5 1 an0 an1 an2 rb3/mclr c2in+ c2in- cv ref c2out t0cki 2 c1in+ c1in- c1out ? trisc trisc trisc trisc trisc 3 trisb trisb trisb ? ? ? ? ? ? pic16f526 ds41326e-page 36 ? 2010 microchip technology inc. 6.5 i/o programming considerations 6.5.1 bidirectional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and rewrite the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit 5 of portb will cause all eight bits of portb to be read into the cpu, bit 5 to be set and the portb value to be written to the output latches. if another bit of portb is used as a bidirec- tional i/o pin (say bit 0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit 0 is switched into output mode later on, the content of the data latch may now be unknown. example 6-1 shows the effect of two sequential read-modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (?wired or?, ?wired and?). the resulting high output currents may damage the chip. example 6-1: read-modify-write instructions on an i/o port(e.g. dstemp) 6.5.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 6-11). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the cpu. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 6-11: successive i/o operation ;initial portb settings ;portb<5:3> inputs ;portb<2:0> outputs ; ; portb latch portb pins ; ---------- ---------- bcf portb, 5 ;--01 -ppp --11 pppp bcf portb, 4 ;--10 -ppp --11 pppp movlw 007h; tris portb ;--10 -ppp --11 pppp ; note 1: the user may have expected the pin values to be ? --00 pppp ?. the 2nd bcf caused rb5 to be latched as the pin value (high). pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb<5:0> movwf portb nop port pin sampled here nop movf portb , w instruction executed movwf portb (write to portb) nop movf portb,w this example shows a write to portb followed by a read from portb. data setup time = (0.25 t cy ? t pd ) where: t cy = instruction cycle. t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic. (read portb) port pin written here ? 2010 microchip technology inc. ds41326e-page 37 pic16f526 7.0 timer0 module and tmr0 register the timer0 module has the following features: ? 8-bit timer/counter register, tmr0 ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select: - edge select for external clock figure 7-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit of the option register. in timer mode, the timer0 module will increment every instruction cycle (without pres- caler). if tmr0 register is written, the increment is inhibited for the following two cycles (figure 7-2 and figure 7-3). the user can work around this by writing an adjusted value to the tmr0 register. there are two types of counter mode. the first counter mode uses the t0cki pin to increment timer0. it is selected by setting the t0cs bit of the option regis- ter, setting the c1t0cs bit of the cm1con0 register and setting the c1outen bit of the cm1con0 regis- ter. in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the t0se bit of the option register determines the source edge. clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 7.1 ?using timer0 with an external clock? . the second counter mode uses the output of the comparator to increment timer0. it can be entered in two different ways. the first way is selected by setting the t0cs bit of the option register, and clearing the c1t0cs bit of the cm1con0 register (c1outen [cm1con0<6>] does not affect this mode of operation). this enables an internal connection between the comparator and the timer0. the prescaler may be used by either the timer0 module or the watchdog timer, but not both. the prescaler assignment is controlled in software by the control bit, psa of the option register. clearing the psa bit will assign the prescaler to timer0. the pres- caler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 7.2 ?prescaler? details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 7-1. figure 7-1: timer0 block diagram note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register. 2: the prescaler is shared with the watchdog timer. 3: the c1t0cs bit is in the cm1con0 register. t0cki t0se (1) 0 1 1 0 pin t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg ps out (2 cycle delay) ps out data bus 8 psa (1) ps2 (1) , ps1 (1) , ps0 (1) 3 sync 0 1 comparator output c1t0cs (3) pic16f526 ds41326e-page 38 ? 2010 microchip technology inc. figure 7-2: timer0 timing: in ternal clock/no prescale figure 7-3: timer0 timing: internal clock/prescale 1:2 table 7-1: registers associated with timer0 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 01h tmr0 timer0 ? 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 08h cm1con0 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu 1111 1111 uuuu uuuu 0bh cm2con0 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu 1111 1111 uuuu uuuu n/a option rbwu rbpu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 n/a tris (1) ? ? i/o control register (portb, portc) --11 1111 --11 1111 legend: shaded cells are not used by timer0. ? = unimplemented, x = unknown, u = unchanged. note 1: the tris of the t0cki pin is overridden when t0cs = 1 . pc ? 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetch timer0 pc pc + 1 pc + 2 pc + 3 pc + 4 pc + 6 t0 t0 + 1 t0 + 2 nt0 nt0 + 1 nt0 + 2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc + 5 pc (program counter) pc ? 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetch timer0 pc pc + 1 pc + 2 pc + 3 pc + 4 pc + 6 t0 t0 + 1 nt0 nt0 + 1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc + 5 pc (program counter) ? 2010 microchip technology inc. ds41326e-page 39 pic16f526 7.1 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. also, there is a delay in the actual incrementing of timer0 after synchronization. 7.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 7-4). therefore, it is necessary for t0cki to be high for at least 2 t osc (and a small rc delay of 2 tt0h) and low for at least 2 t osc (and a small rc delay of 2 tt0h). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. for the external clock to meet the sampling require- ment, the ripple counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4 t osc (and a small rc delay of 4 tt0h) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of tt0h. refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 7.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actually incremented. figure 7-4 shows the delay from the external clock edge to the timer incrementing. figure 7-4: timer0 timing with external clock increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) prescaler output (2) (1) note 1: delay from clock input change to timer0 increment is 3 t osc to 7 t osc . (duration of q = t osc ). therefore, the error in measuring the interval between two edges on timer0 input = 4 t osc max. 2: external clock if no prescaler selected; prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs. pic16f526 ds41326e-page 40 ? 2010 microchip technology inc. 7.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module or as a postscaler for the watchdog timer (wdt), respectively (see section 8.6 ?watch- dog timer (wdt)? ). for simplicity, this counter is being referred to as ?prescaler? throughout this data sheet. the psa and ps<2:0> bits of the option register determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0 , movwf tmr0, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is neither readable nor writable. on a reset, the prescaler contains all ? 0 ?s. 7.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on-the-fly? during program execution). to avoid an unintended device reset, the following instruction sequence (example 7- 1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 7-1: changing prescaler (timer0 ?? wdt) to change the prescaler from the wdt to the timer0 module, use the sequence shown in example 7-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switching the prescaler. example 7-2: changing prescaler (wdt ?? timer0) note: the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt and vice versa. clrwdt ;clear wdt clrf tmr0 ;clear tmr0 & prescaler movlw b'00xx1111' clrwdt ;ps<2:0> are 000 or 001 movlw b'00xx1xxx' ;set postscaler to option ;desired wdt rate clrwdt ;clear wdt and ;prescaler movlw b'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source option ? 2010 microchip technology inc. ds41326e-page 41 pic16f526 figure 7-5: block diagram of the timer0/wdt prescaler t cy (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8-to-1 mux m mux watchdog timer psa (1) 0 1 0 1 wdt time-out ps<2:0> (1) 8 psa (1) wdt enable bit 0 1 0 1 data bus 8 psa (1) t0cs (1) m u x m u x u x t0se (1) note 1: t0cs, t0se, psa, ps<2:0> are bits in the option register. t0cki pin 0 1 c1tocs comparator output pic16f526 ds41326e-page 42 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds41326e-page 43 pic16f526 8.0 special features of the cpu what sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. the pic16f526 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power- saving operating modes and offer code protection. these features are: ? oscillator selection ? reset: - power-on reset (por) - device reset timer (drt) - wake-up from sleep on pin change ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming? ?clock out the pic16f526 device has a watchdog timer, which can be shut off only through configuration bit wdte. it runs off of its own rc oscillator for added reliability. if using hs, xt or lp selectable oscillator options, there is always an 18 ms (nominal) delay provided by the device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. if using intrc or extrc, there is a 1 ms delay only on v dd power-up. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through a change on input pins or through a watchdog timer time-out. several oscillator options are also made available to allow the part to fit the application, including an internal 4/8 mhz oscillator. the extrc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. 8.1 configuration bits the pic16f526 configuration words consist of 12 bits. configuration bits can be programmed to select various device configurations. three bits are for the selection of the oscillator type; one bit is the watchdog timer enable bit, one bit is the mclr enable bit and one bit is for code protection (register 8-1). pic16f526 ds41326e-page 44 ? 2010 microchip technology inc. register 8-1: config: co nfiguration word register cp df ioscfs mclre cp wdte fosc2 fosc1 fosc0 bit 7 bit 0 bit 7 cp df : code protection bit ? flash data memory 1 = code protection off 0 = code protection on bit 6 ioscfs: internal oscillator frequency select bit 1 = 8 mhz intosc frequency 0 = 4 mhz intosc frequency bit 5 mclre: master clear enable bit 1 = rb3/mclr pin functions as mclr 0 = rb3/mclr pin functions as rb3, mclr internally tied to v dd bit 4 cp : code protection bit ? user program memory 1 = code protection off 0 = code protection on bit 3 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 2-0 fosc<2:0>: oscillator selection bits 000 = lp oscillator and 18 ms drt 001 = xt oscillator and 18 ms drt 010 = hs oscillator and 18 ms drt 011 = ec oscillator with rb4 function on rb4/osc2/clkout and 1 ms drt (1) 100 = intrc with rb4 function on rb4/osc2/clkout and 1 ms drt (1) 101 = intrc with clkout function on rb4/osc2/clkout and 1 ms drt (1) 110 = extrc with rb4 function on rb4/osc2/clkout and 1 ms drt (1) 111 = extrc with clkout function on rb4/osc2/clkout and 1 ms drt (1) note 1: refer to the ? pic16f526 memory programming specification ?, ds41317 to determine how to access the configuration word. 2: drt length (18 ms or 1 ms) is a function of clock mode selection. it is the responsibility of the application designer to ensure the use of either 18 ms (nominal) drt or the 1 ms (nominal) drt will result in acceptable operation. refer to section 14.1 ?dc characteristics: pic16f526 (industrial)? and section 14.2 ?dc characteristics: pic16f526 (extended)? for v dd rise time and stability requirements for this mode of operation. ? 2010 microchip technology inc. ds41326e-page 45 pic16f526 8.2 oscillator configurations 8.2.1 oscillator types the pic16f526 device can be operated in up to six different oscillator modes. the user can program up to three configuration bits (fosc<2:0>). to select one of these modes: ? lp: low-power crystal ? xt: crystal/resonator ? hs: high-speed crystal/resonator ? intrc: internal 4/8 mhz oscillator ? extrc: external resistor/capacitor ? ec: external high-speed clock input 8.2.2 crystal oscillator/ceramic resonators in hs, xt or lp modes, a crystal or ceramic resonator is connected to the rb5/osc1/clkin and rb4/osc2/ clkout pins to establish oscillation (figure 8-1). the pic16f526 oscillator designs require the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in hs, xt or lp modes, the device can have an external clock source drive the rb5/osc1/clkin pin (figure 8-2). in this mode, the output drive levels on the osc2 pin are very weak. if the part is used in this fashion, then this pin should be left open and unloaded. also when using this mode, the external clock should observe the frequency limits for the clock mode chosen (hs, xt or lp). figure 8-1: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) figure 8-2: external clock input operation (hs, xt, lp or ec osc configuration) table 8-1: capacitor selection for ceramic resonators note 1: this device has been designed to per- form to the parameters of its data sheet. it has been tested to an electrical specification designed to determine its conformance with these parameters. due to process differences in the manufacture of this device, this device may have different performance charac- teristics than its earlier version. these differences may cause this device to perform differently in your application than the earlier version of this device. 2: the user should verify that the device oscillator starts and performs as expected. adjusting the loading capacitor values and/or the oscillator mode may be required. osc type resonator freq. cap. range c1 cap. range c2 xt 4.0 mhz 30 pf 30 pf hs 16 mhz 10-47 pf 10-47 pf note 1: these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf approx. value = 10 m ? . c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic16f526 clock from ext. system pic16f526 osc2/clkout/rb4 rb5/osc1/clkin osc2/clkout/rb4 (1) ec, hs, xt, lp note 1: rb4 is available in ec mode only. pic16f526 ds41326e-page 46 ? 2010 microchip technology inc. table 8-2: capacitor selection for crystal oscillator (2) 8.2.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crystal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. figure 8-3 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k ? resistor provides the negative feedback for stability. the 10 k ? potentiometers bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 8-3: external parallel resonant crystal oscillator circuit figure 8-4 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator circuit. the 330 ? resistors provide the negative feedback to bias the inverters in their linear region. figure 8-4: external series resonant crystal oscillator circuit 8.2.4 external rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit-to-unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 8-5 shows how the r/c combination is con- nected to the pic16f526 device. for r ext values below 3.0 k ? , the oscillator operation may become unstable, or stop completely. for very high r ext values (e.g., 1 m ? ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping r ext between 5.0 k ? and 100 k ? . although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. section 14.0 ?electrical characteristics? shows rc frequency variation from part-to-part due to normal process variation. the variation is larger for larger val- ues of r (since leakage current variation will affect rc frequency more for large r) and for smaller values of c (since variation of input capacitance will affect rc frequency more). osc type resonator freq. cap. range c1 cap. range c2 lp 32 khz (1) 15 pf 15 pf xt 200 khz 1 mhz 4 mhz 47-68 pf 15 pf 15 pf 47-68 pf 15 pf 15 pf hs 20 mhz 15-47 pf 15-47 pf note 1: for v dd > 4.5v, c1 = c2 ? 30 pf is recommended. 2: these values are for design guidance only. rs may be required to avoid over- driving crystals with low drive level specifi- cation. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 clkin to o t h e r devices pic16f526 330 74as04 74as04 pic16f526 clkin to other devices xtal 330 74as04 0.1 mf ? 2010 microchip technology inc. ds41326e-page 47 pic16f526 also, see the electrical specifications section for variation of oscillator frequency due to v dd for given r ext /c ext values, as well as frequency variation due to operating temperature for given r, c and v dd values. figure 8-5: external rc oscillator mode 8.2.5 internal 4/8 mhz rc oscillator the internal rc oscillator provides a fixed 4/8 mhz (nominal) system clock at v dd = 5v and 25c, (see section 14.0 ?electrical characteristics? for information on variation over voltage and temperature). in addition, a calibration instruction is programmed into the last address of memory, which contains the calibra- tion value for the internal rc oscillator. this location is always non-code protected, regardless of the code- protect settings. this value is programmed as a movlw xx instruction where xx is the calibration value, and is placed at the reset vector. this will load the w register with the calibration value upon reset and the pc will then roll over to the users program at address 0x000. the user then has the option of writing the value to the osccal register (05h) or ignoring it. osccal, when written to with the calibration value, will ?trim? the internal oscillator to remove process variation from the oscillator frequency. for the pic16f526 device, only bits 7:1 of osccal are used for calibration. see register 4-3 for more information. v dd r ext c ext v ss osc1 internal clock n f osc /4 osc2/clkout pic16f526 note: erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. note: the bit 0 of the osccal register is unimplemented and should be written as ? 0 ? when modifying osccal for compatibility with future devices. pic16f526 ds41326e-page 48 ? 2010 microchip technology inc. 8.3 reset the device differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt time-out reset during normal operation ? wdt time-out reset during sleep ? wake-up from sleep on pin change some registers are not reset in any way, they are unknown on por and unchanged in any other reset. most other registers are reset to ?reset state? on power-on reset (por), mclr , wdt or wake-up on pin change reset during normal operation. they are not affected by a wdt reset during sleep or mclr reset during sleep, since these resets are viewed as resumption of normal operation. the exceptions to this are to , pd and rbwuf bits. they are set or cleared differently in different reset situations. these bits are used in software to determine the nature of reset. see table 8-3 for a full description of reset states of all registers. table 8-3: reset conditions for registers register address power-on reset mclr reset, wdt time-out, wake-up on pin change w ? qqqq qqq 0 (1) qqqq qqq0 (1) indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pcl 02h 1111 1111 1111 1111 status 03h 0001 1xxx qq0q quuu (2) fsr 04h 100x xxxx 1uuu uuuu osccal 05h 1111 111- uuuu uuu- portb 06h --xx xxxx --uu uuuu portc 07h --xx xxxx --uu uuuu cmicon0 08h q111 1111 quuu uuuu adcon0 09h 1111 1100 1111 1100 adres 0ah xxxx xxxx uuuu uuuu cm2con0 0bh q111 1111 quuu uuuu vrcon 0ch 001-1111 uuu-uuuu option ? 1111 1111 1111 1111 trisb ? --11 1111 --11 1111 trisc ? --11 1111 --11 1111 eecon 21h/61h ---0 x000 ---0 q000 eedata 25h/65h xxxx xxxx uuuu uuuu eeadr 26h/66h --xx xxxx --uu uuuu legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?, q = value depends on condition. note 1: bits <7:1> of w register contain oscillator calibration values due to movlw xx instruction at top of memory. 2: see table 8-4 for reset value for specific conditions. ? 2010 microchip technology inc. ds41326e-page 49 pic16f526 table 8-4: reset condition for special registers status addr: 03h power-on reset 0001 1xxx mclr reset during normal operation 000u uuuu mclr reset during sleep 0001 0uuu wdt reset during sleep 0000 0uuu wdt reset normal operation 0000 uuuu wake-up from sleep on pin change 1001 0uuu wake-up from sleep on comparator change 0101 0uuu legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?. pic16f526 ds41326e-page 50 ? 2010 microchip technology inc. 8.3.1 mclr enable this configuration bit, when unprogrammed (left in the ? 1 ? state), enables the external mclr function. when programmed, the mclr function is tied to the internal v dd and the pin is assigned to be a i/o. see figure 8-6. figure 8-6: mclr select 8.4 power-on reset (por) the pic16f526 device incorporates an on-chip power- on reset (por) circuitry, which provides an internal chip reset for most power-up situations. the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper oper- ation. to take advantage of the internal por, program the rb3/mclr /v pp pin as mclr and tie through a resistor to v dd , or program the pin as rb3. an internal weak pull-up resistor is implemented using a transistor (refer to table 14-5 for the pull-up resistor ranges). this will eliminate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is specified. see section 14.0 ?electrical char- acteristics? for details. when the device starts normal operation (exit the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating parameters are met. a simplified block diagram of the on-chip power-on reset circuit is shown in figure 8-7. the power-on reset circuit and the device reset timer (see section 8.5 ?device reset timer (drt)? ) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, which is typically 18 ms or 1 ms, it will reset the reset latch and thus end the on-chip reset signal. a power-up example where mclr is held low is shown in figure 8-8. v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 8-9, the on-chip power-on reset feature is being used (mclr and v dd are tied together or the pin is programmed to be rb3. the v dd is stable before the start-up timer times out and there is no problem in get- ting a proper reset. however, figure 8-10 depicts a problem situation where v dd rises too slowly. the time between when the drt senses that mclr is high and when mclr and v dd actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip may not function correctly. for such situations, we recommend that external rc circuits be used to achieve longer por delay times (figure 8-9). for additional information, refer to application notes an522 ?power-up considerations? (ds00522) and an607 ?power-up trouble shooting? (ds00607). rb3/mclr /v pp mclre internal mclr r bwu note: when the device starts normal operation (exit the reset condition), device operat- ing parameters (voltage, frequency, tem- perature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. ? 2010 microchip technology inc. ds41326e-page 51 pic16f526 figure 8-7: simplified block di agram of on-chip reset circuit figure 8-8: time-out sequ ence on power-up (mclr pulled low) figure 8-9: time-out sequ ence on power-up (mclr tied to v dd ): fast v dd rise time sq r q v dd rb3/mclr /v pp power-up detect por (power-on reset) wdt reset chip reset mclre wake-up on pin change reset start-up timer (10 ms, 1.125 ms wdt time-out pin change sleep mclr reset or 18 ms) comparator change wake-up on comparator change v dd mclr internal por drt time-out internal reset tdrt v dd mclr internal por drt time-out internal reset tdrt pic16f526 ds41326e-page 52 ? 2010 microchip technology inc. figure 8-10: time-out sequ ence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset tdrt v1 note: when v dd rises slowly, the t drt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 ? v dd min. ? 2010 microchip technology inc. ds41326e-page 53 pic16f526 8.5 device reset timer (drt) on the pic16f526 device, the drt runs any time the device is powered up. drt runs from reset and varies based on oscillator selection and reset type (see table 8-5). the drt operates on an internal rc oscillator. the processor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd min. and for the oscillator to stabilize. oscillator circuits based on crystals or ceramic resona- tors require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the device in a reset condition after mclr has reached a logic high (v ih mclr ) level. programming rb3/mclr /v pp as mclr and using an external rc network connected to the mclr input is not required in most cases. this allows savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the rb3/ mclr /v pp pin as a general purpose input. the device reset time delays will vary from chip-to- chip due to v dd , temperature and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out from sleep. this is particularly important for applications using the wdt to wake from sleep mode automatically. reset sources are por, mclr , wdt time-out and wake-up on pin or comparator change. see section 8.9.2 ?wake-up from sleep?, notes 1, 2 and 3 . 8.6 watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator, which does not require any external components. this rc oscillator is separate from the external rc oscillator of the rb5/osc1/clkin pin and the internal 4/8 mhz oscillator. this means that the wdt will run even if the main processor clock has been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset, generates a device reset. the to bit of the status register will be cleared upon a watchdog timer reset. the wdt can be permanently disabled by programming the configuration wdte as a ? 0 ? (see section 8.1 ?configuration bits? ). refer to the pic16f526 programming specifications to determine how to access the configuration word. table 8-5: typical drt periods 8.6.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writing to the option register. thus, a time-out period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to-part process variations (see dc specs). under worst-case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt time-out occurs. 8.6.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. oscillator configuration por reset subsequent resets hs, xt, lp 18 ms 18 ms ec 1.125 ms 10 ? s intosc, extrc 1.125 ms 10 ? s pic16f526 ds41326e-page 54 ? 2010 microchip technology inc. figure 8-11: watchdo g timer block diagram table 8-6: summary of registers as sociated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a option rbwu rbpu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: shaded boxes = not used by watchdog timer. (figure 7-1) postscaler note 1: psa, ps<2:0> are bits in the option register. wdt time-out watchdog time from timer0 clock source wdt enable configuration bit psa postscaler 8-to-1 mux ps<2:0> (1) (figure 7-4) to timer0 0 1 m u x 1 0 psa (1) mux ? 2010 microchip technology inc. ds41326e-page 55 pic16f526 8.7 time-out sequence, power-down and wake-up from sleep status bits (to , pd , rbwuf, cwuf) the to , pd and rbwuf bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr or watchdog timer (wdt) reset. table 8-7: to /pd /rbwuf/cwuf status after reset 8.8 reset on brown-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic16f526 devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in figure 8-12 and figure 8-13. figure 8-12: brown-out protection circuit 1 figure 8-13: brown-out protection circuit 2 figure 8-14: brown-out protection circuit 3 cwuf rbwuf to pd reset caused by 0000 wdt wake-up from sleep 000u wdt time-out (not from sleep) 0010 mclr wake-up from sleep 0011 power-up 00uu mclr not during sleep 0110 wake-up from sleep on pin change 1010 wake up from sleep on comparator change legend: u = unchanged note 1: the to , pd and rbwuf bits maintain their status ( u ) until a reset occurs. a low-pulse on the mclr input does not change the to , pd and rbwuf status bits. note 1: this circuit will activate reset when v dd goes below vz + 0.7v (where vz = zener voltage). 2: pin must be configured as mclr . 33k 10k 40k (1) v dd mclr (2) pic12f510 v dd q1 pic16f506 note 1: this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: 2: pin must be configured as mclr . v dd ? r1 r1 + r2 = 0.7v r2 40k (1) v dd mclr (2) pic12f510 r1 q1 v dd pic16f506 note: this brown-out protection circuit employs microchip technology?s mcp809 microcon- troller supervisor. there are 7 different trip point selections to accommodate 5v to 3v systems. mclr pic12f510 v dd v dd v ss rst mcp809 v dd bypass capacitor pic16f506 pic16f526 ds41326e-page 56 ? 2010 microchip technology inc. 8.9 power-down mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 8.9.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit of the status register is set, the pd bit of the status register is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was exe- cuted (driving high, driving low or high-impedance). for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the rb3/ mclr /v pp pin must be at a logic high level if mclr is enabled. 8.9.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. an external reset input on rb3/mclr /v pp pin, when configured as mclr . 2. a watchdog timer time-out reset (if wdt was enabled). 3. a change on input pin rb0, rb1, rb3 or rb4 when wake-up on change is enabled. 4. a change in one of the comparator output bits, c1out or c2out (if comparator wake-up is enabled). these events cause a device reset. the to , pd and cwuf/rbwuf bits can be used to determine the cause of device reset. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the cwuf bit indicates a change in a com- parator output state while the device was in sleep. the rbwuf bit indicates a change in state while in sleep at pins rb0, rb1, rb3 or rb4 (since the last file or bit operation on rb port). the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. note: a reset generated by a wdt time-out does not drive the mclr pin low. note: caution: right before entering sleep, read the input pins. when in sleep, wake-up occurs when the values at the pins change from the state they were in at the last reading. if a wake-up on change occurs and the pins are not read before re-entering sleep, a wake-up will occur immediately even if no pins change while in sleep mode. note: caution: right before entering sleep, read the comparator configuration register(s) cm1con0 and cm2con0. when in sleep, wake-up occurs when the comparator output bit c1out and c2out change from the state they were in at the last reading. if a wake-up on comparator change occurs and the pins are not read before re-entering sleep, a wake-up will occur immediately, even if no pins change while in sleep mode. ? 2010 microchip technology inc. ds41326e-page 57 pic16f526 8.10 program verification/code protection if the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. the first 64 locations and the last location (osccal) can be read, regardless of the code protection bit setting. the last memory location can be read regardless of the code protection bit setting on the pic16f526 device. 8.11 id locations four memory locations are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are readable and writable during program/verify. use only the lower 4 bits of the id locations and always program the upper 8 bits as ? 0 ?s. 8.12 in-circuit serial programming? the pic16f526 microcontroller can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware, or a custom firmware, to be programmed. the devices are placed into a program/verify mode by holding the rb1 and rb0 pins low while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). rb1 becomes the programming clock and b0 becomes the programming data. both rb1 and rb0 are schmitt trigger inputs in this mode. after reset, a 6-bit command is then supplied to the device. depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic16f526 programming specifications. a typical in-circuit serial programming connection is shown in figure 8-15. figure 8-15: typical in-circuit serial programming connection external connector signals to n o r m a l connections to n o r m a l connections v dd v ss mclr /v pp rb1 rb0 +5v 0v v pp clk data v dd pic16f526 pic16f526 ds41326e-page 58 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds41326e-page 59 pic16f526 9.0 analog-to-digital (a/d) converter the a/d converter allows conversion of an analog signal into an 8-bit digital signal. 9.1 clock divisors the adc has 4 clock source settings adcs<1:0>. there are 3 divisor values 16, 8 and 4. the fourth setting is intosc with a divisor of 4. these settings will allow a proper conversion when using an external oscillator at speeds from 20 mhz to 350 khz. using an external oscillator at a frequency below 350 khz requires the adc oscillator setting to be intosc/4 (adcs<1:0> = 11 ) for valid adc results. the adc requires 13 t ad periods to complete a conversion. the divisor values do not affect the number of t ad periods required to perform a conversion. the divisor values determine the length of the t ad period. when the adcs<1:0> bits are changed while an adc conversion is in process, the new adc clock source will not be selected until the next conversion is started. this clock source selection will be lost when the device enters sleep. 9.1.1 voltage reference there is no external voltage reference for the adc. the adc reference voltage will always be v dd . 9.1.2 analog mode selection the ans<1:0> bits are used to configure pins for analog input. upon any reset, ans<1:0> defaults to 11. this configures pins an0, an1 and an2 as analog inputs. the comparator output, c1out, will override an2 as an input if the comparator output is enabled. pins configured as analog inputs are not available for digital output. users should not change the ans bits while a conversion is in process. ans bits are active regardless of the condition of adon. 9.1.3 adc channel selection the chs bits are used to select the analog channel to be sampled by the adc. the chs<1:0> bits can be changed at any time without adversely effecting a con- version. to acquire an analog signal the chs<1:0> selection must match one of the pin(s) selected by the ans<1:0> bits. when the adc is on (adon = 1 ) and a channel is selected that is also being used by the comparator, then both the comparator and the adc will see the analog voltage on the pin. when the chs<1:0> bits are changed during an adc conversion, the new channel will not be selected until the current conversion is completed. this allows the current conversion to complete with valid results. all channel selection information will be lost when the device enters sleep. table 9-1: channel select (adcs) bits after an event 9.1.4 the go/done bit the go/done bit is used to determine the status of a conversion, to start a conversion and to manually halt a conversion in process. setting the go/done bit starts a conversion. when the conversion is complete, the adc module clears the go/done bit. a conversion can be terminated by manually clearing the go/done bit while a conversion is in process. manual termination of a conversion may result in a partially converted result in adres. the go/done bit is cleared when the device enters sleep, stopping the current conversion. the adc does not have a dedicated oscillator, it runs off of the instruction clock. therefore, no conversion can occur in sleep. the go/done bit cannot be set when adon is clear. note: the adc clock is derived from the instruc- tion clock. the adcs divisors are then applied to create the adc clock note: it is the users responsibility to ensure that use of the adc and comparator simulta- neously on the same pin, does not adversely affect the signal being monitored or adversely effect device operation. event adcs<1:0> mclr 11 conversion completed cs<1:0> conversion terminated cs<1:0> power-on 11 wake from sleep 11 pic16f526 ds41326e-page 60 ? 2010 microchip technology inc. 9.1.5 sleep this adc does not have a dedicated adc clock, and therefore, no conversion in sleep is possible. if a conversion is underway and a sleep command is executed, the go/done and adon bit will be cleared. this will stop any conversion in process and power- down the adc module to conserve power. due to the nature of the conversion process, the adres may con- tain a partial conversion. at least 1 bit must have been converted prior to sleep to have partial conversion data in adres. the adcs and chs bits are reset to their default condition; ans<1:0> = 11 and chs<1:0> = 11 . ? for accurate conversions, t ad must meet the following: ?500ns < t ad < 50 ? s ?t ad = 1 /(f osc /divisor) shaded areas indicate t ad out of range for accurate conversions. if analog input is desired at these frequencies, use intosc/8 for the adc clock source. table 9-2: t ad for adcs settings with various oscillators table 9-3: effects of sleep on adcon0 source adcs <1:0> divisor 20 mhz 16 mhz 8mhz 4mhz 1mhz 500 khz 350 khz 200 khz 100 khz 32 khz intosc 11 4 ? ?.5 ? s1 ? s ? ? ? ? ? ? fosc 10 4 .2 ? s .25 ? s.5 ? s1 ? s4 ? s8 ? s11 ? s20 ? s40 ? s 125 ? s fosc 01 8 .4 ? s.5 ? s1 ? s2 ? s8 ? s16 ? s23 ? s40 ? s 80 ? s 250 ? s fosc 00 16 .8 ? s1 ? s2 ? s4 ? s16 ? s32 ? s46 ? s 80 ? s 160 ? s 500 ? s ans1 ans0 adcs1 adcs0 chs1 chs0 go/done adon entering sleep unchanged unchanged 111100 wake or reset 11111100 ? 2010 microchip technology inc. ds41326e-page 61 pic16f526 9.1.6 analog conversion result register the adres register contains the results of the last conversion. these results are present during the sampling period of the next analog conversion process. after the sampling period is over, adres is cleared (= 0 ). a ?leading one? is then right shifted into the adres to serve as an internal conversion complete bit. as each bit weight, starting with the msb, is converted, the leading one is shifted right and the converted bit is stuffed into adres. after a total of 9 right shifts of the ?leading one? have taken place, the conversion is complete; the ?leading one? has been shifted out and the go/done bit is cleared. if the go/done bit is cleared in software during a conversion, the conversion stops. the data in adres is the partial conversion result. this data is valid for the bit weights that have been converted. the position of the ?leading one? determines the number of bits that have been converted. the bits that were not converted before the go/done was cleared are unrecoverable. register 9-1: adcon0: a/d control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 ans1 ans0 adcs1 adcs0 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 ans<1:0>: adc analog input pin select bits (1), (2), (5) 00 = no pins configured for analog input 01 = an2 configured as an analog input 10 = an2 and an0 configured as analog inputs 11 = an2, an1 and an0 configured as analog inputs bit 5-4 adcs<1:0>: adc conversion clock select bits 00 = f osc /16 01 = f osc /8 10 = f osc /4 11 = intosc/4 bit 3-2 chs<1:0>: adc channel select bits (3, 5) 00 = channel an0 01 = channel an1 10 = channel an2 11 = 0.6v absolute voltage reference bit 1 go/done : adc conversion status bit (4) 1 = adc conversion in progress. setting th is bit starts an adc conversion cycle. this bit is automatically cleared by hardware when the adc is done converting. 0 = adc conversion completed/not in progress. manually clear ing this bit while a conversion is in process termi- nates the current conversion. bit 0 adon: adc enable bit 1 = adc module is operating 0 = adc module is shut-off and consumes no power note 1: when the ans bits are set, the channels selected will automatic ally be forced into analog mode, regardless of the pin function previously defined. the only exc eption to this is the comparator, wher e the analog input to the comparator and the adc will be active at the same time. it is the users re sponsibility to ensure that the adc loading on the comparator input does not affect their application. 2: the ans<1:0> bits are active regardless of the condition of adon. 3: chs<1:0> bits default to 11 after any reset. 4: if the adon bit is clear, the go/done bit cannot be set. 5: c1out, when enabled, overrides an2. pic16f526 ds41326e-page 62 ? 2010 microchip technology inc. example 9-1: performing an analog-to-digital conversion example 9-2: channel selection change during conversion register 9-2: adres: a/d conversion results register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x adres7 adres6 adres5 adres4 adres3 adres2 adres1 adres0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown ;sample code operates out of bank0 movlw 0xf1 ;configure a/d movwf adcon0 bsf adcon0, 1 ;start conversion loop0 btfsc adcon0, 1;wait for ?done? goto loop0 movf adres, w ;read result movwf result0 ;save result bsf adcon0, 2 ;setup for read of ;channel 1 bsf adcon0, 1 ;start conversion loop1 btfsc adcon0, 1;wait for ?done? goto loop1 movf adres, w ;read result movwf result1 ;save result bsf adcon0, 3 ;setup for read of bcf adcon0, 2 ;channel 2 bsf adcon0, 1 ;start conversion loop2 btfsc adcon0, 1;wait for ?done? goto loop2 movf adres, w ;read result movwf result2 ;save result movlw 0xf1 ;configure a/d movwf adcon0 bsf adcon0, 1 ;start conversion bsf adcon0, 2 ;setup for read of ;channel 1 loop0 btfsc adcon0, 1;wait for ?done? goto loop0 movf adres, w ;read result movwf result0 ;save result bsf adcon0, 1 ;start conversion bsf adcon0, 3 ;setup for read of bcf adcon0, 2 ;channel 2 loop1 btfsc adcon0, 1;wait for ?done? goto loop1 movf adres, w ;read result movwf result1 ;save result bsf adcon0, 1 ;start conversion loop2 btfsc adcon0, 1;wait for ?done? goto loop2 movf adres, w ;read result movwf result2 ;save result clrf adcon0 ;optional: returns ;pins to digital mode and turns off ;the adc module ? 2010 microchip technology inc. ds41326e-page 63 pic16f526 10.0 comparator(s) this device contains two comparators and a comparator voltage reference. register 10-1: cm1con0: comparator c1 control register r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c1out: comparator output bit 1 = v in + > v in - 0 = v in + < v in - bit 6 c1outen : comparator output enable bit (1), (2) 1 = output of comparator is not placed on the c1out pin 0 = output of comparator is placed in the c1out pin bit 5 c1pol: comparator output polarity bit (2) 1 = output of comparator is not inverted 0 = output of comparator is inverted bit 4 c1t0cs : comparator tmr0 clock source bit (2) 1 = tmr0 clock source selected by t0cs control bit 0 = comparator output used as tmr0 clock source bit 3 c1on: comparator enable bit 1 = comparator is on 0 = comparator is off bit 2 c1nref: comparator negative reference select bit (2) 1 = c1in- pin 0 = 0.6v v ref bit 1 c1pref: comparator positive reference select bit (2) 1 = c1in+ pin 0 = c1in- pin bit 0 c1wu : comparator wake-up on change enable bit (2) 1 = wake-up on comparator change is disabled 0 = wake-up on comparator change is enabled note 1: overrides t0cs bit for tris control of rb2. 2: when comparator is turned on, these control bits assert themselves. otherwise, the other registers have precedence. pic16f526 ds41326e-page 64 ? 2010 microchip technology inc. register 10-2: cm2con0: comparator c2 control register r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c2out: comparator output bit 1 = v in + > v in - 0 = v in + < v in - bit 6 c2outen : comparator output enable bit (1), (2) 1 = output of comparator is not placed on the c2out pin 0 = output of comparator is placed in the c2out pin bit 5 c2pol: comparator output polarity bit (2) 1 = output of comparator not inverted 0 = output of comparator inverted bit 4 c2pref2: comparator positive reference select bit (2) 1 = c1in+ pin 0 = c2in- pin bit 3 c2on: comparator enable bit 1 = comparator is on 0 = comparator is off bit 2 c2nref: comparator negative reference select bit (2) 1 = c2in- pin 0 = cv ref bit 1 c2pref1: comparator positive reference select bit (2) 1 = c2in+ pin 0 = c2pref2 controls analog input selection bit 0 c2wu : comparator wake-up on change enable bit (2) 1 = wake-up on comparator change is disabled 0 = wake-up on comparator change is enabled. note 1: overrides tocs bit for tris control of rc4. 2: when comparator is turned on, these control bits assert themselves. otherwise, the other registers have precedence. ? 2010 microchip technology inc. ds41326e-page 65 pic16f526 figure 10-1: comparat ors block diagram + - c1in+ c1in- v ref (0.6v) c1on c1pol c1t0cs rb2/c1out c1outen c1out (register) t0cki pin t0cki qd s read cm1con0 c1wu c1pref c1nref + - c2in+ c2in- c2on c2pol c2pref1 c2nref cv ref c2pref2 rc4/c2out c2outen c2out (register) qd s cwuf read cm2con0 c2wu 1 0 1 0 1 0 1 0 1 0 1 0 pic16f526 ds41326e-page 66 ? 2010 microchip technology inc. 10.1 comparator operation a single comparator is shown in figure 10-2 along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. the shaded area of the output of the comparator in figure 10-2 represent the uncertainty due to input offsets and response time. see table 14-2 for common mode voltage. figure 10-2: single comparator 10.2 comparator reference an internal reference signal may be used depending on the comparator operating mode. the analog signal that is present at v in - is compared to the signal at v in +, and the digital output of the comparator is adjusted accordingly (figure 10-2). please see section 11.0 ?comparator voltage reference module? for internal reference specifications. 10.3 comparator response time response time is the minimum time after selecting a new reference voltage or input source before the comparator output is to have a valid level. if the comparator inputs are changed, a delay must be used to allow the comparator to settle to its new state. please see table 14-3 for comparator response time specifications. 10.4 comparator output the comparator output is read through the cm1con0 or cm2con0 register. this bit is read-only. the comparator output may also be used externally, see figure 10-1. 10.5 comparator wake-up flag the comparator wake-up flag is set whenever all of the following conditions are met: ?c1wu = 0 (cm1con0<0>) or c2wu = 0 (cm2con0<0>) ? cm1con0 or cm2con0 has been read to latch the last known state of the c1out and c2out bit ( movf cm1con0 , w ) ? device is in sleep ? the output of a comparator has changed state the wake-up flag may be cleared in software or by another device reset. 10.6 comparator operation during sleep when the comparator is enabled it is active. to minimize power consumption while in sleep mode, turn off the comparator before entering sleep. 10.7 effects of reset a power-on reset (por) forces the cm2con0 register to its reset state. this forces the comparator input pins to analog reset mode. device current is minimized when analog inputs are present at reset time. 10.8 analog input connection considerations a simplified circuit for an analog input is shown in figure 10-3. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. ? + v in + v in - result result v in - v in + note: analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. ? 2010 microchip technology inc. ds41326e-page 67 pic16f526 figure 10-3: analog input mode table 10-1: registers associated with comparator module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets status rbwuf cwuf pa0 to pd zdcc 0001 1xxx qq0q quuu cm1con0 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu q111 1111 quuu uuuu cm2con0 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu q111 1111 quuu uuuu tris ? ? i/o control register (portb, portc) --11 1111 --11 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?, q = depends on condition. va r s < 10 k a in c pin 5pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin r ic = interconnect resistance r s = source impedance va = analog voltage pic16f526 ds41326e-page 68 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds41326e-page 69 pic16f526 11.0 comparator voltage reference module the comparator voltage reference module also allows the selection of an internally generated voltage reference for one of the c2 comparator inputs. the vrcon register (register 11-1) controls the voltage reference module shown in figure 11-1. 11.1 configuring the voltage reference the voltage reference can output 32 voltage levels; 16 in a high range and 16 in a low range. equation 11-1 determines the output voltages: equation 11-1: 11.2 voltage reference accuracy/error the full range of v ss to v dd cannot be realized due to construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 11-1) keep cv ref from approaching v ss or v dd . the exception is when the module is disabled by clearing the vren bit of the vrcon register. when disabled, the reference voltage is v ss when vr<3:0> is ? 0000 ? and the vrr bit of the vrcon register is set. this allows the comparator to detect a zero-crossing and not consume the cv ref module current. the voltage reference is v dd derived and, therefore, the cv ref output changes with fluctuations in v dd . the tested absolute accuracy of the comparator voltage reference can be found in section 14.0 ?elec- trical characteristics? . vrr = 1 (low range): cv ref = (vr<3:0>/24) x v dd vrr = 0 (high range): cv ref = (v dd /4) + (vr<3:0> x v dd /32) register 11-1: vrcon: voltag e reference control register r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 vren vroe vrr ?vr3vr2vr1vr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 vren: cv ref enable bit 1 = cv ref is powered on 0 = cv ref is powered down, no current is drawn bit 6 vroe: cv ref output enable bit (1) 1 = cv ref output is enabled 0 = cv ref output is disabled bit 5 vrr: cv ref range selection bit 1 = low range 0 = high range bit 4 unimplemented: read as ? 0 ? bit 3-0 vr<3:0> cv ref value selection bit when v rr = 1 : cv ref = (vr<3:0>/24)*v dd when v rr = 0 : cv ref = v dd /4+(vr<3:0>/32)*v dd note 1: when this bit is set, the tris for the cv ref pin is overridden and the analog voltage is placed on the cv ref pin. pic16f526 ds41326e-page 70 ? 2010 microchip technology inc. figure 11-1: comparator voltage reference block diagram table 11-1: registers associated with comparator voltage reference name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets vrcon vren vroe vrr ? vr3 vr2 vr1 vr0 001- 1111 uuu- uuuu cm1con0 c1out c1outen c1pol c1t0cs c1on c1nref c1pref c1wu q111 1111 quuu uuuu cm2con0 c2out c2outen c2pol c2pref2 c2on c2nref c2pref1 c2wu q111 1111 quuu uuuu legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?, q = value depends on condition. v dd 8r r r vren 16-1 analog mux cv ref to comparator 2 input vr<3:0> v ren vr<3:0> = 0000 vrr vrr 8r rr 16 stages rc2/cv ref v roe ? 2010 microchip technology inc. ds41326e-page 71 pic16f526 12.0 instruction set summary the pic16 instruction set is highly orthogonal and is comprised of three basic categories. ? byte-oriented operations ? bit-oriented operations ? literal and control operations each pic16 instruction is a 12-bit word divided into an opcode , which specifies the instruction type, and one or more operands which further specify the operation of the instruction. the formats for each of the categories is presented in figure 12-1, while the various opcode fields are summarized in table 12-1. for byte-oriented instructions, ?f? represents a file register designator and ?d? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator which selects the number of the bit affected by the operation, while ?f? represents the number of the file in which the bit is located. for literal and control operations, ?k? represents an 8 or 9-bit constant or literal value. table 12-1: opcode field descriptions all instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 ? s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 ? s. figure 12-1 shows the three general formats that the instructions can have. all examples in the figure use the following format to represent a hexadecimal number: 0xhhh where ?h? signifies a hexadecimal digit. figure 12-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ) the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in file register ?f?) default is d = 1 label label name tos top-of-stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents ? assigned to < > register bit field ? in the set of italics user defined term (font is courier) byte-oriented file register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit file register address bit-oriented file register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit file register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations ? goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value pic16f526 ds41326e-page 72 ? 2010 microchip technology inc. table 12-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c, dc, z z z z z z none z none z z none none c c c, dc, z none z 1, 2, 4 2, 4 4 2, 4 2, 4 2, 4 2, 4 2, 4 2, 4 1, 4 2, 4 2, 4 1, 2, 4 2, 4 2, 4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2, 4 2, 4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k ? k k k ? k ? f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none to , pd none z none none none to , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a ? 0 ? by any instruction that writes to the pc except for goto . see section 4.6 ?program counter? . 2: when an i/o register is modified as a function of itself (e.g. movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 3: the instruction tris f , where f = 6, causes the contents of the w register to be written to the tri-state latches of portb. a ? 1 ? forces the pin to a high-impedance state and disables the output buffers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared (if assigned to tmr0). ? 2010 microchip technology inc. ds41326e-page 73 pic16f526 addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 31 d ??? 0 ? 1 ? operation: (w) + (f) ? (dest) status affected: c, dc, z description: add the contents of the w register and register ?f?. if ?d? is? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w).and. (k) ? (w) status affected: z description: the contents of the w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 31 d ?? [0,1] operation: (w) .and. (f) ? (dest) status affected: z description: the contents of the w register are and?ed with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 31 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 31 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 31 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruc- tion fetched during the current instruction execution is discarded, and a nop is executed instead, making this a two-cycle instruction. pic16f526 ds41326e-page 74 ? 2010 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 31 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruc- tion fetched during the current instruction execution, is discarded and a nop is executed instead, making this a two-cycle instruction. call subroutine call syntax: [ label ] call k operands: 0 ? k ? 255 operation: (pc) + 1 ? top-of-stack; k ? pc<7:0>; (status<6:5>) ? pc<10:9>; 0 ? pc<8> status affected: none description: subroutine call. first, return address (pc + 1) is pushed onto the stack. the eight-bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from status<6:5>, pc<8> is cleared. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 31 operation: 00h ? (f); 1 ? z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w); 1 ? z status affected: z description: the w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt; 0 ? wdt prescaler (if assigned); 1 ? to; 1 ? pd status affected: to , pd description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f ) ? (dest) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. ? 2010 microchip technology inc. ds41326e-page 75 pic16f526 decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) ? 1 ? (dest) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) ? 1 ? d; skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, the next instruc- tion, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 511 operation: k ? pc<8:0>; status<6:5> ? pc<10:9> status affected: none description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two- cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) + 1 ? (dest) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) + 1 ? (dest), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, then the next instruction, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. (k) ? (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. pic16f526 ds41326e-page 76 ? 2010 microchip technology inc. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (w).or. (f) ? (dest) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f) ? (dest) status affected: z description: the contents of register ?f? are moved to destination ?d?. if ?d? is ? 0 ?, destination is the w register. if ?d? is ? 1 ?, the destination is file register ?f?. ?d? = 1 is useful as a test of a file register, since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the eight-bit literal ?k? is loaded into the w register. the ?don?t cares? will assembled as ? 0 ?s. movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 31 operation: (w) ? (f) status affected: none description: move data from the w register to register ?f?. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none description: the content of the w register is loaded into the option register. ? 2010 microchip technology inc. ds41326e-page 77 pic16f526 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 31 d ? [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 31 d ? [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. c register ?f? c register ?f? sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt; 0 ? wdt prescaler; 1 ? to ; 0 ? pd status affected: to , pd, rbwuf description: time-out status bit (to ) is set. the power-down status bit (pd ) is cleared. rbwuf is unaffected. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 8.9 ?power-down mode (sleep)? on sleep for more details. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 31 d ? [0,1] operation: (f) ? (w) ??? dest) status affected: c, dc, z description: subtract (2?s complement method) the w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (f<3:0>) ? (dest<7:4>); (f<7:4>) ? (dest<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w register. if ?d? is ? 1 ?, the result is placed in register ?f?. pic16f526 ds41326e-page 78 ? 2010 microchip technology inc. tris load tris register syntax: [ label ] tris f operands: f = 6 operation: (w) ? tris register f status affected: none description: tris register ?f? (f = 6 or 7) is loaded with the contents of the w register xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 31 d ? [0,1] operation: (w) .xor. (f) ??? dest) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. ? 2010 microchip technology inc. ds41326e-page 79 pic16f526 13.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 13.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. pic16f526 ds41326e-page 80 ? 2010 microchip technology inc. 13.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 13.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 13.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 13.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 13.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility ? 2010 microchip technology inc. ds41326e-page 81 pic16f526 13.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 13.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables. 13.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 13.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. pic16f526 ds41326e-page 82 ? 2010 microchip technology inc. 13.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break- point, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 13.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 13.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ? 2010 microchip technology inc. ds41326e-page 83 pic16f526 14.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ......... -40c to +125c storage temperature ............................................................................................................ ................ -65c to +150c voltage on v dd with respect to v ss ............................................................................................................... 0 to +6.5v voltage on mclr with respect to v ss ..........................................................................................................0 to +13.5v voltage on all other pins with respect to v ss ............................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... ... 700 mw max. current out of v ss pin ........................................................................................................................... ..... 200 ma max. current into v dd pin ........................................................................................................................... ........ 150 ma input clamp current, i ik (v i < 0 or v i > v dd ) ??????????????????????????????????????????????????????????????? ????????????????????????????????????????????????????? 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ??????????????????????????????????????????????????????????????? ????????????????????????????????????????????? 20 ma max. output current sunk by any i/o pin ........................................................................................ ...................... 25 ma max. output current sourced by any i/o pin ..................................................................................... .................... 25 ma max. output current sourced by i/o port ....................................................................................... ....................... 75 ma max. output current sunk by i/o port .......................................................................................... ......................... 75 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? ? i oh } + ? {(v dd ? v oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. pic16f526 ds41326e-page 84 ? 2010 microchip technology inc. figure 14-1: pic16f526 volt age-frequency graph, -40 ? c ? t a ? +125 ? c figure 14-2: maximum oscillator frequency table 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 intosc or ec mode only 0 200 khz 4 mhz 20 mhz frequency hs intosc xt lp oscillator mode ec xtrc 8 mhz ? 2010 microchip technology inc. ds41326e-page 85 pic16f526 14.1 dc characteristics: pic16f526 (industrial) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial) param no. sym. characteristic min. typ. (1) max. units conditions d001 v dd supply voltage 2.0 5.5 v see figure 14-1 d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?vss? vsee section 8.4 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 8.4 ?power-on reset (por)? for details d005 i ddp supply current during prog/ erase ? 250* ? ? a d010 i dd supply current (3, 4, 6) ? ? 175 400 250 700 ? a ? a f osc = 4 mhz, v dd = 2.0v f osc = 4 mhz, v dd = 5.0v ? ? 250 0.75 400 1.2 ? a ma f osc = 8 mhz, v dd = 2.0v f osc = 8 mhz, v dd = 5.0v ?1.42.2maf osc = 20 mhz, v dd = 5.0v ? ? 11 38 22 55 ? a ? a f osc = 32 khz, v dd = 2.0v f osc = 32 khz, v dd = 5.0v d020 i pd power-down current (5) ? ? 0.1 0.35 1.2 2.2 ? a ? a v dd = 2.0v v dd = 5.0v d022 i wdt wdt current (5) ? ? 1.0 7.0 3.0 16.0 ? a ? a v dd = 2.0v v dd = 5.0v d023 i cmp comparator current (5) ? ? 15 60 26 76 ? a ? a v dd = 2.0v (per comparator) v dd = 5.0v (per comparator) d022 i cvref c vref current (5) ? ? 30 75 75 135 ? a ? a v dd = 2.0v (high range) v dd = 5.0v (high range) d023 i fvr internal 0.6v fixed voltage reference current (5) ? ? 100 175 120 205 ? a ? a v dd = 2.0v (reference and 1 comparator enabled) v dd = 5.0v (reference and 1 comparator enabled) d024 ? i ad * a/d conversion current ? 120 150 ? a2.0v ? 200 250 ? a5.0v * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. 5: for standby current measurements, the conditions are the same as i dd , except that the device is in sleep mode. if a module current is listed, the current is for that specific module enabled and the device in sleep. 6: for extrc mode, does not include current through r ext . the current through the resistor can be estimated by the formula: i = v dd /2r ext (ma) with r ext in k ? . pic16f526 ds41326e-page 86 ? 2010 microchip technology inc. 14.2 dc characteristics: pic16f526 (extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +125 ? c (extended) param no. sym. characteristic min. typ. (1) max. units conditions d001 v dd supply voltage 2.0 5.5 v see figure 14-1 d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?vss? vsee section 8.4 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 8.4 ?power-on reset (por)? for details d005 i ddp supply current during prog/ erase ? 250* ? ? a d010 i dd supply current (3,4,6) ? ? 175 400 250 700 ? a ? a f osc = 4 mhz, v dd = 2.0v f osc = 4 mhz, v dd = 5.0v ? ? 250 0.75 400 1.2 ? a ma f osc = 8 mhz, v dd = 2.0v f osc = 8 mhz, v dd = 5.0v ?1.42.2maf osc = 20 mhz, v dd = 5.0v ? ? 11 38 26 110 ? a ? a f osc = 32 khz, v dd = 2.0v f osc = 32 khz, v dd = 5.0v d020 i pd power-down current (5) ? ? 0.1 0.35 9.0 15.0 ? a ? a v dd = 2.0v v dd = 5.0v d022 i wdt wdt current (5) ? ? 1.0 7.0 18 22 ? a ? a v dd = 2.0v v dd = 5.0v d023 icmp comparator current (5) ? ? 15 60 26 76 ? a ? a v dd = 2.0v (per comparator) v dd = 5.0v (per comparator) d022 ic vref cv ref current (5) ? ? 30 75 75 135 ? a ? a v dd = 2.0v (high range) v dd = 5.0v (high range) d023 i fvr internal 0.6v fixed voltage reference current (5) ? ? 100 175 130 220 ? a ? a v dd = 2.0v (reference and 1 comparator enabled) v dd = 5.0v (reference and 1 comparator enabled) d024 ? i ad * a/d conversion current ? 120 150 ? a2.0v ? 200 250 ? a5.0v * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characterization results at 25 ? c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. 5: for standby current measurements, the conditions are the same as i dd , except that the device is in sleep mode. if a module current is listed, the current is for that specific module enabled and the device in sleep. 6: for extrc mode, does not include current through r ext . the current through the resistor can be estimated by the formula: i = v dd /2r ext (ma) with r ext in k ? . ? 2010 microchip technology inc. ds41326e-page 87 pic16f526 table 14-1: dc characteristics: pic16f526 (industrial, extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40c ? t a ? +85c (industrial) -40c ? t a ? +125c (extended) operating voltage v dd range as described in dc spec. param no. sym. characteristic min. typ.? max. units conditions v il input low voltage i/o ports d030 with ttl buffer vss ? 0.8 v for all 4.5 ? v dd ?? 5.5v d030a vss ? 0.15 v dd v otherwise d031 with schmitt trigger buffer vss ? 0.15 v dd v d032 mclr , t0cki vss ? 0.15 v dd v d033 osc1 (extrc mode), ec (1) vss ? 0.15 v dd v d033 osc1 (hs mode) vss ? 0.3 v dd v d033 osc1 (xt and lp modes) vss ? 0.3 v v ih input high voltage i/o ports ? d040 with ttl buffer 2.0 ? v dd v4.5 ? v dd ?? 5.5v d040a 0.25v dd + 0.8v ?v dd v otherwise d041 with schmitt trigger buffer 0.85v dd ?v dd v for entire v dd range d042 mclr, t0cki 0.85v dd ?v dd v d042a osc1 (extrc mode), ec (1) 0.85v dd ?v dd v d042a osc1 (hs mode) 0.7v dd ?v dd v d043 osc1 (xt and lp modes) 1.6 ? v dd v d070 i pur portb weak pull-up current (4) 50 250 400 ? av dd = 5v, v pin = v ss i il input leakage current (2,5) d060 i/o ports ? ? 1 ? avss ?? v pin ?? v dd , pin at high-impedance d061 rb3/mclr (3) ?0.75 ? avss ?? v pin ?? v dd d063 osc1 ? ? 5 ? avss ?? v pin ?? v dd , xt, hs and lp osc configuration v ol output low voltage d080 i/o ports/clkout ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, ?40 ? c to +85 ? c d080a ? ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, ?40 ? c to +125 ? c v oh output high voltage d090 i/o ports/clkout v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, ?40 ? c to +85 ? c d090a v dd ? 0.7 ? ? v i oh = -2.5 ma, v dd = 4.5v, ?40 ? c to +125 ? c capacitive loading specs on output pins d100 cosc2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 cio all i/o pins and osc2 ? ? 50 pf flash data memory d120 e d byte endurance 100k 1m ? e/w ?40 ? c ? t a ? +85 ? c d120a e d byte endurance 10k 100k ? e/w +85 ? c ? t a ? +125 ? c d121 v drw v dd for read/write v min ?5.5 v ? data in ?typ? column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16f526 be driven with external clock in rc mode. 2: negative current is defined as coming out of the pin. 3: this spec. applies to rb3/mclr configured as rb3 with pull-up disabled. 4: this spec. applies to all weak pull-up devic es, including the weak pull-up found on rb3/mclr . the current value listed will be the same whether or not the pin is configured as rb3 with pull-up enabled or as mclr . 5: the leakage current on the nmclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage may be measured at different input voltages. pic16f526 ds41326e-page 88 ? 2010 microchip technology inc. table 14-2: comparator specifications. table 14-3: comparator voltage reference (v ref ) specifications comparator specifications standard operating conditions (unless otherwise stated) operating temperature -40c to 125c characteristics sym. min. typ. max. units comments internal voltage reference v ivrf 0.50 0.60 0.70 v input offset voltage v os ? ? 5.0 ? 10 mv input common mode voltage* v cm 0?v dd ? 1.5 v cmrr* c mrr 55 ? ? db response time (1)* t rt ? 150 400 ns comparator mode change to output valid* t mc 2 cov ?? 10 ? s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2 while the other input transitions from v ss to v dd ? 1.5v. sym. characteristics min. typ. max. units comments cv res resolution ? ? v dd /24* v dd /32 ? ? lsb lsb low range (v rr = 1 ) high range (v rr = 0 ) absolute accuracy (2) ? ? ? ? 1/2* 1/2* lsb lsb low range (v rr = 1 ) high range (v rr = 0 ) unit resistor value (r) ? ? 2k* ? ? settling time (1) ??10* ? s * these parameters are characterized but not tested. note 1: settling time measured while v rr = 1 and vr<3:0> transitions from 0000 to 1111 . 2: do not use reference externally when v dd < 2.7v. under this condition, reference should only be used with comparator voltage common mode observed. ? 2010 microchip technology inc. ds41326e-page 89 pic16f526 table 14-4: a/d converter characteristics : table 14-5: pull-up resistor ranges a/d converter specifications standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ.? max. units conditions a01 n r resolution ? ? 8 bit a03 e inl integral error ? ? ? 1.5 lsb v dd = 5.0v a04 e dnl differential error ? ? -1< e dnl ? 1.7 lsb no missing codes to 8 bits v dd = 5.0v a06 e off offset error ? ? ? 1.5 lsb v dd = 5.0v a07 e gn gain error -0.7 ? +2.2 lsb v dd = 5.0v a10 ? monotonicity ? guaranteed (1) ??v ss ? v ain ? v dd a25 v ain analog input voltage v ss ?v dd v a30 z ain recommended impedance of analog voltage source ?? 10k ? * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. v dd (volts) temperature ( ? c) min. typ. max. units rb0/rb1/rb4 2.0 -40 73k 105k 186k ? 25 73k 113k 187k ? 85 82k 123k 190k ? 125 86k 132k 190k ? 5.5 -40 15k 21k 33k ? 25 15k 22k 34k ? 85 19k 26k 35k ? 125 23k 29k 35k ? rb3 2.0 -40 63k 81k 96k ? 25 77k 93k 116k ? 85 82k 96k 116k ? 125 86k 100k 119k ? 5.5 -40 16k 20k 22k ? 25 16k 21k 23k ? 85 24k 25k 28k ? 125 26k 27k 29k ? pic16f526 ds41326e-page 90 ? 2010 microchip technology inc. 14.3 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: figure 14-3: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance c l v ss pin legend: c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1 ? 2010 microchip technology inc. ds41326e-page 91 pic16f526 figure 14-4: external clock timing table 14-6: external clock timing requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial), -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 14.1 ?dc characteristics: pic16f526 (industrial)? param no. sym. characteristic min. typ. (1) max. units conditions 1a f osc external clkin frequency (2) dc ? 4 mhz xt oscillator mode dc ? 20 mhz hs/ec oscillator mode dc ? 200 khz lp oscillator mode oscillator frequency (2) ? ? 4 mhz extrc oscillator mode 0.1 ? 4 mhz xt oscillator mode 4 ? 20 mhz hs/ec oscillator mode ? ? 200 khz lp oscillator mode 1t osc external clkin period (2) 250 ? ? ns xt oscillator mode 50 ? ? ns hs/ec oscillator mode 5? ? ? s lp oscillator mode oscillator period (2) 250 ? ? ns extrc oscillator mode 250 ? 10,000 ns xt oscillator mode 50 ? 250 ns hs/ec oscillator mode 5? ? ? s lp oscillator mode 2t cy instruction cycle time 200 4/f osc ?ns 3 tosl, to s h clock in (osc1) low or high time 50* ? ? ns xt oscillator 2* ? ? ? s lp oscillator 10* ? ? ns hs/ec oscillator 4tosr, to s f clock in (osc1) rise or fall time ? ? 25* ns xt oscillator ? ? 50* ns lp oscillator ? ? 15* ns hs/ec oscillator * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. osc1 q4 q1 q2 q3 q4 q1 133 44 2 pic16f526 ds41326e-page 92 ? 2010 microchip technology inc. table 14-7: calibrated internal rc frequencies ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial), -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 14.1 ?dc characteristics: pic16f526 (industrial)? param no. sym. characteristic freq. tolerance min. typ.? max. units conditions f10 f osc internal calibrated intosc frequency (1) ?? 1% 7.92 8.00 8.08 mhz 3.5v, +25 ? c ?? 2% 7.84 8.00 8.16 mhz 2.5v ?? v dd ? 5.5v 0 ? c ? t a ? +85 ? c ?? 5% 7.60 8.00 8.40 mhz 2.0v ?? v dd ? 5.5v -40 ? c ? t a ? +85 ? c (ind.) -40 ? c ? t a ? +125 ? c (ext.) * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 uf and 0.01 uf values in parallel are recommended. ? 2010 microchip technology inc. ds41326e-page 93 pic16f526 figure 14-5: i/o timing table 14-8: timing requirements ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial) -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 14.1 ?dc characteristics: pic16f526 (industrial)? param no. sym. characteristic min. typ. (1) max. units 17 t os h2 io vosc1 ? (q1 cycle) to port out valid (2), (3) ??100*ns 18 t os h2 io iosc1 ? (q2 cycle) to port input invalid (i/o in hold time) (2) 50 ? ? ns 19 t io v2 os h port input valid to osc1 ? (i/o in setup time) 20 ? ? ns 20 t io r port output rise time (3) ?1050**ns 21 t io f port output fall time (3) ?1058**ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in extrc mode. 3: see figure 14-3 for loading conditions. osc1 i/o pin (input) i/o pin (output) q4 q1 q2 q3 17 20, 21 18 old value new value 19 note: all tests must be done with specified capacitive loads (see data sheet) 50 pf on i/o pins and clkout. pic16f526 ds41326e-page 94 ? 2010 microchip technology inc. figure 14-6: reset, watchdog timer and device reset timer timing table 14-9: reset, watchdog timer and device reset timer ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial) -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 14.1 ?dc characteristics: pic16f526 (industrial)? param no. sym. characteristic min. typ. (1) max. units conditions 30 t mc lmclr pulse width (low) 2000* ? ? ns v dd = 5.0v 31 t wdt watchdog timer time-out period (no prescaler) 9* 9* 18* 18* 30* 40* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) 32 t drt device reset timer period standard 9* 9* 18* 18* 30* 40* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) short 0.5* 0.5* 1.125* 1.125* 2* 2.5* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) 34 t ioz i/o high-impedance from mclr low ? ? 2000* ns * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out (2) internal reset watchdog timer reset 32 31 34 i/o pin (1) 32 32 34 30 note 1: i/o pins must be taken out of high-impedance mode by enabling the output drivers in software. 2: runs in mclr or wdt reset only in xt, lp and hs modes. ? 2010 microchip technology inc. ds41326e-page 95 pic16f526 figure 14-7: timer0 clock timings table 14-10: timer0 clock requirement ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial) -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 14.1 ?dc characteristics: pic16f526 (industrial)? param no. sym. characteristic min. typ. (1) max. units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 42 tt0p t0cki period 20 or t cy + 40* n ? ? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42 pic16f526 ds41326e-page 96 ? 2010 microchip technology inc. table 14-11: flash data memory write/erase time ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 ? c ? t a ? +85 ? c (industrial) -40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 14.1 ?dc characteristics: pic16f526 (industrial)? param no. sym. characteristic min. typ. (1) max. units conditions 43 t dw flash data memory write cycle time 23.55ms 44 t de flash data memory erase cycle time 23.55ms * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. ? 2010 microchip technology inc. ds41326e-page 97 pic16f526 15.0 dc and ac characteristics graphs and charts the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are ensured to operate properly only within the specified range ?typical? represents the mean of the distribution at 25 ? c. ?maximum? or ?minimum? represents (mean + 3 ? ) or (mean - 3 ? ) respectively, where s is a standard deviation, over each temperature range. figure 15-1: i dd vs . f osc over v dd (hs mode) note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 3.00 2.50 2.00 1.50 1.00 0.50 0.00 5 10 15 20 25 max. 5v typical 5v max. 2v typical 2v fosc (mhz) i dd (ma) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) pic16f526 ds41326e-page 98 ? 2010 microchip technology inc. figure 15-2: typical i dd vs. f osc over v dd (xt, extrc mode) figure 15-3: maximum i dd vs. f osc over v dd (xt, extrc mode) f osc (mhz) 0 100 200 300 400 500 600 700 800 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) 024 3 1 5 2v 5v i dd ( ? a ) f osc (mhz) 0 100 200 300 400 500 600 700 800 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) 024 3 1 5 2v 5v i dd ( ? a) ? 2010 microchip technology inc. ds41326e-page 99 pic16f526 figure 15-4: i dd vs. v dd over f osc (lp mode) 40 60 80 100 v dd (v) i dd ( ? a) 24 3 1 5 120 typical: statistical mean @25c extended: mean (worst-case temp) + 3 (-40c to 125c) 32 khz maximum industrial 32 khz typical 20 0 6 32 khz maximum extended industrial: mean (worst-case temp) + 3 ? (-40c to 85c) pic16f526 ds41326e-page 100 ? 2010 microchip technology inc. figure 15-5: typical i pd vs. v dd (sleep mode, all peripherals disabled) figure 15-6: maximum i pd vs. v dd (sleep mode, all peripherals disabled) 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) max. 125c max. 85c 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) ? 2010 microchip technology inc. ds41326e-page 101 pic16f526 figure 15-7: typical wdt i pd vs. v dd figure 15-8: maximum wdt i pd vs. v dd over temperature 0 1 2 3 4 5 6 7 8 9 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) max. 125c max. 85c 0.0 5.0 10.0 15.0 20.0 25.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) pic16f526 ds41326e-page 102 ? 2010 microchip technology inc. figure 15-9: comparator i pd vs. v dd (comparator enabled) figure 15-10: wdt time-out vs. v dd over temperature (no prescaler) 0 20 40 60 80 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( ? a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) typical maximum 0 5 10 15 20 25 30 35 40 45 50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) time (ms) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) max. 125c max. 85c typical. 25c min. -40c ? 2010 microchip technology inc. ds41326e-page 103 pic16f526 figure 15-11: v ol vs. i ol over temperature (v dd = 3.0v) figure 15-12: v ol vs. i ol over temperature (v dd = 5.0v) (vdd = 3v, -40c to 125c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 i ol (ma) v ol (v) max. 125c typical 25c min. -40c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) max. 85c 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 i ol (ma) v ol (v) typical: statistical mean @25c maximum: meas + 3 (-40c to 125c) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) max. 85c typ. 25c min. -40c max. 125c pic16f526 ds41326e-page 104 ? 2010 microchip technology inc. figure 15-13: v oh vs. i oh over temperature (v dd = 3.0v) figure 15-14: v oh vs. i oh over temperature (v dd = 5.0v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 i oh (ma) v oh (v) typ. 25c max. -40c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) (, ) 3.0 3.5 4.0 4.5 5.0 5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 i oh (ma) v oh (v) max. -40c typ. 25c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) ? 2010 microchip technology inc. ds41326e-page 105 pic16f526 figure 15-15: ttl input threshold v in vs. v dd figure 15-16: schmitt trigger input threshold v in vs. v dd (ttl input, -40c to 125c) 0.5 0.7 0.9 1.1 1.3 1.5 1.7 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) typ. 25c max. -40c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) (st input, -40c to 125c) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max. 125c v ih min. -40c v il min. 125c v il max. -40c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 ? (-40c to 125c) pic16f526 ds41326e-page 106 ? 2010 microchip technology inc. figure 15-17: device reset timer (hs, xt and lp) vs. v dd maximum (sleep mode all peripherals disabled) 0 5 10 15 20 25 30 35 40 45 2.02.5 3.03.5 4.04.5 5.05.5 v dd (v) drt (ms) min. -40c max. 85c note: see table 14-9 if another clock mode is selected. max. 125c typical. 25c ? 2010 microchip technology inc. ds41326e-page 107 pic16f526 16.0 packaging information 16.1 package marking information table 16-1: 16-lead 3x3 qfn (mg) top marking part number marking pic16f526-i/mg mg1 pic16f526-e/mg mg2 xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn 14-lead pdip (300 mil) 14-lead soic (3.90 mm) xxxxxxxxxxx yywwnnn example pic16f526-e 0431017 xxxxxxxxxxx 14-lead tssop (4.4 mm) xxxxxxxx yyww example 16f526-i 0431 nnn 017 /slg0125 example pic16f526 0410017 0215 3 e -i/pg xxx 16-lead qfn yyww nnn mg1 example 0431 017 note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard pic ? device marking consists of microchip part number, year code, week code, and traceability code. for pic device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. 3 e 3 e pic16f526 ds41326e-page 108 ? 2010 microchip technology inc. ! "#$ %! & '(!%&! %( %")% % % " *$ %+ % % , & "- " %!"& "$ % ! "$ % ! %#" . " & "% -/ 0 1+21 & % # % ! ))% !%% 3 % & %! % 4 " ) ' % 4 $ % %" % %% 255)))& &5 4 6% 7+8- & 9&% 7 7: ; 7!&( $ 7 % 1+ % % < < "" 4 4 0 , 0 1 % % 0 < < !" % !" ="% - , ,0 "" 4 ="% - 0 > : 9% ,0 0 0 % % 9 0 , 0 9 " 4 > 0 6 9 "="% ( 0 ? 9 ) 9 "="% ( > : ) * 1 < < , n e1 d note 1 12 3 e c eb a2 l a a1 b1 be ) +01 ? 2010 microchip technology inc. ds41326e-page 109 pic16f526 ! " ! ##$% &' !"( ! "#$ %! & '(!%&! %( %")% % % " *$ %+ % % , & "- " %!"& "$ % ! "$ % ! %#" 0&& " & "% -/ 0 1+2 1 & % # % ! ))% !%% -32 $ & '! ! )% !%% '$ $ & % ! 3 % & %! % 4 " ) ' % 4 $ % %" % %% 255)))& &5 4 6% 99- - & 9&% 7 7: ; 7!&( $ 7 % 1+ : 8 % < < 0 "" 4 4 0 < < % " $$* < 0 : ="% - ?1+ "" 4 ="% - ,1+ : 9% >?01+ + &$ @ % a 0 < 0 3 %9% 9 < 3 % % 9 -3 3 % b < >b 9 " 4 < 0 9 "="% ( , < 0 " $% 0b < 0b " $%1 %% & 0b < 0b note 1 n d e e1 1 23 b e a a1 a2 l l1 c h h ) +?01 pic16f526 ds41326e-page 110 ? 2010 microchip technology inc. 3 % & %! % 4 " ) ' % 4 $ % %" % %% 255)))& &5 4 ? 2010 microchip technology inc. ds41326e-page 111 pic16f526 )* !*#+ ! " !) & )!!" ! "#$ %! & '(!%&! %( %")% % % " & "- " %!"& "$ % ! "$ % ! %#" 0&& " , & "% -/ 0 1+2 1 & % # % ! ))% !%% -32 $ & '! ! )% !%% '$ $ & % ! 3 % & %! % 4 " ) ' % 4 $ % %" % %% 255)))& &5 4 6% 99- - & 9&% 7 7: ; 7!&( $ 7 % ?01+ : 8 % < < "" 4 4 > 0 % " $$ 0 < 0 : ="% - ?1+ "" 4 ="% - , 0 "" 4 9% 0 0 3 %9% 9 0 ? 0 3 % % 9 -3 3 % b < >b 9 " 4 < 9 "="% ( < , note 1 d n e e1 1 2 e b c a a1 a2 l1 l ) +>1 pic16f526 ds41326e-page 112 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2010 microchip technology inc. ds41326e-page 113 pic16f526 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging pic16f526 ds41326e-page 114 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2010 microchip technology inc. ds41326e-page 115 pic16f526 appendix a: revision history revision a (august 2007) original release of this document. revision b (december 2008) added dc and ac characteristics graphs; updated electrical characteristics section; added i/o diagrams; updated the flash data memory control section; made various changes to the special features of the cpu section and made general edits. miscellaneous updates. revision c (july 2009) removed ?preliminary? status; revised table 6-3: i/o pins; revised table 8-3: reset conditions; revised table 14-4: a/d converter char. revision d (march 2010) added package drawings and package marking information for the 16-lead package quad flat, no lead package (mg) - 3x3x0.9 mm body (qfn); updated the product identification system section. revision e (june 2010) revised section 6 (i/o) figures 6-1, 6-4 and 6-6. pic16f526 ds41326e-page 116 ? 2010 microchip technology inc. notes: ? 2010 microchip technology inc. ds41326e-page 117 pic16f526 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com pic16f526 ds41326e-page 118 ? 2010 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41326e pic16f526 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2010 microchip technology inc. ds41326e-page 119 pic16f526 index a a/d specifications.............................................................. 89 alu ..................................................................................... 11 assembler mpasm assembler..................................................... 80 b block diagram comparator for the pic16f526................................... 65 on-chip reset circuit ................................................. 51 timer0......................................................................... 37 tmr0/wdt prescaler................................................. 41 watchdog timer.......................................................... 54 brown-out protection circuit .............................................. 55 c c compilers mplab c18 ................................................................ 80 carry ................................................................................... 11 clock divisors ..................................................................... 59 clocking scheme ................................................................ 14 code protection ............................................................ 43, 57 config1 register.............................................................. 44 configuration bits................................................................ 43 customer change notification service ............................. 115 customer notification service........................................... 115 customer support............................................................. 115 d data memory (sram and fsrs) register file map.................................................. 16, 17 dc and ac characteristics ................................................. 97 graphs and tables ..................................................... 97 development support ......................................................... 79 digit carry ........................................................................... 11 e errata .................................................................................... 5 f flash data memory control ................................................ 23 fsr ..................................................................................... 22 fuses. see configuration bits i i/o interfacing ..................................................................... 29 i/o ports .............................................................................. 27 i/o programming considerations........................................ 36 id locations .................................................................. 43, 57 indf.................................................................................... 22 indirect data addressing..................................................... 22 instruction cycle ................................................................. 14 instruction flow/pipelining .................................................. 14 instruction set summary..................................................... 72 internet address................................................................ 115 l loading of pc ..................................................................... 21 m memory organization.......................................................... 15 memory map ............................................................... 15 pic16f526.................................................................. 15 program memory (pic16f526) .................................. 15 microchip internet web site.............................................. 115 mplab asm30 assembler, linker, librarian ..................... 80 mplab integrated development environment software.... 79 mplab pm3 device programmer ...................................... 82 mplab real ice in-circuit emulator system .................. 81 mplink object linker/mplib object librarian .................. 80 o option register................................................................... 19 osc selection..................................................................... 43 osccal register............................................................... 20 oscillator configurations..................................................... 45 oscillator types hs............................................................................... 45 lp ............................................................................... 45 rc .............................................................................. 45 xt ............................................................................... 45 p pic16f526 device varieties................................................. 9 por device reset timer (drt) ................................... 43, 53 pd ............................................................................... 55 power-on reset (por)............................................... 43 to ............................................................................... 55 portb ............................................................................... 27 portc ............................................................................... 27 power-down mode.............................................................. 56 prescaler ............................................................................ 40 program counter ................................................................ 21 q q cycles .............................................................................. 14 r rc oscillator....................................................................... 46 reader response............................................................. 116 read-modify-write.............................................................. 36 registers config1 (configuration word register 1)................ 44 special function ......................................................... 16 reset .................................................................................. 43 s sleep ............................................................................ 43, 56 software simulator (mplab sim) ...................................... 81 special ................................................................................ 17 special features of the cpu .............................................. 43 special function registers ........................................... 16, 17 stack................................................................................... 21 status register................................................................. 55 status register ............................................................. 11, 18 t timer0 timer0 ........................................................................ 37 timer0 (tmr0) module .............................................. 37 tmr0 with external clock .......................................... 39 timing diagrams and specifications .................................. 91 timing parameter symbology and load conditions .......... 90 tris register ..................................................................... 27 pic16f526 ds41326e-page 120 ? 2010 microchip technology inc. w wake-up from sleep ........................................................... 56 watchdog timer (wdt) ................................................ 43, 53 period.......................................................................... 53 programming considerations ..................................... 53 www address.................................................................. 115 www, on-line support........................................................ 5 z zero bit ................................................................................ 11 ? 2010 microchip technology inc. ds41326e-page 121 pic16f526 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16f526 pic16f526t (1) temperature range: i= -40 ? c to +85 ? c (industrial) e= -40 ? c to +125 ? c (extended) package: p = plastic (pdip) (2) sl = 14l small outline, 3.90 mm (soic) (2) st = thin shrink small outline (tssop) (2) mg = 16-lead 3x3 (qfn) (2) pattern: special requirements examples: a) pic16f526-e/p 301 = extended temp., pdip package, qtp pattern #301 b) pic16f526-i/sl = industrial temp., soic package c) pic16f526t-e/p = extended temp., pdip package, tape and reel d) pic16f526t-i/mg = industrial temp., qfn package, tape and reel note 1: t = in tape and reel soic, tssop and qfn packages only 2: pb-free. ds41326e-page 122 ? 2010 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 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munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/05/10 |
Price & Availability of PIC16F526-ESL
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