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1999 microchip technology inc. ds40139e-page 1 devices included in this data sheet: ? pic12c508 ? pic12c508a ? pic12ce518 ? pic12c509 ? pic12c509a ? pic12ce519 ? pic12cr509a note: throughout this data sheet pic12c5xx refers to the pic12c508, pic12c509, pic12c508a, pic12c509a, pic12cr509a, pic12ce518 and pic12ce519. pic12ce5xx refers to pic12ce518 and pic12ce519. high-performance risc cpu: ? only 33 single word instructions to learn ? all instructions are single cycle (1 m s) except for program branches which are two-cycle ? operating speed: dc - 4 mhz clock input dc - 1 m s instruction cycle ? 12-bit wide instructions ? 8-bit wide data path ? seven special function hardware registers ? two-level deep hardware stack ? direct, indirect and relative addressing modes for data and instructions ? internal 4 mhz rc oscillator with programmable calibration ? in-circuit serial programming device memory eprom program rom program ram data eeprom data pic12c508 512 x 12 25 pic12c508a 512 x 12 25 pic12c509 1024 x 12 41 pic12c509a 1024 x 12 41 pic12ce518 512 x 12 25 16 pic12ce519 1024 x 12 41 16 pic12cr509a 1024 x 12 41 peripheral features: ? 8-bit real time clock/counter (tmr0) with 8-bit programmable prescaler ? power-on reset (por) ?device reset timer (drt) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code-protection ? 1,000,000 erase/write cycle eeprom data memory ? eeprom data retention > 40 years ? power saving sleep mode ? wake-up from sleep on pin change ? internal weak pull-ups on i/o pins ? internal pull-up on mclr pin ? selectable oscillator options: - intrc: internal 4 mhz rc oscillator - extrc: external low-cost rc oscillator - xt: standard crystal/resonator - lp: power saving, low frequency crystal cmos technology: ? low power, high speed cmos eprom/rom technology ? fully static design ? wide operating voltage range ? wide temperature range: - commercial: 0c to +70c - industrial: -40c to +85c - extended: -40c to +125c ? low power consumption - < 2 ma @ 5v, 4 mhz - 15 m a typical @ 3v, 32 khz - < 1 m a typical standby current pic12c5xx 8-pin, 8-bit cmos microcontrollers
pic12c5xx ds40139e-page 2 1999 microchip technology inc. pin diagram - pic12c508/509 pin diagram - pic12c508a/509a, pic12ce518/519 pin diagram - pic12cr509a pdip, 208 mil soic, windowed ceramic side brazed 8 7 6 5 1 2 3 4 v ss gp0 gp1 gp2/t0cki gp5/osc1/clkin gp4/osc2 gp3/mclr /v pp v dd pic12c508 pic12c509 pdip, 150 & 208 mil soic, windowed cerdip 8 7 6 5 1 2 3 4 pic12ce518 v ss gp0 gp1 gp2/t0cki pic12ce519 gp5/osc1/clkin gp4/osc2 gp3/mclr /v pp v dd pic12c508a pic12c509a pdip, 150 & 208 mil soic 8 7 6 5 1 2 3 4 v ss gp0 gp1 gp2/t0cki pic12cr509a gp5/osc1/clkin gp4/osc2 gp3/mclr /v pp v dd device differences note 1: if you change from the pic12c50x to the pic12c50xa or to the pic12cr50xa, please verify oscillator characteristics in your application. note 2: see section 7.2.5 for osccal implementation differences. device voltage range oscillator oscillator calibration 2 (bits) process technology (microns) pic12c508a 3.0-5.5 see note 1 6 0.7 pic12lc508a 2.5-5.5 see note 1 6 0.7 pic12c508 2.5-5.5 see note 1 4 0.9 pic12c509a 3.0-5.5 see note 1 6 0.7 pic12lc509a 2.5-5.5 see note 1 6 0.7 pic12c509 2.5-5.5 see note 1 4 0.9 pic12cr509a 2.5-5.5 see note 1 6 0.7 pic12ce518 3.0-5.5 - 6 0.7 pic12lce518 2.5-5.5 - 6 0.7 pic12ce519 3.0-5.5 - 6 0.7 pic12lce519 2.5-5.5 - 6 0.7
1999 microchip technology inc. ds40139e-page 3 pic12c5xx table of contents 1.0 general description......................................................................................................... ...................................... 4 2.0 pic12c5xx device varieties .................................................................................................. .............................. 7 3.0 architectural overview...................................................................................................... ..................................... 9 4.0 memory organization ......................................................................................................... ................................. 13 5.0 i/o port .................................................................................................................... ............................................ 21 6.0 timer0 module and tmr0 register ............................................................................................. ....................... 25 7.0 eeprom peripheral operation................................................................................................. .......................... 29 8.0 special features of the cpu ................................................................................................. .............................. 35 9.0 instruction set summary ..................................................................................................... ................................ 47 10.0 development support........................................................................................................ .................................. 59 11.0 electrical characteristics - pic12c508/pic12c509........................................................................... ................. 65 12.0 dc and ac characteristics - pic12c508/pic12c509 ............................................................................ ............ 75 13.0 electrical characteristics pic12c508a/pic12c509a/pic12lc508a/pic12lc509a/pic12cr509a/ pic12ce518/pic12ce519/ pic12lce518/pic12lce519/pic12lcr509a ........................................................................................... ........ 79 14.0 dc and ac characteristics pic12c508a/pic12c509a/pic12lc508a/pic12lc509a/pic12ce518/pic12ce519/pic12cr509a/ pic12lce518/pic12lce519/ pic12lcr509a .......................................................................................... ........ 93 15.0 packaging information...................................................................................................... ................................... 99 index .......................................................................................................................... ................................................. 105 pic12c5xx product identification system ....................................................................................... ......................... 109 sales and support: ............................................................................................................. ........................................ 109 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. the last character of the literature number is the version number. e.g., ds30000a is version a of doc- ument ds30000. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and rec- ommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchips worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literature center; u.s. fax: (602) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. corrections to this data sheet we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that this document is correct. however, we realize that we may have missed a few things. if you find any information that is missing or appears in error, please: ? fill out and mail in the reader response form in the back of this data sheet. ? e-mail us at webmaster@microchip.com. we appreciate your assistance in making this a better document.
pic12c5xx ds40139e-page 4 1999 microchip technology inc. 1.0 general description the pic12c5xx from microchip technology is a fam- ily of low-cost, high performance, 8-bit, fully static, eeprom/eprom/rom-based cmos microcontrol- lers. it employs a risc architecture with only 33 sin- gle word/single cycle instructions. all instructions are single cycle (1 m s) except for program branches which take two cycles. the pic12c5xx delivers per- formance an order of magnitude higher than its com- petitors in the same price category. the 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. the easy to use and easy to remember instruction set reduces development time signifi- cantly. the pic12c5xx products are equipped with special features that reduce system cost and power require- ments. the power-on reset (por) and device reset timer (drt) eliminate the need for external reset cir- cuitry. there are four oscillator configurations to choose from, including intrc internal oscillator mode and the power-saving lp (low power) oscillator mode. power saving sleep mode, watchdog timer and code protection features also improve system cost, power and reliability. the pic12c5xx are available in the cost-effective one-time-programmable (otp) versions which are suitable for production in any volume. the customer can take full advantage of microchips price leadership in otp microcontrollers while benefiting from the otps flexibility. the pic12c5xx products are supported by a full-fea- tured macro assembler, a software simulator, an in-cir- cuit emulator, a c compiler, fuzzy logic support tools, a low-cost development programmer, and a full fea- tured programmer. all the tools are supported on ibm pc and compatible machines. 1.1 applications the pic12c5xx series fits perfectly in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. the eprom technology makes customizing applica- tion programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and conve- nient, while the eeprom data memory technology allows for the changing of calibration factors and secu- rity codes. the small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. low-cost, low-power, high performance, ease of use and i/o flexibility make the pic12c5xx series very ver- satile even in areas where no microcontroller use has been considered before (e.g., timer functions, replace- ment of glue logic and plds in larger systems, copro- cessor applications).
1999 microchip technology inc. ds40139e-page 5 pic12c5xx table 1-1: pic12cxxx & pic12cexxx family of devices pic12c508(a) pic12c509(a) pic12cr509a pic12ce518 pic12ce519 pic12c671 pic12c672 pic12ce673 pic12ce674 clock maximum frequency of operation (mhz) 4444410101010 memory eprom program memory 512 x 12 1024 x 12 1024 x 12 (rom) 512 x 12 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14 ram data memory (bytes) 25 41 41 25 41 128 128 128 128 peripherals eeprom data memory (bytes) 16161616 timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 a/d con- verter (8-bit) channels 4444 features wake-up from sleep on pin change yes yes yes yes yes yes yes yes yes interrupt sources 4444 i/o pins 5 5 5 5 5 5 5 5 5 input pins111111111 internal pull-ups yes yes yes yes yes yes yes yes yes in-circuit serial programming yes yes yes yes yes yes yes yes number of instructions 33 33 33 33 33 35 35 35 35 packages 8-pin dip, jw, soic 8-pin dip, jw, soic 8-pin dip, soic 8-pin dip, jw, soic 8-pin dip, jw, soic 8-pin dip, jw, soic 8-pin dip, jw, soic 8-pin dip, jw 8-pin dip, jw all pic12cxxx & pic12cexxx devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic12cxxx & pic12cexxx devices use serial programming with data pin gp0 and clock pin gp1.
pic12c5xx ds40139e-page 6 1999 microchip technology inc. notes:
1999 microchip technology inc. ds40139e-page 7 pic12c5xx 2.0 pic12c5xx device varieties a variety of packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic12c5xx product identification system at the back of this data sheet to specify the correct part number. 2.1 uv erasable devices the uv erasable version, offered in ceramic side brazed package, is optimal for prototype development and pilot programs. the uv erasable version can be erased and reprogrammed to any of the configuration modes. microchip's picstart a plus and pro mate a pro- grammers all support programming of the pic12c5xx. third party programmers also are available; refer to the microchip third party guide for a list of sources. 2.2 one-time-programmable (otp) devices the availability of otp devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications. the otp devices, packaged in plastic packages permit the user to program them once. in addition to the program memory, the configuration bits must also be programmed. note: please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. the calibration value must be saved prior to erasing the part. 2.3 quick-turnaround-production (qtp) devices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. the devices are identical to the otp devices but with all eprom locations and fuse options already programmed by the factory. certain code and prototype verification procedures do apply before production shipments are available. please con- tact your local microchip technology sales office for more details. 2.4 serialized quick-turnaround production (sqtp sm ) devices microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number which can serve as an entry-code, password or id number. 2.5 read only memory (rom) device microchip offers masked rom to give the customer a low cost option for high volume, mature products.
pic12c5xx ds40139e-page 8 1999 microchip technology inc. notes:
1999 microchip technology inc. ds40139e-page 9 pic12c5xx 3.0 architectural overview the high performance of the pic12c5xx family can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic12c5xx uses a harvard architecture in which program and data are accessed on separate buses. this improves bandwidth over traditional von neumann architecture where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12-bits wide making it possible to have all single word instructions. a 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions. consequently, all instructions (33) execute in a single cycle (1 m s @ 4mhz) except for program branches. the table below lists program memory (eprom), data memory (ram), rom memory, and non-volatile (eeprom) for each device. the pic12c5xx can directly or indirectly address its register files and data memory. all special function registers including the program counter are mapped in the data memory. the pic12c5xx has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of special optimal situations make programming with the pic12c5xx simple yet efficient. in addition, the learning curve is reduced significantly. device memory eprom program rom program ram data eeprom data pic12c508 512 x 12 25 pic12c509 1024 x 12 41 pic12c508a 512 x 12 25 pic12c509a 1024 x 12 41 pic12cr509a 1024 x 12 41 pic12ce518 512 x 12 25 x 8 16 x 8 pic12ce519 1024 x 12 41 x 8 16 x 8 the pic12c5xx device contains an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8-bits wide and capable of addition, subtraction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's complement in nature. in two-operand instructions, typically one operand is the w (working) register. the other operand is either a file register or an immediate constant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the subwf and addwf instructions for examples. a simplified block diagram is shown in figure 3-1, with the corresponding device pins described in table 3-1.
pic12c5xx ds40139e-page 10 1999 microchip technology inc. figure 3-1: pic12c5xx block diagram device reset timer power-on reset watchdog timer rom/eprom program memory 12 data bus 8 12 program bus instruction reg program counter ram file registers direct addr 5 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode & control timing generation osc1/clkin osc2 mclr v dd , v ss timer0 gpio 8 8 gp4/osc2 gp3/mclr /v pp gp2/t0cki gp1 gp0 5-7 3 gp5/osc1/clkin stack1 stack2 512 x 12 or 25 x 8 or 1024 x 12 4 1 x 8 internal rc osc 16 x 8 eeprom data memory pic12ce5xx only sda scl
1999 microchip technology inc. ds40139e-page 11 pic12c5xx table 3-1: pic12c5xx pinout description name dip pin # soic pin # i/o/p type buffer type description gp0 7 7 i/o ttl/st bi-directional i/o port/ serial programming data. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. this buffer is a schmitt trigger input when used in serial programming mode. gp1 6 6 i/o ttl/st bi-directional i/o port/ serial programming clock. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. this buffer is a schmitt trigger input when used in serial programming mode. gp2/t0cki 5 5 i/o st bi-directional i/o port. can be configured as t0cki. gp3/mclr /v pp 4 4 i ttl/st input port/master clear (reset) input/programming volt- age input. when configured as mclr , this pin is an active low reset to the device. voltage on mclr /v pp must not exceed v dd during normal device operation or the device will enter programming mode. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. weak pull-up always on if configured as mclr . st when in mclr mode. gp4/osc2 3 3 i/o ttl bi-directional i/o port/oscillator crystal output. con- nections to crystal or resonator in crystal oscillator mode (xt and lp modes only, gpio in other modes). gp5/osc1/clkin 2 2 i/o ttl/st bidirectional io port/oscillator crystal input/external clock source input (gpio in internal rc mode only, osc1 in all other oscillator modes). ttl input when gpio, st input in external rc oscillator mode. v dd 11p positive supply for logic and i/o pins v ss 8 8 p ground reference for logic and i/o pins legend: i = input, o = output, i/o = input/output, p = power, = not used, ttl = ttl input, st = schmitt trigger input
pic12c5xx ds40139e-page 12 1999 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks namely q1, q2, q3 and q4. internally, the program counter is incremented every q1, and the instruction is fetched from program memory and latched into instruction register in q4. it is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-2 and example 3-1. 3.2 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ) then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed. 1. movlw 03h fetch 1 execute 1 2. movwf gpio fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf gpio, bit1 fetch 4 flush fetch sub_1 execute sub_1
1999 microchip technology inc. ds40139e-page 13 pic12c5xx 4.0 memory organization pic12c5xx memory is organized into program mem- ory and data memory. for devices with more than 512 bytes of program memory, a paging scheme is used. program memory pages are accessed using one sta- tus register bit. for the pic12c509, pic12c509a, piccr509a and pic12ce519 with a data memory register file of more than 32 registers, a banking scheme is used. data memory banks are accessed using the file select register (fsr). 4.1 program memory organization the pic12c5xx devices have a 12-bit program counter (pc) capable of addressing a 2k x 12 program memory space. only the first 512 x 12 (0000h-01ffh) for the pic12c508, pic12c508a and pic12ce518 and 1k x 12 (0000h-03ffh) for the pic12c509, pic12c509a, pic12cr509a, and pic12ce519 are physically implemented. refer to figure 4-1. accessing a location above these boundaries will cause a wrap- around within the first 512 x 12 space (pic12c508, pic12c508a and pic12ce518) or 1k x 12 space (pic12c509, pic12c509a, pic12cr509a and pic12ce519). the effective reset vector is at 000h, (see figure 4-1). location 01ffh (pic12c508, pic12c508a and pic12ce518) or location 03ffh (pic12c509, pic12c509a, pic12cr509a and pic12ce519) contains the internal clock oscillator calibration value. this value should never be overwritten. figure 4-1: program memory map and stack call, retlw pc<11:0> stack level 1 stack level 2 user memory space 12 0000h 7ffh 01ffh 0200h on-chip program memory reset vector (note 1) note 1: address 0000h becomes the effective reset vector. location 01ffh (pic12c508, pic12c508a, pic12ce518) or location 03ffh (pic12c509, pic12c509a, pic12cr509a, pic12ce519) con- tains the movlw xx internal rc oscillator calibration value. 512 word 1024 word 03ffh 0400h on-chip program memory
pic12c5xx ds40139e-page 14 1999 microchip technology inc. 4.2 data memory organization data memory is composed of registers, or bytes of ram. therefore, data memory for a device is specified by its register file. the register file is divided into two functional groups: special function registers and general purpose registers. the special function registers include the tmr0 register, the program counter (pc), the status register, the i/o registers (ports), and the file select register (fsr). in addition, special purpose registers are used to control the i/o port configuration and prescaler options. the general purpose registers are used for data and control information under command of the instructions. for the pic12c508, pic12c508a and pic12ce518, the register file is composed of 7 special function registers and 25 general purpose registers (figure 4- 2). for the pic12c509, pic12c509a, pic12cr509a, and pic12ce519 the register file is composed of 7 special function registers, 25 general purpose registers, and 16 general purpose registers that may be addressed using a banking scheme (figure 4-3). 4.2.1 general purpose register file the general purpose register file is accessed either directly or indirectly through the file select register fsr (section 4.8). figure 4-2: pic12c508, pic12c508a and pic12ce518 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal gpio general purpose registers note 1: not a physical register. see section 4.8 figure 4-3: pic12c509, pic12c509a, pic12cr509a and pic12ce519 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal gpio 0fh 10h bank 0 bank 1 3fh 30h 20h 2fh general purpose registers general purpose registers general purpose registers addresses map back to addresses in bank 0. note 1: not a physical register. see section 4.8 fsr<6:5> 00 01
1999 microchip technology inc. ds40139e-page 15 pic12c5xx 4.2.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral functions to control the operation of the device (table 4-1). the special registers can be classified into two sets. the special function registers associated with the core functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. table 4-1: special function register (sfr) summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (2) n/a tris --11 1111 --11 1111 n/a option contains control bits to configure timer0, timer0/wdt prescaler, wake-up on change, and weak pull-ups 1111 1111 1111 1111 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h tmr0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h (1) pcl low order 8 bits of pc 1111 1111 1111 1111 03h status gpwuf pa0to pd zdcc 0001 1xxx q00q quuu (3) 04h fsr (pic12c508/ pic12c508a/ pic12c518) indirect data memory address pointer 111x xxxx 111u uuuu 04h fsr (pic12c509/ pic12c509a/ pic12cr509a/ pic12ce519) indirect data memory address pointer 110x xxxx 11uu uuuu 05h osccal (pic12c508/ pic12c509) cal3 cal2 cal1 cal0 0111 ---- uuuu ---- 05h osccal (pic12c508a/ pic12c509a/ pic12ce518/ pic12ce519/ pic12cr509a) cal5 cal4 cal3 cal2 cal1 cal0 1000 00-- uuuu uu-- 06h gpio (pic12c508/ pic12c509/ pic12c508a/ pic12c509a/ pic12cr509a) gp5 gp4 gp3 gp2 gp1 gp0 --xx xxxx --uu uuuu 06h gpio (pic12ce518/ pic12ce519) scl sda gp5 gp4 gp3 gp2 gp1 gp0 11xx xxxx 11uu uuuu legend: shaded boxes = unimplemented or unused, = unimplemented, read as '0' (if applicable) x = unknown, u = unchanged, q = see the tables in section 8.7 for possible values. note 1: the upper byte of the program counter is not directly accessible. see section 4.6 for an explanation of how to access these bits. 2: other (non power-up) resets include external reset through mclr , watchdog timer and wake-up on pin change reset. 3: if reset was due to wake-up on pin change then bit 7 = 1. all other resets will cause bit 7 = 0.
pic12c5xx ds40139e-page 16 1999 microchip technology inc. 4.3 s tatus register this register contains the arithmetic status of the alu, the reset status, and the page preselect bit for program memories larger than 512 words. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf , bsf and movwf instructions be used to alter the status register because these instructions do not affect the z, dc or c bits from the status register. for other instructions, which do affect status bits, see instruction set summary. figure 4-4: status register (address:03h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x gpwuf pa 0 to pd z dc c r = readable bit w = writable bit - n = value at por reset bit7 6 5 4 3 2 1 bit0 bit 7: gpwuf : gpio reset bit 1 = reset due to wake-up from sleep on pin change 0 = after power up or other reset bit 6: unimplemented bit 5: pa 0 : program page preselect bits 1 = page 1 (200h - 3ffh) - pic12c509, pic12c509a, pic12cr509a and pic12ce519 0 = page 0 (000h - 1ffh) - pic12c5xx each page is 512 bytes. using the pa0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit (for addwf and subwf instructions) addwf 1 = a carry from the 4th low order bit of the result occurred 0 = a carry from the 4th low order bit of the result did not occur subwf 1 = a borrow from the 4th low order bit of the result did not occur 0 = a borrow from the 4th low order bit of the result occurred bit 0: c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf subwf rrf or rlf 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred
1999 microchip technology inc. ds40139e-page 17 pic12c5xx 4.4 o ption register the option register is a 8-bit wide, write-only register which contains various control bits to configure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option register. a reset sets the option<7:0> bits. note: if tris bit is set to 0, the wake-up on change and pull-up functions are disabled for that pin; i.e., note that tris overrides option control of gppu and gpwu . note: if the t0cs bit is set to 1, gp2 is forced to be an input even if tris gp2 = 0. figure 4-5: option register w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 gpwu gppu t0cs t0se psa ps2 ps1 ps0 w = writable bit u = unimplemented bit - n = value at por reset reference table 4-1 for other resets. bit7 6 5 4 3 2 1 bit0 bit 7: gpwu : enable wake-up on pin change (gp0, gp1, gp3) 1 = disabled 0 = enabled bit 6: gppu : enable weak pull-ups (gp0, gp1, gp3) 1 = disabled 0 = enabled bit 5: t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = transition on internal instruction cycle clock, fosc/4 bit 4: t0se : timer0 source edge select bit 1 = increment on high to low transition on the t0cki pin 0 = increment on low to high transition on the t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
pic12c5xx ds40139e-page 18 1999 microchip technology inc. 4.5 osccal register the oscillator calibration (osccal) register is used to calibrate the internal 4 mhz oscillator. it contains four to six bits for calibration. increasing the cal value increases the frequency. see section 7.2.5 for more information on the internal oscillator. figure 4-6: osccal register (address 05h) for pic12c508 and pic12c509 figure 4-7: osccal register (address 05h) for pic12c508a/c509a/cr509a/12ce518/ 12ce519 r/w-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 u-0 u-0 cal3 cal2 cal1 cal0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-4: cal<3:0>: calibration bit 3-0: unimplemented: read as '0' r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 cal5 cal4 cal3 cal2 cal1 cal0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-2: cal<5:0>: calibration bit 1-0: unimplemented: read as '0'
1999 microchip technology inc. ds40139e-page 19 pic12c5xx 4.6 program counter as a program instruction is executed, the program counter (pc) will contain the address of the next program instruction to be executed. the pc value is increased by one every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. the pc latch (pcl) is mapped to pc<7:0>. bit 5 of the status register provides page information to bit 9 of the pc (figure 4- 8). for a call instruction, or any instruction where the pcl is the destination, bits 7:0 of the pc again are provided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 4-8). instructions where the pcl is the destination, or modify pcl instructions, include movwf pc, addwf pc, and bsf pc,5. figure 4-8: loading of pc branch instructions - pic12c5xx note: because pc<8> is cleared in the call instruction, or any modify pcl instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any pro- gram memory page (512 words long). pa 0 status pc 87 0 pcl 9 10 instruction word 70 goto instruction call or modify pcl instruction 11 pa 0 status pc 87 0 pcl 9 10 instruction word 70 11 reset to 0 4.6.1 effects of reset the program counter is set upon a reset, which means that the pc addresses the last location in the last page i.e., the oscillator calibration instruction. after executing movlw xx, the pc will roll over to location 00h, and begin executing user code. the status register page preselect bits are cleared upon a reset, which means that page 0 is pre- selected. therefore, upon a reset, a goto instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 4.7 s tack pic12c5xx devices have a 12-bit wide l.i.f.o. hardware push/pop stack. a call instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. if more than two sequential call s are executed, only the most recent two return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. if more than two sequential retlw s are executed, the stack will be filled with the address previously stored in level 2. note that the w register will be loaded with the literal value specified in the instruction. this is particularly useful for the implementation of data look-up tables within the program memory. upon any reset, the contents of the stack remain unchanged, however the program counter (pcl) will also be reset to 0. note 1: there are no status bits to indicate stack overflows or stack underflow condi- tions. note 2: there are no instructions mnemonics called push or pop. these are actions that occur from the execution of the call and retlw instructions.
pic12c5xx ds40139e-page 20 1999 microchip technology inc. 4.8 indirect data addressing; indf and fsr registers the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 4-1: indirect addressing ? register file 07 contains the value 10h ? register file 08 contains the value 0ah ? load the value 07 into the fsr register ? a read of the indf register will return the value of 10h ? increment the value of the fsr register by one (fsr = 08) ? a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-2. example 4-2: how to clear ram using indirect addressing movlw 0x10 ;in itialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue the fsr is a 5-bit wide register. it is used in conjunction with the indf register to indirectly address the data memory area. the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. pic12c508/pic12c508a/pic12ce518: does not use banking. fsr<7:5> are unimplemented and read as '1's. pic12c509/pic12c509a/pic12cr509a/ pic12ce519: uses fsr<5>. selects between bank 0 and bank 1. fsr<7:6> is unimplemented, read as '1 . figure 4-9: direct/indirect addressing note 1: for register map detail see section 4.2. note 2: pic12c509, pic12c509a, pic12cr509a, pic12ce519. bank location select location select bank select indirect addressing direct addressing data memory (1) 0fh 10h bank 0 bank 1 (2) 0 4 5 6 (fsr) 00 01 00h 1fh 3fh (opcode) 0 4 5 6 (fsr) addresses map back to addresses in bank 0.
1999 microchip technology inc. ds40139e-page 21 pic12c5xx 5.0 i/o port as with any other register, the i/o register can be written and read under program control. however, read instructions (e.g., movf gpio,w ) always read the i/o pins independent of the pins input/output modes. on reset, all i/o ports are defined as input (inputs are at hi-impedance) since the i/o control registers are all set. see section 7.0 for scl and sda description for pic12ce5xx. 5.1 gpio gpio is an 8-bit i/o register. only the low order 6 bits are used (gp5:gp0). bits 7 and 6 are unimplemented and read as '0's. please note that gp3 is an input only pin. the configuration word can set several i/os to alternate functions. when acting as alternate functions the pins will read as 0 during port read. pins gp0, gp1, and gp3 can be configured with weak pull-ups and also with wake-up on change. the wake-up on change and weak pull-up functions are not pin selectable. if pin 4 is configured as mclr , weak pull- up is always on and wake-up on change for this pin is not enabled. 5.2 tris register the output driver control register is loaded with the contents of the w register by executing the tris f instruction. a '1' from a tris register bit puts the corresponding output driver in a hi-impedance mode. a '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. the exceptions are gp3 which is input only and gp2 which may be controlled by the option register, see figure 4- 5. the tris registers are write-only and are set (output drivers disabled) upon reset. note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. 5.3 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 5-1. all port pins, except gp3 which is input only, may be used for both input and output operations. for input operations these ports are non-latching. any input must be present until read by an input instruction (e.g., movf gpio,w ). the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the corresponding direction control bit in tris must be cleared (= 0). for use as an input, the corresponding tris bit must be set. any i/o pin (except gp3) can be programmed individually as input or output. figure 5-1: equivalent circuit for a single i/o pin data bus q d q ck q d q ck p n wr port tris f data tris rd port v ss v dd i/o pin (1,3) w reg latch latch reset (2) note 1: i/o pins have protection diodes to v dd and v ss . note 2: see table 3-1 for buffer type. note 3: see section 7.0 for scl and sda description for pic12ce5xx
pic12c5xx ds40139e-page 22 1999 microchip technology inc. table 5-1: summary of port registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a tris --11 1111 --11 1111 n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 03h status gpwuf pa o to pd z dc c 0001 1xxx q00q quuu (1) 06h gpio (pic12c508/ pic12c509/ pic12c508a/ pic12c509a/ pic12cr509a) gp5 gp4 gp3 gp2 gp1 gp0 --xx xxxx --uu uuuu 06h gpio (pic12ce518/ pic12ce519) scl sda gp5 gp4 gp3 gp2 gp1 gp0 11xx xxxx 11uu uuuu legend: shaded cells not used by port registers, read as 0, = unimplemented, read as '0', x = unknown, u = unchanged, q = see tables in section 8.7 for possible values. note 1: if reset was due to wake-up on change, then bit 7 = 1. all other resets will cause bit 7 = 0. 5.4 i/o programming considerations 5.4.1 bi-directional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and re-write the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit5 of gpio will cause all eight bits of gpio to be read into the cpu, bit5 to be set and the gpio value to be written to the output latches. if another bit of gpio is used as a bi- directional i/o pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. example 5-1 shows the effect of two sequential read- modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (wired-or, wired- and). the resulting high output currents may damage the chip. example 5-1: read-modify-write instructions on an i/o port ;initial gpio settings ; gpio<5:3> inputs ; gpio<2:0> outputs ; ; gpio latch gpio pins ; ---------- ---------- bcf gpio, 5 ;--01 -ppp --11 pppp bcf gpio, 4 ;--10 -ppp --11 pppp movlw 007h ; tris gpio ;--10 -ppp --11 pppp ; ;note that the user may have expected the pin ;values to be --00 pppp. the 2nd bcf caused ;gp5 to be latched as the pin value (high). 5.4.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-2). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the cpu, is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port.
1999 microchip technology inc. ds40139e-page 23 pic12c5xx figure 5-2: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched gp5:gp0 movwf gpio nop port pin sampled here nop movf gpio,w instruction executed movwf gpio (write to gpio) nop movf gpio,w this example shows a write to gpio followed by a read from gpio. data setup time = (0.25 t cy C t pd ) where: t cy = instruction cycle. t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic. (read gpio) port pin written here
pic12c5xx ds40139e-page 24 1999 microchip technology inc. notes:
1999 microchip technology inc. ds40139e-page 25 pic12c5xx 6.0 timer0 module and tmr0 register the timer0 module has the following features: ? 8-bit timer/counter register, tmr0 - readable and writable ? 8-bit software programmable prescaler ? internal or external clock select - edge select for external clock figure 6-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two instruction cycles (figure 6-2 and figure 6-3). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the t0se bit (option<4>) determines the source edge. clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.1. the prescaler may be used by either the timer0 module or the watchdog timer, but not both. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 6.2 details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 6-1. figure 6-1: timer0 block diagram note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register. 2: the prescaler is shared with the watchdog timer (figure 6-5). 0 1 1 0 t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg psout (2 t cy delay) psout data bus 8 psa (1) ps2, ps1, ps0 (1) 3 sync t0se gp2/t0cki pin
pic12c5xx ds40139e-page 26 1999 microchip technology inc. figure 6-2: timer0 timing: internal clock/no prescale figure 6-3: timer0 timing: internal clock/prescale 1:2 table 6-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 01h tmr0 timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 n/a tris gp5 gp4 gp3 gp2 gp1 gp0 --11 1111 --11 1111 legend: shaded cells not used by timer0, - = unimplemented, x = unknown, u = unchanged, pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0+1 nt0+2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute t0
1999 microchip technology inc. ds40139e-page 27 pic12c5xx 6.1 using t imer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. also, there is a delay in the actual incrementing of timer0 after synchronization. 6.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-4). therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of 10 ns. refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actually incremented. figure 6-4 shows the delay from the external clock edge to the timer incrementing. 6.1.3 option register effect on gp2 tris if the option register is set to read timer0 from the pin, the port is forced to an input regardless of the tris reg- ister setting. figure 6-4: timer0 timing with external clock increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) note 1: 2: 3: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = 4tosc max. external clock if no prescaler selected, prescaler output otherwise. the arrows indicate the points in time where sampling occurs. prescaler output (2) (1)
pic12c5xx ds40139e-page 28 1999 microchip technology inc. 6.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer (wdt), respectively (section 8.6). for simplicity, this counter is being referred to as prescaler throughout this data sheet. note that the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt, and vice-versa. the psa and ps2:ps0 bits (option<3:0>) determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is neither readable nor writable. on a reset, the prescaler contains all '0's. 6.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed on the fly during program execution). to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 6-1: changing prescaler (timer0 ? wdt) 1.clrwdt ;clear wdt 2. clrf tmr0 ;clear tmr0 & prescaler 3.movlw '00xx1111b ;these 3 lines (5, 6, 7) 4.option ; are required only if ; desired 5.clrwdt ;ps<2:0> are 000 or 001 6.movlw '00xx1xxxb ;set postscaler to 7.option ; desired wdt rate to change prescaler from the wdt to the timer0 module, use the sequence shown in example 6-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switching the prescaler. example 6-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and ;prescaler movlw 'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source option figure 6-5: block diagram of the timer0/wdt prescaler t cy ( = fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m mux watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are bits in the option register. psa wdt enable bit 0 1 0 1 data bus 8 psa t0cs m u x m u x u x t0se gp2/t0cki pin
1999 microchip technology inc. ds40139e-page 29 pic12c5xx 7.0 eeprom peripheral operation this section applies to pic12ce518 and pic12ce519 only. the pic12ce518 and pic12ce519 each have 16 bytes of eeprom data memory. the eeprom mem- ory has an endurance of 1,000,000 erase/write cycles and a data retention of greater than 40 years. the eeprom data memory supports a bi-directional 2-wire bus and data transmission protocol. these two-wires are serial data (sda) and serial clock (scl), that are mapped to bit6 and bit7, respectively, of the gpio reg- ister (sfr 06h). unlike the gp0-gp5 that are con- nected to the i/o pins, sda and scl are only connected to the internal eeprom peripheral. for most applications, all that is required is calls to the fol- lowing functions: ; byte_write: byte write routine ; inputs: eeprom address eeaddr ; eeprom data eedata ; outputs: return 01 in w if ok, else return 00 in w ; ; read_current: read eeprom at address currently held by ee device. ; inputs: none ; outputs: eeprom data eedata ; return 01 in w if ok, else return 00 in w ; ; read_random: read eeprom byte at supplied address ; inputs: eeprom address eeaddr ; outputs: eeprom data eedata ; return 01 in w if ok, else return 00 in w the code for these functions is available on our website www.microchip.com. the code will be accessed by either including the source code fl51xinc.asm or by linking flash5ix.asm. it is very important to check the return codes when using these calls, and retry the operation if unsuccess- ful. unsuccessful return codes occur when the ee data memory is busy with the previous write, which can take up to 4 ms. 7.0.1 serial data sda is a bi-directional pin used to transfer addresses and data into and data out of the device. for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop condi- tions. the eeprom interface is a 2-wire bus protocol con- sisting of data (sda) and a clock (scl). although these lines are mapped into the gpio register, they are not accessible as external pins; only to the internal eeprom peripheral. sda and scl operation is also slightly different than gpo-gp5 as listed below. namely, to avoid code overhead in modifying the tris register, both sda and scl are always outputs. to read data from the eeprom peripheral requires out- putting a 1 on sda placing it in high-z state, where only the internal 100k pull-up is active on the sda line. sda: built-in 100k (typical) pull-up to vdd open-drain (pull-down only) always an output outputs a 1 on reset scl: full cmos output always an output outputs a 1 on reset the following example requires: ? code space: 77 words ? ram space: 5 bytes (4 are overlayable) ? stack levels:1 (the call to the function itself. the functions do not call any lower level functions.) ? timing: - write_byte takes 328 cycles - read_current takes 212 cycles - read_random takes 416 cycles. ? io pins: 0 (no external io pins are used) this code must reside in the lower half of a page. the code achieves its small size without additional calls through the use of a sequencing table. the table is a list of procedures that must be called in order. the table uses an addwf pcl,f instruction, effectively a computed goto, to sequence to the next procedure. however the addwf pcl,f instruction yields an 8 bit address, forcing the code to reside in the first 256 addresses of a page.
pic12c5xx ds40139e-page 30 1999 microchip technology inc. figure 7-1: block diagram of gpio6 (sda line) figure 7-2: block diagram of gpio7 (scl line) en d en qd ck reset ck q databus write output latch to 24l00 sda schmitt trigger ltchpin input latch read v dd pad gpio gpio en d en qd ck ck q databus write to 2 4 l c 0 0 s c l ltchpin read v dd pad schmitt trigger gpio gpio
1999 microchip technology inc. ds40139e-page 31 pic12c5xx 7.0.2 serial clock this scl input is used to synchronize the data transfer from and to the device. 7.1 bus characteristics the following bus protocol is to be used with the eeprom data memory. ? data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 7-3). 7.1.1 bus not busy (a) both data and clock lines remain high. 7.1.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 7.1.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 7.1.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited. 7.1.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition (figure 7-4). note: acknowledge bits are not generated if an internal programming cycle is in progress.
pic12c5xx ds40139e-page 32 1999 microchip technology inc. figure 7-3: data transfer sequence on the serial bus figure 7-4: acknowledge timing (a) (b) (c) (d) (a) (c) scl sda start condition address or acknowledge valid data allowed to change stop condition scl 9 8 7 6 5 4 3 2 1123 transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. data from transmitter data from transmitter sda acknowledge bit 7.2 device addressing after generating a start condition, the bus master transmits a control byte consisting of a slave address and a read/write bit that indicates what type of opera- tion is to be performed. the slave address consists of a 4-bit device code (1010) followed by three don't care bits. the last bit of the control byte determines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected. (figure 7-5). the bus is monitored for its cor- responding slave address all the time. it generates an acknowledge bit if the slave address was true and it is not in a programming mode. figure 7-5: control byte format 1010xxx sack r/w device select bits dont care bits slave address acknowledge bit start bit read/write bit
1999 microchip technology inc. ds40139e-page 33 pic12c5xx 7.3 write operations 7.3.1 byte write following the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the r/w bit (which is a logic low) are placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer. only the lower four address bits are used by the device, and the upper four bits are dont cares. the address byte is acknowledgeable and the master device will then transmit the data word to be written into the addressed memory location. the mem- ory acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time will not generate acknowledge sig- nals (figure 7-7). after a byte write command, the inter- nal address counter will not be incremented and will point to the same address location that was just written. if a stop bit is transmitted to the device at any point in the write command sequence before the entire sequence is complete, then the command will abort and no data will be written. if more than 8 data bits are transmitted before the stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. if more than one data byte is transmitted to the device and a stop bit is sent before a full eight data bits have been transmitted, then the write command will abort and no data will be written. the eeprom memory employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below minimum vdd. byte write operations must be preceded and immedi- ately followed by a bus not busy bus cycle where both sda and scl are held high. 7.4 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master send- ing a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if no ack is returned, then the start bit and control byte must be re-sent. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 7-6 for flow diagram. figure 7-6: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes figure 7-7: byte write s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k 10 x 10 x xx x = dont care bit xxx 0
pic12c5xx ds40139e-page 34 1999 microchip technology inc. 7.5 read operations read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 7.5.1 current address read it contains an address counter that maintains the address of the last word accessed, internally incre- mented by one. therefore, if the previous read access was to address n, the next current address read opera- tion would access data from address n + 1. upon receipt of the slave address with the r/w bit set to one, the device issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the device discontinues transmission (figure 7-8). 7.5.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the device as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. it will then issue an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does gen- erate a stop condition and the device discontinues transmission (figure 7-9). after this command, the internal address counter will point to the address loca- tion following the one that was just read. 7.5.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the device transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the device to transmit the next sequentially addressed 8-bit word (figure 7-10). to provide sequential reads, it contains an internal address pointer which is incremented by one at the completion of each read operation. this address pointer allows the entire memory contents to be serially read during one operation. figure 7-8: current address read figure 7-9: random read figure 7-10: sequential read bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k 11 00xxx1 x = dont care bit p bus activity master sda line bus activity s t a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k x xxx s1 1 00xxx0 s11 00xxx1 x = dont care bit p bus activity master sda line bus activity s t o p control byte a c k n o a c k data n data n + 1 data n + 2 data n + x a c k a c k a c k
1999 microchip technology inc. ds40139e-page 35 pic12c5xx 8.0 special features of the cpu what sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. the pic12c5xx family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these features are: ? oscillator selection ? reset - power-on reset (por) -device reset timer (drt) - wake-up from sleep on pin change ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming the pic12c5xx has a watchdog timer which can be shut off only through configuration bit wdte. it runs off of its own rc oscillator for added reliability. if using xt or lp selectable oscillator options, there is always an 18 ms (nominal) delay provided by the device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. if using intrc or extrc there is an 18 ms delay only on v dd power-up. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through a change on input pins or through a watchdog timer time-out. several oscillator options are also made available to allow the part to fit the application, including an internal 4 mhz oscillator. the extrc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. 8.1 configuration bits the pic12c5xx configuration word consists of 12 bits. configuration bits can be programmed to select various device configurations. two bits are for the selection of the oscillator type, one bit is the watchdog timer enable bit, and one bit is the mclr enable bit. figure 8-1: configuration word for pic12c5xx mclre cp wdte fosc1 fosc0 register: config address (1) :fffh bit1110987654321 bit0 bit 11-5: unimplemented bit 4: mclre: mclr enable bit. 1 = mclr pin enabled 0 = mclr tied to v dd , (internally) bit 3: cp: code protection bit. 1 = code protection off 0 = code protection on bit 2: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0: oscillator selection bits 11 = extrc - external rc oscillator 10 = intrc - internal rc oscillator 01 = xt oscillator 00 = lp oscillator note 1: refer to the pic12c5xx programming specifications to determine how to access the configuration word. this register is not user addressable during device operation.
pic12c5xx ds40139e-page 36 1999 microchip technology inc. 8.2 oscillator configurations 8.2.1 oscillator types the pic12c5xx can be operated in four different oscillator modes. the user can program two configuration bits (fosc1:fosc0) to select one of these four modes: ?lp: low power crystal ? xt: crystal/resonator ? intrc: internal 4 mhz oscillator ? extrc: external resistor/capacitor 8.2.2 crystal oscillator / ceramic resonators in xt or lp modes, a crystal or ceramic resonator is connected to the gp5/osc1/clkin and gp4/osc2 pins to establish oscillation (figure 8-2). the pic12c5xx oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in xt or lp modes, the device can have an external clock source drive the gp5/ osc1/clkin pin (figure 8-3). figure 8-2: crystal operation (or ceramic resonator) (xt or lp osc configuration) figure 8-3: external clock input operation (xt or lp osc configuration) note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf approximate value = 10 m w . c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic12c5xx clock from ext. system osc1 osc2 open pic12c5xx table 8-1: capacitor selection for ceramic resonators - pic12c5xx table 8-2: capacitor selection for crystal oscillator - pic12c5xx osc type resonator freq cap. range c1 cap. range c2 xt 4.0 mhz 30 pf 30 pf these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. osc type resonator freq cap.range c1 cap. range c2 lp 32 khz (1) 15 pf 15 pf xt 200 khz 1 mhz 4 mhz 47-68 pf 15 pf 15 pf 47-68 pf 15 pf 15 pf note 1: for v dd > 4.5v, c1 = c2 ? 30 pf is recommended. these values are for design guidance only. rs may be required to avoid overdriving crystals with low drive level specification. since each crystal has its own characteristics, the user should consult the crys- tal manufacturer for appropriate values of external components.
1999 microchip technology inc. ds40139e-page 37 pic12c5xx 8.2.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crystal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. figure 8-4 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k w resistor provides the negative feedback for stability. the 10 k w potentiometers bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 8-4: external parallel resonant crystal oscillator circuit figure 8-5 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator circuit. the 330 w resistors provide the negative feedback to bias the inverters in their linear region. figure 8-5: external series resonant crystal oscillator circuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 clkin to o t h e r devices pic12c5xx 330 74as04 74as04 clkin to o t h e r devices xtal 330 74as04 0.1 m f pic12c5xx 8.2.4 external rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (rext) and capacitor (cext) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low cext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 8-6 shows how the r/c combination is connected to the pic12c5xx. for rext values below 2.2 k w , the oscillator operation may become unstable, or stop completely. for very high rext values (e.g., 1 m w ) the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping rext between 3 k w and 100 k w . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. the electrical specifications sections show rc frequency variation from part to part due to normal process variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). also, see the electrical specifications sections for variation of oscillator frequency due to v dd for given rext/cext values as well as frequency variation due to operating temperature for given r, c, and v dd values. figure 8-6: external rc oscillator mode v dd rext cext v ss osc1 internal clock n pic12c5xx
pic12c5xx ds40139e-page 38 1999 microchip technology inc. 8.2.5 internal 4 mhz rc oscillator the internal rc oscillator provides a fixed 4 mhz (nom- inal) system clock at vdd = 5v and 25c, see electri- cal specifications section for information on variation over voltage and temperature. in addition, a calibration instruction is programmed into the top of memory which contains the calibration value for the internal rc oscillator. this location is never code protected regardless of the code protect settings. this value is programmed as a movlw xx instruction where xx is the calibration value, and is placed at the reset vector. this will load the w register with the calibration value upon reset and the pc will then roll over to the users program at address 0x000. the user then has the option of writing the value to the osccal register (05h) or ignoring it. osccal, when written to with the calibration value, will trim the internal oscillator to remove process variation from the oscillator frequency. . for the pic12c508a, pic12c509a, pic12ce518, pic12ce519, and pic12cr509a, bits <7:2>, cal5- cal0 are used for calibration. adjusting cal5-0 from 000000 to 111111 yields a higher clock speed. note that bits 1 and 0 of osccal are unimplemented and should be written as 0 when modifying osccal for compatibility with future devices. for the pic12c508 and pic12c509, the upper 4 bits of the register are used. writing a larger value in this loca- tion yields a higher clock speed. 8.3 reset the device differentiates between various kinds of reset: a) power on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) wdt time-out reset during normal operation e) wdt time-out reset during sleep f) wake-up from sleep on pin change note: please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part. so it can be repro- grammed correctly later. some registers are not reset in any way; they are unknown on por and unchanged in any other reset. most other registers are reset to reset state on power- on reset (por), mclr , wdt or wake-up on pin change reset during normal operation. they are not affected by a wdt reset during sleep or mclr reset during sleep, since these resets are viewed as resumption of normal operation. the exceptions to this are to , pd , and gpwuf bits. they are set or cleared differently in different reset situations. these bits are used in software to determine the nature of reset. see table 8-3 for a full description of reset states of all registers.
1999 microchip technology inc. ds40139e-page 39 pic12c5xx table 8-3: reset conditions for registers table 8-4: reset condition for special registers register address power-on reset mclr reset wdt time-out wake-up on pin change w (pic12c508/509) qqqq xxxx (1) qqqq uuuu (1) w (pic12c508a/509a/ pic12ce518/519/ pic12ce509a) qqqq qqxx (1) qqqq qquu (1) indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pc 02h 1111 1111 1111 1111 status 03h 0001 1xxx q00q quuu (2,3) fsr (pic12c508/ pic12c508a/ pic12ce518) 04h 111x xxxx 111u uuuu fsr (pic12c509/ pic12c509a/ pic12ce519/ pic12cr509a) 04h 110x xxxx 11uu uuuu osccal (pic12c508/509) 05h 0111 ---- uuuu ---- osccal (pic12c508a/509a/ pic12ce518/512/ pic12cr509a) 05h 1000 00-- uuuu uu-- gpio (pic12c508/pic12c509/ pic12c508a/ pic12c509a/ pic12cr509a) 06h --xx xxxx --uu uuuu gpio (pic12ce518/ pic12ce519) 06h 11xx xxxx 11uu uuuu option 1111 1111 1111 1111 tris --11 1111 --11 1111 legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0, q = value depends on condition. note 1: bits <7:2> of w register contain oscillator calibration values due to movlw xx instruction at top of memory. note 2: see table 8-7 for reset value for specific conditions note 3: if reset was due to wake-up on pin change, then bit 7 = 1. all other resets will cause bit 7 = 0. status addr: 03h pcl addr: 02h power on reset 0001 1xxx 1111 1111 mclr reset during normal operation 000u uuuu 1111 1111 mclr reset during sleep 0001 0uuu 1111 1111 wdt reset during sleep 0000 0uuu 1111 1111 wdt reset normal operation 0000 uuuu 1111 1111 wake-up from sleep on pin change 1001 0uuu 1111 1111 legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0.
pic12c5xx ds40139e-page 40 1999 microchip technology inc. 8.3.1 mclr enable this configuration bit when unprogrammed (left in the 1 state) enables the external mclr function. when programmed, the mclr function is tied to the internal v dd , and the pin is assigned to be a gpio. see figure 8-7. when pin gp3/mclr /v pp is configured as mclr , the internal pull-up is always on. figure 8-7: mclr select 8.4 p ower-on reset ( por) the pic12c5xx family incorporates on-chip power- on reset (por) circuitry which provides an internal chip reset for most power-up situations. the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper opera- tion. to take advantage of the internal por, program the gp3/mclr /v pp pin as mclr and tie through a resistor to v dd or program the pin as gp3. an internal weak pull-up resistor is implemented using a transistor. refer to table 11-1 for the pull-up resistor ranges. this will eliminate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is specified. see electrical specifications for details. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating parameters are met. a simplified block diagram of the on-chip power-on reset circuit is shown in figure 8-8. gp3/mclr /v pp mclre internal mclr weak pull-up the power-on reset circuit and the device reset timer (section 8.5) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on- chip reset signal. a power-up example where mclr is held low is shown in figure 8-9. v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 8-10, the on-chip power-on reset feature is being used (mclr and v dd are tied together or the pin is programmed to be gp3.). the v dd is stable before the start-up timer times out and there is no problem in getting a proper reset. however, figure 8- 11 depicts a problem situation where v dd rises too slowly. the time between when the drt senses that mclr is high and when m clr (and v dd ) actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip is, therefore, not guaranteed to function correctly. for such situations, we recommend that external rc circuits be used to achieve longer por delay times (figure 8-10). for additional information refer to application notes power-up considerations - an522 and power-up trouble shooting - an607. note: when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, tempera- ture, etc.) must be meet to ensure opera- tion. if these conditions are not met, the device must be held in reset until the oper- ating conditions are met.
1999 microchip technology inc. ds40139e-page 41 pic12c5xx figure 8-8: simplified block diagram of on-chip reset circuit figure 8-9: time-out sequence on power-up (mclr pulled low) figure 8-10: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time sq r q v dd gp3/m clr /v pp power-up detect on-chip drt osc por (power-on reset) wdt time-out reset chip reset 8-bit asynch ripple counter (start-up timer) mclre sleep pin change wake-up on pin change v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt
pic12c5xx ds40139e-page 42 1999 microchip technology inc. figure 8-11: time-out sequence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset t drt v1 when v dd rises slowly, the t drt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 3 v dd min. 8.5 device reset timer (drt) in the pic12c5xx, drt runs from reset and varies based on oscillator selection (see table 8-5.) the drt operates on an internal rc oscillator. the processor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd min., and for the oscillator to stabilize. oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the device in a reset condition for approximately 18 ms after mclr has reached a logic high (v ih mclr ) level. thus, programming gp3/mclr /v pp as mclr and using an external rc network connected to the mclr input is not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the gp3/ mclr /v pp pin as a general purpose input. the device reset time delay will vary from chip to chip due to v dd , temperature, and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out. this is particularly important for applications using the wdt to wake from sleep mode automatically. 8.6 w atchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator which does not require any external components. this rc oscillator is separate from the external rc oscillator of the gp5/osc1/clkin pin and the internal 4 mhz oscillator. that means that the wdt will run even if the main processor clock has been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset generates a device reset. the to bit (status<4>) will be cleared upon a watchdog timer reset. the wdt can be permanently disabled by programming the configuration bit wdte as a '0' (section 8.1). refer to the pic12c5xx programming specifications to determine how to access the configuration word. table 8-5: drt (device reset timer period) oscillator configuration por reset subsequent resets intrc & extrc 18 ms (typical) 300 s (typical) xt & lp 18 ms (typical) 18 ms (typical)
1999 microchip technology inc. ds40139e-page 43 pic12c5xx 8.6.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writing to the option register. thus, a time-out period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to- part process variations (see dc specs). under worst case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt time-out occurs. 8.6.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. figure 8-12: watchdog timer block diagram table 8-6: summary of registers associated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: shaded boxes = not used by watchdog timer, = unimplemented, read as '0', u = unchanged 1 0 1 0 from timer0 clock source (figure 8-5) to timer0 (figure 8-4) postscaler wdt enable configuration bit psa wdt time-out ps2:ps0 psa mux 8 - to - 1 mux postscaler m u x watchdog timer note: t0cs, t0se, psa, ps2:ps0 are bits in the option register.
pic12c5xx ds40139e-page 44 1999 microchip technology inc. 8.7 time-out sequence , p ower down , and wake-up from sleep s tatus bits ( to / pd /gpwu f ) the to , p d , and gpwuf bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr or watchdog timer (wdt) reset. 8.8 reset on brown-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic12c5xx devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in figure 8-13 , figure 8-14 and figure 8-15 figure 8-13: brown-out protection circuit 1 table 8-7: to /pd /gpwuf status after reset gpwuf to pd reset caused by 0 0 0 wdt wake-up from sleep 0 0 u wdt time-out (not from sleep) 010mclr wake-up from sleep 011power-up 0uumclr not during sleep 1 1 0 wake-up from sleep on pin change legend: u = unchanged note 1: the to , pd , and gpwuf bits maintain their status (u) until a reset occurs. a low- pulse on the mclr input does not change the to , pd , and gpwuf status bits. this circuit will activate reset when v dd goes below vz + 0.7v (where vz = zener voltage). *refer to figure 8-7 and table 11-1 for internal weak pull-up on mclr. 33k 10k 40k* mclr pic12c5xx v dd q1 v dd v dd figure 8-14: brown-out protection circuit 2 figure 8-15: brown-out protection circuit 3 this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: *refer to figure 8-7 and table 11-1 for internal weak pull-up on mclr. v dd ? r1 r1 + r2 = 0.7v r2 40k* mclr pic12c5xx r1 q1 v dd v dd v dd this brown-out protection circuit employs microchip technologys mcp809 microcontroller supervisor. the mcp8xx and mcp1xx family of supervisors provide push-pull and open collector outputs with both high and low active reset pins. there are 7 different trip point selections to accomodate 5v and 3v systems. mclr pic12c5xx v dd v dd vss rst mcp809 v dd bypass capacitor
1999 microchip technology inc. ds40139e-page 45 pic12c5xx 8.9 power-down mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 8.9.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit (status<4>) is set, the pd bit (status<3>) is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, driving low, or hi-impedance). it should be noted that a reset generated by a wdt time-out does not drive the mclr pin low. for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the gp3/ mclr /v pp pin must be at a logic high level (v ihmc ) if mclr is enabled. 8.9.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. an external reset input on gp3/mclr /v pp pin, when configured as mclr . 2. a watchdog timer time-out reset (if wdt was enabled). 3. a change on input pin gp0, gp1, or gp3/ mclr /v pp when wake-up on change is enabled. these events cause a device reset. the to , p d , and gpwuf bits can be used to determine the cause of device reset. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the gpwuf bit indicates a change in state while in sleep at pins gp0, gp1, or gp3 (since the last time there was a file or bit operation on gp port). the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. caution: right before entering sleep, read the input pins. when in sleep, wake up occurs when the values at the pins change from the state they were in at the last reading. if a wake-up on change occurs and the pins are not read before reentering sleep, a wake up will occur immediately even if no pins change while in sleep mode. 8.10 p rogram verification/code protection if the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. the first 64 locations can be read by the pic12c5xx regardless of the code protection bit setting. the last memory location cannot be read if code pro- tection is enabled on the pic12c508/509. the last memory location can be read regardless of the code protection bit setting on the pic12c508a/509a/ cr509a/ce518/ce519. 8.11 id locations four memory locations are designated as id locations where the user can store checksum or other code- identification numbers. these locations are not accessible during normal execution but are readable and writable during program/verify. use only the lower 4 bits of the id locations and always program the upper 8 bits as '0's.
pic12c5xx ds40139e-page 46 1999 microchip technology inc. 8.12 in-circuit serial programming the pic12c5xx microcontrollers with eprom pro- gram memory can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows cus- tomers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be pro- grammed. the device is placed into a program/verify mode by holding the gp1 and gp0 pins low while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). gp1 becomes the programming clock and gp0 becomes the programming data. both gp1 and gp0 are schmitt trigger inputs in this mode. after reset, a 6-bit command is then supplied to the device. depending on the command, 14-bits of pro- gram data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic12c5xx programming specifications. a typical in-circuit serial programming connection is shown in figure 8-16. figure 8-16: typical in-circuit serial programming connection external connector signals to n o r m a l connections to n o r m a l connections pic12c5xx v dd v ss mclr /v pp gp1 gp0 +5v 0v v pp clk data i/o v dd
1999 microchip technology inc. ds40139e-page 47 pic12c5xx 9.0 instruction set summary each pic12c5xx instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. the pic12c5xx instruction set summary in table 9-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. table 9-1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. the file register designator is used to specify which one of the 32 file registers is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is '0', the result is placed in the w register. if 'd' is '1', the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. table 9-1: opcode field descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in file register 'f') default is d = 1 label label name tos top of stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents ? assigned to < > register bit field ? in the set of i talics user defined term (font is courier) all instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 m s. figure 9-1 shows the three general formats that the instructions can have. all examples in the figure use the following format to represent a hexadecimal number: 0xhhh where 'h' signifies a hexadecimal digit. figure 9-1: general format for instructions byte-oriented file register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit file register address bit-oriented file register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit file register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations - goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value
pic12c5xx ds40139e-page 48 1999 microchip technology inc. table 9-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f,d f,d f C f, d f, d f, d f, d f, d f, d f, d f C f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z none z none z z none none c c c,dc,z none z 1,2,4 2,4 4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2,4 2,4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k k k k k C k C f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none to , pd none z none none none to , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a '0' by any instruction that writes to the pc except for goto . (section 4.6) 2: when an i/o register is modified as a function of itself (e.g. movf gpio, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: the instruction tris f , where f = 6 causes the contents of the w register to be written to the tristate latches of gpio. a '1' forces the pin to a hi-impedance state and disables the output buffers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to tmr0).
1999 microchip technology inc. ds40139e-page 49 pic12c5xx addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 31 d ? [0,1] operation: (w) + (f) ? (dest) status affected: c, dc, z encoding: 0001 11df ffff description: add the contents of the w register and register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is '1' the result is stored back in register 'f' . words: 1 cycles: 1 example: addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w).and. (k) ? (w) status affected: z encoding: 1110 kkkk kkkk description: the contents of the w register are anded with the eight-bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 example: andlw 0x5f before instruction w= 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 31 d ? [0,1] operation: (w) .and. (f) ? (dest) status affected: z encoding: 0001 01df ffff description: the contents of the w register are anded with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is '1' the result is stored back in register 'f' . words: 1 cycles: 1 example: andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 31 0 b 7 operation: 0 ? (f) status affected: none encoding: 0100 bbbf ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 example: bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47
pic12c5xx ds40139e-page 50 1999 microchip technology inc. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 31 0 b 7 operation: 1 ? (f) status affected: none encoding: 0101 bbbf ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 example: bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 31 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 0110 bbbf ffff description: if bit 'b' in register 'f' is 0 then the next instruction is skipped. if bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and an nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example: here false true btfsc goto ? ? ? flag,1 process_code before instruction pc = address (here) after instruction if flag<1>=0, pc = address (true) ; if flag<1>=1, pc = address (false) btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 31 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 0111 bbbf ffff description: if bit 'b' in register 'f' is '1' then the next instruction is skipped. if bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and an nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example: here btfss flag,1 false goto process_code true before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (false) ; if flag<1>=1, pc = address (true)
1999 microchip technology inc. ds40139e-page 51 pic12c5xx call subroutine call syntax: [ label ] call k operands: 0 k 255 operation: (pc) + 1 ? top of stack; k ? pc<7:0>; (status<6:5>) ? pc<10:9>; 0 ? pc<8> status affected: none encoding: 1001 kkkk kkkk description: subroutine call. first, return address (pc+1) is pushed onto the stack. the eight bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from sta- tus<6:5>, pc<8> is cleared. call is a two cycle instruction. words: 1 cycles: 2 example: here call there before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 1) clrf clear f syntax: [ label ] clrf f operands: 0 f 31 operation: 00h ? (f); 1 ? z status affected: z encoding: 0000 011f ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 example: clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w); 1 ? z status affected: z encoding: 0000 0100 0000 description: the w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example: clrw before instruction w = 0x5a after instruction w = 0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt; 0 ? wdt prescaler (if assigned); 1 ? to; 1 ? pd status affected: to , pd encoding: 0000 0000 0100 description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. words: 1 cycles: 1 example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescale = 0 to =1 pd =1
pic12c5xx ds40139e-page 52 1999 microchip technology inc. comf complement f syntax: [ label ] comf f,d operands: 0 f 31 d ? [0,1] operation: (f ) ? (dest) status affected: z encoding: 0010 01df ffff description: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w=0xec decf decrement f syntax: [ label ] decf f,d operands: 0 f 31 d ? [0,1] operation: (f) C 1 ? (dest) status affected: z encoding: 0000 11df ffff description: decrement register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 31 d ? [0,1] operation: (f) C 1 ? d; skip if result = 0 status affected: none encoding: 0010 11df ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded and an nop is executed instead mak- ing it a two cycle instruction. words: 1 cycles: 1(2) example: here decfsz cnt, 1 goto loop continue ? ? ? before instruction pc = address (here) after instruction cnt = cnt - 1; if cnt = 0, pc = address (continue) ; if cnt 1 0, pc = address (here+1) goto unconditional branch syntax: [ label ] goto k operands: 0 k 511 operation: k ? pc<8:0>; status<6:5> ? pc<10:9> status affected: none encoding: 101k kkkk kkkk description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two cycle instruction. words: 1 cycles: 2 example: goto there after instruction pc = address (there)
1999 microchip technology inc. ds40139e-page 53 pic12c5xx incf increment f syntax: [ label ] incf f,d operands: 0 f 31 d ? [0,1] operation: (f) + 1 ? (dest) status affected: z encoding: 0010 10df ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 31 d ? [0,1] operation: (f) + 1 ? (dest), skip if result = 0 status affected: none encoding: 0011 11df ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, then the next instruc- tion, which is already fetched, is dis- carded and an nop is executed instead making it a two cycle instruc- tion. words: 1 cycles: 1(2) example: here incfsz cnt, 1 goto loop continue ? ? ? before instruction pc = address (here) after instruction cnt = cnt + 1; if cnt = 0, pc = address (continue) ; if cnt 1 0, pc = address (here +1) iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. (k) ? (w) status affected: z encoding: 1101 kkkk kkkk description: the contents of the w register are ored with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: iorlw 0x35 before instruction w = 0x9a after instruction w= 0xbf z=0 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 31 d ? [0,1] operation: (w).or. (f) ? (dest) status affected: z encoding: 0001 00df ffff description: inclusive or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=0
pic12c5xx ds40139e-page 54 1999 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 f 31 d ? [0,1] operation: (f) ? (dest) status affected: z encoding: 0010 00df ffff description: the contents of register 'f' is moved to destination 'd'. if 'd' is 0, destination is the w register. if 'd' is 1, the destination is file register 'f'. 'd' is 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k ? (w) status affected: none encoding: 1100 kkkk kkkk description: the eight bit literal 'k' is loaded into the w register. the dont cares will assem- ble as 0s. words: 1 cycles: 1 example: movlw 0x5a after instruction w= 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 f 31 operation: (w) ? (f) status affected: none encoding: 0000 001f ffff description: move data from the w register to regis- ter 'f' . words: 1 cycles: 1 example: movwf temp_reg before instruction temp_reg = 0xff w = 0x4f after instruction temp_reg = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 0000 0000 description: no operation. words: 1 cycles: 1 example: nop
1999 microchip technology inc. ds40139e-page 55 pic12c5xx option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 0000 0000 0010 description: the content of the w register is loaded into the option register. words: 1 cycles: 1 example option before instruction w=0x07 after instruction option = 0x07 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k ? (w); tos ? pc status affected: none encoding: 1000 kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. words: 1 cycles: 2 example: table call table ;w contains ;table offset ;value. ? ;w now has table ? ;value. ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w= 0x07 after instruction w= value of k8 rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 31 d ? [0,1] operation: see description below status affected: c encoding: 0011 01df ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 1100 1100 c= 1 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 31 d ? [0,1] operation: see description below status affected: c encoding: 0011 00df ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: rrf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 0111 0011 c= 0 c register 'f' c register 'f'
pic12c5xx ds40139e-page 56 1999 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt; 0 ? wdt prescaler; 1 ? to ; 0 ? pd status affected: to , pd , gpwuf encoding: 0000 0000 0011 description: time-out status bit (to ) is set. the power down status bit (pd ) is cleared. gpwuf is unaffected. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see sec- tion on sleep for more details. words: 1 cycles: 1 example: sleep subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 31 d ? [0,1] operation: (f) C (w) ? ( dest) status affected: c, dc, z encoding: 0000 10df ffff description: subtract (2s complement method) the w register from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example 1 : subwf reg1, 1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1 ; result is positive e xample 2 : before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1 ; result is zero e xample 3 : before instruction reg1 = 1 w=2 c=? after instruction reg1 = ff w=2 c = 0 ; result is negative
1999 microchip technology inc. ds40139e-page 57 pic12c5xx swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 31 d ? [0,1] operation: (f<3:0>) ? (dest<7:4>); (f<7:4>) ? (dest<3:0>) status affected: none encoding: 0011 10df ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0 the result is placed in w register. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 example swapf reg1, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: f = 6 operation: (w) ? tris register f status affected: none encoding: 0000 0000 0fff description: tris register 'f' (f = 6) is loaded with the contents of the w register words: 1 cycles: 1 example tris gpio before instruction w=0xa5 after instruction tris = 0xa5 note: f = 6 for pic12c5xx only. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ? ( w) status affected: z encoding: 1111 kkkk kkkk description: the contents of the w register are xored with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: xorlw 0xaf before instruction w= 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 31 d ? [0,1] operation: (w) .xor. (f) ? ( dest) status affected: z encoding: 0001 10df ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg,1 before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5
pic12c5xx ds40139e-page 58 1999 microchip technology inc. notes:
1999 microchip technology inc. ds40139e-page 59 pic12c5xx 10.0 development support 10.1 development tools the picmicro a microcontrollers are supported with a full range of hardware and software development tools: ? mplab?-ice real-time in-circuit emulator ? icepic ? low-cost pic16c5x and pic16cxxx in-circuit emulator ?pro mate a ii universal programmer ? picstart a plus entry-level prototype programmer ? simice ? picdem-1 low-cost demonstration board ? picdem-2 low-cost demonstration board ? picdem-3 low-cost demonstration board ?mpasm assembler ? mplab ? sim software simulator ? mplab-c17 (c compiler) ? fuzzy logic development system ( fuzzy tech a - mp) ?k ee l oq ? evaluation kits and programmer 10.2 mplab-ice: high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro a microcontrollers (mcus). mplab-ice is supplied with the mplab integrated development environment (ide), which allows editing, make and download, and source debugging from a single envi- ronment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support all new microchip micro- controllers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc compatible 386 (and higher) machine platform and microsoft windows a 3.x or windows 95 environment were chosen to best make these features available to you, the end user. mplab-ice is available in two versions. mplab-ice 1000 is a basic, low-cost emulator system with simple trace capabilities. it shares processor mod- ules with the mplab-ice 2000. this is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. both systems will operate across the entire operating speed range of the picmicro a mcu. 10.3 icepic: low-cost picmicro a in-circuit emulator icepic is a low-cost in-circuit emulator solution for the microchip pic12cxxx, pic16c5x and pic16cxxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 386 through pentium ? based machines under windows 3.x, windows 95, or win- dows nt environment. icepic features real time, non- intrusive emulation. 10.4 pro mate ii: universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices. it can also set configuration and code-protect bits in this mode. 10.5 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus is not recommended for production programming. picstart plus supports all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices with up to 40 pins. larger pin count devices such as the pic16c923, pic16c924 and pic17c756 may be sup- ported with an adapter socket. picstart plus is ce compliant.
pic12c5xx ds40139e-page 60 1999 microchip technology inc. 10.6 simice entry-level hardware simulator simice is an entry-level hardware development sys- tem designed to operate in a pc-based environment with microchips simulator mplab?-sim. both sim- ice and mplab-sim run under microchip technol- ogys mplab integrated development environment (ide) software. specifically, simice provides hardware simulation for microchips pic12c5xx, pic12ce5xx, and pic16c5x families of picmicro a 8-bit microcon- trollers. simice works in conjunction with mplab-sim to provide non-real-time i/o port emulation. simice enables a developer to run simulator code for driving the target system. in addition, the target system can provide input to the simulator code. this capability allows for simple and interactive debugging without having to manually generate mplab-sim stimulus files. simice is a valuable debugging tool for entry- level system development. 10.7 picdem-1 low-cost picmicro a demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and download the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 10.8 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 10.9 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals.
1999 microchip technology inc. ds40139e-page 61 pic12c5xx 10.10 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows based application which contains: ? a full featured editor ? three operating modes -editor -emulator - simulator ? a project manager ? customizable tool bar and key mapping ? a status bar with project information ? extensive on-line help mplab allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro a tools (automatically updates all project information) ? debug using: - source files - absolute listing file the ability to use mplab with microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 10.11 assembler (mpasm) the mpasm universal macro assembler is a pc- hosted symbolic assembler. it supports all microcon- troller series including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers. mpasm allows full symbolic debugging from mplab- ice, microchips universal emulator system. mpasm has the following features to assist in develop- ing software for specific use applications. ? provides translation of assembler source code to object code for all microchip microcontrollers. ? macro assembly capability. ? produces all the files (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. ? supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the picmicro a . directives are helpful in making the development of your assemble source code shorter and more maintainable. 10.12 software simulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the picmicro a series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mpasm. the software simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 10.13 mplab-c17 compiler the mplab-c17 code development system is a complete ansi c compiler and integrated develop- ment environment for microchips pic17cxxx family of microcontrollers. the compiler provides powerful inte- gration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display. 10.14 fuzzy logic development system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzy lab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 10.15 seeval a evaluation and programming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can significantly reduce time-to-market and result in an optimized system.
pic12c5xx ds40139e-page 62 1999 microchip technology inc. 10.16 k ee l oq a evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
1999 microchip technology inc. ds40139e-page 63 pic12c5xx table 10-1: development tools from microchip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c7xx 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products mplab ?-ice icepic ? low-cost in-circuit emulator software tools mplab ? integrated development environment mplab ? c17* compiler fuzzy tech a -mp explorer/edition fuzzy logic dev. tool total endurance ? software model programmer s picstart a plus low-cost universal dev. kit pro mate a ii universal programmer keeloq a programmer demo boards seeval a designers kit simice picdem-14a picdem-1 picdem-2 picdem-3 k ee l oq ? evaluation kit k ee l oq transponder kit
pic12c5xx ds40139e-page 64 1999 microchip technology inc. notes:
1999 microchip technology inc. ds40139e-page 65 pic12c5xx 11.0 electrical characteristics - pic12c508/pic12c509 absolute maximum ratings? ambient temperature under bias ................................................................................................. .......... C40c to +125c storage temperature ............................................................................................................ ................. C65c to +150c voltage on v dd with respect to v ss .................................................................................................................0 to +7.5 v voltage on mclr with respect to v ss ...............................................................................................................0 to +14 v voltage on all other pins with respect to v ss ............................................................................... C0.6 v to (v dd + 0.6 v) total power dissipation (1) ............................................................................................................................... .....700 mw max. current out of v ss pin ........................................................................................................................... .......200 ma max. current into v dd pin ........................................................................................................................... ..........150 ma input clamp current, i ik (v i < 0 or v i > v dd ) .................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma max. output current sunk by any i/o pin........................................................................................ ........................25 ma max. output current sourced by any i/o pin..................................................................................... ......................25 ma max. output current sourced by i/o port (gpio) ................................................................................. ................100 ma max. output current sunk by i/o port (gpio )................................................................................... ...................100 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic12c5xx ds40139e-page 66 1999 microchip technology inc. 11.1 dc characteristics: pic12c508/509 (commercial, industrial, extended) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) parm no. characteristic sym min typ (1) max units conditions d001 supply voltage v dd 2.5 3.0 5.5 5.5 v v f osc = dc to 4 mhz (commercial/ industrial) f osc = dc to 4 mhz (extended) d002 ram data retention voltag e (2) v dr 1.5* v device in sleep mode d003 v dd start voltage to ensure power-on reset v por v ss v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05 * v/ms see section on power-on reset for details d010 d010c d010a supply current (3) i dd .78 1.1 10 14 14 2.4 2.4 27 35 35 ma ma m a m a a xt and extrc options (4) f osc = 4 mhz, v dd = 5.5v intrc option f osc = 4 mhz, v dd = 5.5v lp o ption , commercial temperature f osc = 32 khz, v dd = 3.0v, wdt disabled lp o ption , industrial temperature f osc = 32 khz, v dd = 3.0v, wdt disabled lp o ption , extended temperature f osc = 32 khz, v dd = 3.0v, wdt disabled d020 d021 d021b power-down current (5) i pd 0.25 0.25 2 4 5 18 m a m a m a v dd = 3.0v, commercial wdt disabled v dd = 3.0v, industrial wdt disabled v dd = 3.0v, extended wdt disabled d022 d i wdt 3.75 3.75 3.75 8 9 14 m a m a m a v dd = 3.0v, commercial v dd = 3.0v, industrial v dd = 3.0v, extended * these parameters are characterized but not tested. note 1: data in the typical (typ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in kohm. 5: the power down current in sleep mode does not depend on the oscillator type. power down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss .
1999 microchip technology inc. ds40139e-page 67 pic12c5xx 11.2 dc characteristics: pic12c508/509 (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 0c t a +70c (commercial) C40c t a +85c (industrial) C40c t a +125c (extended) operating voltage v dd range as described in dc spec section 11.1 and section 11.2. param no. characteristic sym min typ? max units conditions input low voltage i/o ports v il - d030 with ttl buffer v ss -0.8vv4.5 < v dd 5.5v -0.15v dd votherwise d031 with schmitt trigger buffer v ss -0.15v dd v d032 mclr , gp2/t0cki (in extrc mode) v ss -0.15v dd v d033 osc1 (extrc) (1) v ss -0.15v dd d033 osc1 (in xt and lp) v ss -0.3v dd vnote1 input high voltage i/o ports v ih - d040 with ttl buffer v ss 2.0v - v dd v4.5 v dd 5.5v d040a 0.25v dd + 0.8v -v dd votherwise d041 with schmitt trigger buffer 0.85v dd -v dd v for entire v dd range d042 mclr /gp2/t0cki 0.85v dd -v dd v d042a osc1 (xt and lp) 0.7v dd -v dd vnote1 d043 osc1 (in extrc mode) 0.85v dd -v dd v d070 gpio weak pull-up current i pur 50 250 400 m av dd = 5v, v pin = v ss input leakage current (2, 3) for v dd 5.5v d060 i/o ports i il -1 0.5 + 1 m a vss v pin v dd , pin at hi-impedance d061 mclr , gp2/t0cki 20 130 0.5 250 +5 m a m a v pin = v ss + 0.25v (2) v pin = v dd d063 osc1 -3 0.5 +3 m a vss v pin v dd , xt and lp options output low voltage d080 i/o ports/clkout v ol --0.6vi ol = 8.7 ma, v dd = 4.5v output high voltage d090 i/o ports/clkout (3) v oh v dd - 0.7--vi oh = -5.4 ma, v dd = 4.5v capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt and lp modes when external clock is used to drive osc1. d101 all i/o pins c io - - 50 pf ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic12c5xx be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin.
pic12c5xx ds40139e-page 68 1999 microchip technology inc. table 11-1: pull-up resistor ranges - pic12c508/c509 v dd (volts) temperature ( c) min typ max units gp0/gp1 2.5 C40 38k 42k 63k w 25 42k 48k 63k w 85 42k 49k 63k w 125 50k 55k 63k w 5.5 C40 15k 17k 20k w 25 18k 20k 23k w 85 19k 22k 25k w 125 22k 24k 28k w gp3 2.5 C40 285k 346k 417k w 25 343k 414k 532k w 85 368k 457k 532k w 125 431k 504k 593k w 5.5 C40 247k 292k 360k w 25 288k 341k 437k w 85 306k 371k 448k w 125 351k 407k 500k w * these parameters are characterized but not tested.
1999 microchip technology inc. ds40139e-page 69 pic12c5xx 11.3 timing parameter symbology and load conditions - pic12c508/c509 the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance figure 11-1: load conditions - pic12c508/c509 c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt or lp modes when external clock is used to drive osc1
pic12c5xx ds40139e-page 70 1999 microchip technology inc. 11.4 timing diagrams and specifications figure 11-2: external clock timing - pic12c508/c509 table 11-2: external clock timing requirements - pic12c508/c509 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial), C40 c t a +85 c (industrial), C40 c t a +125 c (extended) operating voltage v dd range is described in section 11.1 parameter no. sym characteristic min typ (1) max units conditions f osc external clkin frequency (2) dc 4 mhz xt osc mode dc 200 khz lp osc mode oscillator frequency (2) 0.1 4 mhz xt osc mode dc 200 khz lp osc mode 1t osc external clkin period (2) 250 ns extrc osc mode 250 ns xt osc mode 5 ms lp osc mode oscillator period (2) 250 ns extrc osc mode 250 10,000 ns xt osc mode 5 ms lp osc mode 2tcy instruction cycle time (3) 4/f osc 3 tosl, tosh clock in (osc1) low or high time 50* ns xt oscillator 2* ms lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time 25* ns xt oscillator 50* ns lp oscillator * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the max cycle time limit is dc (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 q4 q1 q2 q3 q4 q1 133 44 2
1999 microchip technology inc. ds40139e-page 71 pic12c5xx table 11-3: calibrated internal rc frequencies - pic12c508/c509 figure 11-3: i/o timing - pic12c508/c509 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial), C40 c t a +85 c (industrial), C40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min* typ (1) max* units conditions internal calibrated rc frequency 3.58 4.00 4.32 mhz v dd = 5.0v internal calibrated rc frequency 3.50 4.26mhzv dd = 2.5v * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. osc1 i/o pin (input) i/o pin (output) q4 q1 q2 q3 17 20, 21 18 old value new value note: all tests must be done with specified capacitive loads (see data sheet) 50 pf on i/o pins and clkout. 19
pic12c5xx ds40139e-page 72 1999 microchip technology inc. table 11-4: timing requirements - pic12c508/c509 figure 11-4: reset, watchdog timer, and device reset timer timing - pic12c508/c509 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) operating voltage v dd range is described in section 11.1 parameter no. sym characteristic min typ (1) max units 17 to s h 2 i o v osc1 - (q1 cycle) to port out valid (3) 100* ns 18 to s h 2 i o i o s c 1 - (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19 tiov2osh port input valid to osc1 - (i/o in setup time) tbd ns 20 tior port output rise time (2, 3) 1025**ns 21 tiof port output fall time (2, 3) 1025**ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. note 1: data in the typical (typ) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in extrc mode. 3: see figure 11-1 for loading conditions. v dd mclr internal por drt timeout internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 30 (note 2) 2: runs in mclr or wdt reset only in xt and lp modes.
1999 microchip technology inc. ds40139e-page 73 pic12c5xx table 11-5: reset, watchdog timer, and device reset timer - pic12c508/c509 table 11-6: drt (device reset timer period - pic12c508/c509) ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) operating voltage v dd range is described in section 11.1 parameter no. sym characteristic min typ (1) max units conditions 30 tmcl mclr pulse width (low) 2000* ns v dd = 5 v 31 twdt watchdog timer time-out period (no prescaler) 9* 18* 30* ms v dd = 5 v (commercial) 32 t drt device reset timer period (2) 9* 18* 30* ms v dd = 5 v (commercial) 34 tio z i/o hi-impedance from mclr low 2000* ns * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 2: see table 11-6. oscillator configuration por reset subsequent resets intrc & extrc 18 ms (typical) 300 s (typical) xt & lp 18 ms (typical) 18 ms (typical)
pic12c5xx ds40139e-page 74 1999 microchip technology inc. figure 11-5: timer0 clock timings - pic12c508/c509 table 11-7: timer0 clock requirements - pic12c508/c509 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) operating voltage v dd range is described in section 11.1. parameter no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 42 tt0p t0cki period 20 or t cy + 40 * n ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42
1999 microchip technology inc. ds40139e-page 75 pic12c5xx 12.0 dc and ac characteristics - pic12c508/pic12c509 the graphs and tables provided in this section are for design guidance and are not tested. in some graphs or tables the data presented are outside specified operating range (e.g., outside specified v dd range). this is for information only and devices will operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 s ) and (mean C 3 s ) respectively, where s is standard deviation. figure 12-1: calibrated internal rc frequency range vs. temperature (v dd = 2.5v) 4.50 4.10 4.00 3.90 3.80 3.70 3.60 -40 25 85 125 temperature (deg.c) frequency (mhz) min. max. 4.40 4.30 4.20 3.50 figure 12-2: calibrated internal rc frequency range vs. temperature (v dd = 5.0v) 4.50 4.10 4.00 3.90 3.80 3.70 3.60 -40 25 85 125 temperature (deg.c) frequency (mhz) min. max. 4.40 4.30 4.20 3.50
pic12c5xx ds40139e-page 76 1999 microchip technology inc. table 12-1: dynamic i dd (typical) - wdt enabled, 25c oscillator frequency v dd = 2.5v v dd = 5.5v external rc 4 mhz 250 a* 780 a* internal rc 4 mhz 420 a 1.1 ma xt 4 mhz 251 a 780 a lp 32 khz 15 a 37 a *does not include current through external r&c. figure 12-3: wdt timer time-out period vs. v dd 50 45 40 35 30 25 20 15 10 5 234567 v dd (volts) wdt period (ms) max +125 c max +85 c ty p + 2 5 c min C40 c figure 12-4: short drt period vs. v dd 1000 900 800 700 600 500 400 300 200 100 234567 v dd (volts) wdt period ( s) max +125 c max +85 c ty p + 2 5 c min C40 c
1999 microchip technology inc. ds40139e-page 77 pic12c5xx figure 12-5: i oh vs. v oh , v dd = 2.5 v figure 12-6: i oh vs. v oh , v dd = 5.5 v 500m 1.0 1.5 v oh (volts) i oh (ma) 2.0 2.5 0 -1 -2 -3 -4 -5 -6 -7 m i n + 1 2 5 c m a x C 4 0 c t y p + 2 5 c m i n + 8 5 c 3.5 4.0 4.5 v oh (volts) i oh (ma) 5.0 5.5 0 -5 -10 -15 -20 -25 -30 m i n + 1 2 5 c m a x C 4 0 c t y p + 2 5 c m i n + 8 5 c figure 12-7: i ol vs. v ol , v dd = 2.5 v figure 12-8: i ol vs. v ol , v dd = 5.5 v 25 20 15 10 5 0 250.0m 500.0m 1.0 v ol (volts) i ol (ma) min +85 c max C40 c ty p + 2 5 c 0 min +125 c 50 40 30 20 10 0 500.0m 750.0m 1.0 v ol (volts) i ol (ma) 250.0m min +85 c max C40 c ty p + 2 5 c min +125 c
pic12c5xx ds40139e-page 78 1999 microchip technology inc. notes:
1999 microchip technology inc. ds40139e-page 79 pic12c5xx 13.0 electrical characteristics - pic12c508a/pic12c509a/ pic12lc508a/pic12lc509a/pic12cr509a/pic12ce518/pic12ce519/ pic12lce518/pic12lce519/pic12lcr509a absolute maximum ratings? ambient temperature under bias ................................................................................................. .......... C40c to +125c storage temperature ............................................................................................................ ................. C65c to +150c voltage on v dd with respect to v ss .................................................................................................................0 to +7.0 v voltage on mclr with respect to v ss ...............................................................................................................0 to +14 v voltage on all other pins with respect to v ss ............................................................................... C0.3 v to (v dd + 0.3 v) total power dissipation (1) ............................................................................................................................... .....700 mw max. current out of v ss pin ........................................................................................................................... .......200 ma max. current into v dd pin ........................................................................................................................... ..........150 ma input clamp current, i ik (v i < 0 or v i > v dd ) .................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma max. output current sunk by any i/o pin........................................................................................ ........................25 ma max. output current sourced by any i/o pin..................................................................................... ......................25 ma max. output current sourced by i/o port (gpio) ................................................................................. ................100 ma max. output current sunk by i/o port (gpio )................................................................................... ...................100 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic12c5xx ds40139e-page 80 1999 microchip technology inc. 13.1 dc characteristics: pic12c508a/509a (commercial, industrial, extended) pic12ce518/519 (commercial, industrial, extended) pic12cr509a (commercial, industrial, extended) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) parm no. characteristic sym min typ (1) max units conditions d001 supply voltage v dd 3.0 5.5 v f osc = dc to 4 mhz (commercial/ industrial, extended) d002 ram data retention vo ltag e (2) v dr 1.5* v device in sleep mode d003 v dd start voltage to ensure power-on reset v por v ss v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* v/ms see section on power-on reset for details d010 d010c d010a supply current (3) i dd 0.8 0.8 19 19 30 1.4 1.4 27 35 55 ma ma m a m a a xt and extrc options (note 4) f osc = 4 mhz, v dd = 5.5v intrc option f osc = 4 mhz, v dd = 5.5v lp o ption , commercial temperature f osc = 32 khz, v dd = 3.0v, wdt disabled lp o ption , industrial temperature f osc = 32 khz, v dd = 3.0v, wdt disabled lp o ption , extended temperature f osc = 32 khz, v dd = 3.0v, wdt disabled d020 d021 d021b power-down current (5) i pd 0.25 0.25 2 4 5 12 m a m a m a v dd = 3.0v, commercial wdt disabled v dd = 3.0v, industrial wdt disabled v dd = 3.0v, extended wdt disabled d022 power-down current d i wdt 2.2 2.2 4 5 6 11 m a m a m a v dd = 3.0v, commercial v dd = 3.0v, industrial v dd = 3.0v, extended supply current (3) during read/write to eeprom peripheral d i ee 0.1 0.2 ma fosc = 4 mhz, vdd = 5.5v, scl = 400khz * these parameters are characterized but not tested. note 1: data in the typical (typ) column is based on characterization results at 25 c. this data is for design guid- ance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in kohm. 5: the power down current in sleep mode does not depend on the oscillator type. power down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss .
1999 microchip technology inc. ds40139e-page 81 pic12c5xx 13.2 dc characteristics: pic12lc508a/509a (commercial, industrial) pic12lce518/519 (commercial, industrial) pic12lcr509a (commercial, industrial) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) parm no. characteristic sym min typ (1) max units conditions d001 supply voltage v dd 2.5 5.5 v f osc = dc to 4 mhz (commercial/ industrial) d002 ram data retention vo ltag e (2) v dr 1.5* v device in sleep mode d003 v dd start voltage to ensure power-on reset v por v ss v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset s vdd 0.05* v/ms see section on power-on reset for details d010 d010c d010a supply current (3) i dd 0.4 0.4 15 15 0.8 0.8 23 31 ma ma m a m a xt and extrc options (note 4) f osc = 4 mhz, v dd = 2.5v intrc option f osc = 4 mhz, v dd = 2.5v lp o ption , commercial temperature f osc = 32 khz, v dd = 2.5v, wdt disabled lp o ption , industrial temperature f osc = 32 khz, v dd = 2.5v, wdt disabled d020 d021 d021b power-down current (5) i pd 0.2 0.2 3 4 m a m a v dd = 2.5v, commercial v dd = 2.5v, industrial d i wdt 2.0 2.0 4 5 ma ma v dd = 2.5v, commercial v dd = 2.5v, industrial * these parameters are characterized but not tested. note 1: data in the typical (typ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in kohm. 5: the power down current in sleep mode does not depend on the oscillator type. power down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss .
pic12c5xx ds40139e-page 82 1999 microchip technology inc. 13.3 dc characteristics: pic12c508a/509a (commercial, industrial, extended) pic12c518/519 (commercial, industrial, extended) pic12cr509a (commercial, industrial, extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 0c t a +70c (commercial) C40c t a +85c (industrial) C40c t a +125c (extended) operating voltage v dd range as described in dc spec section 13.1 and section 13.2. param no. characteristic sym min typ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss - 0.8v v for 4.5v v dd 5.5v v ss - 0.15v dd v otherwise d031 with schmitt trigger buffer v ss -0.2v dd v d032 mclr , gp2/t0cki (in extrc mode) v ss -0.2v dd v d033 osc1 (in extrc mode) v ss -0.2v dd note 1 d033 osc1 (in xt and lp) v ss -0.3v dd v note 1 input high voltage i/o ports v ih - d040 with ttl buffer 0.25v dd + 0.8v -v dd v4.5v v dd 5.5v d040a 2.0v - v dd v otherwise d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr , gp2/t0cki 0.8v dd -v dd v d042a osc1 (xt and lp) 0.7v dd -v dd v note 1 d043 osc1 (in extrc mode) 0.9v dd -v dd v d070 gpio weak pull-up current (note 4) i pur 30 250 400 m av dd = 5v, v pin = v ss mclr pull-up current - - - 30 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il --+ 1 m a vss v pin v dd , pin at hi- impedance d061 t0cki - - + 5 m a vss v pin v dd d063 osc1 - - + 5 m a vss v pin v dd , xt and lp osc configuration output low voltage d080 i/o ports v ol --0.6vi ol = 8.5 ma, v dd = 4.5v, C40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v, C40 c to +125 c output high voltage d090 i/o ports (note 3) v oh v dd - 0.7--vi oh = -3.0 ma, v dd = 4.5v, C40 c to +85 c d090a v dd - 0.7--vi oh = -2.5 ma, v dd = 4.5v, C40 c to +125 c capacitive loading specs on output pins d100 osc2 pin cosc2 - - 15 pf in xt and lp modes when exter- nal clock is used to drive osc1. d101 all i/o pins c io - - 50 pf ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic12c5xx be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: this spec. applies when gp3/mclr is configured as mclr . the leakage current of the mclr circuit is higher than the standard i/o logic.
1999 microchip technology inc. ds40139e-page 83 pic12c5xx 13.4 dc characteristics: pic12lc508a/509a (commercial, industrial) pic12lc518/519 (commercial, industrial) pic12lcr509a (commercial, industrial) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 0c t a +70c (commercial) C40c t a +85c (industrial) operating voltage v dd range as described in dc spec section 13.1 and section 13.2. param no. characteristic sym min typ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss - 0.8v v for 4.5v v dd 5.5v v ss -0.15v dd v otherwise d031 with schmitt trigger buffer v ss -0.2v dd v d032 mclr , gp2/t0cki (in extrc mode) v ss -0.2v dd v d033 osc1 (in extrc mode) v ss -0.2v dd v note 1 d033 osc1 (in xt and lp) v ss -0.3v dd v note 1 input high voltage i/o ports v ih - d040 with ttl buffer 0.25v dd + 0.8v -v dd v4.5v v dd 5.5v d040a 2.0v - v dd v otherwise d041 with schmitt trigger buffer 0.8v dd -v dd v for entire v dd range d042 mclr , gp2/t0cki 0.8v dd -v dd v d042a osc1 (xt and lp) 0.7v dd -v dd v note 1 d043 osc1 (in extrc mode) 0.9v dd -v dd v d070 gpio weak pull-up current (note 4) i pur 30 250 400 m av dd = 5v, v pin = v ss mclr pull-up current - - - 30 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il --+ 1 m a vss v pin v dd , pin at hi-imped- ance d061 t0cki - - + 5 m a vss v pin v dd d063 osc1 - - + 5 m a vss v pin v dd , xt and lp osc configuration output low voltage d080 i/o ports v ol --0.6vi ol = 8.5 ma, v dd = 4.5v, C40 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4.5v, C40 c to +125 c output high voltage d090 i/o ports (note 3) v oh v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v, C40 c to +85 c d090a v dd - 0.7 - - v i oh = -2.5 ma, v dd = 4.5v, C40 c to +125 c capacitive loading specs on output pins d100 osc2 pin cosc 2 - - 15 pf in xt and lp modes when exter- nal clock is used to drive osc1. d101 all i/o pins c io - - 50 pf ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic12c5xx be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: this spec. applies when gp3/mclr is configured as mclr . the leakage current of the mclr circuit is higher than the standard i/o logic.
pic12c5xx ds40139e-page 84 1999 microchip technology inc. table 13-1: pull-up resistor ranges* - pic12c508a, pic12c509a, pic12cr509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 v dd (volts) temperature ( c) min typ max units gp0/gp1 2.5 C40 38k 42k 63k w 25 42k 48k 63k w 85 42k 49k 63k w 125 50k 55k 63k w 5.5 C40 15k 17k 20k w 25 18k 20k 23k w 85 19k 22k 25k w 125 22k 24k 28k w gp3 2.5 C40 285k 346k 417k w 25 343k 414k 532k w 85 368k 457k 532k w 125 431k 504k 593k w 5.5 C40 247k 292k 360k w 25 288k 341k 437k w 85 306k 371k 448k w 125 351k 407k 500k w * these parameters are characterized but not tested.
1999 microchip technology inc. ds40139e-page 85 pic12c5xx 13.5 timing parameter symbology and load conditions - pic12c508a, pic12c509a, pic12cr509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance figure 13-1: load conditions - pic12c508a/c509a, pic12ce518/519, pic12lc508a/509a, pic12lce518/519, pic12lcr509a c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1
pic12c5xx ds40139e-page 86 1999 microchip technology inc. 13.6 timing diagrams and specifications figure 13-2: external clock timing - pic12c508a, pic12c509a, pic12cr509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 table 13-2: external clock timing requirements - pic12c508a, pic12c509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial), C40 c t a +85 c (industrial), C40 c t a +125 c (extended) operating voltage v dd range is described in section 13.1 parameter no. sym characteristic min typ (1) max units conditions f osc external clkin frequency (2) dc 4 mhz xt osc mode dc 200 khz lp osc mode oscillator frequency (2) dc 4 mhz extrc osc mode 0.1 4 mhz xt osc mode dc 200 khz lp osc mode 1t osc external clkin period (2) 250 ns xt osc mode 5 ms lp osc mode oscillator period (2) 250 ns extrc osc mode 250 10,000 ns xt osc mode 5 ms lp osc mode 2tcy instruction cycle time (3) 4/f osc 3 tosl, tosh clock in (osc1) low or high time 50* ns xt oscillator 2* ms lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time 25* ns xt oscillator 50* ns lp oscillator * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the max cycle time limit is dc (no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 q4 q1 q2 q3 q4 q1 133 44 2
1999 microchip technology inc. ds40139e-page 87 pic12c5xx table 13-3: calibrated internal rc frequencies - pic12c508a, pic12c509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial), C40 c t a +85 c (industrial), C40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min* typ (1) max* units conditions internal calibrated rc frequency 3.65 4.00 4.28 mhz v dd = 5.0v internal calibrated rc frequency 3.55 4.31mhzv dd = 2.5v * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic12c5xx ds40139e-page 88 1999 microchip technology inc. figure 13-3: i/o timing - pic12c508a, pic12c509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 table 13-4: timing requirements - pic12c508a, pic12c509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) operating voltage v dd range is described in section 13.1 parameter no. sym characteristic min typ (1) max units 17 to s h 2 i o v osc1 - (q1 cycle) to port out valid (3) 100* ns 18 to s h 2 i o i o s c 1 - (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19 tiov2osh port input valid to osc1 - (i/o in setup time) tbd ns 20 tior port output rise time (2, 3) 1025**ns 21 tiof port output fall time (2, 3) 1025**ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. note 1: data in the typical (typ) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in extrc mode. 3: see figure 13-1 for loading conditions. osc1 i/o pin (input) i/o pin (output) q4 q1 q2 q3 17 20, 21 18 old value new value note: all tests must be done with specified capacitive loads (see data sheet) 50 pf on i/o pins and clkout. 19
1999 microchip technology inc. ds40139e-page 89 pic12c5xx figure 13-4: reset, watchdog timer, and device reset timer timing - pic12c508a, pic12c509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 table 13-5: reset, watchdog timer, and device reset timer - pic12c508a, pic12c509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) operating voltage v dd range is described in section 13.1 parameter no. sym characteristic min typ (1) max units conditions 30 tmcl mclr pulse width (low) 2000* ns v dd = 5 v 31 twdt watchdog timer time-out period (no prescaler) 9* 18* 30* ms v dd = 5 v (commercial) 32 t drt device reset timer period (2) 9* 18* 30* ms v dd = 5 v (commercial) 34 tio z i/o hi-impedance from mclr low 2000* ns * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 2: see table 13-6. v dd mclr internal por drt timeout internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 30 (note 2) 2: runs in mclr or wdt reset only in xt and lp modes.
pic12c5xx ds40139e-page 90 1999 microchip technology inc. table 13-6: drt (device reset timer period) - pic12c508a, pic12c509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 figure 13-5: timer0 clock timings - pic12c508a, pic12c509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 table 13-7: timer0 clock requirements - pic12c508a, pic12c509a, pic12ce518, pic12ce519, pic12lc508a, pic12lc509a, pic12lcr509a, pic12lce518 and pic12lce519 oscillator configuration por reset subsequent resets intrc & extrc 18 ms (typical) (1) 300 s (typical) (1) xt & lp 18 ms (typical) (1) 18 ms (typical) (1) note 1: d ata in the typical (typ) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) operating voltage v dd range is described in section 13.1. parameter no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 42 tt0p t0cki period 20 or t cy + 40 * n ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42
1999 microchip technology inc. ds40139e-page 91 pic12c5xx table 13-8: eeprom memory bus timing requirements - pic12ce5xx only . ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c, vcc = 3.0v to 5.5v (commercial) C40 c t a +85 c, vcc = 3.0v to 5.5v (industrial) C40 c t a +125 c, vcc = 4.5v to 5.5v (extended) operating voltage v dd range is described in section 13.1 parameter symbol min max units conditions clock frequency f clk 100 100 400 khz 4.5v vcc 5.5v (e temp range) 3.0v vcc 4.5v 4.5v vcc 5.5v clock high time t high 4000 4000 600 ns 4.5v vcc 5.5v (e temp range) 3.0v vcc 4.5v 4.5v vcc 5.5v clock low time t low 4700 4700 1300 ns 4.5v vcc 5.5v (e temp range) 3.0v vcc 4.5v 4.5v vcc 5.5v sda and scl rise time (note 1) t r 1000 1000 300 ns 4.5v vcc 5.5v (e temp range) 3.0v vcc 4.5v 4.5v vcc 5.5v sda and scl fall time t f 300 ns (note 1) start condition hold time t hd : sta 4000 4000 600 ns 4.5v vcc 5.5v (e temp range) 3.0v vcc 4.5v 4.5v vcc 5.5v start condition setup time t su : sta 4700 4700 600 ns 4.5v vcc 5.5v (e temp range) 3.0v vcc 4.5v 4.5v vcc 5.5v data input hold time t hd : dat 0 ns (note 2) data input setup time t su : dat 250 250 100 ns 4.5v vcc 5.5v (e temp range) 3.0v vcc 4.5v 4.5v vcc 5.5v stop condition setup time t su : sto 4000 4000 600 ns 4.5v vcc 5.5v (e temp range) 3.0v vcc 4.5v 4.5v vcc 5.5v output valid from clock (note 2) t aa 3500 3500 900 ns 4.5v vcc 5.5v (e temp range) 3.0v vcc 4.5v 4.5v vcc 5.5v bus free time: time the bus must be free before a new transmis- sion can start t buf 4700 4700 1300 ns 4.5v vcc 5.5v (e temp range) 3.0v vcc 4.5v 4.5v vcc 5.5v output fall time from v ih minimum to v il maximum t of 20+0.1 cb 250 ns (note 1), cb 100 pf input filter spike suppression (sda and scl pins) t sp 50 ns (notes 1, 3) write cycle time t wc 4ms endurance 1m cycles 25 c, v cc = 5.0v, block mode (note 4) note 1: not 100% tested. cb = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a specific appli- cation, please consult the total endurance model which can be obtained on microchips website.
pic12c5xx ds40139e-page 92 1999 microchip technology inc. notes:
1999 microchip technology inc. ds40139e-page 93 pic12c5xx 14.0 dc and ac characteristics - pic12c508a/pic12c509a/ pic12lc508a/pic12lc509a, pic12ce518/pic12ce519/pic12cr509a/ pic12lce518/pic12lce519/ pic12lcr509a the graphs and tables provided in this section are for design guidance and are not tested. in some graphs or tables the data presented are outside specified operating range (e.g., outside specified v dd range). this is for information only and devices will operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 s ) and (mean C 3 s ) respectively, where s is standard deviation. figure 14-1: calibrated internal rc frequency range vs. temperature (v dd = 5.0v) (internal rc is calibrated to 25c, 5.0v) 4.40 4.30 4.20 4.10 4.00 3.90 3.80 3.70 3.60 3.50 -40 25 85 125 4.50 0 max. mi n. frequency (mhz) temperature (deg.c) figure 14-2: calibrated internal rc frequency range vs. temperature (v dd = 2.5v) (internal rc is calibrated to 25c, 5.0v) 4.40 4.30 4.20 4.10 4.00 3.90 3.80 3.70 3.60 3.50 -40 25 85 125 4.50 0 max. mi n . frequency (mhz) temperature (deg.c)
pic12c5xx ds40139e-page 94 1999 microchip technology inc. table 14-1: dynamic i dd (typical) - wdt enabled, 25c oscillator frequency v dd =3.0v v dd = 5.5v external rc 4 mhz 240 a* 800 a* internal rc 4 mhz 320 a 800 a xt 4 mhz 300 a 800 a lp 32 khz 19 a 50 a *does not include current through external r&c. figure 14-3: typical i dd vs. v dd (wdt dis, 25c, frequency = 4mh z ) 500 450 400 350 300 250 200 150 100 0 2.5 4.5 5.0 5.5 v dd (volts) 550 3.0 i dd ( a ) 600 figure 14-4: typical i dd vs. frequency (wdt dis, 25c, v dd = 5.5v) 500 450 400 350 300 250 200 150 100 0 0 2.0 3.5 4.0 frequency (mhz) 550 1.0 i dd ( a ) 600 3.0 2.5 1.5 .5
1999 microchip technology inc. ds40139e-page 95 pic12c5xx figure 14-5: wdt timer time-out period vs. v dd figure 14-6: short drt period vs. v dd min C40 c ty p + 2 5 c max +85 c max +125 c 55 50 45 40 35 30 25 20 15 10 0 2.5 3.5 4.5 5.5 6.5 v dd (volts) wdt period ( s) min C40 c ty p + 2 5 c max +85 c max +125 c 950 850 750 650 550 450 350 250 150 0 0 2.5 3.5 4.5 5.5 6.5 v dd (volts) wdt period ( s) figure 14-7: i oh vs. v oh , v dd = 2.5 v figure 14-8: i oh vs. v oh , v dd = 3.5 v max -40 c ty p + 2 5 c min +85 c min +125 c v oh (volts) i oh (ma) .5 1.0 1.5 2.0 2.5 -0 -1 -2 -3 -4 -5 -10 2.25 1.75 1.25 .75 -6 -7 -8 -9 v oh (volts) i oh (ma) 1.5 2.0 2.5 3.0 3.5 0 -5 -10 -15 -20 -25 min +125 c min +85 c typ + 2 5 c max -40 c
pic12c5xx ds40139e-page 96 1999 microchip technology inc. figure 14-9: i ol vs. v ol , v dd = 2.5 v figure 14-10: i ol vs. v ol , v dd = 3.5 v min +125 c min +85 c ty p + 2 5 c max -40 c 25 20 15 10 5 0 0.5 0.75 1.0 v ol (volts) i ol (ma) 0 30 35 0.25 min +125 c min +85 c ty p + 2 5 c max -40 c 30 25 20 15 10 0 0.5 0.75 1.0 v ol (volts) i ol (ma) 0 35 40 0.25 45 figure 14-11: i oh vs. v oh , v dd = 5.5 v figure 14-12: i ol vs. v ol , v dd = 5.5 v 3.5 4.0 4.5 v oh (volts) i oh (ma) 5.0 5.5 0 -5 -10 -15 -20 -25 -30 m i n + 1 2 5 c m a x C 4 0 c t y p + 2 5 c m i n + 8 5 c -35 -40 min +125 c min +85 c ty p + 2 5 c max -40 c 30 25 20 15 10 0 0.5 0.75 1.0 v ol (volts) i ol (ma) 0 35 40 0.25 45 50 55
1999 microchip technology inc. ds40139e-page 97 pic12c5xx figure 14-13: typical ipd vs. v dd , watchdog disabled ( 25c) ipd (na) 260 250 240 230 220 210 200 2.5 3.0 3.5 4.5 5.0 5.5 v dd (volts) figure 14-14: vth (input threshold voltage) of gpio pins vs. v dd ty p ( 2 5 ) max (-40 to 125) min (-40 to 125) 1.6 1.4 1.2 1.0 0.8 0.6 0 2.5 3.5 4.5 5.5 v dd (volts) v th (volts) 1.8
pic12c5xx ds40139e-page 98 1999 microchip technology inc. figure 14-15: vil, vih of nmclr, and t0cki vs. v dd 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2.5 3.5 4.5 5.5 v dd (volts) v il , v ih (volts) vih max (-40 to 125) v ih ty p (2 5 ) v ih min (-40 to 125) v il max (-40 to 125) v il ty p ( 2 5 ) v il min (-40 to 125)
1999 microchip technology inc. ds40139e-page 99 pic12c5xx 15.0 packaging information 15.1 package marking information legend: mm...m microchip part number information xx...x customer specific information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week 01) c facility code of the plant at which wafer is manufactured o = outside vendor c = 5 line s = 6 line h = 8 line d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. xxxxxxxx xxxxxcde aabb 8-lead pdip (300 mil) example 8-lead soic (208 mil) xxxxxxx aabbcde xxxxxxx 8-lead windowed ceramic side brazed (300 mil) xxxxxx xxx example example 12c508a 04i/psaz 9825 12c508a 9824saz 04i/sm 12c508a jw 8-lead soic (150 mil) xxxxxxx example aabb c508a 9825
pic12c5xx ds40139e-page 100 1999 microchip technology inc. package type: k04-018 8-lead plastic dual in-line (p) C 300 mil * controlling parameter. ? dimension b1 does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b1. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e. 0.310 0.267 0.245 0.355 0.120 0.005 0.060 0.140 0.006 0.000 0.055 0.014 mold draft angle bottom mold draft angle top overall row spacing radius to radius width molded package width tip to seating plane base to seating plane top of lead to seating plane top to seating plane upper lead width lower lead width pcb row spacing package length lead thickness shoulder radius number of pins pitch eb b a l e1 e ? d ? a2 a1 a b b1 ? r c n p dimension limits units min 0.380 0.342 5 5 10 10 15 15 0.130 0.280 0.250 0.370 0.020 0.080 0.150 0.018 0.012 0.005 0.060 0.100 0.300 8 0.292 0.260 0.385 0.140 0.035 0.100 0.160 0.015 0.010 0.065 0.022 9.65 8.67 7.87 5 5 10 10 15 15 7.10 6.35 9.40 3.30 0.51 2.03 3.81 0.29 0.13 1.52 0.46 2.54 7.62 3.05 6.78 6.22 9.02 0.13 1.52 3.56 0.36 0.20 0.00 1.40 3.56 7.42 6.60 9.78 0.89 2.54 4.06 8 0.56 0.38 0.25 1.65 min nom inches* max millimeters nom max n 1 2 r d e c b eb e1 a p a1 l a a2 b b1
1999 microchip technology inc. ds40139e-page 101 pic12c5xx package type: k04-057 8-lead plastic small outline (sn) C narrow, 150 mil min dimension limits mold draft angle bottom mold draft angle top lower lead width radius centerline gull wing radius shoulder radius chamfer distance outside dimension molded package width molded package length shoulder height overall pack. height lead thickness foot angle foot length standoff number of pins pitch b a c b ? f x a2 a1 a n p e ? r2 l1 l r1 e1 d ? units max nom min max nom 8 12 12 0.017 0.009 0 0 0.014 0.008 0.020 0.010 15 15 0.005 0.016 0.005 0.005 0.015 0.237 0.154 0.193 0.007 0.035 0.061 0.050 0.150 0.005 0.000 0.011 0 0.005 0.010 0.229 0.189 0.004 0.027 0.054 0.157 0.010 0.021 0.010 0.010 0.020 0.244 48 0.196 0.010 0.044 0.069 8 0.36 0.19 0 0 12 12 0.43 0.22 15 15 0.51 0.25 3.81 0.00 0.28 0.13 0.13 0.25 5.82 0 4.80 0.10 0.69 1.37 3.99 3.90 0.13 4 0.13 0.41 0.38 0.13 6.01 0.25 0.25 0.53 0.51 0.25 6.20 0.18 4.89 0.90 8 1.56 1.27 0.25 4.98 1.11 1.75 inches* millimeters n 1 2 r2 r1 d p b e1 e l1 x l b c 45 f a1 a a a2 * controlling parameter. ? dimension b does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e.
pic12c5xx ds40139e-page 102 1999 microchip technology inc. package type: k04-056 8-lead plastic small outline (sm) C medium, 208 mil min mold draft angle bottom mold draft angle top lower lead width radius centerline gull wing radius shoulder radius outside dimension molded package width molded package length shoulder height overall pack. height lead thickness foot angle foot length standoff number of pins pitch c b a b ? f a2 a1 a n p r2 l1 l r1 e1 d ? e ? dimension limits units 8 0.010 0.009 0.008 12 12 0.017 0 0.014 0 0.020 15 15 0.015 0.016 0.005 0.005 0.313 0.208 0.205 0.005 0.042 0.074 0.050 0.005 0.010 0.011 0 0.005 0.300 0.037 0.203 0.200 0.002 0.070 0.020 0.021 0.010 0.010 0.325 48 0.213 0.210 0.009 0.048 0.079 8 0.25 0.22 0.19 0.36 0 0 12 12 0.43 15 15 0.51 0.25 0.28 0.13 0.13 7.62 0 5.16 5.08 0.05 0.94 1.78 0.13 4 0.38 0.41 0.13 7.94 0.25 0.51 0.53 0.25 8.26 1.08 5.21 5.28 0.14 8 1.89 1.27 1.21 5.33 5.41 0.22 2.00 nom inches* max nom millimeters min max n 1 2 r2 r1 a a1 a a2 l1 l c b f d p b e1 e * controlling parameter. ? dimension b does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e.
1999 microchip technology inc. ds40139e-page 103 pic12c5xx package type: k04-084 8-lead ceramic side brazed dual in-line with window (jw) C 300 mil n 1 2 0.260 0.440 0.161 0.310 0.280 0.510 0.130 0.025 0.103 0.145 0.008 0.050 0.016 0.098 min window diameter overall row spacing package length tip to seating plane base to seating plane top of body to seating plane top to seating plane upper lead width lower lead width pcb row spacing dimension limits lid length lid width package width lead thickness number of pins pitch units t u d w eb e a2 a1 l b a c b1 p n 0.450 0.270 0.520 0.166 0.338 0.290 0.140 0.035 0.123 0.460 0.280 0.171 0.365 0.300 0.530 0.150 0.045 0.143 8 nom 0.018 0.165 0.010 0.055 0.100 0.300 max 0.185 0.012 0.060 0.020 0.102 6.86 11.43 4.22 8.57 7.37 13.21 3.56 0.89 3.12 11.18 6.60 12.95 4.09 7.87 7.11 3.30 0.64 2.62 11.68 7.11 13.46 4.34 9.27 7.62 3.81 1.14 3.63 4.19 0.25 1.40 0.46 2.54 7.62 nom millimeters min 0.41 3.68 0.20 1.27 2.49 max 8 0.51 4.70 0.30 1.52 2.59 d t e u w c eb l a1 b b1 a a2 p inches* * controlling parameter.
pic12c5xx ds40139e-page 104 1999 microchip technology inc. notes:
1999 microchip technology inc. ds40139e-page 105 pic12c5xx index a alu ....................................................................................... 9 applications........................................................................... 4 architectural overview .......................................................... 9 assembler mpasm assembler..................................................... 61 b block diagram on-chip reset circuit ................................................. 41 timer0......................................................................... 25 tmr0/wdt prescaler................................................. 28 watchdog timer.......................................................... 43 brown-out protection circuit .............................................. 44 c cal0 bit .............................................................................. 18 cal1 bit .............................................................................. 18 cal2 bit .............................................................................. 18 cal3 bit .............................................................................. 18 calfst bit ......................................................................... 18 calslw bit ........................................................................ 18 carry ..................................................................................... 9 clocking scheme ................................................................ 12 code protection ............................................................ 35, 45 configuration bits................................................................ 35 configuration word ............................................................. 35 d dc and ac characteristics ........................................... 75, 93 development support ......................................................... 59 development tools ............................................................. 59 device varieties .................................................................... 7 digit carry ............................................................................. 9 e eeprom peripheral operation .......................................... 29 errata .................................................................................... 3 f family of devices.................................................................. 5 features ................................................................................ 1 fsr ..................................................................................... 20 fuzzy logic dev. system ( fuzzy tech -mp) .................... 61 i i/o interfacing ..................................................................... 21 i/o ports .............................................................................. 21 i/o programming considerations........................................ 22 icepic low-cost pic16cxxx in-circuit emulator ............ 59 id locations .................................................................. 35, 45 indf.................................................................................... 20 indirect data addressing..................................................... 20 instruction cycle ................................................................. 12 instruction flow/pipelining .................................................. 12 instruction set summary..................................................... 48 k keeloq evaluation and programming tools.................... 62 l loading of pc ..................................................................... 19 m memory organization.......................................................... 13 data memory .............................................................. 14 program memory ........................................................ 13 mplab integrated development environment software .... 61 o option register................................................................ 17 osc selection..................................................................... 35 osccal register............................................................... 18 oscillator configurations..................................................... 36 oscillator types hs............................................................................... 36 lp ............................................................................... 36 rc .............................................................................. 36 xt ............................................................................... 36 p package marking information............................................. 99 packaging information........................................................ 99 picdem-1 low-cost picmicro demo board ..................... 60 picdem-2 low-cost pic16cxx demo board................... 60 picdem-3 low-cost pic16cxxx demo board ................ 60 picstart plus entry level development system ......... 59 por device reset timer (drt) ................................... 35, 42 pd ............................................................................... 44 power-on reset (por).............................................. 35 to ............................................................................... 44 porta ............................................................................... 21 power-down mode ............................................................. 45 prescaler ............................................................................ 28 pro mate ii universal programmer .............................. 59 program counter ................................................................ 19 q q cycles.............................................................................. 12 r rc oscillator....................................................................... 37 read modify write .............................................................. 22 register file map................................................................ 14 registers special function ......................................................... 15 reset .................................................................................. 35 reset on brown-out ........................................................... 44 s seeval evaluation and programming system .............. 61 sleep .......................................................................... 35, 45 software simulator (mplab-sim) ...................................... 61 special features of the cpu .............................................. 35 special function registers................................................. 15 stack................................................................................... 19 status ............................................................................... 9 status register ............................................................... 16 t timer0 switching prescaler assignment ................................ 28 timer0 ........................................................................ 25 timer0 (tmr0) module .............................................. 25 tmr0 with external clock .......................................... 27 timing diagrams and specifications ............................ 70, 86 timing parameter symbology and load conditions .... 69, 85 tris registers ................................................................... 21 w wake-up from sleep......................................................... 45 watchdog timer (wdt)................................................ 35, 42 period ......................................................................... 43 programming considerations ..................................... 43 www, on-line support ....................................................... 3 z zero bit ................................................................................. 9
pic12c5xx ds40139e-page 106 1999 microchip technology inc.
1999 microchip technology inc. ds40139e-page 107 pic12c5xx systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-602-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom, mplab and fuzzy- lab are trademarks and sqtp is a service mark of micro- chip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ? device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development sys- tems, technical information and more ? listing of seminars and events 981103
pic12c5xx ds40139e-page 108 1999 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds40139e pic12c5xx
1999 microchip technology inc. ds40139e-page 109 pic12c5xx pic12c5xx product identification system please contact your local sales office for exact ordering procedures. sales and support: data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. pattern: special requirements package: sn = 150 mil soic sm = 208 mil soic p = 300 mil pdip jw = 300 mil windowed ceramic side brazed temperature range: -=0 c to +70 c i=-40 c to +85 c e=-40 c to +125 c frequency range: 04 = 4 mhz device pic12c508 pic12c509 pic12c508t (tape & reel for soic only) pic12c509t (tape & reel for soic only) pic12c508a pic12c509a pic12c508at (tape & reel for soic only) pic12c509at (tape & reel for soic only) pic12lc508a pic12lc509a pic12lc508at (tape & reel for soic only) pic12lc509at (tape & reel for soic only) pic12cr509a pic12cr509at (tape & reel for soic only) pic12lcr509a pic12lcr509at (tape & reel for soic only) pic12ce518 pic12ce518t (tape & reel for soic only) pic12ce519 pic12ce519t (tape & reel for soic only) pic12lce518 pic12lce518t (tape & reel for soic only) pic12lce519 pic12lce519t (tape & reel for soic only) part no. -xx x /xx xxx examples a) pic12c508a-04/p commercial temp., pdip package, 4 mhz, normal v dd limits b) pic12c508a-04i/sm industrial temp., soic package, 4 mhz, normal v dd limits c) pic12c509-04i/p industrial temp., pdip package, 4 mhz, normal v dd limits
pic12c5xx ds40139e-page 110 1999 microchip technology inc. notes:
1999 microchip technology inc. ds40139e-page 111 pic12c5xx notes:
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth er intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?an road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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