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description the 4506 group is a 4-bit single-chip microcomputer designed with cmos technology. its cpu is that of the 4500 series using a simple, high-speed instruction set. the computer is equipped with two 8-bit timers (each timer has a reload register), interrupts, and 10-bit a/d converter. the various microcomputers in the 4506 group include variations of the built-in memory size as shown in the table below. features minimum instruction execution time ................................ 0.68 s (at 4.4 mhz oscillation frequency, in high-speed mode) supply voltage .......................................................... 2.0 v to 5.5 v (it depends on the oscillation frequency and operating mode.) part number M34506M2-XXXFP m34506m4-xxxfp m34506e4fp ( note ) rom type mask rom mask rom one time prom package prsp0020da-a prsp0020da-a prsp0020da-a ram size ( ? 4 bits) 128 words 256 words 256 words rom (prom) size ( ? 10 bits) 2048 words 4096 words 4096 words timers timer 1 ...................................... 8-bit timer with a reload register timer 2 ...................................... 8-bit timer with a reload register interrupt ........................................................................ 4 sources key-on wakeup function pins ................................................... 12 input/output port ...................................................................... 14 a/d converter .................. 10-bit successive comparison method watchdog timer clock generating circuit (ceramic resonator/rc oscillation) led drive directly enabled (port d) application electrical household appliance, consumer electronic products, of- fice automation equipment, etc. note: shipped in blank. pin configuration pin configuration (top view) (4506 group) 19 18 17 16 15 14 13 12 11 20 p 1 2 / c n t r p 1 3 / i n t d 0 d 1 p 0 3 p 0 2 p 0 1 p 0 0 p 1 1 p 1 0 o u t l i n e p r s p 0 0 2 0 d a - a ( 2 0 p 2 n - a ) 2 3 4 5 6 7 8 9 10 1 m 3 4 5 0 6 m x - x x x f p m 3 4 5 0 6 e 4 f p p 2 1 / a i n 1 x i n x o u t c n v s s v ss v d d p 2 0 / a i n 0 r e s e t d 3 /k d 2 /c rev.3.01 2005.02.07 page 1 of 111 rej03b0106-0301 4506 group single-chip 4-bit cmos microcomputer rej03b0106-0301 rev.3.01 2005.02.07
rev.3.01 2005.02.07 page 2 of 111 rej03b0106-0301 4506 group block diagram block diagram (4506 group) r a m r o m m e m o r y i / o p o r t i n t e r n a l p e r i p h e r a l f u n c t i o n s t i m e r t i m e r 1 ( 8 b i t s ) s y s t e m c l o c k g e n e r a t i n g c i r c u i t t i m e r 2 ( 8 b i t s ) 1 2 8 , 2 5 6 w o r d s ? 4 b i t s 2 0 4 8 , 4 0 9 6 w o r d s ? 1 0 b i t s 4 5 0 0 s e r i e s c p u c o r e r e g i s t e r b ( 4 b i t s ) r e g i s t e r a ( 4 b i t s ) r e g i s t e r d ( 3 b i t s ) r e g i s t e r e ( 8 b i t s ) s t a c k r e g i s t e r s k ( 8 l e v e l s ) i n t e r r u p t s t a c k r e g i s t e r s d p ( 1 l e v e l ) a l u ( 4 b i t s ) x i n - x o u t w a t c h d o g t i m e r ( 1 6 b i t s ) ( 1 0 b i t s ? 2 c h ) a / d c o n v e r t e r p o r t p 0 4 p o r t p 1 4 p o r t p 2 2 p o r t d 4
4506 group rev.3.01 2005.02.07 page 3 of 111 rej03b0106-0301 performance overview function 110 0.68 s (at 4.4 mhz oscillation frequency, in high-speed mode) 2048 words ? 10 bits 4096 words ? 10 bits 128 words ? 4 bits 256 words ? 4 bits four independent i/o ports . input is examined by skip decision. ports d 2 and d 3 are equipped with a pull-up function and a key-on wakeup function. both func- tions can be switched by software. ports d 2 and d 3 are also used as ports c and k, respectively. 4-bit i/o port; each pin is equipped with a pull-up function and a key-on wakeup function. both functions can be switched by software. 4-bit i/o port; each pin is equipped with a pull-up function and a key-on wakeup function. both functions can be switched by software. ports p1 2 and p1 3 are also used as cntr and int, respectively. 2-bit i/o port; each pin is equipped with a pull-up function and a key-on wakeup function. both functions can be switched by software. ports p2 0 and p2 1 are also used as a in0 and a in1 , respectively. 1-bit i/o; port c is also used as port d 2 . 1-bit i/o; port k is also used as port d 3 . 1-bit i/o; cntr pin is also used as port p1 2 . 1-bit input; int pin is also used as port p1 3 . two independent i/o ports; a in0 , a in1 are also used as p2 0 and p2 1 , respectively. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register and has a event counter. 10-bit wide, this is equipped with an 8-bit comparator function. 2 channel (a in0 pin, a in1 pin) 4 (one for external, two for timer, one for a/d) 1 level 8 levels cmos silicon gate 20-pin plastic molded sop (prsp0020da-a) ?0 ? to 85 ? 2.0 v to 5.5 v (it depends on the oscillation frequency and operating mode. refer to the recom- mended operating condition.) 1.7 ma (ta=25?, v dd = 5.0 v, 4.0 mhz oscillation frequency, in high-speed mode, output tran- sistors in the cut-off state) 0.5 ma (ta=25?, v dd = 3.0 v, 2.0 mhz oscillation frequency, in high-speed mode, output tran- sistors in the cut-off state) 0.1 a (ta=25?, v dd = 5 v, output transistors in the cut-off state) parameter number of basic instructions minimum instruction execution time memory sizes input/output ports rom ram d 0 ? 3 p0 0 ?0 3 p1 0 ?1 3 p2 0 , p2 1 c k cntr int a in0 , a in1 timer 1 timer 2 analog input sources nesting active mode ram back-up mode m34506m2 m34506m4/e4 m34506m2 m34506m4/e4 i/o i/o i/o i/o i/o i/o timer i/o interrupt input analog input timers a/d converter interrupt subroutine nesting device structure package operating temperature range supply voltage power dissipation (typical value)
rev.3.01 2005.02.07 page 4 of 111 rej03b0106-0301 4506 group pin description name power supply ground cnv ss reset input/output system clock input i/o port d i/o port p0 i/o port p1 i/o port p2 i/o port c i/o port k timer input/output interrupt input analog input pin v dd v ss cnv ss reset x in d 0 ? 3 p0 0 ?0 3 p1 0 ?1 3 p2 0 , p2 1 port c port k cntr int a in0 ? in1 input/output i/o input i/o i/o i/o i/o i/o i/o i/o input input function connected to a plus power supply. connected to a 0 v power supply. connect cnv ss to v ss and apply ??(0v) to cnv ss certainly. an n-channel open-drain i/o pin for a system reset. when the watchdog timer or the built-in power-on reset causes the system to be reset, the reset pin outputs ??level. i/o pins of the system clock generating circuit. when using a ceramic resonator, connect it between pins x in and x out . a feedback resistor is built-in between them. when using the rc oscillation, connect a resistor and a capacitor to x in , and leave x out pin open. each pin of port d has an independent 1-bit wide i/o function. each pin has an out- put latch. for input use, set the latch of the specified bit to ?.?input is examined by skip decision. the output structure is n-channel open-drain. ports d 2 and d 3 are equipped with a pull-up function and a key-on wakeup function. both functions can be switched by software. ports d 2 and d 3 are also used as ports c and k, respectively. p ort p0 serves as a 4-bit i/o port, and it can be used as inputs when the output latch is set to ?.?the output structure is n-channel open-drain. port p0 has a key-on wakeup function and a pull-up function. both functions can be switched by software. p ort p1 serves as a 4-bit i/o port, and it can be used as inputs when the output latch is set to ?.?the output structure is n-channel open-drain. port p1 has a key-on wakeup function and a pull-up function. both functions can be switched by software. ports p1 2 and p1 3 are also used as cntr and int, respectively. p ort p2 serves as a 2-bit i/o port, and it can be used as inputs when the output latch is set to ?.?the output structure is n-channel open-drain. port p2 has a key-on wakeup function and a pull-up function. both functions can be switched by software. ports p2 0 and p2 1 are also used as a in0 and a in1 , respectively. 1 -bit i/o port. port c can be used as inputs when the output latch is set to ?.?the output structure is n-channel open-drain. port c has a key-on wakeup function and a pull-up function. both functions can be switched by software. port c is also used as port d 2 . 1 -bit i/o port. port k can be used as inputs when the output latch is set to ?.?the output structure is n-channel open-drain. port k has a key-on wakeup function and a pull-up function. both functions can be switched by software. port k is also used as port d 3 . cntr pin has the function to input the clock for the timer 2 event counter, and to out- put the timer 1 or timer 2 underflow signal divided by 2. this pin is also used as port p1 2 . int pin accepts external interrupts. it has the key-on wakeup function which can be switched by software. this pin is also used as port p1 3 . a/d converter analog input pins. a in0 and a in1 are also used as ports p2 0 and p2 1 , respectively. notes 1: pins except above have just single function. 2: the input/output of d 2 , d 3 , p1 2 and p1 3 can be used even when c, k, cntr (input) and int are selected. 3: the input of p1 2 can be used even when cntr (output) is selected. 4: the input/output of p2 0 , p2 1 can be used even when a in0 , a in1 are selected. pin d 2 d 3 p1 2 p1 3 multifunction c k cntr int multifunction pin c k cntr int multifunction d 2 d 3 p1 2 p1 3 pin p2 0 p2 1 multifunction a in0 a in1 pin a in0 a in1 multifunction p2 0 p2 1 x out system clock output output
4506 group rev.3.01 2005.02.07 page 5 of 111 rej03b0106-0301 definition of clock and cycle operation source clock the operation source clock is the source clock to operate this product. in this product, the following clocks are used. ?external ceramic resonator ?external rc oscillation ?clock (f(x in )) by the external clock ?clock (f(ring)) of the on-chip oscillator which is the internal oscillator. system clock the system clock is the basic clock for controlling this product. the system clock is selected by the bits 2 and 3 of the clock con- trol register mr. register mr system clock (note 1) f(x in ) or f(ring) f(x in )/2 or f(ring)/2 f(xin)/4 or f(ring)/4 f(xin)/8 or f(ring)/8 table selection of system clock port function port port d port p0 port p1 port p2 i/o unit 1 4 4 2 control instructions sd, rd szd, cld scp, rcp snzcp iak, oka op0a iap0 op1a iap1 op2a iap2 control registers pu2, k2 pu0, k0 pu1, k1 w6, i1 pu2, k2 q1 output structure n-channel open-drain n-channel open-drain n-channel open-drain n-channel open-drain input output i/o (4) i/o (4) i/o (4) i/o (2) remark pin d 0 , d 1 d 2 /c d 3 /k p0 0 ?0 3 p1 0 , p1 1 p1 2 /cntr, p1 3 /int p2 0 /a in0 p2 1 /a in1 notes 1: the on-chip oscillator clock is f(ring), the clock by the ceramic resonator, rc oscillation or external clock is f(x in ). 2: the default mode is selected after system is released from reset and is returned from ram back-up. mr 2 0 1 0 1 mr 3 0 0 1 1 operation mode high-speed mode middle-speed mode low-speed mode default mode instruction clock the instruction clock is a signal derived by dividing the system clock by 3. the one instruction clock cycle generates the one machine cycle. machine cycle the machine cycle is the standard cycle required to execute the instruction. built-in programmable pull-up functions key-on wakeup functions (programmable) built-in programmable pull-up functions key-on wakeup functions (programmable) built-in programmable pull-up functions key-on wakeup functions (programmable) built-in programmable pull-up functions key-on wakeup functions (programmable)
rev.3.01 2005.02.07 page 6 of 111 rej03b0106-0301 4506 group notes 1: when the ceramic resonator or the rc oscillation is not selected by program, system operates by the on-chip oscillator (internal oscillator). 2: when the pull-up function is left valid, the supply current is increased. do not select the pull-up function. 3: when the key-on wakeup function is left valid, the system returns from the ram back-up state immediately after going into th e ram back-up state. do not select the key-on wakeup function. 4: when selecting the key-on wakeup function, select also the pull-up function. 5: clear the bit 3 (i1 3 ) of register i1 to ??to disable to input to int pin (after reset: i1 3 = ?? (note when connecting to v ss ) connect the unused pins to v ss using the thickest wire at the shortest distance against noise. connections of unused pins connection connect to v ss . open. open. (output latch is set to ?.? open. (output latch is set to ?.? connect to v ss . open. (output latch is set to ?.? open. (output latch is set to ?.? connect to v ss . open. (output latch is set to ?.? open. (output latch is set to ?.? connect to v ss . open. (output latch is set to ?.? open. (output latch is set to ?.? connect to v ss . open. (output latch is set to ?.? open. (output latch is set to ?.? connect to v ss . open. (output latch is set to ?.? open. (output latch is set to ?.? connect to v ss . pin x in x out d 0 , d 1 d 2 /c d 3 /k p0 0 ?0 3 p1 0 , p1 1 p1 2 /cntr p1 3 /int p2 0 /a in0 p2 1 /a in1 usage condition system operates by the on-chip oscillator. (note 1) system operates by the external clock. (the ceramic resonator is selected with the cmck instruction.) system operates by the rc oscillator. (the rc oscillation is selected with the crck instruction.) system operates by the on-chip oscillator. (note 1) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. the input to int pin is disabled. (notes 4, 5) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the key-on wakeup function is not selected. (note 4) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3) the pull-up function and the key-on wakeup function are not selected. (notes 2, 3)
4506 group rev.3.01 2005.02.07 page 7 of 111 rej03b0106-0301 port block diagrams port block diagram (1) d 0 , d 1 s rq d 2 / c s rq skip decision (szd instruction) (note 1) pu2 2 s rq k2 2 pull-up transistor ( n o t e 2 ) l level detection circuit d 3 /k s rq pu2 3 d tq a 0 o k a i n s t r u c t i o n register a iak instruction k 2 3 ( n o t e 2 ) sd instruction d e c o d e r skip decision (szd instruction) r e g i s t e r y r d i n s t r u c t i o n cld instruction skip decision (snzcp instruction) sd instruction r d i n s t r u c t i o n c l d i n s t r u c t i o n d e c o d e r r e g i s t e r y scp instruction rcp instruction key-on wakeup skip decision (szd instruction) (note 1) pull-up transistor l level detection circuit sd instruction r d i n s t r u c t i o n c l d i n s t r u c t i o n decoder register y k e y - o n w a k e u p this symbol represents a parasitic diode on the port. 2: applied potential to ports d 2 /c and d 3 /k must be v dd or less. n o t e s 1 : (note 1)
rev.3.01 2005.02.07 page 8 of 111 rej03b0106-0301 4506 group port block diagram (2) i a p 0 i n s t r u c t i o n k0 i o p 0 a i n s t r u c t i o n r e g i s t e r a a i a i d t q ( n o t e 1 ) pu0 i ( n o t e 2 ) ( n o t e 2 ) ( n o t e 4 ) l l e v e l d e t e c t i o n c i r c u i t p 0 2 , p 0 3 iap0 instruction k0 j o p 0 a i n s t r u c t i o n r e g i s t e r a a j a j d t q ( n o t e 1 ) pu0 j p u l l - u p t r a n s i s t o r ( n o t e 3 ) ( n o t e 3 ) (note 4) k e y - o n w a k e u p l level detection circuit t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : i r e p r e s e n t s 0 o r 1 . 3 : j r e p r e s e n t s 2 o r 3 . 4 : a p p l i e d p o t e n t i a l t o p o r t p 0 m u s t b e v d d o r l e s s . notes 1: k e y - o n w a k e u p i n p u t p u l l - u p t r a n s i s t o r p 0 0 , p 0 1
4506 group rev.3.01 2005.02.07 page 9 of 111 rej03b0106-0301 port block diagram (3) p1 0 , p1 1 (note 3) register a a i ai d tq ( n o t e 2 ) k1 i pu1 i (note 2) ( n o t e 2 ) a 3 a 3 d t q pu1 3 p1 3 /int (note 3) k1 3 k 1 3 p 1 2 / c n t r ( n o t e 3 ) a 2 a 2 d tq k1 2 pu1 2 w6 0 0 1 w 2 0 w 2 1 i a p 1 i n s t r u c t i o n o p 1 a i n s t r u c t i o n ( n o t e 1 ) l level detection circuit t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : i r e p r e s e n t s 0 o r 1 . 3 : a p p l i e d p o t e n t i a l t o p o r t p 1 m u s t b e v d d o r l e s s . n o t e s 1 : k e y - o n w a k e u p i n p u t pull-up transistor r e g i s t e r a iap1 instruction op1a instruction (note 1) l l e v e l d e t e c t i o n c i r c u i t k e y - o n w a k e u p i n p u t pull-up transistor clock input for timer 2 event counter t i m e r 1 o r t i m e r 2 u n d e r f l o w s i g n a l d i v i d e d b y 2 l l e v e l d e t e c t i o n c i r c u i t key-on wakeup input p u l l - u p t r a n s i s t o r r e g i s t e r a i a p 1 i n s t r u c t i o n o p 1 a i n s t r u c t i o n e x t e r n a l 0 i n t e r r u p te x t e r n a l i n t e r r u p t c i r c u i t (note 1)
rev.3.01 2005.02.07 page 10 of 111 rej03b0106-0301 4506 group port block diagram (4) a 1 a 1 d t q p u 2 1 p 2 1 / a i n 1 k 2 1 a 0 a 0 d t q ( n o t e 3 ) p u 2 0 p2 0 /a in0 k 2 0 analog input register a i a p 2 i n s t r u c t i o n o p 2 a i n s t r u c t i o n ( n o t e 1 ) l l e v e l d e t e c t i o n c i r c u i t k e y - o n w a k e u p i n p u t pull-up transistor d e c o d e r register a iap2 instruction o p 2 a i n s t r u c t i o n (note 1) l level detection circuit key-on wakeup input pull-up transistor ( n o t e 3 ) analog input decoder t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : i r e p r e s e n t s 0 o r 1 . 3 : a p p l i e d p o t e n t i a l t o p o r t p 2 m u s t b e v d d o r l e s s . n o t e s 1 : q1 q 1
4506 group rev.3.01 2005.02.07 page 11 of 111 rej03b0106-0301 external interrupt circuit structure 0 1 i 1 2 0 1 e x f 0 i1 1 s n z i 0 i n s t r u c t i o n p 1 3 / i n t k1 3 i 1 3 ( n o t e ) w a k e u p s k i p r i s i n g f a l l i n g one-sided edge detection circuit both edges detection circuit e x t e r n a l 0 i n t e r r u p t t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . t i m e r 1 c o u n t s t a r t s y n c h r o n i z a t i o n c i r c u i t i n p u t
rev.3.01 2005.02.07 page 12 of 111 rej03b0106-0301 4506 group function block operations cpu (1) arithmetic logic unit (alu) the arithmetic logic unit alu performs 4-bit arithmetic such as 4- bit data addition, comparison, and operation, or operation, and bit manipulation. (2) register a and carry flag register a is a 4-bit register used for arithmetic, transfer, ex- change, and i/o operation. carry flag cy is a 1-bit flag that is set to 1 when there is a carry with the amc instruction (figure 1). it is unchanged with both a n instruction and am instruction. the value of a 0 is stored in carry flag cy with the rar instruction (fig- ure 2). carry flag cy can be set to 1 with the sc instruction and cleared to 0 with the rc instruction. (3) registers b and e register b is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register a. register e is an 8-bit register. it can be used for 8-bit data transfer with register b used as the high-order 4 bits and register a as the low-order 4 bits (figure 3). register e is undefined after system is released from reset and re- turned from the ram back-up. accordingly, set the initial value. (4) register d register d is a 3-bit register. it is used to store a 7-bit rom address together with register a and is used as a pointer within the specified page when the tabp p, bla p, or bmla p instruction is executed (figure 4). register d is undefined after system is released from reset and re- turned from the ram back-up. accordingly, set the initial value. fig. 1 amc instruction execution example fig. 2 rar instruction execution example fig. 3 registers a, b and register e fig. 4 tabp p instruction execution example ( c y ) ( m ( d p ) ) (a) addition alu < c a r r y > < r e s u l t > a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 tab instruction t e a b i n s t r u c t i o n t a b e i n s t r u c t i o n tba instruction r e g i s t e r br e g i s t e r a register b register a register e c ya 3 a 2 a 1 a 0 a 0 cy a 3 a 2 a 1 rar instruction < s e t > s c i n s t r u c t i o n < c l e a r > r c i n s t r u c t i o n s p e c i f y i n g a d d r e s s t a b p p i n s t r u c t i o n p 6 p 5 p 4 p 3 p 2 p 1 p 0 pc h dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 pc l i m m e d i a t e f i e l d v a l u e p t h e c o n t e n t s o f r e g i s t e r d rom 840 middle-order 4 bits l o w - o r d e r 4 b i t s r e g i s t e r a ( 4 ) r e g i s t e r b ( 4 ) the contents of register a
4506 group rev.3.01 2005.02.07 page 13 of 111 rej03b0106-0301 (5) stack registers (sk s ) and stack pointer (sp) stack registers (sks) are used to temporarily store the contents of program counter (pc) just before branching until returning to the original routine when; branching to an interrupt service routine (referred to as an inter- rupt service routine), performing a subroutine call, or executing the table reference instruction (tabp p). stack registers (sks) are eight identical registers, so that subrou- tines can be nested up to 8 levels. however, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. accordingly, be care- ful not to over the stack when performing these operations together. the contents of registers sks are destroyed when 8 lev- els are exceeded. the register sk nesting level is pointed automatically by 3-bit stack pointer (sp). the contents of the stack pointer (sp) can be transferred to register a with the tasp instruction. figure 5 shows the stack registers (sks) structure. figure 6 shows the example of operation at subroutine call. (6) interrupt stack register (sdp) interrupt stack register (sdp) is a 1-stage register. when an inter- rupt occurs, this register (sdp) is used to temporarily store the contents of data pointer, carry flag, skip flag, register a, and regis- ter b just before an interrupt until returning to the original routine. unlike the stack registers (sks), this register (sdp) is not used when executing the subroutine call instruction and the table refer- ence instruction. (7) skip flag skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. when an interrupt oc- curs, the contents of skip flag is stored automatically in the interrupt stack register (sdp) and the skip condition is retained. fig. 5 stack registers (sks) structure fig. 6 example of operation at subroutine call s k 0 s k 1 s k 2 s k 3 s k 4 s k 5 s k 6 sk 7 ( s p ) = 0 ( s p ) = 1 ( s p ) = 2 ( s p ) = 3 ( s p ) = 4 ( s p ) = 5 ( s p ) = 6 (sp) = 7 program counter (pc) e x e c u t i n g r t i n s t r u c t i o n e x e c u t i n g b m i n s t r u c t i o n s t a c k p o i n t e r ( s p ) p o i n t s 7 a t r e s e t o r r e t u r n i n g f r o m r a m b a c k - u p m o d e . i t p o i n t s 0 b y e x e c u t i n g t h e f i r s t b m i n s t r u c t i o n , a n d t h e c o n t e n t s o f p r o g r a m c o u n t e r i s s t o r e d i n s k 0 . w h e n t h e b m i n s t r u c t i o n i s e x e c u t e d a f t e r e i g h t s t a c k r e g i s t e r s a r e u s e d ( ( s p ) = 7 ) , ( s p ) = 0 a n d t h e c o n t e n t s o f s k 0 i s d e s t r o y e d . returning to the bm instruction execution address with the rt instruction, and the bm instruction becomes the nop instruction. (sp) note :
rev.3.01 2005.02.07 page 14 of 111 rej03b0106-0301 4506 group (8) program counter (pc) program counter (pc) is used to specify a rom address (page and address). it determines a sequence in which instructions stored in rom are read. it is a binary counter that increments the number of instruction bytes each time an instruction is executed. however, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table refer- ence instruction (tabp p) is executed. program counter consists of pc h (most significant bit to bit 7) which specifies to a rom page and pc l (bits 6 to 0) which speci- fies an address within a page. after it reaches the last address (address 127) of a page, it specifies address 0 of the next page (figure 7). make sure that the pc h does not specify after the last page of the built-in rom. (9) data pointer (dp) data pointer (dp) is used to specify a ram address and consists of registers z, x, and y. register z specifies a ram file group, reg- ister x specifies a file, and register y specifies a ram digit (figure 8). register y is also used to specify the port d bit position. when using port d, set the port d bit position to register y certainly and execute the sd, rd, or szd instruction (figure 9). note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the ram back-up. after system is returned from the ram back-up, set these registers. fig. 7 program counter (pc) structure fig. 8 data pointer (dp) structure fig. 9 sd instruction execution example p 5 p 4 p 3 p 2 p 1 p 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 p r o g r a m c o u n t e r p c h s p e c i f y i n g p a g e pc l specifying address p 6 z 1 z 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 d a t a p o i n t e r ( d p ) register z (2) r e g i s t e r x ( 4 ) register y (4) s p e c i f y i n g r a m d i g i t s p e c i f y i n g r a m f i l e specifying ram file group 0 01 1 set specifying bit position port d output latch register y (4) d 2 d 3 d 1 d 0 0
4506 group rev.3.01 2005.02.07 page 15 of 111 rej03b0106-0301 program memoy (rom) the program memory is a mask rom. 1 word of rom is composed of 10 bits. rom is separated every 128 words by the unit of page (addresses 0 to 127). table 1 shows the rom size and pages. fig- ure 10 shows the rom map of m34506m4. table 1 rom size and pages part number m34506m2 m34506m4 m34506e4 rom (prom) size ( ? fig. 10 rom map of m34506m4/m34506e4 fig. 11 page 1 (addresses 0080 16 to 00ff 16 ) structure 0 87654321 0 0 0 0 1 6 0 0 8 0 1 6 0 1 7 f 1 6 subroutine special page 0 0 7 f 1 6 0 0 f f 1 6 0 1 0 0 1 6 0 1 8 0 1 6 p a g e 1 p a g e 2 p a g e 0 p a g e 3 p a g e 3 1 0 f f f 1 6 i n t e r r u p t a d d r e s s p a g e 9 90 87654321 external 0 interrupt address 0080 16 0082 16 timer 1 interrupt address 0084 16 timer 2 interrupt address 0 0 8 6 1 6 0088 16 0 0 8 a 1 6 00ff 16 a/d interrupt address 008c 16 008e 16
rev.3.01 2005.02.07 page 16 of 111 rej03b0106-0301 4506 group data memory (ram) 1 word of ram is composed of 4 bits, but 1-bit manipulation (with the sb j, rb j, and szb j instructions) is enabled for the entire memory area. a ram address is specified by a data pointer. the data pointer consists of registers z, x, and y. set a value to the data pointer certainly when executing an instruction to access ram. table 2 shows the ram size. figure 12 shows the ram map. note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the ram back-up. after system is returned from the ram back-up, set these registers. fig. 12 ram map table 2 ram size part number m34506m2 m34506m4 m34506e4 ram size 128 words ? ? ? ?
4506 group rev.3.01 2005.02.07 page 17 of 111 rej03b0106-0301 interrupt function the interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. an interrupt occurs when the following 3 conditions are satisfied. an interrupt activated condition is satisfied (request flag = 1 ) interrupt enable bit is enabled ( 1 ) interrupt enable flag is enabled (inte = 1 ) table 3 shows interrupt sources. (refer to each interrupt request flag for details of activated conditions.) (1) interrupt enable flag (inte) the interrupt enable flag (inte) controls whether the every inter- rupt enable/disable. interrupts are enabled when inte flag is set to 1 with the ei instruction and disabled when inte flag is cleared to 0 with the di instruction. when any interrupt occurs, the inte flag is automatically cleared to 0, so that other interrupts are disabled until the ei instruction is executed. (2) interrupt enable bit use an interrupt enable bit of interrupt control registers v1 and v2 to select the corresponding interrupt or skip instruction. table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. table 5 shows the interrupt enable bit function. (3) interrupt request flag when the activated condition for each interrupt is satisfied, the cor- responding interrupt request flag is set to 1. each interrupt request flag is cleared to 0 when either; an interrupt occurs, or the next instruction is skipped with a skip instruction. each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the inte flag or its in- terrupt enable bit. once set, the interrupt request flag retains set until a clear condition is satisfied. accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. if more than one interrupt request flag is set when the interrupt dis- able state is released, the interrupt priority level is as follows shown in table 3. table 3 interrupt sources activated condition level change of int pin timer 1 underflow timer 2 underflow completion of a/d conversion priority level 1 2 3 4 interrupt name external 0 interrupt timer 1 interrupt timer 2 interrupt a/d interrupt table 5 interrupt enable bit function occurrence of interrupt enabled disabled skip instruction invalid valid interrupt enable bit 1 0 interrupt address address 0 in page 1 address 4 in page 1 address 6 in page 1 address c in page 1 table 4 interrupt request flag, interrupt enable bit and skip in- struction interrupt request flag exf0 t1f t2f adf interrupt name external 0 interrupt timer 1 interrupt timer 2 interrupt a/d interrupt skip instruction snz0 snzt1 snzt2 snzad interrupt enable bit v1 0 v1 2 v1 3 v2 2
rev.3.01 2005.02.07 page 18 of 111 rej03b0106-0301 4506 group (4) internal state during an interrupt the internal state of the microcomputer during an interrupt is as fol- lows (figure 14). program counter (pc) an interrupt address is set in program counter. the address to be executed when returning to the main routine is automatically stored in the stack register (sk). interrupt enable flag (inte) inte flag is cleared to 0 so that interrupts are disabled. interrupt request flag only the request flag for the current interrupt source is cleared to 0. data pointer, carry flag, skip flag, registers a and b the contents of these registers and flags are stored automatically in the interrupt stack register (sdp). (5) interrupt processing when an interrupt occurs, a program at an interrupt address is ex- ecuted after branching a data store sequence to stack register. write the branch instruction to an interrupt service routine at an in- terrupt address. use the rti instruction to return from an interrupt service routine. interrupt enabled by executing the ei instruction is performed after executing 1 instruction (just after the next instruction is executed). accordingly, when the ei instruction is executed just before the rti instruction, interrupts are enabled after returning the main routine. (refer to figure 13) fig. 13 program example of interrupt processing program counter (pc) ............................................................... each interrupt address stack register (sk) .................................................................................................... interrupt enable flag (inte) .................................................................. 0 (interrupt disabled) interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 data pointer, carry flag, registers a and b, skip flag ........ stored in the interrupt stack register (sdp) automatically the address of main routine to be executed when returning fig. 15 interrupt system diagram fig. 14 internal state when interrupt occurs t1f v1 2 e x f 0 v1 0 address 4 in page 1 address 0 in page 1 t2f v1 3 address 6 in page 1 a d fv 2 2 t i m e r 1 u n d e r f l o w t i m e r 2 u n d e r f l o w c o m p l e t i o n o f a / d c o n v e r s i o n address c in page 1 request flag (state retained) e n a b l e b i t e n a b l e f l a g inte a c t i v a t e d c o n d i t i o n int pin (l e i r t i i n t e r r u p t s e r v i c e r o u t i n e interrupt occurs interrupt is enabled m a i n r o u t i n e : i n t e r r u p t e n a b l e d s t a t e : i n t e r r u p t d i s a b l e d s t a t e
4506 group rev.3.01 2005.02.07 page 19 of 111 rej03b0106-0301 (6) interrupt control registers interrupt control register v1 interrupt enable bits of external 0, timer 1 and timer 2 are as- signed to register v1. set the contents of this register through register a with the tv1a instruction. the tav1 instruction can be used to transfer the contents of register v1 to register a. interrupt control register v2 the a/d interrupt enable bit is assigned to register v2. set the contents of this register through register a with the tv2a instruc- tion. the tav2 instruction can be used to transfer the contents of register v2 to register a. table 6 interrupt control registers v1 3 v1 2 v1 1 v1 0 v2 3 v2 2 v2 1 v2 0 not used a/d interrupt enable bit not used not used interrupt control register v1 timer 2 interrupt enable bit timer 1 interrupt enable bit not used external 0 interrupt enable bit notes 1: r represents read enabled, and w represents write enabled. 2: these instructions are equivalent to the nop instrucion. interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) (note 2) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) (note 2) this bit has no function, but read/write is enabled. interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) (note 2) this bit has no function, but read/write is enabled. interrupt disabled (snzad instruction is valid) interrupt enabled (snzad instruction is invalid) (note 2) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. 0 1 0 1 0 1 0 1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 interrupt control register v2 r/w at ram back-up : 0000 2 at reset : 0000 2 0 1 0 1 0 1 0 1 (7) interrupt sequence interrupts only occur when the respective inte flag, interrupt en- able bits (v1 0 , v1 2 , v1 3 , v2 2 ), and interrupt request flag are 1. the interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. the interrupt occurs after 3 machine cycles only when the three interrupt conditions are sat- isfied on execution of other than one-cycle instructions (refer to figure 16).
rev.3.01 2005.02.07 page 20 of 111 rej03b0106-0301 4506 group fig. 16 interrupt sequence t 1 f , t 2 f a d f i n t e x f 0 t 1 t 2 t 3 t 1 t 2 t 3 t 2 t 3 t 1 t 1 t 2 t 3 t 1 t 2 s y s t e m c l o c k t h e p r o g r a m s t a r t s f r o m t h e i n t e r r u p t a d d r e s s . i n t e r r u p t e n a b l e d s t a t e
4506 group rev.3.01 2005.02.07 page 21 of 111 rej03b0106-0301 table 7 external interrupt activated conditions name external 0 interrupt input pin int activated condition when the next waveform is input to int pin falling waveform ( h l ) rising waveform ( l h ) both rising and falling waveforms valid waveform selection bit i1 1 i1 2 fig. 17 external interrupt circuit structure external interrupts the 4506 group has the external 0 interrupt. an external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). the external interrupt can be controlled with the interrupt control register i1. 0 1 i 1 2 0 1 exf0 i 1 1 snzi0 instruction p 1 3 / i n t k1 3 i 1 3 ( n o t e ) wakeup skip r i s i n g f a l l i n g o n e - s i d e d e d g e d e t e c t i o n c i r c u i t b o t h e d g e s d e t e c t i o n c i r c u i t e x t e r n a l 0 i n t e r r u p t this symbol represents a parasitic diode on the port. t i m e r 1 c o u n t s t a r t s y n c h r o n i z a t i o n c i r c u i t i n p u t (1) external 0 interrupt request flag (exf0) external 0 interrupt request flag (exf0) is set to 1 when a valid waveform is input to int pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 16). the state of exf0 flag can be examined with the skip instruction (snz0). use the interrupt control register v1 to select the interrupt or the skip instruction. the exf0 flag is cleared to 0 when an in- terrupt occurs or when the next instruction is skipped with the skip instruction. external 0 interrupt activated condition external 0 interrupt activated condition is satisfied when a valid waveform is input to int pin. the valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the external 0 interrupt is as follows. ? 1 for the int pin to be in the input enabled state. ? ? 0 with the snz0 instruction. ? ? 1. the external 0 interrupt is now enabled. now when a valid wave- form is input to the int pin, the exf0 flag is set to 1 and the external 0 interrupt occurs.
rev.3.01 2005.02.07 page 22 of 111 rej03b0106-0301 4506 group (2) external interrupt control registers interrupt control register i1 register i1 controls the valid waveform for the external 0 inter- rupt. set the contents of this register through register a with the ti1a instruction. the tai1 instruction can be used to transfer the contents of register i1 to register a. table 8 external interrupt control register i1 3 i1 2 i1 1 i1 0 int pin input control bit (note 2) interrupt valid waveform for int pin/ return level selection bit (note 2) int pin edge detection circuit control bit int pin timer 1 control enable bit interrupt control register i1 r/w at ram back-up : state retained at reset : 0000 2 int pin input disabled int pin input enabled falling waveform ( l level of int pin is recognized with the snzi0 instruction)/ l level rising waveform ( h level of int pin is recognized with the snzi0 instruction)/ h level one-sided edge detected both edges detected disabled enabled 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. accordingly, clear exf0 flag with the snz0 in- struction when the bit 0 (v1 0 ) of register v1 to 0 . in this time, set the nop instruction after the snz0 instruction, for the case when a skip is performed with the snz0 instruction.
4506 group rev.3.01 2005.02.07 page 23 of 111 rej03b0106-0301 (3) notes on interrupts ? depending on the input state of the p1 3 /int pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 18 ? 0 after executing at least one instruction (refer to figure 18 ? ? ??? ? ??? ? ? ? fig. 18 external 0 interrupt program example-1 ? 0 , the ram back-up mode is selected and the input of int pin is disabled, be careful about the following notes. when the key-on wakeup function of port p1 3 is not used (regis- ter k1 3 = 0 ), clear bits 2 and 3 of register i1 before system enters to the ram back-up mode. (refer to figure 19 ? la 0 ; (00 ?? ? ? fig. 19 external 0 interrupt program example-2 ? depending on the input state of the p1 3 /int pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 20 ? 0 after executing at least one instruction (refer to figure 20 ? ? ??? ? ? ?? ? ? ? fig. 20 external 0 interrupt program example-3
rev.3.01 2005.02.07 page 24 of 111 rej03b0106-0301 4506 group timers the 4506 group has the following timers. programmable timer the programmable timer has a reload register and enables the frequency dividing ratio to be set. it is decremented from a set- ting value n. when it underflows (count to n + 1), a timer interrupt request flag is set to 1, new data is loaded from the reload reg- ister, and count continues (auto-reload function). fixed dividing frequency timer the fixed dividing frequency timer has the fixed frequency divid- ing ratio (n). an interrupt request flag is set to 1 after every n count of a count pulse. fig. 21 auto-reload function ff 16 n 00 16 n : c o u n t e r i n i t i a l v a l u e c o u n t s t a r t s r e l o a d reload 1st underflow 2nd underflow n+1 coun t n+1 coun t t i m e a n i n t e r r u p t o c c u r s o r a s k i p i n s t r u c t i o n i s e x e c u t e d . t i m e r i n t e r r u p t r e q u e s t f l a g t h e c o n t e n t s o f c o u n t e r 1 0 count source instruction clock prescaler output (orclk) timer 1 underflow prescaler output (orclk) cntr input system clock instruction clock structure frequency divider 8-bit programmable binary down counter (link to int input) 8-bit programmable binary down counter 16-bit fixed dividing frequency binary down counter circuit prescaler timer 1 timer 2 16-bit timer use of output signal timer 1 and 2 count sources timer 2 count source cntr output timer 1 interrupt cntr output timer 2 interrupt watchdog timer (the 16th bit is counted twice) frequency dividing ratio 4, 16 1 to 256 1 to 256 65536 control register w1 w1 w2 w6 w2 w6 the 4506 group timer consists of the following circuits. prescaler : frequency divider timer 1 : 8-bit programmable timer timer 2 : 8-bit programmable timer (timers 1 and 2 have the interrupt function, respectively) 16-bit timer prescaler and timers 1 and 2 can be controlled with the timer con- trol registers w1, w2 and w6. the 16-bit timer is a free counter which is not controlled with the control register. each function is described below. table 9 function related timers
4506 group rev.3.01 2005.02.07 page 25 of 111 rej03b0106-0301 fig. 22 timers structure 1 6 - b i t t i m e r ( w d t ) 11 6 i n s t r u c t i o n c l o c k q s q t d w d f 2 o r c l k x i n 1 / 4 1 / 1 6 w1 3 0 1 0 1 w 1 2 division circuit divided by 8 divided by 4 divided by 2 p 1 2 / c n t r p 1 2 o u t p u t 0 1 w 6 0 0 1 w 2 3 (tr1ab) t1f t 2 f ( t a b 1 ) 0 1 w1 1 w 2 1 , w 2 0 1 1 1 0 0 1 0 0 1 / 2 0 1 w 6 1 1 / 2 (t2ab) ( t a b 2 ) (tab1) (tab2) ( n o t e 2 ) (note 2) t 1 a bt1ab mr 3 , mr 2 0 0 0 1 1 0 1 1 w 1 0 0 1 q r s 0 1 i 1 2 0 1 i 1 1 p 1 3 / i n t (note 1) i1 0 w2 2 t i m e r 1 u n d e r f l o w s i g n a l i 1 3 r q r s w e f r e s e t s i g n a l ( n o t e 5 ) d w d t i n s t r u c t i o n + w r s t i n s t r u c t i o n ( n o t e 4 ) r wdf1 wrst instruction (note 3) t i m e r 1 ( 8 ) t i m e r 1 i n t e r r u p t r e l o a d r e g i s t e r r 1 ( 8 ) r e g i s t e r b register a timer 2 (8) reload register r2 (8) register b register a t i m e r 2 i n t e r r u p t d a t a i s s e t a u t o m a t i c a l l y f r o m e a c h r e l o a d r e g i s t e r w h e n t i m e r 1 o r 2 u n d e r f l o w s ( a u t o - r e l o a d f u n c t i o n ) notes 1: timer 1 count start synchronous circuit is set by the valid edge of p1 3 /int pin selected by bits 1 (i1 1 ) and 2 (i1 2 ) of register i1. 2: count source is stopped by clearing to 0. 3: when the wrst instruction is executed at wdf1 flag = 1, wdf1 flag is cleared to 0 and the next instruction is skipped. when the wrst instruction is executed at wdf1 flag = 0, skip is not executed. 4: when the dwdt and wrst instructions are executed continuously, wef flag is cleared to 0 and reset by watchdog timer is not executed. 5: the wef flag is set to 1 at system reset or ram back-up mode. i n s t r u c t i o n c l o c k i n t e r n a l c l o c k g e n e r a t i n g c i r c u i t ( d i v i d e d b y 3 ) prescaler o n e - s i d e d e d g e d e t e c t i o n c i r c u i t both edges detection circuit f a l l i n g r i s i n g c l o c k g e n e r a t i o n c i r c u i t s y s t e m c l o c k timer 1 underflow signal t i m e r 2 u n d e r f l o w s i g n a l reset signal watchdog reset signal
rev.3.01 2005.02.07 page 26 of 111 rej03b0106-0301 4506 group table 10 timer control registers 0 1 0 1 0 1 0 1 w2 1 0 0 1 1 stop (state initialized) operating instruction clock divided by 4 instruction clock divided by 16 stop (state retained) operating count start synchronous circuit not selected count start synchronous circuit selected prescaler control bit prescaler dividing ratio selection bit timer 1 control bit timer 1 count start synchronous circuit control bit stop (state retained) operating count auto-stop circuit not selected count auto-stop circuit selected count source timer 1 underflow signal prescaler output (orclk) cntr input system clock timer 2 control bit timer 1 count auto-stop circuit selection bit (note 2) timer 2 count source selection bits 0 1 0 1 w2 0 0 1 0 1 w1 3 w1 2 w1 1 w1 0 w2 3 w2 2 w2 1 w2 0 timer control register w1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 timer control register w2 r/w at ram back-up : state retained at reset : 0000 2 this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. timer 1 underflow signal divided by 2 output timer 2 underflow signal divided by 2 output p1 2 (i/o)/cntr input (note 3) p1 2 (input)/cntr input/output (note 3) not used not used cntr output selection bit p1 2 /cntr function selection bit 0 1 0 1 0 1 0 1 timer control register w6 r/w at ram back-up : state retained at reset : 0000 2 notes 1: r represents read enabled, and w represents write enabled. 2: this function is valid only when the timer 1 count start synchronization circuit is selected. 3: cntr input is valid only when cntr input is selected as the timer 2 count source. (1) timer control registers timer control register w1 register w1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ra- tio and count operation of prescaler. set the contents of this register through register a with the tw1a instruction. the taw1 instruction can be used to transfer the contents of register w1 to register a. timer control register w2 register w2 controls the selection of timer 1 count auto-stop cir- cuit, and the count operation and count source of timer 2. set the contents of this register through register a with the tw2a instruc- tion. the taw2 instruction can be used to transfer the contents of register w2 to register a. timer control register w6 register w6 controls the p1 2 /cntr pin function and the selec- tion of cntr output. set the contents of this register through register a with the tw6a instruction. the taw6 instruction can be used to transfer the contents of register w6 to register a.. (2) prescaler prescaler is a frequency divider. its frequency dividing ratio can be selected. the count source of prescaler is the instruction clock. use the bit 2 of register w1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. prescaler is initialized, and the output signal (orclk) stops when the bit 3 of register w1 is cleared to 0. w6 3 w6 2 w6 1 w6 0
4506 group rev.3.01 2005.02.07 page 27 of 111 rej03b0106-0301 (6) count start synchronization circuit (timer 1) timer 1 has the count start synchronous circuit which synchronizes the input of int pin, and can start the timer count operation. timer 1 count start synchronous circuit function is selected by set- ting the bit 0 of register w1 to 1. the control by int pin input can be performed by setting the bit 0 of register i1 to 1. the count start synchronous circuit is set by level change ( h l or l h ) of int pin input. this valid waveform is selected by bits 1 (i1 1 ) and 2 (i1 2 ) of register i1 as follows; i1 1 = 0 : synchronized with one-sided edge (falling or rising) i1 1 = 1 : synchronized with both edges (both falling and rising) when register i1 1 = 0 (synchronized with the one-sided edge), the ris- ing or falling waveform can be selected by the bit 2 of register i1; i1 2 = 0 : falling waveform i1 2 = 1 : rising waveform when timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to int pin. once set, the count start synchronous circuit is cleared by clearing the bit i1 0 to 0 or reset. however, when the count auto-stop circuit is selected (register w2 2 = 1 ), the count start synchronous circuit is cleared (auto-stop) at the timer 1 underflow. (7) count auto-stop circuit (timer 1) timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start syn- chronous circuit is used. the count auto-stop cicuit is valid by setting the bit 2 of register w2 to 1 . it is cleared by the timer 1 underflow and the count source to timer 1 is stopped. this function is valid only when the timer 1 count start synchronous circuit is selected. (3) timer 1 (interrupt function) timer 1 is an 8-bit binary down counter with the timer 1 reload reg- ister (r1). data can be set simultaneously in timer 1 and the reload register (r1) with the t1ab instruction. stop counting and then ex- ecute the t1ab instruction to set data to timer 1. data can be written to reload register (r1) with the tr1ab instruction. when writing data to reload register r1 with the tr1ab instruction, the downcount after the underflow is started from the setting value of reload register r1. timer 1 starts counting after the following process; ? ? 1. however, int pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register w1 to 1. also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 2 of register w2 to 1. when a value set is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes 0 ), the timer 1 interrupt request flag (t1f) is set to 1, new data is loaded from reload register r1, and count continues (auto-reload function). data can be read from timer 1 with the tab1 instruction. when reading the data, stop the counter and then execute the tab1 in- struction. (4) timer 2 (interrupt function) timer 2 is an 8-bit binary down counter with the timer 2 reload reg- ister (r2). data can be set simultaneously in timer 2 and the reload register (r2) with the t2ab instruction. stop counting and then ex- ecute the t2ab instruction to set data to timer 2. timer 2 starts counting after the following process; ? ? ? 1. when a value set is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes 0 ), the timer 2 interrupt request flag (t2f) is set to 1, new data is loaded from reload register r2, and count continues (auto-reload function). data can be read from timer 2 with the tab2 instruction. when reading the data, stop the counter and then execute the tab2 in- struction. (5) timer interrupt request flags (t1f, t2f) each timer interrupt request flag is set to 1 when each timer underflows. the state of these flags can be examined with the skip instructions (snzt1, snzt2). use the interrupt control register v1 to select an interrupt or a skip instruction. an interrupt request flag is cleared to 0 when an interrupt occurs or when the next instruction is skipped with a skip instruction.
rev.3.01 2005.02.07 page 28 of 111 rej03b0106-0301 4506 group fig. 23 count timing diagram at cntr input (8) timer input/output pin (p1 2 /cntr pin) cntr pin is used to input the timer 2 count source and output the timer 1 and timer 2 underflow signal divided by 2. the p1 2 /cntr pin function can be selected by bit 0 of register w6. the cntr output signal can be selected by bit 1 of register w6. when the cntr input is selected for timer 2 count source, timer 2 counts the falling waveform of cntr input. (9) precautions note the following for the use of timers. prescaler stop the prescaler operation to change its frequency dividing ratio. count source stop timer 1 or 2 counting to change its count source. reading the count value stop timer 1 or 2 counting and then execute the tab1 or tab2 in- struction to read its data. writing to the timer stop timer 1 or 2 counting and then execute the t1ab or t2ab in- struction to write its data. writing to reload register r1 when writing data to reload register r1 while timer 1 is operating, avoid a timing when timer 1 underflows. 03 16 02 16 01 16 00 16 ff 16 fe 16 cntr input timer 2 count timer 2 interrupt request flag (t2f) (note) note: this is an example when ff 16 is set to timer 2 reload register r2 l. timer 1 and timer 2 count start timing and count time when op- eration starts count starts from the first rising edge of the count source (2) af- ter timer 1 and timer 2 operations start (1). time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. when selecting cntr input as the count source of timer 2, timer 2 operates synchronizing with the falling edge of cntr input. fig. 24 t imer count start timing and count time when opera- tion starts (t1, t2) (1) timer count source timer value timer underflow signal 321 032 103 2 count source (cntr input) (2) (3) (4)
4506 group rev.3.01 2005.02.07 page 29 of 111 rej03b0106-0301 fig. 25 watchdog timer function watchdog timer watchdog timer provides a method to reset the system when a pro- gram run-away occurs. watchdog timer consists of timer wdt(16-bit binary counter), watchdog timer enable flag (wef), and watchdog timer flags (wdf1, wdf2). the timer wdt downcounts the instruction clocks as the count source from ffff 16 after system is released from reset. after the count is started, when the timer wdt underflow occurs (after the count value of timer wdt reaches ffff 16 , the next count pulse is input), the wdf1 flag is set to 1. if the wrst instruction is never executed until the timer wdt un- derflow occurs (until timer wdt counts 65534), wdf2 flag is set to 1, and the reset pin outputs l level to reset the microcom- puter. execute the wrst instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. when the wef flag is set to 1 after system is released from reset, the watchdog timer function is valid. when the dwdt instruction and the wrst instruction are ex- ecuted continuously, the wef flag is cleared to 0 and the watchdog timer function is invalid. the wef flag is set to "1" at system reset or ram back-up mode. the wrst instruction has the skip function. when the wrst in- struction is executed while the wdf1 flag is 1 , the wdf1 flag is cleared to 0 and the next instruction is skipped. when the wrst instruction is executed while the wdf1 flag is 0 , the next instruction is not skipped. the skip function of the wrst instruction can be used even when the watchdog timer function is invalid. 6 5 5 3 4 c o u n t ( n o t e ) v a l u e o f 1 6 - b i t t i m e r ( w d t ) w d f 1 f l a g ? ? ? ? ? 1 . ? 0 , t h e n e x t i n s t r u c t i o n i s s k i p p e d . ? 1 , w d f 2 f l a g i s s e t t o 1 a n d t h e w a t c h d o g r e s e t s i g n a l i s o u t p u t . ? o n b y t h e w a t c h d o g r e s e t s i g n a l a n d s y s t e m r e s e t i s e x e c u t e d . n o t e : t h e n u m b e r o f c o u n t i s e q u a l t o t h e n u m b e r o f m a c h i n e c y c l e b e c a u s e t h e c o u n t s o u r c e o f w a t c h d o g t i m e r i s t h e i n s t r u c t i o n c l o c k . f f f f 1 6 0 0 0 0 1 6 ? ? ?
rev.3.01 2005.02.07 page 30 of 111 rej03b0106-0301 4506 group fig. 26 program example to start/stop watchdog timer fig. 27 program example to enter the ram back-up mode when using the watchdog timer wrst ; wdf1 flag cleared nop di ; interrupt disabled epof ; pof instruction enabled pof2 when the watchdog timer is used, clear the wdf1 flag at the pe- riod of 65534 machine cycles or less with the wrst instruction. when the watchdog timer is not used, execute the dwdt instruc- tion and the wrst instruction continuously (refer to figure 26). the watchdog timer is not stopped with only the dwdt instruction. the contents of wdf1 flag and timer wdt are initialized at the ram back-up mode. when using the watchdog timer and the ram back-up mode, ini- tialize the wdf1 flag with the wrst instruction just before the microcomputer enters the ram back-up state (refer to figure 27) the watchdog timer function is valid after system is returned from the ram back-up. when not using the watchdog timer function, ex- ecute the dwdt instruction and the wrst instruction continuously every system is returned from the ram back-up, and stop the watchdog timer function. wrst ; wdf1 flag cleared di dwdt ; wat chdog timer function enabled/disabled wrst ; wef and wdf1 flags cleared
4506 group rev.3.01 2005.02.07 page 31 of 111 rej03b0106-0301 a/d converter the 4506 group has a built-in a/d conversion circuit that performs conversion by 10-bit successive comparison method. table 11 shows the characteristics of this a/d converter. this a/d converter can also be used as an 8-bit comparator to compare analog volt- ages input from the analog input pin with preset values. table 11 a/d converter characteristics characteristics successive comparison method 10 bits linearity error: 2lsb differential non-linearity error: 0.9lsb 46.5 fig. 28 a/d conversion circuit structure v s s v d d dac d a c o n v e r t e r t a b a d 1/6 q1 3 q1 1 q1 0 q1 2 t a d a b 0 1 4 4 4 4 8 8 8 01 1 8 1 0 q1 3 q 1 3 0 1 q 1 3 8 ( n o t e 1 ) 8 2 t a l a q1 3 taq1 t q 1 a adf (1) p 2 0 / a i n 0 2 1 0 10 p 2 1 / a i n 1 i a p 2 ( p 2 0 , p 2 1 ) o p 2 a ( p 2 0 , p 2 1 ) register a (4) register b (4) dac operation signal comparator 2- c h a n n el m u l t i - p l e x e d an a l o g s w i t c h instruction clock a/d control circuit successive comparison register (ad) (10) a/d interrupt comparator register (8) n o t e s 1 : t h i s s w i t c h i s t u r n e d o n o n l y w h e n a / d c o n v e r t e r i s o p e r a t i n g a n d g e n e r a t e s t h e c o m p a r i s o n v o l t a g e . 2 : w r i t i n g / r e a d i n g d a t a t o t h e c o m p a r a t o r r e g i s t e r i s p o s s i b l e o n l y i n t h e c o m p a r a t o r m o d e ( q 1 3 = 1 ) . t h e v a l u e o f t h e c o m p a r a t o r r e g i s t e r i s r e t a i n e d e v e n w h e n t h e m o d e i s s w i t c h e d t o t h e a / d c o n v e r s i o n m o d e ( q 1 3 = 0 ) b e c a u s e i t i s s e p a r a t e d f r o m t h e s u c c e s s i v e c o m p a r i s o n r e g i s t e r ( a d ) . a l s o , t h e r e s o l u t i o n i n t h e c o m p a r a t o r m o d e i s 8 b i t s b e c a u s e t h e c o m p a r a t o r r e g i s t e r c o n s i s t s o f 8 b i t s . ( n o t e 2 )
rev.3.01 2005.02.07 page 32 of 111 rej03b0106-0301 4506 group q1 3 q1 2 a/d control register q1 a/d operation mode selection bit not used analog input pin selection bits at reset : 0000 2 at ram back-up : state retained 0 1 0 1 q1 1 0 0 1 1 a/d conversion mode comparator mode this bit has no function, but read/write is enabled. selected pins a in0 a in1 not available not available note: r represents read enabled, and w represents write enabled. q1 0 0 1 0 1 (1) operating at a/d conversion mode the a/d conversion mode is set by setting the bit 3 of register q1 to 0. (2) successive comparison register ad register ad stores the a/d conversion result of an analog input in 10-bit digital data format. the contents of the high-order 8 bits of this register can be stored in register b and register a with the tabad instruction. the contents of the low-order 2 bits of this reg- ister can be stored into the high-order 2 bits of register a with the tala instruction. however, do not execute these instructions dur- ing a/d conversion. when the contents of register ad is n, the logic value of the com- parison voltage v ref generated from the built-in da converter can be obtained with the reference voltage v dd by the following for- mula: logic value of comparison voltage v ref v ref = ? table 12 a/d control registers (3) a/d conversion completion flag (adf) a/d conversion completion flag (adf) is set to 1 when a/d con- version completes. the state of adf flag can be examined with the skip instruction (snzad). use the interrupt control register v2 to select the interrupt or the skip instruction. the adf flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction. (4) a/d conversion start instruction (adst) a/d conversion starts when the adst instruction is executed. the conversion result is automatically stored in the register ad. (5) a/d control register q1 register q1 is used to select the operation mode and one of ana- log input pins. q1 1 q1 0 (6) operation description a/d conversion is started with the a/d conversion start instruction (adst). the internal operation during a/d conversion is as follows: ? 000 16 . ? 1, and the comparison voltage v ref is compared with the analog input volt- age v in . ? 1. when the comparison result is v ref > v in , it is cleared to 0. the 4506 group repeats this operation to the lowermost bit of the register ad to convert an analog value to a digital value. a/d con- version stops after 62 machine cycles (46.5 1 as soon as a/d conversion completes (figure 29).
4506 group rev.3.01 2005.02.07 page 33 of 111 rej03b0106-0301 table 13 change of successive comparison register ad during a/d conversion comparison voltage (v ref ) value change of successive comparison register ad at starting conversion ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ------------- ------------- ------------- ------------- ------------- ------------- ------------- ------------- fig. 30 setting registers a/d control register q1 a in1 pin selected a/d conversion mode 0001 (bit 3) (bit 0) (7) a/d conversion timing chart figure 29 shows the a/d conversion timing chart. fig. 29 a/d conversion timing chart (8) how to use a/d conversion how to use a/d conversion is explained using as example in which the analog input from p2 1 /a in1 pin is a/d converted, and the high- order 4 bits of the converted data are stored in address m(z, x, y) = (0, 0, 0), the middle-order 4 bits in address m(z, x, y) = (0, 0, 1), and the low-order 2 bits in address m(z, x, y) = (0, 0, 2) of ram. the a/d interrupt is not used in this example. ? ? ? ? ? ? ? ?
rev.3.01 2005.02.07 page 34 of 111 rej03b0106-0301 4506 group (9) operation at comparator mode the a/d converter is set to comparator mode by setting bit 3 of the register q1 to 1. below, the operation at comparator mode is described. (10) comparator register in comparator mode, the built-in da comparator is connected to the 8-bit comparator register as a register for setting comparison volt- ages. the contents of register b is stored in the high-order 4 bits of the comparator register and the contents of register a is stored in the low-order 4 bits of the comparator register with the tadab in- struction. when changing from a/d conversion mode to comparator mode, the result of a/d conversion (register ad) is undefined. however, because the comparator register is separated from regis- ter ad, the value is retained even when changing from comparator mode to a/d conversion mode. note that the comparator register can be written and read at only comparator mode. if the value in the comparator register is n, the logic value of com- parison voltage v ref generated by the built-in da converter can be determined from the following formula: (11) comparison result store flag (adf) in comparator mode, the adf flag, which shows completion of a/d conversion, stores the results of comparing the analog input volt- age with the comparison voltage. when the analog input voltage is lower than the comparison voltage, the adf flag is set to 1. the state of adf flag can be examined with the skip instruction (snzad). use the interrupt control register v2 to select the inter- rupt or the skip instruction. the adf flag is cleared to 0 when the interrupt occurs or when the next instruction is skipped with the skip instruction. (12) comparator operation start instruction (adst instruction) in comparator mode, executing adst starts the comparator oper- ating. the comparator stops 8 machine cycles after it has started (6 1. (13) notes for the use of a/d conversion 1 note the following when using the analog input pins also for port p2 function: selection of analog input pins even when p2 0 /a in0 , p2 1 /a in1 are set to pins for analog input, they continue to function as port p2 input/output. accordingly, when any of them are used as i/o port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to 1. also, the port input function of the pin functions as an analog input is undefined. tala instruction when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high-order 2 bits of register a, si- multaneously, the low-order 2 bits of register a is 0. (14) notes for the use of a/d conversion 2 do not change the operating mode (both a/d conversion mode and comparator mode) of a/d converter with the bit 3 of register q1 while the a/d converter is operating. when the operating mode of a/d converter is changed from the comparator mode to a/d conversion mode with the bit 3 of register q1, note the following; clear the bit 2 of register v2 to 0 to change the operating mode of the a/d converter from the comparator mode to a/d conver- sion mode with the bit 3 of register q1. the a/d conversion completion flag (adf) may be set when the operating mode of the a/d converter is changed from the com- parator mode to the a/d conversion mode. accordingly, set a value to the bit 3 of register q1, and execute the snzad instruc- tion to clear the adf flag. logic value of comparison voltage v ref v ref = ? fig. 31 comparator operation timing chart v dd 256 adst instruction c o m p a r i s o n r e s u l t s t o r e f l a g ( a d f ) 8 m a c h i n e c y c l e s d a c o p e r a t i o n s i g n a l c o m p a r a t o r o p e r a t i o n c o m p l e t e d . ( t h e v a l u e o f a d f i s d e t e r m i n e d )
4506 group rev.3.01 2005.02.07 page 35 of 111 rej03b0106-0301 (15) definition of a/d converter accuracy the a/d conversion accuracy is defined below (refer to figure 32). relative accuracy ? 0 to 1. ? 1023 to 1022. ? ? absolute accuracy this means a deviation from the ideal characteristics between 0 to v dd of actual a/d conversion characteristics. fig. 32 definition of a/d conversion accuracy v fst v 0t 1022 v dd 1024 vn: analog input voltage when the output data changes from n to n+1 (n = 0 to 1022) 1lsb at relative accuracy 1lsb at absolute accuracy a a [ l s b ] actual a/d conversion characteristics a : 1 l s b b y r e l a t i v e a c c u r a c y b : v n + 1 v n c : d i f f e r e n c e b e t w e e n i d e a l v n a n d a c t u a l v n zero transition voltage (v 0t ) a n a l o g v o l t a g e full-scale transition voltage (v fst ) i d e a l l i n e o f a / d c o n v e r s i o n b e t w e e n v 0 v 1 0 2 2
rev.3.01 2005.02.07 page 36 of 111 rej03b0106-0301 4506 group reset function system reset is performed by applying l level to reset pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. then when h level is applied to reset pin, software starts from address 0 in page 0. fig. 33 reset release timing fig. 34 reset pin input waveform and reset operation f(x in ) reset p r o g r a m s t a r t s ( a d d r e s s 0 i n p a g e 0 ) on-chip oscillator (internal oscillator) is counted 5359 times. reset 0 . 3 v d d 0.85v dd ( note ) note: keep the value of supply voltage to the minimum value or more of the recommended operating conditions . r e s e t i n p u t 1 m a c h i n e c y c l e o r m o r e = p r o g r a m s t a r t s ( a d d r e s s 0 i n p a g e 0 ) on-chip oscillator (internal oscillator) is counted 5359 times.
4506 group rev.3.01 2005.02.07 page 37 of 111 rej03b0106-0301 fig. 35 structure of reset pin and its peripherals, and power-on reset operation name d 0 , d 1 d 2 /c, d 3 /k p0 0 , p0 1 , p0 2 , p0 3 p1 0 , p1 1 , p1 2 /cntr, p1 3 /int p2 0 /a in0 , p2 1 /a in1 notes 1: output latch is set to 1. 2: pull-up transistor is turned off. function d 0 , d 1 d 2 , d 3 p0 0 p0 3 p1 0 p1 3 p2 0 , p2 1 state high-impedance (note 1) high-impedance (notes 1, 2) high-impedance (notes 1, 2) high-impedance (notes 1, 2) high-impedance (notes 1, 2) (1) power-on reset reset can be performed automatically at power on (power-on re- set) by connecting a diode and a capacitor to reset pin. connect reset pin and the external circuit at the shortest distance. table 14 port state at reset v d d wef v d d watchdog timer output i n t e r n a l r e s e t s i g n a l power-on r e s e t r e l e a s e d internal reset signal reset state this symbol represents a parasitic diode. 2: applied potential to reset pin must be v dd or less. ( n o t e 1 ) ( n o t e 2 ) p u l l - u p t r a n s i s t o r reset pin reset pin voltage notes 1:
rev.3.01 2005.02.07 page 38 of 111 rej03b0106-0301 4506 group program counter (pc) .......................................................................................................... address 0 in page 0 is set to program counter. interrupt enable flag (inte) .................................................................................................. power down flag (p) ........................................................................................................... .. external 0 interrupt request flag (exf0) .............................................................................. interrupt control register v1 ................................................................................................. . interrupt control register v2 ................................................................................................. . interrupt control register i1 ................................................................................................. .. timer 1 interrupt request flag (t1f) ..................................................................................... timer 2 interrupt request flag (t2f) ..................................................................................... watchdog timer flags (wdf1, wdf2) .................................................................................. watchdog timer enable flag (wef) ...................................................................................... timer control register w1 ..................................................................................................... timer control register w2 ..................................................................................................... timer control register w6 ..................................................................................................... clock control register mr ..................................................................................................... key-on wakeup control register k0 ...................................................................................... key-on wakeup control register k1 ...................................................................................... key-on wakeup control register k2 ...................................................................................... pull-up control register pu0 ................................................................................................. pull-up control register pu1 ................................................................................................. pull-up control register pu2 ................................................................................................. a/d conversion completion flag (adf) ................................................................................. a/d control register q1 ....................................................................................................... .. carry flag (cy) ............................................................................................................... ....... register a .................................................................................................................... ......... register b .................................................................................................................... ......... register d .................................................................................................................... ......... register e .................................................................................................................... ......... register x .................................................................................................................... ......... register y .................................................................................................................... ......... register z .................................................................................................................... ......... stack pointer (sp) ............................................................................................................ .... oscillation clock ..................................................................... on-chip oscillator (operating) ceramic resonator circuit ..................................................................................... operating rc oscillation circuit ...................................................................................................... stop ? represents undefined. fig. 36 internal state at reset ?? (2) internal state at reset figure 36 shows internal state at reset (they are the same after sys- tem is released from reset). the contents of timers, registers, flags and ram except shown in figure 36 are undefined, so set the ini- tial value to them. 00000000000000 0 (interrupt disabled) 0 0 0 0 0 0 (interrupt disabled) 0 0 0 0 (interrupt disabled) 0000 0 0 0 1 0 0 0 0 (prescaler and timer 1 stopped) 0 0 0 0 (timer 2 stopped) 0000 1100 0000 0000 0000 0000 0000 0000 0 0000 0 0000 0000 ??? ?????? ??
4506 group rev.3.01 2005.02.07 page 39 of 111 rej03b0106-0301 ram back-up mode the 4506 group has the ram back-up mode. when the pof2 instruction is executed continuously after the epof instruction, system enters the ram back-up state. the pof2 instruction is equal to the nop instruction when the epof instruction is not executed before the pof2 instruction. as oscillation stops retaining ram, the function of reset circuit and states at ram back-up mode, current dissipation can be reduced without losing the contents of ram. table 15 shows the function and states retained at ram back-up. figure 36 shows the state transition. (1) identification of the start condition warm start (return from the ram back-up state) or cold start (re- turn from the normal reset state) can be identified by examining the state of the power down flag (p) with the snzp instruction. (2) warm start condition when the external wakeup signal is input after the system enters the ram back-up state by executing the epof instruction and pof2 instruction continuously, the cpu starts executing the pro- gram from address 0 in page 0. in this case, the p flag is 1. (3) cold start condition the cpu starts executing the program from address 0 in page 0 when; reset pulse is input to reset pin, or reset by watchdog timer is performed, or in this case, the p flag is 0. table 15 functions and states retained at ram back-up function program counter (pc), registers a, b, carry flag (cy), stack pointer (sp) (note 2) contents of ram port level selected oscillation circuit timer control register w1 timer control registers w2, w6 clock control register mr interrupt control registers v1, v2 interrupt control register i1 timer 1 function timer 2 function a/d conversion function a/d control register q1 pull-up control registers pu0 to pu2 key-on wakeup control registers k0 to k2 external 0 interrupt request flag (exf0) timer 1 interrupt request flag (t1f) timer 2 interrupt request flag (t2f) watchdog timer flags (wdf1) watchdog timer enable flag (wef) 16-bit timer (wdt) a/d conversion completion flag (adf) interrupt enable flag (inte) ram back-up ? ? ? ? ? ? ? ? ? ? ? ? ? o represents that the function can be retained, and ? repre- sents that the function is initialized. registers and flags other than the above are undefined at ram back-up, and set an initial value after returning. 2: the stack pointer (sp) points the level of the stack register and is initialized to 7 at ram back-up. 3: the state of the timer is undefined. 4: initialize the watchdog timer flag wdf1 with the wrst instruction, and then execute the pof2 instruction. 5: as for the d 2 /c pin, the output latch of port c is set to 1 at the ram back-up. however, the output latch of port d 2 is retained. as for the other ports, their output levels are retained at the ram back-up.
rev.3.01 2005.02.07 page 40 of 111 rej03b0106-0301 4506 group (4) return signal an external wakeup signal is used to return from the ram back-up mode because the oscillation is stopped. table 16 shows the return condition for each return source. (5) control registers key-on wakeup control register k0 register k0 controls the port p0 key-on wakeup function. set the contents of this register through register a with the tk0a instruc- tion. in addition, the tak0 instruction can be used to transfer the contents of register k0 to register a. key-on wakeup control register k1 register k1 controls the port p1 key-on wakeup function. set the contents of this register through register a with the tk1a instruc- tion. in addition, the tak1 instruction can be used to transfer the contents of register k0 to register a. key-on wakeup control register k2 register k2 controls the ports p2, d 2 /c and d 3 /k key-on wakeup function. set the contents of this register through register a with the tk2a instruction. in addition, the tak2 instruction can be used to transfer the contents of register k2 to register a. table 16 return source and return condition remarks the key-on wakeup function can be selected by one port unit. set the port using the key-on wakeup function to h level before going into the ram back-up state. select the return level ( l level or h level) with the bit 2 of register i1 ac- cording to the external state before going into the ram back-up state. return condition return by an external l level in- put. external wakeup signal return source port p0 port p1 (note) port p2 ports d 2 /c, d 3 /k port p1 3 /int (note) pull-up control register pu0 register pu0 controls the on/off of the port p0 pull-up transis- tor. set the contents of this register through register a with the tpu0a instruction. pull-up control register pu1 register pu1 controls the on/off of the port p1 pull-up transis- tor. set the contents of this register through register a with the tpu1a instruction. pull-up control register pu2 register pu2 controls the on/off of the ports p2, d 2 /c and d 3 / k pull-up transistor. set the contents of this register through reg- ister a with the tpu2a instruction. interrupt control register i1 register i1 controls the valid waveform of the external 0 inter- rupt, the input control of int pin and the return input level. set the contents of this register through register a with the ti1a in- struction. in addition, the tai1 instruction can be used to transfer the contents of register i1 to register a. return by an external h level or l level input. the return level can be selected with the bit 2 (i1 2 ) of register i1. when the return level is input, the exf0 flag is not set. note: when the bit 3 (k1 3 ) of register k1 is 0 , the key-on wakeup of the int pin is valid ( h or l level). it is 1 , the key-on wakeup of port p1 3 is valid ( l level).
4506 group rev.3.01 2005.02.07 page 41 of 111 rej03b0106-0301 fig. 37 state transition fig. 38 set source and clear source of the p flag fig. 39 start condition identified example using the snzp in- struction r e s e t ( s t a b i l i z i n g t i m e a ) b o p e r a t i o n s o u r c e c l o c k : c e r a m i c r e s o n a t o r o n - c h i p o s c i l l a t o r : s t o p r c o s c i l l a t i o n c i r c u i t : s t o p a o p e r a t i o n s o u r c e c l o c k : o n - c h i p o s c i l l a t o r c l o c k c e r a m i c r e s o n a t o r : o p e r a t i n g ( n o t e 2 ) r c o s c i l l a t i o n c i r c u i t : s t o p c operation source clock: rc oscillation on-chip oscillator: stop ceramic resonator: stop c m c k i n s t r u c t i o n e x e c u t i o n ( n o t e 3 ) crck instruction execution ( note 3 ) k e y - o n w a k e u p (stabilizing time b ) pof2 instruction execution key-on wakeup (stabilizing time c ) pof2 instruction execution e r a m b a c k - u p ( a l l f u n c t i o n s o f m i c r o c o m p u t e r s t o p ) o p e r a t i o n s o u r c e c l o c k : s t o p k e y - o n w a k e u p (stabilizing time a ) pof2 instruction execution stabilizing time a : microcomputer starts its operation after counting the on-chip oscillator clock 5359 times by hardware. stabilizing time b : microcomputer starts its operation after counting the f(x in ) 5359 times by hardware. stabilizing time c : microcomputer starts its operation after counting the f(x in ) 165 times by hardware. notes 1: continuous execution of the epof instruction and pof2 instruction is required to go into the ram back-up state. 2: through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock. 3: the oscillator clock corresponding to each instruction is selected as the operation source clock, and the on-chip oscillator is stopped. o p e r a t i n g o p e r a t i n g o p e r a t i n g s r q power down flag p p o f 2 i n s t r u c t i o n reset inpu t e p o f i n s t r u c t i o n p o f 2 i n s t r u c t i o n e p o f i n s t r u c t i o n + + program start p = 1 ? y e s w a r m s t a r t cold start no
rev.3.01 2005.02.07 page 42 of 111 rej03b0106-0301 4506 group table 17 key-on wakeup control register k0 3 k0 2 k0 1 k0 0 key-on wakeup control register k0 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p0 3 key-on wakeup control bit port p0 2 key-on wakeup control bit port p0 1 key-on wakeup control bit port p0 0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w note: r represents read enabled, and w represents write enabled. k1 3 k1 2 k1 1 k1 0 key-on wakeup control register k1 p1 3 key-on wakeup not used/int pin key-on wakeup used p1 3 key-on wakeup used/int pin key-on wakeup not used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p1 3 /int key-on wakeup control bit port p1 2 /cntr key-on wakeup control bit port p1 1 key-on wakeup control bit port p1 0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w k2 3 k2 2 k2 1 k2 0 key-on wakeup control register k2 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port d 3 /k key-on wakeup control bit port d 2 /c key-on wakeup control bit port p2 1 /a in1 key-on wakeup control bit port p2 0 /a in0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w
4506 group rev.3.01 2005.02.07 page 43 of 111 rej03b0106-0301 pu0 3 pu0 2 pu0 1 pu0 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p0 3 pull-up transistor control bit port p0 2 pull-up transistor control bit port p0 1 pull-up transistor control bit port p0 0 pull-up transistor control bit pull-up control register pu0 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w table 18 pull-up control register and interrupt control register pu1 3 pu1 2 pu1 1 pu1 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p1 3 /int pull-up transistor control bit port p1 2 /cntr pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit pull-up control register pu1 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w pu2 3 pu2 2 pu2 1 pu2 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port d 3 /k pull-up transistor control bit port d 2 /c pull-up transistor control bit port p2 1 /a in1 pull-up transistor control bit port p2 0 /a in0 pull-up transistor control bit pull-up control register pu2 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w i1 3 i1 2 i1 1 i1 0 int pin input control bit (note 2) interrupt valid waveform for int pin/ return level selection bit (note 2) int pin edge detection circuit control bit int pin timer 1 control enable bit notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. accordingly, clear exf0 flag with the snz0 in- struction when the bit 0 (v1 0 ) of register v1 to 0 . in this time, set the nop instruction after the snz0 instruction, for the case when a skip is performed with the snz0 instruction. interrupt control register i1 r/w at ram back-up : state retained at reset : 0000 2 int pin input disabled int pin input enabled falling waveform ( l level of int pin is recognized with the snzi0 instruction)/ l level rising waveform ( h level of int pin is recognized with the snzi0 instruction)/ h level one-sided edge detected both edges detected disabled enabled 0 1 0 1 0 1 0 1
rev.3.01 2005.02.07 page 44 of 111 rej03b0106-0301 4506 group clock control the clock control circuit consists of the following circuits. on-chip oscillator (internal oscillator) ceramic resonator rc oscillation circuit multi-plexer (clock selection circuit) frequency divider internal clock generating circuit fig. 40 clock control circuit structure the system clock and the instruction clock are generated as the source clock for operation by these circuits. figure 40 shows the structure of the clock control circuit. the 4506 group operates by the on-chip oscillator clock (f(ring)) which is the internal oscillator after system is released from reset. also, the ceramic resonator or the rc oscillation can be used for the source oscillation (f(x in )) of the 4506 group. the cmck in- struction or crck instruction is executed to select the ceramic resonator or rc oscillator, respectively. mr 3, mr 2 0 0 0 1 1 0 1 1 q s qr q s r c r c k i n s t r u c t i o n q s r cmck instruction q s r reset pin x o u t x i n key-on wakeup signal i n s t r u c t i o n c l o c k c o u n t e r wait time (note 2) control circuit program start signal rc oscillation circuit division circuit divided by 8 divided by 4 divided by 2 i n t e r n a l c l o c k g e n e r a t i o n c i r c u i t ( d i v i d e d b y 3 ) n o t e s 1 : s y s t e m o p e r a t e s b y t h e o n - c h i p o s c i l l a t o r c l o c k ( f ( r i n g ) ) u n t i l t h e c m c k o r c r c k i n s t r u c t i o n i s e x e c u t e d a f t e r s y s t e m i s r e l e a s e d f r o m r e s e t . 2 : t h e w a i t t i m e c o n t r o l c i r c u i t i s u s e d t o g e n e r a t e t h e t i m e r e q u i r e d t o s t a b i l i z e t h e f ( x i n ) o s c i l l a t i o n . a f t e r t h e c e r t a i n o s c i l l a t i o n s t a b i l i z i n g w a i t t i m e e l a p s e s , t h e p r o g r a m s t a r t s i g n a l i s o u t p u t . t h i s c i r c u i t o p e r a t e s w h e n s y s t e m i s r e l e a s e d f r o m r e s e t o r r e t u r n e d f r o m r a m b a c k - u p . s y s t e m c l o c k o n - c h i p o s c i l l a t o r ( i n t e r n a l o s c i l l a t o r ) ( n o t e 1 ) m u l t i p l e x e r c e r a m i c r e s o n a t o r c i r c u i t epof instruction + pof2 instruction
4506 group rev.3.01 2005.02.07 page 45 of 111 rej03b0106-0301 fig. 41 switch to ceramic resonance/rc oscillation fig. 42 handling of x in and x out when operating on-chip oscillator fig. 43 ceramic resonator external circuit fig. 44 external rc oscillation circuit execute the cmck instruc- tion in program. note: externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manu- facturer s recommended value because constants such as ca- pacitance depend on the resonator. (1) selection of source oscillation (f(x in )) the ceramic resonator or rc oscillation can be used for the source oscillation of the mcu. after system is released from reset, the mcu starts operation by the clock output from the on-chip oscillator which is the internal os- cillator. when the ceramic resonator is used, execute the cmck instruc- tion. when the rc oscillation is used, execute the crck instruction. the oscillation circuit by the cmck or crck instruction can be selected only at once. the oscillation circuit corresponding to the first executed one of these two instructions is valid. other os- cillation circuit and the on-chip oscillator stop. execute the cmck or the crck instruction in the initial setting rou- tine of program (executing it in address 0 in page 0 is recommended). also, when the cmck or the crck instruction is not executed in program, the mcu operates by the on-chip oscilla- tor. (2) on-chip oscillator operation when the mcu operates by the on-chip oscillator as the source os- cillation (f(x in )) without using the ceramic resonator or the rc oscillator, connect x in pin to v ss and leave x out pin open (figure 42). the clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies when designing application products. (3) ceramic resonator when the ceramic resonator is used as the source oscillation (f(x in )), connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. then, execute the cmck instruction. a feedback resistor is built in between pins x in and x out (figure 43). (4) rc oscillation when the rc oscillation is used as the source oscillation (f(x in )), connect the x in pin to the external circuit of resistor r and the ca- pacitor c at the shortest distance and leave x out pin open. then, execute the crck instruction (figure 44). the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. * reset o n - c h i p o s c i l l a t o r o p e r a t i o n c m c k i n s t r u c t i o n crck instruction ceramic resonator valid on-chip oscillator stop rc oscillation stop r c o s c i l l a t i o n v a l i d o n - c h i p o s c i l l a t o r s t o p c e r a m i c r e s o n a t o r s t o p 4506 x i n x o u t * do not use the cmck instruction and crck instruction in program. 4 5 0 6 x i n x out rd c in c out 4 5 0 6 x i n x o u t r c * e x e c u t e t h e c r c k i n s t r u c t i o n i n p r o g r a m .
rev.3.01 2005.02.07 page 46 of 111 rej03b0106-0301 4506 group (5) external clock when the external signal clock is used as the source oscillation (f(x in )), connect the x in pin to the clock source and leave x out pin open. then, execute the cmck instruction (figure 45). be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). also, note that the ram back-up mode (pof2 instruction) cannot be used when using the external clock. (6) clock control register mr register mr controls system clock. set the contents of this register through register a with the tmra instruction. in addition, the tamr instruction can be used to transfer the contents of register mr to register a. table 19 clock control register mr fig. 45 external clock input circuit rom ordering method please submit the information described below when ordering mask rom. (1) mask rom order confirmation form ..................................... 1 (2) data to be written into mask rom ............................... eprom (three sets containing the identical data) (3) mark specification form .......................................................... 1 ? renesas technology corp. homepage (http://www.renesas.com/en/rom). note : r represents read enabled, and w represents write enabled. mr 3 clock control register mr system clock f(x in ) (high-speed mode) f(x in )/2 (middle-speed mode) f(x in )/4 (low-speed mode) f(x in )/8 (default mode) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. at reset : 1100 2 at ram back-up : 1100 2 mr 3 0 0 1 1 r/w not used not used system clock selection bits 0 1 0 1 mr 2 0 1 0 1 mr 1 mr 0 mr 2 4 5 0 6 x in x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t v d d v s s e x e c u t e t h e c m c k i n s t r u c t i o n i n p r o g r a m . *
4506 group rev.3.01 2005.02.07 page 47 of 111 rej03b0106-0301 list of precautions ? ? ? ? ? ? ? ? ? ? fig. 46 t imer count start timing and count time when opera- tion starts (t1, t2) (1) timer count source timer value timer underflow signal 321 032 103 2 count source (cntr input) (2) (3) (4) 10 11 12 13 14
rev.3.01 2005.02.07 page 48 of 111 rej03b0106-0301 4506 group note [2] on bit 3 of register i1 when the bit 3 of register i1 is cleared to 0 , the ram back-up mode is selected and the input of int pin is disabled, be careful about the following notes. when the key-on wakeup function of port p1 3 is not used (regis- ter k1 3 = 0 ), clear bits 2 and 3 of register i1 before system enters to the ram back-up mode. (refer to figure 48 ? ?? ? ? fig. 48 external 0 interrupt program example-2 note [3] on bit 2 of register i1 when the interrupt valid waveform of the p1 3 /int pin is changed with the bit 2 of register i1 in software, be careful about the fol- lowing notes. depending on the input state of the p1 3 /int pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 49 ? 0 after executing at least one instruction (refer to figure 49 ? ? ??? ? ? ?? ? ? ? fig. 49 external 0 interrupt program example-3 la 4 ; ( ??? ? ??? ? ? ? fig. 47 external 0 interrupt program example-1 p1 3 /int pin note [1] on bit 3 of register i1 when the input of the int pin is controlled with the bit 3 of regis- ter i1 in software, be careful about the following notes. depending on the input state of the p1 3 /int pin, the external 0 in- terrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to 0 (refer to figure 47 ? 0 after executing at least one instruction (refer to figure 47 ? ?
4506 group rev.3.01 2005.02.07 page 49 of 111 rej03b0106-0301 fig. 51 analog input external circuit example-1 fig. 52 analog input external circuit example-2 notes for the use of a/d conversion 2 do not change the operating mode (both a/d conversion mode and comparator mode) of a/d converter with the bit 3 of register q1 while the a/d converter is operating. when the operating mode of a/d converter is changed from the comparator mode to a/d conversion mode with the bit 3 of regis- ter q1, note the following; clear the bit 2 of register v2 to 0 (refer to figure 50 ? the a/d conversion completion flag (adf) may be set when the operating mode of the a/d converter is changed from the com- parator mode to the a/d conversion mode. accordingly, set a value to the bit 3 of register q1, and execute the snzad instruc- tion to clear the adf flag. la 8 ; ( ? ?? ? ??? ? fig. 50 a/d conversion interrupt program example sensor a i n about 1k ? selection of analog input pins even when p2 0 /a in0 and p2 1 /a in1 are set to pins for analog in- put, they continue to function as port p2 input/output. accordingly, when any of them are used as i/o port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to 1. also, the port input func- tion of the pin functions as an analog input is undefined. tala instruction when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high-order 2 bits of register a, si- multaneously, the low-order 2 bits of register a is 0. 16 17 18
rev.3.01 2005.02.07 page 50 of 111 rej03b0106-0301 4506 group electric characteristic differences between mask rom and one time prom version mcu there are differences in electric characteristics, operation margin, noise immunity, and noise radiation between mask rom and one time prom version mcus due to the difference in the manufac- turing processes. when manufacturing an application system with the one time prom version and then switching to use of the mask rom ver- sion, please perform sufficient evaluations for the commercial samples of the mask rom version. note on power source voltage when the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. clock control execute the cmck or the crck instruction in the initial setting routine of program (executing it in address 0 in page 0 is recom- mended). the oscillation circuit by the cmck or crck instruction can be selected only at once. the oscillation circuit corresponding to the first executed one of these two instruction is valid. other oscilla- tion circuits and the on-chip oscillator stop. on-chip oscillator the clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. be careful that variable frequencies when designing application products. also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. when considering the oscillation stabilize wait time after system is re- leased from reset, be careful that the variable frequency of the on-chip oscillator clock. external clock when the external signal clock is used as the source oscillation (f(x in )), note that the ram back-up mode (pof2 instructions) cannot be used. 22 23 19 20 21
4506 group rev.3.01 2005.02.07 page 51 of 111 rej03b0106-0301 control registers i1 3 i1 2 i1 1 i1 0 int pin input control bit (note 3) interrupt valid waveform for int pin/ return level selection bit (note 3) int pin edge detection circuit control bit int pin timer 1 control enable bit interrupt control register i1 r/w at ram back-up : state retained at reset : 0000 2 int pin input disabled int pin input enabled falling waveform ( l level of int pin is recognized with the snzi0 instruction)/ l level rising waveform ( h level of int pin is recognized with the snzi0 instruction)/ h level one-sided edge detected both edges detected disabled enabled 0 1 0 1 0 1 0 1 mr 3 clock control register mr system clock f(x in ) (high-speed mode) f(x in )/2 (middle-speed mode) f(x in )/4 (low-speed mode) f(x in )/8 (default mode) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. at reset : 1100 2 at ram back-up : 1100 2 mr 3 0 0 1 1 r/w not used not used system clock selection bits 0 1 0 1 mr 2 0 1 0 1 mr 1 mr 0 mr 2 this bit has no function, but read/write is enabled. interrupt disabled (snzad instruction is valid) interrupt enabled (snzad instruction is invalid) (note 2) this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. r/w v1 3 v1 2 v1 1 v1 0 v2 3 v2 2 v2 1 v2 0 not used a/d interrupt enable bit not used not used interrupt control register v2 at ram back-up : 0000 2 at reset : 0000 2 0 1 0 1 0 1 0 1 interrupt control register v1 timer 2 interrupt enable bit timer 1 interrupt enable bit not used external 0 interrupt enable bit interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) (note 2) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) (note 2) this bit has no function, but read/write is enabled. interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) (note 2) 0 1 0 1 0 1 0 1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 notes 1: r represents read enabled, and w represents write enabled. 2: these instructions are equivalent to the nop instruction. 3: when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. accordingly, clear exf0 flag with the snz0 in- struction when the bit 0 (v1 0 ) of register v1 to 0 . in this time, set the nop instruction after the snz0 instruction, for the case when a skip is performed with the snz0 instruction.
rev.3.01 2005.02.07 page 52 of 111 rej03b0106-0301 4506 group 0 1 0 1 0 1 0 1 w2 1 0 0 1 1 stop (state initialized) operating instruction clock divided by 4 instruction clock divided by 16 stop (state retained) operating count start synchronous circuit not selected count start synchronous circuit selected prescaler control bit prescaler dividing ratio selection bit timer 1 control bit timer 1 count start synchronous circuit control bit stop (state retained) operating count auto-stop circuit not selected count auto-stop circuit selected count source timer 1 underflow signal prescaler output (orclk) cntr input system clock timer 2 control bit timer 1 count auto-stop circuit selection bit (note 2) timer 2 count source selection bits 0 1 0 1 w2 0 0 1 0 1 w1 3 w1 2 w1 1 w1 0 timer control register w1 r/w at ram back-up : 0000 2 at reset : 0000 2 r/w at ram back-up : 0000 2 at reset : 0000 2 timer control register w2 r/w at ram back-up : state retained at reset : 0000 2 this bit has no function, but read/write is enabled. this bit has no function, but read/write is enabled. timer 1 underflow signal divided by 2 output timer 2 underflow signal divided by 2 output p1 2 (i/o)/cntr input (note 3) p1 2 (input)/cntr input/output (note 3) not used not used cntr output selection bit p1 2 /cntr function selection bit 0 1 0 1 0 1 0 1 timer control register w6 r/w at ram back-up : state retained at reset : 0000 2 notes 1: r represents read enabled, and w represents write enabled. 2: this function is valid only when the timer 1 count start synchronization circuit is selected. 3: cntr input is valid only when cntr input is selected as the timer 2 count source. q1 3 q1 2 a/d control register q1 a/d operation mode selection bit not used analog input pin selection bits at reset : 0000 2 at ram back-up : state retained 0 1 0 1 q1 1 0 0 1 1 a/d conversion mode comparator mode this bit has no function, but read/write is enabled. selected pins a in0 a in1 not available not available q1 0 0 1 0 1 r/w q1 1 q1 0 w2 3 w2 2 w2 1 w2 0 w6 3 w6 2 w6 1 w6 0
4506 group rev.3.01 2005.02.07 page 53 of 111 rej03b0106-0301 k0 3 k0 2 k0 1 k0 0 key-on wakeup control register k0 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p0 3 key-on wakeup control bit port p0 2 key-on wakeup control bit port p0 1 key-on wakeup control bit port p0 0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w note: r represents read enabled, and w represents write enabled. k1 3 k1 2 k1 1 k1 0 key-on wakeup control register k1 p1 3 key-on wakeup not used/int pin key-on wakeup used p1 3 key-on wakeup used/int pin key-on wakeup not used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port p1 3 /int key-on wakeup control bit port p1 2 /cntr key-on wakeup control bit port p1 1 key-on wakeup control bit port p1 0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w k2 3 k2 2 k2 1 k2 0 key-on wakeup control register k2 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used port d 3 /k key-on wakeup control bit port d 2 /c key-on wakeup control bit port p2 1 /a in1 key-on wakeup control bit port p2 0 /a in0 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w
rev.3.01 2005.02.07 page 54 of 111 rej03b0106-0301 4506 group pu0 3 pu0 2 pu0 1 pu0 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p0 3 pull-up transistor control bit port p0 2 pull-up transistor control bit port p0 1 pull-up transistor control bit port p0 0 pull-up transistor control bit pull-up control register pu0 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w pu1 3 pu1 2 pu1 1 pu1 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port p1 3 /int pull-up transistor control bit port p1 2 /cntr pull-up transistor control bit port p1 1 pull-up transistor control bit port p1 0 pull-up transistor control bit pull-up control register pu1 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w pu2 3 pu2 2 pu2 1 pu2 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on port d 3 /k pull-up transistor control bit port d 2 /c pull-up transistor control bit port p2 1 /a in1 pull-up transistor control bit port p2 0 /a in0 pull-up transistor control bit pull-up control register pu2 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 w notes 1: r represents read enabled, and w represents write enabled.
4506 group rev.3.01 2005.02.07 page 55 of 111 rej03b0106-0301 symbol a b dr e q1 v1 v2 i1 w1 w2 w6 mr k0 k1 k2 pu0 pu1 pu2 x y z dp pc pc h pc l sk sp cy r1 r2 t1 t2 t1f t2f contents register a (4 bits) register b (4 bits) register d (3 bits) register e (8 bits) a/d control register q1 (4 bits) interrupt control register v1 (4 bits) interrupt control register v2 (4 bits) interrupt control register i1 (4 bits) timer control register w1 (4 bits) timer control register w2 (4 bits) timer control register w6 (4 bits) clock control register mr (4 bits) key-on wakeup control register k0 (4 bits) key-on wakeup control register k1 (4 bits) key-on wakeup control register k2 (4 bits) pull-up control register pu0 (4 bits) pull-up control register pu1 (4 bits) pull-up control register pu2 (4 bits) register x (4 bits) register y (4 bits) register z (2 bits) data pointer (10 bits) (it consists of registers x, y, and z) program counter (14 bits) high-order 7 bits of program counter low-order 7 bits of program counter stack register (14 bits ? ? contents of registers and memories negate, flag unchanged after executing instruction ram address pointed by the data pointer label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 in page p 5 p 4 p 3 p 2 p 1 p 0 hex. c + hex. number x (also same for others) symbol wdf1 wef inte exf0 p adf d p0 p1 p2 c k x y z p n i j a 3 a 2 a 1 a 0 ? m(dp) a p, a c + x note : some instructions of the 4506 group has the skip function to unexecute the next described instruction. the 4506 group jus t invalidates the next instruc- tion when a skip is performed. the contents of program counter is not increased by 2. accordingly, the number of cycles does no t change even if skip is not performed. however, the cycle count becomes 1 if the tabp p, rt, or rts instruction is skipped. instructions the 4506 group has the 110 instructions. each instruction is de- scribed as follows; (1) index list of instruction function (2) machine instructions (index by alphabet) (3) machine instructions (index by function) (4) instruction code table symbol the symbols shown below are used in the following list of instruc- tion function and the machine instructions.
rev.3.01 2005.02.07 page 56 of 111 rej03b0106-0301 4506 group index list of instruction function group- ing ram addresses mnemonic xami j tma j la n tabp p am amc a n and or sc rc szc cma rar function (a) dr 0 , a 3 a 0 ) (b) 4 (a) 0 (pc) 1 (a) e 4 ) e 0 ) e 4 ) (a) e 0 ) (dr 2 dr 0 ) a 0 ) (a 2 a 0 ) dr 0 ) (a 3 ) a 0 ) sp 0 ) (a 3 ) 1 (a) 1 ram to register transfer arithmetic operation ram to register transfer register to register transfer group- ing page 75, 88 81, 88 81, 88 86, 88 82, 88 76, 88 81, 88 76, 88 81, 88 80, 88 79, 88 66, 88 66, 88 66, 88 63, 88 78, 88 86, 88 87, 88 page 87, 88 83, 88 66, 90 76, 90 60, 90 60, 90 60, 90 61, 90 68, 90 71, 90 69, 90 74, 90 63, 90 68, 90 note: p is 0 to 15 for m34506m2, p is 0 to 31 for m34506m4/e4.
4506 group rev.3.01 2005.02.07 page 57 of 111 rej03b0106-0301 index list of instruction function (continued) group- ing function (mj(dp)) a 0 (pc h ) a 0 (pc h ) dr 0 , a 3 a 0 ) (sp) a 0 (sp) a 0 (sp) dr 0 , a 3 a 0 ) (pc) 1 (pc) 1 (pc) 1 comparison operation subroutine operation branch operation bit operation return operation mnemonic sb j rb j szb j seam sea n b a bl p, a bla p bm a bml p, a bmla p rti rt rts group- ing page 70, 90 69, 90 74, 90 72, 90 71, 90 61, 92 61, 92 61, 92 62, 92 62, 92 62, 92 70, 92 70, 92 70, 92 function (inte) h ? i1 2 = 0 : (int) = l ? (a) t1 4 ) (a) t1 0 ) (r1 7 r1 4 ) t1 4 ) r1 0 ) t1 0 ) t2 4 ) (a) t2 0 ) (r2 7 r2 4 ) t2 4 ) r2 0 ) t2 0 )
rev.3.01 2005.02.07 page 58 of 111 rej03b0106-0301 4506 group index list of instruction function (continued) group- ing group- ing function (r1 7 r1 4 ) r1 0 ) a 1 ) ad 6 ) (a) ad 2 ) in comparator mode (q1 3 = 1), (b) ad 4 ) (a) ad 0 ) (a 3 , a 2 ) ad 4 ) ad 0 )
4506 group rev.3.01 2005.02.07 page 59 of 111 rej03b0106-0301 mnemonic nop pof2 epof snzp dwdt wrst cmck crck tamr tmra function (pc) index list of instruction function (continued) group- ing page 67, 98 68, 98 64, 98 73, 98 64, 98 86, 98 63, 98 63, 98 78, 98 83, 98
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.3.01 2005.02.07 page 60 of 111 rej03b0106-0301 4506 group machine instructions (index by alphabet) a n (add n and accumulator) 000110nnnn 06n 11 overflow = 0 grouping: arithmetic operation description: adds the value n in the immediate field to register a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction when there is overflow as the result of operation. operation: (a) adst (a/d conversion start) 1010011111 29f 11 grouping: a/d conversion operation description: clears (0) to a/d conversion completion flag adf, and the a/d conversion at the a/d conversion mode (q1 3 = 0) or the compara- tor operation at the comparator mode (q1 3 = 1) is started. operation: (adf) am (add accumulator and memory) 0000001010 00a 11 grouping: arithmetic operation description: adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy remains unchanged. operation: (a) amc (add accumulator, memory and carry) 0000001011 00b 11 0/1 grouping: arithmetic operation description: adds the contents of m(dp) and carry flag cy to register a. stores the result in regis- ter a and carry flag cy. operation: (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 4506 group rev.3.01 2005.02.07 page 61 of 111 rej03b0106-0301 and (logical and between accumulator and memory) 0000011000 018 11 grouping: arithmetic operation description: takes the and operation between the con- tents of register a and the contents of m(dp), and stores the result in register a. operation: (a) b a (branch to address a) 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 1a 11 grouping: branch operation description: branch within a page : branches to address a in the identical page. note: specify the branch address within the page including this instruction. operation: (pc l ) bl p, a (branch long to address a in page p) 00111p 4 p 3 p 2 p 1 p 0 0p 22 grouping: branch operation description: branch out of a page : branches to address a in page p. note: p is 0 to 15 for m34506m2, and p is 0 to 31 for m34506m4/e4. operation: (pc h ) bla p (branch long to address (d) + (a) in page p) 0000010000 010 22 grouping: branch operation description: branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. note: p is 0 to 15 for m34506m2, and p is 0 to 31 for m34506m4/e4. 8 +a 2 16 100a 6 a 5 a 4 a 3 a 2 a 1 a 0 2aa e +p operation: (pc h ) dr 0 , a 3 a 0 ) 2 16 100p 4 00p 3 p 2 p 1 p 0 2pp machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.3.01 2005.02.07 page 62 of 111 rej03b0106-0301 4506 group bm a (branch and mark to address a in page 2) 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 1aa 11 grouping: subroutine call operation description: call the subroutine in page 2 : calls the subroutine at address a in page 2. note: subroutine extending from page 2 to an- other page can also be called with the bm instruction when it starts on page 2. be careful not to over the stack because the maximum level of subroutine nesting is 8. operation: (sp) a 0 bml p, a (branch and mark long to address a in page p) 00110p 4 p 3 p 2 p 1 p 0 0p 22 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address a in page p. note: p is 0 to 15 for m34506m2, and p is 0 to 31 for m34506m4/e4. be careful not to over the stack because the maximum level of subroutine nesting is 8. operation: (sp) a 0 bmla p (branch and mark long to address (d) + (a) in page p) 0000110000 030 22 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 speci- fied by registers d and a in page p. note: p is 0 to 15 for m34506m2, and p is 0 to 31 for m34506m4/e4. be careful not to over the stack because the maximum level of subroutine nesting is 8. cld (clear port d) 0000010001 011 11 grouping: input/output operation description: sets (1) to port d. operation: (d) operation: (sp) dr 0 , a 3 a 0 ) 2 16 100p 4 00p 3 p 2 p 1 p 0 2pp machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 4506 group rev.3.01 2005.02.07 page 63 of 111 rej03b0106-0301 cma (complement of accumulator) 0000011100 01c 11 grouping: arithmetic operation description: stores the one s complement for register a s contents in register a. operation: (a) cmck (clock select: ceramic resonance clock) 1010011010 29a 11 grouping: other operation description: selects the ceramic resonance circuit and stops the on-chip oscillator. operation: ceramic resonance circuit selected crck (clock select: rc oscillation clock) 1010011011 29b 11 grouping: other operation description: selects the rc oscillation circuit and stops the on-chip oscillator. operation: rc oscillation circuit selected dey (decrement register y) 0000010111 017 11 (y) = 15 grouping: ram addresses description: subtracts 1 from the contents of register y. as a result of subtraction, when the con- tents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. operation: (y) 1 machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.3.01 2005.02.07 page 64 of 111 rej03b0106-0301 4506 group di (disable interrupt) 0000000100 004 11 grouping: interrupt control operation description: clears (0) to interrupt enable flag inte, and disables the interrupt. note: interrupt is disabled by executing the di in- struction after executing 1 machine cycle. operation: (inte) dwdt (disable watchdog timer) 1010011100 29c 11 grouping: other operation description: stops the watchdog timer function by the wrst instruction after executing the dwdt instruction. operation: stop of watchdog timer function enabled epof (enable pof instruction) 0001011011 05b 11 grouping: other operation description: makes the immediate after pof or pof2 instruction valid by executing the epof in- struction. operation: pof2 instruction valid ei (enable interrupt) 0000000101 005 11 grouping: interrupt control operation description: sets (1) to interrupt enable flag inte, and enables the interrupt. note: interrupt is enabled by executing the ei in- struction after executing 1 machine cycle. operation: (inte) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 4506 group rev.3.01 2005.02.07 page 65 of 111 rej03b0106-0301 iak (input accumulator from port k) 1001101111 26f 11 grouping: input/output operation description: transfers the contents of port k to the bit 0 (a 0 ) of register a. note: after this instruction is executed, 0 is stored to the high-order 3 bits (a 3 a 1 ) of register a. operation: (a 0 ) a 1 ) iap0 (input accumulator from port p0) 1001100000 260 11 grouping: input/output operation description: transfers the input of port p0 to register a. iap1 (input accumulator from port p1) 1001100001 261 11 grouping: input/output operation description: transfers the input of port p1 to register a. operation: (a) iap2 (input accumulator from port p2) 1001100010 262 11 grouping: input/output operation description: transfers the input of port p2 to the low-or- der 2 bits (a 1 , a 0 ) of register a. note: after this instruction is executed, 0 is stored to the high-order 2 bits (a 3 , a 2 ) of register a. operation: (a 1 , a 0 ) operation: (a) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.3.01 2005.02.07 page 66 of 111 rej03b0106-0301 4506 group lz z (load register z with z) 00010010z 1 z 0 04 11 grouping: ram addresses description: loads the value z in the immediate field to register z. operation: (z) iny (increment register y) 0000010011 013 11 (y) = 0 grouping: ram addresses description: adds 1 to the contents of register y. as a re- sult of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of register y is not 0, the next instruction is executed. operation: (y) la n (load n in accumulator) 000111nnnn 07n 11 continuous description grouping: arithmetic operation description: loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la in- struction is executed and other la instructions coded continuously are skipped. operation: (a) lxy x, y (load register x and y with x and y) 11x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 3xy 11 continuous description grouping: ram addresses description: loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instruc- tions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continu- ously are skipped. operation: (x) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 4506 group rev.3.01 2005.02.07 page 67 of 111 rej03b0106-0301 nop (no operation) 0000000000 000 11 grouping: other operation description: no operation; adds 1 to program counter value, and others remain unchanged. operation: (pc) oka (output port k from accumulator) 1000011111 21f 11 grouping: input/output operation description: outputs the contents of bit 0 (a 0 ) of register a to port k. op0a (output port p0 from accumulator) 1000100000 220 11 grouping: input/output operation description: outputs the contents of register a to port p0. operation: (p0) operation: (k) machine instructions (index by alphabet) (continued) op1a (output port p1 from accumulator) 1000100001 221 11 grouping: input/output operation description: outputs the contents of register a to port p1. operation: (p1)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.3.01 2005.02.07 page 68 of 111 rej03b0106-0301 4506 group pof2 (power off2) 0000001000 008 11 grouping: other operation description: puts the system in ram back-up state by executing the pof2 instruction after ex- ecuting the epof instruction. operations of all functions are stopped. note: if the epof instruction is not executed before executing this instruction, this instruction is equivalent to the nop instruction. operation: ram back-up rar (rotate accumulator right) 0000011101 01d 11 0/1 grouping: arithmetic operation description: rotates 1 bit of the contents of register a in- cluding the contents of carry flag cy to the right. operation: op2a (output port p2 from accumulator) 1000100010 222 11 grouping: input/output operation description: outputs the contents of the low-order 2 bits (a 1 , a 0 ) of register a to port p2. operation: (p2 1 , p2 0 ) or (logical or between accumulator and memory) 0000011001 019 11 grouping: arithmetic operation description: takes the or operation between the con- tents of register a and the contents of m(dp), and stores the result in register a. operation: (a) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 4506 group rev.3.01 2005.02.07 page 69 of 111 rej03b0106-0301 rb j (reset bit) 00010011j j 04 11 grouping: bit operation description: clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). operation: (mj(dp)) machine instructions (index by alphabet) (continued) rc (reset carry flag) 0000000110 006 11 0 grouping: arithmetic operation description: clears (0) to carry flag cy. operation: (cy) rd (reset port d specified by register y) 0000010100 014 11 grouping: input/output operation description: clears (0) to a bit of port d specified by register y. note: set 0 to 3 to register y because port d is four ports (d 0 d 3 ). when values except above are set to regis- ter y, this instruction is equivalent to the nop instruction. operation: (d(y)) rcp (reset port c) 1010001100 28c 11 grouping: input/output operation description: clears (0) to port c. operation: (c)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.3.01 2005.02.07 page 70 of 111 rej03b0106-0301 4506 group rti (return from interrupt) 0001000110 046 11 grouping: return operation description: returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous description of the la/lxy in- struction, register a and register b to the states just before interrupt. rts (return from subroutine and skip) 0001000101 045 12 skip at uncondition grouping: return operation description: returns from subroutine to the routine called the subroutine, and skips the next in- struction at uncondition. operation: (pc) 1 operation: (pc) 1 sb j (set bit) 00010111j j 05 11 grouping: bit operation description: sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). operation: (mj(dp)) rt (return from subroutine) 0001000100 044 12 grouping: return operation description: returns from subroutine to the routine called the subroutine. operation: (pc) 1 machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 4506 group rev.3.01 2005.02.07 page 71 of 111 rej03b0106-0301 sc (set carry flag) 0000000111 007 11 1 grouping: arithmetic operation description: sets (1) to carry flag cy. operation: (cy) machine instructions (index by alphabet) (continued) scp (set port c) 1010001101 28d 11 grouping: input/output operation description: sets (1) to port c. operation: (c) sea n (skip equal, accumulator with immediate data n) 0000100101 025 22 (a) = n grouping: comparison operation description: skips the next instruction when the con- tents of register a is equal to the value n in the immediate field. executes the next instruction when the con- tents of register a is not equal to the value n in the immediate field. operation: (a) = n ? n = 0 to 15 sd (set port d specified by register y) 0000010101 015 11 grouping: input/output operation description: sets (1) to a bit of port d specified by register y. note: set 0 to 3 to register y because port d is four ports (d 0 d 3 ). when values except above are set to regis- ter y, this instruction is equivalent to the nop instruction. operation: (d(y))
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.3.01 2005.02.07 page 72 of 111 rej03b0106-0301 4506 group snz0 (skip if non zero condition of external 0 interrupt request flag) 0000111000 038 11 v1 0 = 0: (exf0) = 1 grouping: interrupt operation description: when v1 0 = 0 : skips the next instruction when external 0 interrupt request flag exf0 is 1. after skipping, clears (0) to the exf0 flag. when the exf0 flag is 0, executes the next instruction. when v1 0 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 0 = 0: (exf0) = 1 ? after skipping, (exf0) snzcp (skip if non zero condition of port c) 1010001001 289 11 (c) = 1 grouping: input/output operation description: skips the next instruction when the con- tents of port c is 1. executes the next instruction when the con- tents of port c is 0. operation: (c) = 1 ? snzad (skip if non zero condition of a/d conversion completion flag) 1010000111 287 11 v2 2 = 0: (adf) = 1 grouping: a/d conversion operation description: when v2 2 = 0 : skips the next instruction when a/d conversion completion flag adf is 1. after skipping, clears (0) to the adf flag. when the adf flag is 0, executes the next instruction. when v2 2 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 2 = 0: (adf) = 1 ? after skipping, (adf) seam (skip equal, accumulator with memory) 0000100110 026 11 (a) = (m(dp)) grouping: comparison operation description: skips the next instruction when the con- tents of register a is equal to the contents of m(dp). executes the next instruction when the con- tents of register a is not equal to the contents of m(dp). operation: (a) = (m(dp)) ? machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 4506 group rev.3.01 2005.02.07 page 73 of 111 rej03b0106-0301 snzi0 (skip if non zero condition of external 0 interrupt input pin) 0000111010 03a 11 i1 2 = 0 : (int) = l i1 2 = 1 : (int) = h grouping: interrupt operation description: when i1 2 = 0 : skips the next instruction when the level of int pin is l. executes the next instruction when the level of int pin is h. when i1 2 = 1 : skips the next instruction when the level of int pin is h. executes the next instruction when the level of int pin is l. operation: i1 2 = 0 : (int) = l ? i1 2 = 1 : (int) = h ? (i1 2 : bit 2 of the interrupt control register i1) machine instructions (index by alphabet) (continued) snzp (skip if non zero condition of power down flag) 0000000011 003 11 (p) = 1 grouping: other operation description: skips the next instruction when the p flag is 1 . after skipping, the p flag remains un- changed. executes the next instruction when the p flag is 0. operation: (p) = 1 ? snzt1 (skip if non zero condition of timer 1 interrupt request flag) 1010000000 280 11 v1 2 = 0: (t1f) = 1 grouping: timer operation description: when v1 2 = 0 : skips the next instruction when timer 1 interrupt request flag t1f is 1. after skipping, clears (0) to the t1f flag. when the t1f flag is 0, executes the next instruction. when v1 2 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 2 = 0: (t1f) = 1 ? after skipping, (t1f) snzt2 (skip if non zero condition of timer 2 interrupt request flag) 1010000001 281 11 v1 3 = 0: (t2f) = 1 grouping: timer operation description: when v1 3 = 0 : skips the next instruction when timer 2 interrupt request flag t2f is 1. after skipping, clears (0) to the t2f flag. when the t2f flag is 0, executes the next instruction. when v1 3 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 3 = 0: (t2f) = 1 ? after skipping, (t2f)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.3.01 2005.02.07 page 74 of 111 rej03b0106-0301 4506 group szc (skip if zero, carry flag) 0000101111 02f 11 (cy) = 0 grouping: arithmetic operation description: skips the next instruction when the con- tents of carry flag cy is 0. after skipping, the cy flag remains un- changed. executes the next instruction when the con- tents of the cy flag is 1. operation: (cy) = 0 ? szd (skip if zero, port d specified by register y) 0000100100 024 22 (d(y)) = 0 (y) = 0 to 3 grouping: input/output operation description: skips the next instruction when a bit of port d specified by register y is 0. executes the next instruction when the bit is 1. note: set 0 to 3 to register y because port d is four ports (d 0 d 3 ). when values except above are set to regis- ter y, this instruction is equivalent to the nop instruction. t1ab (transfer data to timer 1 and register r1 from accumulator and register b) 1000110000 230 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 re- load register r1. transfers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1. operation: (t1 7 t1 4 ) r1 4 ) t1 0 ) r1 0 ) operation: (d(y)) = 0 ? (y) = 0 to 3 2 16 0000101011 02b szb j (skip if zero, bit) 00001000j j 02j 11 (mj(dp)) = 0 j = 0 to 3 grouping: bit operation description: skips the next instruction when the con- tents of bit j (bit specified by the value j in the immediate field) of m(dp) is 0. executes the next instruction when the con- tents of bit j of m(dp) is 1. operation: (mj(dp)) = 0 ? j = 0 to 3 machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 4506 group rev.3.01 2005.02.07 page 75 of 111 rej03b0106-0301 t2ab (transfer data to timer 2 and register r2 from accumulator and register b) 1000110001 231 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 2 and timer 2 re- load register r2. transfers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2. operation: (t2 7 t2 4 ) r2 4 ) t2 0 ) r2 0 ) machine instructions (index by alphabet) (continued) tab (transfer data to accumulator from register b) 0000011110 01e 11 grouping: other operation description: transfers the contents of register b to reg- ister a. operation: (a) tab1 (transfer data to accumulator and register b from timer 1) 1001110000 270 11 grouping: timer operation description: transfers the high-order 4 bits (t1 7 t1 4 ) of timer 1 to register b. transfers the low-order 4 bits (t1 3 t1 0 ) of timer 1 to register a. operation: (b) t1 4 ) (a) t1 0 ) tab2 (transfer data to accumulator and register b from timer 2) 1001110001 271 11 grouping: timer operation description: transfers the high-order 4 bits (t2 7 t2 4 ) of timer 2 to register b. transfers the low-order 4 bits (t2 3 t2 0 ) of timer 2 to register a. operation: (b) t2 4 ) (a) t2 0 )
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 rev.3.01 2005.02.07 page 76 of 111 rej03b0106-0301 4506 group tabe (transfer data to accumulator and register b from register e) 0000101010 02a 11 grouping: register to register transfer description: transfers the high-order 4 bits (e 7 e 4 ) of register e to register b, and low-order 4 bits of register e to register a. operation: (b) e 4 ) (a) e 0 ) tabp p (transfer data to accumulator and register b from program memory in page p) 00100p 4 p 3 p 2 p 1 p 0 0p 13 grouping: arithmetic operation description: transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. note: p is 0 to 15 for m34506m2, and p is 0 to 31 for m34506m4/e4. when this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. operation: (sp) dr 0 , a 3 a 0 ) (b) 4 (a) 0 (pc) 1 tad (transfer data to accumulator from register d) 0001010001 051 11 grouping: register to register transfer description: transfers the contents of register d to the low-order 3 bits (a 2 a 0 ) of register a. note: when this instruction is executed, 0 is stored to the bit 3 (a 3 ) of register a. operation: (a 2 a 0 ) dr 0 ) (a 3 ) tabad (transfer data to accumulator and register b from register ad) 1001111001 279 11 grouping: a/d conversion operation description: in the a/d conversion mode (q1 3 = 0), trans- fers the high-order 4 bits (ad 9 ad 6 ) of register ad to register b, and the middle-order 4 bits (ad 5 ad 2 ) of register ad to register a. in the comparator mode (q1 3 = 1), transfers the high- order 4 bits (ad 7 ad 4 ) of comparator register to register b, and the low-order 4 bits (ad 3 ad 0 ) of comparator register to register a. operation: in a/d conversion mode (q1 3 = 0), (b) ad 6 ) (a) ad 2 ) in comparator mode (q1 3 = 1), (b) ad 4 ) (a) ad 0 ) (q1 3 : bit 3 of a/d control register q1) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 4506 group rev.3.01 2005.02.07 page 77 of 111 rej03b0106-0301 tadab (transfer data to register ad from accumulator from register b) 1000111001 239 11 grouping: a/d conversion operation description: in the a/d conversion mode (q1 3 = 0), this in- struction is equivalent to the nop instruction. in the comparator mode (q1 3 = 1), trans- fers the contents of register b to the high-order 4 bits (ad 7 ad 4 ) of comparator register, and the contents of register a to the low-order 4 bits (ad 3 ad 0 ) of compara- tor register. (q1 3 = bit 3 of a/d control register q1) operation: (ad 7 ad 4 ) ad 0 ) machine instructions (index by alphabet) (continued) tai1 (transfer data to accumulator from register i1) 1001010011 253 11 grouping: interrupt operation description: transfers the contents of interrupt control register i1 to register a. operation: (a) tak0 (transfer data to accumulator from register k0) 1001010110 256 11 grouping: input/output operation description: transfers the contents of key-on wakeup control register k0 to register a. operation: (a) tak1 (transfer data to accumulator from register k1) 1001011001 259 11 grouping: input/output operation description: transfers the contents of key-on wakeup control register k1 to register a. operation: (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 rev.3.01 2005.02.07 page 78 of 111 rej03b0106-0301 4506 group tak2 (transfer data to accumulator from register k2) 1001011010 25a 11 grouping: input/output operation description: transfers the contents of key-on wakeup control register k2 to register a. operation: (a) machine instructions (index by alphabet) (continued) tala (transfer data to accumulator from register la) 1001001001 249 11 grouping: a/d conversion operation description: transfers the low-order 2 bits (ad 1 , ad 0 ) of register ad to the high-order 2 bits (a 3 , a 2 ) of register a. note: after this instruction is executed, 0 is stored to the low-order 2 bits (a 1 , a 0 ) of register a. operation: (a 3 , a 2 ) tam j (transfer data to accumulator from memory) 101100 jjjj 2cj 11 grouping: ram to register transfer description: after transferring the contents of m(dp) to register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the re- sult in register x. tamr (transfer data to accumulator from register mr) 1001010010 252 11 grouping: other operation description: transfers the contents of clock control reg- ister mr to register a. operation: (a) operation: (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 4506 group rev.3.01 2005.02.07 page 79 of 111 rej03b0106-0301 taq1 (transfer data to accumulator from register q1) 1001000100 244 11 grouping: a/d conversion operation description: transfers the contents of a/d control regis- ter q1 to register a. operation: (a) machine instructions (index by alphabet) (continued) tasp (transfer data to accumulator from stack pointer) 0001010000 050 11 grouping: register to register transfer description: transfers the contents of stack pointer (sp) to the low-order 3 bits (a 2 a 0 ) of register a. note: after this instruction is executed, 0 is stored to the bit 3 (a 3 ) of register a. operation: (a 2 a 0 ) sp 0 ) (a 3 ) tav1 (transfer data to accumulator from register v1) 0001010100 054 11 grouping: interrupt operation description: transfers the contents of interrupt control register v1 to register a. operation: (a) tav2 (transfer data to accumulator from register v2) 0001010101 055 11 grouping: interrupt operation description: transfers the contents of interrupt control register v2 to register a. operation: (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 rev.3.01 2005.02.07 page 80 of 111 rej03b0106-0301 4506 group taw1 (transfer data to accumulator from register w1) 1001001011 24b 11 grouping: timer operation description: transfers the contents of timer control reg- ister w1 to register a. operation: (a) machine instructions (index by alphabet) (continued) taw2 (transfer data to accumulator from register w2) 1001001100 24c 11 grouping: timer operation description: transfers the contents of timer control reg- ister w2 to register a. operation: (a) taw6 (transfer data to accumulator from register w6) 1001010000 250 11 grouping: timer operation description: transfers the contents of timer control reg- ister w6 to register a. tax (transfer data to accumulator from register x) 0001010010 052 11 grouping: register to register transfer description: transfers the contents of register x to reg- ister a. operation: (a) operation: (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 4506 group rev.3.01 2005.02.07 page 81 of 111 rej03b0106-0301 tay (transfer data to accumulator from register y) 0000011111 01f 11 grouping: register to register transfer description: transfers the contents of register y to regis- ter a. operation: (a) machine instructions (index by alphabet) (continued) taz (transfer data to accumulator from register z) 0001010011 053 11 grouping: register to register transfer description: transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. note: after this instruction is executed, 0 is stored to the high-order 2 bits (a 3 , a 2 ) of register a. operation: (a 1 , a 0 ) tba (transfer data to register b from accumulator) 0000001110 00e 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter b. tda (transfer data to register d from accumulator) 0000101001 029 11 grouping: register to register transfer description: transfers the contents of the low-order 3 bits (a 2 a 0 ) of register a to register d. operation: (dr 2 dr 0 ) a 0 ) operation: (b)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 rev.3.01 2005.02.07 page 82 of 111 rej03b0106-0301 4506 group teab (transfer data to register e from accumulator and register b) 0000011010 01a 11 grouping: register to register transfer description: transfers the contents of register b to the high-order 4 bits (e 3 e 0 ) of register e, and the contents of register a to the low-order 4 bits (e 3 e 0 ) of register e. operation: (e 7 e 4 ) e 0 ) machine instructions (index by alphabet) (continued) ti1a (transfer data to register i1 from accumulator) 1000010111 217 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register i1. operation: (i1) tk0a (transfer data to register k0 from accumulator) 1000011011 21b 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k0. operation: (k0) tk1a (transfer data to register k1 from accumulator) 1000010100 214 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k1. operation: (k1)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 4506 group rev.3.01 2005.02.07 page 83 of 111 rej03b0106-0301 tk2a (transfer data to register k2 from accumulator) 1000010101 215 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k2. operation: (k2) machine instructions (index by alphabet) (continued) tma j (transfer data to memory from accumulator) 101011 jjjj 2bj 11 grouping: ram to register transfer description: after transferring the contents of register a to m(dp), an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. operation: (m(dp)) tmra (transfer data to register mr from accumulator) 1000010110 216 11 grouping: other operation description: transfers the contents of register a to clock control register mr. tpu0a (transfer data to register pu0 from accumulator) 1000101101 22d 11 grouping: input/output operation description: transfers the contents of register a to pull- up control register pu0. operation: (pu0) operation: (mr)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 rev.3.01 2005.02.07 page 84 of 111 rej03b0106-0301 4506 group tpu1a (transfer data to register pu1 from accumulator) 1000101110 22e 11 grouping: input/output operation description: transfers the contents of register a to pull- up control register pu1. operation: (pu1) machine instructions (index by alphabet) (continued) tpu2a (transfer data to register pu2 from accumulator) 1000101111 22f 11 grouping: input/output operation description: transfers the contents of register a to pull- up control register pu2. operation: (pu2) tq1a (transfer data to register q1 from accumulator) 1000000100 204 11 grouping: a/d conversion operation description: transfers the contents of register a to a/d control register q1. operation: (q1) tr1ab (transfer data to register r1 from accumulator and register b) 1000111111 23f 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits (r1 7 r1 4 ) of reload regis- ter r1, and the contents of register a to the low-order 4 bits (r1 3 r1 0 ) of reload regis- ter r1. operation: (r1 7 r1 4 ) r1 0 )
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 4506 group rev.3.01 2005.02.07 page 85 of 111 rej03b0106-0301 tv1a (transfer data to register v1 from accumulator) 0000111111 03f 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register v1. operation: (v1) machine instructions (index by alphabet) (continued) tv2a (transfer data to register v2 from accumulator) 0000111110 03e 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register v2. operation: (v2) tw1a (transfer data to register w1 from accumulator) 1000001110 20e 11 grouping: timer operation description: transfers the contents of register a to timer control register w1. operation: (w1) tw2a (transfer data to register w2 from accumulator) 1000001111 20f 11 grouping: timer operation description: transfers the contents of register a to timer control register w2. operation: (w2)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 rev.3.01 2005.02.07 page 86 of 111 rej03b0106-0301 4506 group tw6a (transfer data to register w6 from accumulator) 1000010011 213 11 grouping: timer operation description: transfers the contents of register a to timer control register w6. operation: (w6) machine instructions (index by alphabet) (continued) tya (transfer data to register y from accumulator) 0000001100 00c 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter y. operation: (y) wrst (watchdog timer reset) 1010100000 2a0 11 (wdf1) = 1 grouping: other operation description: skips the next instruction when watchdog timer flag wdf1 is 1. after skipping, clears (0) to the wdf1 flag. when the wdf1 flag is 0, executes the next instruction. also, stops the watchdog timer function when ex- ecuting the wrst instruction immediately after the dwdt instruction. operation: (wdf1) = 1 ? after skipping, (wdf1) xam j (exchange accumulator and memory data) 101101 jjjj 2dj 11 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. operation: (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 4506 group rev.3.01 2005.02.07 page 87 of 111 rej03b0106-0301 xamd j (exchange accumulator and memory data and decrement register y and skip) 101111 jjjj 2fj 11 (y) = 15 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the con- tents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. operation: (a) 1 machine instructions (index by alphabet) (continued) xami j (exchange accumulator and memory data and increment register y and skip) 101110 jjjj 2ej 11 (y) = 0 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a re- sult of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of register y is not 0, the next instruction is executed. operation: (a)
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.3.01 2005.02.07 page 88 of 111 rej03b0106-0301 4506 group (a) e 4 ) e 0 ) e 4 ) (a) e 0 ) (dr 2 dr 0 ) a 0 ) (a 2 a 0 ) dr 0 ) (a 3 ) a 0 ) sp 0 ) (a 3 ) 1 (a) 1 (a) machine instructions (index by types) 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 00010010z 1 z 0 0000010011 0000010111 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 01e 00e 01f 00c 01a 02a 029 051 053 052 050 3xy 048 +z 013 017 2cj 2dj 2fj 2ej 2bj 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ram addresses ram to register transfer register to register transfer
4506 group rev.3.01 2005.02.07 page 89 of 111 rej03b0106-0301 skip condition datailed description carry flag cy continuous description (y) = 0 (y) = 15 (y) = 15 (y) = 0 transfers the contents of register b to register a. transfers the contents of register a to register b. transfers the contents of register y to register a. transfers the contents of register a to register y. transfers the contents of register b to the high-order 4 bits (e 3 e 0 ) of register e, and the contents of regis- ter a to the low-order 4 bits (e 3 e 0 ) of register e. transfers the high-order 4 bits (e 7 e 4 ) of register e to register b, and low-order 4 bits of register e to regis- ter a. transfers the contents of the low-order 3 bits (a 2 a 0 ) of register a to register d. transfers the contents of register d to the low-order 3 bits (a 2 a 0 ) of register a. transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. transfers the contents of register x to register a. transfers the contents of stack pointer (sp) to the low-order 3 bits (a 2 a 0 ) of register a. loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instructions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continuously are skipped. loads the value z in the immediate field to register z. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next in- struction is skipped. when the contents of register y is not 0, the next instruction is executed. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. after transferring the contents of m(dp) to register a, an exclusive or operation is performed between reg- ister x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next in- struction is skipped. when the contents of register y is not 0, the next instruction is executed. after transferring the contents of register a to m(dp), an exclusive or operation is performed between reg- ister x and the value j in the immediate field, and stores the result in register x.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.3.01 2005.02.07 page 90 of 111 rej03b0106-0301 4506 group note : p is 0 to 15 for m34506m2, p is 0 to 31 for m34506m4/e4. machine instructions (index by types) (continued) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 07n 08p +p 00a 00b 06n 018 019 007 006 02f 01c 01d 05c +j 04c +j 02j 026 025 07n 000111nnnn 00100p 4 p 3 p 2 p 1 p 0 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn la n tabp p am amc a n and or sc rc szc cma rar sb j rb j szb j seam sea n 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 arithmetic operation comparison operation bit operation (a) dr 0 , a 3 a 0 ) (b) 4 (a) 0 (pc) 1 (a)
4506 group rev.3.01 2005.02.07 page 91 of 111 rej03b0106-0301 skip condition datailed description carry flag cy continuous description overflow = 0 (cy) = 0 (mj(dp)) = 0 j = 0 to 3 (a) = (m(dp)) (a) = n 0/1 1 0 0/1 loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la instruction is executed and other la instructions coded continuously are skipped. transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in ad- dress (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. when this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy re- mains unchanged. adds the contents of m(dp) and carry flag cy to register a. stores the result in register a and carry flag cy. adds the value n in the immediate field to register a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction when there is overflow as the result of operation. takes the and operation between the contents of register a and the contents of m(dp), and stores the re- sult in register a. takes the or operation between the contents of register a and the contents of m(dp), and stores the result in register a. sets (1) to carry flag cy. clears (0) to carry flag cy. skips the next instruction when the contents of carry flag cy is 0. stores the one s complement for register a s contents in register a. rotates 1 bit of the contents of register a including the contents of carry flag cy to the right. sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of m(dp) is 0. executes the next instruction when the contents of bit j of m(dp) is 1. skips the next instruction when the contents of register a is equal to the contents of m(dp). executes the next instruction when the contents of register a is not equal to the contents of m(dp). skips the next instruction when the contents of register a is equal to the value n in the immediate field. executes the next instruction when the contents of register a is not equal to the value n in the immediate field.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.3.01 2005.02.07 page 92 of 111 rej03b0106-0301 4506 group b a bl p, a bla p bm a bml p, a bmla p rti rt rts 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 00111p 4 p 3 p 2 p 1 p 0 100a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000010000 100p 4 00p 3 p 2 p 1 p 0 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 00110p 4 p 3 p 2 p 1 p 0 100a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000110000 100p 4 00p 3 p 2 p 1 p 0 0001000110 0001000100 0001000101 18a +a 0ep +p 2aa 010 2pp 1aa 0cp +p 2aa 030 2pp 046 044 045 1 2 2 1 2 2 1 1 1 1 2 2 1 2 2 1 2 2 subroutine operation return operation (pc l ) a 0 (pc h ) a 0 (pc h ) dr 0 , a 3 a 0 ) (sp) a 0 (sp) a 0 (sp) dr 0 ,a 3 a 0 ) (pc) 1 (pc) 1 (pc) 1 branch operation note : p is 0 to 15 for m34506m2, p is 0 to 31 for m34506m4/e4. machine instructions (index by types) (continued)
4506 group rev.3.01 2005.02.07 page 93 of 111 rej03b0106-0301 skip condition datailed description carry flag cy skip at uncondition branch within a page : branches to address a in the identical page. branch out of a page : branches to address a in page p. branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. call the subroutine in page 2 : calls the subroutine at address a in page 2. call the subroutine : calls the subroutine at address a in page p. call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous de- scription of the la/lxy instruction, register a and register b to the states just before interrupt. returns from subroutine to the routine called the subroutine. returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
di ei snz0 snzi0 tav1 tv1a tav2 tv2a tai1 ti1a taw1 tw1a taw2 tw2a taw6 tw6a tab1 t1ab tab2 t2ab tr1ab snzt1 snzt2 (inte) l ? i1 2 = 1 : (int) = h ? (a) t1 4 ) (a) t1 0 ) (t1 7 t1 4 ) r1 4 ) t1 0 ) r1 0 ) t2 4 ) (a) t2 0 ) (t2 7 t2 4 ) r2 4 ) t2 0 ) r2 0 ) r1 4 ) r1 0 ) machine instructions (index by types) (continued) 4506 group rev.3.01 2005.02.07 page 94 of 111 rej03b0106-0301
v1 0 = 0: (exf0) = 1 (int) = l however, i1 2 = 0 (int) = h however, i1 2 = 1 v1 2 = 0: (t1f) = 1 v1 3 = 0: (t2f) =1 skip condition datailed description carry flag cy clears (0) to interrupt enable flag inte, and disables the interrupt. sets (1) to interrupt enable flag inte, and enables the interrupt. when v1 0 = 0 : skips the next instruction when external 0 interrupt request flag exf0 is 1. after skipping, clears (0) to the exf0 flag. when the exf0 flag is 0, executes the next instruction. when v1 0 = 1 : this instruction is equivalent to the nop instruction. (v1 0 : bit 0 of interrupt control register v1) when i1 2 = 0 : skips the next instruction when the level of int pin is l. executes the next instruction when the level of int pin is h. when i1 2 = 1 : skips the next instruction when the level of int pin is h. executes the next instruction when the level of int pin is l. (i1 2 : bit 2 of interrupt control register i1) transfers the contents of interrupt control register v1 to register a. transfers the contents of register a to interrupt control register v1. transfers the contents of interrupt control register v2 to register a. transfers the contents of register a to interrupt control register v2. transfers the contents of interrupt control register i1 to register a. transfers the contents of register a to interrupt control register i1. transfers the contents of timer control register w1 to register a. transfers the contents of register a to timer control register w1. transfers the contents of timer control register w2 to register a. transfers the contents of register a to timer control register w2. transfers the contents of timer control register w6 to register a. transfers the contents of register a to timer control register w6. transfers the high-order 4 bits (t1 7 t1 4 ) of timer 1 to register b. transfers the low-order 4 bits (t1 3 t1 0 ) of timer 1 to register a. transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 reload register r1. trans- fers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1. transfers the high-order 4 bits (t2 7 t2 4 ) of timer 2 to register b. transfers the low-order 4 bits (t2 3 t2 0 ) of timer 2 to register a. transfers the contents of register b to the high-order 4 bits of timer 2 and timer 2 reload register r2. trans- fers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2. transfers the contents of register b to the high-order 4 bits (r1 7 r1 4 ) of reload register r1, and the con- tents of register a to the low-order 4 bits (r1 3 r1 0 ) of reload register r1. when v1 2 = 0 : skips the next instruction when timer 1 interrupt request flag t1f is 1. after skipping, clears (0) to the t1f flag. when the t1f flag is 0, executes the next instruction. when v1 2 = 1 : this instruction is equivalent to the nop instruction. (v1 2 : bit 2 of interrupt control register v1) when v1 3 = 0 : skips the next instruction when timer 1 interrupt request flag t2f is 1. after skipping, clears (0) to the t2f flag. when the t2f flag is 0, executes the next instruction. when v1 3 = 1 : this instruction is equivalent to the nop instruction. (v1 3 : bit 3 of interrupt control register v1) 4506 group rev.3.01 2005.02.07 page 95 of 111 rej03b0106-0301
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.3.01 2005.02.07 page 96 of 111 rej03b0106-0301 4506 group iap0 op0a iap1 op1a iap2 op2a cld rd sd szd scp rcp snzcp iak oka tk0a tak0 tk1a tak1 tk2a tak2 tpu0a tpu1a tpu2a 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 260 220 261 221 262 222 011 014 015 024 02b 28d 28c 289 26f 21f 21b 256 214 259 215 25a 22d 22e 22f 1001100000 1000100000 1001100001 1000100001 1001100010 1000100010 0000010001 0000010100 0000010101 0000100100 0000101011 1010001101 1010001100 1010001001 1001101111 1000011111 1000011011 1001010110 1000010100 1001011001 1000010101 1001011010 1000101101 1000101110 1000101111 input/output operation (a) a 1 ) machine instructions (index by types) (continued)
4506 group rev.3.01 2005.02.07 page 97 of 111 rej03b0106-0301 skip condition datailed description carry flag cy (d(y)) = 0 ? (y) = 0 to 3 (c) = 1 transfers the input of port p0 to register a. outputs the contents of register a to port p0. transfers the input of port p1 to register a. outputs the contents of register a to port p1. transfers the input of port p2 to the low-order 2 bits (a 1 , a 0 ) of register a. outputs the contents of the low-order 2 bits (a 1 , a 0 ) of register a to port p2. sets (1) to port d. clears (0) to a bit of port d specified by register y. sets (1) to a bit of port d specified by register y. skips the next instruction when a bit of port d specified by register y is 0. executes the next instruction when a bit of port d specified by register y is 1. sets (1) to port c. clears (0) to port c. skips the next instruction when the contents of port c is 1. executes the next instruction when the contents of port c is 0. transfers the contents of port k to the bit 0 (a 0 ) of register a. outputs the contents of bit 0 (a 0 ) of register a to port k. transfers the contents of register a to key-on wakeup control register k0. transfers the contents of key-on wakeup control register k0 to register a. transfers the contents of register a to key-on wakeup control register k1. transfers the contents of key-on wakeup control register k1 to register a. transfers the contents of register a to key-on wakeup control register k2. transfers the contents of key-on wakeup control register k2 to register a. transfers the contents of register a to pull-up control register pu0. transfers the contents of register a to pull-up control register pu1. transfers the contents of register a to pull-up control register pu2.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation rev.3.01 2005.02.07 page 98 of 111 rej03b0106-0301 4506 group tabad tala tadab taq1 tq1a adst snzad nop pof2 epof snzp dwdt wrst cmck crck tamr tmra 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 279 249 239 244 204 29f 287 000 008 05b 003 29c 2a0 29a 29b 252 216 1001111001 1001001001 1000111001 1001000100 1000000100 1010011111 1010000111 0000000000 0000001000 0001011011 0000000011 1010011100 1010100000 1010011010 1010011011 1001010010 1000010110 a/d conversion operation other operation in a/d conversion mode (q1 3 = 0), (b) ad 6 ) (a) ad 2 ) in comparator mode (q1 3 = 1), (b) ad 4 ) (a) ad 0 ) (a 3 , a 2 ) ad 4 ) ad 0 ) machine instructions (index by types) (continued)
4506 group rev.3.01 2005.02.07 page 99 of 111 rej03b0106-0301 skip condition datailed description carry flag cy v2 2 = 0: (adf) = 1 (p) = 1 (wdf1) = 1 in the a/d conversion mode (q1 3 = 0), transfers the high-order 4 bits (ad 9 ad 6 ) of register ad to register b, and the middle-order 4 bits (ad 5 ad 2 ) of register ad to register a. in the comparator mode (q1 3 = 1), transfers the high-order 4 bits (ad 7 ad 4 ) of comparator register to reg- ister b, and the low-order 4 bits (ad 3 ad 0 ) of comparator register to register a. (q1 3 : bit 3 of a/d control register q1) transfers the low-order 2 bits (ad 1 , ad 0 ) of register ad to the high-order 2 bits (ad 3 , ad 2 ) of register a. in the a/d conversion mode (q1 3 = 0), this instruction is equivalent to the nop instruction. in the comparator mode (q1 3 = 1), transfers the contents of register b to the high-order 4 bits (ad 7 ad 4 ) of comparator register, and the contents of register a to the low-order 4 bits (ad 3 ad 0 ) of comparator register. (q1 3 = bit 3 of a/d control register q1) transfers the contents of a/d control register q1 to register a. transfers the contents of register a to a/d control register q1. clears (0) to a/d conversion completion flag adf, and the a/d conversion at the a/d conversion mode (q1 3 = 0) or the comparator operation at the comparator mode (q1 3 = 1) is started. (q1 3 = bit 3 of a/d control register q1) when v2 2 = 0 : skips the next instruction when a/d conversion completion flag adf is 1. after skipping, clears (0) to the adf flag. when the adf flag is 0, executes the next instruction. when v2 2 = 1 : this instruction is equivalent to the nop instruction. (v2 2 : bit 2 of interrupt control register v2) no operation; adds 1 to program counter value, and others remain unchanged. puts the system in ram back-up state by executing the pof2 instruction after executing the epof instruction. operations of all functions are stopped. makes the immediate after pof2 instruction valid by executing the epof instruction. skips the next instruction when the p flag is 1 . after skipping, the p flag remains unchanged. executes the next instruction when the p flag is 0. stops the watchdog timer function by the wrst instruction after executing the dwdt instruction. skips the next instruction when watchdog timer flag wdf1 is 1. after skipping, clears (0) to the wdf1 flag. when the wdf1 flag is 0, executes the next instruction. also, stops the watchdog timer function when ex- ecuting the wrst instruction immediately after the dwdt instruction. selects the ceramic resonance circuit and stops the on-chip oscillator. selects the rc oscillation circuit and stops the on-chip oscillator. transfers the contents of clock control register mr to register a. transfers the contents of register a to clock control register mr.
rev.3.01 2005.02.07 page 100 of 111 rej03b0106-0301 4506 group instruction code table d 3 d 0 hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f d 9 d 4 00 nop snzp di ei rc sc pof2 am amc tya tba 000001 01 bla cld iny rd sd dey and or teab cma rar tab tay 000010 02 szb 0 szb 1 szb 2 szb 3 szd sean seam tda tabe szc 000011 03 bmla snz0 snzi0 tv2a tv1a 000100 04 rt rts rti lz 0 lz 1 lz 2 lz 3 rb 0 rb 1 rb 2 rb 3 000101 05 tasp tad tax taz tav1 tav2 epof sb 0 sb 1 sb 2 sb 3 000110 06 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 000111 07 la 0 la 1 la 2 la 3 la 4 la 5 la 6 la 7 la 8 la 9 la 10 la 11 la 12 la 13 la 14 la 15 001000 08 tabp 0 tabp 1 tabp 2 tabp 3 tabp 4 tabp 5 tabp 6 tabp 7 tabp 8 tabp 9 tabp 10 tabp 11 tabp 12 tabp 13 tabp 14 tabp 15 001001 09 tabp 16* tabp 17* tabp 18* tabp 19* tabp 20* tabp 21* tabp 22* tabp 23* tabp 24* tabp 25* tabp 26* tabp 27* tabp 28* tabp 29* tabp 30* tabp 31* 001010 0a 001011 0b 001100 0c 001101 0d 001110 0e 001111 0f bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bml* bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bl* bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm 010000 010111 011000 011111 18 1f b b b b b b b b b b b b b b b b bl bml bla bmla sea szd the second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 * cannot be used in the M34506M2-XXXFP. 10 17 000000 the above table shows the relationship between machine language codes and machine language instructions. d 3 d 0 show the low-order 4 bits of the machine language code, and d 9 d 4 show the high-order 6 bits of the machine language code. the hexadecimal representa- tion of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each i nstruction is shown. do not use code marked . the codes for the second word of a two-word instruction are described below.
4506 group rev.3.01 2005.02.07 page 101 of 111 rej03b0106-0301 instruction code table (continued) tq1a tw1a tw2a tw6a tk1a tk2a tmra ti1a tk0a oka t1ab t2ab tadab tr1ab taq1 tala taw1 taw2 taw6 tamr tai1 tak0 tak1 tak2 iap0 iap1 iap2 iak tab1 tab2 tabad snzt1 snzt2 snzad snzcp rcp scp cmck crck dwdt adst wrst tam 0 tam 1 tam 2 tam 3 tam 4 tam 5 tam 6 tam 7 tam 8 tam 9 tam 10 tam 11 tam 12 tam 13 tam 14 tam 15 xam 0 xam 1 xam 2 xam 3 xam 4 xam 5 xam 6 xam 7 xam 8 xam 9 xam 10 xam 11 xam 12 xam 13 xam 14 xam 15 xami 0 xami 1 xami 2 xami 3 xami 4 xami 5 xami 6 xami 7 xami 8 xami 9 xami 10 xami 11 xami 12 xami 13 xami 14 xami 15 xamd 0 xamd 1 xamd 2 xamd 3 xamd 4 xamd 5 xamd 6 xamd 7 xamd 8 xamd 9 xamd 10 xamd 11 xamd 12 xamd 13 xamd 14 xamd 15 lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy tma 0 tma 1 tma 2 tma 3 tma 4 tma 5 tma 6 tma 7 tma 8 tma 9 tma 10 tma 11 tma 12 tma 13 tma 14 tma 15 bl bml bla bmla sea szd the second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 op0a op1a op2a tpu0a tpu1a tpu2a d 3 d 0 hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f d 9 d 4 20 100001 21 100010 22 100011 23 100100 24 100101 25 100110 26 100111 27 101000 28 101001 29 101010 2a 101011 2b 101100 2c 101101 2d 101110 2e 101111 2f 110000 111111 30 3f 100000 the above table shows the relationship between machine language codes and machine language instructions. d 3 d 0 show the low- order 4 bits of the machine language code, and d 9 d 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use code marked . the codes for the second word of a two-word instruction are described below.
rev.3.01 2005.02.07 page 102 of 111 rej03b0106-0301 4506 group parameter supply voltage input voltage p0, p1, p2, d 0 , d 1 , d 2 /c, d 3 /k, reset , x in input voltage a in0 a in1 output voltage p0, p1, p2, d 0 , d 1 , d 2 /c, d 3 /k, reset output voltage x out power dissipation operating temperature range storage temperature range conditions output transistors in cut-off state ta = 25 c symbol v dd v i v i v o v o p d topr tstg unit v v v v v mw c c ratings 0.3 to 6.5 0.3 to v dd +0.3 0.3 to v dd +0.3 0.3 to v dd +0.3 0.3 to v dd +0.3 300 20 to 85 40 to 125 electrical characteristics absolute maximum ratings
4506 group rev.3.01 2005.02.07 page 103 of 111 rej03b0106-0301 symbol v dd v dd v ram v ss v ih v ih v ih v ih v il v il v il v il i ol (peak) i ol (peak) i ol (peak) i ol (peak) i ol (avg) i ol (avg) i ol (avg) i ol (avg) h level input voltage h level input voltage h level input voltage h level input voltage l level input voltage l level input voltage l level input voltage l level input voltage l level peak output current l level peak output current l level peak output current l level peak output current l level average output current l level average output current l level average output current l level average output current l level total average current note : the average output current (i oh , i ol ) is the average value during 100 ms. unit conditions high-speed mode middle-speed mode low-speed mode default mode high-speed mode middle-speed mode low-speed mode default mode (at ram back-up) p0, p1, p2, d 0 d 3 , x in reset c, k cntr, int p0, p1, p2, d 0 d 3 , x in c, k reset cntr, int p2, reset d 0 , d 1 d 2 /c, d 3 /k p0, p1 p2, reset (note) d 0 , d 1 (note) d 2 /c, d 3 /k (note) p0, p1 (note) p2, d, reset p0, p1 max. 5.5 5.5 5.5 v dd v dd v dd v dd v dd 0.2v dd 0.16v dd 0.3v dd 0.15v dd 10 4.0 40 30 24 12 24 12 5.0 2.0 30 15 15 7.0 12 6.0 80 80 limits min. 2.7 2.0 2.7 1.8 0.8v dd 0.85v dd 0.5v dd 0.7v dd 0.85v dd 0 0 0 0 typ. 0 f(x in ) recommended operating conditions 1 (ta = 20 c to 85 c, v dd = 2.0 to 5.5 v, unless otherwise noted)
rev.3.01 2005.02.07 page 104 of 111 rej03b0106-0301 4506 group 4.4 2.0 2.7 5.5 v dd [v] 2.2 4.4 2.0 5.5 v dd [v] 4.4 2.7 5.5 v dd [v] rc oscillation circuit selected 3.2 2.0 2.7 5.5 v dd [v] 1.6 3.2 2.0 5.5 v dd [v] ceramic resonator and high-speed mode selected except ceramic resonator and high-speed mode external clock input, high-speed mode selected (ceramic resonator selected) except external clock input, high-speed mode (ceramic resonator selected) recommended operating condition recommended operating condition recommended operating condition recommended operating condition recommended operating condition f [mhz] f [mhz] f [mhz] f [mhz] f [mhz]
4506 group rev.3.01 2005.02.07 page 105 of 111 rej03b0106-0301 f(x in ) f(x in ) f(x in ) ? h and l pulse width) conditions mhz mhz mhz % hz s max. 4.4 2.2 4.4 4.4 3.2 1.6 3.2 ?7 ?7 f(x in )/6 f(x in )/12 f(x in )/24 f(x in )/48 limits high-speed mode middle-speed mode low-speed mode default mode high-speed mode middle-speed mode low-speed mode default mode high-speed mode middle-speed mode low-speed mode default mode v dd = 5.0 v ?0 %, ta = 25 c, 20 to 85 c v dd = 3.0 v ?0 %, ta = 25 c, 20 to 85 c high-speed mode middle-speed mode low-speed mode default mode high-speed mode middle-speed mode low-speed mode default mode min. typ. 3/f(x in ) 6/f(x in ) 12/f(x in ) 24/f(x in ) parameter symbol unit note: the frequency at rc oscillation is affected by a capacitor, a resistor and a microcomputer. so, set the constants within the range of the frequency limits. v dd = 2.7 v to 5.5 v v dd = 2.0 v to 5.5 v v dd = 2.0 v to 5.5 v v dd = 2.7 v to 5.5 v v dd = 2.7 v to 5.5 v v dd = 2.0 v to 5.5 v v dd = 2.0 v to 5.5 v recommended operating conditions 2 (ta = 20 c to 85 c, v dd = 2.0 to 5.5 v, unless otherwise noted)
rev.3.01 2005.02.07 page 106 of 111 rej03b0106-0301 4506 group v ol v ol v ol v ol i ih i ih i il i il i dd r pu v t+ v t v t+ v t f(ring) l level output voltage p0, p1 l level output voltage p2, reset l level output voltage d 0 , d 1 l level output voltage d 2 /c, d 3 /k h level input current p0, p1, p2, reset h level input current d 0 , d 1 , d 2 /c, d 3 /k l level input current p0, p1, p2 l level input current d 0 , d 1 , d 2 /c, d 3 /k supply current pull-up resistor value p0, p1, p2, d 2 /c, d 3 /k, reset hysteresis int, cntr hysteresis reset on-chip oscillator clock frequency (note 2) at active mode (note 1) at ram back-up mode (pof2 instruction execution) v v v v ? c v dd = 5.0 v v dd = 3.0 v v i = 0 v v dd = 5.0 v v dd = 3.0 v v dd = 5.0 v v dd = 3.0 v v dd = 5.0 v v dd = 3.0 v limits max. 2.0 0.9 0.9 0.6 2.0 0.6 0.9 2.0 0.9 2.0 0.9 2.0 0.9 2.0 0.9 1.0 1.0 5.0 3.9 3.3 3.0 1.5 1.2 1.1 0.9 1.0 10 6.0 150 300 3.0 1.8 i ol = 12 ma i ol = 4.0 ma i ol = 6.0 ma i ol = 2.0 ma i ol = 5.0 ma i ol = 1.0 ma i ol = 2.0 ma i ol = 30 ma i ol = 10 ma i ol = 15 ma i ol = 5.0 ma i ol = 15 ma i ol = 5.0 ma i ol = 9.0 ma i ol = 3.0 ma high-speed mode middle-speed mode low-speed mode default mode high-speed mode middle-speed mode low-speed mode default mode v dd = 5.0 v v dd = 3.0 v min. 1.0 1.0 30 50 1.0 0.5 typ. 1.7 1.3 1.1 1.0 0.5 0.4 0.35 0.3 0.1 60 120 0.25 0.25 1.2 0.5 2.0 1.0 symbol parameter unit notes 1: when the a/d converter is used, the a/d operation current (ia dd ) is included. 2: when system operates by the on-chip oscillator, the system clock frequency is the on-chip oscillator clock divided by the di viding ratio selected with register mr. electrical characteristics (ta = 20 c to 85 c, v dd = 2.0 to 5.5 v, unless otherwise noted)
4506 group rev.3.01 2005.02.07 page 107 of 111 rej03b0106-0301 symbol v dd v ia f(x in ) parameter supply voltage analog input voltage oscillation frequency conditions unit v v mhz ta = 25 c ta = 20 c to 85 c v dd = 2.7 v to 5.5 v high-speed mode middle-speed mode low-speed mode default mode min. 2.7 3.0 0 0.1 0.2 0.4 0.8 typ. max. 5.5 5.5 v dd +2lsb limits symbol v 0t v fst ia dd t conv parameter resolution linearity error differential non-linearity error zero transition voltage full-scale transition voltage a/d operating current (note 1) a/d conversion time comparator resolution comparator error (note 2) comparator comparison time test conditions bits lsb lsb mv mv ma c, v dd = 2.7 v to 5.5 v ta = 25 c to 85 c, v dd = 3.0 v to 5.5 v ta = 25 c, v dd = 2.7 v to 5.5 v ta = 25 c to 85 c, v dd = 3.0 v to 5.5 v v dd = 5.12 v v dd = 3.072 v v dd = 5.12 v v dd = 3.072 v v dd = 5.0 v v dd = 3.0 v f(x in ) = 4.0 mhz high-speed mode middle-speed mode low-speed mode default mode v dd = 5.12 v v dd = 3.072 v f(x in ) = 4.0 mhz high-speed mode middle-speed mode low-speed mode default mode min. 10 3 5115 3063 typ. 20 9 5125 3069 0.3 0.1 max. 10 ?.0 ?.9 30 15 5135 3075 0.9 0.3 46.5 93.0 186 372 8 ?0 ?5 6.0 12 24 48 limits notes 1: when the a/d converter is used, the ia dd is included to i dd . 2: as for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logic v alue of the comparison voltage v ref which is generated by the built-in da converter can be obtained by the following formula. logic value of comparison voltage v ref v ref = ? a/d converter recommended operating conditions (comparator mode included, ta = 20 c to 85 c, unless otherwise noted) a/d converter characteristcs (comparator mode included, ta = 20 c to 85 c, unless otherwise noted)
rev.3.01 2005.02.07 page 108 of 111 rej03b0106-0301 4506 group x i n : h i g h - s p e e d m o d e ( s y s t e m c l o c k = f ( x i n ) ) parameter p i n n a m e m a c h i n e c y c l e mi mi+1 d 0 , d 1 , d 2 / c , d 3 / k p 0 0 ep 0 3 p1 0 e p1 3 p 0 0 e p 0 3 p 1 0 e p 1 3 p 2 0 , p 2 1 x i n : m i d d l e - s p e e d m o d e ( s y s t e m c l o c k = f ( x i n ) / 2 ) p 2 0 , p 2 1 c l o c k p o r t d o u t p u t port d input p o r t p 0 , p 1 , p 2 o u t p u t p o r t p 0 , p 1 , p 2 i n p u t cntr timer output x i n : l o w - s p e e d m o d e ( s y s t e m c l o c k = f ( x i n ) / 4 ) x i n : d e f a u l t m o d e ( s y s t e m c l o c k = f ( x i n ) / 8 ) d 0 , d 1 , d 2 /c, d 3 /k int interrupt input c n t r t i m e r i n p u t basic timing diagram
4506 group rev.3.01 2005.02.07 page 109 of 111 rej03b0106-0301 table 20 product of built-in prom version prom size ( ? ? built-in prom version in addition to the mask rom versions, the 4506 group has the one time prom versions whose proms can only be written to and not be erased. the built-in prom version has functions similar to those of the mask rom versions, but it has prom mode that enables writing to built-in prom. table 20 shows the product of built-in prom version. figure 54 shows the pin configurations of built-in prom versions. the one time prom version has pin-compatibility with the mask rom version. (1) prom mode the 4506 group has a prom mode in addition to a normal opera- tion mode. it has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in prom using only a few pins. this mode can be selected by setting pins sda (serial data input/output), s clk (serial clock input), pgm to h after connecting wires as shown in figure 54 and powering on the v dd pin, and then apply- ing 12 v to the v pp pin. in the prom mode, three types of software commands (read, pro- gram, and program verify) can be used. clock-synchronous serial i/o is used, beginning from the lsb (lsb first). use the special-perpose serial programmer when performing serial read/program. as for the serial programmer for the single-chip microcomputer (se- rial programmer and control software), refer to the renesas microcomputer development support tools hompage ( http:// www.renesas.com/en/tools). fig. 53 flow of writing and test of the product shipped in blank rom type package part number writing with prom programmer screening (leave at 150 note ) verify test with prom programmer f u n c t i o n t e s t i n t a r g e t d e v i c e s i n c e t h e s c r e e n i n g t e m p e r a t u r e i s h i g h e r t h a n s t o r a g e t e m p e r a t u r e , n e v e r e x p o s e t h e m i c r o c o m p u t e r t o 1 5 0 note: (2) notes on handling ? ?
rev.3.01 2005.02.07 page 110 of 111 rej03b0106-0301 4506 group fig. 54 pin configuration of built-in prom version pin configuration (top view) o u t l i n e p r s p 0 0 2 0 d a - a ( 2 0 p 2 n - a ) 2 3 4 5 6 7 8 9 1 0 1 19 18 17 16 15 14 13 12 11 20 m 3 4 5 0 6 e 4 f p p2 1 /a in1 p1 2 /cntr p1 3 /int x i n x o u t c n v s s v s s v d d p2 0 /a in0 reset d 3 /k d 2 /c d 0 d 1 p0 3 p0 2 p0 1 p0 0 p1 1 p1 0 v d d v s s v p p s c l k s d a v dd p g m
4506 group rev.3.01 2005.02.07 page 111 of 111 rej03b0106-0301 package outline 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. 1.42 1.12 b p a 1 h e y0.1 e 1.27 c 0 8 l 0.4 0.6 0.8 00.10.2 a2.1 7.5 7.8 8.1 a 2 1.8 e5.25.35.4 d 12.5 12.6 12.7 reference symbol dimension in millimeters min nom max 0.35 0.4 0.5 0.18 0.2 0.25 p-sop20-5.3x12.6-1.27 0.3g mass[typ.] 20p2n-a prsp0020da-a renesas code jeita package code previous code detail f l a 2 a 1 y index mark * 1 * 2 * 3 1 10 11 20 f h e e e b p a c d
rev. rev. no. date 1.0 first edition 000808 1.1 pages 3, 4, 22, 38 : character fonts errors revised 000905 2.0 the 4506/4507 group data sheet is separated. 010531 page 10: port block diagram (3); block diagram of p1 2 /cntr pin revised. page 26: fig. 22 timers structure; block diagram of p1 2 /cntr pin revised. page 29: ( 9) precautions 0.3 to 6. 0 0.3 to 6. 5 page 104: recommended operating conditions 1; operating condition map added. 3.0 all pages: words standardized: on-chip oscillator, a/d converter 040827 page 3: power dissipation ta=25 c added. page 4: ____________ description of reset pin revised. page 24: table 9 : control register of timer 1 and timer 2 revised. page 25: fig.22 : note 5 added. page 29: some description revised. page 30: fig.25 : di instruction added. page 31: table 11: revised. page 39: table 15 : port level and note 4 revised, note 5 added. page 50: 21 electric characteristic differences between mask rom and one time prom version mcu, 22 note on power source voltage added. page 76: tabad : description revised. page 99: tabad : description revised. revision description list 4506 group data sheet (1/2) revision description
rev. rev. no. date 3.01 page 1, 3: package name revised. 050207 page 28: timer 1 and timer 2 count start timing and count time when operation starts added. page 47: 10 timer 1 and timer 2 count start timing and count time when operation starts added. p109, 110: package name revised. p111: package outline revised. revision description list 4506 group data sheet (2/2) revision description
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