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micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2006-01 preliminary specifications 1 micro netw orks an integrated circuit systems compan y iso 9001 registered iso 9001 registered m2006-01 frequency synthesizer applications sonet / sdh / 10gbe system synchronization add / drop muxes, access and edge switches line card system clock cleaner / t ranslator optical module clock cleaner / translator description the m2006-01 integrates a high performance phase locked loop (pll) with a voltage controlled saw oscillator (vcso) to provide a low jitter frequency synthesizer in a 9mm x 9mm surface mount package. the internal high ??saw filter provides low jitter signal performance and determines the output frequency of the vcso. selecting between two differential lvpecl clocks or one single-ended lvcmos / lvttl clock provides the input r eference signal to the frequency translator. the maximum input frequency is 700mhz. the m2006-01 will default to a multiplying factor of 32 on power-up. the multiplying factor can be changed by serially programming the input and feedback dividers via the configuration logic. a differential lvpecl signal provides the output clock for the device. a second differential output which can be programmed to divide the output frequency by a factor of 4 is also available. the output frequency can be momentarily increased or decreased to add or subtract one net output clock cycle by asserting the add_clk or drop_clk inputs, respectively. an external loop filter sets the pll bandwidth which can be optimized to provide jitter attenuation of the input reference clock. a phase slope limiting feature, which reduces phase build-out in order to meet gr-253 mtie upon an input transient, can be manually selected by asserting the psl input. the phase slope limiting feature is automatically activated whenever a new input reference clock is selected. the frequency agility, bandwidth control, and phase slope limiting features make the m2006-01 ideal for use as a clock jitter attenuator, frequency translator, and clock frequency generator in oc-3 through oc-192 applications. inputs, v i : ................................................. -0.5 to v cc +0.5v output, v o : ................................................. -0.5 to v cc +0.5v supply voltage, v cc : ......................................................... 4.6 v storage temperature, t sto : ............................ -45 c to +100 c absolute max ratings output clock frequency up to 700mhz intrinsic jitter <1ps rms (12khz - 50mhz) automatic phase slope limiting dual differential inputs input compatible with lvpecl, lvds, hstl, sstl, etc. t riple input mux configurable input and feedback dividers t unable loop filter response t wo differential lvpecl outputs single 3.3v supply small 9mm x 9mm smt package features stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2006-01 preliminary specifications 2 micro netw orks an integrated circuit systems compan y functional block diagram the inter nal pll will adjust the vcso output fr equency to be m (feedback divider) divided by r (input divider) times the selected input r efer ence clock fr equency . note that the ratio of m/r times input fr equency must be such that it falls within the lock range of the vcso. the m divider (10-bits) can be pr ogrammed for a maximum value of 1023 and a minimum value of 4. the r divider (9-bits) can be set to a maximum value of 511 and a minimum value of 1. ther e ar e two dif fer ential l vpecl outputs (fout 0, fout 1) which operate at the vcso fr equency . when p1 is high the fout 1 output will operate at 1/4 the vcso fr equency and when p1 is low fout 1 output operates at the vcso fr equency . the r elationship between the vcso fr equency , the m and r dividers, and the input ref_clk is defined as follows: f vcso = f ref_clk x m / r on power -up the r and m dividers ar e set to 1 and 32, r espectively . the input r efer ence clock is selected fr om dif_clk 0, dif_clk 1, or ref_clk by selecting the appr opriate ref_sel 0 and ref_sel 1 inputs. when a new r efer ence is selected the m2006-01 will automatically switch to the phase slope limiting mode to control the phase build-out of the output clocks. the add_clk and drop_clk inputs incr ements or decr ements the m (feedback) divider for one phase detector cycle. this r esults in a momentar y incr ease or decrease in output frequency and an extra or missing output clock cycle r elative to the input re fer enc e clo ck . the "phase slope limiter" is used to ensure mtie compliance. the psl input provides manual control.
when psl is high, the output phase slope is limited by changing the phase detector gain to a non-linear function. . the m2006-01 is serially programmed via a 3 wire interface. refer to the timing diagram below (labeled "serial programming") for the following explanation. serial operation begins at point "(a)", when s_load is low; the shift register is loaded one bit at-a-time by sampling the s_data bits with the rising edge of s_clock. divider load occurs at point "(b)" , when s_load transitions from low to high; all of the data in the shift register is loaded into the r and m dividers. latch occurs at point "(c)", on the high-to-low transition of s_load; divider values will not be affected by serial input. (if s_load is held high, any s_data input is passed directly to the r and m dividers on each rising edge of s_clock.) note: t1 and t0, which are used for test automation, must be set to 0. t2 is set to 1 for normal bandwidth, 0 for narrow bandwidth. s_data t2 t1 t0 r8 r7 r6 r5 r4 r3 r2 r1 r0 m9 m8 m7 m6 m5 m4 m3 m2 m1 m0 s_clock s_l oad serial programming m2006-01 saw delay line phase shifter vcso c post c post vc nvc r post nop_out op_out r post r loop r loop c loop c loop r in r in op_in nop_in m divider m = 3-1024 power-up default = 32 serial configuration register phase detector loop filter amplifier external loop filter components fout0 nfout0 s_data s_clock s_load r divider r = 1-511 power-up default = 1 mux 00 ref_sel1:0 ref_clk dif_ref1 ndif_ref1 dif_ref0 ndif_ref0 01 1x 2 add_clk drop_clk p divider p = 1 ( p1 = 0 ) or 4 ( p1 = 1 ) fout1 nfout1 p1 psl (a) (b) (c)
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2006-01 preliminary specifications 3 micro netw orks an integrated circuit systems compan y functional description loop filter figure 2 the m2006-01 requires the use of an external loop filter via the provided filter pins. due to the differential design, the implementation requires two identical rc filters as shown in figure 2. rloop rloop cloop cloop cpost cpost rpost rpost table 1. example of loop filter values input reference frequency = 19.44mhz; vcso frequency = 622.0800mhz pll damping r loop c loop r post c post bandwidth factor 330hz 2.0 3.9k ? 2.2 f 20k ? 250pf 1015hz 2.0 12k ? .22 f 20k ? 250pf 1975hz 2.7 24k ? .1 f 20k ? 250pf
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2006-01 preliminary specifications 4 micro netw orks an integrated circuit systems compan y pin descriptions table 2 pin number name i/o configuration description 1, 2, 3 gnd gnd power supply ground 4, 9 op_in, nop_in analog i/o used for external loop filter. see figure 2. 5, 8 nop_out, op_out analog i/o used for external loop filter. see figure 2. 6, 7 nvc, vc input vcso differential control voltage input pair 10, 14, 26 gnd gnd power supply ground 11, 19, 33 vcc power positive supply pins 12, 13 fout1, nfout1 output unterminated differential output, 3.3v lvpecl levels. 15, 16 fout0, nfout0 output unterminated differential output, 3.3v lvpecl levels. 17 p1 input pull - down determines the output divider value. lvcmos / lvttl interface levels. 18 s_clock input pull - down clocks in serial data present at s_data input into the shift register on the rising edge of s_clock. l vcmos / lvttl interface levels. 20 s_data input pull - down shift register serial input. data is sampled on the rising edge of s_clock. lvcmos / lvttl interface levels. 21 s_load input pull - down controls transition of data from shift register into the dividers. lvcmos / lvttl interface levels. 22, 29 ref_sel1, ref_sel0 input pull - down selects between the different reference clock inputs as the pll reference source. lvcmos / lvttl interface levels. 23 ndif_clk0 input pull - up inverting differential clock input. l vcmos / lvttl interface levels. 24 dif_clk0 input pull - down non-inverting differential clock input. lvcmos / lvttl interface levels. 25 ref_clk input pull - down reference clock input. lvcmos / lvttl interface levels. 27 ndif_clk1 input pull - up inverting differential clock input. lvpecl levels. 28 dif_clk1 input pull - down non-inverting differential clock input. 30 add_clk input pull - down increases the output frequency by one output clock cy c le for a given input clock cycle. the added clock occurs during the next input clock period following the rising edge of add_clk. only one output clock can be added for each input reference clock cycle. lvcmos / l vttl interface levels. 31 drop_clk input pull - down decreases the output frequency by one output clock cy c le for a given input clock cycle. the deletion occurs during the next input clock period following the rising edge of drop_clk. only one output clock can be deleted for each input reference clock cycle. lvcmos / l vttl interface levels. 32 psl input pull - down asserting psl (phase slope limiter) causes a decrease in the loop bandwidth by reducing the phase detector gain. lvcmos / lvttl interface levels. 34, 35, 36 dnc no connection. internal test pins must be left floating.
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2006-01 preliminary specifications 5 micro netw orks an integrated circuit systems compan y table 5 table 4 pin characteristics inputs s_load s_ clock s_data conditions l b data serial input mode. shift register loads state of s_data on each rising clock of s_clock. (however, serial input does not affect the values in the r and m dividers.) b ld at a entire contents of the shift register are passed (all at once) to the r and m dividers. ? l d a ta r and m divider values are latched. lx x serial input does not affect the values in the r and m dividers. h b data serial input affects dividers: s_data passed directly to r and m dividers as it is clocked. note: l = low; h = high; x = don't care; b = rising edge transition; ? = falling edge transition table 5c inputs ref_sel1 ref_sel0 reference 00 dif_clk0, ndif_clk0 01 dif_clk1, ndif_clk1 1x ref_clk reference select function table serial mode function symbol parameter test conditions min typical max units c in input capacitance 4 pf r pullup input pullup resistor 51 k 1 r pulldown input pulldown resistor 51 k 1
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2006-01 preliminary specifications 6 micro netw orks an integrated circuit systems compan y symbol parameter test conditions min max units v ih input high ref_sel0, ref_sel1, s_load, 2 v cc + 0.3 v v oltage s_data, s_clk, add_clk, drop_clk, p1, psl, ref_clk v il input low ref_sel0, ref_sel1, s_load, -0.3 0.8 v v oltage s_data, s_clk, add_clk, drop_clk, p1, psl, ref_clk i ih input high ref_sel0, ref_sel1, s_load, 150 a current s_data, s_clk, add_clk, drop_clk, p1, psl, ref_clk i il input low ref_sel0, ref_sel1, s_load, -5 a current s_data, s_clk, add_clk, drop_clk, p1, psl, ref_clk l vcmos/lvttl dc characteristics v cc = 3.3v 5%, t a = 0 c to 70 c symbol parameter test conditions min typ max units v cc po wer supply voltage 3.135 3.3 3.465 v i cc po wer supply current 162 ma v cc = 3.3v 5%, t a = 0 c to 70 c power supply dc characteristics v cc = 3.3v 5%, t a = 0 c to 70 c differential input dc characteristics symbol parameter test conditions min typ max units lib input high ndif_clk0, ndif_clk1 5 a current dif_clk0, dif_clk1 150 a iil input high ndif_clk0, ndif_clk1 -150 a current dif_clk0, dif_clk1 -5 a v p-p p eak to peak input voltage 0.15 v v cmr common mode input voltage 0.5 v cc - .85 v l vpecl dc characteristics symbol parameter test conditions min max units v oh output high voltage v cc e 1.4 v cc e 1.0 v v ol output low voltage v cc e 2.0 v cc e 1.7 v v p-p p eak-to-peak output voltage 0.6 0.85 v note 1: output terminated with 50 1 to v cc e2.v
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2006-01 preliminary specifications 7 micro netw orks an integrated circuit systems compan y input frequency characteristics symbol parameter test conditions min max units f in input frequency dif_clk0, ndif_clk0 0.3 700 mhz dif_clk1, ndif_clk1 s_clock 50 mhz ref_clk 0.3 200 mhz note 1: output terminated with 50 1 to v cc e2.v ac characteristics symbol parameter test conditions min typ max units f out output frequency 75 700 mhz n single side band 1khz offset 1khz offset -72 dbc/hz phase noise 10khz offset 10khz offset -94 dbc/hz @ 622mhz 100khz offset 100khz offset -123 dbc/hz j (t) jitter (rms) non-deterministic 50khz to 80mhz 0.50 1 ps odc output duty cycle 50 % t r output rise time fout = 155mhz 20% to 80%, each 350 450 550 ps (note 1) for output pairs fout = 311mhz output of pair measured 325 425 500 ps fout0, nfout0 & fout = 622mhz is terminated into 50 1 200 275 350 ps fout1, nfout1 load biased at vcc-2v t f output fall time fout = 155mhz 20% to 80%, each 350 450 550 ps (note 1) for output pairs fout = 311mhz output of pair measured 325 425 500 ps fout0, nfout0 & fout = 622mhz is terminated into 50 1 200 275 350 ps fout1, nfout1 load biased at vcc-2v t s setup time s_data to s_clk 5 ns s_clk to s_load 5 ns t h hold time s_data to s_clk 5 ns s_clk to s_load 5 ns t lock pll lock time 100 ms t pw input pulse width s_load 10 ns add_clk 10 ns drop_clk 10 ns mtie mean time interval error compliant with gr-253-core note: the output frequencies of 155mhz, 311mhz and 622mhz were chosen for device characterization as these are common optical n etwork clock frequencies.
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2006-01 preliminary specifications 8 micro netw orks an integrated circuit systems compan y odc & t period setup and hold time thold tset-up s_data s_clock s_load clock inputs and outputs 20% 80% 80% 20% t r t f v swing pulse width t period t pw t period odc = differential input level input and output rise and fall time parameter measurement information v cmr cross points v pp vcc ndiff_clk diff_clk vee
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2006-01 preliminary specifications 9 micro netw orks an integrated circuit systems compan y connection via to 3.3v power plane ferrite chip 0.01f 1 nf vcc pin 11 0.01f vcc pin 19 vcc pin 33 4.7f 0.01f 0.01f recommended power supply decoupling
micro networks 32 4 clark street w orcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com m2006-01 preliminary specifications 10 micro netw orks an integrated circuit systems compan y recommended footprint micro networks an integrated circuit systems company 32 4 clark street worcester, ma 01606 tel: 508-852-5400 fax: 508-852-8456 european sales headquarters hertogsingel 20 6214 ad maastricht t he netherlands tel: +31-43-32-70912 fax: +31-43-32-70715 www.micronetworks.com micro networks makes no assertion or warranty that the circuitry and the uses thereof disclosed herein are non-infringing on any valid us or foreign patents. micro networks assumes no liability as a result of the use of said specifications and reserves the right to make changes to specifications without notice. contact your nearest micro networks sales representative office for the latest specifications. mechanical dimensions & pin configuration rev. 11.2 ordering information pin# designation 1 gnd 2 gnd 3 gnd 4 op_in 5 nop_out 6 nvc 7vc 8 op_out 9 nop_in 10 gnd 11 vcc 12 fout1 13 nfout1 14 gnd 15 fout0 16 nfout0 17 p1 1. dimensions are in inches, (dimensions) are in mm. pin# designation 18 s_clock 19 vcc 20 s_data 21 s_load 22 ref_sel1 23 ndif_clk0 24 dif_clk0 25 ref_clk 26 gnd 27 ndif_clk1 28 dif_clk1 29 ref_sel0 30 add_clk 31 drop_clk 32 psl 33 vcc 34, 35, 36 dnc a vailable vcso frequencies 622.0800 669.1281 625.0000 669.3266 627.3296 672.1600 644.5313 690.5692 666.5143 693.4830 part number m2006-01-622.0800 series model vcso center frequency (i.e. 622.0800mhz)

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