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user?s manual pd789304 pd789306 pd789314 pd789316 pd78f9306 pd78f9316 pd789306, 789316 subseries 8-bit single-chip microcontrollers printed in japan document no. u14800ej2v0ud00 (2nd edition) date published april 2004 ns cp(k) 2000, 2004
2 user?s manual u14800ej2v0ud [memo]
user?s manual u14800ej2v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices eeprom and fip are trademarks of nec electronics corporation. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trad emarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc.
4 user?s manual u14800ej2v0ud these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of august, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate suffici ent safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
user?s manual u14800ej2v0ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
user?s manual u14800ej2v0ud 6 introduction target readers this manual is intended to give user engineers an understanding of the functions of the pd789306 and pd789316 subseries to design and develop its application systems and programs. target products: ? pd789306 subseries: pd789304, 789306, 78f9306 ? pd789316 subseries: pd789314, 789316, 78f9316 for the main system clock frequency, f x is applied to ceramic/crystal oscillation ( pd789306 subseries) and f cc is applied to rc oscillation ( pd789316 subseries). purpose this manual is designed to deepen your understanding of the following functions using the following organization. organization two manuals are available for the pd789306 and pd789316 subseries: this manual and the instruction manual (common to the 78k/0s series). pd789306, 789316 subseries user?s manual 78k/0s series user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other internal peripheral functions ? electrical specifications ? cpu function ? instruction set ? instruction description how to use this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to understand the overa ll functions of the pd789306 and pd789316 subseries read this manual in the order of the contents . the mark shows major revised points. ? how to read register formats where the bit number is enclosed in angle brackets (<>), the bit name is reserved for the assembler and is defined as an sfr variable by the #pragma sfr directive for the c compiler. ? to learn the detailed functions of a register whose register name is known see appendix c . ? to learn the details of the instru ction functions of the 78k/0s series refer to 78k/0s series instructions user?s manual (u11047e) separately available. ? to learn the electrical specifications of the pd789306 and pd789316 subseries refer to chapter 22 electrical specifications .
user?s manual u14800ej2v0ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd789306, 789316 subseries user ?s manual this manual 78k/0s series instructions user?s manual u11047e documents related to developmen t software tools (user?s manuals) document name document no. operation u16656e language u14877e ra78k0s assembler package structured assembly language u11623e operation u16654e cc78k0s c compiler language u14872e operation u16768e sm78k series ver. 2.52 system simulator external part user open inte rface specifications u15802e id78k0s-ns ver. 2.52 integrated debugger operation u16584e pm plus ver. 5.10 u16569e documents related to development hardware tools (user?s manuals) document name document no. ie-78k0s-ns in-circuit emulator u13549e ie-78k0s-ns-a in-circuit emulator u15207e ie-789306-ns-em1 emulation board u16115e caution the related documen ts listed above are subject to change without notice. be sure to use the latest version of each document for designing.
user?s manual u14800ej2v0ud 8 documents related to flash memory writing document name document no. pg-fp3 flash memory progr ammer user?s manual u13502e pg-fp4 flash memory progr ammer user?s manual u15260e other related documents document name document no. semiconductor selection guide - products and packages - x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? w ebpage (http://www.necel.com/pkg/en/mount/index.html) caution the related documen ts listed above are subject to change without notice. be sure to use the latest version of each document for designing.
user?s manual u14800ej2v0ud 9 contents chapter 1 general ( pd789306 subseries)................................. ........................................... 15 1.1 features ................................................................................................................... ................... 15 1.2 applications ............................................................................................................... ................ 15 1.3 ordering information ....................................................................................................... .......... 16 1.4 pin configuration (top view) ................................... ............................................................ .... 17 1.5 78k/0s series lineup ....................................................................................................... ......... 19 1.6 block diagram.............................................................................................................. .............. 22 1.7 overview of functions ...................................................................................................... ........ 23 chapter 2 general ( pd789316 subseries)................................. ........................................... 25 2.1 features ................................................................................................................... ................... 25 2.2 applications ............................................................................................................... ................ 25 2.3 ordering information ....................................................................................................... .......... 26 2.4 pin configuration (top view) ................................... ............................................................ .... 27 2.5 78k/0s series lineup ....................................................................................................... ......... 29 2.6 block diagram.............................................................................................................. .............. 32 2.7 overview of functions ...................................................................................................... ........ 33 chapter 3 pin functions ( pd789306 subseries) ................................................................ 35 3.1 list of pin functions ...................................................................................................... ........... 35 3.2 description of pin functions ...................................... ......................................................... ..... 37 3.2.1 p00 to p03 (por t 0) ...................................................................................................... ................. 37 3.2.2 p10 to p13 (por t 1) ...................................................................................................... ................. 37 3.2.3 p20 to p26 (por t 2) ...................................................................................................... ................. 37 3.2.4 p30 to p33 (por t 3) ...................................................................................................... ................. 38 3.2.5 p50 to p53 (por t 5) ...................................................................................................... ................. 38 3.2.6 s0 to s23 ................................................................................................................ ...................... 38 3.2.7 com0 to com3 ............................................................................................................. ............... 38 3.2.8 v lc0 to v lc2 ............................................................................................................................... .... 38 3.2.9 caph , capl............................................................................................................... .................. 38 3.2.10 reset ................................................................................................................... ....................... 39 3.2.11 x1 , x2 .................................................................................................................. ......................... 39 3.2.12 xt1, xt2................................................................................................................ ....................... 39 3.2.13 v dd ............................................................................................................................... ................. 39 3.2.14 v ss ............................................................................................................................... ................. 39 3.2.15 v pp ( pd78f9306 only) ................................................................................................................ 39 3.2.16 ic (mask ro m versi on onl y) .............................................................................................. ........... 39 3.3 pin input/output circuits and recommended conn ection of unused pins ....................... 40 chapter 4 pin functions ( pd789316 subseries) ................................................................ 42 4.1 list of pin functions ...................................................................................................... ........... 42
user?s manual u14800ej2v0ud 10 4.2 description of pin functions ............................................................................................... .....44 4.2.1 p00 to p03 (por t 0) ...................................................................................................... ................. 44 4.2.2 p10 to p13 (por t 1) ...................................................................................................... ................. 44 4.2.3 p20 to p26 (por t 2) ...................................................................................................... ................. 44 4.2.4 p30 to p33 (por t 3) ...................................................................................................... ................. 45 4.2.5 p50 to p53 (por t 5) ...................................................................................................... ................. 45 4.2.6 s0 to s23 ................................................................................................................ ...................... 45 4.2.7 com0 to com3 ............................................................................................................. ............... 45 4.2.8 v lc0 to v lc2 ............................................................................................................................... .... 45 4.2.9 caph , capl............................................................................................................... .................. 46 4.2.10 reset ................................................................................................................... ....................... 46 4.2.11 cl1, cl2 ................................................................................................................ ....................... 46 4.2.12 xt1, xt2................................................................................................................ ....................... 46 4.2.13 v dd ............................................................................................................................... ................. 46 4.2.14 v ss ............................................................................................................................... ................. 46 4.2.15 v pp ( pd78f9316 only) ................................................................................................................ 46 4.2.16 ic (mask ro m versi on onl y) .............................................................................................. ........... 47 4.3 pin input/output circuits and recommended conn ection of unused pins........................48 chapter 5 cpu archi tecture ................................................................................................. .....50 5.1 memory space............................................................................................................... .............50 5.1.1 internal progr am memory space ............................................................................................ ....... 53 5.1.2 internal data memory (i nternal high-speed ram) spac e ............................................................... 54 5.1.3 special function register (s fr) area ..................................................................................... ........ 54 5.1.4 data memo ry addre ssing ................................................................................................... ........... 55 5.2 processor registers ........................................................................................................ ..........58 5.2.1 control regist ers........................................................................................................ .................... 58 5.2.2 general-pur pose regi sters................................................................................................ ............. 61 5.2.3 special functi on register s (sfrs)........................................................................................ .......... 62 5.3 instruction address addressing .................................... ......................................................... .65 5.3.1 relative addre ssing ...................................................................................................... ................. 65 5.3.2 immediat e addre ssing ..................................................................................................... .............. 66 5.3.3 table indi rect addr essing ................................................................................................ .............. 67 5.3.4 register addre ssing ...................................................................................................... ................ 67 5.4 operand address addr essing ................................................................................................. .68 5.4.1 direct addressi ng ........................................................................................................ .................. 68 5.4.2 short dire ct addre ssing .................................................................................................. ............... 69 5.4.3 special function r egister (sfr ) addre ssing ............................................................................... .... 70 5.4.4 register addre ssing ...................................................................................................... ................ 71 5.4.5 register i ndirect addr essing............................................................................................. ............. 72 5.4.6 based addressi ng ......................................................................................................... ................ 73 5.4.7 stack addressi ng......................................................................................................... .................. 73
user?s manual u14800ej2v0ud 11 chapter 6 port f unctions................................................................................................... ........ 74 6.1 port functions............................................................................................................. ............... 74 6.2 port configuration ......................................................................................................... ............ 76 6.2.1 po rt 0 ................................................................................................................... ......................... 77 6.2.2 po rt 1 ................................................................................................................... ......................... 78 6.2.3 po rt 2 ................................................................................................................... ......................... 79 6.2.4 po rt 3 ................................................................................................................... ......................... 83 6.2.5 po rt 5 ................................................................................................................... ......................... 85 6.3 registers controlling port functi on........................................................................................ 86 6.4 port function operation.................................................................................................... ........ 90 6.4.1 writing to i/o port...................................................................................................... .................... 90 6.4.2 reading fr om i/o port .................................................................................................... ............... 90 6.4.3 arithmetic oper ation of i/o port ......................................................................................... ............ 90 chapter 7 clock generator ( pd789306 subseries) ....................................................... 91 7.1 clock generator functions......................................... ......................................................... ..... 91 7.2 clock generator configuration .................................. ............................................................ .. 91 7.3 registers controlling clock generator ..................... .............................................................. 93 7.4 system clock oscillators................................................................................................... ....... 96 7.4.1 main system clock osc illator............................................................................................. ............. 96 7.4.2 subsystem cl ock osc illator ............................................................................................... ............. 97 7.4.3 examples of incorre ct resonator connec tion ............................................................................... .. 98 7.4.4 divider circ uit .......................................................................................................... ...................... 99 7.4.5 when no subsystem clock is used .......................................................................................... ...... 99 7.5 clock generator operation....................................... ........................................................... ...100 7.6 changing setting of system clo ck and cpu clock ............................................................. 101 7.6.1 time required for switching between system clock and cpu cl ock ............................................. 101 7.6.2 switching between system clock and cp u cloc k ........................................................................ 102 chapter 8 clock generator ( pd789316 subseries) ..................................................... 103 8.1 clock generator functions......................................... ......................................................... ...103 8.2 clock generator configuration .................................. ............................................................ 103 8.3 registers controlling clock generator ................... .............................................................. 105 8.4 system clock oscillators................................................................................................... ..... 108 8.4.1 main system clock osc illator............................................................................................. ........... 108 8.4.2 subsystem cl ock osc illator ............................................................................................... ........... 109 8.4.3 examples of incorre ct resonator connec tion ............................................................................... 110 8.4.4 divider circ uit .......................................................................................................... .................... 113 8.4.5 when no subsystem clock is used .......................................................................................... .... 113 8.5 clock generator operation....................................... ........................................................... ...114 8.6 changing setting of system clo ck and cpu clock ............................................................. 115 8.6.1 time required for switching between system clock and cpu cl ock ............................................. 115 8.6.2 switching between system clock and cp u cloc k ........................................................................ 116
user?s manual u14800ej2v0ud 12 chapter 9 16-bit timer 20.................................................................................................. ...........117 9.1 16-bit timer 20 functions .................................................................................................. .....117 9.2 16-bit timer 20 configuration.............................................................................................. ...118 9.3 registers controlling 16-bit timer 20.......................... ..........................................................12 0 9.4 16-bit timer 20 operation .................................................................................................. .....123 9.4.1 operation as timer in terrupt............................................................................................. ............ 123 9.4.2 operation as time r out put................................................................................................ ............ 125 9.4.3 captur e operat ion ........................................................................................................ ............... 126 9.4.4 16-bit timer counter 20 r eadout .......................................................................................... ......... 127 9.5 cautions on using 16-bit timer 20 .............................. ..........................................................12 8 9.5.1 restrictions when rewriti ng 16-bit compare register 20 ............................................................... 128 chapter 10 8-bit timer 30, 40.............................................................................................. .........130 10.1 8-bit timer 30, 40 functions .............................................................................................. .....130 10.2 8-bit timer 30, 40 configuration............................... ........................................................... ...131 10.3 registers controlling 8-bit timer 30, 40 ..................... ..........................................................136 10.4 8-bit timer 30, 40 operation .............................................................................................. .....141 10.4.1 operation as 8-bit time r count er........................................................................................ .......... 141 10.4.2 operation as 16-bit time r count er....................................................................................... ......... 151 10.4.3 operation as carrier generat or .......................................................................................... .......... 158 10.4.4 operation as pwm output (timer 40 onl y) ................................................................................. .. 163 10.5 notes on using 8-bit timer 30, 40................................ ......................................................... .165 chapter 11 watch time r ..................................................................................................... ........167 11.1 watch timer functions ..................................................................................................... ......167 11.2 watch timer configuratio n................................................................................................. ....169 11.3 register controlling watch timer............................ .............................................................. 170 11.4 watch timer operation ..................................................................................................... .......171 11.4.1 operation as watch timer ................................................................................................ ............ 171 11.4.2 operation as interval timer ............................................................................................. ............. 171 chapter 12 watchdog timer .................................................................................................. ...173 12.1 watchdog timer functions.................................................................................................. ...173 12.2 watchdog timer configuration .... .......................................................................................... 174 12.3 registers controlling watchdog timer ......................... ........................................................175 12.4 watchdog timer operation.................................................................................................. ...177 12.4.1 operation as watchdog timer ............................................................................................. ......... 177 12.4.2 operation as interval timer ............................................................................................. ............. 178 chapter 13 serial interface 10 ................................ ............................................................ ..179 13.1 serial interface 10 functions ............................................................................................. .....179 13.2 serial interface 10 configuratio n......................................................................................... ...180 13.3 register controlling serial in terface 10 ................................................................................18 2
user?s manual u14800ej2v0ud 13 13.4 serial interface 10 operation .................................... ......................................................... ..... 184 13.4.1 operati on stop mode ..................................................................................................... .............. 184 13.4.2 3-wire se rial i/o mode .................................................................................................. ............... 185 chapter 14 serial interface 20 ............................... ............................................................. ..187 14.1 serial interface 20 functions.................................... ......................................................... ..... 187 14.2 serial interface 20 configuratio n ......................................................................................... ..188 14.3 registers controlling serial inte rface 20 .............................................................................. 192 14.4 serial interface 20 operation .................................... ......................................................... ..... 199 14.4.1 operati on stop mode ..................................................................................................... .............. 199 14.4.2 asynchronous serial interface (uar t) mode .............................................................................. 2 01 14.4.3 3-wire se rial i/o mode .................................................................................................. ............... 214 chapter 15 lcd controller/driver.............................. ......................................................... 219 15.1 lcd controller/driver functions................................ ........................................................... .219 15.2 lcd controller/driver configuration ....................... .............................................................. 21 9 15.3 registers controlling lcd contro ller/driver ........................................................................ 222 15.4 setting lcd controller/driver............................................................................................. .... 226 15.5 lcd display data memory ................................................................................................... ...226 15.6 common and segment signals ..................................... ......................................................... 22 7 15.7 display modes............................................................................................................. ............. 229 15.7.1 three-time slot display example ......................................................................................... ........ 229 15.7.2 four-time slot display example .......................................................................................... ......... 232 15.8 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 ............................................................. 235 chapter 16 interrupt functions ................................... ......................................................... 2 36 16.1 interrupt function typ es.................................................................................................. ....... 236 16.2 interrupt sources and configuratio n..................................................................................... 23 6 16.3 registers controlling interrupt function ................ .............................................................. 239 16.4 interrupt servicing operation ............................................................................................. .... 245 16.4.1 non-maskable interrupt r equest acknowledgment operatio n ...................................................... 245 16.4.2 maskable interrupt reques t acknowledgment operatio n .............................................................. 247 16.4.3 multiple inte rrupt serv icing ............................................................................................ .............. 248 16.4.4 putting interrupt requests on hol d ...................................................................................... ......... 250 chapter 17 standby function...................................... .......................................................... ..251 17.1 standby function and configuratio n .................................................................................... 251 17.1.1 standby functi on ........................................................................................................ ................. 251 17.1.2 register contro lling standby functi on ................................................................................... ....... 252 17.2 standby function operation ...................................... .......................................................... ..253 17.2.1 halt mode............................................................................................................... .................. 253 17.2.2 stop mode ............................................................................................................... ................. 256 chapter 18 reset function .................................................................................................. ..... 259
user?s manual u14800ej2v0ud 14 chapter 19 flash memory..................................................................................................... ......262 19.1 flash memory characteristi cs.............................................................................................. ..263 19.1.1 programmi ng envir onment ................................................................................................. ......... 263 19.1.2 communi cation mode ...................................................................................................... ........... 264 19.1.3 on-board pin connec tions ................................................................................................ ........... 267 19.1.4 connection when using flas h memory writ ing adapt er ................................................................ 270 chapter 20 mask options .................................................................................................... .......274 chapter 21 instruction set ................................................................................................. .....275 21.1 operation ................................................................................................................. .................275 21.1.1 operand identifiers and descripti on met hods ............................................................................. . 275 21.1.2 description of ?operation? column....................................................................................... ........ 276 21.1.3 description of ?flag? column ............................................................................................ ........... 276 21.2 operation list............................................................................................................ ...............277 21.3 instructions listed by addr essing type ...............................................................................282 chapter 22 electrical specifications.......................... ........................................................285 chapter 23 characteristics cur ves of lcd controller/driver (reference values) ................................................ ...............................................304 chapter 24 package draw ings ................................................................................................. 306 chapter 25 recommended soldering conditions..... ........................................................308 appendix a development tools............................................................................................... 310 a.1 software package ........................................................................................................... .........312 a.2 language processing software ........................................ .....................................................31 2 a.3 control software ........................................................................................................... ...........313 a.4 flash memory writing tools ................................................................................................. ..313 a.5 debugging tools (hardwar e)................................................................................................. .314 a.6 debugging tools (software) ................................................................................................. ..315 appendix b cautions on design ing target system ..........................................................316 appendix c register index .................................................................................................. .......320 c.1 register index (alphabetic order of register na me)...........................................................320 c.2 register index (alphabetic order of register sy mbol) .......................................................322 appendix d revision history ................................................................................................. .....324 d.1 major revisions in this edition............................................................................................ ..324
user?s manual u14800ej2v0ud 15 chapter 1 general ( pd789306 subseries) 1.1 features main system clock: ceramic/crystal oscillation minimum instruction execution ti me can be changed from high-speed (0.4 s: @ 5.0 mhz operation with main system clock) to ultra-low-speed (122 s: @ 32.768 khz operation with subsystem clock) rom and ram capacities item data memory part number program memory (rom) internal high-speed ram lcd display ram pd789304 8 kb pd789306 mask rom 16 kb pd78f9306 flash memory 16 kb 512 bytes 24 4 bits i/o ports: 23 serial interface: 2 channels switchable between 3-wire serial i/o mode and uart mode: 1 channel 3-wire serial i/o mode: 1 channel timer: 5 channels 16-bit timer: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel lcd controller/driver segment signals: 24, common signals: 4 vectored interrupt sources: 15 power supply voltage: v dd = 1.8 to 5.5 v operating ambient temperature: t a = ?40 to +85 c 1.2 applications remote controllers, healthcare equipment, etc.
chapter 1 general ( pd789306 subseries) user?s manual u14800ej2v0ud 16 1.3 ordering information part number package internal rom pd789304gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom pd789304gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom pd789306gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom pd789306gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom pd78f9306gc-ab8 64-pin plastic qfp (14 14 mm) flash memory pd78f9306gk-9et 64-pin plastic tqfp (12 12 mm) flash memory remark indicates rom code suffix.
chapter 1 general ( pd789306 subseries) user?s manual u14800ej2v0ud 17 1.4 pin configuration (top view) 64-pin plastic qfp (14 14 mm) 64-pin plastic tqfp (fine pitch) (12 12 mm) pd789304gc- -ab8 pd789304gk- -9et pd789306gc- -ab8 pd789306gk- -9et pd78f9306gc-ab8 pd78f9306gk-9et 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p50 p51 p52 p53 ic (v pp ) xt1 xt2 v dd v ss x1 x2 reset p00/kr0 p01/kr1 p02/kr2 p03/kr3 32 caph capl v lc0 v lc1 v lc2 com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 p20/sck10 p21/so10 p22/si10 p23/sck20/asck20 p24/so20/txd20 p25/si20/rxd20 p26/to20 p30/intp0/cpt20 p31/intp1/to30/tmi40 p32/intp2/to40 p33/intp3 p10 p11 p12 p13 s23 caution connect the ic (internally connected) pin directly to v ss . remark the parenthesized values apply to pd78f9306.
chapter 1 general ( pd789306 subseries) user?s manual u14800ej2v0ud 18 asck20: asynchronous serial input s0 to s23: segment output caph, capl: lcd power supply capacitance control sck10, sck20: serial clock com0 to com3: common output si10, si20: serial input cpt20: capture trigger input so10, so20: serial output ic: internally connected tmi40: timer input intp0 to intp3: external interrupt input to20, to30, to40: timer output kr0 to kr3: key return txd20: transmit data p00 to p03: port 0 v dd : power supply p10 to p13: port 1 v lc0 to v lc2 : lcd power supply p20 to p26: port 2 v pp : programming power supply p30 to p33: port 3 v ss : ground p50 to p53: port 5 x1, x2: crystal/ceramic oscillator reset: reset xt1, xt2: crystal oscillator rxd20: receive data
chapter 1 general ( pd789306 subseries) user?s manual u14800ej2v0ud 19 1.5 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 52-pin sio + resistance division method lcd (24 4) 8-bit a/d + internal voltage boosting method lcd (23 4) pd789327 lcd drive 80-pin 80-pin pd789436 pd789446 pd789426 pd789456 pd789417a pd789407a pd789316 pd789467 pd789306 pd789426 with 10-bit a/d pd789860 with enhanced timer function, sio, and expanded rom and ram pd789446 with 10-bit a/d sio + 8-bit a/d + resistance division method lcd (28 4) sio + 8-bit a/d + internal voltage boosting method lcd (15 4) pd789407a with 10-bit a/d sio + 8-bit a/d + internal voltage boosting method lcd (5 4) rc oscillation version of pd789306 sio + internal voltage boosting method lcd (24 4) 64-pin 64-pin 52-pin 64-pin 64-pin 64-pin sio + 10-bit a/d + internal voltage boosting method lcd (28 4) 80-pin sio + 8-bit a/d + resistance division method lcd (28 4) 80-pin pd789478 pd789488 64-pin products under development products in mass production small-scale package, general-purpose applications 78k/0s series 28-pin pd789014 with enhanced timer function and expanded rom and ram on-chip uart and capable of low-voltage (1.8 v) operation pd789074 with subsystem clock added inverter control 44-pin pd789842 on-chip inverter controller and uart pd789146 pd789156 44-pin small-scale package, general-purpose applications and a/d function 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 30-pin 30-pin pd789104a pd789114a pd789167 with 10-bit a/d pd789104a with enhanced timer function pd789124a with 10-bit a/d rc oscillation version of pd789104a pd789104a with 10-bit a/d pd789026 with 8-bit a/d and multiplier added pd789104a with eeprom added pd789146 with 10-bit a/d pd789177y pd789167y y subseries supports smb. usb 88-pin pd789830 pd789835 144-pin uart + dot lcd (40 16) uart + 8-bit a/d + dot lcd (total display outputs: 96) 42-/44-pin 44-pin 30-pin 20-pin 20-pin pd789026 with enhanced timer function rc oscillation version of pd789052 vfd drive 52-pin 64-pin pd789871 on-chip vfd controller (total display outputs: 25) meter control pd789881 uart + resistance division method lcd (26 4) 30-pin pd789074 with enhanced timer function and expanded rom and ram 44-pin pd789800 for pc keyboard. on-chip usb function keyless entry 20-pin 20-pin 30-pin on-chip poc and key return circuit rc oscillation version of pd789860 on-chip bus controller 30-pin 44-pin pd789850a on-chip can controller pd789074 pd789088 pd789062 pd789014 pd789046 pd789026 pd789052 pd789860 pd789861 pd789862 pd789852 pd789860 without eeprom tm , poc, and lvi pd789850a with enhanced timer, a/d, etc. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same.
chapter 1 general ( pd789306 subseries) user?s manual u14800ej2v0ud 20 the major functional differences am ong the subseries are listed below. series for general-purpose applications and lcd drive timer v dd function subseries rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min.value remarks pd789046 16 k 1 ch pd789026 4 k to 16 k 1 ch 34 pd789088 16 k to 32 k 3 ch pd789074 2 k to 8 k 1 ch 1 ch 24 pd789014 2 k to 4 k 2 ch ? ? 1 ch ? ? 1 ch (uart: 1 ch) 22 1.8 v ? pd789062 4 k ? 14 rc-oscillation version small- scale package, general- purpose applica- tions pd789052 ? pd789177 ? 8 ch pd789167 16 k to 24 k 3 ch 1 ch 8 ch ? 31 ? pd789156 ? 4 ch pd789146 8 k to 16 k 4 ch ? on-chip eeprom pd789134a ? 4 ch pd789124a 4 ch ? rc-oscillation version pd789114a ? 4 ch small- scale package, general- purpose applica- tions + a/d converter pd789104a 2 k to 8 k 1 ch 1 ch ? 1 ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? pd789835 24 k to 60 k 6 ch ? 3 ch 37 1.8 v note pd789830 24 k 1 ch ? 1 ch (uart: 1 ch) 30 2.7 v dot lcd supported pd789488 32 k to 48 k ? 8 ch pd789478 24 k to 48 k 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 k to 24 k 3 ch 1 ch 1 ch 1 ch 7 ch ? 1 ch (uart: 1 ch) 43 1.8 v ? pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 k to 16 k 6 ch 40 pd789316 rc-oscillation version pd789306 8 k to 16 k ? 2 ch (uart: 1 ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 k to 24 k 2 ch ? ? ? 1 ch 21 ? note flash memory version: 3.0 v
chapter 1 general ( pd789306 subseries) user?s manual u14800ej2v0ud 21 series for assp timer v dd function subseries rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min.value remarks usb pd789800 8 k 2 ch ? ? 1 ch ? ? 2 ch (usb: 1 ch) 31 4.0 v ? inverter control pd789842 8 k to 16 k 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? pd789852 24 k to 32k 3 ch ? 8 ch 3 ch (uart: 2 ch) 31 on-chip bus controller pd789850a 16 k 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1 ch) 18 4.0 v ? pd789861 1.8 v rc-oscillation version, on-chip eeprom pd789860 4 k 2 ch ? ? 1 ch ? ? ? 14 keyless entry pd789862 16 k 1 ch 2 ch 1 ch (uart: 1 ch) 22 on-chip eeprom vfd drive pd789871 4 k to 8 k 3 ch ? 1 ch 1 ch ? ? 1 ch 33 2.7 v ? meter control pd789881 16 k 2 ch 1 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 28 2.7 v note 2 ? notes 1. 10-bit timer: 1 channel 2. flash memory version: 3.0 v
chapter 1 general ( pd789306 subseries) user?s manual u14800ej2v0ud 22 1.6 block diagram v dd v ss ic (v pp ) 78k/0s cpu core rom (flash memory) to30/tmi40 /intp1/p31 8-bit timer 30 p00 to p03 port 0 p10 to p13 port 1 p20 to p26 port 2 p30 to p33 port 3 p50 to p53 port 5 tmi40/to30 /intp1/p31 to20/p26 16-bit timer 20 watch timer watchdog timer serial interface 20 sck20/asck20/p23 si20/rxd20/p25 so20/txd20/p24 s0 to s23 com0 to com3 ram ram space for lcd data 8-bit tmer/event counter 40 cascaded 16-bit timer/ event counter to40/intp2/p32 cpt20/intp0 /p30 serial interface 10 sck10/p20 si10/p22 so10/p21 v lc0 to v lc2 caph capl lcd controller driver system control reset cl1 cl2 xt1 xt2 interrupt control intp0/cpt20/ p30 intp1/to30/ tmi40/p31 intp2/to40/ p32 intp3/p33 kr0/p00 to kr3/p03 remarks 1. the internal rom capacity varies depending on the product. 2. the parenthesized values apply to pd78f9306.
chapter 1 general ( pd789306 subseries) user?s manual u14800ej2v0ud 23 1.7 overview of functions part number item pd789304 pd789306 pd78f9306 internal memory rom mask rom flash memory 8 kb 16 kb 16 kb high-speed ram 512 bytes lcd display ram 24 4 bits system clock ceramic/crystal oscillation minimum instruction execution time 0.4 s/1.6 s (@ 5.0 mhz operation with main system clock) 122 s (@ 32.768 khz operation with subsystem clock) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulations (such as set, reset, and test) multiplier 8 bits 8 bits = 16 bits i/o ports total: 23 cmos i/o: 19 n-ch open-drain: 4 serial interfaces switchable between 3-wi re serial i/o mode and uart mode: 1 channel 3-wire serial i/o mode: 1 channel timers 16-bit timer: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer outputs 3 lcd controller/driver segment signal outputs: 24 max. common signal outputs: 4 max. maskable internal: 9, external: 5 vectored interrupt sources non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to + 85c package 64-pin plastic qfp (14 14 mm) 64-pin plastic tqfp (12 12 mm)
chapter 1 general ( pd789306 subseries) 24 user?s manual u14800ej2v0ud an outline of the timer is shown below. 16-bit timer 20 8?bit timer 30 8-bit timer/event counter 40 watch timer watchdog timer interval timer ? 1 channel 1 channel 1 channel note 1 1 channel note 2 operation mode external event counter ? ? 1 channel ? ? timer outputs 1 1 1 ? ? square-wave outputs ? 1 1 ? ? capture 1 input ? ? ? ? function interrupt sources 1 1 1 2 2 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has the watchdog timer and interv al timer functions. however, use the watchdog timer by selecting either the watchdog time r function or interval timer function.
user?s manual u14800ej2v0ud 25 chapter 2 general ( pd789316 subseries) 2.1 features main system clock: rc oscillation minimum instruction execution ti me can be changed from high-speed (0.5 s: @ 4.0 mhz operation with main system clock) to ultra-low-speed (122 s: @ 32.768 khz operation with subsystem clock) rom and ram capacities item data memory part number program memory (rom) internal high-speed ram lcd display ram pd789314 mask rom 8 kb pd789316 16 kb pd78f9316 flash memory 16 kb 512 bytes 24 4 bits i/o ports: 23 serial interface: 2 channels switchable between 3-wire serial i/o mode and uart mode: 1 channel 3-wire serial i/o mode: 1 channel timer: 5 channels 16-bit timer: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel lcd controller/driver segment signals: 24, common signals: 4 vectored interrupt sources: 15 power supply voltage: v dd = 1.8 to 5.5 v operating ambient temperature: t a = ?40 to +85 c 2.2 applications remote controllers, healthcare equipment, etc.
chapter 2 general ( pd789316 subseries) user?s manual u14800ej2v0ud 26 2.3 ordering information part number package internal rom pd789314gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom pd789314gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom pd789316gc- -ab8 64-pin plastic qfp (14 14 mm) mask rom pd789316gk- -9et 64-pin plastic tqfp (12 12 mm) mask rom pd78f9316gc-ab8 64-pin plastic qfp (14 14 mm) flash memory pd78f9316gk-9et 64-pin plastic tqfp (12 12 mm) flash memory remark indicates rom code suffix.
chapter 2 general ( pd789316 subseries) user?s manual u14800ej2v0ud 27 2.4 pin configuration (top view) 64-pin plastic qfp (14 14 mm) 64-pin plastic tqfp (fine pitch) (12 12 mm) pd789314gc- -ab8 pd789314gk- -9et pd789316gc- -ab8 pd789316gk- -9et pd78f9316gc-ab8 pd78f9316gk-9et 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p50 p51 p52 p53 ic (v pp ) xt1 xt2 v dd v ss x1 x2 reset p00/kr0 p01/kr1 p02/kr2 p03/kr3 32 caph capl v lc0 v lc1 v lc2 com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 p20/sck10 p21/so10 p22/si10 p23/sck20/asck20 p24/so20/txd20 p25/si20/rxd20 p26/to20 p30/intp0/cpt20 p31/intp1/to30/tmi40 p32/intp2/to40 p33/intp3 p10 p11 p12 p13 s23 caution connect the ic (internally connected) pin directly to v ss . remark the parenthesized values apply to pd78f9316.
chapter 2 general ( pd789316 subseries) user?s manual u14800ej2v0ud 28 asck20: asynchronous serial input rxd20: receive data caph, capl: lcd power supply capacitance control s0 to s23: segment output cl1, cl2: rc oscillator sck10, sck20: serial clock com0 to com3: common output si10, si20: serial input cpt20: capture trigger input so10, so20: serial output ic: internally connected tmi40: timer input intp0 to intp3: external interrupt input to20, to30, to40: timer output kr0 to kr3: key return txd20: transmit data p00 to p03: port 0 v dd : power supply p10 to p13: port 1 v lc0 to v lc2 : lcd power supply p20 to p26: port 2 v pp : programming power supply p30 to p33: port 3 v ss : ground p50 to p53: port 5 xt1, xt2: crystal oscillator reset: reset
chapter 2 general ( pd789316 subseries) user?s manual u14800ej2v0ud 29 2.5 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 52-pin sio + resistance division method lcd (24 4) 8-bit a/d + internal voltage boosting method lcd (23 4) pd789327 lcd drive 80-pin 80-pin pd789436 pd789446 pd789426 pd789456 pd789417a pd789407a pd789316 pd789467 pd789306 pd789426 with 10-bit a/d pd789860 with enhanced timer function, sio, and expanded rom and ram pd789446 with 10-bit a/d sio + 8-bit a/d + resistance division method lcd (28 4) sio + 8-bit a/d + internal voltage boosting method lcd (15 4) pd789407a with 10-bit a/d sio + 8-bit a/d + internal voltage boosting method lcd (5 4) rc oscillation version of pd789306 sio + internal voltage boosting method lcd (24 4) 64-pin 64-pin 52-pin 64-pin 64-pin 64-pin sio + 10-bit a/d + internal voltage boosting method lcd (28 4) 80-pin sio + 8-bit a/d + resistance division method lcd (28 4) 80-pin pd789478 pd789488 64-pin products under development products in mass production small-scale package, general-purpose applications 78k/0s series 28-pin pd789014 with enhanced timer function and expanded rom and ram on-chip uart and capable of low-voltage (1.8 v) operation pd789074 with subsystem clock added inverter control 44-pin pd789842 on-chip inverter controller and uart pd789146 pd789156 44-pin small-scale package, general-purpose applications and a/d function 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 30-pin 30-pin pd789104a pd789114a pd789167 with 10-bit a/d pd789104a with enhanced timer function pd789124a with 10-bit a/d rc oscillation version of pd789104a pd789104a with 10-bit a/d pd789026 with 8-bit a/d and multiplier added pd789104a with eeprom added pd789146 with 10-bit a/d pd789177y pd789167y y subseries supports smb. usb 88-pin pd789830 pd789835 144-pin uart + dot lcd (40 16) uart + 8-bit a/d + dot lcd (total display outputs: 96) 42-/44-pin 44-pin 30-pin 20-pin 20-pin pd789026 with enhanced timer function rc oscillation version of pd789052 vfd drive 52-pin 64-pin pd789871 on-chip vfd controller (total display outputs: 25) meter control pd789881 uart + resistance division method lcd (26 4) 30-pin pd789074 with enhanced timer function and expanded rom and ram 44-pin pd789800 for pc keyboard. on-chip usb function keyless entry 20-pin 20-pin 30-pin on-chip poc and key return circuit rc oscillation version of pd789860 on-chip bus controller 30-pin 44-pin pd789850a on-chip can controller pd789074 pd789088 pd789062 pd789014 pd789046 pd789026 pd789052 pd789860 pd789861 pd789862 pd789852 pd789860 without eeprom, poc, and lvi pd789850a with enhanced timer, a/d, etc. remark vfd (vacuum fluorescent display) is referred to as fip (fluorescent indicator panel) in some documents, but the functions of the two are the same.
chapter 2 general ( pd789316 subseries) user?s manual u14800ej2v0ud 30 the major functional differences am ong the subseries are listed below. series for general-purpose applications and lcd drive timer v dd function subseries rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min.value remarks pd789046 16 k 1 ch pd789026 4 k to 16 k 1 ch 34 pd789088 16 k to 32 k 3 ch pd789074 2 k to 8 k 1 ch 1 ch 24 pd789014 2 k to 4 k 2 ch ? ? 1 ch ? ? 1 ch (uart: 1 ch) 22 1.8 v ? pd789062 4 k ? 14 rc-oscillation version small- scale package, general- purpose applica- tions pd789052 ? pd789177 ? 8 ch pd789167 16 k to 24 k 3 ch 1 ch 8 ch ? 31 ? pd789156 ? 4 ch pd789146 8 k to 16 k 4 ch ? on-chip eeprom pd789134a ? 4 ch pd789124a 4 ch ? rc-oscillation version pd789114a ? 4 ch small- scale package, general- purpose applica- tions + a/d converter pd789104a 2 k to 8 k 1 ch 1 ch ? 1 ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? pd789835 24 k to 60 k 6 ch ? 3 ch 37 1.8 v note pd789830 24 k 1 ch ? 1 ch (uart: 1 ch) 30 2.7 v dot lcd supported pd789488 32 k to 48 k ? 8 ch pd789478 24 k to 48 k 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 k to 24 k 3 ch 1 ch 1 ch 1 ch 7 ch ? 1 ch (uart: 1 ch) 43 1.8 v ? pd789456 ? 6 ch pd789446 6 ch ? 30 pd789436 ? 6 ch pd789426 12 k to 16 k 6 ch 40 pd789316 rc-oscillation version pd789306 8 k to 16 k ? 2 ch (uart: 1 ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 k to 24 k 2 ch ? ? ? 1 ch 21 ? note flash memory version: 3.0 v
chapter 2 general ( pd789316 subseries) user?s manual u14800ej2v0ud 31 series for assp timer v dd function subseries rom capacity (bytes) 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min.value remarks usb pd789800 8 k 2 ch ? ? 1 ch ? ? 2 ch (usb: 1 ch) 31 4.0 v ? inverter control pd789842 8 k to 16 k 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? pd789852 24 k to 32k 3 ch ? 8 ch 3 ch (uart: 2 ch) 31 on-chip bus controller pd789850a 16 k 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1 ch) 18 4.0 v ? pd789861 1.8 v rc-oscillation version, on-chip eeprom pd789860 4 k 2 ch ? ? 1 ch ? ? ? 14 keyless entry pd789862 16 k 1 ch 2 ch 1 ch (uart: 1 ch) 22 on-chip eeprom vfd drive pd789871 4 k to 8 k 3 ch ? 1 ch 1 ch ? ? 1 ch 33 2.7 v ? meter control pd789881 16 k 2 ch 1 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 28 2.7 v note 2 ? notes 1. 10-bit timer: 1 channel 2. flash memory version: 3.0 v
chapter 2 general ( pd789316 subseries) user?s manual u14800ej2v0ud 32 2.6 block diagram v dd v ss ic (v pp ) 78k/0s cpu core rom (flash memory) to30/tmi40 /intp1/p31 8-bit timer 30 p00 to p03 port 0 p10 to p13 port 1 p20 to p26 port 2 p30 to p33 port 3 p50 to p53 port 5 tmi40/to30 /intp1/p31 to20/p26 16-bit timer 20 watch timer watchdog timer serial interface 20 sck20/asck20/p23 si20/rxd20/p25 so20/txd20/p24 s0 to s23 com0 to com3 ram ram space for lcd data 8-bit timer/event counter 40 cascaded 16-bit tmer/ event counter to40/intp2/p32 cpt20/intp0 /p30 serial interface 10 sck10/p20 si10/p22 so10/p21 v lc0 to v lc2 caph capl lcd controller driver system control reset cl1 cl2 xt1 xt2 interrupt control intp0/cpt20/ p30 intp1/to30/ tmi40/p31 intp2/to40/ p32 intp3/p33 kr0/p00 to kr3/p03 remarks 1. the internal rom capacity varies depending on the product. 2. the parenthesized values apply to pd78f9316.
chapter 2 general ( pd789316 subseries) user?s manual u14800ej2v0ud 33 2.7 overview of functions part number item pd789314 pd789316 pd78f9316 internal memory rom mask rom flash memory 8 kb 16 kb 16 kb high-speed ram 512 bytes lcd display ram 24 4 bits system clock rc oscillation minimum instruction execution time 0.5 s/2.0 s (@ 4.0 mhz operation with main system clock) 122 s (@ 32.768 khz operation with subsystem clock) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulations (such as set, reset, and test) multiplier 8 bits 8 bits = 16 bits i/o ports total: 23 cmos i/o: 19 n-ch open-drain: 4 serial interfaces switchable between 3-wi re serial i/o mode and uart mode: 1 channel 3-wire serial i/o mode: 1 channel timers 16-bit timer: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer outputs 3 lcd controller/driver segment signal outputs: 24 max. common signal outputs: 4 max. maskable internal: 9, external: 5 vectored interrupt sources non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to + 85c package 64-pin plastic qfp (14 14 mm) 64-pin plastic tqfp (12 12 mm)
chapter 2 general ( pd789316 subseries) 34 user?s manual u14800ej2v0ud an outline of the timer is shown below. 16-bit timer 20 8?bit timer 30 8-bit timer/event counter 40 watch timer watchdog timer interval timer ? 1 channel 1 channel 1 channel note 1 1 channel note 2 operation mode external event counter ? ? 1 channel ? ? timer outputs 1 1 1 ? ? square-wave outputs ? 1 1 ? ? capture 1 input ? ? ? ? function interrupt sources 1 1 1 2 2 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has the watchdog timer and interv al timer functions. however, use the watchdog timer by selecting either the watchdog time r function or interval timer function.
user?s manual u14800ej2v0ud 35 chapter 3 pin functions ( pd789306 subseries) 3.1 list of pin functions (1) port pins pin name i/o function after reset alternate function p00 to p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by means of pull-up resi stor option register 0 (pu0) or key return mode register 00 (krm00) in port units. input kr0 to kr3 p10 to p13 i/o port 1. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resi stor option register 0 (pu0) in port units. input ? p20 sck10 p21 so10 p22 si10 p23 sck20/asck20 p24 so20/txd20 p25 si20/rxd20 p26 i/o port 2. 7-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resi stor option register b2 (pub2) in 1-bit units. input to20 p30 intp0/cpt20 p31 intp1/to30/ tmi40 p32 intp2/to40 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resi stor option register b3 (pub3) in 1-bit units. input intp3 p50 to p53 i/o port 5. 4-bit n-ch open-drain i/o port. input/output can be specified in 1-bit units. for a mask rom version, an on-chip pull-up resistor can be specified by the mask option in 1-bit units. input ?
chapter 3 pin functions ( pd789306 subseries) user?s manual u14800ej2v0ud 36 (2) non-port pins pin name i/o function after reset alternate function intp0 p30/cpt20 intp1 p31/to30/tmi40 intp2 p32/to40 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p33 kr0 to kr3 input key return signal detection input p00 to p03 sck10 serial interface 10 se rial clock input/output p20 sck20 i/o serial interface 20 seri al clock input/output input p23/asck20 si10 serial interface 10 serial data input p22 si20 input serial interface 20 serial data input input p25/rxd20 so10 serial interface 10 serial data output p21 so20 output serial interface 20 serial data output input p24/txd20 asck20 input serial clock i nput for asynchronous serial interface input p23/sck20 rxd20 input serial data input for asynch ronous serial interface input p25/si20 txd20 output serial data output for asyn chronous serial interface input p24/so20 to20 output 16-bit timer 20 output input p26 cpt20 input capture edge input input p30/intp0 to30 output timer 30 output input p31/intp1/tmi40 to40 output timer 40 output input p32/intp2 tmi40 input external count clock i nput to timer 40 input p31/intp1/to30 s0 to s23 output lcd controller/driver segment signal output output low level ? com0 to com3 output lcd controller/driver common signal output output low level ? v lc0 to v lc2 ? lcd driving voltage ? ? caph ? ? ? capl ? capacitor connection pin for lcd drive ? ? x1 input ? ? x2 ? connecting crystal resonator for main system clock oscillation ? ? xt1 input ? ? xt2 ? connecting crystal resonator fo r subsystem clock oscillation ? ? reset input system reset input input ? v dd ? positive power supply ? ? v ss ? ground potential ? ? ic ? internally connected. connect directly to v ss . ? ? v pp ? sets flash memory programming mode. applies high voltage when a program is written or verified. ? ?
chapter 3 pin functions ( pd789306 subseries) user?s manual u14800ej2v0ud 37 3.2 description of pin functions 3.2.1 p00 to p03 (port 0) these pins constitute a 4-bit i/o port. in additi on, these pins enable key return signal detection. port 0 can be specified in the follo wing operation modes in 1-bit units. (1) port mode these pins constitute a 4-bit i/o port and can be set in the input or output port m ode in 1-bit units by port mode register 0 (pm0). when used as an input port, use of an on-chip pu ll-up resistor can be specified by pull-up resistor option register 0 (pu0) in port units. (2) control mode in this mode, p00 to p03 function as key return signal detection pins (kr0 to kr3). 3.2.2 p10 to p13 (port 1) these pins constitute a 4-bit i/o port and can be set in t he input or output port mode in 1-bit units by port mode register 1 (pm1). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0) in port units. 3.2.3 p20 to p26 (port 2) these pins constitute a 7-bit i/o port. in addition, t hese pins enable timer output, serial interface data i/o, and clock i/o. port 2 can be specified in the follo wing operation modes in 1-bit units. (1) port mode in this mode, p20 to p26 function as a 7-bit i/o port. port 2 can be set in the i nput or output port mode in 1- bit units by port mode register 2 (pm2). when used as an input port, use of an on- chip pull-up resistor can be specified by pull-up resistor option register b2 (pub2) in 1-bit units. (2) control mode in this mode, p20 to p26 function as the ti mer output, serial interface data i/o, and clock i/o. (a) to20 this is the timer output pin of 16-bit timer 20. (b) si10, si20, so10, so20 these are the serial data i/o pins of the serial interface. (c) sck10, sck20 these are the serial clock i/o pi ns of the serial interface. (d) rxd20, txd20 these are the serial data i/o pins of the asynchronous serial interface. (e) asck20 this is the serial clock input pin of the asynchronous serial interface.
chapter 3 pin functions ( pd789306 subseries) user?s manual u14800ej2v0ud 38 caution when using p20 to p26 as serial interface pins, the i/o mode and out put latch must be set according to the functions to be used. for the de tails of the setting, refer to table 13-2 settings of serial interface 10 operating mode and tabl e 14-2 settings of serial interface 20 operating mode. 3.2.4 p30 to p33 (port 3) these pins constitute a 4-bit i/o port. in addition, they also function as timer i/o and external interrupt input. port 3 can be specified in the fo llowing operation mode in 1-bit units. (1) port mode in this mode, port 3 functions as a 4-bit i/o port. port 3 can be set in the input or output port mode in 1-bit units by port mode register 3 (pm3). when used as an input port, use of an on-ch ip pull-up resistor can be specified by pull-up resistor option r egister b3 (pub3) in 1-bit units. (2) control mode in this mode, the pins function as timer i/o and external interrupt input. (a) tmi40 this is the external clock input pin to timer 40. (b) to30, to40 these are the timer output pins of timer 30 and timer 40 (c) intp0 to intp3 these are external interrupt input pins for whic h valid edges (rising edge, falling edge, or both rising and falling edges) can be specified. 3.2.5 p50 to p53 (port 5) these pins function as a 4-bit n-ch open-drain i/o port. port 5 can be set in the input or output port mode in 1-bit units by port mode register 5 (pm5). in the mask rom vers ion, use of an on-chip pull-up resistor can be specified by a mask option. 3.2.6 s0 to s23 these pins are segment signal output pins for the lcd controller/driver. 3.2.7 com0 to com3 these pins are common signal output pi ns for the lcd controller/driver. 3.2.8 v lc0 to v lc2 these pins are power supply vo ltage pins to drive the lcd. 3.2.9 caph, capl these pins are capacitor connec tion pins to drive the lcd.
chapter 3 pin functions ( pd789306 subseries) user?s manual u14800ej2v0ud 39 3.2.10 reset this pin inputs an active-low system reset signal. 3.2.11 x1, x2 these pins are used to connect a crystal re sonator for main system clock oscillation. to supply an external clock, input the clo ck to x1 and input the inverted signal to x2. 3.2.12 xt1, xt2 these pins are used to connect a crystal re sonator for subsystem clock oscillation. to supply an external clock, input the clock to xt1 and input the inverted signal to xt2. 3.2.13 v dd this is the positive power supply pin. 3.2.14 v ss this is the ground pin. 3.2.15 v pp ( pd78f9306 only) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. handle the pins in either of the following ways. ? independently connect a 10 k ? pull-down resistor. ? switch this pin to be directly connected to the dedicated flash programmer in programming mode or to v ss in normal operation mode using a jumper on the board. if the wiring between the v pp pin and v ss pin is long, or external noise is superimposed on the v pp pin, the user program may not run correctly. 3.2.16 ic (mask rom version only) the ic (internally connected) pin is used to set the pd789304 and pd789306 in the test mode before shipment. in the normal operation mode, directly connect this pin to the v ss pin with as short a wiring length as possible. if a potential difference is gener ated between the ic pin and v ss pin due to a long wiring length, or an external noise superimposed on the ic pin, the user program may not run correctly. ? directly connect the ic pin to the v ss pin. v ss ic keep short
chapter 3 pin functions ( pd789306 subseries) user?s manual u14800ej2v0ud 40 3.3 pin input/output circuits and r ecommended connection of unused pins the input/output circuit type of eac h pin and recommended connection of unused pi ns are shown in table 3-1. for the input/output circuit configurat ion of each type, see figure 3-1. table 3-1. types of pin input/output circuits pin name i/o circuit type i/o recommended connection of unused pins p00/kr0 to p03/kr3 8-a p10 to p13 5-a p20/sck10 p21/so10 p22/si10 p23/sck20/asck20 p24/so20/txd20 p25/si20/rxd20 p26/to20 input: independently connect to v dd or v ss via a resistor. output: leave open. p30/inpt0/cpt20 p31/inpt1/to30/tmi40 p32/inpt2/to40 p33/inpt3 8-a input: independently connect to v ss via a resistor. output: leave open. p50 to p53 (mask rom version) 13-w p50 to p53 ( pd78f9306) 13-v i/o input: independently connect to v ss via a resistor. output: leave this pin open at low-level output after clearing the output latch of the port to 0. s0 to s23 17 com0 to com3 18 output v lc0 to v lc2 ? caph, capl ? ? leave open. xt1 input connect to v ss . xt2 ? ? leave open. reset 2 input ? ic (mask rom version) connect directly to v ss . v pp ( pd78f9306) ? ? independently connect to a 10 k ? pull-down resistor or connect directly to v ss .
chapter 3 pin functions ( pd789306 subseries) user?s manual u14800ej2v0ud 41 figure 3-1. pin input/output circuits type 2 type 13-w schmitt-triggered input with hysteresis characteristics in v ss output data output disable in/out v dd n-ch middle-voltage input buffer input enable pull-up resistor (mask option) type 5-a type 17 pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch v ss p-ch p-ch v lc0 v lc1 n-ch p-ch n-ch v lc2 seg data p-ch out n-ch n-ch type 8-a type 18 pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch v ss com data out p-ch p-ch v lc0 v lc1 n-ch v lc2 p-ch n-ch n-ch p-ch n-ch n-ch p-ch type 13-v v ss output data output disable in/out n-ch middle-voltage input buffer input enable
user?s manual u14800ej2v0ud 42 chapter 4 pin functions ( pd789316 subseries) 4.1 list of pin functions (1) port pins pin name i/o function after reset alternate function p00 to p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by means of pull-up resi stor option register 0 (pu0) or key return mode register 00 (krm00) in port units. input kr0 to kr3 p10 to p13 i/o port 1. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resi stor option register 0 (pu0) in port units. input ? p20 sck10 p21 so10 p22 si10 p23 sck20/asck20 p24 so20/txd20 p25 si20/rxd20 p26 i/o port 2. 7-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resi stor option register b2 (pub2) in 1-bit units. input to20 p30 intp0/cpt20 p31 intp1/to30/ tmi40 p32 intp2/to40 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resi stor option register b3 (pub3). input intp3 p50 to p53 i/o port 5. 4-bit n-ch open-drain i/o port. input/output can be specified in 1-bit units. for a mask rom version, an on-chip pull-up resistor can be specified by the mask option in 1-bit units. input ?
chapter 4 pin functions ( pd789316 subseries) user?s manual u14800ej2v0ud 43 (2) non-port pins pin name i/o function after reset alternate function intp0 p30/cpt20 intp1 p31/to30/tmi40 intp2 p32/to40 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p33 kr0 to kr3 input key return signal detection input p00 to p03 sck10 serial interface 10 se rial clock input/output p20 sck20 i/o serial interface 20 seri al clock input/output input p23/asck20 si10 serial interface 10 serial data input p22 si20 input serial interface 20 serial data input input p25/rxd20 so10 serial interface 10 serial data output p21 so20 output serial interface 20 serial data output input p24/txd20 asck20 input serial clock i nput for asynchronous serial interface input p23/sck20 rxd20 input serial data input for asynch ronous serial interface input p25/si20 txd20 output serial data output for asyn chronous serial interface input p24/so20 to20 output 16-bit timer 20 output input p26 cpt20 input capture edge input input p30/intp0 to30 output timer 30 output input p31/intp1/tmi40 to40 output timer 40 output input p32/intp2 tmi40 input external count clock i nput to timer 40 input p31/intp1/to30 s0 to s23 output lcd controller/driver segment signal output output low level ? com0 to com3 output lcd controller/driver common signal output output low level ? v lc0 to v lc2 ? lcd driving voltage ? ? caph ? ? ? capl ? capacitor connection pin for lcd drive ? ? cl1 input ? ? cl2 ? connecting resistor (r) and capacitor (c) for main system clock oscillation ? ? xt1 input ? ? xt2 ? connecting crystal resonator fo r subsystem clock oscillation ? ? reset input system reset input input ? v dd ? positive power supply ? ? v ss ? ground potential ? ? ic ? internally connected. connect directly to v ss . ? ? v pp ? sets flash memory programming mode. applies high voltage when a program is written or verified. ? ?
chapter 4 pin functions ( pd789316 subseries) user?s manual u14800ej2v0ud 44 4.2 description of pin functions 4.2.1 p00 to p03 (port 0) these pins constitute a 4-bit i/o port. in additi on, these pins enable key return signal detection. port 0 can be specified in the follo wing operation modes in 1-bit units. (1) port mode these pins constitute a 4-bit i/o port and can be set in the input or output port m ode in 1-bit units by port mode register 0 (pm0). when used as an input port, use of an on-chip pu ll-up resistor can be specified by pull-up resistor option register 0 (pu0) in port units. (2) control mode in this mode, p00 to p03 function as key return signal detection pins (kr0 to kr3). these pins constitute a 4-bit i/o port and can be set in the input or output port m ode in 1-bit units by port mode register 0 (pm0). when used as an input port, use of an on-chip pull-up re sistor can be specified by pull-up resistor option register 0 (pu0). 4.2.2 p10 to p13 (port 1) these pins constitute a 4-bit i/o port and can be set in t he input or output port mode in 1-bit units by port mode register 1 (pm1). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0) in port units. 4.2.3 p20 to p26 (port 2) these pins constitute a 7-bit i/o port. in addition, t hese pins enable timer output, serial interface data i/o, and clock i/o. port 2 can be specified in the follo wing operation modes in 1-bit units. (1) port mode in this mode, p20 to p26 function as a 7-bit i/o port. port 2 can be set in the i nput or output port mode in 1- bit units by port mode register 2 (pm2). when used as an input port, use of an on- chip pull-up resistor can be specified by pull-up resistor option register b2 (pub2) in 1-bit units. (2) control mode in this mode, p20 to p26 function as the ti mer output, serial interface data i/o, and clock i/o. (a) to20 this is the timer output pin of 16-bit timer 20. (b) si10, si20, so10, so20 these are the serial data i/o pins of the serial interface. (c) sck10, sck20 these are the serial clock i/o pi ns of the serial interface. (d) rxd20, txd20 these are the serial data i/o pins of the asynchronous serial interface.
chapter 4 pin functions ( pd789316 subseries) user?s manual u14800ej2v0ud 45 (e) asck20 this is the serial clock input pin of the asynchronous serial interface. caution when using p20 to p26 as serial interface pins, the i/o mode and out put latch must be set according to the functions to be used. for the de tails of the setting, refer to table 13-2 settings of serial interface 10 operating mode and tabl e 14-2 settings of serial interface 20 operating mode. 4.2.4 p30 to p33 (port 3) these pins constitute a 4-bit i/o port. in addition, they also function as timer i/o and external interrupt input. port 3 can be specified in the follo wing operation modes in 1-bit units. (1) port mode in this mode, port 3 functions as a 4-bit i/o port. port 3 can be set in the input or output port mode in 1-bit units by port mode register 3 (pm3). when used as an input port, use of an on-ch ip pull-up resistor can be specified by pull-up resistor option r egister b3 (pub3) in 1-bit units. (2) control mode in this mode, the pins function as timer i/o and external interrupt input. (a) tmi40 this is the external clock input pin to timer 40. (b) to30, to40 these are the timer output pins of timer 30 and timer 40 (c) cpt20 this is the capture edge input pin for 16-bit timer 20. (d) intp0 to intp3 these are external interrupt input pins for whic h valid edges (rising edge, falling edge, or both rising and falling edges) can be specified. 4.2.5 p50 to p53 (port 5) these pins function as a 4-bit n-ch open-drain i/o port. port 5 can be set in the input or output port mode in 1-bit units by port mode register 5 (pm5). in the mask rom vers ion, use of an on-chip pull-up resistor can be specified by a mask option. 4.2.6 s0 to s23 these pins are segment signal output pins for the lcd controller/driver. 4.2.7 com0 to com3 these pins are common signal output pi ns for the lcd controller/driver. 4.2.8 v lc0 to v lc2 these pins are power supply vo ltage pins to drive the lcd.
chapter 4 pin functions ( pd789316 subseries) user?s manual u14800ej2v0ud 46 4.2.9 caph, capl these pins are capacitor connec tion pins to drive the lcd. 4.2.10 reset this pin inputs an active-low system reset signal. 4.2.11 cl1, cl2 these pins are used to connect a resistor (r) and capacitor (c) for main system clock oscillation. to supply an external clock, input the clock to cl1 and input the inverted signal to cl2. 4.2.12 xt1, xt2 these pins are used to connect a crystal re sonator for subsystem clock oscillation. to supply an external clock, input the clock to xt1 and input the inverted signal to xt2. 4.2.13 v dd this is the positive power supply pin. 4.2.14 v ss this is the ground pin. 4.2.15 v pp ( pd78f9316 only) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. handle the pins in either of the following ways. ? independently connect a 10 k ? pull-down resistor. ? switch this pin to be directly connected to the dedicated flash programmer in programming mode or to v ss in normal operation mode using a jumper on the board. if the wiring between the v pp pin and v ss pin is long, or external noise is superimposed on the v pp pin, the user program may not run correctly.
chapter 4 pin functions ( pd789316 subseries) user?s manual u14800ej2v0ud 47 4.2.16 ic (mask rom version only) the ic (internally connected) pin is used to set the pd789314 and pd789316 in the test mode before shipment. in the normal operation mode, directly connect this pin to the v ss pin with as short a wiring length as possible. if a potential difference is gener ated between the ic pin and v ss pin due to a long wiring length, or an external noise superimposed on the ic pin, the user program may not run correctly. ? directly connect the ic pin to the v ss pin. v ss ic keep short
chapter 4 pin functions ( pd789316 subseries) user?s manual u14800ej2v0ud 48 4.3 pin input/output circuits and r ecommended connection of unused pins the input/output circuit type of eac h pin and recommended connection of unused pi ns are shown in table 4-1. for the input/output circuit configurat ion of each type, see figure 4-1. table 4-1. types of pin input/output circuits pin name i/o circuit type i/o recommended connection of unused pins p00/kr0 to p03/kr3 8-a p10 to p13 5-a p20/sck10 p21/so10 p22/si10 p23/sck20/asck20 p24/so20/txd20 p25/si20/rxd20 p26/to20 input: independently connect to v dd or v ss via a resistor. output: leave open. p30/intp0/cpt20 p31/intp1/to30/tmi40 p32/intp2/to40 p33/intp3 8-a input: independently connect to v ss via a resistor. output: leave open. p50 to p53 (mask rom version) 13-w p50 to p53 ( pd78f9316) 13-v i/o input: independently connect to v ss via a resistor. output: leave this pin open at low-level output after clearing the output latch of the port to 0. s0 to s23 17 com0 to com3 18 output v lc0 to v lc2 ? caph, capl ? ? leave open. xt1 input connect to v ss . xt2 ? ? leave open. reset 2 input ? ic (mask rom version) connect directly to v ss . v pp ( pd78f9316) ? ? independently connect to a 10 k ? pull-down resistor or connect directly to v ss .
chapter 4 pin functions ( pd789316 subseries) user?s manual u14800ej2v0ud 49 figure 4-1. pin input/output circuits type 2 type 13-w schmitt-triggered input with hysteresis characteristics in v ss output data output disable in/out v dd n-ch middle-voltage input buffer input enable pull-up resistor (mask option) type 5-a type 17 pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch v ss p-ch p-ch v lc0 v lc1 n-ch p-ch n-ch v lc2 seg data p-ch out n-ch n-ch type 8-a type 18 pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch v ss com data out p-ch p-ch v lc0 v lc1 n-ch v lc2 p-ch n-ch n-ch p-ch n-ch n-ch p-ch type 13-v v ss output data output disable in/out n-ch middle-voltage input buffer input enable
user?s manual u14800ej2v0ud 50 chapter 5 cpu architecture 5.1 memory space the pd789306 and pd789316 subseries can access 64 kb of memory space. figures 5-1 through 5-3 show the memory maps. figure 5-1. memory map ( pd789304, 789314) special function registers 256 8 bits internal high-speed ram 512 8 bits lcd display ram 24 4 bits reserved reserved internal rom 8192 8 bits ffffh ff00h feffh fd00h fcffh fa00h f9ffh 0000h program memory space data memory space 1fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area fa18h fa17h 2000h 1fffh
chapter 5 cpu architecture user?s manual u14800ej2v0ud 51 figure 5-2. memory map ( pd789306, 789316) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa18h fa17h 4000h 3fffh
chapter 5 cpu architecture user?s manual u14800ej2v0ud 52 figure 5-3. memory map ( pd78f9306, 78f9316) special function registers 256 8 bits internal high-speed ram 512 8 bits internal flash memory 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0022h 0021h vector table area lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa18h fa17h 4000h 3fffh
chapter 5 cpu architecture user?s manual u14800ej2v0ud 53 5.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the pd789306 and pd789316 subseries provide internal rom (or fl ash memory) with the following capacity for each product. table 5-1. internal rom capacity part number internal rom structure capacity pd789304, 789314 8192 8 bits pd789306, 789316 mask rom 16384 8 bits pd78f9306, 78f9316 flash memory 16384 8 bits the following areas are allocated to t he internal program memory space. (1) vector table area the 34-byte area of addresses 0000h to 0021h is reserved as a vector table area. this area stores program start addresses to be used when branching by the reset input or an interrupt request generation. of a 16- bit program address, the lower 8 bi ts are stored in an even address, and the higher 8 bits are stored in an odd address. table 5-2. vector table (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh. vector table address interrupt request vector table address interrupt request 0000h reset input 0012h intst20 0004h intwdt 0014h intwti 0006h intp0 0016h inttm20 0008h intp1 0018h inttm30 000ah intp2 001ah inttm40 000ch intp3 001eh intwt 000eh intsr20/intcsi20 0020h intkr00 0010h intcsi10
chapter 5 cpu architecture user?s manual u14800ej2v0ud 54 5.1.2 internal data memory (internal high-speed ram) space the pd789306 and pd789316 subseries products inco rporate the following ram. (1) internal high-speed ram internal high-speed ram is incorporat ed in the area between fd00h and feffh. the internal high-speed ram is also used as a stack. (2) lcd display ram lcd display ram is allocated in the area between fa00h and fa17h. the lcd display ram can also be used as ordinary ram. 5.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allo cated in the area between ff00h to ffffh (see table 5-3 ).
chapter 5 cpu architecture user?s manual u14800ej2v0ud 55 5.1.4 data memory addressing the pd789306 and pd789316 subseries are provided with a variet y of addressing modes to make memory manipulation as efficient as possibl e. at the addresses corresponding to data memory area (fd00h to ffffh) especially, specific addressing modes that correspond to the particular function an area, such as the special function registers are available. figures 5-4 thr ough 5-6 show the data memory addressing modes. figure 5-4. data memory addressing ( pd789304, 789314) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 8192 8 bits ffffh 0000h direct adressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh 2000h 1fffh fa18h fa17h
chapter 5 cpu architecture user?s manual u14800ej2v0ud 56 figure 5-5. data memory addressing ( pd789306, 789316) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa18h fa17h
chapter 5 cpu architecture user?s manual u14800ej2v0ud 57 figure 5-6. data memory addressing ( pd78f9306, 78f9316) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal flash memory 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa18h fa17h
chapter 5 cpu architecture user?s manual u14800ej2v0ud 58 5.2 processor registers the pd789306 and pd789316 subseries provide the followi ng on-chip processor registers. 5.2.1 control registers the control registers contai n special functions to cont rol the program sequence status es and stack memory. the program counter, program status word, and stack pointer are c ontrol registers. (1) program counter (pc) the program counter is a 16-bit r egister that holds the address info rmation of the next program to be executed. in normal operation, the pc is automat ically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is execut ed, immediate data or r egister contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 5-7. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. the program status word contents are automatica lly stacked upon interrupt request generation or push psw instruction execution and ar e automatically restored upon exec ution of the reti and pop psw instructions. reset input sets psw to 02h. figure 5-8. program status word configuration 70 ie z 0 ac 0 0 1 cy psw
chapter 5 cpu architecture user?s manual u14800ej2v0ud 59 (a) interrupt enable flag (ie) this flag controls interrupt request a cknowledgement operati ons of the cpu. when 0, ie is set to the interrupt disable stat us (di), and interrupt reques ts other than non-maskable interrupt are all disabled. when 1, ie is set to the interrupt enable status (ei). interrupt request acknowledgement enable is controlled with an interrupt mask flag for various interrupt sources. ie is reset (0) upon di instruction execution or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0) in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (d) carry flag (cy) this flag stores overflow and underfl ow upon add/subtract instruction exec ution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
chapter 5 cpu architecture user?s manual u14800ej2v0ud 60 (3) stack pointer (sp) this is a 16-bit register to hold t he start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 5-9. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. each stack operation saves/restores dat a as shown in figures 5-10 and 5-11. caution since reset input makes the sp contents unde fined, be sure to initialize the sp before instruction execution. figure 5-10. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 higher register pairs figure 5-11. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs ret instruction pop rp instruction sp pc7 to pc0 higher register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3
chapter 5 cpu architecture user?s manual u14800ej2v0ud 61 5.2.2 general-purpose registers the general-purpose register s consist of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit r egister, or two 8-bit registers in pairs can be used as a 16-bit register (ax, bc, de, and hl). general-purpose registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, or hl) or absolute names (r0 to r7 and rp0 to rp3). figure 5-12. general-purpo se register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) function names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h
chapter 5 cpu architecture user?s manual u14800ej2v0ud 62 5.2.3 special function registers (sfrs) unlike a general-purpose register, each special function register has a special function. the special function registers are allocat ed in the 256-byte area of ff00h to ffffh. special function registers can be m anipulated, like general-purpos e registers, by operat ion, transfer, and bit manipulation instructions. the manipul atable bit units (1, 8, and 16) differ depending on the special function register type. the manipulatable bits can be specified as follows. 1-bit manipulation describes a symbol reserved by the assembler for the 1-bit manipulation instructi on operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation describes a symbol reserved by the assembler for t he 8-bit manipulation instru ction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation describes a symbol reserved by the assembler fo r the 16-bit manipulation instruction operand. when addressing an address, describe an even address. table 5-3 lists the special function r egisters. the meanings of the symbol s in this table are as follows: symbol indicates the addresses of the im plemented special function registers. the symbols are reserved for the assembler and are defined as an sfr vari able by the #pragma sfr directive for the c compiler. therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. r/w indicates whether the special function r egister in question can be read or written. r/w: read/write r: read only w: write only bit manipulation unit indicates the bit units (1, 8, 16) in which the s pecial function register in question can be manipulated. after reset indicates the status of t he special function register w hen the reset signal is input.
chapter 5 cpu architecture user?s manual u14800ej2v0ud 63 table 5-3. special function register list (1/2) bit manipulation unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 ? ff01h port 1 p1 ? ff02h port 2 p2 ? ff03h port 3 p3 ? ff05h port 5 p5 r/w ? 00h ff0ch 8-bit compare register 40 cr40 ? ff0dh 8-bit compare register 30 cr30 cr4 note1 w ? notes 2, 3 undefined ff0eh 8-bit timer counter 40 tm40 ? ff0fh 8-bit timer counter 30 tm30 tm4 note1 r ? notes 2, 3 00h ff10h transmit shift register 20 txs20 w ? ? ffh receive buffer register 20 rxb20 sio20 r ? ? ff11h serial shift register 10 sio10 r/w ? ? undefined ff16h ff17h 16-bit compare register 20 cr20 note 1 w ? ? notes 2, 3 ffffh ff18h ff19h 16-bit timer counter 20 tm20 note 1 ? ? notes 2, 3 0000h ff1ah 16-bit capture register 20 ff1bh tcp20 note 1 r ? ? notes 2, 3 undefined ff20h port mode register 0 pm0 ? ff21h port mode register 1 pm1 ? ff22h port mode register 2 pm2 ? ff23h port mode register 3 pm3 ? ff25h port mode register 5 pm5 ? ffh ff32h pull-up resistor option register b2 pub2 ? ff33h pull-up resistor option register b3 pub3 ? ff42h watchdog timer clock select register wdcs ? ? ff48h 16-bit timer mode control register 20 tmc20 ? ff4ah watch timer mode control register wtm r/w ? 00h ff4ch 8-bit compare register h40 crh40 w ? ? undefined notes 1. name of sfr dedicated for 16-bit access. 2. only in short direct addressing, 16-bit access is possible. 3. these are 16-bit access dedicated r egisters, however, 8-bit access is possible. when performing 8-bit access, access using direct addressing.
chapter 5 cpu architecture user?s manual u14800ej2v0ud 64 table 5-3. special function register list (2/2) bit manipulation unit address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff4dh 8-bit timer mode control register 30 tmc30 ? ff4eh 8-bit timer mode control register 40 tmc40 r/w ? ff4fh carrier generator output control register 40 tca40 w ? ? ff70h asynchronous serial interface mode register 20 asim20 r/w ? ff71h asynchronous serial interf ace status register 20 asis20 r ? ff72h serial operation mode register 20 csim20 ? ff73h baud rate generator control register 20 brgc20 ? ? ff78h serial operation mode register 10 csim10 ? ffb0h lcd display mode register 0 lcdm0 ? ffb2h lcd clock control register 0 lcdc0 ? ffb3h lcd voltage amplification control register 0 lcdva0 ? ffe0h interrupt request flag register 0 if0 ? ffe1h interrupt request flag register 1 if1 ? 00h ffe4h interrupt mask flag register 0 mk0 ? ffe5h interrupt mask flag register 1 mk1 ? ffh ffech external interrupt mode register 0 intm0 ? ? ffedh external interrupt mode register 1 intm1 ? ? fff0h suboscillation mode register sckm ? fff2h subclock control register css ? fff5h key return mode register 00 krm00 ? fff7h pull-up resistor option register 0 pu0 ? fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time select register note osts ? ? 04h fffbh processor clock control register pcc r/w ? 02h note pd789306 subseries only.
chapter 5 cpu architecture user?s manual u14800ej2v0ud 65 5.3 instruction address addressing an instruction address is determined by the program counter (p c) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an in struction to be fetched each time another instruction is ex ecuted. when a branch instruct ion is executed, the branch destination information is set to the pc and branched by the following addressing (f or details of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) ). 5.3.1 relative addressing [function] the value obtained by adding 8-bit immedi ate data (displacement value: jdis p8) of an instruction code to the start address of the following instruction is transfe rred to the program counter (pc) and branched. the displacement value is treated as signed two?s comple ment data (?128 to +127) and bit 7 becomes a sign bit. this means that information is relatively branched to a location between ?128 and +127, from the start address of the next instruction when relative addressing is used. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates all bits 0. ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates all bits 1.
chapter 5 cpu architecture user?s manual u14800ej2v0ud 66 5.3.2 immediate addressing [function] immediate data in the instructi on word is transferred to the pr ogram counter (pc) and branched. this function is carried out when the call !addr 16 or br !addr16 instru ction is executed. call !addr16 and br !addr16 instruct ions can be branched to any location in the memory space. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr.
chapter 5 cpu architecture user?s manual u14800ej2v0ud 67 5.3.3 table indirect addressing [function] table contents (branch desti nation address) of the particular locati on to be addressed by the lower 5-bit immediate data of an instru ction code from bit 1 to bit 5 are trans ferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instructi on is executed. the in struction enables a branch to any location in the memory space by referring to t he addresses stored in the memo ry table at 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4?0 instruction code 5.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word ar e transferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 5 cpu architecture user?s manual u14800ej2v0ud 68 5.4 operand address addressing the following various methods are available to spec ify the register and memory (addressing) which undergo manipulation during inst ruction execution. 5.4.1 direct addressing [function] the memory indicated with imm ediate data in an instruction wo rd is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 0 0 1 0 1001op code 00000000 11111110 00h feh [illustration] 70 op code addr16 (lower) addr16 (higher) memory ? ? ? ? ?
chapter 5 cpu architecture user?s manual u14800ej2v0ud 69 5.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit dat a in an instruction word. the fixed space is the 256-byte space fe20h to ff1fh where the addressing is applied. internal high-speed ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addr essing is applied is a part of the whole sfr area. ports that are frequently accessed in a program and the compare register of the timer/event counter are mapped in this area, and these sf rs can be manipulated with a sma ll number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh i mmediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 1 1 1 10101 10010000 01010000 op code 90h (saddr-offset) 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1.
chapter 5 cpu architecture user?s manual u14800ej2v0ud 70 5.4.3 special function register (sfr) addressing [function] the memory-mapped special function registers (sfrs) are addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 256-byte space ff00h to ffffh. however, the sfrs mapped at ff00h to ff1fh can also be accessed with short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 11100111 00100000 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 5 cpu architecture user?s manual u14800ej2v0ud 71 5.4.4 register addressing [function] in the register addressing mode, general-purpose registers are access ed as operands. the general-purpose register to be accessed is specified by a register specification code or f unctional name in the instruction code. register addressing is carried out when an instruction with the following operand forma t is executed. when an 8-bit register is specified, one of the eight registers is specified wit h 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 0 0 1 0 1 0 00100101 register specification code incw de; when selecting the de register pair for rp instruction code 1 0001000 register specification code
chapter 5 cpu architecture user?s manual u14800ej2v0ud 72 5.4.5 register indirect addressing [function] in the register indirect addressing m ode, memory is manipulated according to the contents of a register pair specified as an operand. the r egister pair to be accessed is specified by the register pair s pecification code in an instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 00101011 [illustration] 15 0 8 d 7 e 0 7 7 0 a de addressed memory contents are transferred. memory address specified with register pair de.
chapter 5 cpu architecture user?s manual u14800ej2v0ud 73 5.4.6 based addressing [function] 8-bit immediate data is added to the cont ents of the base register, that is, t he hl register pair, and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 00101101 00010000 5.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatic ally employed when the push, po p, subroutine call, and return instructions are executed or t he register is saved/restored upon generation of an interrupt request. only the internal high-speed ram area can be addressed using stack addressing. [description example] in the case of push de instruction code 10101010
user?s manual u14800ej2v0ud 74 chapter 6 port functions 6.1 port functions the pd789306 and pd789316 subseries provide the ports shown in figure 6-1, enabling various methods of control. numerous other functions are provi ded that can be used in addition to the digital i/o port functions. for more information on these additional functions, see chapter 3 pin functions ( pd789306 subseries) and chapter 4 pin functions ( pd789316 subseries) . figure 6-1. port types p30 p33 p00 p03 p50 p53 p20 p26 port 3 port 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? port 2 ? ? ? ? ? ? ? ? ? ? ? p10 p13 port 1 port 0 ? ? ? ? ? ? ? ? ? ? ?
chapter 6 port functions user?s manual u14800ej2v0ud 75 table 6-1. port functions pin name i/o function after reset alternate function p00 to p03 i/o port 0. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (pu0) or key return mode register 00 (krm00) in port units. input kr0 to kr3 p10 to p13 i/o port 1. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by pull-up re sistor option register 0 (pu0) in port units. input ? p20 sck10 p21 so10 p22 si10 p23 sck20/asck20 p24 so20/txd20 p25 si20/rxd20 p26 i/o port 2. 7-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b2 (pub2) in 1-bit units. input to20 p30 intp0/cpt20 p31 intp1/to30/tmi40 p32 intp2/to40 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register b3 (pub3) in 1-bit units. input intp3 p50 to p53 i/o port 5. 4-bit n-ch open-drain i/o port. input/output can be specified in 1-bit units. for a mask rom version, an on-chip pull-up resistor can be specified by a mask option in 1 bit units. input ?
chapter 6 port functions user?s manual u14800ej2v0ud 76 6.2 port configuration ports have the following har dware configuration. table 6-2. configuration of port item configuration control registers port mode register (pmm: m = 0 to 3, 5) pull-up resistor option register 0 (pu0) pull-up resistor option register b2, b3 (pub2, pub3) ports total: 23 (cmos i/o: 19, n-ch open-drain i/o: 4) pull-up resistors ? mask rom version total: 23 (software control: 19, mask option control: 4) ? flash memory version total: 19 (software control only)
chapter 6 port functions user?s manual u14800ej2v0ud 77 6.2.1 port 0 this is a 4-bit i/o port with an output latc h. port 0 can be specified in the i nput or output mode in 1-bit units by using the port mode register 0 (pm0). when the p00 to p03 pins are used as i nput port pins, on-chip pull-up resistors can be connected in 4-bit units by using pu ll-up resistor option register 0 (pu0). port 0 is set in the input mode when the reset signal is input. figure 6-2 shows a block diagram of port 0. figure 6-2. block di agram of p00 to p03 wr krm00 v dd p00/kr0 to p03/kr3 wr puo rd wr port w rpm pu00 pm00 to pm03 krm000 p-ch internal bus selector output latch (p00 to p03) alternate function krm00: key return mode register 00 pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 6 port functions user?s manual u14800ej2v0ud 78 6.2.2 port 1 this is a 4-bit i/o port with an output latc h. port 1 can be specified in the i nput or output mode in 1-bit units by using port mode register 1 (pm1). when using the p10 to p13 pins as input por t pins, on-chip pull-up resistors can be connected in 4-bit units by using pull- up resistor option register 0 (pu0). this port is set in the input mode when the reset signal is input. figure 6-3 shows a block diagram of port 1. figure 6-3. block di agram of p10 to p13 wr pu0 rd wr port wr pm pu01 pm10 to pm13 v dd p-ch p10 to p13 internal bus selector output latch (p10 to p13) pu0: pull-up resistor option register 0 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 6 port functions user?s manual u14800ej2v0ud 79 6.2.3 port 2 this is a 7-bit i/o port with an output latc h. port 2 can be specified in the i nput or output mode in 1-bit units by using port mode register 2 (pm2). when using the p20 to p26 pins as input por t pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b2 (pub2). the port is also used as a data i/o and clock i/o to and from the serial interface and for timer output. this port is set in the input mode when the reset signal is input. figures 6-4 to 6-7 show block diagrams of port 2. caution when using the pins of port 2 as the serial interface pin , the i/o or output latch must be set according to the function to be used. for how to set the latches, see table 13-2 settings of serial interface 10 operating mode and figure 14-2 settings of serial interface 20 operating mode. figure 6-4. block diagram of p20 and p23 internal bus v dd p-ch p20/sck10, p23/asck20/ sck20 wr pub2 rd wr port wr pm pub20, pub23 alternate function output latch (p20, p23) pm20, pm23 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 6 port functions user?s manual u14800ej2v0ud 80 figure 6-5. block diagram of p21 and p24 internal bus v dd p-ch p21/so10, p24/so20/txd20 wr pub2 rd wr port wr pm pub21, pub24 output latch (p21, p24) pm21, pm24 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 6 port functions user?s manual u14800ej2v0ud 81 figure 6-6. block diagram of p22 and p25 internal bus v dd p-ch p22/si10, p25/si20/rxd20 wr pub2 rd wr port wr pm pub22, pub25 alternate function output latch (p22, p25) pm22, pm25 selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 6 port functions user?s manual u14800ej2v0ud 82 figure 6-7. block diagram of p26 internal bus v dd p26/to20 wr pub2 rd wr port wr pm pub26 alternate function output latch (p26) pm26 selector p-ch pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 6 port functions user?s manual u14800ej2v0ud 83 6.2.4 port 3 this is a 4-bit i/o port with an output latc h. port 3 can be specified in the i nput or output mode in 1-bit units by using port mode register 3 (pm3). when using the p30 to p33 pins as input por t pins, on-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register b3 (pub3). this port is also used as an external interrupt input, capture input, and timer i/o. this port is set in the input mode when the reset signal is input. figures 6-8 and 6-9 show block diagrams of port 3. figure 6-8. block diagram of p30 and p33 p30/intp0/cpt20, p33/intp3 wr pub2 rd wr port wr pm pub30, pub33 pm30, pm33 v dd p-ch internal bus alternate function selector output latch (p30, p33) pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 6 port functions user?s manual u14800ej2v0ud 84 figure 6-9. block diagram of p31 and p32 p31/intp1/to30/ tmi40, p32/intp2/to40 wr pub2 rd wr port wr pm pub31, pub32 pm31, pm32 v dd p-ch internal bus alternate function selector output latch (p31, p32) alternate function pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 6 port functions user?s manual u14800ej2v0ud 85 6.2.5 port 5 this is a 4-bit n-ch open-drain i/o port wit h an output latch. port 5 can be spec ified in the input or output mode in 1-bit units by using port mode register 5 (pm5). for a mask rom version, use of an on- chip pull-up resistor can be specified by a mask option. this port is set in the input mode when the reset signal is input. figure 6-10 shows a block diagram of port 5. figure 6-10. block di agram of p50 to p53 internal bus selector rd pm50 to pm53 p50 to p53 n-ch wr port output latch (p50 to p53) wr pm v dd mask option resistor mask rom version only. for flash memory version, a pull-up resistor is not incorporated. pm: port mode register rd: port 5 read signal wr: port 5 write signal
chapter 6 port functions user?s manual u14800ej2v0ud 86 6.3 registers controlling port function the ports are controlled by the fo llowing two types of registers. ? port mode registers (pm0 to pm3, pm5) ? pull-up resistor option registers (pu0, pub2, pub3) (1) port mode registers (pm0 to pm3, pm5) these registers are used to set por t input/output in 1-bit units. the port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch according to table 6-3. caution as port 3 has an alternate function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, th e interrupt mask flag should be preset to 1.
chapter 6 port functions user?s manual u14800ej2v0ud 87 figure 6-11. format of port mode register pmmn 0 output mode (output buffer on) input mode (output buffer off) 1 1 1 1 1 1 1 1 1 1 1 1 1 pm03 pm13 pm53 pm02 pm12 pm52 pm01 pm11 pm51 pm00 pm10 pm50 pm0 pm1 pm5 7 symbol address after reset 6543210 r/w ff20h ff21h ff25h ffh ffh ffh r/w r/w r/w 1 1 pm26 1 pm25 1 pm24 1 pm23 pm33 pm22 pm32 pm21 pm31 pm20 pm30 pm2 pm3 ff22h ff23h ffh ffh r/w r/w pmn pin input/output mode selection (m = 0 to 3, 5, n = 0 to 6) table 6-3. port mode register and output latch settings when us ing alternate functions alternate function pin name name i/o pmxx pxx p00 to p03 kr0 to kr3 input 1 x p26 to20 output 0 0 intp0 input 1 x p30 cpt20 input 1 x intp1 input 1 x to30 output 0 0 p31 tmi40 input 1 x intp2 input 1 x p32 to40 output 0 0 p33 intp3 input 1 x caution when port 2 is used as a serial interface pin, the i/o latch or output latch must be set according to its function. for the setting method, see tabl e 13-2 settings of serial interface 10 operating mode and table 14-2 settings of se rial interface 20 operating mode. remark x: don?t care pmxx: port mode register pxx: port output latch
chapter 6 port functions user?s manual u14800ej2v0ud 88 (2) pull-up resistor option register 0 (pu0) pull-up resistor option register 0 (p u0) sets whether an on-chip pull-up resistor on each port is used or not. on the port specified to use an on-ch ip pull-up resistor by pu0, the pu ll-up resistor can be internally used only for the bits set in the input mode. no on-chip pu ll-up resistors can be used for the bits set in the output mode regardless of the setting of pu0. this also applies to cases when the pins are used for alternate functions. pu0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pu0 to 00h. figure 6-12. format of pull-up resistor option register 0 pm on-chip pull-up resistor selection (m = 0, 1) 000000 pu01 pu00 pu0 address after reset r/w fff7h 00h r/w 765432<1><0> pu0m 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol caution bits 2 to 7 must be set to 0. (3) pull-up resistor option register b2 (pub2) pull-up resistor option register b2 (pub2) sets whether on-chip pull-up resistors on p20 to p26 are used or not. on the port specified to use an on-ch ip pull-up resistor by pub2, the pu ll-up resistor can be internally used only for the bits set in the input mode. no on-chip pu ll-up resistors can be used for the bits set in the output mode regardless of the setting of pub2. this also applies to cases when the pins are used for alternate functions. pub2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pub2 to 00h. figure 6-13. format of pull-up resistor option register b2 p2n on-chip pull-up resistor selection (n = 0 to 6) 0 pub26 pub25 pub24 pub23 pub22 pub21 pub20 pub2 address after reset r/w ff32h 00h r/w 7 <6> <5> <4> <3> <2> <1> <0> pub2n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol caution bit 7 must be set to 0.
chapter 6 port functions user?s manual u14800ej2v0ud 89 (4) pull-up resistor option register b3 (pub3) pull-up resistor option register b3 (pub3) sets whether on-chip pull-up resistors on p30 to p33 are used or not. on the port specified to use an on-ch ip pull-up resistor by pub3, the pu ll-up resistor can be internally used only for the bits set in the input mode. no on-chip pu ll-up resistors can be used for the bits set in the output mode regardless of the setting of pub3. this also applies to cases when the pins are used for alternate functions. pub3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pub3 to 00h. figure 6-14. format of pull-up resistor option register b3 p3n on-chip pull-up resistor selection (n = 0 to 3) 00 0 0 pub33 pub32 pub31 pub30 pub3 address after reset r/w ff33h 00h r/w 7 6 5 4 <3> <2> <1> <0> pub3n 0 1 on-chip pull-up resistor not used on-chip pull-up resistor used symbol caution bits 4 to 7 must be set to 0.
chapter 6 port functions user?s manual u14800ej2v0ud 90 6.4 port function operation the operation of a port differs depending on whether the port is set in the input or output m ode, as described below. 6.4.1 writing to i/o port (1) in output mode a value can be written to the output la tch of a port by using a transfer inst ruction. the cont ents of the output latch can be output from the pins of the port. data once written to the output latch is retai ned until new data is writt en to the output latch. (2) in input mode a value can be written to the output latc h by using a transfer instruction. however, the status of the port pin is not changed because the out put buffer is off. data once written to the output latch is retai ned until new data is writt en to the output latch. caution a 1-bit memory manipulation instructi on is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 6.4.2 reading from i/o port (1) in output mode the status of an output latc h can be read by using a transfer instructi on. the contents of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 6.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed with the contents of the output latch. the re sult of the operation is written to the output latch. the contents of the out put latch are output from the port pins. data once written to the output latch is retai ned until new data is writt en to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instructi on is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined.
user?s manual u14800ej2v0ud 91 chapter 7 clock generator ( pd789306 subseries) 7.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are used. ? main system clock (cer amic/crystal) oscillator this circuit oscillates at 1.0 to 5.0 mhz. oscillati on can be stopped by executing the stop instruction or setting the processor clock control register (pcc). ? subsystem clock oscillator this circuit oscillates at 32.768 khz. oscillation can be stopped by the suboscilla tion mode register (sckm). 7.2 clock generator configuration the clock generator includes the following hardware. table 7-1. configuration of clock generator item configuration control registers processor cl ock control register (pcc) suboscillation mode register (sckm) subclock control register (css) oscillators main system clock oscillator subsystem clock oscillator
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 92 figure 7-1. block diag ram of clock generator f xt f x prescaler f x 2 2 f xt 2 1/2 prescaler watch timer lcd controller /driver clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller selector stop mcc pcc1 cls css0 internal bus suboscillation mode register (sckm) frc scc internal bus subclock control register (css) processor clock control register (pcc) subsystem clock oscillator x1 x2 xt1 xt2 main system clock oscillator
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 93 7.3 registers controlling clock generator the clock generator is controll ed by the following registers. ? processor clock control register (pcc) ? suboscillation mode register (sckm) ? subclock control register (css) (1) processor clock control register (pcc) pcc sets cpu clock selection and the division ratio. pcc is set with a 1-bit or 8-bit me mory manipulation instruction. reset input sets pcc to 02h. figure 7-2. format of processo r clock control register control of main system clock oscillator operation mcc00000 pcc1 0 pcc symbol address after reset r/w fffbh 02h r/w <7>6543210 mcc 0 1 operation enabled operation disabled 0.4 s 1.6 s 122 s selection of cpu clock (f cpu ) note css0 0 0 1 1 pcc1 0 1 0 1 f x f x /2 2 f xt /2 minimum instruction execution time: 2/f cpu f x = 5.0 mhz or f xt = 32.768 khz operation note the cpu clock is selected according to a combinati on of the pcc1 flag in the processor clock control register (pcc) and the css0 flag in the s ubclock control register (css) (refer to 7.3 (3) subclock control register (css) ). cautions 1. bits 0 and 2 to 6 must be set to 0. 2. the mcc can be set only when the subsyst em clock has been select ed as the cpu clock. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 94 (2) suboscillation mode register (sckm) sckm selects a feedback resistor for the subsystem clock, and controls the o scillation of the clock. sckm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sckm to 00h. figure 7-3. format of subo scillation mode register feedback resistor selection note 000000frcscc sckm symbol address after reset r/w fff0h 00h r/w 76543210 frc 0 1 on-chip feedback resistor used on-chip feedback resistor not used control of subsystem clock oscillator operation scc 0 1 operation enabled operation disabled note the feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the supply voltage. only when the subclock is not used, t he power consumption in stop mode can be further reduced by setting frc = 1. caution bits 2 to 7 must be set to 0.
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 95 (3) subclock control register (css) css specifies whether the main system or subsystem clock oscillator is to be selected. it also specifies the cpu clock operation status. css is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears css to 00h. figure 7-4. format of subclock control register cpu clock operation status 0 0 cls css0 0000 css address after reset r/w fff2h 00h r/w 76543210 cls 0 1 operation based on the output of the divided main system clock operation based on the subsystem clock selection of the main system or subsystem clock oscillator css0 0 1 divided output from the main system clock oscillator output from the subsystem clock oscillator symbol note note bit 5 is read only. caution bits 0 to 3, 6, and 7 must be set to 0.
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 96 7.4 system clock oscillators 7.4.1 main system clock oscillator the main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the x1 pin, and input the inverted signal to the x2 pin. figure 7-5 shows the external circuit of the main system clock oscillator. figure 7-5. external circuit of main system clock oscillator (a) crystal or ceramic osc illation (b) external clock crystal or ceramic resonator v ss x2 x1 external clock x1 x2 caution when using the main system or subsystem cl ock oscillator, wire as follo ws in the area enclosed by the broken lines in figures 7-5 and 7-6 to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator.
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 97 7.4.2 subsystem clock oscillator the subsystem clock oscillator is oscillated by the cr ystal resonator (32.768 khz t yp.) connected across the xt1 and xt2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the xt1 pin, and input the inverted signal to the xt2 pin. figure 7-6 shows the external circuit of the subsystem clock oscillator. figure 7-6. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 v ss xt1 32.768 khz crystal resonator external clock xt1 xt2 caution when using the main system or subsystem cl ock oscillator, wire as follo ws in the area enclosed by the broken lines in figures 7-5 and 7-6 to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. when using the subsystem clo ck, particular care is require d because the s ubsystem clock oscillator is designed as a low-amplitude ci rcuit for reducing cu rrent consumption.
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 98 7.4.3 examples of incorrect resonator connection figure 7-7 shows examples of incorrect resonator connection. figure 7-7. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line v ss x1 x2 v ss x1 x2 portn (n = 0 to 3, 5) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 high current v ss x1 ab c p mn v dd high current x2 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, re spectively, and connect a resistor to the xt2 in series.
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 99 figure 7-7. examples of incorr ect resonator connection (2/2) (e) signal is fetched (f) parallel and near signal lines of main system clock and subsystem clock v ss x1 x2 v ss x2 xt2 is wired parallel to x1. x1 xt2 xt1 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, re spectively, and connect a resistor to the xt2 in series. caution if the x1 wire is in para llel with the xt2 wire, crosstalk noise may occur between the x1 and xt2, resulting in a malfunction. to avoid this, do not lay the x1 and xt2 wires in parallel. 7.4.4 divider circuit the divider circuit divides the output of the main system clock oscillator (f x ) to generate various clocks. 7.4.5 when no subsyst em clock is used if a subsystem clock is not necessary, for example, fo r low-power consumption oper ation or clock operation, handle the xt1 and xt2 pins as follows: xt1: connect to v ss xt2: leave open in this case, however, a small current leaks via the on- chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. to avoid this, set bit 1 (frc) of the suboscilla tion mode register (sckm) so that the on-chip feedback resistor will not be used. also in this case, handle the xt1 and xt2 pins as stated above.
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 100 7.5 clock generator operation the clock generator generates the following clocks and controls the operat ion modes of the cpu, such as the standby mode. ? main system clock f x ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the operation and function of the clock generator is dete rmined by the processor clock control register (pcc), suboscillation mode register (sckm), and subclo ck control register (css), as follows. (a) the low-speed mode (1.6 s: at 5.0 mhz operation) of the ma in system clock is selected when the reset signal is generated (pcc = 02h). while a low leve l is input to the reset pin, oscillation of the main system clock is stopped. (b) three types of minimum instruction execution time (0.4 s and 1.6 s: main system clock (at 5.0 mhz operation), 122 s: subsystem clock (at 32.768 khz operati on)) can be selected by the pcc, sckm, and css settings. (c) two standby modes, stop and halt , can be used with the main system clock selected. in a system where no subsystem clock is used, setting bit 1 (f rc) of the sckm so t hat the on-chip feedback resistor cannot be used reduces curr ent consumption in stop mode. in a system where a subsystem clock is used, setting sckm bit 0 to 1 can c ause the subsystem clock to stop oscillation. (d) css bit 4 (css0) can be used to select the subsyst em clock so that low cu rrent consumption operation is used (122 s: at 32.768 khz operation). (e) with the subsystem clock selected, it is possibl e to cause the main system clock to stop oscillating using bit 7 (mcc) of pcc. the halt mode can be used, but the stop mode cannot. (f) the clock pulse for the peripheral hardware is generated by dividing the fr equency of the main system clock, but the subsystem clock pulse is only suppli ed to the watch timer and lcd controller/driver. the watch timer and lcd controller/driver can ther efore keep running even dur ing standby. the other hardware stops when the main syst em clock stops because it runs based on the main system clock (except for external input clock operations).
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 101 7.6 changing setting of s ystem clock and cpu clock 7.6.1 time required for switching between system clock and cpu clock the cpu clock can be selected by using bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css). actually, the specified clock is not selected immediately after the se tting of pcc has been changed, and the old clock is used for the duration of se veral instructions after that (see table 7-2 ). table 7-2. maximum time re quired for switching cpu clock set value before switching set value after switching css0 pcc1 css0 pcc1 css0 pcc1 css0 pcc1 0 0 0 1 1 x 0 0 4 clocks 2f x /f xt clocks (306 clocks) 1 2 clocks f x /2f xt clocks (76 clocks) 1 x 2 clocks 2 clocks remarks 1. two clocks are the minimum instruction execut ion time of the cpu clock before switching. 2. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 3. x: don?t care
chapter 7 clock generator ( pd789306 subseries) user?s manual u14800ej2v0ud 102 7.6.2 switching between system clock and cpu clock the following figure illustrates how t he cpu clock and system clock switch. figure 7-8. switching between system clock and cpu clock system clock cpu clock interrupt request signal reset v dd f x f x f xt f x low-speed operation high-speed operation subsystem clock operation high-speed operation wait (6.55 ms: at 5.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on pow er application. the effect of resetting is released when the reset pin is later made high, and the main syst em clock starts oscillating. at this time, the oscillation stabilization time (2 15 /f x ) is automatically secured. after that, the cpu starts inst ruction execution at the slow s peed of the main system clock (1.6 s: at 5.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at high speed has elapsed, bit 1 (pcc1) of the processor clock cont rol register (pcc) and bit 4 (css0) of the subclock control register (css) are rewritten so that high-speed operat ion can be selected. <3> a drop of the v dd voltage is detected with an in terrupt request signal. the clock is switched to the subsystem clock (at this moment, the subsystem clo ck must be in the oscillati on stabilization status). <4> a recover of the v dd voltage is detected with an inte rrupt request signal. bit 7 (mcc) of pcc is set to 0, and then the main system clock starts oscillating. after the time required for the oscillation to stabilize has elapsed, pcc1 and css0 are rewritten so t hat high-speed operation can be selected again. caution when the main system clock is stoppe d and the device is operating on the subsystem clock, wait until the oscillation stabilization ti me has been secured by the program before switching back to the main system clock.
user?s manual u14800ej2v0ud 103 chapter 8 clock generator ( pd789316 subseries) 8.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are used. ? main system clock (rc) oscillator this circuit oscillates at 2.0 to 4.0 mhz. oscillati on can be stopped by executing the stop instruction or setting the processor clock control register (pcc). ? subsystem clock oscillator this circuit oscillates at 32.768 khz. oscillation can be stopped by the suboscilla tion mode register (sckm). 8.2 clock generator configuration the clock generator includes the following hardware. table 8-1. configuration of clock generator item configuration control registers processor cl ock control register (pcc) suboscillation mode register (sckm) subclock control register (css) oscillators main system clock oscillator subsystem clock oscillator
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 104 figure 8-1. block diag ram of clock generator f xt f cc prescaler f cc 2 2 f xt 2 1/2 prescaler watch timer lcd controller /driver clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller selector stop mcc pcc1 cls css0 internal bus suboscillation mode register (sckm) frc scc internal bus subclock control register (css) processor clock control register (pcc) subsystem clock oscillator cl1 cl2 xt1 xt2 main system clock oscillator
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 105 8.3 registers controlling clock generator the clock generator is controll ed by the following registers. ? processor clock control register (pcc) ? suboscillation mode register (sckm) ? subclock control register (css) (1) processor clock control register (pcc) pcc sets cpu clock selection and the division ratio. pcc is set with a 1-bit or 8-bit me mory manipulation instruction. reset input sets pcc to 02h. figure 8-2. format of processo r clock control register control of main system clock oscillator operation mcc00000 pcc1 0 pcc symbol address after reset r/w fffbh 02h r/w <7>6543210 mcc 0 1 operation enabled operation disabled 0.5 s 2.0 s 122 s selection of cpu clock (f cpu ) note css0 0 0 1 1 pcc1 0 1 0 1 f cc f cc /2 2 f xt /2 minimum instruction execution time: 2/f cpu f cc = 4.0 mhz or f xt = 32.768 khz operation note the cpu clock is selected according to a combinati on of the pcc1 flag in the processor clock control register (pcc) and the css0 flag in the s ubclock control register (css) (refer to 8.3 (3) subclock control register (css) ). cautions 1. bits 0 and 2 to 6 must be set to 0. 2. the mcc can be set only when the subsyst em clock has been select ed as the cpu clock. remarks 1. f cc : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 106 (2) suboscillation mode register (sckm) sckm selects a feedback resistor for the subsystem clock, and controls the o scillation of the clock. sckm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sckm to 00h. figure 8-3. format of subo scillation mode register feedback resistor selection note 000000frcscc sckm symbol address after reset r/w fff0h 00h r/w 76543210 frc 0 1 on-chip feedback resistor used on-chip feedback resistor not used control of subsystem clock oscillator operation scc 0 1 operation enabled operation disabled note the feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the supply voltage. only when the subclock is not used, t he power consumption in stop mode can be further reduced by setting frc = 1. caution bits 2 to 7 must be set to 0.
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 107 (3) subclock control register (css) css specifies whether the main system or subsystem clock oscillator is to be selected. it also specifies the cpu clock operation status. css is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears css to 00h. figure 8-4. format of subclock control register cpu clock operation status 0 0 cls css0 0000 css address after reset r/w fff2h 00h r/w 76543210 cls 0 1 operation based on the output of the divided main system clock operation based on the subsystem clock selection of the main system or subsystem clock oscillator css0 0 1 divided output from the main system clock oscillator output from the subsystem clock oscillator symbol note note bit 5 is read only. caution bits 0 to 3, 6, and 7 must be set to 0.
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 108 8.4 system clock oscillators 8.4.1 main system clock oscillator the main system clock oscillator is oscillated by the re sistor (r) and capacitor (c) (4.0 mhz: typ.) connected across the cl1 and cl2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the cl1 pin, and input the inverted signal to the cl2 pin. figure 8-5 shows the external circuit of the main system clock oscillator. figure 8-5. external circuit of main system clock oscillator (a) rc oscillation (b) external clock v ss cl1 r c cl2 external clock cl1 cl2 caution when using the main system or subsystem cl ock oscillator, wire as follo ws in the area enclosed by the broken lines in figures 8-5 and 8-6 to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator.
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 109 8.4.2 subsystem clock oscillator the subsystem clock oscillator is oscillated by the cr ystal resonator (32.768 khz t yp.) connected across the xt1 and xt2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the xt1 pin, and input the inverted signal to the xt2 pin. figure 8-6 shows the external circuit of the subsystem clock oscillator. figure 8-6. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 v ss xt1 32.768 khz crystal resonator external clock xt1 xt2 caution when using the main system or subsystem cl ock oscillator, wire as follo ws in the area enclosed by the broken lines in figures 8-5 and 8-6 to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. when using the subsystem clo ck, particular care is require d because the s ubsystem clock oscillator is designed as a low-amplitude ci rcuit for reducing cu rrent consumption.
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 110 8.4.3 examples of incorrect resonator connection figure 8-7 shows examples of incorrect resonator connection. figure 8-7. examples of incorr ect resonator connection (1/3) (a) too long wiring ? main system clock ? subsystem clock v ss cl2 cl1 xt1 xt2 v ss (b) crossed signal line ? main system clock ? subsystem clock v ss cl2 portn (n = 0 to 2, 5) cl1 portn (n = 0 to 3, 5) xt1 xt2 v ss
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 111 figure 8-7. examples of incorr ect resonator connection (2/3) (c) wiring near high fluctuating current ? main system clock ? subsystem clock v ss cl2 cl1 high current xt1 xt2 v ss high current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) ? main system clock ? subsystem clock v ss v dd cl2 cl1 portn (n = 0 to 3, 5) ab high current v dd portn (n = 0 to 3, 5) xt1 xt2 v ss abc high current
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 112 figure 8-7. examples of incorr ect resonator connection (3/3) (e) signal is fetched ? main system clock ? subsystem clock v ss cl2 cl1 xt1 xt2 v ss (f) parallel and near signal lines of main system clock and subsystem clock v ss xt1 xt2 is wired parallel to cl1. xt2 cl1 cl2
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 113 8.4.4 divider circuit the divider circuit divides the output of the main system clock oscillator (f cc ) to generate various clocks. 8.4.5 when no subsyst em clock is used if a subsystem clock is not necessary, for example, fo r low-power consumption oper ation or clock operation, handle the xt1 and xt2 pins as follows: xt1: connect to v ss xt2: leave open in this case, however, a small current leaks via the on- chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. to avoid this, set bit 1 (frc) of the suboscilla tion mode register (sckm) so that the on-chip feedback resistor will not be used. also in this case, handle the xt1 and xt2 pins as stated above.
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 114 8.5 clock generator operation the clock generator generates the following clocks and controls the operat ion modes of the cpu, such as the standby mode. ? main system clock f cc ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the operation and function of the clock generator is dete rmined by the processor clock control register (pcc), suboscillation mode register (sckm), and subclo ck control register (css), as follows. (a) the low-speed mode (2.0 s: at 4.0 mhz operation) of the ma in system clock is selected when the reset signal is generated (pcc = 02h). while a low leve l is input to the reset pin, oscillation of the main system clock is stopped. (b) three types of minimum instruction execution time (0.5 s and 2.0 s: main system clock (at 4.0 mhz operation), 122 s: subsystem clock (at 32.768 khz operati on)) can be selected by the pcc, sckm, and css settings. (c) two standby modes, stop and halt , can be used with the main system clock selected. in a system where no subsystem clock is used, setting bit 1 (f rc) of the sckm so t hat the on-chip feedback resistor cannot be used reduces curr ent consumption in stop mode. in a system where a subsystem clock is used, setting sckm bit 0 to 1 can c ause the subsystem clock to stop oscillation. (d) css bit 4 (css0) can be used to select the subsyst em clock so that low cu rrent consumption operation is used (122 s: at 32.768 khz operation). (e) with the subsystem clock selected, it is possibl e to cause the main system clock to stop oscillating using bit 7 (mcc) of pcc. the halt mode can be used, but the stop mode cannot. (f) the clock pulse for the peripheral hardware is generated by dividing the fr equency of the main system clock, but the subsystem clock pulse is only suppli ed to the watch timer and lcd controller/driver. the watch timer and lcd controller/driver can ther efore keep running even dur ing standby. the other hardware stops when the main syst em clock stops because it runs based on the main system clock (except for external input clock operations).
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 115 8.6 changing setting of s ystem clock and cpu clock 8.6.1 time required for switching between system clock and cpu clock the cpu clock can be selected by using bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css). actually, the specified clock is not selected immediately after the se tting of pcc has been changed, and the old clock is used for the duration of se veral instructions after that (see table 8-2 ). table 8-2. maximum time re quired for switching cpu clock set value before switching set value after switching css0 pcc1 css0 pcc1 css0 pcc1 css0 pcc1 0 0 0 1 1 x 0 0 4 clocks 2f cc /f xt clocks (244 clocks) 1 2 clocks f cc /2f xt clocks (61 clocks) 1 x 2 clocks 2 clocks remarks 1. two clocks are the minimum instruction execut ion time of the cpu clock before switching. 2. the parenthesized values apply to operation at f cc = 4.0 mhz or f xt = 32.768 khz. 3. x: don?t care
chapter 8 clock generator ( pd789316 subseries) user?s manual u14800ej2v0ud 116 8.6.2 switching between system clock and cpu clock the following figure illustrates how t he cpu clock and system clock switch. figure 8-8. switching between system clock and cpu clock system clock cpu clock interrupt request signal reset v dd f cc f cc f xt f cc low-speed operation high-speed operation subsystem clock operation high-speed operation wait (32 s: at 4.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on pow er application. the effect of resetting is released when the reset pin is later made high, and the main syst em clock starts oscillating. at this time, the oscillation stabilization time (2 7 /f cc ) is automatically secured. after that, the cpu starts inst ruction execution at the slow s peed of the main system clock (2.0 s: at 4.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at high speed has elapsed, bit 1 (pcc1) of the processor clock cont rol register (pcc) and bit 4 (css0) of the subclock control register (css) are rewritten so that high-speed operat ion can be selected. <3> a drop of the v dd voltage is detected with an in terrupt request signal. the clock is switched to the subsystem clock (at this moment, the subsystem clo ck must be in the oscillati on stabilization status). <4> a recover of the v dd voltage is detected with an inte rrupt request signal. bit 7 (mcc) of pcc is set to 0, and then the main system clock starts oscillating. after the time required for the oscillation to stabilize has elapsed, pcc1 and css0 are rewritten so t hat high-speed operation can be selected again. caution when the main system clock is stoppe d and the device is operating on the subsystem clock, wait until the oscillation stabilization ti me has been secured by the program before switching back to the main system clock.
user?s manual u14800ej2v0ud 117 chapter 9 16-bit timer 20 16-bit timer 20 references the free r unning counter and provides the functions such as timer interrupt and timer output. in addition, the count value can be captured by a capt ure trigger pin. 9.1 16-bit timer 20 functions 16-bit timer 20 has the following functions. ? timer interrupt ? timer output ? count value capture (1) timer interrupt an interrupt is generated when a count value and compare value matches. (2) timer output timer output control is possible when a count value and compare value matches. (3) count value capture the 16-bit timer counter 20 (tm20) c ount value is latched to capture r egister in synchronization with the capture trigger and retained.
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 118 9.2 16-bit timer 20 configuration 16-bit timer 20 includes in the following hardware. table 9-1. configuration of 16-bit timer 20 item configuration timer counter 16 bits 1 (tm20) registers compare register: 16 bits 1 (cr20) capture register: 16 bits 1 (tcp20) timer outputs 1 (to20) control registers 16-bit timer mode control register 20 (tmc20) port mode register 2 (pm2) port mode register 3 (pm3) port 2 (p2) figure 9-1. block diag ram of 16-bit timer 20 cpt20/p30 /intp0 internal bus internal bus 16-bit timer mode control register 20 (tmc20) 16-bit timer mode control register 20 (tmc20) tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 f clk f clk /2 5 f clk /2 2 f clk /2 7 edge detector 16-bit capture register 20 (tcp20) 16-bit counter read buffer 16-bit timer counter 20 (tm20) 16-bit compare register 20 (cr20) match selector ovf f/f tod20 to20/p26 inttm20 p26 output latch pm26 remark f clk : f x or f cc
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 119 (1) 16-bit compare register 20 (cr20) this register compares the value set to cr20 with the count value of 16-bit timer counter 20 (tm20), and when they match, generates an interrupt request (inttm20). cr20 is set with a 16-bit memory manipulation instruct ion. the values 0000h to ffffh can be set. reset input sets cr20 to ffffh. cautions 1. this register is manipulated with a 16-bit memory manipulation instruction, however an 8-bit memory manipulation instruction can al so be used. when manipulated with an 8- bit memory manipulation instruction, the accessing method should be direct addressing. 2. when rewriting cr20 during a count opera tion, preset cr20 to interrupt disabled using interrupt mask flag register 0 (mk0). al so set the timer output data to inversion disabled using 16-bit timer mode control register 20 (tmc20). if cr20 is rewritten while interrupts are en abled, an interrupt re quest may be generated at that time. (2) 16-bit timer counter 20 (tm20) this is a 16-bit register that counts count pulses. tm20 is read with a 16-bit memory manipulation instruction. this register is in free running mode during count clock input. reset input sets tm20 to 0000h and then to free running mode again. cautions 1. the count value after releasing st op becomes undefined because the count operation is executed during the oscillation stabilization time. 2. this register is manipulated with a 16-bi t memory manipulation instruction, however an 8-bit memory manipulation instruction can al so be used. when manipulated with an 8- bit memory manipulation instruction, the accessing method should be direct addressing. 3. when manipulated with an 8-bit memory manipulation instruction, readout should be performed in the order from lower byte to higher byte and must be in pairs. (3) 16-bit capture register 20 (tcp20) this is a 16-bit register that captures t he contents of 16-bit timer counter 20 (tm20). the tcp20 is set with a 16-bit me mory manipulation instruction. reset input sets tcp20 undefined. caution this register is manipulated with a 16-bi t memory manipulation in struction, however an 8- bit memory manipulation instru ction can also be used. wh en manipulated with an 8-bit memory manipulation instruction, the accessing method should be direct addressing. (4) 16-bit counter read buffer this buffer latches a counter value and retains t he count value of 16-bit timer counter 20 (tm20).
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 120 9.3 registers controlling 16-bit timer 20 the following four register s control 16-bit timer 20. ? 16-bit timer mode control register 20 (tmc20) ? port mode register 2 (pm2) ? port mode register 3 (pm3) ? port 2 (p2) (1) 16-bit timer mode control register 20 (tmc20) 16-bit timer mode control register 20 (tmc20) controls the setting of t he count clock, c apture edge, etc. tmc20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc20 to 00h.
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 121 figure 9-2. format of 16-bit timer mode control register 20 toc20 0 1 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 tmc20 r/w ff48h 00h r/w <6>54321 cpt201 0 0 1 1 cpt200 0 1 0 1 capture operation disabled rising edge of cpt20 falling edge of cpt20 both edges of cpt20 tof20 0 1 <7> <0> set by overflow of 16-bit timer symbol address after reset timer output data inversion control inversion disabled inversion enabled capture edge selection during f x = 5.0 mhz operation during f cc = 4.0 mhz operation toe20 0 1 tcl201 0 0 tcl200 0 1 f x (5.0 mhz) f x /2 2 (1.25 mhz) f x /2 5 (156.3 khz) f x /2 7 (39.1 khz) f cc (4.0 mhz) f cc /2 2 (1.0 mhz) f cc /2 5 (125 khz) f cc /2 7 (31.3 khz) 1 1 0 1 16-bit timer counter 20 output control output disabled (port mode) output enabled 16-bit timer counter 20 count clock selection overflow flag set cleared by reset and software 0 1 timer output data is 1 timer output data is 0 tod20 timer output data note note bit 7 is read-only. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation)
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 122 (2) port mode register 2, 3 (pm2, pm3) this register sets the input/out put of port 2, 3 in 1-bit units. to use the p26/to20 pin for timer output, se t the output latch of pm26 and p26 to 0. to use the p30/intp0/cpt20 pin for capture input, set the pm30 to 1. pm2, pm3 is set with a 1-bit or 8-bi t memory manipulation instruction. reset input sets pm2 to ffh. figure 9-3. format of port mode register 2, 3 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 r/w ff22h ffh r/w 654321 70 symbol address after reset 11 11 pm33 pm32 pm31 pm30 pm3 ff23h ffh r/w pmmn 0 1 input mode (output buffer off) pmn pin input/output mode selection (mn = 20-26, 30-33) output mode (output buffer on)
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 123 9.4 16-bit timer 20 operation 9.4.1 operation as timer interrupt 16-bit timer 20 can generate interrupts repeatedly each time the free-running counter val ue reaches the value set to cr20. since this counter is not cl eared and holds the count even after an interr upt is generated, the interval time is equal to one cycle of the count clock set in tcl201 and tcl200. to operate 16-bit timer 20 as a timer interrupt, the following settings are required. ? set count values to cr20 ? set 16-bit timer mode control register 20 (tmc20) as shown in figure 9-4. figure 9-4. settings of 16-bit timer mode cont rol register 20 at timer interrupt operation ? 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 tmc20 setting of count clock (see table 9-2 ) caution if both the cpt201 flag and cpt200 flag ar e set to 0, the capture edge becomes operation disabled. when the count value of 16-bit time r counter 20 (tm20) matches the va lue set to cr20, counting of tm20 continues and an interrupt request signal (inttm20) is generated. table 9-2 shows the interval time, and figure 9-5 s hows the timing of the ti mer interrupt operation. caution process as follows when rewr iting cr20 during a count operation. <1> set the interrupt to disabled (tmmk20 (bit 1of interrupt mask flag register 1(mk1) = 1) <2> set the inversion control of time r output data to disabled (toc20 = 0) if cr20 is rewritten while interrupts are enab led, an interrupt request may be generated at that time. table 9-2. interval time of 16-bit timer 20 count clock interval time tcl201 tcl200 during f x = 5.0 mhz operation during f cc = 4.0 mhz operation during f x = 5.0 mhz operation during f cc = 4.0 mhz operation 0 0 1/f x (0.2 s) 1/f cc (0.25 s) 2 16 /f x (13.1 ms) 2 16 /f cc (16.4 ms) 0 1 2 2 /f x (0.8 s) 2 2 /f cc (1.0 s) 2 18 /f x (52.4 ms) 2 18 /f cc (65.5 ms) 1 0 2 5 /f x (6.4 s) 2 5 /f cc (8.0 s) 2 21 /f x (419.4 ms) 2 21 /f cc (524.2 ms) 1 1 2 7 /f x (25.6 s) 2 7 /f cc (32 s) 2 23 /f x (1.68 s) 2 23 /f cc (2.10 ms) remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation)
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 124 figure 9-5. timing of timer interrupt operation count clock tm20 count value cr20 inttm20 to20 tof20 0000h 0001h n ffffh 0000h 0001h n ffffh nn n nn interrupt acknowledgement interrupt acknowledgement overflow flag set remark n = 0000h to ffffh
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 125 9.4.2 operation as timer output 16-bit timer 20 can invert the timer output repeatedly each time the free-running counter va lue reaches the value set to cr20. since this counter is not cleared and holds the count even after the timer output is inverted, the interval time is equal to one cycle of the count clock set in tcl201 and tcl200. to operate 16-bit timer 20 as a timer out put, the following settings are required. ? set p26 to output mode (pm26 = 0) ? set the output latch of p26 to 0 ? set the count value to cr20 ? set 16-bit timer mode control regist er 20 (tmc20) as shown in figure 9-6 figure 9-6. settings of 16-bit timer mode c ontrol register 20 at timer output operation ? 0/1 0/1 0/1 1 0/1 0/1 1 tod20 tof20 cpt201 cpt200 toc20 tcl201 tcl200 toe20 tmc20 setting of count clock (see table 9-2 ) inversion enable of timer output data to20 output enable caution if both the cpt201 flag and cpt200 flag ar e set to 0, the capture edge becomes operation disabled. when the count value of 16-bit timer c ounter 20 (tm20) matches the value set in cr20, the output status of the to20/p26 pin is inverted. this enables timer output. at that time, tm20 continues counting and an interrupt request signal (inttm20) is generated. figure 9-7 shows the timing of timer output (see table 9-2 for the interval time of the 16-bit timer 20). figure 9-7. timer output timing count clock tm20 count value cr20 inttm20 to20 note tof20 0000h 0001h n ffffh 0000h 0001h n ffffh nn n nn interrupt acknowledgement interrupt acknowledgement overflow flag set note the to20 initial value becomes low level during output enable (toe20 = 1). remark n = 0000h to ffffh
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 126 9.4.3 capture operation the capture operation f unctions to capture and latch the count value of 16-bit timer counter 20 (tm20) to the capture register in synchroni zation with a capture trigger. set as shown in figure 9-8 to allow 16-bi t timer 20 to start the capture operation. figure 9-8. settings of 16-bit timer mode control register 20 at capture operation ? 0/1 0/1 0/1 0/1 0/1 0/1 0/1 tod 20 tof 20 cpt201 cpt200 toc 20 tcl201 tcl200 toe 20 tmc20 count clock selection capture edge selection (see table 9-3 ) 16-bit capture register 20 (tcp20) starts a capture operation after t he cpt20 capture trigger edge has been detected, and latches and retains the c ount value of 16-bit timer counter 20 (tm20). tcp20 fetches count value within 2 clocks and retains the count va lue until the next c apture edge detection. table 9-3 and figure 9-9 show the setti ng contents of the captur e edge and capture operation timing, respectively. table 9-3. setting contents of capture edge cpt201 cpt200 capture edge selection 0 0 capture operation disabled 0 1 rising edge of cpt20 pin 1 0 falling edge of cpt20 pin 1 1 both edges of cpt20 pin caution because tcp20 is rewritten when a capture trigger edge is detected during a tcp20 read, disable capture trigger edge detection during a tcp20 read. figure 9-9. capture operation timing (w ith both edges of cpt20 pin specified) count clock tm20 counter read buffer tcp20 cpt20 0000h 0000h 0001h 0001h undefined n n n m ? 1 m m m capture start capture start capture edge detection capture edge detection
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 127 9.4.4 16-bit timer counter 20 readout the count value of 16-bit timer c ounter 20 (tm20) is read out by a 16-bit manipulation instruction. tm20 readout is performed through a counter read buffer. the counter read bu ffer latches the tm20 count value, and buffer operation is held pending at the cpu clock falling edge after the read signal of the tm20 lower byte rises and the count value is retained. the counter read buffer value in the retent ion state can be read out as the count value. cancellation of pending is performed at the cpu clock fa lling edge after the read signal of the tm20 higher byte falls. reset input sets tm20 to 0000h and starts it free running. figure 9-10 shows the timing of 16-bit timer counter 20 readout. cautions 1. the count value after releasing st op becomes undefined because the count operation is executed during oscillation stabilization time. 2. although tm20 is a register dedicated for a 16- bit transfer instructi on, an 8-bit transfer instruction can also be used. when using an 8-bit transfer instru ction, execute it using direct addressing. 3. when using an 8-bit transfer instruction, execute in the order from lower byte to higher byte in pairs. if only the lower byte is read, th e pending state of the counter read buffer is not canceled, and if only the higher byte is read, an undefined c ount value is read. figure 9-10. 16-bit timer counter 20 readout timing cpu clock count clock tm20 counter read buffer tm20 read signal 0000h 0000h 0001h 0001h n n n + 1 read signal latch dosabled period remark n = 0000h to ffffh
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 128 9.5 cautions on using 16-bit timer 20 9.5.1 restrictions when rewr iting 16-bit compare register 20 (1) disable interrupts (tmmk20 = 1) and the inversion cont rol of timer output (toc20 = 0) before rewriting the compare register (cr20). if cr20 is rewritten with interrupts enabled, an interrupt request may be generated immediately. (2) depending on the timing of rewriti ng the compare register (cr20), the interval time may become twice as long as the intended time. similarly, a shorter wa veform or twice-longer waveform than the intended timer output waveform may be output. to avoid this problem, rewrite the compare register using either of the following procedures a or b. when rewriting using 8-bit access <1> disable interrupts (tmmk20 = 1) and the inve rsion control of timer output (toc20 = 0). <2> first rewrite the higher 1 byte of cr20 (16 bits). <3> then rewrite the lower 1 byte of cr20 (16 bits). <4> clear the interrupt request flag (tmif20). <5> enable timer interrupts/timer output inversion after hal f a cycle or more of the count clock has elapsed from the beginning of the interrupt. (count clock = 32/f x , cpu clock = f x ) tm20_vct: set1 tmmk20 ; disable timer interrupts (6 clocks) clr1 tmc20.3 ; disable timer output inversion (6 clocks) mov a,#xxh ; set the rewrite value of higher byte (6 clocks) mov !0ff17h,a ; rewrite cr20 higher byte (8 clocks) mov a,#yyh ; set the rewrite value of lower byte (6 clocks) mov !0ff16h,a ; rewrite cr20 lower byte (8 clocks) clr1 tmif20 ; clear interrupt request flag (6 clocks) clr1 tmmk20 ; enable timer interrupts (6 clocks) set1 tmc20.3 ; enable timer output inversion note because the inttm20 signal becomes high level for hal f a cycle of the count clock after an interrupt is generated, the output is inve rted if toc20 is set to 1 during this period. total: 16 clocks or more note
chapter 9 16-bit timer 20 user?s manual u14800ej2v0ud 129 when rewriting using 16-bit access <1> disable interrupts (tmmk20 = 1) and the inve rsion control of timer output (toc20 = 0). <2> rewrite cr20 (16 bits). <3> wait for one cycle or more of the count clock. <4> clear the interrupt request flag (tmif20). <5> enable timer interrupts/timer output inversion. (count clock = 32/f x , cpu clock = f x ) tm20_vct set1 tmmk20 ; disable timer interrupts clr1 tmc20.3 ; disable timer output inversion movw ax,#xxyyh ; set the rewrite value of cr20 movw cr20,ax ; rewrite cr20 nop nop : ; 16 nop instructions (wait for 32/f x ) note nop nop clr1 tmif20 ; clear interrupt request flag clr1 tmmk20 ; enable timer interrupts set1 tmc20.3 ; enable timer output inversion note clear the interrupt request flag (tmif20) after wait ing for one cycle or more of the count clock from the instruction rewriting cr20 (movw cr20, ax).
user?s manual u14800ej2v0ud 130 chapter 10 8-bit timer 30, 40 10.1 8-bit timer 30, 40 functions an 8-bit timer (one channel, timer 30) and an 8-bit timer/ev ent counter (one channel, time r 40) are incorporated in the pd789306, 789316 subseries. t he operation modes listed in the followi ng table can be set via mode register settings. table 10-1. operation modes channel mode timer 30 timer 40 8-bit timer counter mode (discrete mode) available available 16-bit timer counter mode (cascade connection mode) available carrier generator mode available pwm output mode not available available (1) 8-bit timer counter mode (discrete mode) the following functions can be used in this mode. ? interval timer with 8-bit resolution ? external event counter with 8- bit resolution (timer 40 only) ? square wave output with 8-bit resolution (2) 16-bit timer counter m ode (cascade connection mode) operation as a 16-bit time r/event counter is enabled dur ing cascade connection mode. the following functions can be used in this mode. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square wave output with 16-bit resolution (3) carrier generator mode the carrier clock generated by timer 40 is output in cycles set by timer 30. (4) pwm output mode (timer 40 only) pulses are output using any duty factor set by timer 40.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 131 10.2 8-bit timer 30, 40 configuration the 8-bit timer 30, 40 includes the following hardware. table 10-2. 8-bit timer 30, 40 configuration item configuration timer counters 8 bits 2 (tm30, tm40) registers compare registers: 8 bits 3 (cr30, cr40, crh40) timer outputs 2 (to30, to40) control registers 8-bit timer mode control register 30 (tmc30) 8-bit timer mode control register 40 (tmc40) carrier generator output control register 40 (tca40) port mode register 3 (pm3) port 3 (p3)
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 132 tce30 tcl300 tmd300 tcl301 8-bit timer mode control register 30 (tmc30) selector decoder selector selector 8-bit compare register 30 (cr30) 8-bit timer counter 30 (tm30) selector internal reset signal timer 40 match signal (during cascade connection mode) timer 30 match signal (during cascade connection mode) from figure 10-2 (d) count operation start signal (during cascade connection mode) inttm30 f clk /2 4 f clk /2 8 timer 40 interrupt request signal (from figure 10-2 (b)) carrier clock (from figure 10-2 (c)) clear cascade connection mode match from figure 10-2 (e) to figure 10-2 (f) to figure 10-2 (g) internal bus ovf timer 30 match signal (during carrier generator mode) bit 7 of tm40 (from figure 10-2 (a)) (a) (c) (d) (e) (f) (g) (b) toe30 pm31 p31 output latch to30/p31/ intp1/tmi40 figure 10-1. block diagram of timer 30 remark f clk : f x or f cc
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 133 tce40 tcl402 tcl401 tcl400 tmd401 tmd400 toe40 8-bit timer mode control register 40 (tmc40) decoder 8-bit timer counter 40 (tm40) f/f tm30 match signal (during cascade connection mode) count operation start signal to timer 30 (during cascade connection mode) tm40 timer counter match signal (during cascade connection mode) clear 8-bit compare register 40 (cr40) selector output control ler note rmc40 nrzb40 nrz40 carrier generator output control register 40 (tca40) to figure 10-1 (d) (d) (f) (e) (b) (a) (c) (g) count clock input signal to tm30 internal reset signal inttm40 to figure 10-1 (a) bit 7 of tm40 (during cascade connection mode) from figure 10-1 (f) to figure 10-1 (e) match to40/p32/intp2 to figure 10-1 (c) carrier clock reset carrier generator mode pwm mode cascade connection mode 8-bit compare register h40 (crh40) internal bus selector ovf to figure 10-1 (b) timer 40 interrupt request signal from figure 10-1 (g) timer counter match signal from timer 30 (during carrier generator mode) f clk /2 3 f clk /2 7 tmi40/p31/ intp1/to30 tmi/2 tmi/2 2 tmi/2 3 prescaler figure 10-2. block diagram of timer 40 note for details, see figure 10-3 . remark f clk : f x or f cc
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 134 figure 10-3. block diagram of output controller (timer 40) f/f rmc40 nrz40 toe40 pm32 p32 output latch selector to40/p32/ intp2 carrier generator mode carrier clock (1) 8-bit compare register 30 (cr30) this 8-bit register is used to continually compare t he value set to cr30 with the count value in 8-bit timer counter 30 (tm30) and to generate an interrupt request (inttm30) when a match occurs. cr30 is set with an 8-bit memory manipulation instruction. reset input makes cr30 undefined. caution cr30 cannot be used during pwm output mode. (2) 8-bit compare register 40 (cr40) this 8-bit register is used to continually compare t he value set to cr40 with the count value in 8-bit timer counter 40 (tm40) and to generate an interrupt request (inttm40) when a match occurs. when connected to tm30 via a cascade connection and used as a 16-bit ti mer/event counter, the in terrupt request (inttm40) occurs only when matches occur simultaneous ly between cr30 and tm30 and between cr40 and tm40 (inttm30 does not occur). in carrier generator mode and pwm output mode, this registers is used for low-level width setting. cr40 is set with an 8-bit memory manipulation instruction. reset input makes cr40 undefined. (3) 8-bit compare register h40 (crh40) during carrier generator mode or pwm out put mode, the high-level width of timer output is set by writing a value to crh40. the value set in crh40 is constant ly compared with tm40 count value, and an interrupt request (inttm40) is generated if they match. crh40 is set with an 8-bit memory manipulation instruction. reset input makes crh40 undefined.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 135 (4) 8-bit timer counters 30 and 40 (tm30 and tm40) these are 8-bit registers that ar e used to count the count pulse. tm30 and tm40 are read with an 8-bit me mory manipulation instruction. reset input clears tm30 and tm40 to 00h. tm30 and tm40 are cleared to 00h under the following conditions. (a) discrete mode (i) tm30 ? after reset ? when tce30 (bit 7 of 8-bit timer mode c ontrol register 30 (tmc30)) is cleared to 0 ? when a match occurs between tm30 and cr30 ? when the tm30 count value overflows (ii) tm40 ? after reset ? when tce40 (bit 7 of 8-bit timer mode c ontrol register 40 (tmc40)) is cleared to 0 ? when a match occurs between tm40 and cr40 ? when the tm40 count value overflows (b) cascade connection mode (tm30 and tm 40 are simultaneously cleared to 00h) ? after reset ? when the tce40 flag is cleared to 0 ? when matches occur simultaneously bet ween tm30 and cr30 and between tm40 and cr40 ? when the tm30 and tm40 count va lues overflow simultaneously (c) carrier generator mode/p wm output mode (tm40 only) ? after reset ? when the tce40 flag is cleared to 0 ? when a match occurs between tm40 and cr40 ? when a match occurs between tm40 and crh40 ? when the tm40 count value overflows
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 136 10.3 registers controlling 8-bit timer 30, 40 the 8-bit timer 30, 40 is controlled by the following five registers. ? 8-bit timer mode control register 30 (tmc30) ? 8-bit timer mode control register 40 (tmc40) ? carrier generator output c ontrol register 40 (tca40) ? port mode register 3 (pm3) ? port 3 (p3)
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 137 (1) 8-bit timer mode control register 30 (tmc30) 8-bit timer mode control register 30 (tmc30) is us ed to control the timer 30 count clock setting and the operation mode setting. tmc30 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc30 to 00h. figure 10-4. format of 8-bit timer mode control register 30 symbol <7> 6 5 4 3 2 1 <0> address after reset r/w tmc30 tce30 0 0 tcl301 tcl300 0 tmd300 toe30 ff4dh 00h r/w tce30 control of tm30 count operation note 1 0 clears tm30 count value and stops operation 1 starts count operation selection of timer 30 count clock tcl301 tcl300 during f x = 5.0 mhz operation during f cc = 4.0 mhz operation 0 0 f x /2 4 (312.5 khz) f cc /2 4 (250 khz) 0 1 f x /2 8 (19.5 khz) f cc /2 8 (15.6 khz) 1 0 timer 40 match signal 1 1 carrier clock (during carrier generator mode) or timer 40 output signal (during a mode other than carrier generator mode) tmd300 tmd401 tmd400 selection of operation mode for timer 30 and timer 40 note 2 0 0 0 8-bit timer counter mode (discrete mode) 1 0 1 16-bit timer counter mode (cascade connection mode) 0 1 1 carrier generator mode 0 1 0 timer 40: pwm output mode timer 30: 8-bit timer counter mode other than above setting prohibited toe30 control of timer output 0 output disabled (port mode) 1 output enabled notes 1. since the count operation is cont rolled by tce40 (bit 7 of tmc 40) in cascade connection mode, any setting for tce30 is ignored. 2. the operation mode selection is set to bot h the tmc30 register and tmc40 register. caution in cascade connection mode, the timer 40 output signal is forcibly selected for the count clock. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation)
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 138 (2) 8-bit timer mode control register 40 (tmc40) 8-bit timer mode control register 40 (tmc40) is us ed to control the timer 40 count clock setting and the operation mode setting. tmc40 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc40 to 00h. figure 10-5. format of 8-bit timer mode control register 40 symbol <7> 6 5 4 3 2 1 <0> address after reset r/w tmc40 tce40 0 tcl402 tcl401 tcl400 tmd401 tmd400 toe40 ff4eh 00h r/w tce40 control of tm40 count operation note 1 0 clears tm40 count value and stops operation (the c ount value is also cleared for tm30 during cascade connection mode) 1 starts count operation (the c ount operation is also started fo r tm30 during cascade connection mode) selection of timer 40 count clock tcl402 tcl401 tcl400 during f x = 5.0 mhz operation during f cc = 4.0 mhz operation 0 0 0 f x /2 3 (625 khz) f cc /2 3 (500 khz) 0 0 1 f x /2 7 (39.1 khz) f cc /2 7 (31.3 khz) 0 1 0 f tmi 0 1 1 f tmi /2 1 0 0 f tmi /2 2 1 0 1 f tmi /2 3 tmd300 tmd401 tmd400 selection of operation mode for timer 30 and timer 40 note 2 0 0 0 8-bit timer counter mode (discrete mode) 1 0 1 16-bit timer counter mode (cascade connection mode) 0 1 1 carrier generator mode 0 1 0 timer 40: pwm output mode timer 30: 8-bit timer counter mode other than above setting prohibited toe40 control of timer output 0 output disabled (port mode) 1 output enabled notes 1. since the count operation is cont rolled by tce40 (bit 7 of tmc 40) in cascade connection mode, any setting for tce30 is ignored. 2. the operation mode selection is set to bot h the tmc30 register and tmc40 register. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation) 3. f tmi : external clock input from the tmi40 pin
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 139 (3) carrier generator output control register 40 (tca40) this register is used to set the time r output data during ca rrier generator mode. tca40 is set with an 8-bit memo ry manipulation instruction. reset input clears tca40 to 00h. figure 10-6. format of carrier gene rator output control register 40 symbol 7 6 5 4 3 2 1 0 address after reset r/w tca40 0 0 0 0 0 rmc40 nrzb40 nrz40 ff4fh 00h w rmc40 control of remote control output 0 when nrz40 = 1, a carrier pulse is output to to40/intp2/p32 pin 1 when nrz40 = 1, high-level signal is output to to40/intp2/p32 pin nrzb40 this is the bit that stores the next data to be out put to nrz40. data is transferred to nrz40 at the rising edge of the timer 30 match signal. nrz40 no return zero data 0 outputs low-level signal (carrier clock is stopped) 1 outputs carrier pulse or high-level signal cautions 1. bits 3 to 7 must be set to 0. 2. tca40 cannot be set with a 1-bit memory mani pulation instruction. be sure to use an 8- bit memory manipulation in struction to set tca40. 3. the nrz40 flag can be written only when carrier generator output is stopped (toe40 = 0). the data cannot be o verwritten when toe40 = 1. 4. when the carrier generator is stopped once and then started again, nrzb40 does not hold the previous data. re-set data to nrzb40. at this time, a 1-bit memory manipulation instruction must not be used . be sure to use an 8-bit memory manipulation instruction. 5. to enable operation in the carrier generator mode, set a val ue to the compare registers (cr30, cr40, and crh40), and input th e necessary value to the nrzb40 and nrz40 flags in advance. otherwise, the signal of the timer matc h circuit will become unstable and the nrz40 flag will be undefined. 6. while inttm30 (interrupt generated by the match signal of timer 30) is being output, accessing tca40 is prohibited. accessing tca40 is prohibited while 8- bit timer counter 30 (tm30) is 00h. to access tca40 while tm30 = 00h, wait for mo re than half a period of the tm30 count clock and then rewrite tca40.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 140 (4) port mode register 3 (pm3) this register is used to set the i/o mode of port 3 in 1-bit units. when using the p31/to30/intp1/tmi40 pin as a time r output, set the pm31 and p31 output latch to 0. when using the p31/to30/intp1/tmi40 pin as a timer input, set the pm31 to 1. when using the p32/to40/intp2 pin as a timer output, set the pm32 and p32 output latch to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 10-7. format of port mode register 3 symbol 7 6 5 4 3 2 1 0 address after reset r/w pm3 1 1 1 1 pm33 pm32 pm31 pm30 ff23h ffh r/w pm3n i/o mode of p3n pin (n = 0 to 3) 0 output mode (output buffer is on) 1 input mode (output buffer is off)
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 141 10.4 8-bit timer 30, 40 operation 10.4.1 operation as 8-bit timer counter timer 30 and timer 40 can independently be used as an 8-bit timer counter. the following modes can be used for the 8-bit timer counter. ? interval timer with 8-bit resolution ? external event counter with 8- bit resolution (timer 40 only) ? square wave output with 8-bit resolution (1) operation as interval timer with 8-bit resolution the interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register n0 (crn0). to operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter n0 (tmn0) (tcen0 = 0). <2> disable timer output of ton0 (toen0 = 0). <3> set a count value in crn0. <4> set the operation mode of timer n0 to 8-bi t timer counter mode (see figures 10-4 and 10-5). <5> set the count clock for timer n0 (see tables 10-3 to 10-6). <6> enable the operation of tmn0 (tcen0 = 1). when the count value of 8-bit timer counter n0 (tmn0) matches the val ue set in crn0, tmn0 is cleared to 00h and continues counting. at the same time, an interrupt request signal (inttmn0) is generated. tables 10-3 to 10-6 show interval time, and figures 10-8 to 10-12 show the timing of the interval timer operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data. remark n = 3, 4
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 142 table 10-3. interval time of timer 30 (during f x = 5.0 mhz operation) tcl301 tcl300 minimum interval time ma ximum interval time resolution 0 0 2 4 /f x (3.2 s) 2 12 /f x (0.82 ms) 2 4 /f x (3.2 s) 0 1 2 8 /f x (51.2 s) 2 16 /f x (13.1 ms) 2 8 /f x (51.2 s) 1 0 input cycle of timer 40 match signal input cycle of timer 40 match signal 2 8 input cycle of timer 40 match signal 1 1 input cycle of timer 40 output input cycle of timer 40 output 2 8 input cycle of timer 40 remark f x : main system clock oscillation frequency (ceramic/crystal oscillation) table 10-4. interval time of timer 30 (during f cc = 4.0 mhz operation) tcl301 tcl300 minimum interval time ma ximum interval time resolution 0 0 2 4 /f cc (4.0 s) 2 12 /f cc (1.02 ms) 2 4 /f cc (4.0 s) 0 1 2 8 /f cc (64 s) 2 16 /f cc (16.4 ms) 2 8 /f cc (64 s) 1 0 input cycle of timer 40 match signal input cycle of timer 40 match signal 2 8 input cycle of timer 40 match signal 1 1 input cycle of timer 40 output input cycle of timer 40 output 2 8 input cycle of timer 40 remark f cc : main system clock oscillation frequency (rc oscillation) table 10-5. interval time of timer 40 (during f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum interval time maximum interval time resolution 0 0 0 2 3 /f x (1.6 s) 2 11 /f x (0.41 ms) 2 3 /f x (1.6 s) 0 0 1 2 7 /f x (25.6 s) 2 15 /f x (6.55 ms) 2 7 /f x (25.6 s) 0 1 0 f tmi input cycle f tmi input cycle 2 8 f tmi input cycle 0 1 1 f tmi /2 input cycle f tmi /2 input cycle 2 8 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 8 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 8 f tmi /2 3 input cycle remark f x : main system clock oscillation frequency (ceramic/crystal oscillation) table 10-6. interval time of timer 40 (during f cc = 4.0 mhz operation) tcl402 tcl401 tcl400 minimum interval time maximum interval time resolution 0 0 0 2 3 /f cc (2.0 s) 2 11 /f cc (0.51 ms) 2 3 /f cc (2.0 s) 0 0 1 2 7 /f cc (32 s) 2 15 /f cc (8.19 ms) 2 7 /f cc (32 s) 0 1 0 f tmi input cycle f tmi input cycle 2 8 f tmi input cycle 0 1 1 f tm i/2 input cycle f tmi /2 input cycle 2 8 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 8 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 8 f tmi /2 3 input cycle remark f cc : main system clock oscillation frequency (rc oscillation)
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 143 figure 10-8. timing of interval timer oper ation with 8-bit resolution (basic operation) count stop count clock tmn0 crn0 tcen0 inttmn0 ton0 n t tmn0 n 00h 01h n 00h 01h n 00h 00h 01h 00h 01h clear clear clear count start interrupt acknowledgement interrupt acknowledgement interrupt acknowledgement interval time interval time remarks 1. interval time = (n + 1) t: n = 00h to ffh 2. n = 3, 4 figure 10-9. timing of interval timer operation with 8-bit resolution (when crn0 is cleared to 00h) count clock crn0 tcen0 inttmn0 ton0 00h tmn0 00h count start tmn0 remark n = 3, 4
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 144 figure 10-10. timing of interval timer operati on with 8-bit resolution (when crn0 is set to ffh) count clock crn0 tcen0 inttmn0 ton0 ffh tmn0 ffh 00h 01h 00h 01h 00h 00h 01h ffh ffh ffh 00h clear clear clear count start tmn0 remark n = 3, 4 figure 10-11. timing of interval ti mer operation with 8-bit resolution (when crn0 changes from n to m (n < m)) count clock crn0 tcen0 inttmn0 ton0 tmn0 tmn0 n 00h 00h n 00h 01h 00h 01h m nm n m clear clear clear count start interrupt acknowledgement interrupt acknowledgement crn0 overwritten remark n = 3, 4
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 145 figure 10-12. timing of interval ti mer operation with 8-bit resolution (when crn0 changes from n to m (n > m)) count clock crn0 tcen0 inttmn0 ton0 tmn0 tmn0 00h 00h 00h n ? 1 n mn m n m 00h ffh m h clear clear clear tmn0 overflows because m < n crn0 overwritten remark n = 3, 4
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 146 figure 10-13. timing of interval ti mer operation with 8-bit resolution (when timer 40 match signal is sel ected for timer 30 count clock) timer 40 count clock cr40 tce40 inttm40 to40 tm40 n 00h m 00h 00h 01h m n m 00h m 00h 00h 02h y 01h 00h y 00h y to30 inttm30 tce30 cr30 tm30 input clock to timer 30 (timer 40 match signal) clear clear clear clear count start count start
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 147 (2) operation as external event counter with 8-bit resolution (timer 40 only) the external event counter counts t he number of external clock pulses input to the tmi40/p31/intp1/to30 pin by using 8-bit timer counter 40 (tm40). to operate timer 40 as an external event counter , settings must be made in the following sequence. <1> disable operation of 8-bit time r counter 40 (tm40) (tce40 = 0). <2> disable timer output of to40 (toe40 = 0). <3> set p31 to input mode (pm31 = 1). <4> select the external input clo ck for timer 40 (see tables 10-5 and 10-6). <5> set the operation mode of timer 40 to 8-bi t timer counter mode (see figures 10-4 and 10-5). <6> set a count value in cr40. <7> enable the operati on of tm40 (tce40 = 1). note this operation only applies to timer 40. each time the valid edge is input, the value of tm40 is incremented. when the count value of tm40 matc hes the value set in cr40, tm40 is cleared to 00h and continues counting. at the same time, an interr upt request signal (inttm40) is generated. figure 10-14 shows the timing of the external event counter operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 148 figure 10-14. timing of operation of exte rnal event counter with 8-bit resolution tmi40 pin input tm40 count value cr40 tce40 inttm40 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n remark n = 00h to ffh
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 149 (3) operation as square-wave output with 8-bit resolution square waves of any frequency can be output at an interval specified by t he value preset in 8-bit compare register n0 (crn0). to operate timer n0 for square-wave output, se ttings must be made in the following sequence. <1> when using timer 30, set p31 to output mode (pm31 = 0). when using timer 40, set p32 to output mode (pm32 = 0). <2> set the output latches of p31 and p32 to 0. <3> disable operation of timer c ounter n0 (tmn0) (tcen0 = 0). <4> set a count clock for timer n0 and enable output of ton0 (toen0 = 1). <5> set a count value in crn0. <6> enable the operation of tmn0 (tcen0 = 1). when the count value of tmn0 matches the value set in crn0, the ton0 pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match occurs, tmn0 is cleared to 00h and continues counting. at the same time, an in terrupt request signal (inttmn0) is generated. the square-wave output is cleared to 0 by setting tcen0 to 0. tables 10-7 to 10-10 show the squar e-wave output range, and figure 10-15 shows the timing of square-wave output. caution be sure to stop the timer operation before overwriting the count cl ock with different data. remark n = 3, 4 table 10-7. square-wave output range of timer 30 (during f x = 5.0 mhz operation) tcl301 tcl300 minimum pulse width maximum pulse width resolution 0 0 2 4 /f x (3.2 s) 2 12 /f x (0.82 ms) 2 4 /f x (3.2 s) 0 1 2 8 /f x (51.2 s) 2 16 /f x (13.1 ms) 2 8 /f x (51.2 s) remark f x : main system clock oscillation frequency (ceramic/crystal oscillation) table 10-8. square-wave output range of timer 30 (during f cc = 4.0 mhz operation) tcl301 tcl300 minimum pulse width maximum pulse width resolution 0 0 2 4 /f cc (4.0 s) 2 12 /f cc (1.02 ms) 2 4 /f cc (4.0 s) 0 1 2 8 /f cc (64 s) 2 16 /f cc (16.4 ms) 2 8 /f cc (64 s) remark f cc : main system clock oscillation frequency (rc oscillation) table 10-9. square-wave output range of timer 40 (during f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum pulse width maximum pulse width resolution 0 0 0 2 3 /f x (1.6 s) 2 11 /f x (0.41 ms) 2 3 /f x (1.6 s) 0 0 1 2 7 /f x (25.6 s) 2 15 /f x (6.55 ms) 2 7 /f x (25.6 s) remark f x : main system clock oscillation frequency (ceramic/crystal oscillation)
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 150 table 10-10. square-wave output range of timer 40 (during f cc = 4.0 mhz operation) tcl402 tcl401 tcl400 minimum pulse width maximum pulse width resolution 0 0 0 2 3 /f cc (2.0 s) 2 11 /f cc (0.51 ms) 2 3 /f cc (2.0 s) 0 0 1 2 7 /f cc (32 s) 2 15 /f cc (8.19 ms) 2 7 /f cc (32 s) remark f cc : main system clock oscillation frequency (rc oscillation) figure 10-15. timing of square-wave output with 8-bit resolution count clock crn0 tcen0 inttmn0 ton0 note n tmn0 tmn0 n 00h 01h n 00h 01h n 00h 01h 00h 01h clear clear clear count start interrupt acknowledgement interrupt acknowledgement interrupt acknowledgement note the initial value of ton0 is low level when output is enabled (toen0 = 1). remark n = 3, 4
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 151 10.4.2 operation as 16-bit timer counter timer 30 and timer 40 can be used as a 16-bit timer counter using cascade connection. in this case, 8-bit timer counter 30 (tm30) is the higher 8 bits and 8-bit timer counter 40 (tm40) is the lower 8 bits. 8-bit timer 40 controls reset and clear. the following modes can be used for the 16-bit timer counter. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square-wave output with 16-bit resolution (1) operation as interval timer with 16-bit resolution the interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register 30 (cr30) and 8-bit compare register 40 (cr40). to operate as an interval timer with 16-bit resoluti on, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter 30 (tm 30) and 8-bit timer counter 40 (tm40) (tce30 = 0, tce40 = 0). <2> disable timer output of to40 (toe40 = 0). <3> set the count clock for timer 40 (see tables 10-5 and 10-6). <4> set the operation mode of timer 30 and 8-bit time r 40 to 16-bit timer counter mode (see figures 10-4 and 10-5). <5> set a count value in cr30 and cr40. <6> enable the operation of tm30 and tm40 (tce40 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce40 (the value of tce30 is invalid). when the count values of tm30 and tm40 match the values set in cr30 and cr40 respectively, both tm30 and tm40 are simultaneously cleared to 00h and counting continues. at the same time, an interrupt request signal (inttm40) is generated (i nttm30 is not generated). tables 10-11 and 10-12 show interval time, and figure 10-16 shows the timing of the interval timer operation. cautions 1. be sure to stop the timer operation before overwriting th e count clock with different data. 2. in the 16-bit timer counter mode, to30 cannot be used. be sure to set toe30 = 0 to disable to30 output.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 152 table 10-11. interval time with 16-bit resolution (during f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum interval time maximum interval time resolution 0 0 0 2 3 /f x (1.6 s) 2 19 /f x (0.10 s) 2 3 /f x (1.6 s) 0 0 1 2 7 /f x (25.6 s) 2 23 /f x (1.68 s) 2 7 /f x (25.6 s) 0 1 0 f tmi input cycle f tmi input cycle 2 16 f tmi input cycle 0 1 1 f tmi /2 input cycle f tmi /2 input cycle 2 16 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 16 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 16 f tmi /2 3 input cycle remark f x : main system clock oscillation frequency (ceramic/crystal oscillation) table 10-12. interval time with 16-bit resolution (during f cc = 4.0 mhz operation) tcl402 tcl401 tcl400 minimum interval time maximum interval time resolution 0 0 0 2 3 /f cc (2.0 s) 2 19 /f cc (0.13 s) 2 3 /f cc (2.0 s) 0 0 1 2 7 /f cc (32 s) 2 23 /f cc (2.10 s) 2 7 /f cc (32 s) 0 1 0 f tmi input cycle f tmi input cycle 2 16 f tmi input cycle 0 1 1 f tmi /2 input cycle f tmi /2 input cycle 2 16 f tmi /2 input cycle 1 0 0 f tmi /2 2 input cycle f tmi /2 2 input cycle 2 16 f tmi /2 2 input cycle 1 0 1 f tmi /2 3 input cycle f tmi /2 3 input cycle 2 16 f tmi /2 3 input cycle remark f cc : main system clock oscillation frequency (rc oscillation)
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 153 interval time count clock tm40 cr40 tce40 inttm40 to40 ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm30 tm40 count clock tm30 00h x x ? 1 01h cr30 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h t not cleared because tm30 does not match cleared because tm30 and tm40 match simultaneously count start interrupt not generated because tm30 does not match interrupt acknowledgement interrupt acknowledgement remark interval time = (256x + n + 1) t: x = 00h to ffh, n = 00h to ffh figure 10-16. timing of interval ti mer operation with 16-bit resolution
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 154 (2) operation as external event counter with 16-bit resolution the external event counter counts t he number of external clock pulses input to the tmi40/p31/intp1/to30 pin by tm30 and tm40. to operate as an external event c ounter with 16-bit resolution, setti ngs must be made in the following sequence. <1> disable operation of tm30 and tm40 (tce30 = 0, tce40 = 0). <2> disable timer output of to40 (toe40 = 0). <3> set p31 to input mode (pm31 = 1). <4> select the external input clo ck for timer 40 (see tables 10-5 and 10-6). <5> set the operation mode of timer 30 and 8-bit time r 40 to 16-bit timer counter mode (see figures 10-4 and 10-5). <6> set a count value in cr30 and cr40. <7> enable the operation of tm30 and tm40 (tce40 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce40 (the value of tce30 is invalid). each time the valid edge is input, the values of tm30 and tm40 are incremented. when the count values of tm30 and tm40 simult aneously match the values set in cr30 and cr40 respectively, both tm30 and tm40 are cleared to 00h and c ounting continues. at the same time, an interrupt request signal (inttm40) is generat ed (inttm30 is not generated). figure 10-17 shows the timing of the external event counter operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 155 tmi40 pin input tm40 cr40 tce40 inttm40 ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm30 count clock tm30 00h x 01h cr30 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h x ? 1 not cleared because tm30 does not match cleared because tm30 and tm40 match simultaneously count start interrupt not generated because tm30 does not match interrupt acknowledgement interrupt acknowledgement remark x = 00h to ffh, n = 00h to ffh figure 10-17. timing of external event counter operation with 16-bit resolution
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 156 (3) operation as square-wave output with 16-bit resolution square waves of any frequency can be out put at an interval specified by the count value preset in cr30 and cr40. to operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1> disable operation of tm30 and tm40 (tce30 = 0, tce40 = 0). <2> disable output of to30 and to40 (toe30 = 0, toe40 = 0). <3> set a count clock for timer 40. <4> set p32 to output mode (pm32 = 0) and p32 out put latch to 0 and enable to40 output (toe40 = 1) (to30 cannot be used). <5> set count values in cr30 and cr40. <6> enable the operati on of tm40 (tce40 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce40 (the value of tce30 is invalid). when the count values of tm30 and tm40 simult aneously match the values set in cr30 and cr40 respectively, the to40 pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match o ccurs, tm30 and tm40 are cleared to 00h and counting continues. at the same time, an interrupt request si gnal (inttm40) is generated (inttm30 is not generated). the square-wave output is cleared to 0 by setting tce40 to 0. tables 10-13 and 10-14 show the squar e wave output range, and figure 10- 18 shows timing of square wave output. cautions 1. be sure to stop the timer operation before overwriting the count clock with different data. 2. in the 16-bit timer counter mode, to30 ca nnot be used. be sure to set toe30 = 0 to disable to30 output. table 10-13. square-wave output ra nge with 16-bit resolution (during f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum pulse width maximum pulse width resolution 0 0 0 2 3 /f x (1.6 s) 2 19 /f x (0.10 s) 2 3 /f x (1.6 s) 0 0 1 2 7 /f x (25.6 s) 2 23 /f x (1.68 s) 2 7 /f x (25.6 s) remark f x : main system clock oscillation frequency (ceramic/crystal oscillation) table 10-14. square-wave output ra nge with 16-bit resolution (during f cc = 4.0 mhz operation) tcl402 tcl401 tcl400 minimum pulse width maximum pulse width resolution 0 0 0 2 3 /f cc (2.0 s) 2 19 /f cc (0.13 s) 2 3 /f cc (2.0 s) 0 0 1 2 7 /f cc (32 s) 2 23 /f cc (2.10 s) 2 7 /f cc (32 s) remark f cc : main system clock oscillation frequency (rc oscillation)
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 157 count clock count value cr40 tce40 inttm40 to40 note ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n count clock tm40 tm40 count value tm30 tm30 00h x x ? 1 01h cr30 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h not cleared because tm30 does not match cleared because tm30 and tm40 match simultaneously count start interrupt not generated because tm30 does not match interrupt acknowledgement interrupt acknowledgement figure 10-18. timing of square-wave output with 16-bit resolution note the initial value of to40 is low level when output is enabled (toe40 = 1). remark x = 00h to ffh, n = 00h to ffh
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 158 10.4.3 operation as carrier generator an arbitrary carrier clock generated by tm 40 can be output in the cycle set in tm30. to operate timer 30 and timer 40 as carrier generators, settings must be made in the following sequence. <1> disable operation of tm30 and tm40 (tce30 = 0, tce40 = 0). <2> disable timer output of to30 and to40 (toe30 = 0, toe40 = 0). <3> set count values in cr30, cr40, and crh40. <4> set the operation mode of timer 30 and timer 40 to carrier generator mode (see figures 10-4 and 10-5). <5> set the count clock for timer 30 and timer 40. <6> set remote control output to carrier pulse (rmc40 (bit 2 of carrier generator output control register 40 (tca40)) = 0). input the required value to nrzb 40 (bit 1 of tca40) by program. input a value to nrz40 (bit 0 of tca 40) before it is reloaded from nrzb40. <7> set p32 to output mode (pm32 = 0) and the p32 output latch to 0 and enable to40 output by setting toe40 to 1. <8> enable the operation of tm30 and tm40 (tce30 = 1, tce40 = 1). <9> save the value of nrzb40 to a general-purpose register. <10> when inttm30 rises, the value of nrzb40 is transfe rred to nrz40. after that, rewrite tca40 with an 8-bit memory manipulation instruction. i nput the value to be transferred to nrz40 next time to nrzb40, and input the value saved in <9> to nrz40. <11> generate the desired carrier signal by repeating <9> and <10>. the operation of the carrier generator is as follows. <1> when the count value of tm40 ma tches the value set in cr40, an in terrupt request signal (inttm40) is generated and output of timer 40 is in verted, which makes the compare register switch from cr40 to crh40. <2> after that, when the count value of tm40 matches the value set in crh40, an interrupt request signal (inttm40) is generated and output of ti mer 40 is inverted again, which make s the compare register switch from crh40 to cr40. <3> the carrier clock is generated by repeating <1> and <2> above. <4> when the count value of tm30 ma tches the value set in cr30, an in terrupt request signal (inttm30) is generated. the rising edge of inttm30 is the data reload signal of nrz b40 and is transferred to nrz40. <5> when nrz40 is 1, a carrier cl ock is output from to40 pin. cautions 1. tca40 cannot be set with a 1-bit memory manipulation instruction. be sure to use an 8-bit memory manipulation instruction. 2. the nrz40 flag can be rewritten only when the carrier generator output is stopped (toe40 = 0). the data of the flag is not changed even if a write instruction is executed while toe40 = 1. 3. when setting the carrier generator opera tion again after stopping it once, reset nrzb40 because the previous value is not retained. in this case also a 1-bi t memory manipulation instruction cannot be used. be sure to use an 8-bit memory manipulation instruction.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 159 cautions 4. to enable operation in the carrier generator mode, set a value to the co mpare registers (cr30, cr40, and crh40), and input the necessar y value to the nrzb 40 and nrz40 flags in advance. otherwise, the signa l of the timer match circui t will become unstable and the nrz40 flag will be undefined. 5. while inttm30 (interrupt generated by the match signal of timer 30) is being output, accessing tca40 is prohibited. accessing tca40 is prohibited while 8-bi t timer counter 30 (tm30) is 00h. to access tca40 while tm30 = 00h, wait for mo re than half a period of the tm30 count clock and then rewrite tca40.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 160 figures 10-19 to 10-21 show the operat ion timing of the carrier generator. figure 10-19. timing of carrier generato r operation (when cr40 = n, crh40 = m (m > n)) tm40 count clock tm40 count value cr40 tce40 inttm40 m 00h n 00h 01h n crh40 m n 00h carrier clock n 00h 00h n m 00h 01h x 00h 01h x 00h 01h x 00h x 00h 01h tm30 count value cr30 tce30 inttm30 tm30 count clock 0 1 0 10 0 1 01 0 nrzb40 nrz40 to40 carrier clock x count start clear clear clear clear
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 161 figure 10-20. timing of carrier generator operation (when cr40 = n, crh40 = m (m < n)) tm40 count clock tm40 count value cr40 tce40 inttm40 n 00h n crh40 m carrier clock n 00h 00h 01h x 00h 01h x 00h 01h x 00h x 00h 01h tm30 count value cr30 tce30 inttm30 tm30 count clock 0 1 0 10 0 1 01 0 nrzb40 nrz40 to40 carrier clock m 00h m m 00h m 00h x count start clear clear clear clear remark this timing chart shows an example in which the value of nrz40 is changed while the carrier clock is high.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 162 figure 10-21. timing of carrier genera tor operation (when cr40 = crh40 = n) count clock tm40 count value cr40 tm40 tm30 tce40 inttm40 n 00h 00h 00h n x crh40 n n carrier clock 00h 00h n n 00h 01h x 00h 01h x 00h 01h x 00h x 00h 01h tm30 cr30 tce30 inttm30 count clock 0 1 0 10 0 1 01 0 nrzb40 nrz40 to40 carrier clock n n 00h clear clear clear clear clear count start
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 163 10.4.4 operation as pwm output (timer 40 only) in the pwm output mode, a pulse of any duty ratio can be output by setting a low-level width using cr40 and a high-level width using crh40. to operate timer 40 in pwm output mode, setti ngs must be made in the following sequence. <1> disable operation of tm40 (tce40 = 0). <2> disable timer output of to40 (toe40 = 0). <3> set count values in cr40 and crh40. <4> set the operation mode of timer 40 to carrier generator mode (see figure 10-5). <5> set the count clock for timer 40. <6> set p32 to output mode (pm32 = 0) and the p32 out put latch to 0 and enable time r output of to40 (toe40 = 1). <7> enable the operation of tm40 (tce40 = 1). the operation in the pwm out put mode is as follows. <1> when the count value of tm40 ma tches the value set in cr40, an in terrupt request signal (inttm40) is generated and output of timer 40 is in verted, which makes the compare register switch from cr40 to crh40. <2> a match between tm40 and cr40 clears the tm40 value to 00h and then counting starts again. <3> after that, when the count value of tm40 matches the value set in crh40, an interrupt request signal (inttm40) is generated and output of ti mer 40 is inverted again, which make s the compare register switch from crh40 to cr40. <4> a match between tm40 and crh40 clears the tm40 va lue to 00h and then counting starts again. a pulse of any duty ratio is output by repeating <1> to <4> above. fi gures 10-22 and 10-23 s how the operation timing in the pwm output mode.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 164 figure 10-22. pwm output mode timing (basic operation) count clock tm40 count value cr40 tce40 tm40 inttm40 00h n 00h 01h n crh40 m n to40 note 00h 00h 01h m 01h 01h m 00h clear clear clear clear count start note the initial value of to40 is low level when output is enabled (toe40 = 1). figure 10-23. pwm output mode timing (when cr40 and crh40 are overwritten) count clock tm40 count value cr40 tce40 tm40 inttm40 00h n 00h 01h n crh40 m n to40 note m x y 00h 00h x 00h x ym clear clear clear clear count start note the initial value of to40 is low level when output is enabled (toe40 = 1).
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 165 10.5 notes on using 8-bit timer 30, 40 (1) error on starting timer an error of up to 1.5 clocks is included in the time between when the timer is st arted and a match signal is generated. this is because the counter may be increment ed by detecting a rising edge at the timing at which the timer starts while the count clock is high level (see figure 10-24 ). figure 10-24. case in which erro r of 1.5 clocks (max.) occurs tcen0 tcen0 00h 01h 02h 03h if delay a > delay b when the timer starts while the selected clock is high level, an error of 1.5 clocks (max.) occurs. tmn0 count value count pulse clear signal selected clock clear signal 8-bit timer counter n0 (tmn0) count pulse delay a delay a delay b delay b selected clock remark n = 3, 4 (2) count value if external clock input from tmi40 pin is selected when the external clock signal input fr om the tmi40 pin is selected as t he count clock, the count value may start from 01h if the timer is enabled (tce40 = 0 1) while the tmi40 pin is high. this is because the input signal of the tmi40 pin is interna lly anded with the tce40 signal. c onsequently, the counter is incremented because the rising edge of the count cl ock is input to the timer immediately when the tce40 pin is set. depending on the delay timing, the count value is incr emented by one if the risi ng edge is input after the counter is cleared. counting is not affected if the rising edge is input before the counter is cleared (the counter operates normally). use the timer being aware that it has an error of one count, or take either of the following actions a or b. always start the ti mer when the tmi40 pin is low. save the count value to a control register when the timer is started, s ubtract the count value from the count value saved to the c ontrol register when reading the c ount value, and take the result as the true count value.
chapter 10 8-bit timer30, 40 user?s manual u14800ej2v0ud 166 figure 10-25. counting operation if ti mer is started when tmi40 is high tce40 flag tmi40 h rising edge detector counter clear increment remark n = 0, 1 (3) setting of 8-bit compare register n0 8-bit compare register n0 (crn0) can be cleared to 00h. therefore, one pulse can be c ounted when the 8-bit timer oper ates as an event counter. figure 10-26. timing of operation as exte rnal event counter (8-bit resolution) tmi40 input cr40 00h tm40 count value 00h 00h 00h 00h interrupt request flag remark n = 3, 4
user?s manual u14800ej2v0ud 167 chapter 11 watch timer 11.1 watch timer functions the watch timer has the following functions. watch timer interval timer the watch and interval timers can be used at the same time. figure 11-1 is a block diagram of the watch timer. figure 11-1. watch timer block diagram f clk /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selecter clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) internal bus selecter remark f clk : f x or f cc
chapter 11 watch timer 168 user?s manual u14800ej2v0ud (1) watch timer the 4.19 mhz main system clock or 32.768 khz subsyst em clock is used to generate an interrupt request (intwt) at 0.5-second intervals. caution when the main system clock is operating at 5.0 mhz (ceramic/crystal oscillation) or 4.0 mhz (rc oscillation), it cannot be used to genera te a 0.5-second interval. in this case, the subsystem clock, which operates at 32.768 khz, should be used instead. (2) interval timer the interval timer is used to generate an interr upt request (intwt) at specified intervals. table 11-1. interval time of inter val timer (ceramic/crystal oscillation) interval during f x = 5.0 mhz operation during f x = 4.19 mhz operation during f xt = 32.768 khz operation 2 4 1/f w 409.6 s 488 s 488 s 2 5 1/f w 819.2 s 977 s 977 s 2 6 1/f w 1.64 ms 1.95 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.81 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 3. f xt : subsystem clock oscillation frequency table 11-2. interval time of interval timer (rc oscillation) interval during f cc = 4.0 mhz operation during f xt = 32.768 khz operation 2 4 1/f w 512 s 488 s 2 5 1/f w 1.02 ms 977 s 2 6 1/f w 2.05 ms 1.95 ms 2 7 1/f w 4.10 ms 3.91 ms 2 8 1/f w 8.19 ms 7.81 ms 2 9 1/f w 16.4 ms 15.6 ms remarks 1. f w : watch timer clock frequency (f cc /2 7 or f xt ) 2. f cc : main system clock oscillation frequency (rc oscillation) 3. f xt : subsystem clock oscillation frequency
chapter 11 watch timer user?s manual u14800ej2v0ud 169 11.2 watch timer configuration the watch timer includes the following hardware. table 11-3. watch timer configuration item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm)
chapter 11 watch timer user?s manual u14800ej2v0ud 170 11.3 register controlling watch timer the watch timer mode control register (wt m) is used to control the watch timer. watch timer mode control register (wtm) wtm selects a count clock for the watch timer and specif ies whether to enable clocking of the timer. it also specifies the prescaler interval and how the 5-bit counter is controlled. wtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wtm to 00h. figure 11-2. format of watch timer mode control register watch timer count clock selection during f x = 5.0 mhz, f xt = 32.768 khz operation during f cc = 4.0 mhz, f xt = 32.768 khz operation wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm symbol address after reset r/w ff4ah 00h r/w 765432<1><0> wtm7 0 1 prescaler interval selection wtm6 0 0 0 0 1 1 2 4 /f w 2 5 /f w 2 6 /f w 2 7 /f w 2 8 /f w 2 9 /f w wtm5 0 0 1 1 0 0 wtm4 0 1 0 1 0 1 control of 5-bit counter operation wtm1 0 1 cleared after stop started watch timer operation wtm0 0 1 operation stopped (both prescaler and timer cleared) operation enabled other than above f x /2 7 f xt (39.1 khz) (32.768 khz) f cc /2 7 (31.3 khz) setting prohibited remarks 1. f w : watch timer clock frequency (f x /2 7 , f cc /2 7 , or f xt ) 2. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 3. f cc : main system clock oscillation frequency (rc oscillation) 4. f xt : subsystem clock oscillation frequency
chapter 11 watch timer user?s manual u14800ej2v0ud 171 11.4 watch timer operation 11.4.1 operation as watch timer the main system clock (4.19 mhz) or subsystem clock (32.768 khz) is used as a watch timer which generates 0.5-second intervals. the watch timer is used to generate an inte rrupt request at specified intervals. by setting bits 0 and 1 (wtm0 and wtm1) of the watch time r mode control register (wtm) to 1, the watch timer starts counting. by setting them to 0, the 5-bit counter is cleared and the watc h timer stops counting. when the interval timer also operates at the same time , only the watch timer can be started from 0 seconds by setting wtm1 to 0. however, an error of up to 2 9 1/f w seconds may occur for the first overflow of the watch timer (intwt) after a 0-second start because the 9-bi t prescaler is not cleared in this case. 11.4.2 operation as interval timer the interval timer is used to repeatedly generate an interrupt request at the interval s pecified by a preset count value. the interval time can be selected by bits 4 to 6 (wtm4 to wtm6) of the watch timer m ode control register (wtm). table 11-4. interval time of inter val timer (ceramic/crystal oscillation) interval during f x = 5.0 mhz operation during f x = 4.19 mhz operation during f xt = 32.768 khz operation 2 4 1/f w 409.6 s 488 s 488 s 2 5 1/f w 819.2 s 977 s 977 s 2 6 1/f w 1.64 ms 1.95 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.81 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 3. f xt : subsystem clock oscillation frequency table 11-5. interval time of interval timer (rc oscillation) interval during f cc = 4.0 mhz operation during f xt = 32.768 khz operation 2 4 1/f w 512 s 488 s 2 5 1/f w 1.02 ms 977 s 2 6 1/f w 2.05 ms 1.95 ms 2 7 1/f w 4.10 ms 3.91 ms 2 8 1/f w 8.19 ms 7.81 ms 2 9 1/f w 16.4 ms 15.6 ms remarks 1. f w : watch timer clock frequency (f cc /2 7 or f xt ) 2. f cc : main system clock oscillation frequency (rc oscillation) 3. f xt : subsystem clock oscillation frequency
chapter 11 watch timer user?s manual u14800ej2v0ud 172 figure 11-3. watch timer/inte rval timer operation timing 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti watch timer interrupt time (0.5 s) watch timer interrupt time (0.5 s) interval timer (t) t caution when operation of the watc h timer and 5-bit counter has b een enabled by setting the watch timer mode control register (wt m) (setting wtm0 (bit 0 of wtm) to 1), the time until the first interrupt request after this se tting will not be exactly the same as the time set by watch timer interrupt time (0.5 s). this is because the 5- bit counter starts counting one cycle after the output of the 9-bit prescaler. the intwt signal will be generated at the set time from its second generation. remarks 1. f w : watch timer clock frequency 2. the parenthesized values apply to operation at f w = 32.768 khz.
user?s manual u14800ej2v0ud 173 chapter 12 watchdog timer 12.1 watchdog timer functions the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect program runaway . when the runaway is detected, a non-maskable interrupt or the reset signal can be generated. table 12-1. runaway detect ion time of watchdog timer runaway detection time during f x = 5.0 mhz operation during f cc = 4.0 mhz operation 2 11 1/f clk 2 11 /f x (410 s) 2 11 /f cc (512 s) 2 13 1/f clk 2 13 /f x (1.64 ms) 2 13 /f cc (2.05 ms) 2 15 1/f clk 2 15 /f x (6.55 ms) 2 15 /f cc (8.19 ms) 2 17 1/f clk 2 17 /f x (26.2 ms) 2 17 /f cc (32.8 ms) remarks 1. f clk : f x or f cc 2. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 3. f cc : main system clock oscillation frequency (rc oscillation) (2) interval timer the interval timer generates an inte rrupt at any preset intervals. table 12-2. interval time of watchdog timer interval time during f x = 5.0 mhz operation during f cc = 4.0 mhz operation 2 11 1/f clk 2 11 /f x (410 s) 2 11 /f cc (512 s) 2 13 1/f clk 2 13 /f x (1.64 ms) 2 13 /f cc (2.05 ms) 2 15 1/f clk 2 15 /f x (6.55 ms) 2 15 /f cc (8.19 ms) 2 17 1/f clk 2 17 /f x (26.2 ms) 2 17 /f cc (32.8 ms) remarks 1. f clk : f x or f cc 2. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 3. f cc : main system clock oscillation frequency (rc oscillation)
chapter 12 watchdog timer user?s manual u14800ej2v0ud 174 12.2 watchdog timer configuration the watchdog timer includes the following hardware. table 12-3. watchdog timer configuration item configuration control registers watchdog timer cl ock select register (wdcs) watchdog timer mode register (wdtm) figure 12-1. watchdog timer block diagram internal bus internal bus prescaler selector controller f clk 2 6 f clk 2 8 f clk 2 10 3 7-bit counter clear wdtif wdtmk wdcs2 wdcs1 wdcs0 watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) wdtm4 run wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f clk 2 4 remark f clk : f x or f cc
chapter 12 watchdog timer user?s manual u14800ej2v0ud 175 12.3 registers controlling watchdog timer the following two registers are used to control the watchdog timer. ? watchdog timer clock select register (wdcs) ? watchdog timer mode register (wdtm) (1) watchdog timer clock select register (wdcs) this register sets the watchdog timer count clock. wdcs is set with an 8-bit memo ry manipulation instruction. reset input clears wdcs to 00h. figure 12-2. format of watchdog timer clock select register wdcs2 0 0 1 1 00000 wdcs2 wdcs1 0 wdcs r/w r/w 76543210 wdcs1 0 1 0 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 setting prohibited symbol address ff42h 00h after reset other than above during f x = 5.0 mhz operation count clock selection during f cc = 4.0 mhz operation (313 khz) (78.1 khz) (19.5 khz) (4.88 khz) f cc /2 4 f cc /2 6 f cc /2 8 f cc /2 10 (250 khz) (62.5 khz) (15.6 khz) (3.91 khz) remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation)
chapter 12 watchdog timer user?s manual u14800ej2v0ud 176 (2) watchdog timer mode register (wdtm) this register sets an operation mode of the watchdog timer, and enables /disables counting of the watchdog timer. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 12-3. format of watc hdog timer mode register run 0 1 selection of operation of watchdog timer note 1 run 0 0 wdtm4 wdtm3 000 wdtm symbol address after reset r/w fff9h 00h r/w <7>6543210 stops counting clears counter and starts counting wdtm4 selection of operation mode of watchdog timer note 2 wdtm3 0 1 1 0 1 1 operation stopped interval timer mode (when overflow occurs, a maskable interrupt occur) note 3 watchdog timer mode 1 (when overflow occurs, a non-maskable interrupt occurs) watchdog timer mode 2 (when overflow occurs, reset operation starts) 0 0 notes 1. once run has been set (1), it cannot be cleared (0) by software. therefore, w hen counting is started, it cannot be stopped by any m eans other than reset input. 2. once wdtm3 and wdtm4 have been set (1), they cannot be cleared (0) by software. 3. the watchdog timer starts operations as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by setting run to 1, th e actual overflow time is up to 0.8% shorter than the time set by the watchdog timer clock select register (wdcs). 2. in watchdog timer mode 1 or 2, set wdtm4 to 1 after confirming that the wdtif (bit 0 of interrupt request flag register 0 (if0)) is set to 0. while wdtif is 1, a non-maskable interrupt is generated upon write comp letion if watchdog timer m ode 1 or 2 is selected.
chapter 12 watchdog timer user?s manual u14800ej2v0ud 177 12.4 watchdog timer operation 12.4.1 operation as watchdog timer the watchdog timer detects a program runaway when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs ). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 within the set runaway detection time interval after the watchdog timer has been started. by setting run to 1, the watchdog timer can be cleared and star t counting. if run is not set to 1, and the runaway detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in the halt mode, but stops in the st op mode. therefore, set run to 1 before entering the stop mode to clear the watchdog timer, and then ex ecute the stop instruction. cautions 1. the actual runaway detection time may be up to 0. 8% shorter than the set time. 2. when the subsystem clock is selected as th e cpu clock, the watchdog timer stops counting. in this case, therefore, the watchdog time r stops operation even though the main system clock is oscillating. table 12-4. runaway detect ion time of watchdog timer wdcs2 wdcs1 during f x = 5.0 mhz operation during f cc = 4.0 mhz operation 0 0 2 11 /f x (410 s) 2 11 /f cc (512 s) 0 1 2 13 /f x (1.64 ms) 2 13 /f cc (2.05 ms) 1 0 2 15 /f x (6.55 ms) 2 15 /f cc (8.19 ms) 1 1 2 17 /f x (26.2 ms) 2 17 /f cc (32.8 ms) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation)
chapter 12 watchdog timer user?s manual u14800ej2v0ud 178 12.4.2 operation as interval timer when bit 4 (wdtm4) and bit 3 (wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer also operates as an interv al timer that repeatedly generat es an interrupt at time intervals specified by a preset count value. select a count clock (or interval time) by setting bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). the watchdog timer star ts operation as an interval timer when t he run bit (bit 7 of wdtm) is set to 1. in the interval timer mode, the interrupt mask flag (w dtmk) is valid, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in the halt mode, but st ops in the stop mode. therefore, set run to 1 before entering the stop mode to cl ear the interval timer, and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set , unless the reset signal is input. 2. the interval time immediat ely after the setting by wdtm may be up to 0.8% shorter than the set time. table 12-5. interval time of watchdog timer wdcs2 wdcs1 during f x = 5.0 mhz operation during f cc = 4.0 mhz operation 0 0 2 11 /f x (410 s) 2 11 /f cc (512 s) 0 1 2 13 /f x (1.64 ms) 2 13 /f cc (2.05 ms) 1 0 2 15 /f x (6.55 ms) 2 15 /f cc (8.19 ms) 1 1 2 17 /f x (26.2 ms) 2 17 /f cc (32.8 ms) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation)
user?s manual u14800ej2v0ud 179 chapter 13 serial interface 10 13.1 serial interface 10 functions serial interface 10 has the following two modes. ? operation stop mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not carri ed out. it enables a reduction in power consumption. (2) 3-wire serial i/o mode (ms b/lsb-first switchable) in this mode, 8-bit data transfer is carried out-first with three lines, one for the serial clock (sck10) and two for serial data (si10 and so10). the 3-wire serial i/o mode supports simultaneous trans mit and receive operations, reducing data transfer processing time. it is possible to switch the start bit of 8-bit dat a to be transmitted between t he msb and the lsb, thus allowing connection to devices with either start bit. the 3-wire serial i/o mode is effective for connecting di splay controllers and peripheral i/o such as the 75xl series, 78k series, and 17k series, which have inte rnal conventional clocked serial interfaces.
chapter 13 serial interface 10 180 user?s manual u14800ej2v0ud 13.2 serial interface 10 configuration serial interface 10 includes the following hardware. table 13-1. configuration of serial interface 10 item configuration register serial shi ft register 10 (sio10) control register serial operation mode register 10 (csim10) port mode register 2 (pm2) port 2 (p2) (1) serial shift register 10 (sio10) this is an 8-bit register used for parallel- to-serial conversion and to perform serial data transmission/reception in synchronization with serial clocks. sio10 is set with an 8-bit memo ry manipulation instruction. reset input makes sio10 undefined.
chapter 13 serial interface 10 user?s manual u14800ej2v0ud 181 internal bus si10/p22 serial operation mode register 10 (csim10) csie10 tps101 tps100 dir10 csck10 serial shift register 10 (sio10) so10/p21 pm21 pm20 sck10/p20 serial clock counter interrupt request generator clock controller selector selector intcsi10 f/f f clk /2 2 f clk /2 3 f clk /2 4 f clk /2 5 output latch (p20) output latch (p21) 2 remark f clk : f x or f cc figure 13-1. block diagra m of serial interface 10
chapter 13 serial interface 10 user?s manual u14800ej2v0ud 182 13.3 register controlling serial interface 10 the following three registers are used to control serial interface 10. ? serial operation mode register 10 (csim10) ? port mode register 2 (pm2) ? port 2 (p2) (1) serial operation mode register 10 (csim10) this register is used to control serial inte rface 10 and set the serial clock and start bit. csim10 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim10 to 00h. figure 13-2. format of serial operation mode register 10 csie10 0 1 operation control in 3-wire serial i/o mode csie10 0 tps101 tps100 0 dir10 csck10 0 csim10 symbol address after reset r/w ff78h 00h r/w <7>6543210 operation stopped operation enabled dir10 0 1 start bit specification msb lsb csck10 0 1 sio10 clock selection input clock to sck10 pin from external internal clock selected by tps100, tps101 during f x = 5.0 mhz operation during f cc = 4.0 mhz operation tps101 0 0 tps100 0 1f x /2 3 (625 khz) f x /2 2 (1.25 mhz) f x /2 4 (313 khz) f x /2 5 (156 khz) f cc /2 3 (500 khz) f cc /2 2 (1.0 mhz) f cc /2 4 (250 khz) f cc /2 5 (125 khz) 1 1 0 1 count clock selection when internal clock is selected cautions 1. bits 0, 3, and 6 must be set to 0. 2. switch operation mode after stoppi ng the serial transmit/receive operation. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation)
chapter 13 serial interface 10 user?s manual u14800ej2v0ud 183 table 13-2. settings of serial interface 10 operating mode (1) operation stop mode csim10 pm22 p22 pm21 p21 pm20 p20 start shift p22/si10 p21/so10 p20/sck10 csie10 dir10 csck10 bit clock pin function pin func tion pin function 0 note 1 note 1 note 1 note 1 note 1 note 1 ? ? p22 p21 p20 other than above setting prohibited (2) 3-wire serial i/o mode csim10 pm22 p22 pm21 p21 pm20 p20 start shift p22/si10 p21/so10 p20/sck10 csie10 dir10 csck10 bit clock pin function pin func tion pin function 1 0 0 1 note 2 note 2 0 1 1 msb external clock si10 note 2 so10 (cmos output) sck10 input 1 0 1 internal clock sck10 output 1 1 0 1 lsb external clock sck10 input 1 0 1 internal clock sck10 output other than above setting prohibited notes 1. can be used as port function. 2. if used only for transmission, can be used as p22 (cmos i/o). remark : don?t care
chapter 13 serial interface 10 user?s manual u14800ej2v0ud 184 13.4 serial interface 10 operation serial interface 10 provides the following two types of modes. ? operation stop mode ? 3-wire serial i/o mode 13.4.1 operation stop mode in the operation stop mode, serial transfer is not execut ed, therefore enabling a reduction in the power consumption. the p20/sck10, p21/so10, and p22/si10 pins can be used as normal i/o ports. (1) register setting operation stop mode is set by serial operation mode register 10 (csim10). serial operation mode register 10 (csim10) csim10 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim10 to 00h. csie10 0 1 operation control in 3-wire serial i/o mode csie10 0 tps101 tps100 0 dir10 csck10 0 csim10 symbol address after reset r/w ff78h 00h r/w <7>6543210 operation stopped operation enabled caution bits 0, 3, and 6 must be set to 0.
chapter 13 serial interface 10 user?s manual u14800ej2v0ud 185 13.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful fo r connection of peripheral i/o and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75x/xl series, 78k series, 17k series. communication is performed using three lines: a serial clock line (sck10), serial output line (so10), and serial input line (si10). (1) register setting 3-wire serial i/o mode settings are performed using se rial operation mode regist er 10 (csim10), port mode register 2 (pm2), and port 2 (p2). (a) serial operation mode register 10 (csim10) csim10 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim10 to 00h. csie10 0 1 operation control in 3-wire serial i/o mode csie10 0 tps101 tps100 0 dir10 csck10 0 csim10 symbol address after reset r/w ff78h 00h r/w <7>6543210 operation stopped operation enabled dir10 0 1 start bit specification msb lsb csck10 0 1 sio10 clock selection input clock to sck10 pin from external internal clock selected by tps100, tps101 during f x = 5.0 mhz operation during f cc = 4.0 mhz operation tps101 0 0 tps100 0 1f x /2 3 (625 khz) f x /2 2 (1.25 mhz) f x /2 4 (313 khz) f x /2 5 (156 khz) f cc /2 3 (500 khz) f cc /2 2 (1.0 mhz) f cc /2 4 (250 khz) f cc /2 5 (125 khz) 1 1 0 1 count clock selection when internal clock is selected cautions 1. bits 0, 3, and 6 must be set to 0. 2. switch operation mode after stoppi ng the serial transmit/receive operation. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation)
chapter 13 serial interface 10 user?s manual u14800ej2v0ud 186 (2) communication operation in the 3-wire serial i/o mode, data transmission/rec eption is performed in 8-bit units. data is transmitted/received bit by bit in syn chronization with the serial clock. transmit shift register 10 (sio10) shift operations are performed in synchronization with the fall of the serial clock (sck10). transmit data is then held in the so10 latch and output from the so 10 pin. also, receive data input to the si10 pin is latched in the i nput bits of sio10 on the rise of sck10. at the end of an 8-bit transfer, t he operation of sio10 stops automatically, and the interrupt request signal (intcsi10) is generated. figure 13-3. 3-wire serial i/o mode timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 end of transfer transfer starts at the falling edge of sck10 sck10 si10 so10 intcsi10 cautions 1. when data is writte n to sio10 in the serial operation disabled status (csie10 = 0), the data cannot be tran smitted or received. 2. when data is written to sio10 in the serial operation disabled status (csie10 = 0) and then serial operation is enabled (csie10 = 1), the data cannot be transmitted or received. 3. once data has been written to sio10 with the serial clock selected (csck10 = 0), overwriting the data does not upda te the contents of sio10. 4. when csim10 is operated during data transmission/reception, data cannot be transmitted or received normally. 5. when sio10 is operate d during data transmission/r eception, the data cannot be transmitted or received normally. (3) transfer start serial transfer is started by setting transfer data to the transmit shift register 10 (sio10) when the following two conditions are satisfied. ? bit 7 (csie10) of serial operat ion mode register 10 (csim10) = 1 ? internal serial clock is stopped or sck10 is a high level after 8-bit serial transfer. termination of 8-bit transfer stops the serial transfe r automatically and generates the interrupt request signal (intcsi10).
user?s manual u14800ej2v0ud 187 chapter 14 serial interface 20 14.1 serial interface 20 functions serial interface 20 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not carried out. it can reduce power consumption. (2) asynchronous serial interface (uart) mode in this mode, one byte of data fo llowing the start bit is transmitted/ received, and full-duplex operation is possible. a dedicated uart baud rate generator is incorporated, allowing comm unication over a wide range of baud rates. in addition, the baud rate can be defined by scaling the input clock to the asck20 pin. caution use the main system clock with ceramic/c rystal oscillation in the uart mode. with rc oscillation, the frequency vari es so much that transmission and reception may be affected when the internal clock is selected for the source clock of the baud rate generator. (3) 3-wire serial i/o mode (ms b/lsb-first switchable) in this mode, 8-bit data transfer is carried out with th ree lines, one for the serial clock (sck20) and two for serial data (si20, so20). the 3-wire serial i/o mode supports simultaneous trans mit and receive operations, reducing data transfer processing time. it is possible to switch the start bit of 8-bit dat a to be transmitted between t he msb and the lsb, thus allowing connection to devices with either start bit. the 3-wire serial i/o mode is effective for connecting di splay controllers and peripheral i/o such as the 75xl series, 78k series, and 17k series, which have inte rnal conventional clocked serial interfaces.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 188 14.2 serial interface 20 configuration serial interface 20 includes the following hardware configuration. table 14-1. configuration of serial interface 20 item configuration registers transmit shift register 20 (txs20) receive shift register 20 (rxs20) receive buffer register 20 (rxb20) control registers serial operat ion mode register 20 (csim20) asynchronous serial interfac e mode register 20 (asim20) asynchronous serial interface status register 20 (asis20) baud rate generator control register 20 (brgc20) port mode register 2 (pm2) port 2 (p2)
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 189 internal bus receive buffer register 20 (rxb20) switching start bit asynchronous serial interface status register 20 (asis20) serial operation mode register 20 (csim20) receive shift register 20 (rxs20) csie20 dir20 csck20 pe20 fe20 ove20 txe20 rxe20 ps201 ps200 cl20 sl20 asynchronous serial interface mode register 20 (asim20) transmit shift register 20 (txs20) transmit shift clock selector csie20 data phases control receive shift clock si20/p25 /rxd20 so20/p24 /txd20 4 parity detection detection of stop bit receive data counter parity operation addition of stop bit transmit data counter sl20, cl20, ps200, ps201 receive enabl receive clock detection clock detection of start bit pm24 csie20 csck20 sck20/p23 /asck20 clock phases control receive detection internal clock output external clock input transmit/receive clock control baud rate generator note 4 tps203 tps202 tps201 tps200 csie20 csck20 f clk /2-f clk /2 8 baud rate generator control register 20 (brgc20) intst20 intsr20/intcsi20 internal bus output latch (p24) output latch (p23) pm23 note for the baud rate generator configuration, see figure 14-2. remark f clk: f x or f cc figure 14-1. block diagra m of serial interface 20
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 190 receive detection clock transmit shift clock receive shift clock receive detection txe20 rxe20 csie20 1/2 1/2 transmit clock counter (3 bits) receive clock counter (3 bits) 4 f clk /2 f clk /2 3 f clk /2 4 f clk /2 5 f clk /2 6 f clk /2 7 f clk /2 8 f clk /2 2 asck20/sck20/p23 tps203 tps202 tps201 tps200 baud rate generator control register 20 (brgc20) remark f clk : f x or f cc selector selector selector internal bus figure 14-2. block diagram of baud rate generator
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 191 (1) transmit shift register 20 (txs20) this register is used to specify data to be transmitted. data written to t xs20 is transmitted as serial data. if the data length is specified as 7 bits , bits 0 to 6 of the data written to txs20 are transferred as the transmit data. the transmit operation is star ted by writing data to txs20. txs20 is written to with an 8-bit memory m anipulation instruction. it cannot be read. reset input sets txs20 to ffh. caution during a transmit operation, do not write to txs20. txs20 and receive buffer register 20 (rxb20) are allocated to the same address, so when reading is performed, rxb20 values are read. (2) receive shift register 20 (rxs20) this register is used to convert serial data input to the rxd20 pin into parallel data. each time one byte of data is received, it is transferred to receive buffer register 20 (rxb20). the rxs20 cannot be manipulat ed directly by program. (3) receive buffer register 20 (rxb20) this register is used to hold received data. each time one byte of data is receiv ed, a new byte of data is transferred from receive shift register 20 (rxs20). if the data length is specified as 7 bi ts, receive data is transferred to bits 0 to 6 of rxb20, and the msb of rxb20 always becomes 0. rxb20 can be read with an 8-bit memory manipulat ion instruction. it cannot be written to. reset input makes rxb20 undefined. caution rxb20 and transmit shift register 20 (txs 20) are allocated to th e same address, so when writing is performed, the val ues are written to txs20. (4) transmit controller this circuit controls transmit operations by adding a star t bit, parity bit, and stop bit to data written to transmit shift register 20 (txs20), according to the data set to asynchronous serial interface mode register 20 (asim20). (5) receive controller this circuit controls receive operations according to the data set to asynchronous serial interface mode register 20 (asim20). it performs also parity error che ck, etc., during receive operations, and when an error is detected, it sets the value to a synchronous serial interface status register 20 (asi s20) depending on the nature of the error.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 192 14.3 registers controlling serial interface 20 the following six registers are used to control serial interface 20. ? serial operation mode register 20 (csim20) ? asynchronous serial interf ace mode register 20 (asim20) ? asynchronous serial interfac e status register 20 (asis20) ? baud rate generator cont rol register 20 (brgc20) ? port mode register 2 (pm2) ? port 2 (p2) (1) serial operation mode register 20 (csim20) this register is set when using serial in terface 20 in the 3-wire serial i/o mode. csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. figure 14-3. format of serial operation mode register 20 csie20 0 1 operation control in 3-wire serial i/o mode csie20 0000 dir20 csck20 0 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation stopped operation enabled dir20 0 1 start bit specification msb lsb csck20 0 1 clock selection in 3-wire serial i/o mode input clock to sck20 pin from external dedicated baud rate generator output cautions 1. bits 0, and 3 to 6 must be set to 0. 2. clear csim20 to 00h in the uart mode. 3. when the external input clo ck is selected in 3-wire serial i/o mode, set input mode by setting bit 3 of port mode register 2 (pm2) to 1. 4. switching operation modes must be perfo rmed after the serial tran smit/receive operation is stopped.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 193 (2) asynchronous serial interface mode register 20 (asim20) this register is set when using the serial interf ace 20 in the asynchronous serial interface mode. asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. figure 14-4. format of asynchronous serial interface mode register 20 txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission parity check is not performed at reception (no parity error is generated) odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification of transmit data 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification cautions 1. bits 0 and 1 must be set to 0. 2. clear asim20 to 00h in the 3-wire serial i/o mode. 3. switching operation modes must be perfo rmed after the serial tran smit/receive operation is stopped.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 194 table 14-2. settings of serial interface 20 operating mode (1) operation stop mode p25/si20/rxd20 p24/so20/txd20 p23/sck20/asck20 p25 p24 p23 asim20 txe20 0 rxe20 0 csie20 0 csim20 dir20 x csck20 x pm25 x note 1 p25 x note 1 pm24 x note 1 p24 x note 1 pm23 x note 1 p23 x note 1 ? ? other than above setting prohibited start bit shift clock pin function pin function pin function (2) 3-wire serial i/o mode msb lsb si20 note 2 so20 (cmos output) sck20 input sck20 output 0 0 1 1 0 1 0 1 0 1 1 note 2 x note 2 0 1 1 0 1 0 x 1 x 1 external clock external clock internal clock internal clock other than above setting prohibited p25/si20/rxd20 p24/so20/txd20 p23/sck20/asck20 asim20 txe20 rxe20 csie20 csim20 dir20 csck20 pm25 p25 pm24 p24 pm23 p23 start bit shift clock pin function pin function pin function sck20 input sck20 output (3) asynchronous serial interface mode p25/si20/rxd20 p24/so20/txd20 p23/sck20/asck20 lsb p25 rxd20 txd20 (cmos output) p24 txd20 (cmos output) asck20 input p23 asck20 input p23 asck20 input p23 asim20 txe20 1 0 1 rxe20 0 1 1 csie20 0 0 0 csim20 dir20 0 0 0 csck20 0 0 0 pm25 x note 1 1 1 p25 x note 1 x x pm24 0 x note 1 0 p24 1 x note 1 1 pm23 1 x note 1 1 x note 1 1 x note 1 p23 x x note 1 x x note 1 x x note 1 other than above start bit shift clock pin function pin function pin function external clock external clock external clock internal clock internal clock internal clock setting prohibited notes 1. can be used as port function. 2. if used only for transmission, can be used as p25 (cmos i/o). remark x: don?t care
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 195 (3) asynchronous serial interface status register 20 (asis20) this register indicates types of error when a recepti on error is generated in the a synchronous interface mode. asis20 is read with a 1-bit or 8-bit memory manipulation instruction. the contents of asis20 become undefined in the 3-wire serial i/o mode. reset input clears asis20 to 00h. figure 14-5. format of asynchronous serial interface status register 20 pe20 0 1 parity error flag 00000 pe20 fe20 ove20 asis20 symbol address after reset r/w ff71h 00h r 76543<2><1><0> parity error not generated parity error generated (when the transmit parity and receive parity did not match) flaming error not generated flaming error generated note 1 (when stop bit is not detected.) overrun error not generated overrun error generated note 2 (when the next receive operation is completed before the data is read from the receive buffer register 20.) fe20 0 1 0 1 flaming error flag overrun error flag ove20 notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim20), the st op bit detection in the case of reception is performed with 1 bit. 2. be sure to read receive buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is received an overrun error occurs.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 196 (4) baud rate generator cont rol register 20 (brgc20) this register is used to set the seri al clock of serial interface 20. brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. figure 14-6. format of baud rate generator control register 20 tps203 0 0 0 0 0 0 0 0 1 tps203 tps202 tps201 tps200 0000 brgc20 r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) f cc /2 f cc /2 2 f cc /2 3 f f cc /2 4 cc /2 5 f cc /2 6 f cc /2 7 f cc /2 8 (2.0 mhz) (1.0 mhz) (500 khz) (250 khz) (125 khz) (62.5 khz) (31.3 khz) (15.6 khz) tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 ? setting prohibited symbol address after reset selection of baud rate generator source clock during f x = 5.0 mhz operation during f cc = 4.0 mhz operation input clock from external to asck20 pin note other than above note only used in the uart mode. cautions 1. when writing to brgc20 is performe d during a communication operation, the output of the baud rate generator is disrupted and communications ca nnot be performed normally. be sure not to write to brgc20 during a communication operation. 2. use the main system clock with ceramic/cr ystal oscillation in the uart mode. with rc oscillation, the frequency vari es so much that transmission and reception may be affected when the internal clock is selected for the source clock of the baud rate generator. 3. be sure not to select n = 1 during operation at f x > 2.5 mhz in uart mode because the resulting baud rate exceeds the rated range. 4. when the external input clo ck is selected in 3-wire serial i/o mode, set input mode by setting bit 3 of port mode register 2 (pm2) to 1. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation) 3. n: value determined in the se ttings of tps200 to tps203 (1 n 8)
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 197 the baud rate transmit/receive clock to be generated is ei ther a signal divided from the system clock, or a signal divided from the clock input from the asck20 pin. (a) generation of uart baud rate transmit/receive clock by means of system clock the transmit/receive clock is generated by dividing the system clock. the baud rate generated from the system clock is estimated by us ing the following expression. [baud rate] = [bps] f x : main system clock oscillation frequency (ceramic/crystal oscillation) n: value in figure 14-6 that is determined by the settings of tps200 to tps203 (2 n 8) table 14-3. example of relationship between system clock and baud rate error (%) baud rate (bps) n brgc00 set value f x = 5.0 mhz f x = 4.9152 mhz 1200 8 70h 2400 7 60h 4800 6 50h 9600 5 40h 19200 4 30h 38400 3 20h 76800 2 10h 1.73 0 caution be sure not to select n = 1 during operation at f x > 2.5 mhz because the resulting baud rate exceeds the rated range. f x 2 n + 1
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 198 (b) generation of uart baud rate transmit/receive clock by means of external clock from asck20 pin the transmit/receive clock is generated by dividing t he clock input from the asck20 pin. the baud rate generated from the clock input from the asck20 pin is estimated by using the following expression. [baud rate] = [bps] f asck : frequency of clock input to the asck20 pin table 14-4. relationship betw een asck20 pin input frequency and baud rate (when brg c20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1200 19.2 2400 38.4 4800 76.8 9600 153.6 19200 307.2 31250 500.0 38400 614.4 (c) generation of serial clock from system clock in 3-wire serial i/o the serial clock is generated by dividing the system clock. the frequency of the serial clock can be obtained by the following expression. if the serial clo ck is externally input to the sck20 pin, it is unnecessary to set brgc20. [serial clock frequency] = [hz] f clk : f x or f cc f x : main system clock oscillation frequency (ceramic/crystal oscillation) f cc : main system clock oscillation frequency (rc oscillation) n: values in figure 14-6 determined by the settings of tps200 to tps203 (1 n 8) f asck 16 f clk 2 n+1
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 199 14.4 serial interface 20 operation serial interface 20 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode 14.4.1 operation stop mode in the operation stop mode, serial transfer is not execut ed, therefore enabling a reduction in the power consumption. the p23/sck20/asck20, p24/so20/txd20, and p25/ si20/rxd20 pins can be used as normal i/o ports. (1) register setting operation stop mode is set by serial operation mode register 20 (csim20) and asynchronous serial interface mode register 20 (asim20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 operation control in 3-wire serial i/o mode csie20 0000 dir20 csck20 0 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation stopped operation enabled caution bits 0 and 3 to 6 must be set to 0.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 200 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 receive operation control caution bits 0 and 1 must be set to 0.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 201 14.4.2 asynchronous serial interface (uart) mode in this mode, the one-byte data follo wing the start bit is transmitted/rece ived and thus full-duplex communications are possible. this device incorporates a uart -dedicated baud rate generator that enables communications at a desired transfer rate from many options. in addition, the baud rate can be also defined by dividing the clock input to the asck20 pin. the uart-dedicated baud rate generator also can output t he 31.25 kbps baud rate whic h complies with the midi standard. caution use the main system clock with ceramic/c rystal oscillation in the uart mode. with rc oscillation, the frequency varies so much that transmission and reception may be affected when the internal clock is select ed for the source clock of the baud rate generator. (1) register setting uart mode is set by serial operat ion mode register 20 (csim20), a synchronous serial interface mode register 20 (asim20), asynchronous serial interface st atus register 20 (asis20) , baud rate generator control register 20 (brgc20), port mode r egister 2 (pm2), and port 2 (p2). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. clear csim20 to 00h in the uart mode. csie20 0 1 operation control in 3-wire serial i/o mode csie20 0000 dir20 csck20 0 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation stopped operation enabled dir20 0 1 start bit specification msb lsb csck20 0 1 clock selection in 3-wire serial i/o mode input clock to sck20 pin from external dedicated baud rate generator output caution 1. bits 0 and 3 to 6 must be set to 0. 2. switching operation modes must be performed after the serial transmit/receive operation is stopped.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 202 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission parity check is not performed at reception (no parity error is generated) odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification cautions 1. bits 0 and 1 must be set to 0. 2. switching operation modes must be performed after the serial transmit/receive operation is stopped.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 203 (c) asynchronous serial interface status register 20 (asis20) asis20 is read with a 1-bit or 8-bit memory manipulation instruction. reset input clears asis20 to 00h. pe20 0 1 parity error flag 00000 pe20 fe20 ove20 asis20 symbol address after reset r/w ff71h 00h r 76543210 parity error not generated parity error generated (when the transmit parity and receive parity did not match) flaming error not generated flaming error generated (when stop bit is not detected.) note 1 overrun error not generated overrun error generated (when the next receive operation is completed before the data is read from the receive buffer register.) note 2 fe20 0 1 0 1 flaming error flag overrun error flag ove20 notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asi m20), the stop bit detection in the case of reception is performed with 1 bit. 2. be sure to read receive buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is received an overrun error occurs.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 204 (d) baud rate generator cont rol register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 1 tps203 tps202 tps201 tps200 0000 brgc20 r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 setting prohibited symbol address after reset selection of baud rate generator source clock input clock to asck20 pin from external note other than above note only used in the uart mode. cautions 1. when writing to brgc20 is pe rformed during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. use the main system clock with ceramic /crystal oscillation in the uart mode. with rc oscillation, the fre quency varies so much that transmission and reception may be affected when the internal clock is selected for the s ource clock of the baud rate generator. 3. be sure not to select n = 1 during operation at f x > 2.5 mhz because the resulting baud rate exceeds the rated range. 4. when external input clo ck is selected, set bit 3 of port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. the parenthesized values apply to operation at f x = 5.0 mhz. 3. n: value determined in the se ttings of tps200 to tps203 (1 n 8)
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 205 the baud rate transmit/receive clock to be generated is either a signal divided from the main system clock, or a signal divided from the clock input from the asck20 pin. (i) generation of uart baud rate transmit/receive clock by means of system clock the transmit/receive clock is generated by di viding the system clock. the baud rate generated from the system clock is estimated by using the following expression. [baud rate] = [bps] f x : main system clock oscillation frequency (ceramic/crystal oscillation) n: value in the above table t hat is determined by the setti ngs of tps200 to tps203 (2 n 8) table 14-5. example of relationship be tween main system clock and baud rate error (%) baud rate (bps) n brgc20 set value f x = 5.0 mhz f x = 4.9152 mhz 1200 8 70h 2400 7 60h 4800 6 50h 9600 5 40h 19200 4 30h 38400 3 20h 76800 2 10h 1.73 0 caution be sure not to select n = 1 during operation at f x > 2.5 mhz because the resulting baud rate exceeds the rated range. f x 2 n + 1
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 206 (ii) generation of uart baud ra te transmit/receive clock by m eans of external clock from asck20 pin the transmit/receive clock is generated by dividi ng the clock input from the asck20 pin. the baud rate generated from the clock i nput from the asck20 pin is es timated by using the following expression. [baud rate] = [bps] f asck : frequency of clock input to the asck20 pin table 14-6. relationship betw een asck20 pin input frequency and baud rate (when brg c20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1200 19.2 2400 38.4 4800 76.8 9600 153.6 19200 307.2 31250 500.0 38400 614.4 f asck 16
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 207 (2) communication operation (a) data format the transmit/receive data format is as shown in figur e 14-7. one data frame c onsists of a start bit, character bits, parity bit and stop bit(s). the specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out by asynchronous se rial interface mode register 20 (asim20). figure 14-7. format of asynchronous serial interface transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame ? start bit ...................... 1 bit ? character bits............. 7 bits/8 bits ? parity bits ................... even parity/odd parity/ 0 parity/no parity ? stop bit(s)................... 1 bit/2 bits when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (b it 7) is ignored, and in reception t he most significant bit (bit 7) is always 0. the serial transfer rate is selected by means of baud rate generator contro l register 20 (brgc20). if a serial data receive error is generated, the re ceive error contents can be determined by reading the status of asynchronous serial inte rface status register 20 (asis20).
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 208 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receivi ng side. with even parit y and odd parity, a one-bit (odd number) error can be detected. with 0 par ity and no parity, an erro r cannot be detected. (i) even parity ? at transmission the transmission operation is contro lled so that the number of bi ts with a value of 1 in the transmit data including parity bit may be even. the parity bit value should be as follows. the number of bits with a value of 1 is an odd number in transmit data: 1 the number of bits with a value of 1 is an even number in transmit data: 0 ? at reception the number of bits with a value of 1 in the receive data including parity bit is counted, and if the number is odd, a parity error is generated. (ii) odd parity ? at transmission conversely to the even parity, t he transmission operation is controll ed so that the number of bits with a value of 1 in the transmit data including par ity bit may be odd. the parity bit value should be as follows. the number of bits with a value of 1 is an odd number in transmit data: 0 the number of bits with a value of 1 is an even number in transmit data: 1 ? at reception the number of bits with a value of 1 in the receive data including parity bit is counted, and if the number is even, a parity error is generated. (iii) 0 parity when transmitting, the parity bit is set to 0 irrespective of the transmit data. at reception, a parity bit check is not perform ed. therefore, a parit y error is not generated, irrespective of whether the parity bit is set to 0 or 1. (iv) no parity a parity bit is not added to the trans mit data. at reception, data is received assuming that there is no parity bit. since there is no parit y bit, a parity error is not generated.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 209 (c) transmission a transmit operation is started by wr iting transmit data to transmit shi ft register 20 (txs20). the start bit, parity bit, and stop bit(s) are added automatically. when the transmit operation starts, the data in txs20 is shifted out, and when txs20 is empty, a transmission completion interr upt (intst20) is generated. figure 14-8. asynchronous serial interf ace transmission completion interrupt timing (a) stop bit length: 1 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 (b) stop bit length: 2 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 caution do not overwrite asynchronous serial in terface mode register 20 (asim20) during a transmit operation. if the asim20 regist er is overwritten during transmission, subsequent transmission may not operate (the normal state is restored by reset input). it is possible to determine whether transm ission is in progress by software by using a transmission completion interrupt (intst20) or the interrupt request flag (stif20) set by the intst20.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 210 (d) reception when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is set (1), a receive operation is enabled and sampling of t he rxd20 pin input is performed. rxd20 pin input sampling is performed using t he serial clock specified by asim20. when the rxd20 pin input becomes lo w, the 3-bit counter starts count ing, and at the time when half the time determined by specified baud rate has passed, the data sampling start timing signal is output. if the rxd20 pin input sampled again as a result of this st art timing signal is low, it is identified as a start bit, the 3-bit counter is initializ ed and starts counting, and data sampli ng is performed. when character data, a parity bit, and one stop bit ar e detected after the start bit, re ception of one frame of data ends. when one frame of data has been receiv ed, the receive data in the shi ft register is transferred to receive buffer register 20 (rxb20), and a recepti on completion interrupt (intsr20) is generated. if an error is generated, the receive data in which t he error was generated is still transferred to rxb20, and intsr20 is generated. if the rxe20 bit is reset (0) during the receive operat ion, the receive operation is stopped immediately. in this case, the contents of rxb20 and asynchronous serial interface status register 20 (asis20) are not changed, and intsr 20 is not generated. figure 14-9. asynchronous serial inte rface reception completion interrupt timing stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 caution be sure to read recei ve buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will be occurred when the next data is received, and the receive error state will continue indefinitely.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 211 (e) receive errors the following three errors may occur during a receive oper ation: a parity error, fr aming error, or overrun error. an error flag is set in asynchronous serial in terface status register 20 ( asis20) as the result of data reception. receive error c auses are shown in table 14-7. it is possible to determine what kind of error was generated during reception by reading the contents of asis20 in the reception error interrupt servicing (see figures 14-9 and 14-10). the contents of asis20 are reset (0 ) by reading receive buffer register 20 (rxb20) or receiving the next data (if there is an error in the next dat a, the corresponding error flag is set). table 14-7. receive error causes receive errors cause value of asis20 parity error parity specifi ed at transmission and reception data parity do not match. 04h framing error stop bit is not detected. 02h overrun error reception of next data is comp leted before data is read from receive buffer register. 01h figure 14-10. receive error timing (a) parity error generated stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 (b) flaming error or overrun error generated stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 cautions 1. the contents of the asis20 register are reset (0) by reading receive buffer register 20 (rxb20) or receiving the next data. to ascertain the error contents, read asis20 before reading rxb20. 2. be sure to read receive buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will be occurred when the next data is received, and the receive error state will continue indefinitely.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 212 (f) reading receive data when the reception completion interrupt (intsr20) is generated, receive dat a can be read by reading the value of receive buffer register 20 (rxb20). to read the receive data stored in receive buffer register 20 (rxb20), read while reception is enabled (rxe20 = 1). remark however, if it is necessary to read rece ive data after reception has stopped (rxe20 = 0), read using either of the following methods. (a) read after setting rxe20 = 0 after waiting for one cycle or more of the source clock selected by brgc20. (b) read after bit 2 (dir20) of serial operat ion mode register 20 (csim20) is set (1). program example of (a) (brgc20 = 00h (source clock = fx/2)) intrxe: ; nop ; 2 clocks clr1 rxe20 ; reception stopped mov a, rxb20 ; read receive data program example of (b) intrxe: ; set1 csim20.2 ; dir20 flag is set to lsb first clr1 rxe20 ; reception stopped mov a, rxb20 ; read receive data
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 213 (3) uart mode cautions (a) when bit 7 (txe20) of asynchronous serial inte rface mode register 20 ( asim20) is cleared during transmission, be sure to set transmit shift regist er 20 (txs20) to ffh, then set txe20 to 1 before executing the next transmission. (b) when bit 6 (rxe20) of asynchronous serial inte rface mode register 20 ( asim20) is cleared during reception, receive buffer register 20 (rxb20) and t he receive completion interrupt (intsr20) are as follows. parity rxd20 pin rxb20 intsr20 <3> <1> <2> when rxe20 is set to 0 at a time indicated by <1> , rxb20 holds the previ ous data and does not generate intsr20. when rxe20 is set to 0 at a time indicated by <2> , rxb20 updates the dat a and does not generate intsr20. when rxe20 is set to 0 at a time indicated by <3> , rxb20 updates the data and generates intsr20.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 214 14.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful fo r connection of peripheral i/o and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75xl series, 78k series, 17k series. communication is performed using three lines: a serial clock line (sck20), serial output line (so20), and serial input line (si20). (1) register setting 3-wire serial i/o mode settings are performed usi ng serial operation mode register 20 (csim20), asynchronous serial interface mode register 20 (asim20), baud rate generat or control register 20 (brgc20), port mode register 2 (pm2), and port 2 (p2). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 operation control in 3-wire serial i/o mode csie20 0000 dir20 csck20 0 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation stopped operation enabled dir20 0 1 start bit specification msb lsb csck20 0 1 clock selection in 3-wire serial i/o mode input clock to sck20 pin from external dedicated baud rate generator output caution 1. bits 0 and 3 to 6 must be set to 0. 2. when the external input clock is selected in 3-wire serial i/o mode, set input mode by setting bit 3 of port mode register 2 (pm2) to 1. 3. switching operation modes must be performed after the serial transmit/receive operation is stopped.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 215 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. when the 3-wire serial i/o mode is sele cted, asim20 must be cleared to 00h. txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission parity check is not performed at reception (no parity error is generated.) odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification cautions 1. bits 0 and 1 must be set to 0. 2. switching operation modes must be performed after the serial transmit/receive operation is stopped.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 216 (c) baud rate generator cont rol register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. tps203 0 0 0 0 0 0 0 0 1 tps203 tps202 tps201 tps200 0000 brgc20 r/w ff73h 00h r/w 76543210 tps202 0 0 0 0 1 1 1 1 0 f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 (2.5 mhz) (1.25 mhz) (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) f cc /2 f cc /2 2 f cc /2 3 f f cc /2 4 cc /2 5 f cc /2 6 f cc /2 7 f cc /2 8 (2.0 mhz) (1.0 mhz) (500 khz) (250 khz) (125 khz) (62.5 khz) (31.3 khz) (15.6 khz) tps201 0 0 1 1 0 0 1 1 0 tps200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 ? setting prohibited symbol address after reset selection of baud rate generator source clock during f x = 5.0 mhz operation during f cc = 4.0 mhz operation input clock to asck20 pin from external note other than above note in 3-wire serial i/o mode, it is setting prohibited. caution when writing to brgc20 is performe d during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation) 3. n: value in the above table that is determined in the se ttings of tps200 to tps203 (1 n 8) if the internal clock is used as the serial clock fo r the 3-wire serial i/o mode, set the tps200 to tps203 bits to set the frequency of the serial clock. to obtain the frequency to be set, use the following formula. when the serial clock is input from external, setting brgc20 is unnecessary. serial clock frequency = [hz] f clk : f x or f cc f x : main system clock oscillation frequency (ceramic/crystal oscillation) f cc : main system clock oscillation frequency (rc oscillation) n: value in the above table t hat is determined in the setti ngs of tps200 to tps203 (1 n 8) f clk 2 n + 1
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 217 (2) communication operation in the 3-wire serial i/o mode, data transmission/rec eption is performed in 8-bit units. data is transmitted/received bit by bit in syn chronization with the serial clock. transmit shift register 20 (txs20/sio20) and receiv e shift register 20 (rxs20) shift operations are performed in synchronization with the fall of the serial clock (sck20). transmit data is then held in the so20 latch and output from the so 20 pin. also, receive data input to t he si20 pin is latched in receive buffer register 20 (rxb20/sio20) on the rise of sck20. at the end of an 8-bit transfer, the operation of txs20/sio20 or rxs20 stops automatic ally, and the interrupt request signal (intcsi20) is generated. figure 14-11. 3-wire serial i/o mode timing (i) master operation 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 note si20 writing to sio20 intcsi20 (ii) slave operation 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 note so20 writing to sio20 intcsi20 note the value of the last bit previously output is output.
chapter 14 serial interface 20 user?s manual u14800ej2v0ud 218 (3) transfer start serial transfer is started by setting transfer data to transmit shift register 20 (txs20/sio20) when the following two conditions are satisfied. ? bit 7 (csie20) of serial operat ion mode register 20 (csim20) = 1 ? internal serial clock is stopped or sck20 is a high level after 8-bit serial transfer. caution if csie20 is set to 1 after data writ e to txs20/sio20, tran sfer does not start. termination of 8-bit transfer stops the serial transfe r automatically and generates the interrupt request signal (intcsi20).
user?s manual u14800ej2v0ud 219 chapter 15 lcd controller/driver 15.1 lcd controller/driver functions the functions of the lcd controller/driver of the pd789306 and pd789316 subseries are as follows. (1) automatic output of segment and common signal s based on automatic display data memory read (2) two different display modes: 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) (3) four different frame frequencies, selectable in each display mode (4) up to 24 segment signal outputs (s0 to s23) and four common signal outputs (com0 to com3) (5) operation with a subsystem clock (6) on-chip voltage boosting circuit table 15-1 lists the maximum number of pixels that can be displayed in each display mode. table 15-1. maximu m number of pixels bias mode number of time slices common signals used maximum number of pixels 3 com0 to com2 72 (24 segments 3 commons) note 1 1/3 4 com0 to com3 96 (24 segments 4 commons) note 2 notes 1. 8-digit lcd panel, each digit having a 3-segment configuration. 2. 12-digit lcd panel, each digit having a 2-segment configuration. 15.2 lcd controller/driver configuration the lcd controller/driver in cludes the following hardware. table 15-2. configuration of lcd controller/driver item configuration display outputs segment signals: 24 common signals: 4 control registers lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) lcd voltage amplification control register 0 (lcdva0)
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 220 the correspondence with the lcd display ram is shown in figure 15-1 below. figure 15-1. corresponden ce with lcd display ram address bit segment 7 6 5 4 3 2 1 0 fa17h 0 0 0 0 s23 fa16h 0 0 0 0 s22 fa15h 0 0 0 0 s21 fa14h 0 0 0 0 s20 fa13h 0 0 0 0 s19 fa12h 0 0 0 0 s18 fa11h 0 0 0 0 s17 fa10h 0 0 0 0 s16 fa0fh 0 0 0 0 s15 fa0eh 0 0 0 0 s14 fa0dh 0 0 0 0 s13 fa0ch 0 0 0 0 s12 fa0bh 0 0 0 0 s11 fa0ah 0 0 0 0 s10 fa09h 0 0 0 0 s9 fa08h 0 0 0 0 s8 fa07h 0 0 0 0 s7 fa06h 0 0 0 0 s6 fa05h 0 0 0 0 s5 fa04h 0 0 0 0 s4 fa03h 0 0 0 0 s3 fa02h 0 0 0 0 s2 fa01h 0 0 0 0 s1 fa00h 0 0 0 0 s0 common com3 com2 com1 com0 remark bit 4 to 7 are fixed to 0.
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 221 internal bus lcdc03 lcdc02 lcdc01 lcdc00 2 2 selector prescaler lcd clock selector selector f lcd 2 6 f lcd 2 7 f lcd 2 8 f lcd 2 9 lcd clock control register 0 (lcdc0) lcdon0 vaon0 lcd display mode register 0 (lcdm0) v lc0 segment driver common driver com0 com1 com2 com3 3210 3210 65 74 fa00h display data memory lcdon0 selector segment driver 3210 3210 65 74 fa17h lcdon0 s23 f clk /2 5 f clk /2 6 f clk /2 7 f xt s0 ............... ............... f lcd selector segment driver 3210 3210 65 74 fa0fh lcdon0 s15 lcdcl lips0 gain lcd voltage amplification control register 0 (lcdva0) v lc2 caph capl v lc1 .......... ........... ............ ........... ........... ........... booster circuit common voltage controller clock generator for boosting timing controller vaon0 segment voltage controller selector segment driver 3210 3210 65 74 fa10h lcdon0 s16 ............. ........... ........... ............ ............ ........... ............ .......... lcdm00 remark f clk : f x or f cc ........... ........... figure 15-2. block diagram of lcd controller/driver
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 222 15.3 registers controlling lcd controller/driver the following three registers cont rol the lcd controller/driver. lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) lcd voltage amplification control register 0 (lcdva0)
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 223 (1) lcd display mode register 0 (lcdm0) lcdm0 is used to control the lcd display enable/di sable status, booster circ uit operation enable/disable status, segment pin/common pi n output, and the display mode. lcdm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears lcdm0 to 00h. figure 15-3. format of lcd display mode register 0 lcdon0 vaon0 0 lips0 0 0 0 lcdm00 lcdm0 symbol address after reset r/w ffb0h 00h r/w <7><6>5<4>3210 lcd controller/driver display mode selection lcdm00 0 1 4 3 lcd display enable/disable lcdon0 0 1 display off (all segment signals are deselected.) display on operation control of segment pin/common pin output note lips0 0 1 booster circuit operation enable/disable note vaon0 0 1 booster circuit stopped booster circuit enabled output ground level to segment/common pin output deselect level to segment pin and lcd waveform to common pin number of time slices bias mode 1/3 1/3 note when the lcd display panel is not used, the vaon0 and lips0 must be set to 0 to reduce power consumption. cautions 1. bits 1 to 3 and 5 must be set to 0. 2. when operating vaon0, follo w the procedure described below. a. to stop voltage amplification after switching display status from on to off : 1) set to display off st atus by setting lcdon0 = 0. 2) disable outputs of all the segment bu ffers and common buffers by setting lips0 = 0. 3) stop voltage amplification by setting vaon0= 0. b. to stop voltage amplification during display on status : setting prohibited. be sure to stop vo ltage amplification afte r setting display off. c. to set display on from voltage amplification stop status : 1) start voltage amplification by setti ng vaon0 = 1, then wait for about 500 ms. 2) set all the segment buffers and comm on buffers to non-display output status by setting lips0 = 1. 3) set display on by setting lcdon0 = 1.
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 224 (2) lcd clock control register 0 (lcdc0) lcdc0 specifies the lcd source clock and lcd clock. the frame frequency is determined according to the lcd clock and the number of time slices. lcdc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears lcdc0 to 00h. figure 15-4. format of lcd clock control register 0 lcdc03 lcdc02 lcdc01 lcdc00 lcdc0 symbol address after reset r/w ffb2h 00h r/w 76543210 lcd source clock (f lcd ) selection note during f x = 5.0 mhz or f xt = 32.768 khz operation during f cc = 4.0 mhz or f xt = 32.768 khz operation lcdc03 0 0 1 1 lcdc02 0 1 0 1 lcd clock (lcdcl) selection lcdc01 0 0 1 1 lcdc00 0 1 0 1 0000 f lcd /2 6 f lcd /2 7 f lcd /2 8 f lcd /2 9 f xt (32.768 khz) f x /2 5 (156.3 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f cc /2 5 (125 khz) f cc /2 6 (62.5 khz) f cc /2 7 (31.3 khz) note specify an lcd source clock (f lcd ) frequency of at least 32 khz. remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation) 3. f xt : subsystem clock oscillation frequency as an example, table 15-3 lists the frame frequencies used when f xt (32.768 khz) is supplied as the lcd source clock (f lcd ). caution set the frame frequency to 128 hz or lower. table 15-3. frame frequencies (hz) lcd clock (lcdcl) number of time slices f xt /2 9 (64 hz) f xt /2 8 (128 hz) f xt /2 7 (256 hz) f xt /2 6 (512 hz) 3 21 43 85 171 note 4 16 32 64 128 note this setting is prohibited because it c auses the frame frequency to exceed 128 hz.
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 225 (3) lcd voltage amplification control register 0 (lcdva0) lcdva0 controls the voltage amplification level during t he voltage amplifier operation. lcdva0 is set using a 1-bit or 8-bi t memory manipulation instruction. reset input clears lcdva0 to 00h. figure 15-5. format of lcd volt age boost control register 0 0 gain lcdva0 symbol address after reset r/w ffb3h 00h r/w 7654321<0> gain 0 1 1.5 v (specification of the lcd panel used is 4.5 v.) 1.0 v (specification of the lcd panel used is 3 v.) 0 0 0 0 00 reference voltage (v lc2 ) level selection note note select the settings according to the specif ications of the lcd panel that is used. caution before changing the lcdva0 setting, be sure to stop voltage boosting (vaon0 = 0). remark the typ. value is indicated as the reference voltage (v lc2 ) value.
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 226 15.4 setting lcd controller/driver set the lcd controller/driver using the following procedure. <1> set the frame frequency using lcd cl ock control register 0 (lcdc0). <2> set the voltage amplification level using lcd vo ltage amplification contro l register 0 (lcdva0). gain = 0: v lc0 = 4.5 v, v lc1 = 3 v, v lc2 = 1. 5 v gain = 1: v lc0 = 3 v, v lc1 = 2 v, v lc2 = 1 v <3> set the time division using lcdm00 (bit 0 of lcd display mode register 0 (lcdm0)). <4> enable voltage amplification by setting vao n0 (bit 6 of lcdm0) (vaon0 = 1). <5> wait for 500 ms or more after setting vaon0. <6> set lips0 (bit 4 of lcdm0) (lips0 = 1) and output the deselect potential. <7> start output corresponding to each data memory by setting lcdon0 (bit 7 of lcdm0) (lcdon0 =1). 15.5 lcd display data memory the lcd display data memory is mapped at addresses fa00h to fa17h. data in the lcd display data memory can be displayed on the lcd panel us ing the lcd controller/driver. figure 15-6 shows the relationship between the c ontents of the lcd disp lay data memory and the segment/common outputs. that part of the display data memory which is not used for display can be used as ordinary ram. figure 15-6. relationship between lcd display data memory cont ents and segment/common outputs s23 fa17h s22 fa16h s21 fa15h s20 s2 fa02h s1 fa01h s0 fa00h com3 com2 com1 com0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address caution no memory has been installe d as the higher 4 bits of the lcd di splay data memory. be sure to set 0 to them.
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 227 15.6 common and segment signals each pixel of the lcd panel turns on when the pot ential difference between the corresponding common and segment signals becomes higher than a s pecific voltage (lcd drive voltage, v lcd ). it turns off when the potential difference becomes lower than v lcd . applying dc voltage to the common and segment signals for an lcd panel would deteriorate it. to avoid this problem, this lcd panel is driven with ac voltage. (1) common signals each common signal is selected sequentially according to a specified number of time slots at the timing listed in table 15-4. in the static di splay mode, the same signal is output to com0 to com3 in common. in the three-time slot m ode, keep the com3 pin open. table 15-4. com signals com signal number of time slots com0 com1 com2 com3 three-time slot mode open four-time slot mode (2) segment signals the segment signals correspond to 24 bytes of lcd display data memory (fa00h to fa17h). bits 0, 1, 2, and 3 of each byte are read in synchronization with com0, com1, com2, and com3, respectively. if the contents of each bit are 1, it is conver ted to the select voltage, and if 0, it is converted to the deselect voltage. the conversion results are output to the segment pins (s0 to s23). check, with the information given above, what combination of the front-s urface electrodes (corresponding to the segment signals) and the rear-sur face electrodes (corresponding to the common signals) forms display patterns in the lcd display data memory, and write t he bit data that corresponds to the desired display pattern on a one-to-one basis. bit 3 of the lcd display data memory is not used for lcd di splay in the three-time slot mode. so this bit can be used for purposes other than display. lcd display data memory bits 4 to 7 are fixed to 0. (3) output waveforms of common and segment signals when both common and segment signals are at t he select voltage, a display-on voltage of v lcd is obtained. the other combinations of the signals correspond to the display-off voltage. figure 15-7 shows the common signal waveforms, and figure 15-8 shows the vo ltages and phases of the common and segment signals.
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 228 figure 15-7. common signal waveforms comn (three-time slot mode) t f = 3 t v lc0 v ss v lcd v lc1 v lc2 t f = 4 t comn (four-time slot mode) v lc0 v lcd v lc1 v lc2 v ss t: one lcd clock period t f : frame frequency figure 15-8. voltages and phases of common and segment signals select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 v lc1 v lc1 t: one lcd clock period
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 229 15.7 display modes 15.7.1 three-time sl ot display example figure 15-10 shows how the 8-digit lcd panel having the disp lay pattern shown in figure 15-9 is connected to the segment signals (s0 to s23) and the co mmon signals (com0 to com2) of the pd789306 or pd789316 subseries chip. this example displays data ?123456.78? in the lcd panel . the contents of the disp lay data memory (addresses fa00h to fa17h) correspond to this display. the following description focuses on numeral ?6.? ( ) displayed in the third digit. to display ?6.? in the lcd panel, it is necessary to apply the select or des elect voltage to the s6 to s8 pins acco rding to table 15-5 at the timing of the common signals com0 to com2; see figure 15-9 for the relationship between t he segment signals and lcd segments. table 15-5. select and desel ect voltages (com0 to com2) segment common s6 s7 s8 com0 deselect select select com1 select select select com2 select select ? according to table 15-5, it is dete rmined that the display data memory loca tion (fa06h) that corresponds to s6 must contain x110. figure 15-11 shows examples of lcd drive waveforms between the s6 signal and each common signal. when the select voltage is applied to s6 at the timing of com1 or com2, an alternate rectangle waveform, +v lcd /?v lcd , is generated to turn on the corresponding lcd segment. figure 15-9. three-time slot lcd disp lay pattern and electrode connections s 3n+2 s 3n com0 com2 s 3n+1 com1 remark n = 0 to 7
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 230 figure 15-10. example of connecting three-time slot lcd panel 001011011101110110111111 001110011011011111001111 bit 3 bit 2 bit 1 bit 0 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e f fa10h 1 2 3 4 5 6 7 s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 com 3 com 2 com 1 com 0 open 00 10 10 00 10 11 00 10 x? x? x? x? x? x? x? x? x?: can be used to store any data because ther e is no corresponding segment in the lcd panel. : can always be used to store any data becaus e of the three-time slot mode being used.
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 231 figure 15-11. three-time slot lcd drive waveform examples v lc0 v lc2 com0 +v lcd 0 com0-s9 ? v lcd v lc1 +1/3v lcd ? 1/3v lcd v ss0 v lc0 v lc2 com1 v lc1 v ss0 v lc0 v lc2 com2 v lc1 v ss0 v lc0 v lc2 s9 v lc1 v ss0 +v lcd 0 com1-s9 ? v lcd +1/3v lcd ? 1/3v lcd +v lcd 0 com2-s9 ? v lcd +1/3v lcd ? 1/3v lcd t f
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 232 15.7.2 four-time slot display example figure 15-13 shows how the 12-digit lcd panel having the di splay pattern shown in figure 15-12 is connected to the segment signals (s0 to s23) and the common signals (com0 to com3) of the pd789306 or pd789316 subseries chip. this example displays data ?123456.789012? in the lcd panel. the cont ents of the display data memory (addresses fa00h to fa17h ) correspond to this display. the following description focuses on numeral ?6.? ( ) disp layed in the seventh digit. to display ?6.? in the lcd panel, it is necessary to apply the select or deselect volt age to the s12 and s13 pins acco rding to table 15-6 at the timing of the common signals com0 to com3; see figure 15-12 for the relationship bet ween the segment signals and lcd segments. table 15-6. select and desel ect voltages (com0 to com3) segment common s12 s13 com0 select select com1 deselect select com2 select select com3 select select according to table 15-6, it is dete rmined that the display data memory loca tion (fa0ch) that corresponds to s12 must contain 1101. figure 15-14 shows examples of lcd drive waveforms between the s12 signal and each common signal. when the select voltage is applied to s12 at the ti ming of com0, an alternate rectangle waveform, +v lcd /?v lcd , is generated to turn on the corresponding lcd segment. figure 15-12. four-time slot lcd displ ay pattern and electrode connections remark n = 0 to 11 com0 s 2n com1 s 2n+1 com2 com3
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 233 figure 15-13. example of connecting four-time slot lcd panel 000101101111111111110001 011111111010011111010111 011001010111011101110110 001010001011001000100010 bit 3 bit 2 bit 1 bit 0 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e f fa10h 1 2 3 4 5 6 7 s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 com 3 com 2 com 1 com 0
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 234 figure 15-14. four-time slot lcd drive wavef orm examples t f v lc0 v lc2 com0 +v lcd 0 com0-s16 ? v lcd v lc1 +1/3v lcd ? 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v ss +v lcd 0 com1-s16 ? v lcd +1/3v lcd ? 1/3v lcd v lc0 v lc2 s16 v lc1 v ss remark the waveforms for com2 to s16 and com3 to s16 are omitted.
chapter 15 lcd controller/driver user?s manual u14800ej2v0ud 235 15.8 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 the pd789306, 789316 subseries contains a booster circuit ( 3 only) to generate a supply voltage to drive the lcd. the internal lcd refer ence voltage is out put from the v lc2 pin. a voltage two times higher than that on v lc2 is output from the v lc1 pin and a voltage three times higher than that on v lc2 is output from the v lc0 pin. the lcd reference voltage (v lc2 ) can be specified by setting lcd boos t control register 0 (lcdva0). the pd789306, 789316 subseries requires an exter nal capacitor (recommended value: 0.47 f) because it employs a capacitance division method to gener ate a supply voltage to drive the lcd. table 15-7. output voltages of v lc0 to v lc2 pins lcdva0 gain = 0 gain = 1 lcd drive power supply pin v lc0 4.5 v 3.0 v v lc1 3.0 v 2.0 v v lc2 (lcd reference voltage) 1.5 v 1.0 v cautions 1. when using the lcd function, do not leave the v lc0 , v lc1 , and v lc2 pins open. refer to figure 15-15 for connection. 2. since the lcd drive voltage is separate from the main pow er supply, a constant voltage can be supplied regardless of v dd fluctuation. figure 15-15. example of conn ecting pins for lcd driver v lc0 v lc1 v lc2 c2 c3 c4 caph c1 external pin c1 = c2 = c3 = c4 = 0.47 f capl remark use a capacitor with as little leakage as possible. in addition, make c1 a nonpolar capacitor.
236 user?s manual u14800ej2v0ud chapter 16 interrupt functions 16.1 interrupt function types the following two types of in terrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. a standby release signal is generated. one interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupt this interrupt undergoes mask control. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in table 16-1. a standby release signal is generated. 5 external and 9 internal interrupt source s are incorporated as maskable interrupts. 16.2 interrupt sources and configuration a total of 15 non-maskable and maskable interrupts are incorporated as interrupt sources (see table 16-1 ).
chapter 16 interrupt functions user?s manual u14800ej2v0ud 237 table 16-1. interrupt source list interrupt source interrupt type priority note 1 name trigger internal/ external vector table address basic configuration type note 2 non-maskable ? intwdt watchdog timer overflow (with watchdog timer mode 1 selected) (a) 0 intwdt watchdog timer overflow (with interval timer mode selected) internal 0004h (b) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 pin input edge detection external 000ch (c) intsr20 end of serial interface 20 uart reception 5 intcsi20 end of serial interface 20 3-wire sio transfer reception 000eh 6 intcsi10 end of serial interface 10 3-wire sio transfer reception 0010h 7 intst20 end of serial interface 20 uart transmission 0012h 8 intwti interval timer interrupt 0014h 9 inttm20 generation of match signal of 16-bit timer 20 0016h 10 inttm30 generation of match signal of 8-bit timer 30 0018h 11 inttm40 generation of match signal of 8-bit timer/event counter 40 001ah 12 intwt watch timer interrupt internal 001eh (b) maskable 13 intkr00 key return signal detection external 0020h (c) notes 1. priority is the priority order when several maskabl e interrupts are generated at t he same time. 0 is the highest order and 13 is the lowest order. 2. basic configuration types (a) to (c) correspond to (a) to (c) in figure 16-1. remark there are two interrupt sources for the wa tchdog timer (intwdt): non-maskable and maskable interrupts (internal). either one (but not both) should be selected for actual use.
chapter 16 interrupt functions user?s manual u14800ej2v0ud 238 figure 16-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt mk if ie internal bus intm0, intm1, krm00 interrupt request edge detector vector table address generator standby release signal intp0: external interrupt mode register 0 intp1: external interrupt mode register 1 krm00: key return mode register 00 if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag
chapter 16 interrupt functions user?s manual u14800ej2v0ud 239 16.3 registers controlling interrupt function the following five types of registers are used to control the interrupt functions. ? interrupt request flag registers 0, 1 (if0 and if1) ? interrupt mask flag registers 0, 1 (mk0 and mk1) ? external interrupt mode regi sters 0, 1 (intm0 and intm1) ? program status word (psw) ? key return mode register 00 (krm00) table 16-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. table 16-2. flags corresponding to interrupt request signal name interrupt request signal name interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intp3 intsr20/intcsi20 intcsi10 intst20 intwti inttm20 inttm30 inttm40 intwt intkr00 wdtif pif0 pif1 pif2 pif3 srif20 csiif10 stif20 wtiif tmif20 tmif30 tmif40 wtif krif00 wdtmk pmk0 pmk1 pmk2 pmk3 srmk20 csimk10 stmk20 wtimk tmmk20 tmmk30 tmmk40 wtmk krmk00
chapter 16 interrupt functions user?s manual u14800ej2v0ud 240 (1) interrupt request flag registers 0, 1 (if0 and if1) the interrupt request flag is set to 1 when the corre sponding interrupt request is generated or an instruction is executed. it is cleared to 0 when an instruction is executed upon acknowledgement of an interrupt request or upon reset input. if0 and if1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input clears if0 and if1 to 00h. figure 16-2. format of interrupt request flag registers 0 1 0 krif00 wtif 0 tmif40 tmif30 tmif20 wtiif if1 ffe1h 00h r/w interrupt request flag no interrupt request signal is generated interrupt request signal is generated; interrupt request state xxifx <6> <5> 4 <3> <2> <1> 7 <0> stif20 csiif10 srif20 pif3 pif2 pif1 pif0 wdtif if0 r/w ffe0h 00h r/w symbol address after reset <6> <5> <4> <3> <2> <1> <7> <0> cautions 1. bits 4 and 7 of if1 must be set to 0. 2. the wdtif flag is r/w enabled only when a wa tchdog timer is used as an interval timer. if the watchdog timer mode 1 or 2 is used, set the wdtif flag to 0. 3. because port 3 has an alte rnate function as the external interrupt input, when the output level is changed by specifying th e output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. 4. if an interrupt is acknowledged, the interrupt request flag is automatically cleared before the interrupt routine is entered.
chapter 16 interrupt functions user?s manual u14800ej2v0ud 241 (2) interrupt mask flag registers 0, 1 (mk0 and mk1) the interrupt mask flag is used to enable/disabl e the corresponding maskable interrupt service. mk0 and mk1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input sets mk0 and mk1 to ffh. figure 16-3. format of interrupt mask flag registers 0 1 1 krmk00 wtmk 1 tmmk40 tmmk30 tmmk20 wtimk mk1 ffe5h ffh r/w interrupt servicing control interrupt servicing enabled interrupt servicing disabled <6> <5> 4 <3> <2> <1> 7 <0> xxmk stmk20 csimk10 srmk20 pmk3 pmk2 pmk1 pmk0 wdtmk mk0 r/w ffe4h ffh r/w symbol address after reset <6> <5> <4> <3> <2> <1> <7> <0> cautions 1. bits 4 and 7 of mk1 must be set to 1. 2. if the wdtmk flag is read when the watc hdog timer is used in watc hdog timer mode 1 or 2, its value becomes undefined. 3. because port 3 has an alte rnate function as the external interrupt input, when the output level is changed by specifying th e output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode.
chapter 16 interrupt functions user?s manual u14800ej2v0ud 242 (3) external interrupt m ode register 0 (intm0) this register is used to specify a valid edge for intp0 to intp2. intm0 is set with an 8-bit memo ry manipulation instruction. reset input clears intm0 to 00h. figure 16-4. format of external interrupt mode register 0 0 0 1 1 es21 es20 es11 es10 es01 es00 0 0 intm0 r/w ffech 00h r/w 76543210 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 symbol address after reset intp0 valid edge selection falling edge rising edge setting prohibited both rising and falling edges intp1 valid edge selection falling edge rising edge setting prohibited both rising and falling edges intp2 valid edge selection falling edge rising edge setting prohibited both rising and falling edges es00 es01 es11 es10 es20 es21 cautions 1. bits 0 and 1 must be set to 0. 2. before setting the intm0 register, be sure to set the relevant interr upt mask flag to 1 to disable interrupts. after that, clear (0) the interrupt request flag, then set the interrupt m ask flag to 0 to enable interrupts.
chapter 16 interrupt functions user?s manual u14800ej2v0ud 243 (4) external interrupt m ode register 1 (intm1) intm1 is used to specify a valid edge for intp3. intm1 is set with an 8-bit memo ry manipulation instruction. reset input clears intm1 to 00h. figure 16-5. format of external interrupt mode register 1 0 0 0 0 0 0 es31 es30 intm1 76543210 es31 0 0 1 1 intp3 valid edge selection es30 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges symbol address after reset r/w ffedh 00h r/w cautions 1. bits 2 to 7 must be set to 0. 2. before setting intm1, set pm k3 to 1 to disable interrupts. after that, clear (0) pif3, then set pmk3 to 0 to enable interrupts. (5) program status word (psw) the program status word is a regist er used to hold the instruction execut ion result and the current status for interrupt requests. the ie flag to set maskable interrupt enable/disable is mapped. besides 8-bit unit read/write, this register can carry out operations wit h a bit manipulation instruction and dedicated instructions (ei, di). w hen a vectored interrupt is acknowledged, the psw is automatically saved into a stack, and the ie flag is reset to 0. reset input sets psw to 02h. figure 16-6. configuration of program status word ie z 0 ac 0 0 1 cy psw 76543210 ie 0 1 02h symbol after reset used when normal instruction is executed interrupt acknowledgement enabled/disabled disabled enabled
chapter 16 interrupt functions user?s manual u14800ej2v0ud 244 (6) key return mode register 00 (krm00) this register sets the pin that detects a key return signal (falling edge of port 0). krm00 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears krm00 to 00h. figure 16-7. format of key return mode register 00 0 1 00 00000 krm000 krm00 fff5h 00h r/w address after reset r/w key return signal detection control no detection detection (detecting falling edge of port 0) 654321 70 krm000 symbol cautions 1. bits 1 to 7 must be set to 0. 2. before setting krm00, always set bit 6 of mk 1 (krmk00 = 1) to disable interrupts. after setting krm00, clear krmk00 after clearing bit 6 of if1 (krif00 = 0) to enable interrupts. 3. when p00 to p03 are in input mode, on-chip pull-up resistors are connected to p00 to p03 by the setting of krm000. after switching to output mode, the on-chip pull-up resistors are cut off. however, key return si gnal detection continues. 4. the key return signal cannot be detected while even one of the pins that specify detection of the key return signal is low, even if a falling e dge is generated at other key return pins. figure 16-8. block diagram of falling edge detector p00/kr0 p01/kr1 p02/kr2 p03/kr3 falling edge detector krmk00 krif00 set signal standby release signal key return mode register 00 (krm00) note selector note selector that selects t he pin used for falling edge input
chapter 16 interrupt functions user?s manual u14800ej2v0ud 245 16.4 interrupt servicing operation 16.4.1 non-maskable interrupt request acknowledgment operation the non-maskable interrupt request is unconditionally ack nowledged even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when the non-maskable interrupt request is acknowledged, psw and pc are saved to the stack in that order, the ie flag is reset to 0, the contents of the vector t able are loaded to the pc, and t hen program execution branches. figure 16-9 shows the flow from non-maskable interr upt request generation to acknowledgement, figure 16-10 shows the timing of non-maskable interrupt ackno wledgement, and figure 16-11 shows the acknowledgement operation when a number of non-ma skable interrupts are generated. caution during non-maskable interrupt service progr am execution, do not input another non-maskable interrupt request; if it is input, the servi ce program will be interr upted and the new non- maskable interrupt requ est will be acknowledged.
chapter 16 interrupt functions user?s manual u14800ej2v0ud 246 figure 16-9. flow from gene ration of non-maskable interrupt request to acknowledgment start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt servicing starts wdtm3 = 0 (non-maskable interrupt is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 16-10. timing of non-maskable interrupt request acknowledgment instruction instruction saving psw and pc, and jump to interrupt servicing interrupt servicing program cpu processing wdtif figure 16-11. non-maskable inte rrupt request acknowledgment second interrupt servicing first interrupt servicing nmi request (second) nmi request (first) main routine
chapter 16 interrupt functions user?s manual u14800ej2v0ud 247 16.4.2 maskable interrupt re quest acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vector ed interrupt is acknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the interrupt servicing afte r a maskable interrupt request has been generated is shown in table 16-3. refer to figures 16-13 and 16-14 for the ti ming of interrupt request acknowledgement. table 16-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an inte rrupt request is generat ed immediately before bt or bf instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generat ed at the same time, they are acknowledged starting from the one assigned the highest priority by the priority specification flag. a pending interrupt is acknowledged when the st atus where it can be acknowledged is set. figure 16-12 shows the algorithm of interrupt request acknowledgement. when a maskable interrupt request is a cknowledged, the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each in terrupt request is loaded to the pc, and execution branches. to return from interrupt servic ing, use the reti instruction. figure 16-12. interrupt request acknowledgment pr ogram algorithm start xxif = 1 ? xxmk = 0 ? ie = 1 ? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending xxif: interrupt request flag xxmk: interrupt mask flag ie: flag to control maskable interrupt reques t acknowledgement (1 = enable, 0 = disable) 1 f cpu
chapter 16 interrupt functions user?s manual u14800ej2v0ud 248 figure 16-13. interrupt request ackno wledgment timing (example: mov a, r) clock cpu mov a, r saving psw and pc, and jump to interrupt servicing 8 clocks interrupt servicing program interrupt if the interrupt request has generated an interrupt request flag (xxif) by t he time the instruction clocks under execution, n clocks (n = 4 to 10), are n ? 1, interrupt request acknowledgment processing will start following the completion of the instruction under exec ution. figure 16-13 shows an example us ing the 8-bit data transfer instruction mov a, r. because this instruction is executed in 4 clocks, if an interrupt request is generated bet ween the start of execution and the 3rd clock, interrupt request acknowledgment processing will ta ke place following the completion of mov a, r. figure 16-14. interrupt re quest acknowledgment timing (when interrupt request flag is gene rated in final clock under execution) clock cpu nop mov a, r saving psw and pc, and jump to interrupt servicing interrupt servicing program interrupt 8 clocks if the interrupt request flag (xxif) is generated in the final clock of the instruction, interrupt request acknowledgment processing will begin after executi on of the next instruction is complete. figure 16-14 shows an example whereby an interrupt request was generated in the 2nd clock of nop (a 2-clock instruction). in this case, the interr upt request will be processed after execution of mov a, r, which follows nop, is complete. caution when interrupt request flag registers 0 and 1 (if0 and if1), or interrupt mask flag registers 0 and 1 (mk0 and mk1) are being accessed, inte rrupt requests will be held pending. 16.4.3 multiple interrupt servicing multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced, can be serviced using the priority order. if multiple interr upts are generated at the same ti me, they are serviced in the order according to the priority assigned to each interrupt request in advance (refer to table 16-1 ).
chapter 16 interrupt functions user?s manual u14800ej2v0ud 249 figure 16-15. example of multiple interrupts example 1. acknowledging multiple interrupts intyy ei main servicing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 the interrupt request intyy is ackno wledged during the servicing of interrupt intxx and multiple interrupts are performed. before each interrupt reques t is acknowledged, the ei instruction is issued and the interrupt request is enabled. example 2. multiple interrupts are not performed because interrupts are disabled intyy ei main servicing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupt requests are disabled (the ei instruction has not been issued) in the interrupt intxx servicing, the interrupt request intyy is not a cknowledged and multiple interrupts are not performed. intyy is held pending and is acknowledged after intxx servicing is completed. ie = 0: interrupt requests disabled
chapter 16 interrupt functions user?s manual u14800ej2v0ud 250 16.4.4 putting interrupt requests on hold if an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being execut ed, the interrupt request will not be acknowledged until the instruct ion is completed. such instructions (interrupt request pendi ng instructions) are as follows. ? instructions that manipulate interrupt request flag registers 0, 1 (if0 and if1) ? instructions that manipulate interr upt mask flag registers 0, 1 (mk0 and mk1)
user?s manual u14800ej2v0ud 251 chapter 17 standby function 17.1 standby function and configuration 17.1.1 standby function the standby function is to reduce the power consumpti on of the system and can be e ffected in the following two modes: (1) halt mode this mode is set when the halt inst ruction is executed. the halt mode stops the operation clock of the cpu. the system clock oscillator continues oscillati ng. this mode does not r educe the power consumption as much as the stop mode, but is useful for resuming processing imm ediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is exec uted. the stop mode stops the main system clock oscillator and stops the entire system. the power consumpti on of the cpu can be s ubstantially reduced in this mode. the data memory can be reta ined at the low voltage (v dd = 1.8 v). therefore, this mode is useful for retaining the contents of the data memory at an extremely low current. the stop mode can be released by an interrupt request, so that this mode can be used for intermittent operation. however, some time is required until the system clock oscilla tor stabilizes after the stop mode has been released. if processing must be resumed immedi ately by using an interrupt request, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memo ry before setting the standby mode are all retained. in addition, the status es of the output latch of the i/o ports and output buffer are also retained. caution to set the stop mode, be sure to stop th e operations of the periphe ral hardware, and then execute the stop instruction.
chapter 17 standby function user?s manual u14800ej2v0ud 252 17.1.2 register controlling standby function the wait time after the stop mode is released upon inte rrupt request until oscillation st abilizes is controlled with the oscillation stabilization ti me select register (osts) note . osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, it takes 2 15 /f x , not 2 17 /f x , after reset input. note the pd789306 subseries only. the pd789316 subseries does not have an o scillation stabilization time sele ct register. the oscillation stabilization time for the pd789316 subseries is fixed at 2 7 /f cc . figure 17-1. format of oscillation st abilization time select register osts2 0 0 1 00000 osts2 osts1 osts0 osts r/w fffah 04h r/w 76543210 osts1 0 1 0 2 12 /f x 2 15 /f x 2 17 /f x (819 s) (6.55 ms) (26.2 ms) osts0 0 0 0 setting prohibited symbol address after reset oscillation stabilization time selection other than above caution the wait time after the stop mode is released does not in clude the time from stop mode release to clock oscillation start (? a? in the figure below), regard less of whether stop mode is released by reset input or by interrupt generation. v ss a stop mode release x1 pin voltage waveform remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 17 standby function user?s manual u14800ej2v0ud 253 17.2 standby function operation 17.2.1 halt mode (1) halt mode the halt mode is set by exec uting the halt instruction. the operation status in the halt mode is shown in the following table. table 17-1. halt mode operating status halt mode operation status while the main system clock is running halt mode operation status while the subsystem clock is running item while the subsystem clock is running while the subsystem clock is not running while the main system clock is running while the main system clock is not running main system clock oscillation enabled oscillation stopped cpu operation stopped port (output latch) remains in the state existing before the selection of halt mode. 16-bit timer 20 operation enabled operation stopped 8-bit timer 30 operation enabled note 1 8-bit timer 40 operation enabled operation enabled note 2 watch timer operation enabled operation enabled note 3 operation enabled operation enabled note 4 watchdog timer operation enabled operation stopped serial interface 10 serial interface 20 operation enabled operation enabled note 5 lcd controller/driver operation enabled operation enabled note 3 operation enabled operation enabled note 4 external interrupt operation enabled note 6 notes 1. operation is enabled only when input signal from time r 40 (timer 40 operation is enabled) is selected as the count clock. 2. operation is enabled when tmi40 is selected as the count clock. 3. operation is enabled while the ma in system clock is selected. 4. operation is enabled while the subsystem clock is selected. 5. operation is enabled only when ex ternal clock is selected. 6. maskable interrupt that is not masked
chapter 17 standby function user?s manual u14800ej2v0ud 254 (2) releasing halt mode the halt mode can be released by the following three types of sources: (a) releasing by unmasked interrupt request the halt mode is released by an unm asked interrupt request. in this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed. if the inte rrupt is disabled, the instruction at the next address is executed. figure 17-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operation mode operation mode clock oscillation remarks 1. the broken line indicates the case where the in terrupt request that has released the standby mode is acknowledged. 2. the wait time is as follows: ? when vectored interrupt proce ssing is performed: 9 to 10 clocks ? when vectored interrupt processi ng is not performed: 1 to 2 clocks (b) releasing by non-maskable interrupt request the halt mode is released regardl ess of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed.
chapter 17 standby function user?s manual u14800ej2v0ud 255 (c) releasing by reset input when the halt mode is released by the reset signal, execution branc hes to the reset vector address in the same manner as the ordinary reset oper ation, and program exec ution is started. figure 17-3. releasing halt mode by reset input halt instruction reset signal wait note reset period halt mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation note for the pd789306 subseries, 2 15 /f x : 6.55 ms (@ f x = 5.0 mhz operation) for the pd789316 subseries, 2 7 /f cc : 32 s (@ f cc = 4.0 mhz operation) remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation) table 17-2. operation after releasing halt mode releasing source mkxx ie operation 0 0 executes next address instruction 0 1 executes interrupt servicing maskable interrupt request 1 x retains halt mode non-maskable interrupt request ? x executes interrupt servicing reset input - ? - ? reset processing x: don?t care
chapter 17 standby function user?s manual u14800ej2v0ud 256 17.2.2 stop mode (1) setting and operation st atus of stop mode the stop mode is set by exec uting the stop instruction. caution because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. when the stop mode is set, therefore, the halt mode is set immediately after the stop instruction has been execu ted, the wait time set by the oscillation stabilization time select register (osts) el apses, and then an operation mode is set. the operation status in the stop m ode is shown in the following table. table 17-3. stop mode operating status stop mode operation status while the main system clock is running item while the subsystem clock is running while the subsystem clock is not running main system clock osc illation stopped cpu operation stopped port (output latch) remains in the state existing before the selection of stop mode. 16-bit timer 20 operation stopped 8-bit timer 30 operation enabled note 1 8-bit timer 40 operation enabled note 2 watch timer operation enabled note 3 operation stopped watchdog timer operation stopped serial interface 10 serial interface 20 operation enabled note 4 lcd controller/driver operation enabled note 3 operation stopped external interrupt operation enabled note 5 notes 1. operation is enabled only when input signal from time r 40 (timer 40 operation is enabled) is selected as the count clock. 2. operation is enabled when tmi40 is selected as the count clock. 3. operation is enabled while the subsystem clock is selected. 4. operation is enabled only when ex ternal clock is selected. 5. maskable interrupt that is not masked
chapter 17 standby function user?s manual u14800ej2v0ud 257 (2) releasing stop mode the stop mode can be released by the following two types of sources: (a) releasing by unmasked interrupt request the stop mode can be released by an unmasked interrupt request. in this case, if the interrupt is enabled to be acknowledged, vectored interrupt pr ocessing is performed, after the oscillation stabilization time has elapsed. if the interrupt is dis abled, the instruction at t he next address is executed. figure 17-4. releasing stop mode by interrupt stop instruction standby release signal wait note (set time by osts) stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation note the pd789316 subseries does not have osts and wait is fixed at 2 7 /f cc . remark the broken line indicates the case where the inte rrupt request that has re leased the standby mode is acknowledged.
chapter 17 standby function user?s manual u14800ej2v0ud 258 (b) releasing by reset input when the stop mode is released by the reset signal, the reset operation is performed after the oscillation stabilization time has elapsed. figure 17-5. releasing stop mode by reset input stop instruction reset signal wait note stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation reset period note for the pd789306 subseries, 2 15 /f x : 6.55 ms (@ f x = 5.0 mhz operation) for the pd789316 subseries, 2 7 /f cc : 32 s (@ f cc = 4.0 mhz operation) remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation) table 17-4. operation after releasing stop mode releasing source mkxx ie operation maskable interrupt request 0 0 ex ecutes next address instruction 0 1 executes interrupt servicing 1 x retains stop mode reset input ? - ? - reset processing x: don?t care
user?s manual u14800ej2v0ud 259 chapter 18 reset function the following two operations are ava ilable to generate reset signals. (1) external reset input by reset pin (2) internal reset by watc hdog timer runaway time detection external and internal reset have no functional differences. in both cases, program exec ution starts at the address at 0000h and 0001h by reset input. when a low level is input to the r eset pin or the watchdog timer overflow s, a reset is applied and each hardware is set to the status shown in tabl e 18-1. each pin has a high impedance dur ing reset input or during oscillation stabilization time just after reset clear. when a high level is input to the r eset pin, the reset is cleared and progr am execution is started after the oscillation stabilization time has elapsed. the reset appli ed by the watchdog timer overfl ow is automatically cleared after reset, and program execution is started afte r the oscillation stabilization time has elapsed (see figures 18-2 to 18-4 .) cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pins become high impedance. figure 18-1. block diagram of reset function reset interrupt function count clock reset controller watchdog timer over- flow reset signal stop
chapter 18 reset function 260 user?s manual u14800ej2v0ud figure 18-2. reset timing by reset input x1, cl1 reset internal reset signal port pin during normal operation delay delay hi-z reset period (oscillation stops) normal operation (reset processing) oscillation stabilization time wait figure 18-3. reset timing by overflow in watchdog timer x1, cl1 overflow in watchdog timer internal reset signal port pin hi-z during normal operation reset period (oscillation continues) normal operation (reset processing) oscillation stabilization time wait figure 18-4. reset timing by reset input in stop mode x1, cl1 reset internal reset signal port pin delay delay hi-z stop instruction execution during normal operation reset period (oscillation stops) stop status (oscillation stops) normal operation (reset processing) oscillation stabilization time wait
chapter 18 reset function user?s manual u14800ej2v0ud 261 table 18-1. hardware status after reset hardware status after reset program counter (pc) note 1 the contents of reset vector tables (0000h and 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose register undefined note 2 port (p0 to p3, p5) (output latch) 00h port mode register (pm0 to pm3, pm5) ffh pull-up resistor option register (pu0, pub2, pub3) 00h processor clock control register (pcc) 02h suboscillation mode register (sckm) 00h subclock control register (css) 00h oscillation stabilization time select register (osts) note 3 04h timer counter (tm20) 0000h compare register (cr20) ffffh control register (tmc20) 00h 16-bit timer 20 capture register (tcp20) undefined timer counter (tm30, tm40) 00h compare register (cr30, cr40, crh40) undefined 8-bit timer 30, 40 mode control register (tmc30, tmc40) 00h watch timer mode control register (wtm) 00h clock select register (wdcs) 00h watchdog timer mode register (wdtm) 00h serial operation mode register (csim10, csim20) 00h asynchronous serial interface mode register (asim20) 00h asynchronous serial interface st atus register (asis20) 00h baud rate generator control register (brgc20) 00h transmit shift register (txs20) ffh serial interface 20 receive buffer register (rxb20) undefined display mode register (lcdm0) 00h clock control register (lcdc0) 00h lcd controller/driver voltage amplification control register (lcdva0) 00h request flag register (if0, if1) 00h mask flag register (mk0, mk1) ffh external interrupt mode register (intm0, intm1) 00h interrupt key return mode register (krm00) 00h notes 1. during reset input and oscillation stabilization ti me wait, only the pc contents among the hardware statuses become undefined. all other hardware remains unchanged after reset. 2. the post-reset values are retained in the standby mode. 3. pd789306 subseries only
user?s manual u14800ej2v0ud 262 chapter 19 flash memory the pd78f9306, 78f9316 are avail able as the flash memory versions of the pd789306, 789316 subseries. the pd78f9306 is a version with t he internal rom of the pd789304, 789306 replaced with flash memory and the pd78f9316 is a version with t he internal rom of the pd789314, 789316 replaced with flash memory. the differences between the pd78f9306, 78f9316 and the mask rom versi ons are shown in table 19-1. table 19-1. differences between pd78f9306, 78f9316 and mask rom versions flash memory version mask rom version part number item pd78f9306 pd78f9316 pd789304 pd789306 pd789314 pd789316 rom 16 kb 8 kb 16 kb 8 kb 16 kb high-speed ram 512 bytes internal memory lcd display ram 24 4 bits system clock ceramic/ crystal oscillation rc oscillation ceramic/crystal oscillation rc oscillation ic pin not provided provided v pp pin provided not provided pull-up resistor 19 (software control: 19) 23 (so ftware control: 19, mask option control: 4) electrical s pecifications refer to chapter 22 electrical specifications . caution there are differences in noi se immunity and noise radiation be tween the flash memory and mask rom versions. when pre-producing an applicati on set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct suffici ent evaluations for the commercial samples (not engineering samples) of the mask rom version.
chapter 19 flash memory user?s manual u14800ej2v0ud 263 19.1 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the pd78f9306, 78f9316 mounted on the target system (on-board). a fl ash memory program adapter (fa adapte r), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. ? software can be modified after the microcontro ller is solder-mounted on the target system. ? distinguishing software facilities sm all-quantity, varied model production ? easy data adjustment when starting mass production 19.1.1 programming environment the following shows the environment required for pd78f9306, 78f9316 flash memory programming. when flashpro iii (part no. fl-pr3, pg-fp3) or flashpro iv (part no. fl-pr4, pg-fp4) is used as a dedicated flash programmer, a host machine is required to contro l the dedicated flash programme r. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals for flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 19-1. environment for wr iting program to flash memory host machine rs-232c usb dedicated flash programmer pd78f9306 pd78f9316 v pp v dd v ss reset 3-wire serial i/o or uart
chapter 19 flash memory user?s manual u14800ej2v0ud 264 19.1.2 communication mode use the communication mode shown in table 19-2 to perform communication between the dedicated flash programmer and pd78f9306, 78f9316. table 19-2. communication mode list type setting note 1 cpu clock communication mode comm port sio clock in flashpro on target board multiple rate pins used number of v pp pulses 3-wire serial i/o sio ch-0 (3-wire, sync.) 100 hz to 1.25 mhz note 2 1, 2, 4, 5 mhz notes 2, 3 1 to 5 mhz note 2 1.0 si10/p22 so10/p21 sck10/p20 0 uart uart ch-0 (async.) 4,800 to 76,800 bps notes 2, 4 5 mhz note 5 4.91 or 5 mhz note 2 1.0 rxd20/si20/p25 txd20/so20/p24 8 notes 1. selection items for type settings on the dedicated flash programmer (flashpro iii (part no. fl-pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)). 2. the possible setting range differs depending on the voltage. for details, refer to chapter 22 electrical specifications . 3. 2 or 4 mhz only for flashpro iii 4. because signal wave slew also affects uart communication, in addition to the baud rate error, thoroughly evaluate the slew and baud rate error. 5. only for flashpro iv. however, when using flashpro iii, be sure to select the clock of the resonator on the board. uart cannot be used with the clock supplied by flashpro iii. figure 19-2. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n v pp pulses
chapter 19 flash memory user?s manual u14800ej2v0ud 265 figure 19-3. example of connecti on with dedicated flash programmer (a) 3-wire serial i/o dedicated flash programmer vpp1 vdd reset sck so si clk note 1 gnd v pp v dd reset sck10 si10 so10 x1 (p03) v ss pd78f9306, 78f9316 (b) uart dedicated flash programmer vpp1 vdd reset so si clk notes 1, 2 gnd v pp v dd reset r x d20 t x d20 x1 (p30) v ss pd78f9306, 78f9316 notes 1. when the system clock is supplied from the dedicated flash programmer to the pd78f9306, connect the clk pin with x1 pin and disconnect the on-board resonator. when using t he clock of the on-board resonator, do not connect the clk pin. when using the pd78f9316, be sure to connect the clk pi n with p03 pin and the system clock is supplied from the dedicated flash programmer. 2. when using uart with flashpro iii, t he clock of the resonator connect ed to the x1 pin must be used, so do not connect to the clk pin. caution the v dd pin, if already connected to the power suppl y, must be connected to the vdd pin of the dedicated flash programmer. when usi ng the power supply connected to the v dd pin, supply voltage before starting programming.
chapter 19 flash memory user?s manual u14800ej2v0ud 266 if flashpro iii/flashpro iv is used as a dedicated flas h programmer, the following signals are generated for the pd78f9306, 78f9316. for details, refer to the manual of flashpro iii/flashpro iv. table 19-3. pin connection list signal name i/o pin function pin name 3-wire serial i/o uart vpp1 output write voltage v pp vpp2 ? ? ? vdd i/o v dd voltage generation/ voltage monitoring v dd note note gnd ? ground v ss x1 ( pd78f9316) clk output clock output p03 ( pd78f9316) reset output reset signal reset si input receive signal so10/txd20 so output transmit signal si10/rxd20 sck output transfer clock sck10 hs input handshake signal ? note v dd voltage must be supplied befor e programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected.
chapter 19 flash memory user?s manual u14800ej2v0ud 267 19.1.3 on-board pin connections when programming on the target system, provide a connector on the target system to connect to the dedicated flash programmer. there may be cases in which an on-board function that switches from the normal operation mode to flash memory programming mode is required. input 0 v to the v pp pin in the normal operation m ode. a write voltage of 10.0 v (typ.) is supplied to the v pp pin in the flash memory programmi ng mode. therefore, connect the v pp pin using method (1) or (2) below. (1) connect a pull-down resistor of rv pp = 10 k ? to the v pp pin. (2) set the jumper on the board to switch the input of v pp pin to the programmer side or directly to gnd. the following shows an example of v pp pin connection. figure 19-4. v pp pin connection example pd78f9306, pd78f9316 v pp pull-down resistor (rv pp ) connection pin of dedicated flash programmer the following shows the pins us ed by each serial interface. serial interface pins used 3-wire serial i/o si10, so10, sck10 uart rxd20, txd20 note that signal conflict or malfuncti on of other devices may occur when an on- board serial interface pin that is connected to another device is connected to the dedica ted flash programmer.
chapter 19 flash memory user?s manual u14800ej2v0ud 268 (1) signal conflict a signal conflict occurs if the dedica ted flash programmer (output) is c onnected to a serial interface pin (input) connected to another dev ice (output). to prevent this signal conflict, isolate t he connection with the other device or put the other devic e in the output hi gh impedance status. figure 19-5. signal conflict (serial interface input pin) pd78f9306, pd78f9316 signal conflict output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict. to prevent this, isolate the signal on the device side. connection pin of dedicated flash programmer other device input pin (2) malfunction of another device when the dedicated flash programmer (out put or input) is connected to a seri al interface pin (input or output) connected to another device (i nput), a signal may be output to the device, causing a malfunction. to prevent such malfunction, isolate the connecti on with other device or set so that the input signal to the device is ignored. figure 19-6. malfunction of another device pd78f9306, pd78f9316 input pin input pin pin pin other device other device connection pin of dedicated flash programmer connection pin of dedicated flash programmer if the signal output by the pd78f9306, 78f9316 affects another device in the flash memory programming mode, isolate the signal on the device side. if the signal output by the dedicated flash programmer affects another device, isolate the signal on the device side. pd78f9306, pd78f9316
chapter 19 flash memory user?s manual u14800ej2v0ud 269 when the reset signal of the dedicated flash programmer is connected to t he reset pin connected to the reset signal generator on the board, a signal c onflict occurs. to prevent this si gnal conflict, isolat e the connection with the reset signal generator. if a reset signal is input from the user system in the flash memory programming mode, a normal programming operation will not be performed. do not input signals other than reset signals from the dedicated flash programmer during this period. figure 19-7. signal conflict (reset pin) reset pd78f9306, pd78f9316 signal conflict output pin reset signal generator in the flash memory programming mode, the signal output by the reset signal generator and the signal output by the dedicated flash programmer conflict, therefore, isolate the signal on the reset signal generator side. connection pin of dedicated flash programmer shifting to the flash memory programming mode sets all the pins except those used for flash memory programming communication to the st atus immediately after reset. therefore, if the exter nal device does not acknowledge an initial status such as t he output high impedance status, connect the external device to v dd or v ss via a resistor. ? in the case of pd78f9306 when using an on-board clock, connection of x1, x2, xt 1, and xt2 must conform to the methods in the normal operation mode. when using the clock output of the fl ash programmer, directly connect it to the x1 pin with the on-board main oscillator disconnected, and leave the x2 pin open. for the subclock, connection conf orms to that in the normal operation mode. ? in the case of pd78f9316 connect cl1, cl2, xt1, and xt2 as required in the normal operation m ode, and connect the clock output of the flash programmer to the p03 pin. to use the power output of the flash programmer, connect the v dd0 pins to vdd of the flash programmer, and the v ss pins to gnd of the flash programmer. to use the on-board power supply, connec tion must conform to that in t he normal operation mode. however, because the voltage is monitored by t he flash programmer, therefore, v dd of the flash programmer must be connected.
chapter 19 flash memory user?s manual u14800ej2v0ud 270 handle the other pins (s0 to s23, com0 to com3, v lc0 to v lc2 , caph, capl) in the same way as in the normal operation mode. 19.1.4 connection when using flash memory writing adapter the following shows an example of the recommended connection when using t he flash memory writing adapter. figure 19-8. example of flash memory writing adap ter connection when using 3-wire serial i/o mode ( pd78f9306) gnd vdd lvdd (vpp2) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
chapter 19 flash memory user?s manual u14800ej2v0ud 271 figure 19-9. example of flash memory writing adap ter connection when using 3-wire serial i/o mode ( pd78f9316) gnd vdd lvdd (vpp2) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
chapter 19 flash memory user?s manual u14800ej2v0ud 272 figure 19-10. example of flash memory writi ng adapter connection when using uart mode ( pd78f9306) gnd vdd lvdd (vpp2) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
chapter 19 flash memory user?s manual u14800ej2v0ud 273 figure 19-11. example of flash memory writi ng adapter connection when using uart mode ( pd78f9316) gnd vdd lvdd (vpp2) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
user?s manual u14800ej2v0ud 274 chapter 20 mask options table 20-1. selection of mask option for pins pin mask option p50 to p53 whether a pull-up resistor is to be incorporated can be spec ified in 1-bit units. for p50 to p53 (port 5), a mask option is used to specify whether a pull-up resistor is to be incorporated. the mask option is selectable in 1-bit units. caution flash memory versions do not have a mask option-based on-chip pull-up resistor function.
user?s manual u14800ej2v0ud 275 chapter 21 instruction set this chapter lists the instruction set of the pd789306 and pd789316 subseries. for the details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) . 21.1 operation 21.1.1 operand identifier s and description methods operands are described in ?operand? colu mn of each instruction in accordanc e with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are described as they are. each symbol has the following meaning. ? #: immediate data specification ? $: relative address specification ? !: absolute address specification ? [ ]: indirect address specification in the case of immediate data, descr ibe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp, either functional names (x, a, c, etc.) or absolute names (names in parenthesis in the table below, r0, r1, r2, etc.) can be used for description. table 21-1. operand identifi ers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark see table 5-3 special function register list for symbols of special function registers.
chapter 21 instruction set user?s manual u14800ej2v0ud 276 21.1.2 description of ?operation? column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag indicating non-maskable interrupt servicing in progress ( ): memory contents indicated by addre ss or register contents in parenthesis x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) v: exclusive logical sum (exclusive or) ? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 21.1.3 description of ?flag? column (blank): unchanged 0: cleared to 0 1: set to 1 x: set/cleared according to the result r: previously saved value is restored
chapter 21 instruction set user?s manual u14800ej2v0ud 277 21.2 operation list mnemonic operands byte clock operation flag z ac cy mov r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 2 4 a r r, a note 1 2 4 r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte x x x a, psw 2 4 a psw psw, a 2 4 psw a x x x a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl+byte] 2 6 a (hl + byte) [hl+byte], a 2 6 (hl + byte) a xch a, x 1 4 a ? x a, r note 2 2 6 a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) a, [hl+byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 21 instruction set user?s manual u14800ej2v0ud 278 mnemonic operands byte clock operation flag z ac cy movw rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp rp, ax note 1 4 rp ax xchw ax, rp note 1 8 ax ? rp add a, #byte 2 4 a, cy a + byte x x x saddr, #byte 3 6 (saddr), cy (saddr) + byte x x x a, r 2 4 a, cy a + r x x x a, saddr 2 4 a, cy a + (saddr) x x x a, !addr16 3 8 a, cy a + (addr16) x x x a, [hl] 1 6 a, cy a + (hl) x x x a, [hl+byte] 2 6 a, cy a + (hl + byte) x x x addc a, #byte 2 4 a, cy a + byte + cy x x x saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy x x x a, r 2 4 a, cy a + r + cy x x x a, saddr 2 4 a, cy a + (saddr) + cy x x x a, !addr16 3 8 a, cy a + (addr16) + cy x x x a, [hl] 1 6 a, cy a + (hl) + cy x x x a, [hl+byte] 2 6 a, cy a + (hl + byte) + cy x x x sub a, #byte 2 4 a, cy a ? byte x x x saddr, #byte 3 6 (saddr), cy (saddr) ? byte x x x a, r 2 4 a, cy a ? r x x x a, saddr 2 4 a, cy a ? (saddr) x x x a, !addr16 3 8 a, cy a ? (addr16) x x x a, [hl] 1 6 a, cy a ? (hl) x x x a, [hl+byte] 2 6 a, cy a ? (hl + byte) x x x note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 21 instruction set user?s manual u14800ej2v0ud 279 mnemonic operands byte clock operation flag z ac cy subc a, #byte 2 4 a, cy a ? byte ? cy x x x saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy x x x a, r 2 4 a, cy a ? r ? cy x x x a, saddr 2 4 a, cy a ? (saddr) ? cy x x x a, !addr16 3 8 a, cy a ? (addr16) ? cy x x x a, [hl] 1 6 a, cy a ? (hl) ? cy x x x a, [hl+byte] 2 6 a, cy a ? (hl + byte) ? cy x x x and a, #byte 2 4 a a byte x saddr, #byte 3 6 (saddr) (saddr) byte x a, r 2 4 a a r x a, saddr 2 4 a a (saddr) x a, !addr16 3 8 a a (addr16) x a, [hl] 1 6 a a (hl) x a, [hl+byte] 2 6 a a (hl + byte) x or a, #byte 2 4 a a byte x saddr, #byte 3 6 (saddr) (saddr) byte x a, r 2 4 a a r x a, saddr 2 4 a a (saddr) x a, !addr16 3 8 a a (addr16) x a, [hl] 1 6 a a (hl) x a, [hl+byte] 2 6 a a (hl + byte) x xor a, #byte 2 4 a a v byte x saddr, #byte 3 6 (saddr) (saddr) v byte x a, r 2 4 a a v r x a, saddr 2 4 a a v (saddr) x a, !addr16 3 8 a a v (addr16) x a, [hl] 1 6 a a v (hl) x a, [hl+byte] 2 6 a a v (hl + byte) x remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 21 instruction set user?s manual u14800ej2v0ud 280 mnemonic operands byte clock operation flag z ac cy cmp a, #byte 2 4 a ? byte x x x saddr, #byte 3 6 (saddr) ? byte x x x a, r 2 4 a ? r x x x a, saddr 2 4 a ? (saddr) x x x a, !addr16 3 8 a ? (addr16) x x x a, [hl] 1 6 a ? (hl) x x x a, [hl+byte] 2 6 a ? (hl + byte) x x x addw ax, #word 3 6 ax, cy ax + word x x x subw ax, #word 3 6 ax, cy ax ? word x x x cmpw ax, #word 3 6 ax ? word x x x inc r 2 4 r r + 1 x x saddr 2 4 (saddr) (saddr) + 1 x x dec r 2 4 r r ? 1 x x saddr 2 4 (saddr) (saddr) ? 1 x x incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 x rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 x rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 x rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 x set1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1 x x x [hl].bit 2 10 (hl).bit 1 clr1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0 x x x [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 1 1 clr1 cy 1 2 cy 0 0 not1 cy 1 2 cy cy x remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 21 instruction set user?s manual u14800ej2v0ud 281 mnemonic operands byte clock operation flag z ac cy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 rrr push psw 1 2 (sp ? 1) psw, sp sp ? 1 rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 pop psw 1 4 psw (sp), sp sp + 1 r r r rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, ax 2 8 sp ax ax, sp 2 6 ax sp br !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 ax 1 6 pc h a, pc l x bc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 bt saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 bf saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 dbnz b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 21 instruction set user?s manual u14800ej2v0ud 282 21.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr !addr16 psw [de] [hl] [hl+byte] $addr1 6 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl+byte] mov note except r = a.
chapter 21 instruction set user?s manual u14800ej2v0ud 283 (2) 16-bit instructions movw, xchw, addw, subw, cmpw , push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1
chapter 21 instruction set user?s manual u14800ej2v0ud 284 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop
user?s manual u14800ej2v0ud 285 chapter 22 electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd ?0.3 to +6.5 v power supply voltage v pp pd78f9306, 78f9316 only note 1 ?0.3 to +10.5 v v i1 p00 to p03, p10 to p13, p20 to p26, p30 to p33, x1 (cl1), x2 (cl2), xt1, xt2, reset ?0.3 to v dd + 0.3 note 2 v n-ch open drain ?0.3 to +13 v input voltage v i2 p50 to p53 on-chip pull-up resistor ?0.3 to v dd + 0.3 note 2 v output voltage v o ?0.3 to v dd + 0.3 note 2 v 1 pin ?10 ma output current, high i oh total for all pins ?30 ma 1 pin 30 ma output current, low i ol total for all pins 160 ma in normal operation ?40 to +85 c operating ambient temperature t a during flash memory programming 10 to 40 c mask rom version ?65 to +150 c storage temperature t stg pd78f9306, 78f9316 ?40 to +125 c notes 1. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (1.8 v) of the operating voltage range (see a in the figure below). when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit va lue (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b 2. 6.5 v or less
chapter 22 electrical specifications user?s manual u14800ej2v0ud 286 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remarks 1. pin names enclosed in par entheses apply when using the pd789316 subseries. 2. unless specified otherwise, the characteristics of alternate-func tion pins are the same as those of port pins.
chapter 22 electrical specifications user?s manual u14800ej2v0ud 287 main system clock o scillator characteristics ceramic/crystal oscillation ( pd789306 subseries) (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 1.0 5.0 mhz ceramic resonator x1 x2 v ss c1 c2 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms oscillation frequency note 1 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator x1 x2 v ss c1 c2 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz x2 x1 x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x2 open x1 x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator whose oscillation stabilizes within the o scillation stabilization wait time. cautions 1. when using the main system clock oscillator, wire as follo ws in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . ? do not ground the capacitor to a ground patte rn through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization ti me has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 22 electrical specifications user?s manual u14800ej2v0ud 288 rc oscillation ( pd789316 subseries) (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f cc ) note 1 2.0 4.0 mhz v dd = 2.7 to 5.5 v 32 s rc resonator cl2 cl1 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 128 s cl1 input frequency (f cc ) note 1 1.0 4.0 mhz cl1 cl2 cl1 input high-/low-level width (t xh , t xl ) 100 500 ns cl1 input frequency (f cc ) note 1 v dd = 2.7 to 5.5 v 1.0 4.0 mhz external clock cl1 open cl2 cl1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 100 500 ns notes 1. indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. the error of capacitor (c) and resistor (r) is not included. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follo ws in the area enclosed by the broken lines in the above fi gure to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . ? do not ground the capacitor to a ground patte rn through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization ti me has been secured by the program before switching back to the main system clock.
chapter 22 electrical specifications user?s manual u14800ej2v0ud 289 rc oscillation frequency characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit f cc1 v dd = 2.7 to 5.5 v 1.5 2.0 2.5 mhz f cc2 v dd = 1.8 to 3.6 v 0.5 2.0 2.5 mhz f cc3 r = 11.0 k ? , c = 22 pf target: 2 mhz v dd = 1.8 to 5.5 v 0.5 2.0 2.5 mhz f cc4 v dd = 2.7 to 5.5 v 2.5 3.0 3.5 mhz f cc5 v dd = 1.8 to 3.6 v 0.75 3.0 3.5 mhz f cc6 r = 6.8 k ? , c = 22 pf target: 3 mhz v dd = 1.8 to 5.5 v 0.75 3.0 3.5 mhz f cc7 v dd = 2.7 to 5.5 v 3.5 4.0 4.7 mhz f cc8 v dd = 1.8 to 3.6 v 1.0 4.0 4.7 mhz oscillation frequency f cc9 r = 4.7 k ? , c = 22 pf target: 4 mhz v dd = 1.8 to 5.5 v 1.0 4.0 4.7 mhz remarks 1. set rc to one of the above nine values so that t he typical value of the oscillation frequency is within 2.0 to 4.0 mhz. 2. the resistor (r) and capacitor (c) error is not included. subsystem clock oscilla tor characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 crystal resonator xt2 xt1 v ss c4 c3 r oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 xt2 xt1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the sub system clock oscillator, wire as follo ws in the area enclosed by the broken lines in the above fi gure to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . ? do not ground the capacitor to a ground patte rn through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more pr one to malfunction due to noise than the main system clock oscillator. particular care is therefor e required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
chapter 22 electrical specifications user?s manual u14800ej2v0ud 290 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/6) parameter symbol conditions min. typ. max. unit 1 pin 10 ma output current, low i ol all pins 80 ma 1 pin ?1 ma output current, high i oh all pins ?15 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 p10 to p13 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih2 p50 to p53 on-chip pull-up resistor v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p00 to p03, p20 to p26, p30 to p33 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1 (cl1), x2 (cl2), xt1, xt2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 p10 to p13 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p00 to p03, p20 to p26, p30 to p33 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1 (cl1), x2 (cl2), xt1, xt2 v dd = 1.8 to 5.5 v 0 0.1 v i oh = ?1 ma v dd = 4.5 to 5.5 v v dd ? 1.0 v output voltage, high v oh i oh = ?100 a v dd = 1.8 to 5.5 v v dd ? 0.5 v 4.5 v dd 5.5 v, i ol = 10 ma 1.0 v v ol1 p00 to p03, p10 to p13, p20 to p26, p30 to p33 1.8 v dd < 4.5 v, i ol = 400 a 0.5 v 4.5 v dd < 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol2 p50 to p53 1.8 v dd < 4.5 v, i ol = 1.6 ma 0.4 v remarks 1. pin names enclosed in par entheses apply when using the pd789316 subseries. 2. unless specified otherwise, the characteristics of alternate-func tion pins are the same as those of port pins.
chapter 22 electrical specifications user?s manual u14800ej2v0ud 291 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/6) parameter symbol conditions min. typ. max. unit i lih1 p00 to p03, p10 to p13, p20 to p26, p30 to p33, reset 3 a i lih2 v i = v dd x1 (cl1), x2 (cl2), xt1, xt2 20 a input leakage current, high i lih3 v i = 12 v p50 to p53 (n-ch open drain) 20 a i lil1 p00 to p03, p10 to p13, p20 to p26, p30 to p33, reset ?3 a i lil2 x1 (cl1), x2 (cl2), xt1, xt2 ?20 a input leakage current, low i lil3 v i = 0 v p50 to p53 (n-ch open drain) ?3 note a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ?3 a software pull-up resistor r 1 v i = 0 v p00 to p03, p10 to p13, p20 to p26, p30 to p33 50 100 200 k ? mask option pullup resistor note 2 r 2 v i = 0 v p50 to p53 10 30 60 k ? notes 1. if p50 to p53 have been set to input mode when a read in struction is executed to read from p50 to p53, a low-level input leakage current of up to ?30 a flows during only one cycle. at all other times, the maximum leakage current is ?3 a. 2. mask rom version only remarks 1. pin names enclosed in par entheses apply when using the pd789316 subseries. 2. unless specified otherwise, the characteristics of alternate-func tion pins are the same as those of port pins.
chapter 22 electrical specifications user?s manual u14800ej2v0ud 292 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (3/6) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 1.8 2.9 ma v dd = 3.0 v 10% note 3 0.36 0.9 ma i dd1 5.0 mhz crystal oscillation operation mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.16 0.45 ma v dd = 5.0 v 10% note 2 0.96 1.92 ma v dd = 3.0 v 10% note 3 0.26 0.76 ma i dd2 5.0 mhz crystal oscillation halt mode note 4 (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.1 0.34 ma v dd = 5.0 v 10% 30 58 a v dd = 3.0 v 10% 9 26 a i dd3 32.768 khz crystal oscillation operation mode note 5 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 4 12 a v dd = 5.0 v 10% 25 48 a v dd = 3.0 v 10% 7 20 a lcd not operating note 4 v dd = 2.0 v 10% 4 10 a v dd = 5.0 v 10% 28 57 a v dd = 3.0 v 10% 9.6 27.8 a i dd4 32.768 khz crystal oscillation halt mode note 5 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 7 v dd = 2.0 v 10% 6 16 a v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a power supply current note 1 ( pd789304, 789306) i dd5 stop mode note 6 v dd = 2.0 v 10% 0.05 3.0 a notes 1. the port current (including the cu rrent that flows to the on-chip pull-up resistors) is not included. 2. high-speed mode operation (when processor clock control register (pcc) is cleared to 00h) 3. low-speed mode operation (when pcc is set to 02h) 4. when the lcd is not operating and t he booster circuit is operating (lcdo n0 = 0, vaon0 = 1, lips0 = 1). 5. when the main system clock is stopped 6. when the lcd is not operating (lcdo n0 = 0, vaon0 = 0, lips0 = 0) 7. then the lcd is operating (lcdon0 = 1, vaon0 = 1, lips0 = 1) remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 22 electrical specifications user?s manual u14800ej2v0ud 293 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (4/6) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 4.5 9 ma v dd = 3.0 v 10% note 3 1 2 ma i dd1 5.0 mhz crystal oscillation operation mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.65 1.5 ma v dd = 5.0 v 10% note 2 1.4 2 ma v dd = 3.0 v 10% note 3 0.4 0.8 ma i dd2 5.0 mhz crystal oscillation halt mode note 4 (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 3 0.19 0.42 ma v dd = 5.0 v 10% 100 230 a v dd = 3.0 v 10% 70 160 a i dd3 32.768 khz crystal oscillation operation mode note 5 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 58 120 a v dd = 5.0 v 10% 25 65 a v dd = 3.0 v 10% 7 29 a lcd not operating note 4 v dd = 2.0 v 10% 4 20 a v dd = 5.0 v 10% 28 70 a v dd = 3.0 v 10% 9.6 34 a i dd4 32.768 khz crystal oscillation halt mode note 5 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 7 v dd = 2.0 v 10% 6 25 a v dd = 5.0 v 10% 0.1 17 a v dd = 3.0 v 10% 0.05 5.5 a power supply current note 1 ( pd78f9306) i dd5 stop mode note 6 v dd = 2.0 v 10% 0.05 3.5 a notes 1. the port current (including the cu rrent that flows to the on-chip pull-up resistors) is not included. 2. high-speed mode operation (when processor clock control register (pcc) is cleared to 00h) 3. low-speed mode operation (when pcc is set to 02h) 4. when the lcd is not operating and t he booster circuit is operating (lcdo n0 = 0, vaon0 = 1, lips0 = 1). 5. when the main system clock is stopped 6. when the lcd is not operating (lcdo n0 = 0, vaon0 = 0, lips0 = 0) 7. then the lcd is operating (lcdon0 = 1, vaon0 = 1, lips0 = 1) remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 22 electrical specifications user?s manual u14800ej2v0ud 294 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (5/6) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 1.65 3.0 ma v dd = 3.0 v 10% note 3 0.65 1.44 ma i dd1 4.0 mhz rc oscillation operation mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 3 0.38 1.05 ma v dd = 5.0 v 10% note 2 1.1 2.29 ma v dd = 3.0 v 10% note 3 0.6 1.28 ma i dd2 4.0 mhz rc oscillation halt mode note 4 (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 3 0.35 0.82 ma v dd = 5.0 v 10% 30 58 a v dd = 3.0 v 10% 9 26 a i dd3 32.768 khz crystal oscillation operation mode note 5 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 4 12 a v dd = 5.0 v 10% 25 48 a v dd = 3.0 v 10% 7 20 a lcd not operating note 4 v dd = 2.0 v 10% 4 10 a v dd = 5.0 v 10% 28 57 a v dd = 3.0 v 10% 9.6 27.8 a i dd4 32.768 khz crystal oscillation halt mode note 5 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 7 v dd = 2.0 v 10% 6 16 a v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a power supply current note 1 ( pd789314, 789316) i dd5 stop mode note 6 v dd = 2.0 v 10% 0.05 3.0 a notes 1. the port current (including the cu rrent that flows to the on-chip pull-up resistors) is not included. 2. high-speed mode operation (when processor clock control register (pcc) is cleared to 00h) 3. low-speed mode operation (when pcc is set to 02h) 4. when the lcd is not operating and t he booster circuit is operating (lcdo n0 = 0, vaon0 = 1, lips0 = 1). 5. when the main system clock is stopped 6. when the lcd is not operating (lcdo n0 = 0, vaon0 = 0, lips0 = 0) 7. then the lcd is operating (lcdon0 = 1, vaon0 = 1, lips0 = 1) remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 22 electrical specifications user?s manual u14800ej2v0ud 295 dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (6/6) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 2 6 9 ma v dd = 3.0 v 10% note 3 2.0 2.5 ma i dd1 4.0 mhz rc oscillation operation mode (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 3 1.2 1.6 ma v dd = 5.0 v 10% note 2 2.5 3.5 ma v dd = 3.0 v 10% note 3 1.5 2 ma i dd2 4.0 mhz rc oscillation halt mode note 4 (r = 4.7 k ? , c = 22 pf) v dd = 2.0 v 10% note 3 0.8 1.5 ma v dd = 5.0 v 10% 100 230 a v dd = 3.0 v 10% 70 160 a i dd3 32.768 khz crystal oscillation operation mode note 5 (c3 = c4 = 22 pf, r1 = 220 k ? ) v dd = 2.0 v 10% 58 120 a v dd = 5.0 v 10% 25 65 a v dd = 3.0 v 10% 7 29 a lcd not operating note 4 v dd = 2.0 v 10% 4 20 a v dd = 5.0 v 10% 28 70 a v dd = 3.0 v 10% 9.6 34 a i dd4 32.768 khz crystal oscillation halt mode note 5 (c3 = c4 = 22 pf, r1 = 220 k ? ) lcd operating note 7 v dd = 2.0 v 10% 6 25 a v dd = 5.0 v 10% 0.1 17 a v dd = 3.0 v 10% 0.05 5.5 a power supply current note 1 ( pd78f9316) i dd5 stop mode note 6 v dd = 2.0 v 10% 0.05 3.5 a notes 1. the port current (including the cu rrent that flows to the on-chip pull-up resistors) is not included. 2. high-speed mode operation (when processor clock control register (pcc) is cleared to 00h) 3. low-speed mode operation (when pcc is set to 02h) 4. when the lcd is not operating and t he booster circuit is operating (lcdo n0 = 0, vaon0 = 1, lips0 = 1). 5. when the main system clock is stopped 6. when the lcd is not operating (lcdo n0 = 0, vaon0 = 0, lips0 = 0) 7. then the lcd is operating (lcdon0 = 1, vaon0 = 1, lips0 = 1) remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 22 electrical specifications user?s manual u14800ej2v0ud 296 ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8.0 s operating with main system clock v dd = 1.8 to 5.5 v 1.6 8.0 s cycle time (minimum instruction execution time) t cy operating with subsystem clock 114 122 125 s cpt20 input high-/low- level width t cpth , t cptl 10 s v dd = 2.7 to 5.5 v 0 4 mhz tmi40 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz v dd = 2.7 to 5.5 v 0.1 s tmi40 input high-/low- level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s interrupt input high- /low-level width t inth , t intl intp0 to intp3 10 s key return input low- level width t krl kr0 to kr3 10 s reset low-level width t rsl 10 s t cy vs v dd (main system clock) power supply voltage v dd (v) 123456 0.1 0.4 0.5 1.0 2.0 10 20 60 cycle time t cy [ s] guaranteed operation range
chapter 22 electrical specifications user?s manual u14800ej2v0ud 297 (2) serial interface 10, 20 (sio10, sio20) (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sckn0 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2?50 ns sckn0 high-/low-level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2?150 ns v dd = 2.7 to 5.5 v 150 ns sin0 setup time (to sckn0 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns sin0 hold time (from sckn0 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns delay time from sckn0 to son0 output t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the son0 output lines. remark n = 1, 2 (b) 3-wire serial i/o mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sckn0 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sckn0 high-/low-level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns sin0 setup time (to sckn0 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns sin0 hold time (from sckn0 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns delay time from sckn0 to son0 output t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and load capacitance of the son0 output lines. remark n = 1, 2
chapter 22 electrical specifications user?s manual u14800ej2v0ud 298 (c) uart mode (sio20 only) (dedi cated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps (d) uart mode (sio20 only) (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise/fall time t r , t f 1 s
chapter 22 electrical specifications user?s manual u14800ej2v0ud 299 ac timing test points (excluding x1 (cl1) and xt1 inputs) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing 1/f clk t xl t xh x1 (cl1) input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) remark f clk : f x or f cc capture input timing cpt20 t cptl t cpth tmi timing 1/f ti t til t tih tmi40 input interrupt input timing intp0 to intp3 t intl t inth
chapter 22 electrical specifications user?s manual u14800ej2v0ud 300 key return input timing kr00 to kr03 t krl reset input timing reset t rsl serial transfer timing 3-wire serial i/o mode: t kcym t klm t khm sck10, sck20 t sikm t ksim t ksom input data output data si10, si20 so10, so20 remark m = 1, 2 uart mode (external clock input): t kcy3 t kl3 t kh3 asck20 t r t f
chapter 22 electrical specifications user?s manual u14800ej2v0ud 301 lcd characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit gain = 1 0.84 1.0 1.165 v lcd output voltage variation range v lcd2 c1 to c4 note 1 = 0.47 f gain = 0 1.26 1.5 1.74 v doubler output v lcd1 c1 to c4 note 1 = 0.47 f 2 v lcd2 ? 0.1 2.0 v lcd2 2.0 v lcd2 v tripler output v lcd0 c1 to c4 note 1 = 0.47 f 3 v lcd2 ? 0.15 3.0 v lcd2 3.0 v lcd2 v gain = 0 1.8 v dd 5.5 v 0.5 s 5.0 v dd 5.5 v 2.0 s 4.5 v dd < 5.0 v 1.0 s voltage boost wait time note 2 t vawait gain = 1 1.8 v dd < 4.5 v 0.5 s lcd output voltage differential note 3 (common) v odc i o = 5 a 0 0.2 v lcd output voltage differential note 3 (segment) v ods i o = 1 a 0 0.2 v notes 1. this is a capacitor that is connected between voltage pins used to drive the lcd. c1: capacitor connected between caph and capl c2: capacitor connected between v lc0 and v ss c3: capacitor connected between v lc1 and v ss c4: capacitor connected between v lc2 and v ss 2. this is the wait time from when voltage boost is started (vaon0 = 1) until display is enabled (lcdon0 = 0). 3. the voltage differential is the difference between the segment and common signal output?s actual and ideal output voltages. data memory stop mode low supply vo ltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s oscillation stabilization wait time (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit release by reset 2 15 /f x s oscillation stabilization wait time note 1 (ceramic/crystal oscillation) t wait release by interrupt note 2 s release by reset 2 7 /f cc s oscillation stabilization wait time (rc oscillation) t wait release by interrupt 2 7 /f cc s notes 1. use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. 2. selection of 2 12 /f x , 2 15 /f x , or 2 17 /f x is possible with bits 0 to 2 (ost s0 to osts2) of the oscillation stabilization time select register (osts). remarks 1. f x : main system clock oscillation frequency (ceramic/crystal oscillation) 2. f cc : main system clock oscillation frequency (rc oscillation)
chapter 22 electrical specifications user?s manual u14800ej2v0ud 302 data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operation mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode release by interrupt signal) v dd data retention mode stop mode halt mode operation mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
chapter 22 electrical specifications user?s manual u14800ej2v0ud 303 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) ( pd78f9306, 78f9316) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1.0 5 mhz operating frequency f x , f cc v dd = 1.8 to 5.5 v 1.0 1.25 mhz ceramic oscillation during f x = 5.0 mhz operation 7 ma write current note 1 (v dd pin) i ddw when v pp supply voltage = v pp1 rc oscillation during f cc = 4.0 mhz operation note 2 9 ma write current note 1 (v pp pin) i ppw when v pp supply voltage = v pp1 12 ma ceramic oscillation during f x = 5.0 mhz operation 7 ma erase current note 1 (v dd pin) i dde when v pp supply voltage = v pp1 rc oscillation during f cc = 4.0 mhz operation note 2 9 ma erase current note 1 (v pp pin) i ppe when v pp supply voltage = v pp1 100 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s write count erase/write are regarded as 1 cycle 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v notes 1. the port current (including the cu rrent that flows to the on-chip pull-up resistors) is not included. 2. when an external clock is input
user?s manual u14800ej2v0ud 304 chapter 23 characteristics cur ves of lcd controller/driver (reference values) (1) characteristics curves of vo ltage boost stabilization time the following shows the characteristi cs curves of the time from the st art of voltage boost (vaon0 = 1) and the changes in the lcd output vo ltage (when gain is set as 1 (using the 3 v display panel)). lcd output voltage/voltage boost time v dd = 4.5 v 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 v dd = 5 v v dd = 5.5 v 0 500 1000 1500 2000 voltage boost time [ms] lcd output voltage [v] 2500 3000 3500 4000 v lcd0 v lcd1 v lcd2
chapter 23 characteristics curves of lcd controller/driver (reference values) user?s manual u14800ej2v0ud 305 (2) temperature characteristi cs of lcd output voltage the following shows the temper ature characteristics curv es of lcd output voltage. lcd output voltage/temperature (when gain = 1) lcd output voltage/temperature (when gain = 0) v lcd2 ? 40 5 4 3 2 1 0 ? 30 ? 20 ? 10 0 10 20 temperature [?c] lcd output voltage [v] 30 40 50 60 70 80 v lcd1 v lcd0 v lcd2 ? 40 5 4 3 2 1 0 ? 30 ? 20 ? 10 0 10 20 temperature [?c] lcd output voltage [v] 30 40 50 60 70 80 v lcd1 v lcd0
user?s manual u14800ej2v0ud 306 chapter 24 package drawings 48 49 32 64 1 17 16 33 64-pin plastic qfp (14x14) note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.6 0.4 14.0 0.2 0.8 (t.p.) 1.0 j 17.6 0.4 k p64gc-80-ab8-5 c 14.0 0.2 i 0.15 1.8 0.2 l 0.8 0.2 f 1.0 n p q 0.10 2.55 0.1 0.1 0.1 r s 5 5 2.85 max. h 0.37 + 0.08 ? 0.07 m 0.17 + 0.08 ? 0.07 s s n j detail of lead end c d a b r k m l p i s q g f m h
chapter 24 package drawings user?s manual u14800ej2v0ud 307 48 32 33 64 1 17 16 49 s s 64-pin plastic tqfp (12x12) item millimeters g 1.125 a 14.0 0.2 c 12.0 0.2 d f 1.125 14.0 0.2 b 12.0 0.2 n 0.10 p q 0.1 0.05 1.0 s r 3 + 4 ? 3 r h k j q g i s p detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. m h 0.32 + 0.06 ? 0.10 i 0.13 j k 1.0 0.2 0.65 (t.p.) l 0.5 m 0.17 + 0.03 ? 0.07 p64gk-65-9et-3 t u 0.6 0.15 0.25 f m a b cd n t l u 1.1 0.1
user?s manual u14800ej2v0ud 308 chapter 25 recommended soldering conditions the pd789306 and pd789316 subseries should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) table 25-1. surface mounting type soldering conditions (1/2) pd789304gc- -ab8: 64-pin plastic qfp (14 14) pd789306gc- -ab8: 64-pin plastic qfp (14 14) pd789314gc- -ab8: 64-pin plastic qfp (14 14) pd789316gc- -ab8: 64-pin plastic qfp (14 14) pd78f9306gc-ab8: 64-pin plastic qfp (14 14) pd78f9316gc-ab8: 64-pin plastic qfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: three times or less ir35-00-3 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: three times or less vp15-00-3 wave soldering soldering bath temperature: 260 c max., time: 10 seconds max., count: 1, preheating temperature: 120 c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering me thods together (except for partial heating).
chapter 25 recommended soldering conditions user?s manual u14800ej2v0ud 309 table 25-1. surface mounting type soldering conditions (2/2) pd789304gk- -9et: 64-pin plastic tqfp (fine pitch) (12 12) pd789306gk- -9et: 64-pin plastic tqfp (fine pitch) (12 12) pd789314gk- -9et: 64-pin plastic tqfp (fine pitch) (12 12) pd789316gk- -9et: 64-pin plastic tqfp (fine pitch) (12 12) pd78f9306gk-9et: 64-pin plasti c tqfp (fine pitch) (12 12) pd78f9316gk-9et: 64-pin plasti c tqfp (fine pitch) (12 12) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vp15-107-2 wave soldering soldering bath temperature: 260 c max., time: 10 seconds max., count: 1, preheating temperature: 120 c max. (package surface temperature), expos ure limit: 7 days note (after that, prebake at 125 c for 10 hours) ws60-107-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating).
user?s manual u14800ej2v0ud 310 appendix a development tools the following development tools are avail able for development of systems using the pd789306 and pd789316 subseries. figure a-1 shows development tools. ? support of pc98-nx series unless specified otherwise, the products supported by ibm pc/at? co mpatibles can be used in the pc98-nx series. when using the pc98-nx series, refer to the explanation of ibm pc/at compatibles. ? windows? unless specified otherwise, ?windows? i ndicates the following operating systems. ? windows 3.1 ? windows 95, 98, 2000 ? windows nt? ver.4.0
appendix a development tools user?s manual u14800ej2v0ud 311 figure a-1. development tools language processing software assembler package c compiler package device file c library source file note 1 debugging software integrated debugger system simulator host machine (pc or ews) interface adapter in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory writing adapter flash memory power supply unit software package control software project manager (windows version only) note 2 software package flash memory writing environment notes 1. c library source file is not included in the software package. 2. project manager is included in the assembler package. project manager is used only in the windows environment.
appendix a development tools user?s manual u14800ej2v0ud 312 a.1 software package software tools for development of the 78k/0 s series are combined in this package. the following tools are included. ra78k0s, cc78k0s, id78k0s-ns, sm78k0s, and device files sp78k0s software package part number: s sp78k0s remark in the part number differs depending on the operating system to be used. s sp78k0s host machine os supply medium ab17 japanese windows cd-rom bb17 pc-9800 series, ibm pc/at compatibles english windows a.2 language processing software program that converts program written in mnemonic into obj ect codes that can be executed by microcontroller. in addition, automatic functions to generate a symbol table and optimize branch instructions are also provided. used in combination with a device file (df789306) (sold separately). the assembler package is a dos-based app lication but may be used in the windows environment by using the proj ect manager of windows (included in the assembler package). ra78k0s assembler package part number: s ra78k0s program that converts program written in c language into objec t codes that can be executed by microcontroller. used in combination with an assembler package (ra78k0s) and device file (df789306) (both sold separately). the c compiler package is a dos-based app lication but may be used in the windows environment by using the proj ect manager of windows (included in the assembler package). cc78k0s c compiler package part number: s cc78k0s file containing the informat ion inherent to the device. used in combination with the ra78k0s, cc 78k0s, id78k0s-ns, and sm78k0s (all sold separately). df789306 note 1 device file part number: s df789306 source file of functions for generating obj ect library included in c compiler package. necessary for changing object library incl uded in c compiler package according to customer?s specificati ons. since this is a source f ile, its working environment does not depend on any particular operating system. cc78k0s-l note 2 c library source file part number: s cc78k0s-l notes 1. df789306 is a common file that can be used with ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. 2. cc78k0s-l is not included in the software package (sp78k0s).
appendix a development tools user?s manual u14800ej2v0ud 313 remark in the part number differs depending on the hos t machine and operating system to be used. s ra78k0s s cc78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5-inch 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at compatibles english windows 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) cd-rom s df789306 s cc78k0s-l host machine os supply medium ab13 japanese windows 3.5-inch 2hd fd bb13 pc-9800 series, ibm pc/at compatibles english windows 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 3.5-inch 2hd fd 3k15 sparcstation sunos (rel. 4.1.4), solaris (rel. 2.5.1) 1/4-inch cgmt a.3 control software project manager control software created for efficient development of the user program in the windows environment. user program dev elopment operations such as editor startup, build, and debugger startup can be performed from the project manager. the project manager is included in the assembler package (ra78k0s). the project manager is used onl y in the windows environment. a.4 flash memory writing tools flashpro iii (fl-pr3, pg-fp3) flashpro iv (fl-pr4, pg-fp4) flash programmer dedicated flash programmer for microcont rollers incorporating flash memory fa-64gc fa-64gk-9et flash memory writing adapter adapter for writing to flash memory and connected to flashpro iii or flashpro iv. ? fa-64gc: for 64-pin pl astic qfp (gc-ab8 type) ? fa-64gk-9et: for 64-pin plastic tqfp (gk-9et type) remark the fl-pr3, fl-pr4, fa-64gc, and fa-64gk-9et ar e products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191).
appendix a development tools user?s manual u14800ej2v0ud 314 a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging a hardware and software of application system using the 78k/0s series. supports an integrated debugger (i d78k0s-ns). used in combination with an ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-78k0s-ns-a in-circuit emulator the ie-78k0s-ns-a provides a coverage function in addition to the ie-78k0s-ns functions, thus enhancing the debug functions, includi ng the tracer and timer functions. ie-70000-mc-ps-b ac adapter adapter for supplying power from ac 100 to 240 v outlet. ie-70000-98-if-c interface adapter adapter necessary when using a pc-9800 seri es pc (except notebook type) as the host machine (c bus supported) ie-70000-cd-if-a pc card interface pc card and interface cable necessary w hen using a notebook pc as the host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter adapter necessary when using an ibm pc/at com patible as the host machine of the (isa bus supported) ie-70000-pci-if-a interface adapter adapter necessary when using a personal comput er incorporating the pci bus as the host machine ie-789306-ns-em1 emulation board board for emulating the peripheral hardware specific to the devic e. used in combination with an in-circuit emulator. np-64gc emulation probe cable to connect an in-circuit emulator to the target system. used in combination with the ev-9200g-64. ev-9200g-64 conversion socket conversion socket to connect the np-64gc to a target system board on which an 64-pin plastic qfp (gc-ab8 type) can be mounted. np-64gc-tq np-h64gc-tq emulation probe cable to connect an in-circuit emulator to the ta rget system. used in combination with the tgb- 064sap. tgb-064sap conversion adapter conversion adapter to connect t he np-64gc-tq or np-h64gc-tq to a target system board on which an 64-pin plastic qfp (g c-ab8 type) can be mounted. np-64gk np-h64gk-tq emulation probe cable to connect an in-circuit emulator to the ta rget system. used in combination with the tgk- 064sbw. tgk-064sbw conversion adapter conversion adapter to connect the np-64gk or np-h64gk-tq to a target system board on which an 64-pin plastic tqfp (fine pi tch) (gk-9et type) can be mounted. remarks 1. the np-64gc, np-64gc-tq, np-h64gc-tq, np-64gk, and np-h 64gk-tq are products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). 2. the tgc-064sap and tgk-064sbw are products made by tokyo eletech corporation. for further information, c ontact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672)
appendix a development tools user?s manual u14800ej2v0ud 315 a.6 debugging tools (software) this debugger supports the in-cir cuit emulators ie-78k0s-ns and ie-78k0s-ns-a for the 78k/0s series. the id78k0s-n s is windows-based software. it has improved c-compatible debuggi ng functions and can display the results of tracing with the source program using an integrating wi ndow function that associates the source program, disassemble display, and memo ry display with the trace result. used in combination with a device file (df789306) (sold separately). id78k0s-ns integrated debugger part number: s id78k0s-ns this is a system simulator for the 78k/0s series. the sm78k0s is windows-based software. it can be used to debug the target system at c source level or assembler level while simulating the operation of the target system on the host machine. using sm78k0s, the logic and performance of the application can be verified independently of hardware development. therefore, t he development efficiency can be enhanced and the software quality can be improved. used in combination with a device file (df789306) (sold separately). sm78k0s system simulator part number: s sm78k0s file containing the informat ion inherent to the device. used in combination with the ra78k0s, cc 78k0s, id78k0s-ns, and sm78k0s (all sold separately). df789306 note device file part number: s df789306 note df789306 is a common file that can be used with ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s. remark in the part number differs depending on the oper ating system and supply medium to be used. s id78k0s-ns s sm78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5-inch 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at compatibles english windows cd-rom
user?s manual u14800ej2v0ud 316 appendix b cautions on designing target system the following shows the conditions when connecting the emulation probe to the c onversion adapter. follow the configuration below and consider t he shape of parts to be mounted on the target system when designing a system. among the products described in this appendix, np-64gc-tq, np-h64gc-t q, np-64gk, and np-h64gk-tq are products of naito densei machi da mfg. co., ltd, and tgc-064sap and tg k-064sbw are products of tokyo eletech corporation. table b-1. distance between ie system and conversion adapter emulation probe conversion adapter distance between ie system and conversion adapter np-64gc-tq 170 mm np-h64gc-tq tgc-064sap 370 mm np-64gk 170 mm np-h64gk-tq tgk-064sbw 370 mm figure b-1. distance between in-circu it emulator and conversion adapter (when 64gc is used) note distance when np-64gc-tq is used. when np-h64gc-tq is used, the distance is 370 mm. 170 mm note in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789306-ns-em1 conversion adapter: tgc-064sap target system cn1 emulation probe np-64gc-tq np-h64gc-tq
appendix b cautions on designing target system user?s manual u14800ej2v0ud 317 figure b-2. connection conditions of targ et system (when np-64gc-tq is used) figure b-3. connection conditions of targ et system (when np-h64gc-tq is used) emulation probe np-64gc-tq emulation board ie-789306-ns-em1 23 mm 25 mm 40 mm 34 mm target system 20.65 mm pin 1 11 mm 20.65 mm conversion adapter tgc-064sap emulation probe np-h64gc-tq emulation board ie-789306-ns-em1 23 mm 23 mm 42 mm 45 mm target system 20.65 mm pin 1 11 mm conversion adapter tgc-064sap 20.65 mm
appendix b cautions on designing target system user?s manual u14800ej2v0ud 318 figure b-4. distance between in-circu it emulator and conversion adapter (when 64gk is used) note distance when np-64gk is used. when np-h 64gk-tq is used, the distance is 370 mm. figure b-5. connection conditions of ta rget system (when np-64gk is used) 170 mm note in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789306-ns-em1 conversion adapter tgk-064sbw target system cn1 emulation probe np-64gk, np-h64gk-tq emulation probe np-64gk emulation board ie-789306-ns-em1 21.95 mm 40 mm 34 mm target system 18.4 mm pin 1 11 mm 25 mm 18.4 mm conversion adapter tgk-064sbw
appendix b cautions on designing target system user?s manual u14800ej2v0ud 319 figure b-6. connection conditions of targ et system (when np-h64gk-tq is used) emulation probe np-h64gk-tq emulation board ie-789306-ns-em1 42 mm 45 mm 18.4 mm target system 18.4 mm pin 1 21.95 mm 23 mm conversion adapter tgk-064sbw 11 mm
user?s manual u14800ej2v0ud 320 appendix c register index c.1 register index (alphabetic order of register name) [a] asynchronous serial interfac e mode register 20 (asi m20)........................................................................ ...........193 asynchronous serial interface status register 20 (asi s20)...................................................................... .............195 [b] baud rate generator contro l register 20 (brg c20) ............................................................................... ...............196 [c] carrier generator output cont rol register 40 (t ca40) ........................................................................... ................139 [e] 8-bit compare regi ster 30 (cr30) ............................................................................................... ..........................134 8-bit compare regi ster 40 (cr40) ............................................................................................... ..........................134 8-bit compare regi ster h40 (crh 40) ............................................................................................. .......................134 8-bit timer count er 30 (t m30) .................................................................................................. .............................135 8-bit timer count er 40 (t m40) .................................................................................................. .............................135 8-bit timer mode contro l register 30 (tmc 30) ................................................................................... ....................137 8-bit timer mode contro l register 40 (tmc 40) ................................................................................... ....................138 external interrupt mode register 0 (intm0) ..................................................................................... .....................242 external interrupt mode register 1 (intm1) ..................................................................................... .....................243 [ i ] interrupt mask flag regist er 0, 1 (mk 0, mk1)................................................................................... .....................241 interrupt request flag regi ster 0, 1 (if0, if1)................................................................................ .........................240 [k] key return mode r egister 00 (krm00)............................................................................................ ......................244 [l] lcd clock control r egister 0 (lcdc0) ........................................................................................... .......................224 lcd display mode r egister 0 (lcdm 0)............................................................................................ .....................223 lcd voltage amplification cont rol register 0 (lcd va0) .......................................................................... ..............225 [o] oscillation stabilization time select regist er (osts) .......................................................................... ...................252 [p] port 0 (p0) .................................................................................................................... ..........................................77 port 1 (p1) .................................................................................................................... ..........................................78 port 2 (p2) .................................................................................................................... ..........................................79 port 3 (p3) .................................................................................................................... ..........................................83 port 5 (p5) .................................................................................................................... ..........................................85
appendix c register index user?s manual u14800ej2v0ud 321 port mode regist er 0 (p m0) ..................................................................................................... ............................... 86 port mode regist er 1 (p m1) ..................................................................................................... ............................... 86 port mode regist er 2 (p m2) ..................................................................................................... ............................... 86 port mode regist er 3 (p m3) ..................................................................................................... ............................... 86 port mode regist er 5 (p m5) ..................................................................................................... ............................... 86 processor clock cont rol regist er (pcc) ......................................................................................... ................. 93, 105 pull-up resistor option register 0 (pu0) ....................................................................................... ........................... 88 pull-up resistor option register b2 (pub2)..................................................................................... ......................... 88 pull-up resistor option register b3 (pub3)..................................................................................... ......................... 89 [r] receive buffer regi ster 20 (rxb20)............................................................................................. ......................... 191 [s] subclock control register (css) ................................................................................................ ..................... 95, 107 suboscillation mode r egister (sckm)............................................................................................ ................. 94, 106 serial operation mode r egister 10 (csim 10) ..................................................................................... ................... 182 serial operation mode r egister 20 (csim 20) ..................................................................................... ................... 192 serial shift regi ster 10 (sio10) ............................................................................................... .............................. 180 16-bit capture regi ster 20 (tcp20) ............................................................................................. .......................... 119 16-bit compare regi ster 20 (cr20) .............................................................................................. ......................... 119 16-bit timer count er 20 (t m20) ................................................................................................. ............................ 119 16-bit timer mode contro l register 20 (tmc 20).................................................................................. ................... 120 [t] transmit shift regi ster 20 (txs20)............................................................................................. ........................... 191 [w] watch timer mode contro l register (wtm)........................................................................................ .................... 170 watchdog timer clock sele ct register (wdcs).................................................................................... .................. 175 watchdog timer mode r egister (wdtm)............................................................................................ ................... 176
appendix c register index user?s manual u14800ej2v0ud 322 c.2 register index (alphabeti c order of register symbol) [a] asim20: asynchronous serial interface mode register 20 ......................................................................... .........193 asis20: asynchronous serial in terface status register 20 ....................................................................... ..........195 [b] brgc20: baud rate generator control r egister 20 ................................................................................ ...............196 [c] cr20: 16-bit compar e regist er 20............................................................................................... ....................119 cr30: 8-bit compar e regist er 30................................................................................................ .....................134 cr40: 8-bit compar e regist er 40................................................................................................ .....................134 crh40: 8-bit compar e register h40 .............................................................................................. ....................134 csim10: serial operati on mode regi ster 10...................................................................................... ..................182 csim20: serial operati on mode regi ster 20...................................................................................... ..................192 css: subclock c ontrol r egister ................................................................................................. .............. 95, 107 [ i ] if0: interrupt reques t flag regi ster 0......................................................................................... ...................240 if1: interrupt reques t flag regi ster 1......................................................................................... ...................240 intm0: external interr upt mode regi ster 0 ...................................................................................... .................242 intm1: external interr upt mode regi ster 1 ...................................................................................... .................243 [k] krm00: key return mode regist er 00 ............................................................................................. ...................244 [l] lcdc0: lcd clock cont rol regist er 0............................................................................................ .....................244 lcdm0: lcd display mode regist er 0 ............................................................................................. ..................233 lcdva0: lcd voltage amplificat ion control r egister 0 ........................................................................... .............225 [m] mk0: interrupt mask flag regist er 0 ............................................................................................ ...................241 mk1: interrupt mask flag regist er 1 ............................................................................................ ...................241 [o] osts: oscillation stabilizati on time select regi ster ........................................................................... ..............252 [p] p0: port 0..................................................................................................................... ................................77 p1: port 1..................................................................................................................... ................................78 p2: port 2..................................................................................................................... ................................79 p3: port 3..................................................................................................................... ................................83 p5: port 5..................................................................................................................... ................................85 pcc: processor clo ck control regist er.......................................................................................... ........... 93, 105 pm0: port mode register 0 ...................................................................................................... ........................86
appendix c register index user?s manual u14800ej2v0ud 323 pm1: port mode register 1 ...................................................................................................... ....................... 86 pm2: port mode register 2 ...................................................................................................... ....................... 86 pm3: port mode register 3 ...................................................................................................... ....................... 86 pm5: port mode register 5 ...................................................................................................... ....................... 86 pu0: pull-up resistor option regi ster 0 ........................................................................................ ................... 88 pub2: pull-up resistor option regi ster b2 ...................................................................................... ................... 88 pub3: pull-up resistor option regi ster b3 ...................................................................................... ................... 89 [r] rxb20: receive bu ffer regist er 20 .............................................................................................. ......................191 [s] sckm: suboscillati on mode r egister ............................................................................................. .............94, 106 sio10: serial si ft regist er 10 ................................................................................................. ...........................180 [t] tca40: carrier generator out put control r egister 40 ............................................................................ .............139 tcp20: 16-bit capt ure regist er 20 .............................................................................................. .......................119 tm20: 16-bit time r counter 20 .................................................................................................. .......................119 tm30: 8-bit time r counter 30 ................................................................................................... ........................135 tm40: 8-bit time r counter 40 ................................................................................................... ........................135 tmc20: 16-bit timer mode control regi ster 20 ................................................................................... ................120 tmc30: 8-bit timer mode control regi ster 30 .................................................................................... .................137 tmc40: 8-bit timer mode control regi ster 40 .................................................................................... .................138 txs20: transmit sh ift regist er 20 .............................................................................................. .......................191 [w] wdcs: watchdog timer clo ck select regist er ..................................................................................... ..............175 wdtm: watchdog time r mode r egister ............................................................................................. ................176 wtm: watch timer m ode control regist er ......................................................................................... ..............170
user?s manual u14800ej2v0ud 324 appendix d revision history d.1 major revisions in this edition (1/2) page description pp.39, 46 modification of pin handling in 3.2.15 v pp ( pd78f9306 only) and 4.2.15 v pp ( pd78f9316 only) pp.40, 48 modification of table 3-1 and table 4-1 types of pin input/output circuits p.53 correction of interrupt request neme in table 5-2. vector table p.62 modification of descriptions about symbol in 5.2.3 special function registers (sfrs) p.78 correction of figure 6-3. block diagram of p10 to p13 pp.94, 106 addition of note about feedback resistor in figure 7-3 and figure 8-3 pp.123, 125 modification of descriptions in 9.4.1 operation as timer interrupt and 9.4.2 operation as timer output p.128 addition of 9.5 cautions on using 16-bit timer 20 p.134 10.2 8-bit timer 30, 40 configuration ? modification of figure 10-3. block diagram of output controller (timer 40) ? modification of cautions in (1) 8-bit compare register 30 (cr30) ? addition of descriptions in (2) 8-bit compare register 40 (cr40) ? addition of descriptions in (3) 8-bit compare register h40 (crh40) p.139 addition of cautions in figure 10-6. format of carrier generator output control register 40 p.158 addition of descriptions and cautions in 10.4.3 operation as carrier generator p.165 10.5 notes on using 8-bit timer 30, 40 ? modification of descriptions in (1) error on starting timer ? addition of (2) count value if external clock input from tmi40 pin is selected p.189 modification of figure 14-1. block diagram of serial interface 20 p.195 modification of description about pe flag in figure 14-5. format of asynchronous serial interface status register 20 p.196 modification of cautions in figure 14-6. format of baud rate generator control register 20 p.201 addition of description about reading receive data in 14.4.2 asynchronous serial interface (uart) mode p.217 division of figure 14-11. 3-wire serial i/o mode timing into master operation and slave operation. p.220 addition of figure 15-1. correspondence with lcd display ram p.221 modification of figure 15-2. block diagram of lcd controller/driver p.222 15.3 registers controlling lcd controller/driver ? modification of description about lcdon0, vaon0 in (1) lcd display mode register 0 (lcdm0) ? addition of description about frame frequencie in (2) lcd clock control register 0 (lcdc0) ? modification of description about gain in (3) lcd voltage amplification control register 0 (lcdva0) p.235 addition of 15.8 supplying lcd drive voltages v lc0 , v lc1 , and v lc2 p.240 addition of cautions in figure 16-2. format of interrupt request flag registers p.244 addition of cautions in figure 16-7. format of key return mode register 00 p.263 overall revision of contents rela ted to flash memory programming as 19.1 flash memory characteristics p.285 addition of chapter 22 electrical specifications p.304 addition of chapter 23 characteristics curves of lcd controller/driver (reference values) p.306 addition of chapter 24 package drawings p.308 addition of chapter 25 recommended soldering conditions
appendix d revision history user?s manual u14800ej2v0ud 325 (2/2) page description p.310 overall revision of contents of appendix a development tools deletion of embedded software p.316 addition of appendix b cautions on designing target system p.324 addition of appendix d revision history

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