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cat24aa01, cat24aa02 ? 2008 scillc. all rights reserved. 1 doc. no. md-1120 rev. c characteristics subject to change without notice 1-kb and 2-kb i 2 c cmos serial eeprom features ? supports standard and fast i 2 c protocol ? 1.7 v to 5.5 v supply voltage range ? 16-byte page write buffer ? hardware write protection for entire memory ? schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda) ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial temperature range ? rohs-compliant tsot-23 5-lead and soic 8-lead packages description the cat24aa01/24aa02 are 1-kb and 2-kb cmos serial eeprom devices internally or ganized as 128x8/256x8 bits. they feature a 16-byte page write buffer and support both the standard (100khz) and the fast (400khz) i 2 c protocols. in contrast to the cat24c01/24c02, the cat24aa01/24aa02 have no external address pins, and are therefore suitable in applications that require a single cat24aa01/02 on the i 2 c bus. for ordering information details, see page 12. pin configuration soic (w) nc 1 8 v cc nc 2 7 wp nc 3 6 scl v ss 4 5 sda tsot-23 (td) scl 1 5 wp v ss 2 sda 3 4 v cc * for the location of pin 1, please consult the corresponding package drawing. pin functions functional symbol pin name function sda serial data/address scl clock input wp write protect v cc power supply v ss ground v cc v ss sda scl wp cat24aa02 cat24aa01
cat24aa01, cat24aa02 doc. no. md-1120 rev. c 2 ? 2008 scillc. all rights reserved. characteristics subject to change without notice absolute maximum ratings (1) parameters ratings units storage temperature ?65 to +150 oc voltage on any pin with respect to ground (2) ?0.5 to +6.5 v reability characteristics (3) symbol parameter min units n end (4) endurance 1,000,000 program/erase cycles t dr data retention 100 years d.c. operating characteristics v cc = 1.7 v to 5.5 v, t a = -40c to 85c, unless otherwise speci ed. symbol parameter test conditions min max units i ccr read current read, f scl = 400 khz 0.5 ma i ccw write current write 1 ma i sb standby current all i/o pins at gnd or v cc 1 a i l i/o pin leakage pin at gnd or v cc 1 a v il input low voltage -0.5 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc 2.5 v, i ol = 3.0 ma 0.4 v v ol2 output low voltage v cc < 2.5 v, i ol = 1.0 ma 0.2 v pin impedance characteristics v cc = 1.7 v to 5.5 v, t a = -40c to 85c, unless otherwise speci ed. symbol parameter conditions max units c in (3 ) sda i/o pin capacitance v in = 0 v 8 pf c in (3 ) input capacitance (other pins) v in = 0 v 6 pf v in < v i h 100 i wp (5 ) wp input current v in > v i h 1 a notes: (1) stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ra tings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability. (2) the dc input voltage on any pin should not be lower than -0.5v or higher than v cc + 0.5v. during transitions, the voltage on any pin may undershoot to no less than -1.5v or overshoot to no more than v cc + 1.5v, for periods of less than 20ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropr iate aec-q100 and jedec test methods. (4) page mode @ 25c (5) when not driven, the wp pin is pulled down to gnd internal ly. for improved noise immunity, the internal pull-down is relat ively strong; therefore the external driver must be able to supply t he pull-down current when attempting to drive the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x v cc ), the strong pull-down reverts to a weak current source.
cat24aa01, cat24aa02 ? 2008 scillc. all rights reserved. 3 doc. no. md-1120 rev. c characteristics subject to change without notice a.c. characteristics (1) v cc = 1.7 v to 5.5 v, t a = -40c to 85c. standard fast symbol parameter min max min max units f sc l clock frequency 100 400 khz t hd:st a start condition hold time 4 0.6 s t lo w low period of scl clock 4.7 1.3 s t hig h high period of scl clock 4 0.6 s t su:st a start condition setup time 4.7 0.6 s t hd:da t data in hold time 0 0 s t su:da t data in setup time 250 100 ns t r sda and scl rise time 1000 300 ns t f (2 ) sda and scl fall time 300 300 ns t su:st o stop condition setup time 4 0.6 s t bu f bus free time between stop and start 4.7 1.3 s t a a scl low to data out valid 3.5 0.9 s t d h data out hold time 100 100 ns t i (2 ) noise pulse filtered at scl and sda inputs 100 100 ns t su:w p wp setup time 0 0 s t hd:w p wp hold time 2.5 2.5 s t w r write cycle time 5 5 ms t pu (2, 3 ) power-up to ready mode 1 1 ms a.c. test conditions notes: (1) test conditions according to ?a.c. test conditions? table. (2) tested initially and after a design or process change that affects this parameter. (3) t pu is the delay between the time v cc is stable and the device is ready to accept commands. input levels 0.2 x v cc to 0.8 x v c c input rise and fall times 50n s input reference levels 0.3 x v cc , 0.7 x v c c output reference levels 0.5 x v c c output load current source: i ol = 3ma (v c c 2.5v); i ol = 1ma (v cc < 2.5v); c l = 100p f
cat24aa01, cat24aa02 doc. no. md-1120 rev. c 4 ? 2008 scillc. all rights reserved. characteristics subject to change without notice power-on reset (por) each cat24aa01/02 incorporates power-on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and w ill power down into reset mode when v cc drops below the por trigger level. this bi-directional por behavior protects the device against brown-out failure, following a temporary loss of power. pin description scl: the serial clock input pin accepts the clock signal generated by the master. sda: the serial data i/o pin accepts input data and delivers output data. in transmit mode, this pin is open drain. data is acquired on the positive edge, and delivered on the negative edge of scl. wp: when the write protect input pin is forced high by an external source, all write operations are inhibited. when the pin is not driven by an external source, it is pulled low internally. functional description the cat24aa01/02 supports the inter-integrated circuit (i 2 c) bus protocol. the protocol relies on the use of a master device, which provides the clock and directs bus traffic, and sl ave devices which execute requests. the cat24aa01/02 operates as a slave device. both master and slave can transmit or receive, but only the master can assign those roles. i 2 c bus protocol the 2-wire i 2 c bus consists of two lines, scl and sda, connected to the v cc supply via pull-up resistors. the master provides the clock to the scl line, and the master and slaves drive the sda line. a ?0? is transmitted by pulling a line low and a ?1? by releasing it high. data tran sfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, sda must remain stable while scl is high. start/stop condition an sda transition while scl is high creates a start or stop condition (figure 1). a start is generated by a high to low transition, while a stop is generated by a low to high transition. the start acts like a wake-up call. absent a start, no slave will respond to the master. the stop completes all commands. device addressing the master addresses a slave by creating a start condition and then broadcasting an 8-bit slave address (figure 2). the first four bits of the slave address are 1010 (ah). for the cat24aa01/02 the next three bits must be 000. the last bit, r/w , instructs the slave to either provide (1) or accept (0) data, i.e. it signals a read (1) or a write (0) request. acknowledge during the 9 th clock cycle following every byte sent onto the bus, the transmitter releases the sda line, allowing the receiver to respond. the receiver then either acknowledges (ack ) by pulling sda low, or does not acknowledge (noack) by letting sda stay high (figure 3). bus timing is illustrated in figure 4.
cat24aa01, cat24aa02 ? 2008 scillc. all rights reserved. 5 doc. no. md-1120 rev. c characteristics subject to change without notice figure 1: start/stop timing figure 2: slave address bits 1 0 1 0 0 0 0 r/w figure 3: acknowledge timing figure 4: bus timing start condition stop condition sda scl 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack delay ( t aa ) ack setup ( t su:dat ) t high scl sda in sd a out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh
cat24aa01, cat24aa02 doc. no. md-1120 rev. c 6 ? 2008 scillc. all rights reserved. characteristics subject to change without notice write operations byte write to write data to memory, the master creates a start condition on the bus and then broadcasts a slave address with the r/w bit set to ?0?. the master then sends an address byte and a data byte and concludes the session by creating a stop condition on the bus. the slave responds with ack after every byte sent by the master (figure 5). the stop starts the internal write cycle, and while this operation is in progress (t wr ), the sda output is tri-stated and the slave does not acknowledge the master (figure 6). page write the byte write operation can be expanded to page write, by sending more than one data byte to the slave before issuing the stop condition (figure 7). up to 16 distinct data bytes can be loaded into the internal page write buffer starting at the address provided by the master. the page address is latched, and as long as the master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). new data can therefore replace data loaded earlier. following the stop, data loaded during the page write session will be written to memory in a single internal write cycle (t wr ). acknowledge polling as soon (and as long) as internal write is in progress, the slave will not acknowledge the master. this feature enables the master to immediately follow-up with a new read or write request, rather than wait for the maximum speci ed write time (t wr ) to elapse. upon receiving a noack response from the slave, the master simply repeats the request until the slave responds with ack. hardware write protection with the wp pin held high, the entire memory is protected against write operations. if the wp pin is left oating or is grounded, it has no impact on the write operation. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the 1 st data byte (figure 8). if the wp pin is high during the strobe interval, the slave will not acknowledge the data byte and the write r equest will be rejected. delivery state the cat24aa01/02 is shipped erased, i.e., all bytes are ffh.
cat24aa01, cat24aa02 ? 2008 scillc. all rights reserved. 7 doc. no. md-1120 rev. c characteristics subject to change without notice figure 5: byte write sequence figure 6: write cycle timing figure 7: page write sequence figure 8: wp timing t wr stop condition start condition address ack 8 th bit byte n scl sda 1891 8 a 7 a 0 d 7 d 0 t su:wp t hd:wp address byte data byte scl sda wp address byte data byte slave address s a c k a c k a c k s t o p p s t a r t bus activity: master slave a 7 a 0 d 7 d 0 a c k a c k a c k s t o p s a c k a c k s t a r t p slave address n = 1 x 15 address byte data byte n data byte n+1 data byte n+x bus activity: master slave
cat24aa01, cat24aa02 doc. no. md-1120 rev. c 8 ? 2008 scillc. all rights reserved. characteristics subject to change without notice read operations immediate read to read data from memory, the master creates a start condition on the bus and then broadcasts a slave address with the r/w bit set to ?1?. the slave responds with ack and starts shifting out data residing at the current address. after receiving the data, the master responds with noack and terminates the session by creating a stop condition on the bus (figure 9). the slave then returns to standby mode. selective read to read data residing at a speci c address, the selected address must rst be loaded into the internal address register. this is done by starting a byte write sequence, whereby the master creates a start condition, then broadcasts a slave address with the r/w bit set to ?0? and then sends an address byte to the slave. rather than completing the byte write sequence by sending data, the master then creates a start condition and broadcasts a slave address with the r/w bit set to ?1?. the slave responds with ack after every byte sent by the master and then sends out data residing at the selected address. after receiving the data, the master responds with noack and then terminates the session by creating a stop condition on the bus (figure 10). sequential read if, after receiving data sent by the slave, the master responds with ack, then the slave will continue transmitting until the master responds with noack followed by stop (figure 11). during sequential read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. for the cat24aa01, the internal address counter will not wrap around at the end of the 128 byte memory space.
cat24aa01, cat24aa02 ? 2008 scillc. all rights reserved. 9 doc. no. md-1120 rev. c characteristics subject to change without notice figure 9: immediate read sequence and timing figure 10: selective read sequence slave s a c k n o a c k s t o p p s t a r t s a c k slave address a c k s t a r t data byte address byte address bus activity: master slave figure 11: sequential read sequence a c k a c k a c k s t o p n o a c k a c k p slave address data byte n data byte n+1 data byte n+2 data byte n+x bus activity: master slave scl sda 8 th bit stop no ack data out 89 slave address s a c k data byte n o a c k s t o p p s t a r t bus activity: master slave
cat24aa01, cat24aa02 doc. no. md-1120 rev. c 10 ? 2008 scillc. all rights reserved. characteristics subject to change without notice package outline drawings soic 8-lead 150mils (w) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec standard ms-012. e1 e a a1 h l c e b d pin # 1 identification top view side view end view a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 5.80 6.20 e1 3.80 4.00 e 1.27 bsc h 0.25 0.50 l 0.40 1.27 0o 8o symbol min nom max for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat24aa01, cat24aa02 ? 2008 scillc. all rights reserved. 11 doc. no. md-1120 rev. c characteristics subject to change without notice tsot 5-lead (td) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec standard mo-193. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 e a2 a1 e b d c a top view side view end view l1 l l2 symbol min nom max a1.00 a1 0.01 0.05 0.10 a2 0.80 0.87 0.90 b 0.30 0.45 c 0.12 0.15 0.20 d 2.90 bsc e 2.80 bsc e1 1.60 bsc e0.95typ l 0.30 0.40 0.50 l1 0.60 ref l2 0.25 bsc 0o 8o
cat24aa01, cat24aa02 doc. no. md-1120 rev. c 12 ? 2008 scillc. all rights reserved. characteristics subject to change without notice example of ordering information (1) notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard plated finish is nipdau. (3) the device used in the above example is a cat24aa02tdi-gt3 (tsot-23 5-lead, industrial temperature, nipdau, tape & reel, 3,000/reel). (4) for additional package and temperature options, please contact your nearest on semiconductor sales office. prefix device # suffix cat 24aa02 td i ? g t3 company id package td: tsot-23 5-lead w: soic 8-lead temperature range i: industrial ( -40oc to 85oc ) tape & reel t: tape & reel 3: 3,000/reel 10: 10 , 000/reel lead finish g: nipdau blank: matte-tin product numbe r 24aa01 24aa02 for product top mark codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp
cat24aa01, cat24aa02 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representati on or guarantee regarding the suitab ility of its products for any partic ular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, an d specifically disclaims any and all liability, including without limita tion special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performa nce may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death ma y occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiarie s, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opport unity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution ce nter for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support : 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center: phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ? 2008 scillc. all rights reserved. 13 doc. no. md-1120 rev. c characteristics subject to change without notice revision history date revision description 07-dec-07 a initial issue 12-mar-08 b add cat24aa01 add link to product top mark code 23-oct-08 c change logo and fine print to on semiconductor

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