low cost vmebus interface controller family cy7c960a cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 september 5, 2000 features ? 80-mbyte-per-second block transfer rates all vme64 transactions provided, including a64/d64, a40/md32 transfers auto slot id cr/csr space all standard (rev. c) vmebus transactions implemented vmebus interrupter no local cpu required programmable from vmebus, serial prom, or local bus dram controller, including refresh local i/o controller flexible vmebus address scheme user-configured vmebus response 64-pin tqfp, 10x10 mm (cy7c960a) functional description the cy7c960a slave vmebus interface controller provides the board designer with an integrated, full-featured vme64 in- terface. this 64-pin device can be programmed to handle every transaction defined in the vme64 specification. the cy7c960a contains all the circuitry needed to control large dram arrays and local i/o circuitry without the interven- tion of a local cpu. there are no registers to read or write, no complex command blocks to be constructed in memory. the cy7c960a simply fetches its own configuration parameters during the power-on reset period. after reset the cy7c960a responds appropriately to vmebus activity and controls local circuitry transparently. vme control interf ace cy7c960a logic block diagram c960?1 region/ am table cy7c964 controller power-on reset generator am [5:0] sysreset* as* ds0* ds1* dtack* write* clk region [3:0] irq* iack* iackin* iackout* local address controller chip select output pattern table data byte enable controller databyte lane decoder local control circuit dram controller refresh controller timing generator vme interrupt interface cs[5:0] dbe [3:0] lack* lden* pren* swden* r/w* ras* cas* row col lirq* d64 strobe deno* denin* denin1* ladi laen ledi ledo aben* lds la [7:1] lword
cy7c960a 2 functional description (continued) the cy7c960a controls a bridge between the vmebus and local dram and i/o. once programmed, the cy7c960a pro- vides activities such as dram refresh and local i/o handshak- ing in a manner that requires no additional local circuitry. the vmebus control signals are connected directly to the cy7c960a. the vmebus address and data signals are con- nected to companion address/data transceivers which are controlled by the cy7c960a. the cy7c964 vmebus inter- face logic circuit is an ideal companion device: the cy7c964 provides a slice of data and address logic that has been opti- mized for vme64 transactions. in addition to providing the specified drive strength and timing for vme64 transactions, the cy7c964 contains all the circuitry needed to multiplex the ad- dress/data bus for multiplexed vmebus transactions. it con- tains counters and latches needed during blt operations; and it also contains address comparators which can be used in the board ? s slave address decoder. for a 6u or 9u application, four cy7c964 devices are controlled by a single cy7c960a. for 3u applications, the cy7c960a controls two cy7c964 devices and an address latch. the design of the cy7c960a makes it unnecessary to know the details of the vmebus transaction timing and protocol. the complex vmebus activities are translated by cy7c960a to simple local cycles involving a few familiar control signals. sim- ilarly, it is not necessary to understand the operation of the companion device, cy7c964: all control sequences for the part are generated automatically by the cy7c960a in re- sponse to vmebus or local activity. if more information is de- sired, consult the cy7c964 chapter in the vmebus interface handbook. vmebus transactions supported by the cy7c960a include d8, d16, d32 (incl. uat), md32, d64, a16, a24, a32, a40, a64 single-cycle and block-transfer reads and writes, read-modify-write cycles (incl. multiplexed), and ad- dress-only (with or without handshake). the cy7c960a func- tions as a vmebus interrupter, and supports the new auto slot id standard and cr/csr space. the cy7c960a also handles lock cycles, although full lock support is not possible within the constraints of the cy7c960a pinout. on the local side, no cpu is needed to program the cy7c960a, nor to manage transactions. all programmable parameters are initialized through the use of either the vmebus, a serial prom, or some other local circuit. as the cy7c960a incor- porates a reliable power-on reset circuit, parameters are self-loaded by the device at power-up or after a system reset. if the vmebus is used to provide parameters, a vmebus master provides the pro- gramming information using a protocol, described in the handbook, which is compliant with the auto slot id protocol from the new vme64 specification. to assist in generating the configuration file, a win- dows ? -based program, winsvic software, is available on the web which guides the user through the process of selecting appropriate options. contact your sales office for further details. cy7c960a 64 63 61 62 60 2 3 1 32 33 34 12 13 15 14 16 4 5 31 30 59 58 17 9 10 8 7 6 11 18 19 21 20 22 23 26 25 2728 29 24 40 39 37 38 36 35 41 42 43 48 46 47 45 44 53 52 50 51 49 57 56 la7 am1 gnd r/w swden* ras*/cs4 cas*/cs5 am2 row/cs2 pren* la6 la5 la4 irq* la3 la1 am5 vcc ds1* lword laen la2 dtack* d64 ledo ledi iackout* iackin* iack* as* ladi deno* lack* lirq* lden* cs0 cs1 am3 gnd region1 region0 denin* region2 54 55 col/cs3 gnd am0 vcc dbe1 dbe2 dbe3 dbe0 strobe aben* gnd ds0* vcc lds denin1* vcc write* region3/cs2 am4 pin configuration sysreset* clk top view
cy7c960a 3 system diagram using the cy7c960a swden rw dbe [3:0], rw lack* ras*, cas*, row, col la [31:0] d[31:16] swap buffer ld[15:0] la [31:0] cy7c964 drammemory i/o lirq* decoder region la [7:1, lword] a [31:1], lword* vmei nterrupt bus vme address bus vmedatabus cy7c964 cy7c964 cy7c964 cy7c960a cs[2:0] irq* iack* iackin* iackout* ds1/0* dtack write* sysreset* d[31:0] am[5:0] as* d[7:0] d[15:8] a[7:1], lword* a[15:8] d[23:16] a[23:16] d[31:24] a[31:24] vcomp
cy7c960a 4 dc specifications - vmebus signals as*, ds1*, ds0*, dtack* parameter description test conditions comm. industrial military units v ih minimum high-level input voltage 2.0 2.0 2.0 v v il maximum low-level input voltage 0.8 0.8 0.8 v v oh minimum high-level output voltage v cc = min., i oh = 2.4 ? 16 ma 2.4 ? 10 ma 2.4 ? 9 ma v v ol maximum low-level output voltage v cc = min., i ol = 0.6 64 ma 0.6 60 ma 0.6 52 ma v i l maximum input leakage current v cc = max., gnd < v in < v cc 5 5 5 a v ik input clamp voltage v cc = min., i in = ? 18 ma ? 1.2 ? 1.2 ? 1.2 v i oz maximum output leakage current v cc = max. gnd < v out < v cc outputs disabled 10 10 10 a dc specifications - vmebus signals am5, am4, am3, am2, am1, am0, irq*, write parameter description test conditions comm. industrial military units v ih maximum high-level input voltage 2.0 2.0 2.0 v v il maximum low-level input voltage 0.8 0.8 0.8 v v oh minimum high-level output voltage v cc = min., i oh = 2.4 ? 16 ma 2.4 ? 10 ma 2.4 ? 9 ma v v ol minimum low-level output voltage v cc = min., i ol = 0.6 48 ma 0.6 44 ma 0.6 38 ma v i l maximum input leakage current v cc = max., gnd < v in < v cc 5 5 5 a v ik input clamp voltage v cc = min., i in = ? 18 ma ? 1.2 ? 1.2 ? 1.2 v i oz maximum output leakage current v cc = max. gnd < v out < v cc outputs disabled 5 5 10 a dc specifications - all other output signals [1] parameter description test conditions comm. industrial military units v ih maximum high-level input voltage 2.0 2.0 2.0 v v il maximum low-level input voltage 0.8 0.8 0.8 v v oh minimum high-level output voltage v cc = min., i oh = 2.4 ? 16 ma 2.4 ? 10 ma 2.4 ? 9 ma v v ol minimum low-level output voltage v cc = min., i ol = 0.6 20 ma 0.6 18 ma 0.6 16 ma v i l maximum input leakage current v cc = max., gnd < v in < vcc 5 5 5 a v ik input clamp voltage v cc = min., i in = ? 18 ma ? 1.2 ? 1.2 ? 1.2 v i oz maximum output leakage current v cc = max. gnd < v out < v cc outputs disabled 5 5 10 a note: 1. some signals have an on-chip pull-up or pull-down resistors. for these signals i oz value is modified.
cy7c960a 5 related documents vmebus interface handbook capacitance - all signals parameters description test conditions max. units c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 15 pf c out output capacitance 15 pf pullup/pulldown current - all signals parameters description test conditions typ. max. i pu input pull-up current t a = ? 55 c, v cc = 5.5v v in = gnd 100 a 250 a i pu input pull-up current t a = ? 55 c, v cc = 5.5v v in = v cc 100 a 250 a operating current (cy7c960a) parameters description test conditions max. units i dd maximum operating current no external dc load 100 ma ordering information ordering code package name package type operating range CY7C960A-ASC a64 10x10 mm body 64-lead plastic thin quad flatpack commercial cy7c960a-nc n65 14x14 mm body 64-lead plastic thin quad flatpack cy7c960a-um u65 14x14 mm body 64 lead ceramic quad flatpack military cy7c960a-umb u65 14x14 mm body 64 lead ceramic quad flatpack windows is a trademark of microsoft corporation. document #: 38-00250-e
cy7c960a 6 package diagrams 64-pin thin plastic quad flat pack (10 x 10 x 1.4 mm) a64 51-85051-a
cy7c960a 7 package diagrams (continued) 64-lead plastic thin quad flatpack n65
cy7c960a ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 64-lead ceramic quad flatpack (cavity up) u65
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