? 2006 california micro devices corp. all rights reserved. 08/16/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 1 cm3202 preliminary features ? two linear regulators -maximum 2a current from vddq -source and sink up to 2a vtt current ? 1.7v to 2.8v adjustable vddq output voltage ? 500mv typical vddq dropout voltage at 2a ? vtt tracking at 50% of vddq ? excellent load and line regulation, low noise ? fast transient response ? meet jedec ddr-i and ddr- ii memory power spec. ? linear regulator design requires no inductors and has low external component count ? integrated power mosfets ? dual purpose adj/shutdown pin ? built-in over-current limit and thermal shutdown for vddq and vtt ? fast transient response ? low quiescent current ? tdfn-8 rohs compliant lead-free package ? 8-lead soic package applications ? ddr memory and active termination buses ? desktop computers, servers ? residential and enterprise gateways ? dsl modems ? routers and switchers ? dvd recorders ? 3d agp cards ? lcd tv and stb product description t he cm3202 is a dual-output low noise linear regulator designed to meet sstl-2 and sstl-3 specifications for ddr-sdram v ddq supply and termination voltage v tt supply. with integrat ed power mosfet?s, the cm3202 can source up to 2a of vddq continuous cur- rent, and source or sink up to 2a vtt continuous cur- rent. the typical dropout voltage for vddq is 500 mv at 2a load current. the cm3202 provides fast response to transient load changes. load regulation is excellent, from no load to full load. it also has built-in over-current limits and ther- mal shutdown at 170 c . the cm3202 supports suspend to ram (str) and acpi compliance with shutdo wn mode which tri-states vtt to minimize quiescent system current. the cm3202 is packaged in an easy-to-use tdfn-8. low thermal resistance allo ws it to withstand high power dissipation at 85 c ambient. it can operate over the industrial ambient temperature range of ?40 c to 85 c . 1 3 2 dl0 vddq chip set dln ddr memory ref r2 10k r1 10k vddq rt0 rtn 220u/ 10v 220u/ 10v v in = 3.3v to 3.6v 1. 25v , 2.5a s/d 1u/10v cer 1k 4.7uf/10v cer adjsd nc vddq vtt vin cm3202 v ref gnd 4 nc 8 6 7 5 220uf/ 10v 4.7uf/ 10v cer 4.7uf/10v, cer vtt gnd v tt =1.25v/2a c tt c in v ddq =2.5v/2a c ddq typical application ddr vddq and vtt terminat ion voltage regulator
? 2006 california micro devices corp. all rights reserved. 2 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 08/16/06 cm3202 preliminary pin descriptions package / pinout diagram 8-lead tdfn package CM3202-00DE top view note: these drawings are not to scale. adjsd bottom view gnd 7 8 pad 4 3 2 1 5 6 (pins down view) (pins up view) 1 2 3 4 8 7 6 5 ? ? ? ? ? ? ? ? cm3202 00sm 8-lead soic package cm3202-00sm top view (pins down view) 2 1 5 6 7 8 4 vtt nc vin vddq gnd gnd pin 1 marking 3 nc cm320 200de pin descriptions lead(s) name description 1 vin input supply voltage pin. bypass with a 220 f capacitor to gnd. 2 nc not internally connected. for better heat flow, connect to gnd (exposed pad). 3vtt vtt regulator output pin, which is preset to 50% of v ddq . 4 nc not internally connected. for better heat flow, connect to gnd (exposed pad). 5 gnd ground pin (analog). 6 gnd ground pin (power). 7adjsd this pin is for v ddq output voltage adjustment. it is available as long as v ddq is enabled. during manual/thermal shutdo wn, it is tightened to gnd. the v ddq output voltage is set using an external resistor divider connected to adjsd: where r1 is the upper resistor a nd r2 is the ground-side resistor. in addition, the adjsd pin functions as a shutdown pin. when adjsd voltage is higher than 2.7v (shdn_h), the circuit is in shutdown mode. when adjsd voltage is below 1.5v (shdn_l), both v ddq and vtt are enabled. a low-leakage schottky diode in series with adjsd pin is recommended to avoid interference with the voltage adjustment setting. 8 vddq vddq regulator output voltage pin. epad gnd the backside exposed pad which serves as the package he atsink. must be connected to gnd. v ddq 1.25v r1 r2 + r2 -------------------- - = package pinout
? 2006 california micro devices corp. all rights reserved. 08/16/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 3 cm3202 preliminary note 1: parts are shipped in tape & reel form unless otherwise specified. specifications note 1: despite the fact that the device is designed to handle large continuous/peak output current s it is not capable of handli ng these under all conditions. limited by the package thermal re sistance, the maximum output current of the device cann?t exceeds the limit imposed by the maximum power dissipation value. note 2: measured with the package using a 4 sq inch / 2 layers pcb with thermal vias. part numbering information pins package lead-free finish ordering part number 1 part marking 8 tdfn CM3202-00DE cm320 200de 8 soic cm3202-00sm cm3202 00sm absolute maximum ratings parameter rating units vin to gnd [gnd - 0.3] to +6.0 v pin voltages v ddq ,v tt to gnd adjsd to gnd [gnd - 0.3] to +6.0 [gnd - 0.3] to +6.0 v v output current vddq / vtt, continuous (note 1) vddq / vtt, peak vddq source + vtt source 2.0 / 2.0 2.8 / 2.8 3 a a a temperature operating ambient operating junction storage -40 to +85 -40 to + 170 -40 to +150 c c c thermal resistance, r ja (note 2) tdfn-8, 3mm x 3mm 55 c/w continuous power dissipation (note 2) tdfn-8, t a = 25c / 85c 2.6 / 1.5 w esd protection (hbm) 2000 v lead temperature (soldering, 10s) 300 c standard operat ing conditions parameter rating units ambient operating temperature range -40 to +85 c vddq regulator ddr-1 supply voltage, vin load current, continuous load current, peak (1 s) c ddq 3.1 to 3.6 0 to 2 2.5 220 v a a f ordering information
? 2006 california micro devices corp. all rights reserved. 4 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 08/16/06 cm3202 preliminary note 1: v in = 3.3v, v ddq = 2.50v, vtt = 1.25v (default values), c ddq =c tt =47 f, t a = 25c unless otherwise specified. note 2: the shdn logic high value is normally satisfied for fu ll input voltage range by using a low leakage current (bellow 1 a). schottky diode at adjsd control pin. note 3: guaranteed by design. note 4: load and line regulation are measured at constant junction temperature by us ing pulse testing with a low duty cycle. changes in output voltage due to heating effects must be taken into account separately. load and line regulation values are guaranteed up to the maximum power dissipation. note 5: dropout voltage is input to output voltage differential at which output voltage has dropped 100mv from the nominal value obtained at 3.3v input. it depends on load curr ent and junction temperature. guaranteed by design. vtt regulator ddr-1 supply voltage, vin load current, continuous load current, peak (1 s) c tt 3.1 to 3.6 0 to 2.0 2.50 220 v ma ma f v in supply voltage range 3.10 to 3.60 v vddq source + vtt source load current, continuous load current, peak (1 s) 2.5 3.5 a a junction operating temperature range -40 to +150 c standard operat ing conditions electrical operating characteristics (see note 1) symbol parameter conditions min typ max units general i q quiescent current i ddq = 0, i tt = 0 8 15 ma i shdn shutdown current v adjsd = 3.3v (shutdown) 0.1 0.5 ma shdn_h shutdown logic high (note 2) 2.7 v shdn_l shutdown logic low 1.50 v uvlo under-voltage lockout hysteresis = 100mv (note 3) 2.4 2.7 2.90 v t over thermal shdn threshold (note 3) 150 170 c t hys thermal shdn hysteresis 50 c tempco v ddq , v tt tempco 150 ppm/ c vddq regulator v ddq def vddq output voltage i ddq = 100ma 2.450 2.500 2.550 v v ddq load vddq load regulation 10ma i ddq 2a (note 4) 10 25 mv v ddq line vddq line regulation 3.1v v in 3.6v, i ddq = 0.1a 5 25 mv v drop vddq dropout voltage i ddq = 2a (note 5) 500 mv i adj adjsd bias current (note 3) 0.8 3 a i ddq lim vddq current limit 2.0 2.5 a vtt regulator v tt def vtt output voltage i tt = 100ma 1.225 1.250 1.275 v v tt load vtt load regulation source, 0 i tt 2a (note 4) sink, -2a i tt 0 (note 4) -30 10 -10 30 mv mv v tt line vtt line regulation 3.1v v in 3.6v, i tt = 0.1a 5 15 mv i tt lim itt current limit source / sink (note 4) 2.0 2.5 a i vtt off vtt shutdown leakage current thermal shutdown enabled 10 a specifications (cont?d)
? 2006 california micro devices corp. all rights reserved. 08/16/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 5 cm3202 preliminary typical operating characteristics vddq dropout vs. iddq dropout voltage (mv) vt t v s. vddq 0.75 0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65 1.5 1.75 2 2.25 2.5 2.75 3 3.25 vddq (v) vtt (v) vin vddq vtt 1v/div 1v/div 2v/div uvlo startup into full load vddq vs. temperature 2.490 2.495 2. 500 2.505 2.510 -40 -20 0 20 40 60 80 100 120 140 temperature ( ) o c vddq (v) vddq vs. load current vddq (v) t a =25 o c vin=3.3v t a =25 o c time (1ms/div) 0 0.5 1.0 1.5 2.0 2.5 0 1.0 2.0 3.0 4.0 0 100 200 300 400 500 600 0 0.5 1.0 1.5 2.0 2.5 3.0 iddq (a) iddq (a) 0 1.0 2.0 3.0 4.0 0 0.5 1.0 1.5 2.0 2.5 itt (a)
? 2006 california micro devices corp. all rights reserved. 6 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 08/16/06 cm3202 preliminary functional block diagram v in = 3.3v +0.75a i ddq 0.5a/div v ddq 0.1v/div i tt 0.5a/div v tt 0.1v/div time (0.2ms/div) time (0.2ms/div) -0.75a vddq transient response vtt transient response 9 , 1 9 ' ' 4 1.22v 9 7 7 * 1 ' $ ' - 6 ' cm3202
9 ' ' 4
9 ' ' 4 & x u u h q w / l p l w & x u u h q w / l p l w & x u u h q w / l p l w 2 7 3 6 k x w g r z q 8 9 / 2 % d q g j d s typical operating ch aracteristics (cont?d)
? 2006 california micro devices corp. all rights reserved. 08/16/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 7 cm3202 preliminary powering ddr memory double-data-rate (ddr) me mory has provided a huge step in performance for pers onal computers, servers and graphic systems. as is apparent in its name, ddr operates at double the data rate of earlier ram, with two memory accesses per cycle versus one. ddr sdram's transmit data at both the rising falling edges of the memory bus clock. ddr?s use of stub series terminated logic (sstl) topology improves noise immunity and power-supply rejection, while reducing po wer dissipation. to achieve this performance improvement, ddr requires more complex power management architecture than previ- ous ram technology. unlike the conventional dram technology, ddr sdram uses differential inpu ts and a reference volt- age for all interface signals. this increases the data bus bandwidth, and lowers the system power con- sumption. power consumptio n is reduced by lower operating voltage, a lower signal voltage swing associ- ated with stub series terminated logic (sstl_2) and by the use of a termination voltage, v tt . sstl_2 is an industry standard, defined in jedec document jesd8-9. sstl_2 maintains high-speed data bus sig- nal integrity by reducing transmission reflections. jedec further defines the ddr sdram specification in jesd79c. ddr memory requires three tightly regulated voltages: v ddq , v tt , and v ref (see figure 1 ). in a typical sstl_2 receiver, the higher current vddq supply volt- age is normally 2.5v with a tolerance of 200 - mv. the active bus termination voltage, v tt , is half of v ddq . v ref is a reference voltage that tracks half of v ddq , 1%, and is compared with the v tt terminated signal at the receiver. v tt must be within 40 - mv of v ref . figure 1. typical ddr terminations, class ii the vtt power requirement is proportional to the num- ber of data lines and the re sistance of the termination resistor, but does not va ry with memory size. in a typi- cal ddr data bus system each data line termination may momentarily consume 16.2 - ma to achieve the 405 - mv minimum over v tt needed at the receiver: a typical 64 mbyte sstl-2 memory system, with 128 terminated lines, has a worst-case maximum v tt sup- ply current up to 2.07a. however, a ddr memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. these high current peaks can be handled by the v tt external capacitor. in a real memory system, the con- tinuous average v tt current level in normal operation is less than 200 ma. the vddq power supply, in addition to supplying cur- rent to the memory banks, could also supply current to controllers and other circuitr y. the current level typi- cally stays within a range of 0.5a to 1a, with peaks up to 2a or more, depending on memory size and the computing operations being performed. the tight tracking requirements and the need for v tt to sink, as well as source, current provide unique chal- lenges for powering ddr sdram. cm3202 regulator the cm3202 dual output linear regulator provides all of the power requirements of ddr memory by combining two linear regulators into a single tdfn-8 package. vddq regulator can supply up to 2a current, and the two-quadrant v tt termination regulator has current sink and source capability to 2a. the vddq linear regulator uses a pmos pass element for a very low dropout voltage, typically 500mv at a 2a output. the output voltage of v ddq can be set by an external volt- age divider. the use of regulators for both the upper and lower side of the vddq output allows a fast tran- sient response to any change of the load, from high current to low current or inversely. the second output, v tt , is regulated at v ddq /2 by an internal resistor divider. same as vddq, vtt has the same fast tran- sient response to load change in both directions. the v tt regulator can source, as well as sink, up to 2a cur- transmitter vddq vtt (=vddq/2) vddq receiver rs = 25 line rt = 25 vref (=vddq/2) i terminaton 405mv rt 25 () -------------------- - 16.2ma == application information
? 2006 california micro devices corp. all rights reserved. 8 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 08/16/06 cm3202 preliminary rent. the cm3202 is designed for optimal operation from a nominal 3.3vdc bus, but can work with vin as high as 5v. when operating at higher vin voltages, attention must be given to the increased package power dissipation and proportionally increased heat generation. v ref is typically routed to inputs with high impedance, such as a comparator, with little current draw. an ade- quate v ref can be created with a simple voltage divider of precision, matched resistors from v ddq to ground. a small ceramic bypass capacitor can also be added for improved noise performance. input and output capacitors the cm3202 requires that at least a 220 f electrolytic capacitor be located near the v in pin for stability and to maintain the input bus voltage during load transients. an additional 4.7 f ceramic capacitor between the v in and the gnd, located as close as possible to those pins, is recommended to ensure stability. a minimum of a 220 f electrolytic capacitor is recom- mended for the v ddq output. an additional 4.7 f ceramic capacitor between the v ddq and gnd, located very close to those pins, is recommended. a minimum of a 220 f, electrolytic capacitor is recom- mended for the v tt output. this capacitor should have low esr to achieve best output transient response. sp or oscon capacitors provide low esr at high fre- quency, and thus are a good choice. in addition, place a 4.7 f ceramic capacitor between the v tt pin and gnd, located very close to those pins. the total esr must be low enough to keep the transient within the v tt window of 40mv during the transition for source to sink. an average current step of 0.5a requires: both outputs will remain stab le and in regulation even during light or no load conditions. adjusting vddq output voltage the cm3202 internal bandgap reference is set at 1.25v. the v ddq voltage is adjustable by using a resistor divider, r1 and r2: where v adj = 1.25v. for best regulator stability, we recommend that r1 and r2 not exceed 10k each. shutdown adjsd also serves as a sh utdown pin. when this is pulled high (shdn_h), both the vddq and the vtt outputs tri-state and could sink/source less than 10 a. during shutdown, the quiescent current is reduced to less than 0.5ma, indepen dent of output load. it is recommended that a low leakage schottky diode be placed between adjsd pin and an external shut- down signal to prevent interference with the adj pin?s normal operation. when the diode anode is pulled low, or left open, the cm3202 is again enabled. current limit, foldback and over-temperature pro- tection the cm3202 features internal current limiting with ther- mal protection. during normal operation, v ddq limits the output current to approximately 2a and v tt limits the output current to approximately 2a. when v tt is current limiting into a hard short circuit, the output cur- rent folds back to a lower level, about 1a, until the over-current condition ends. while current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. if the junction temperature of the device exceeds 170 - c (typical), the thermal protection cir- cuitry triggers and tri-states both vddq and vtt out- puts. once the junction temperature has cooled to below about 120 - c, the cm3202 re turns to normal operation. thermal considerations typical thermal characteristics the overall junction to ambient thermal resistance ( ja ) for device power dissipation (p d ) primarily con- sists of two paths in the series. the first path is the junction to the case ( jc ) which is defined by the pack- age style and the second path is case to ambient ( ca ) thermal resistance which is dependent on board lay- out. the final operating junction temperature for any esr 40mv 1a --------------- < 40m = v ddq v adj r1 r2 + r2 -------------------- - = application info (cont?d)
? 2006 california micro devices corp. all rights reserved. 08/16/06 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 9 cm3202 preliminary condition can be estimated by the following thermal equation: when a cm3202 is mounted on a double-sided printed circuit board with four square inches of copper allo- cated for ?heat spreading,? the ja is approximately 55c/w. based on the over te mperature limit of 170c with an ambient of 85c, the available power of the package will be: pcb layout considerations thecm3202 has a heat spreader attached to the bot- tom of the tdfn-8 package in order for the heat to be transferred more easily from the package to the pcb. the heat spreader is a copper pad of dimensions just smaller than the package itself. by positioning the matching pad on the pcb top layer to connect to the spreader during the manufacturing, the heat will be transferred between the two pads. see the figure 2 , the cm3202 shows the recommended pcb layout. please be noted that there are four vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the pcb. vias can be placed underneath the chip, but this can be resulted in blocking of the solder. the ground and power planes need to be at least 2 square inches of copper by the vias. it also helps dissipation if the chip is positioned away from the edge of the pcb, and not near other heat-dissipating devices. a good thermal link from the pcb pad to the rest of the pcb will assure the best heat transfer from the cm3202 to ambient, ja , of approximately 55c/w. figure 2. thermal layout t junc t amb p d jc () p d ca () ++ = t amb = p d ca () + p d 170 c85 c ? 55 cw ? ------------------------------------ -1.5w == top view bottom layer ground plane top layer copper connects to heat spreader pin solder mask thermal pad solder mask vias (0.3mm diameter) note : this drawing is not to scale application info (cont?d)
? 2006 california micro devices corp. all rights reserved. 10 490 n. mccarthy blvd., milpitas, ca 95035-5112 tel: 408.263.3214 fax: 408.263.7846 www.cmd.com 08/16/06 cm3202 preliminary tdfn-08 mechanical specifications the CM3202-00DE is supplied in an 8-lead, 0.65mm pitch tdfn package. dimensions are presented below. ? this package is compliant with jedec standard mo-229, variation veec-1 with exception of the "d 2", "e2" and "b" dimensions as called out in the table above. package dimensions for 8-lead tdfn package dimensions package tdfn jedec no. mo-229 (var. weec-1) ? leads 6 dim. millimeters inches min nom max min nom max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 a2 0.45 0.55 0.65 0.018 0.022 0.026 a3 0.20 ref 0.008 ref b 0.25 0.30 0.35 0.010 0.012 0.014 d 2.90 3.00 3.10 0.114 0.118 0.122 d2 2.20 2.30 2.40 0.087 0.091 0.094 e 2.90 3.00 3.10 0.114 0.118 0.122 e2 1.40 1.50 1.60 0.055 0.059 0.063 e 0.65 bsc 0.026 bsc k 0.20 0.008 l 0.20 0.30 0.40 0.008 0.012 0.016 # per tape and reel 3000 pieces controlling dimension: millimeters mechanical package diagrams bottom view a a3 a1 0.10 c 0.08 c side view top view b l 0.10 c a b m 8x d2 e2 e gnd pad d e pin 1 marking 3 2 1 6 7 8 a2 k 2 4 6 57 c0.25 3 1 8 4 5 mechanical details
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