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preliminary users manual pd1615, pd16f15, 8-bit single-chip microcontroller ? nec corporation 1999 document no. u13635ee1v0um00 date published march 1999 hardware pd1616
pd1615, pd16f15, pd1616 2 fip is a trademark of nec corporation eeprom and iebus are trademarks of nec corporation. ms-dos and ms-windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of ibm corp. ibm-dos, pc/at and pc dos are trademarks of international business machines corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sun os is a trademark of sun microsystems, inc. ethernet is a trademark of xerox corp. news and news-os are trademarks of sony corporation. osf/motif is a trade mark of opensoftware foundation, inc.. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. the related documents in this publication may include preliminary versions. however, prelimi- nary versions are not marked as such. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m4 94.11 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard:computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product.
3 pd71615, pd16f15, pd1616 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
4 pd1615, pd16f15, pd1616 introduction readers this manual has been prepared for user engineers who want to understand the functions of the pd1615 subseries and design and develop its application systems and programs. pd1615 subseries: pd1615, pd16f15, pd1616. purpose this manual is intended for users to understand the functions described in the organization below. organization the pd1615 subseries manual is separated into two parts: this manual and the instruction edition (common to the 78k/0 series). pd1615 78k/0 series subseries users manual this manual instruction ? pin functions ? cpu functions ? internal block functions ? instruction set ? interrupt ? explanation of each instruction ? other on-chip peripheral functions how to read this manual before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. ? when you want to understand the function in general: ? ? ? ? ? read this manual in the order of the contents. ? how to interpret the register format: ? ? ? ? ? for the bit number enclosed in square, the bit name is defined as a reserved word in the assembler and the compiler. ? to make sure the details of the registers when you know the register name. ? ? ? ? ? refer to appendix c.
5 pd1615, pd16f15, pd1616 chapter organization this manual devides the descriptions for the subseries into different chapters as shown below. read only the chapters related to the device you use. chapter pd1615 pd16f15 pd1616 chapter 1 outline ??? chapter 2 pin function ??? chapter 3 cpu architecture ??? chapter 4 port functions ??? chapter 5 clock generator ??? chapter 6 16-bit timer/counter ??? chapter 7 8-bit timer/event counters 50, 51 ??? chapter 8 watch timer ??? chapter 9 watchdog timer ??? chapter 10 clock output control circuit ??? chapter 11 a/d-converter ??? chapter 12 serial interface outline ??? chapter 13 serial interface channel 30 ??? chapter 14 serial interface uart ??? chapter 15 van controller ??? chapter 16 lcd controller/driver ?? ? chapter 17 sound generator ??? chapter 18 interrupt functions ??? chapter 19 standby function ??? chapter 20 reset function ??? chapter 21 pd16f15 ??? chapter 22 instruction set ??? appendix a development tools ??? appendix b em bedded software ??? appendix c register ??? appendix d revision history ???
6 pd1615, pd16f15, pd1616 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? related documents for pd1615 subseries ? related documents for development tool (user's manuals) document no. document name japanese english pd1615 preliminary product information u13723e pd16f15 preliminary product information u13606e pd1615 subseries users manual this manual 78k/0 series users manual-instruction ieu-849 ieu-1372 78k/0 series instruction table u10903j 78k/0 series instruction set u10904j u12326e pd1615 subseries special function register table document no. document name japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k/0 c compiler operation u11517j language u11518j cc78k/0 c compiler application note programming note eea-618 eea-1208 cc78k series library source file eeu-777 ie-78001-r-a u10057j u10057e ie-78k0-ns-p04 u13359e ie-1615-ns-em4 ie-78k0-r-ex1 sud-3677 sud-3677 ep-78230gc-12 tempr-2093 u10181e sm78k0 system simulator windows? base reference u10181j u1 0092e sm78k0 series system simulator external part user open interface u10092j id78k0 integrated debugger ews base reference u11151j u1 1539e id78k0 integrated debugger pc base reference u11539j u1 1649e id78k0 integrated debugger windows base guide u11649j
7 pd1615, pd16f15, pd1616 ? related documents for embedded software (users manual) ? other documents caution: the above documents are subject to change without prior notice. be sure to use the latest version document when starting design. document no. document name japanese english 78k/0 series real-time os basics u11537j installation u11536j technicals u11538j 78k/0 series os mx78k0 basics eeu-5010 fuzzy knowl edge data creation tool eeu-829 eeu1438 78k/0, 78ik/ii, 87ad series fu zzy inference development s uppport system-translator eeu-862 eeu- 1444 78k/0 series fuzzy inference development s uppport system- fu zzy inference m odule eeu-858 eeu- 1441 78k/0 series fuzzy inference development s uppport system- fu zzy inference d ebugger eeu-921 eeu- 1458 document no. document name japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grade on nec semiconductor devices c11531j c11531e reliability quality control on nec semiconductor devices c10983j c10983e electric static discharge (esd) test mem-539 semiconductor devices quality assurance guide mei-603 mei-1202 microcontroller related product guide - third party manufacturers u11416j
8 pd1615, pd16f15, pd1616 table of contents chapter 1 outline ........................................................................................................... 26 1.1 features .................................................................................................................. .............................. 26 1.2 application ............................................................................................................... ............................. 26 1.3 ordering information ...................................................................................................... ..................... 26 1.4 pin configuration (top view) .............................................................................................. ................ 27 1.5 78k/0 series development .................................................................................................. ................ 30 1.6 block diagram ............................................................................................................ ......................... 31 1.7 overview of functions ..................................................................................................... .................... 33 1.8 mask options .............................................................................................................. .......................... 34 1.9 differences between flash and mask rom version .......................................................................... 34 chapter 2 pin function .................................................................................................. 36 2.1 pin function list .......................................................................................................... ......................... 36 2.2 non-port pins ............................................................................................................. .......................... 38 2.3 description of pin functions .............................................................................................. ................ 40 2.3.1 p00 to p02, p06 and p07 (port 0) ........................................................................................ .............. 40 2.3.2 p10 to p13 (port 1) ..................................................................................................... ....................... 40 2.3.3 p40 to p47 (port 4) ..................................................................................................... ....................... 40 2.3.4 p80 to p87 (port 8) ..................................................................................................... ....................... 41 2.3.5 p90 to p97 (port 9) ..................................................................................................... ....................... 41 2.3.6 p100 to p107 (port 10) .................................................................................................. ..................... 41 2.3.7 p110 to p117 (port 11) .................................................................................................. ..................... 41 2.3.8 p120 to p127 (port 12) .................................................................................................. ..................... 42 2.3.9 com0 to com3 ............................................................................................................ ...................... 42 2.3.10 vlc0 to vlc2 ........................................................................................................... ........................ 42 2.3.11 avdd/avref ............................................................................................................. ...................... 43 2.3.12 avss ................................................................................................................... .............................. 43 2.3.13 reset .................................................................................................................. ............................ 43 2.3.14 x1 and x2 .............................................................................................................. ........................... 43 2.3.15 cl1 and cl2 ............................................................................................................ ........................ 43 2.3.16 vdd0/vdd1 .............................................................................................................. ........................ 43 2.3.17 vss0/vss1 .............................................................................................................. ......................... 43 2.3.18 vpp (pd16f15 only) .................................................................................................... .................. 43 2.4 pin i/o circuits and recommended connection of unused pins .................................................... 44
9 pd1615, pd16f15, pd1616 chapter 3 cpu architecture .......................................................................................... 51 3.1 memory space .............................................................................................................. ........................ 51 3.1.1 internal program memory space ........................................................................................... .......... 53 3.1.2 internal data memory space .............................................................................................. ............... 55 3.1.3 special function register (sfr) area .................................................................................... ........... 55 3.1.4 data memory addressing .................................................................................................. ............... 56 3.2 processor registers ....................................................................................................... ..................... 58 3.2.1 control registers ....................................................................................................... ........................ 58 3.2.2 general registers ....................................................................................................... ....................... 61 3.2.3 special function register (sfr) ......................................................................................... .............. 62 3.3 instruction address addressing ............................................................................................ ............. 65 3.3.1 relative addressing ..................................................................................................... ..................... 65 3.3.2 immediate addressing .................................................................................................... .................. 66 3.3.3 table indirect addressing ............................................................................................... .................. 67 3.3.4 register addressing ..................................................................................................... ..................... 68 3.4 operand address addressing ................................................................................................ ............. 69 3.4.1 implied addressing ...................................................................................................... ..................... 69 3.4.2 register addressing ..................................................................................................... ..................... 70 3.4.3 direct addressing ....................................................................................................... ....................... 71 3.4.4 short direct addressing ................................................................................................. ................... 72 3.4.5 special function register (sfr) addressing .............................................................................. ..... 73 3.4.6 register indirect addressing ............................................................................................ ................ 74 3.4.7 based addressing ........................................................................................................ ...................... 75 3.4.8 based indexed addressing ................................................................................................ ............... 76 3.4.9 stack addressing ........................................................................................................ ....................... 76 chapter 4 port functions .............................................................................................. 78 4.1 port functions ............................................................................................................ .......................... 78 4.2 port configuration ........................................................................................................ ....................... 81 4.2.1 port 0 .................................................................................................................. ................................ 81 4.2.2 port 1 .................................................................................................................. ................................ 83 4.2.3 port 4 .................................................................................................................. ................................ 84 4.2.4 port 8 .................................................................................................................. ................................ 85 4.2.5 port 9 .................................................................................................................. ................................ 86 4.2.6 port 10 ................................................................................................................. ............................... 87 4.2.7 port 11 ................................................................................................................. ............................... 88 4.2.8 port 12 ................................................................................................................. ............................... 89 4.3 port function control registers ........................................................................................... .............. 90 4.4 port function operations .................................................................................................. .................. 93 4.4.1 writing to input/output port ............................................................................................ ................. 93 4.4.2 reading from input/output port .......................................................................................... ............. 93 4.4.3 operations on input/output port ......................................................................................... ............. 93
10 pd1615, pd16f15, pd1616 chapter 5 clock generator ............................................................................................ 95 5.1 clock generator functions ................................................................................................. ................ 95 5.2 clock generator configuration ............................................................................................. .............. 96 5.3 clock generator control register .......................................................................................... ............ 97 5.4 system clock oscillator ................................................................................................... ................... 98 5.4.1 main system clock oscillator ............................................................................................ ............... 98 5.4.2 subsystem clock oscillator .............................................................................................. ................ 99 5.4.3 when no subsystem clocks are used ....................................................................................... ..... 101 5.5 clock generator operations ................................................................................................ ............. 102 5.5.1 main system clock operations ............................................................................................ ........... 103 5.5.2 subsystem clock operations .............................................................................................. ............ 104 5.6 changing system clock and cpu clock settings ............................................................................ 105 5.6.1 time required for switchover between system clock and cpu clock .......................................... 105 5.6.2 system clock and cpu clock switching procedure ..................................................................... 106 chapter 6 16-bit timer/ event counter ...................................................................... 108 6.1 16-bit timer/event counter function ....................................................................................... ........ 108 6.2 16-bit timer/event counter configuration .................................................................................. ..... 109 6.3 16-bit timer/event counter control register ............................................................................... ... 113 6.4 16-bit timer/event counter operations ..................................................................................... ...... 120 6.4.1 operation as interval timer (16 bits) .................................................................................... .......... 120 6.4.2 ppg output operation .................................................................................................... ................. 122 6.4.3 pulse width measurement ................................................................................................. ............. 123 6.4.4 operation as external event counter ..................................................................................... ........ 130 6.4.5 operation to output square wave ......................................................................................... ......... 132 6.4.6 operation to output one-shot pulse ...................................................................................... ........ 134 6.5 16-bit timer/event counter operating precautions ........................................................................ 13 9 chapter 7 8-bit timer/event counters 50 and 51 ...................................................... 143 7.1 8-bit timer/event counters 50 and 51 functions ............................................................................ 143 7.2 8-bit timer/event counters 50 and 51 configurations ................................................................... 146 7.3 8-bit timer/event counters 50 and 51 control registers ............................................................... 149 7.4 8-bit timer/event counters 50 and 51 operations .......................................................................... 1 54 7.4.1 interval timer operations ................................................................................................ ................. 154 7.4.2 external event counter operation ........................................................................................ .......... 158 7.4.3 square-wave output ...................................................................................................... .................. 159 7.4.4 pwm output operations ................................................................................................... ............... 161 7.5 cautions on 8-bit timer/event counters 50 and 51 ........................................................................ 16 4
11 pd1615, pd16f15, pd1616 chapter 8 watch timer ................................................................................................. 167 8.1 watch timer functions ..................................................................................................... ................. 167 8.2 watch timer configuration ................................................................................................. ............... 168 8.3 watch timer mode register (wtm) ........................................................................................... ....... 169 8.4 watch timer operations ..................................................................................................... ................ 170 8.4.1 watch timer operation .................................................................................................... ................. 170 8.4.2 interval timer operation ................................................................................................. .................. 170 chapter 9 watchdog timer .......................................................................................... 173 9.1 watchdog timer functions .................................................................................................. .............. 173 9.2 watchdog timer configuration .............................................................................................. ........... 174 9.3 watchdog timer control registers .......................................................................................... ......... 175 9.4 watchdog timer operations .................................................................................................. ............. 177 9.4.1 watchdog timer operation ................................................................................................. .............. 177 9.4.2 interval timer operation ................................................................................................ .................. 178 chapter 10 clock output control circuit ................................................................... 180 10.1 clock output control circuit functions ................................................................................... ..... 180 10.2 clock output control circuit configuration ............................................................................... .. 181 10.3 clock output function control registers .................................................................................. ... 182 chapter 11 a/d converter ............................................................................................ 185 11.1 a/d converter functions .................................................................................................. ............... 185 11.2 a/d converter configuration .............................................................................................. ............ 186 11.3 a/d converter control registers .......................................................................................... .......... 188 11.4 a/d converter operations ................................................................................................. .............. 191 11.4.1 basic operations of a/d converter ...................................................................................... ........ 191 11.4.2 input voltage and conversion results ................................................................................... ....... 193 11.4.3 a/d converter operation mode ........................................................................................... .......... 194 11.5 a/d converter precautions ................................................................................................ .............. 196 11.6 cautions on emulation ................................................................................................... ................ 199 11.6.1 d/a converter mode register (dam0) ..................................................................................... ..... 199 chapter 12 serial interface outline ............................................................................ 201 12.1 serial interface outline ................................................................................................. ................... 201
12 pd1615, pd16f15, pd1616 chapter 13 serial interface channel 30 ...................................................................... 203 13.1 serial interface channel 30 functions ................................................................................... ....... 203 13.2 serial interface channel 30 configuration ............................................................................... ..... 204 13.3 list of sfrs (special function registers) ............................................................................... ..... 204 13.4 serial interface control registers ..................................................................................... ........... 205 13.5 serial interface operations ............................................................................................ ............... 206 13.5.1 operation stop mode ..................................................................................................... ................ 206 13.5.2 three-wire serial i/o mode ............................................................................................. .............. 207 chapter 14 serial interface uart ............................................................................... 210 14.1 serial interface uart functions ......................................................................................... .......... 210 14.2 serial interface uart configuration ..................................................................................... ........ 211 14.3 list of sfrs (special function registers) .......................................................................... .... 212 14.4 serial interface control registers ...................................................................................... ........... 212 14.5 serial interface operations ............................................................................................ ............... 216 14.5.1 operation stop mode .................................................................................................... ................ 216 14.5.2 asynchronous serial interface (uart) mode ............................................................................. 2 16 14.6 standby function ........................................................................................................ .................... 228 chapter 15 van controller ........................................................................................... 230 15.1 features ............................................................................................................... ........................... 230 15.2 overview of the van bus ................................................................................................ .............. 231 15.2.1 van uart description ................................................................................................. .............. 231 15.2.2 van uart interface ................................................................................................... ................. 231 15.3 functional description ................................................................................................. .................. 235 15.3.1 overview of the van uart registers ................................................................................... .... 235 15.3.2 autonomous mode functions ............................................................................................ ......... 236 15.3.2.1 autonomous mode features ............................................................................................. ......... 236 15.3.2.2 programming of the prescaler in rank 0 transmission (sof included) ................................ 236 15.3.2.3 transmission features in autonomous mode ........................................................................... 23 7 15.3.3 synchronous mode functions ........................................................................................... ......... 238 15.3.3.1 synchronous mode features ........................................................................................... ......... 238 15.3.3.2 transmission features in synchronous mode .......................................................................... 23 8 15.3.4 handling of a collision ................................................................................................ .................. 238 15.3.5 executing the crc ...................................................................................................... .................. 238 15.3.5.1 crc transmission ..................................................................................................... ................. 238 15.3.5.2 reception of the crc ................................................................................................. ............... 239 15.3.6 control of the acknowledge bit ......................................................................................... ........... 239 15.3.7 error control and interrupt control .................................................................................... ......... 239 15.3.7.1 error control ........................................................................................................ ....................... 239 15.3.7.2 interrupt control .................................................................................................... ..................... 240
13 pd1615, pd16f15, pd1616 15.4 van uart registers .................................................................................................... ................. 243 15.4.1 rank0 transmission register (rk0_reg) .................................................................................. 244 15.4.2 in frame response register (ifr_reg) ................................................................................... .. 245 15.4.3 control register (ctrl_reg) ............................................................................................ ......... 247 15.4.4 configuration register (conf_reg) ...................................................................................... .... 250 15.4.5 diagnosis control register (diag_ctrl_reg) ........................................................................ 253 15.4.6 mask1 registers (msk1_msb_reg, msk1_lsb_reg) .............................................................. 256 15.4.7 acceptance code 1 registers (ac1_msb_reg, ac1_lsb_reg) .............................................. 257 15.4.8 mask2 registers (msk2_msb_reg, msk2_lsb_reg) ............................................................. 258 15.4.9 acceptance code 2, 3 and 4 registers (ac2_msb_reg, ac2_lsb_reg, ............................... 259 15.4.10 status register (stat_reg) ............................................................................................ .......... 260 15.4.11 receive register (rec_reg) ............................................................................................ .......... 262 15.4.12 diagnosis status register (diag_stat_reg) ......................................................................... 263 15.4.13 interrupt enable register (int_enable_reg) ......................................................................... 264 15.4.14 van clock selection register (udlccl) ................................................................................. ... 266 15.5 van uart initialisation ................................................................................................. ................. 267 chapter 16 lcd controller/driver ............................................................................... 269 16.1 lcd controller/driver functions ......................................................................................... .......... 269 16.2 lcd controller/driver configuration ..................................................................................... ....... 270 16.3 lcd controller/driver control registers ................................................................................. .... 272 16.4 lcd controller/driver settings .......................................................................................... ............ 275 16.5 lcd display data memory ................................................................................................. ............ 276 16.6 common signals and segment signals ...................................................................................... .. 277 16.7 supply of lcd drive voltages vlc0, vlc1, vlc2 ......................................................................... 28 1 16.8 display modes ............................................................................................................ ...................... 284 16.8.1 static display example ................................................................................................. ................. 284 16.8.2 2-time-division display example ....................................................................................... .......... 287 16.8.3 3-time-division display example ....................................................................................... .......... 290 16.8.4 4-time-division display example ....................................................................................... .......... 294 chapter 17 sound generator ...................................................................................... 298 17.1 sound generator function ................................................................................................. ............. 298 17.2 sound generator configuration ............................................................................................ ......... 299 17.3 sound generator control registers ........................................................................................ ....... 300 17.4 sound generator operations ................................................................................................ ........... 305 17.4.1 to output basic cycle signal sgof (without amplitude) ............................................................ 305 17.4.2 to output basic cycle signal sgo (with amplitude) .................................................................... 305
14 pd1615, pd16f15, pd1616 chapter 18 interrupt functions ................................................................................... 307 18.1 interrupt function types ................................................................................................. ................. 307 18.2 interrupt sources and configuration ...................................................................................... ....... 308 18.3 interrupt function control registers ..................................................................................... ........ 311 18.4 interrupt servicing operations ........................................................................................... ............ 317 18.4.1 non-maskable interrupt request acknowledge operation ......................................................... 317 18.4.2 maskable interrupt request acknowledge operation .................................................................. 320 18.4.3 software interrupt request acknowledge operation .................................................................. 322 18.4.4 multiple interrupt servicing ........................................................................................... ............... 323 18.4.5 interrupt request reserve .............................................................................................. ............... 326 chapter 19 standby function...................................................................................... 328 19.1 standby function and configuration ....................................................................................... ...... 328 19.1.1 standby function ....................................................................................................... .................... 328 19.1.2 standby function control register ...................................................................................... ......... 329 19.2 standby function operations .............................................................................................. ........... 330 19.2.1 halt mode .............................................................................................................. ....................... 330 19.2.2 stop mode .............................................................................................................. ...................... 333 chapter 20 reset function .......................................................................................... 337 20.1 reset function ........................................................................................................... ...................... 337 chapter 21 pd16f15 ................................................................................................... 342 21.1 memory size switching register (ims) ..................................................................................... ..... 343 21.2 internal extension ram size switching register ........................................................................ 34 4 21.3 flash memory programming ................................................................................................. .......... 345 21.3.1 selection of transmission method ....................................................................................... ....... 345 21.3.2 initialization of the programming mode ................................................................................. .... 345 21.3.3 flash memory programming function ...................................................................................... .. 346 21.3.4 flashpro connection .................................................................................................. ................. 346 21.3.5 flash programming precautions .......................................................................................... ....... 347
15 pd1615, pd16f15, pd1616 chapter 22 instruction set .......................................................................................... 349 22.1 legends used in operation list ........................................................................................... .......... 350 22.1.1 operand identifiers and description methods ............................................................................ 350 22.1.2 description of operation column ...................................................................................... ....... 351 22.1.3 description of flag operation column ................................................................................. ..... 351 22.2 operation list ........................................................................................................... ........................ 352 22.3 instructions listed by addressing type ................................................................................... ...... 360 appendix a development tools .................................................................................. 365 a.1 language processing software .............................................................................................. ......... 366 a.2 flash memory writing tools ................................................................................................ ............. 367 a.3 debugging tools ........................................................................................................... ..................... 367 a.3.1 hardware ................................................................................................................ ......................... 367 a.3.2 software (1/2) .......................................................................................................... ........................ 368 a.3.2 software (2/2) .......................................................................................................... ........................ 369 a.4 os for ibm pc ............................................................................................................. ....................... 370 a.5 development environment when using ie-78001-r-a ................................................................... 371 appendix b embedded software ................................................................................ 373 b.1 real-time os (1/2) ......................................................................................................... ..................... 374 b.1 real-time os (2/2) ........................................................................................................ .................... 375 b.2 fuzzy inference development support system .............................................................................. 37 6 appendix c register index .......................................................................................... 378 c.1 register index (in alphabetical order with respect to register names) .................................... 378 c.2 register index (in alphabetical order with respect to register symbol) ................................... 381 appendix d revision history ...................................................................................... 385
16 pd1615, pd16f15, pd1616 contents of figures figure no. title page 1-1 pin configuration pd1615, pd16f15 ....................................................................... 27 1-2 pin configuration pd1616 ......................................................................................... 28 1-3 block diagram pd1615, pd16f15 ............................................................................ 31 1-4 block diagram pd1616 .............................................................................................. 32 2-1 connection of ic pins .................................................................................................. 43 2-2 pin input/output circuits ............................................................................................ 48 3-1 memory map (pd1615, pd1616) ............................................................................. 51 3-2 memory map (pd16f15) ............................................................................................ 52 3-3 data memory addressing (pd1615, pd1616) ........................................................ 56 3-4 data memory addressing (pd16f15) ....................................................................... 57 3-5 program counter configuration ................................................................................. 58 3-6 program status word configuration .......................................................................... 58 3-7 stack pointer configuration ........................................................................................ 60 3-8 data to be saved to stack memory ............................................................................ 60 3-9 data to be reset to stack memory ............................................................................. 60 3-10 general register configuration .................................................................................. 61 3-11 relative addressing ..................................................................................................... 65 3-12 immediate addressing ................................................................................................. 66 3-13 table indirect addressing ........................................................................................... 67 3-14 register addressing .................................................................................................... 68 3-15 register addressing .................................................................................................... 70 3-16 short direct addressing .............................................................................................. 72 3-17 special-function register (sfr) addressing ........................................................... 73 3-18 special-function register (sfr) addressing ........................................................... 74 4-1 port types .................................................................................................................. ... 78 4-2 p00 to p02 and p06, p07 configurations .................................................................... 82 4-3 p10 to p13 configurations .......................................................................................... 83 4-4 p40 to p47 configurations .......................................................................................... 84 4-5 p80 to p87 configurations .......................................................................................... 85 4-6 p90 to p97 configurations .......................................................................................... 86 4-7 p100 to p107 configurations ...................................................................................... 87 4-8 p110 to p117 configurations ...................................................................................... 88 4-9 p120 to p127 configurations ...................................................................................... 89 4-10 port mode register format ......................................................................................... 91 4-11 port function register (pf8 to pf12) format ........................................................... 92
17 pd1615, pd16f15, pd1616 figure no. title page 5-1 block diagram of clock generator ............................................................................ 96 5-2 processor clock control register format ................................................................ 97 5-3 external circuit of main system clock oscillator .................................................... 98 5-4 external circuit of subsystem clock oscillator ....................................................... 99 5-5 examples of oscillator with bad connection (3/3) ................................................... 100 5-6 main system clock stop function (2/2) ..................................................................... 103 5-7 system clock and cpu clock switching ................................................................... 106 6-1 block diagram of 16-bit timer/event counter (tm0) ............................................... 109 6-2 format of 16-bit timer mode control register (tmc0) ............................................ 114 6-3 format of capture/compare control register 0 (crc0) ......................................... 116 6-4 format of 16-bit timer output control register (toc0) ......................................... 117 6-5 format of prescaler mode register 0 (prm0) ........................................................... 118 6-6 port mode register 12 (pm12) format ....................................................................... 119 6-7 port function register 12 (pf12) format .................................................................. 119 6-8 control register settings when timer 0 operates as interval timer ...................... 120 6-9 configuration of interval timer .................................................................................. 121 6-10 timing of interval timer operation ............................................................................ 121 6-11 control register settings in ppg output operation ................................................ 122 6-12 control register settings for pulse width measurement with free running counter and one capture register ........................................................................................... 123 6-13 configuration for pulse width measurement with free running counter ............. 124 6-14 timing of pulse width measurement with free running counter and one capture register (with both edges specified) ......................................................................... 124 6-15 control register settings for measurement of two pulse widths with free running counter ........................................................................................................................ . 125 6-16 cr01 capture operation with rising edge specified .............................................. 126 6-17 timing of pulse width measurement with free running counter (with both edges specified) ..................................................................................................................... . 126 6-18 control register settings for pulse width measurement with free running counter and two capture registers ......................................................................................... 127 6-19 timing of pulse width measurement with free running counter and two capture registers (with rising edge specified) ....................................................................... 128 6-20 control register settings for pulse width measurement by restarting ................ 129 6-21 timing of pulse width measurement by restarting (with rising edge specified) .. 130 6-22 control register settings in external event counter mode .................................... 131 6-23 configuration of external event counter .................................................................. 131 6-24 timing of external event counter operation (with rising edge specified) ............ 132 6-25 set contents of control registers in square wave output mode ........................... 133 6-26 timing of square wave output operation ................................................................. 133 6-27 control register settings for one-shot pulse output with software trigger ....... 135
18 pd1615, pd16f15, pd1616 figure no. title page 6-28 timing of one-shot pulse output operation with software trigger ....................... 136 6-29 control register settings for one-shot pulse output with external trigger ........ 137 6-30 timing of one-shot pulse output operation with external trigger (with rising edge specified) ..................................................................................................................... . 138 6-31 start timing of 16-bit timer register ......................................................................... 139 6-32 timing after changing compare register during timer count operation ............. 139 6-33 data hold timing of capture register ....................................................................... 140 6-34 operation timing of ovf0 flag ................................................................................... 141 7-1 8-bit timer/event counter 50 block diagram ............................................................ 146 7-2 8-bit timer/event counter 51 block diagram ............................................................ 147 7-3 block diagram of 8-bit timer/event counters 50 and 51 output control circuit .. 148 7-4 timer clock select register 50 format ..................................................................... 149 7-5 timer clock select register 51 format ..................................................................... 150 7-6 8-bit timer output control register 50 format ........................................................ 151 7-7 8-bit timer output control register 51 format ........................................................ 152 7-8 port mode register 0 format ...................................................................................... 153 7-9 8-bit timer mode control register settings for interval timer operation ............. 154 7-10 interval timer operation timings (3/3) ....................................................................... 154 7-11 8-bit timer mode control register setting for external event counter operation 158 7-12 external event counter operation timings (with rising edge specified) ............. 158 7-13 8-bit timer mode control register settings for square-wave output operation . 159 7-14 square-wave output operation timing ...................................................................... 159 7-15 8-bit timer control register settings for pwm output operation ......................... 161 7-16 pwm output operation timing (active high setting) ............................................... 162 7-17 pwm output operation timings (crn0 = 00h, active high setting) ........................ 162 7-18 pwm output operation timings (crn = ffh, active high setting) ......................... 163 7-19 pwm output operation timings (crn changing, active high setting) .................... 163 7-20 8-bit timer registers 50 and 51 start timings .......................................................... 164 7-21 external event counter operation timings ............................................................... 164 7-22 timings after compare register change during timer count operation .............. 165 8-1 block diagram of watch timer ................................................................................... 167 8-2 watch timer mode control register (wtm) format ................................................. 169 8-3 operation timing of watch timer/interval timer ....................................................... 171 9-1 watchdog timer block diagram ................................................................................. 174 9-2 watchdog timer clock select register format ........................................................ 175 9-3 watchdog timer mode register format .................................................................... 176
19 pd1615, pd16f15, pd1616 figure no. title page 10-1 remote controlled output application example ...................................................... 180 10-2 clock output control circuit block diagram ............................................................ 181 10-3 clock output selection register format ................................................................... 182 10-4 port mode register 12 format .................................................................................... 183 10-5 port function register 12 (pf12) format .................................................................. 183 11-1 a/d converter block diagram ..................................................................................... 185 11-2 power-fail detection function block diagram ......................................................... 186 11-3 a/d converter mode register (adm1) format .......................................................... 188 11-4 analog input channel specification register (ads1) format ................................. 189 11-5 power-fail compare mode register (pfm) format .................................................. 190 11-6 power-fail compare threshold value register (pft) .................................................. 190 11-7 basic operation of 8-bit a/d converter ..................................................................... 192 11-8 relation between analog input voltage and a/d conversion result ...................... 193 11-9 a/d conversion ............................................................................................................ 1 95 11-10 example method of reducing current consumption in standby mode ................. 196 11-11 analog input pin handling .......................................................................................... 197 11-12 a/d conversion end interrupt request generation timing ..................................... 198 11-13 d/a converter mode register (dam0) format .......................................................... 199 13-1 block diagram of sio30 .............................................................................................. 203 13-2 format of serial operation mode register 30 (csim30) .......................................... 205 13-3 format of serial operation mode register 30 (csim30) .......................................... 206 13-4 format of serial operation mode register 30 (csim30) .......................................... 207 13-5 timing of three-wire serial i/o mode ......................................................................... 208 14-1 block diagram of uart ............................................................................................... 210 14-2 format of asynchronous serial interface mode register (asim0) ......................... 213 14-3 format of asynchronous serial interface status register (asis0) ........................ 214 14-4 format of baud rate generator control register (brgc0) .................................... 215 14-5 register settings ......................................................................................................... 2 16 14-6 asynchronous serial interface mode register (asim0) ............................................ 217 14-7 asynchronous serial interface status register (asis0) ............................................ 218 14-8 baud rate generator control register (brgc0) ......................................................... 219 14-9 error tolerance (when k = 0), including sampling errors ........................................ 222 14-10 format of transmit/receive data in asynchronous serial interface ...................... 223 14-11 timing of asynchronous serial interface transmit completion interrupt ............. 225 14-12 timing of asynchronous serial interface receive completion interrupt ............... 226 14-13 receive error timing ................................................................................................... 227
20 pd1615, pd16f15, pd1616 figure no. title page 15-1 van uart interface ................................................................................................... 231 15-2 van uart block diagram ........................................................................................... 232 15-3 generation of the van clock ...................................................................................... 233 15-4 overview of the van uart registers ...................................................................... 235 15-5 prescaler in rank 0 transmission ............................................................................... 236 15-6 rank0 transmission register format ........................................................................ 244 15-7 frame responce register format .............................................................................. 245 15-8 frame responce register function ........................................................................... 246 15-9 control register format ............................................................................................. 247 15-10 control register block diagram ................................................................................ 248 15-11 control register function ........................................................................................... 248 15-12 last-byte ... .................................................................................................................... 248 15-13 configuration register (conf_reg) format ........................................................... 250 15-14 case where it12 = 0 ..................................................................................................... 250 15-15 case where it12 = 1 ..................................................................................................... 251 15-16 diagnosis control register (diag_ctrl_reg) format ..... ..................................... 253 15-17 prescaler block diagram ............................................................................................. 253 15-18-1 mask1 register msk1_msb_reg format ................................................................. 256 15-18-2 mask1 register msk1_lsb_reg format .................................................................. 256 15-19-1 acceptance code 1 register ac1_msb_reg .......................................................... 257 15-19-2 acceptance code 1 register ac1_lsb_reg ........................................................... 257 15-20-1 mask2 register msk2_msb_reg format .............................................................. 258 15-20-2 mask2 register msk2_lsb_reg format ............................................................... 258 15-21 acceptance code 2, 3 and 4 registers format ........................................................ 259 15-22 status register (stat_reg) format ......................................................................... 260 15-23 receive register (rec_reg) format ........................................................................ 262 15-24 diagnosis status register (diag_stat_reg) format ............................................ 263 15-25 interrupt enable register (int_enable_reg) format ..... ..................................... 264 15-26 van clock selection register (udlccl) format ...................................................... 266
21 pd1615, pd16f15, pd1616 figure no. title page 16-1 lcd controller/driver block diagram ....................................................................... 270 16-2 lcd clock select circuit block diagram ................................................................... 271 16-3 lcd display mode register format ........................................................................... 273 16-4 lcd display clock control register format ............................................................. 274 16-5 relationship between lcd display data memory contents and segment/common outputs ................................................................................. 276 16-6 common signal waveform ......................................................................................... 279 16-7 common signal and static signal voltages and phases .......................................... 280 16-8 lcd drive power supply connection examples (with external split resistor) .... 282 16-9 example of lcd drive voltage supply from off-chip .............................................. 283 16-10 static lcd display pattern and electrode connections .......................................... 284 16-11 static lcd panel connection example ...................................................................... 285 16-12 static lcd drive waveform examples ....................................................................... 286 16-13 2-time-division lcd display pattern and electrode connections ......................... 287 16-14 2-time-division lcd panel connection example ..................................................... 288 16-15 2-time-division lcd drive waveform examples (1/2 bias method) ...................... 289 16-16 3-time-division lcd display pattern and electrode connections ......................... 290 16-17 3-time-division lcd panel connection example ..................................................... 291 16-18 3-time-division lcd drive waveform examples (1/2 bias method) ...................... 292 16-19 3-time-division lcd drive waveform examples (1/3 bias method) ...................... 293 16-20 4-time-division lcd display pattern and electrode connections ......................... 294 16-21 4-time-division lcd panel connection example ..................................................... 295 16-22 4-time-division lcd drive waveform examples (1/3 bias method) ...................... 296 17-1 sound generator block diagram ................................................................................ 298 17-2 concept of each signal ............................................................................................... 299 17-3 sound generator control register (sgcr) format ................................................. 301 17-4 sound generator buzzer control register (sgbr) format .................................... 302 17-5 sound generator frequency selection ...................................................................... 303 17-6 sound generator amplitude register (sgam) format ............................................ 304 17-7 sound generator output operation timing without amplitude ............................. 305 17-8 sound generator output operation timing with amplitude .................................. 305
22 pd1615, pd16f15, pd1616 figure no. title page 18-1 basic configuration of interrupt function (2/2) ........................................................ 309 18-2 interrupt request flag register format .................................................................... 312 18-3 interrupt mask flag register format ......................................................................... 313 18-4 priority specify flag register format ....................................................................... 314 18-5 formats of external interrupt rising edge enable register and external interrupt falling edge enable register ...................................................................................... 315 18-6 program status word format ..................................................................................... 316 18-7 flowchart from non-maskable interrupt generation to acknowledge ................... 318 18-8 non-maskable interrupt request acknowledge timing ............................................ 318 18-9 non-maskable interrupt request acknowledge operation ...................................... 319 18-10 interrupt request acknowledge processing algorithm ........................................... 321 18-11 interrupt request acknowledge timing (minimum time) ........................................ 322 18-12 interrupt request acknowledge timing (maximum time) ........................................ 322 18-13 multiple interrupt example (2/2) ................................................................................. 324 18-14 interrupt request hold ................................................................................................ 326 19-1 oscillation stabilization time select register format ............................................. 329 19-2 halt mode clear upon interrupt generation ............................................................ 331 19-3 halt mode release by reset input ......................................................................... 332 19-4 stop mode release by interrupt generation ............................................................ 334 19-5 release by stop mode reset input ......................................................................... 335 20-1 block diagram of reset function ............................................................................... 337 20-2 timing of reset input by reset input ...................................................................... 338 20-3 timing of reset due to watchdog timer overflow ................................................... 338 20-4 timing of reset input in stop mode by reset input ............................................. 338 21-1 memory size switching register format .................................................................. 343 21-2 internal extension ram size switching register format ........................................ 344 21-3 transmission method selection format .................................................................... 345 21-4 connection of flashpro using 3-wire serial i/o method ......................................... 346 21-5 flashpro connection using uart method ................................................................ 347 21-6 flashpro connection using pseudo 3-wire serial i/o .............................................. 347 a-1 development tool configuration ................................................................................ 365
23 pd1615, pd16f15, pd1616 contents of tables table no. title page 1-1 internal high capacity rom and ram ....................................................................................... ........ 26 1-2 differences between flash and mask rom version ........................................................................ 34 2-1-1 pin input/output types pd1615, pd16f15 .................................................................................. 36 2-1-2 pin input/output types pd1616 .................................................................................................... 37 2-2-1 non-port pins pd1615, pd16f15 .................................................................................................. 38 2-2-2 non-port pins pd1616 .................................................................................................................... 39 2-3-1 types of pin input/output circuits pd1615, pd16f15 (2/2) ...................................................... 44 2-3-2 types of pin input/output circuits pd1616 (2/2) ......................................................................... 46 3-1 internal rom capacities ................................................................................................... .................. 53 3-2 vectored interrupts ....................................................................................................... ....................... 54 3-3 special function register list (2/2 ....................................................................................... ............. 63 3-4 implied addressing ........................................................................................................ ...................... 69 3-5 register addressing ....................................................................................................... ..................... 70 3-6 direct addressing ......................................................................................................... ....................... 71 3-7 short direct addressing ................................................................................................... .................. 72 3-8 special-function register (sfr) addressing ................................................................................ ... 73 3-9 register indirect addressing .............................................................................................. ................ 74 3-10 based addressing ......................................................................................................... ..................... 75 3-11 based indexed addressing ................................................................................................. .............. 76 4-1 pin input/output types pd1615, pd16f15 .................................................................................. ... 79 4-2 pin input/output types pd1616 ............................................................................................ ............ 80 4-3 port configuration ........................................................................................................ ....................... 81 5-1 clock generator configuration ............................................................................................. ............. 96 5-2 maximum time required for cpu clock switchover ..................................................................... 105 6-1 configuration of 16-bit timer/event counter (tm0) ....................................................................... 10 9 6-2 valid edge of ti00 pin and valid edge of capture trigger of capture/compare register ........... 111 6-3 valid edge of ti01 pin and valid edge of capture trigger of capture/compare register ........... 111 7-1 8-bit timer/event counter 50 interval times ............................................................................... .... 144 7-2 8-bit timer/event counter 51 interval times ............................................................................... .... 144 7-3 8-bit timer/event counter 50 square-wave output ranges .......................................................... 145 7-4 8-bit timer/event counter 50 square-wave output ranges .......................................................... 145 7-5 8-bit timer/event counters 50 and 51 configurations ................................................................... 146 7-6 8-bit timer/event counters 50 interval times .............................................................................. ... 157 7-7 8-bit timer/event counters 51 interval times .............................................................................. ... 157 7-8 8-bit timer/event counters 50 square-wave output ranges ........................................................ 160 7-9 8-bit timer/event counters 51 square-wave output ranges ........................................................ 160
24 pd1615, pd16f15, pd1616 table no. title page 8-1 interval timer interval time .............................................................................................. ................. 168 8-2 watch timer configuration ................................................................................................. .............. 168 8-3 interval timer operation .................................................................................................. ................. 170 9-1 watchdog timer inadvertent program overrun detection times .................................................. 173 9-2 interval times ............................................................................................................ ......................... 173 9-3 watchdog timer configuration .............................................................................................. ........... 174 9-4 watchdog timer overrun detection time ..................................................................................... ... 177 9-5 interval timer interval time .............................................................................................. ................. 178 10-1 clock output control circuit configuration ............................................................................... .. 181 11-1 a/d converter configuration .............................................................................................. ............ 186 12-1 differences between the serial interface channels ...................................................................... 20 1 13-1 composition of sio30 ..................................................................................................... ................ 204 13-2 list of sfrs (special function registers) ................................................................................ .... 204 14-1 configuration of uart .................................................................................................... ................ 211 14-2 list of sfrs (special function registers) ................................................................................ .... 212 14-3 relation between 5-bit counters source clock and n value ................................................... 220 14-4 relation between main system clock and baud rate .................................................................. 221 14-5 causes of receive errors ................................................................................................. ............... 227 15-1 network speeds as a function of the quartz clock and the chosen division ratio ................ 237 15-2 error table .............................................................................................................. .......................... 239 15-3 frame responce ........................................................................................................... ................... 241 15-4 van uart registers ..................................................................................................... ................. 243 15-5 stop transmit ............................................................................................................ ....................... 247 15-6 acknowledge request ...................................................................................................... ............... 247 15-7 last-byte ................................................................................................................ ........................... 248 15-8 software reset ........................................................................................................... ...................... 249 15-9 enable / disable interrupt on the 12th bit of the identifier field .................................................. 250 15-10 rank 0 / rank 1 mode .................................................................................................... ................ 251 15-11 enable / disable in frame response ...................................................................................... ...... 251 15-12 mask enable / disable ................................................................................................... ................. 252 15-13 prescaler - network speeds as a function of the quartz clock and the chosen division ratio ...................................................................................................... .......................... 254 15-14 synchronous diagnosis clock ............................................................................................ ......... 254 15-15 enable the transmit diagnosis .......................................................................................... .......... 254 15-16 choice of communication mode ............................................................................................ ...... 255
25 pd1615, pd16f15, pd1616 table no. title page 15-17 la_resp, la ............................................................................................................. ..................... 260 15-18 eom ..................................................................................................................... ............................ 260 15-19 the bits sa and sb ...................................................................................................... .................. 263 15-20 the bit sc .............................................................................................................. .......................... 263 15-21 interrupt enable register (int_enable_reg) (2/2) ................................................................... 264 15-22 van clock selection register (udlccl) ................................................................................... .... 266 16-1 maximum number of display pixels ......................................................................................... ..... 269 16-2 lcd controller/driver configuration ...................................................................................... ....... 270 16-3 frame frequencies (hz) ................................................................................................... ............... 273 16-4 com signals .............................................................................................................. ....................... 277 16-5 lcd drive voltages ....................................................................................................... ................... 278 16-6 lcd drive voltages (with on-chip split resistor)connected externally) .................................. 281 16-7 selection and non-selection voltages (com0) ............................................................................. 2 84 16-8 selection and non-selection voltages (com0, com1) ................................................................ 287 16-9 selection and non-selection voltages (com0 to com2) ............................................................. 290 16-10 selection and non-selection voltages (com0 to com3) ........................................................... 294 17-1 sound generator configuration ............................................................................................ ......... 299 17-2 maximum and minimum values of the buzzer output frequency .............................................. 352 18-1 interrupt source list .................................................................................................... ................... 308 18-2 various flags corresponding to interrupt request sources ....................................................... 311 18-3 times from maskable interrupt request generation to interrupt service .................................. 320 18-4 interrupt request enabled for multiple interrupt during interrupt servicing ............................ 323 19-1 halt mode operating status ............................................................................................... ........... 330 19-2 operation after halt mode release ........................................................................................ ...... 332 19-3 stop mode operating status ............................................................................................... .......... 333 19-4 operation after stop mode release ........................................................................................ ...... 335 20-1 hardware status after reset (2/2) ........................................................................................ .......... 339 21-1 differences among pd16f15 and mask rom versions ............................................................... 342 21-2 values when the memory size switching register is reset ........................................................ 343 21-3 examples of internal extension ram size switching register settings .................................... 344 21-4 transmission method list ................................................................................................. .............. 345 21-5 main functions of flash memory programming ........................................................................... 346 22-1 operand identifiers and description methods .............................................................................. 350
26 pd1615, pd16f15, pd1616 1.1 features ? internal high capacity rom and ram table 1-1: internal high capacity rom and ram ? instruction execution time can be changed from ? van-interface high speed (0.25 s) to ultra low speed ? serial interface : 2 channels ? i/o ports: 57 ? 3-wire mode : 1 channel ? 8-bit resolution a/d converter : 4 channels ? uart mode : 1 channel ? sound generator ? timer : 5 channels ? lcd-controller / driver ? supply voltage : v dd = 4.0 to 5.5 v 1.2 application multifunction display, steering controller, climate controller etc. chapter 1 outline (pd1615 subseries) 1.3 ordering information part number package pd1615gc(a) - xxx - 8bt 80-pin plastic qfp (14 x 14 mm, resin thickness 1.4 mm) pd1616gc(a) - xxx - 8bt 80-pin plastic qfp (14 x 14 mm, resin thickness 1.4 mm) pd16f15gc - 8bt 80-pin plastic qfp (14 x 14 mm, resin thickness 1.4 mm) item program data memory part number memory (rom) internal high- speed ram lcd display ram internal expansion ram van package pd1615 32 k bytes 1024 bytes 40 bytes 512 bytes 256 bytes 80-pin plastic qfp (fine pitch) pd16f15 60 k bytes 1024 bytes 40 bytes 1024 bytes 256 bytes 80-pin plastic qfp (fine pitch) pd1616 32 k bytes 1024 bytes 512 bytes 256 bytes 80-pin plastic qfp (fine pitch)
27 pd1615, pd16f15, pd1616 cautions: 1. connect ic (internally connected) pin directly to v ss . 2. av dd pin should be connected to v dd . 3. av ss pin should be connected to v ss . figure 1-1: pin configuration pd 1615, pd16f15 1.4 pin configuration (top view) 80-pin plastic qfp (14 x 14 mm) pd1615gc(a) - xxx - 8bt pd1616gc(a) - xxx - 8bt pd16f15gc - 8bt p12/ani2 p11/ani1 p10/ani0 av dd /av ref reset x1 x2 v pp /ic cl1 cl2 v ss 0 v dd 0 p00/intp0 p01/intp1 p02/intp2 p06/ti50/to50 p07/ti51/to51 rx1van rx2van rx0van 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p105/s18 p104/s19 p103/s20 p102/s21 p101/s22 p100/s23 p97/s24 p96/s25 p95/s26 p94/s27 p93/s28 p92/s29 p91/s30 p90/s31 p87/s32 p86/s33 p85/s34 p84/s35 p83/s36 p82/s37 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p13/ani3 av ss p127/si3/s0 p126/so3/s1 p125/sck3/s2 p124/txd0/s3 p123/rxd0/s4 p122/ti01/s5 p121/ti00/to0/s6 p120/pcl/s7 p117/s8 p116/s9 p115/s10 p114/s11 p113/s12 p112/s13 p111/s14 p110/s15 p107/s16 p106/s17 txvan p47/sgo/sgof p46/sgoa p45 p44 p43 p42 p41 p40 v ss 1 v dd 1 vlc0 vlc1 vlc2 com0 com1 com2 com3 p80/s39 p81/s38 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
28 pd1615, pd16f15, pd1616 figure 1-2: pin configuration pd1616 cautions: 1. connect ic1 (internally connected) pin directly to v ss . 2. connect ic2 (internally connected) pin directly to v dd . 3. av dd pin should be connected to v dd . 4. av ss pin should be connected to v ss . 5. nc pins are not connected. p12/ani2 p11/ani1 p10/ani0 av dd /av ref reset x1 x2 ic1 cl1 cl2 v ss 0 v dd 0 p00/intp0 p01/intp1 p02/intp2 p06/ti50/to50 p07/ti51/to51 rx1van rx2van rx0van 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p105 p104 p103 p102 p101 p100 p97 p96 p95 p94 p93 p92 p91 p90 p87 p86 p85 p84 p83 p82 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p13/ani3 av ss p127/si3 p126/so3 p125/sck3 p124/txd0 p123/rxd0 p122/ti01 p121/ti00/to0 p120/pcl p117 p116 p115 p114 p113 p112 p111 p110 p107 p106 txvan p47/sgo/sgof p46/sgoa p45 p44 p43 p42 p41 p40 v ss 1 v dd 1 ic2 ic2 ic2 nc nc nc nc p80 p81 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
29 pd1615, pd16f15, pd1616 pin identifications p00 to p02, p06, p07 : port0 p10 to p13 : port1 p40 to p47 : port4 p80 to p87 : port8 p90 to p97 : port9 p100 to p107 : port10 p110 to p117 : port11 p120 to p127 : port12 intp0 to intp2 : interrupt external ti00, ti01, ti50, ti51 : timer input to0 , to51, to52 : timer output rx0van : van receive data rx1van : van receive data rx2van : van receive data txvan : van transmit data si3 : serial input so3 : serial output sck3 : serial clock rxd0 : r eceive data txd0 : transmit data sgo : sound generator output sgoa : sound generator amplitude sgof : sound generator frequency pcl : programmable clock output s0 to s39 : segment output com0 to com3: common output x1, x2 : crystal (main system clock) cl1, cl2 : rc (subsystem clock) reset : reset ani0 to ani3 : analog input av ss : analog ground av dd /av ref : analog power supply and reference voltage v pp : programming power supply v ss : ground ic, ic1, ic2 : internally connected nc : not connected
30 pd1615, pd16f15, pd1616 1.5 78k/0 series development these products are a further development in the 78k/0 series. the designations appearing inside the boxes are subseries names. pd780308 pd780308y pd78002 pd78083 products in mass production products under development y subseries products are compatible with i 2 c bus. timer added to the pd78054, external interface functions enhanced rom-less product for the pd78078 uart and d/a added to the pd78014, i/o enhanced low-voltage (1.8 v) operation version of the pd78014, rom and ram variations enhanced a/d and 16-bit timer added to the pd78002 basic subseries for control m m m m 100-pin 100-pin 80-pin 64-pin 64-pin 64-pin 100-pin 80-pin 64-pin 100-pin 80-pin for control pd78078 m m pd78070a pd78054 pd78018f pd78014 pd780001 64-pin 42/44-pin pd78078y pd78070ay pd78054y pd78018fy pd78014y pd78002y for fip driving pd780208 pd78044a pd78024 for lcd driving pd78064 pd78064y for iebus tm pd78098 i/o, fip c/d of the pd78044a enhanecd, display output total: 53 6-bit u/d counter added to the pd78024, display output total: 34 basic subseries for fip driving, display output total: 26 subseries for lcd driving, internal uart iebus controller added to the pd78054 m m m 78k/0 series internal uart, low-voltage (1.8 v) operation possible a/d added to the pd78002 canbus controller 100-pin 80-pin 64-pin pd780949 pd780826 pd780814
31 pd1615, pd16f15, pd1616 1.6 block diagram remark: the internal rom and ram capacity depends on the product. figure 1-3: block diagram pd 1615, pd16f15 16-bitcounter (tm0) sound generator 8-bit timer (tm50) 8-bit timer (tm51) watchdog timer rom 32 k bytes/ 78k/0 cpu core port 0 p06, p07 p00-p02, port 1 p10-p13 port 4 p40-p47 port 8 p80-p87 port 9 p90-p97 port 10 p100-p107 port 11 p110-p117 port 12 p120-p127 interrupt control intp0/p00- intp2/p02 standby control system control 8.0 m hz / 5 v reset x1 x2 ti00/to0/p121 p122/ti01 ti50/to50/p06 ti51/to51/p07 sgo/sgof/p47 sgoa/p46 watch timer uart rxd0/p123 txd0/p124 sio30 sck3/p125 so3/p126 si3/p127 a/d converter ani0 to ani3 av dd /av ref av ss clock output control pcl/p120 udl i/f van- uart udl txvan rx0van rx1van rx2van ram 1536 bytes/ 5 4 8 8 8 8 8 8 3 lcd controller/ driver com0-com3 p127/s0- p80/s39 vlc0-vlc2 rc oscillator cl1 cl2 v dd1 v dd0 v ss1 v ss0 ic 2048 bytes flash 60 k bytes
32 pd1615, pd16f15, pd1616 figure 1-4: block diagram pd1616 16-bitcounter (tm0) sound generator 8-bit timer (tm50) 8-bit timer (tm51) watchdog timer rom 32 k bytes 78k/0 cpu core port 0 p06, p07 p00-p02, port 1 p10-p13 port 4 p40-p47 port 8 p80-p87 port 9 p90-p97 port 10 p100-p107 port 11 p110-p117 port 12 p120-p127 interrupt control intp0/p00- intp2/p02 standby control system control 8.0 m hz / 5 v reset x1 x2 ti00/to0/p121 p122/ti01 ti50/to50/p06 ti51/to51/p07 sgo/sgof/p47 sgoa/p46 watch timer uart rxd0/p123 txd0/p124 sio30 sck3/p125 so3/p126 si3/p127 a/d converter ani0 to ani3 av dd /av ref av ss clock output control pcl/p120 udl i/f van- uart udl txvan rx0van rx1van rx2van ram 1536 bytes 5 4 8 8 8 8 8 8 3 rc oscillator cl1 cl2 v dd1 v dd0 v ss1 v ss0 ic1 ic2 nc
33 pd1615, pd16f15, pd1616 1.7 overview of functions part number item pd1615 pd1616 pd16f15 rom 32 kbytes 60 kbytes internal high-speed ram 1024 bytes lcd display ram 40 bytes 40 bytes internal memory internal expansion ram 512 bytes 1024 bytes memory space 64 kbytes general registers 8 bits x 32 registers ( 8 bits x 8 registers x 4 banks) instruction cycle on-chip instruction execution time selective function when main system clock selected 0,25 s/0,5 s/1 s/2 s/4 s (at 8 mhz) when subsystem clock selected 122 s (at 32.768 khz) instruction set 16-bit operation multiplication/division ( 8 bits x 8 bits, 16 bits C 8 bits ) bit manipulation ( set, reset, test, boolean operation ) bcd adjustment, etc. total : 57 i/o ports cmos input : 4 cmos i/o : 53 a/d converter 8 bit resolution x 4 channels serial interface 3-wire mode : 1 channel uart mode : 1 channel timer 16 bit timer / event counter : 1 channel 8 bit timer / event counter : 2 channels watch timer : 1 channel watchdog timer : 1 channel timer output 2 (8-bit pwm output x 2 ) clock output 62,5 khz, 125 khz, 250 khz, 500 khz, 1 mhz, 2 mhz, 4 mhz, 8 mhz (at main system clock of 8.0 mhz) sound generator 1 channel (as separate or composed output) lcd controller/driver 40 seg x 4 com van 1 channel maskable interrupts internal : 15 external : 3 non-maskable interrupts internal : 1 vectored interrupts software interrupts internal : 1 supply voltage v dd = 4,0 v to 5,5 v package 80-pin plastic qfp ( 14 mm x 14 mm )
34 pd1615, pd16f15, pd1616 1.8 mask options there are no mask options provided. 1.9 differences between flash and mask rom version the differences between the two versions are shown in the table below. differences of the electrical specification are given in the data sheet. table 1-2: differences between flash and mask rom version flash version mask rom version rom flash eeprom mask rom v pp pin yes none (ic pin)
35 pd1615, pd16f15, pd1616 [memo]
36 pd1615, pd16f15, pd1616 chapter 2 pin function (pd1615 subseries) 2.1 pin function list normal operating mode pins / pin input/output types table 2-1-1: pin input/output types pd 1615, pd16f15 input / output pin name function alternate function after reset p00 intp0 input p01 intp1 input p02 intp2 input p06 ti50/to50 input input / output p07 port 0 5 bit input / output port input / output mode can be specified bit-wise ti51/to51 input input p10-p13 port 1 4 bit input port input mode can be specified bit-wise ani0-ani3 input p40 - input p41 - input p42 - input p43 - input p44 - input p45 - input p46 sg0a input input / output p47 port 4 8 bit input/output port input / output mode can be specified bit-wise sg0/sg0f input input/ output p80-p87 port 8 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register s39 - s32 input input/ output p90-p97 port 9 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register s31 - s24 input input/ output p100- p107 port 10 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register s23 - s16 input input/ output p110- p117 port 11 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register s15 - s8 input p120 pcl/s7 p121 ti00/to0/s6 p122 ti01/s5 p123 rxd0/s4 p124 txd0/s3 p125 sck3/s2 p126 so3/s1 input/ output p127 port 12 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register si3/s0 input
37 pd1615, pd16f15, pd1616 table 2-1-2: pin input/output types pd1616 input / output pin name function alternate function after reset p00 intp0 input p01 intp1 input p02 intp2 input p06 ti50/to50 input input / output p07 port 0 5 bit input / output port input / output mode can be specified bit-wise ti51/to51 input input p10-p13 port 1 4 bit input port input mode can be specified bit-wise ani0-ani3 input p40 - input p41 - input p42 - input p43 - input p44 - input p45 - input p46 sg0a input input / output p47 port 4 8 bit input/output port input / output mode can be specified bit-wise sg0/sg0f input input/ output p80-p87 port 8 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register - input input/ output p90-p97 port 9 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register - input input/ output p100- p107 port 10 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register - input input/ output p110- p117 port 11 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register - input p120 pcl p121 ti00/to0 p122 ti01 p123 rxd0 p124 txd0 p125 sck3 p126 so3 input/ output p127 port 12 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register si3 input
38 pd1615, pd16f15, pd1616 2.2 non-port pins table 2-2-1: non-port pins pd1615, pd16f15 pin name i/o function after reset alternate function pin intp0 p00 intp1 p01 intp2 input external interrupts with specifiable valid edges (rising edge, falling edge, both rising and falling edges) input p02 si3 input serial interface serial data input input p127/s0 so3 output serial interface serial data output input p126/s1 sck3 input/ output serial interface serial clock input / output input p125/s2 rxd0 input asynchronous serial interface data input input p123/s4 txd0 output asynchronous serial interface data output input p124/s3 rx0van, rx1van, rx2van input van serial data input input - txvan output van serial data output output - ti00 p121/to0/s6 ti01 external count clock input to 16-bit timer (tm0) p122/s5 ti50 external count clock input to 8-bit timer (tm50) p06/to50 ti51 input external count clock input to 8-bit timer (tm51) input p07/to51 to0 16-bit timer output p121/ti00/s6 to50 8-bit timer output (also used for pwm output) p06/ti50 to51 output 8-bit timer output (also used for pwm output) input p07/ti51 pcl output clock output input p120/s7 s0 to s7 p127 to p120 s8 to s15 p117 to p110 s16 to s23 p107 to p100 s24 to s31 p97 to p90 s32 to s39 output segment signal output of lcd controller / driver input p87 to p80 com0-com3 output common signal output of lcd controller/driver output - v lc 0 to v lc 2 - lcd drive voltage - - sgo output sound generator output input p47/sgof sgoa output sound generator amplitude output input p46 sgof output sound generator frequency output input p47/sgo ani0 to ani3 input a/d converter analog input input p10 C p13 av dd/ av ref - a/d converter reference voltage input and power supply -- av ss - a/d converter ground potential. connect to v ss. -- reset input system reset input - - x1 - connection for main system clock - - x2 - connection for main system clock - - cl1 input rc connection for subsystem clock - - cl2 - rc connection for subsystem clock - - v dd 1, v dd 2 - positive power supply - - v ss 1, v ss 2 - ground potential - - ic - internal connection. connect directly to v ss -- v pp - programming voltage. connect directly to v ss except flash programming. --
39 pd1615, pd16f15, pd1616 table 2-2-2: non-port pins pd1616 pin name i/o function after reset alternate function pin intp0 p00 intp1 p01 intp2 input external interrupts with specifiable valid edges (rising edge, falling edge, both rising and falling edges) input p02 si3 input serial interface serial data input input p127 so3 output serial interface serial data output input p126 sck3 input/ output serial interface serial clock input / output input p125 rxd0 input asynchronous serial interface data input input p123 txd0 output asynchronous serial interface data output input p124 rx0van, rx1van, rx2van input van serial data input input - txvan output van serial data output output - ti00 p121/to0 ti01 external count clock input to 16-bit timer (tm0) p122 ti50 external count clock input to 8-bit timer (tm50) p06/to50 ti51 input external count clock input to 8-bit timer (tm51) input p07/to51 to0 16-bit timer output p121/ti00 to50 8-bit timer output (also used for pwm output) p06/ti50 to51 output 8-bit timer output (also used for pwm output) input p07/ti51 pcl output clock output input p120 sgo output sound generator output input p47/sgof sgoa output sound generator amplitude output input p46 sgof output sound generator frequency output input p47/sgo ani0 to ani3 input a/d converter analog input input p10 C p13 av dd/ av ref - a/d converter reference voltage input and power supply -- av ss - a/d converter ground potential. connect to v ss. -- reset input system reset input - - x1 - connection for main system clock - - x2 - connection for main system clock - - cl1 input rc connection for subsystem clock - - cl2 - rc connection for subsystem clock - - v dd 1, v dd 2 - positive power supply - - v ss 1, v ss 2 - ground potential - - ic1 - internal connection. connect directly to v ss -- ic2 - internal connection. connect directly to v dd -- nc - not connected - -
40 pd1615, pd16f15, pd1616 2.3 description of pin functions 2.3.1 p00 to p02, p06 and p07 (port 0) this is a 5-bit input/output port. beside serving as input/output port, it supports functions as an external interrupt input, an external count clock input to the timer and a timer signal output. the following operating modes can be specified bit-wise. (1) port mode p00 to p02, p06 and p07 function as input/output ports. p00 to p02, p06 and p07 can be specified for input or output ports bitwise with a port mode register 0. (2) control mode in this mode, this port supports the function like external interrupt input, an external count clock input to the timer and a timer signal output. (a) intp0 to intp2 intp0 to intp2 are external interrupt input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). (b) ti50 pin for external count clock input to 8-bit timer/event counter. (c) ti51 pin for external count clock input to 8-bit timer/event counter. (d) to50 pin for output of the 8-bit timer/event counter. (e) to51 pin for output of the 8-bit timer/event counter. 2.3.2 p10 to p13 (port 1) this is a 4-bit input port. beside serving as input port, it functions as an a/d converter analog input. the following operating modes can be specified bit-wise. (1) port mode thisport functions as 4-bit input ports. (2) control mode this port functions as a/d converter analog input pins (ani0 to ani3). 2.3.3 p40 to p47 (port 4) this is an 8-bit input/output port. beside serving as input/output port, this port functions as sound generator output. the following operating modes can be specified bit-wise. (1) port mode this port functions as an 8-bit input/output port. it can be specified bit-wise as input or output ports with the port mode register 4.
41 pd1615, pd16f15, pd1616 (2) control mode this port functions as timer input, clock output, and sound generator output. (a) sgo, sgoa and sgof pins for separate or composed signal ouput of the sound generator. 2.3.4 p80 to p87 (port 8) this is an 8-bit input/output port. beside serving as input/output port, this port supports an lcd controller/driver. the following operating modes can be specified bit-wise. (1) port mode this port functions as an 8-bit input/output port. it can be specified bit-wise as input/ output ports with the port mode register 8. (2) control mode in this mode it functions as segment signal output pins (s32 to s39) of the lcd controller/ driver. 2.3.5 p90 to p97 (port 9) this is an 8-bit input/output port. in addition to its use as an input/output port, it supports also segment signal output function of the lcd controller/driver. the following operating modes can be specified bit-wise. (1) port mode port 9 functions as an 8-bit input/output port. bit-wise specification as an input port or output port is possible by meaning of port mode register 9. (2) control mode port 9 supports the segment signal output pins (s24 to s31) of the lcd controller/driver. 2.3.6 p100 to p107 (port 10) this is an 8-bit input/output port. in addition to its use as an input/output port, it supports also segment signal output functions of the lcd controller/driver. the following operating modes can be specified bit-wise. (1) port mode port 10 functions as an 8-bit input/output port. bit-wise specification as an input port or output port is possible by meaning of port mode register 10. (2) control mode port 10 supports the segment signal output pins (s16 to s23) of the lcd controller/driver. 2.3.7 p110 to p117 (port 11) this is an 8-bit input/output port. in addition to its use as an input/output port, it supports also segment signal output functions of the lcd controller/driver. the following operating modes can be specified bit-wise. (1) port mode port 11 functions as an 8-bit input/output port. bit-wise specification as an input port or output port is possible by meaning of port mode register 11.
42 pd1615, pd16f15, pd1616 (2) control mode port 11 supports the segment signal output pins (s15 to s8) of the lcd controller/driver. 2.3.8 p120 to p127 (port 12) these are 8-bit input/output ports. besides serving as input/output ports, they function as data input/output to/from the serial interface, serial interface clock input/output, as segment signal output pins of lcd controller/driver and as processor clock output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 12. (2) control mode these ports function as serial interface data input/output, clock input/output. (a) si3, so3 serial interface serial data input/output pins (b) sck3 serial interface serial clock input/output pins (c) rxd0, txd0 asynchronous serial interface data input/output pins (d) pcl clock output pin. (e) lcd controller/driver these ports function as segment output signal pins (s0 to s7) of lcd controller/driver. caution: when this port is used as a serial interface, the i/o and output latches must be set according to the function the user requires. 2.3.9 com0 to com3 these are lcd controller/driver common signal output pins. they output common signals under the following condition: - static mode - 1/2 duty cycle is performed in 1/2 bias mode - 1/3 duty cycle is performed in 1/2 bias mode - 1/3 duty cycle is performed in 1/3 bias mode - 1/4 duty cycle is performed in 1/3 bias mode 2.3.10 vlc0 to vlc2 these are lcd drive voltage pins. in the flash eeprom and the maskrom product an external split resistors are necessary.
43 pd1615, pd16f15, pd1616 2.3.11 av dd /av ref a/d converter reference voltage input pin and the power supply for the a/d-converter. when a/d converter is not used, connect this pin to v dd . 2.3.12 av ss this is a ground voltage pin of a/d converter. always use the same voltage as that of the vss pin even when a/d converter is not used. 2.3.13 reset this is a low-level active system reset input pin. 2.3.14 x1 and x2 crystal resonator connect pins for main system clock oscillation. for external clock supply, input it to x1. 2.3.15 cl1 and cl2 crystal resonator connect pins for subsystem clock oscillation. for external clock supply, input it to cl1 and let cl2 open. 2.3.16 v dd 0/v dd 1 positive power supply pins. 2.3.17 v ss 0/v ss 1 ground potential pins. 2.3.18 v pp ( pd16f15 only ) high-voltage apply pin for flash programming mode setting. connect it directly to vss with the shortest possible wire in the normal operating mode. when a voltage difference is produced between the ic pin and vss pin because the wiring between those two pins is too long or an external noise is input to the ic pin, the users program may not run normally. figure 2-1: connection of ic pins ? connect ic pins to vss pins directly . vss ic as short as possible
44 pd1615, pd16f15, pd1616 2.4 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in the following table. for the input/output circuit configuration of each type, see table. table 2-3-1: types of pin input/output circuits pd1615, pd16f15 (1/2) pin name input/output circuit type i/o recommended connection for unused pins p00/intp0 p01/intp1 p02/intp2 p06/ti50/to50 p07/ti51/to51 8 i/o connect to v ss via a resistor individually p10/ani0 p11/ani1 p12/ani2 p13/ani3 9 i connect to v dd or v ss via a resistor individually p40 p41 p42 p43 p44 p45 p46/sgoa p47/sgo/sgof 5 i/o connect to v dd or v ss via a resistor individually p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 17 i/o connect to v dd or v ss via a resistor individually p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 p95/s26 p96/s25 p97/s24 17 i/o connect to v dd or v ss via a resistor individually
45 pd1615, pd16f15, pd1616 table 2-3-1: types of pin input/output circuits pd1615, pd16f15 (2/2) pin name input/output circuit type i/o recommended connection for unused pins p100/s23 p101/s22 p102/s21 p103/s20 p104/s19 p105/s18 p106/s17 p107/s16 17 i/o connect to v dd or v ss via a resistor individually p110/s15 p111/s14 p112/s13 p113/s12 p114/s11 p115/s10 p116/s9 p117/s8 17 i/o connect to v dd or v ss via a resistor individually p120/s7/pcl 17 p121/s6/ti00/to0 17-c p122/s5/ti01 17-c p123/s4/rxd0 17-c p124/s3/txd0 17 p125/s2/sck3 17-c p126/s1/so3 17 p127/s0/si3 17-c i/o connect to v dd or v ss via a resistor individually com0 C com3 18 o leave open v lc 0 C v lc 2 - - connect to v dd rx0van, rx1van, rx2van 2i - txvan 19 o - cl1 - i connect to v dd or v ss cl2 - - leave open reset 2 i - av dd - i connect to v dd av ss - - connect to v ss ic - - connect directly to v ss v pp 1- connect directly to v ss (except for flash programming)
46 pd1615, pd16f15, pd1616 table 2-3-2: types of pin input/output circuits pd1616 (1/2) pin name input/output circuit type i/o recommended connection for unused pins p00/intp0 p01/intp1 p02/intp2 p06/ti50/to50 p07/ti51/to51 8 i/o connect to v dd or v ss via a resistor individually p10/ani0 p11/ani1 p12/ani2 p13/ani3 9 i connect to v dd or v ss via a resistor individually p40 p41 p42 p43 p44 p45 p46/sgoa p47/sgo/sgof 5 i/o connect to v dd or v ss via a resistor individually p80 p81 p82 p83 p84 p85 p86 p87 5 i/o connect to v dd or v ss via a resistor individually p90 p91 p92 p93 p94 p95 p96 p97 5 i/o connect to v dd or v ss via a resistor individually
47 pd1615, pd16f15, pd1616 table 2-3-2: types of pin input/output circuits pd1616 (2/2) pin name input/output circuit type i/o recommended connection for unused pins p100 p101 p102 p103 p104 p105 p106 p107 8 i/o connect to v dd or v ss via a resistor individually p110 p111 p112 p113 p114 p115 p116 p117 5 i/o connect to v dd or v ss via a resistor individually p120/ pcl 5 p121/ti00/to0 8 p122/ti01 8 p123/rxd0 8 p124/ txd0 5 p125/ sck3 8 p126/so3 5 p127/si3 8 i/o connect to v dd or v ss via a resistor individually rx0van, rx1van, rx2van 2i - txvan 19 o - cl1 - i connect to v dd or v ss cl2 - - leave open reset 2 i - av dd - i connect to v dd av ss - - connect to v ss ic1 - - connect directly to v ss ic2 - - connect directly to v dd nc - - leave open
48 pd1615, pd16f15, pd1616 figure 2-2: pin input/output circuits (1/2) type 1 in input data type 2 data output disable v p-ch n-ch in/out dd input enable type 5 data output disable v p-ch n-ch in/out dd type 8 type 9 + - in p-ch n-ch comparator input enable v ref (threshold voltage) in input data
49 pd1615, pd16f15, pd1616 figure 2-2: pin input/output circuits (2/2) type 17 type 17-c data output disable v p-ch n-ch in/out dd input enable p-ch p-ch n-ch p-ch n-ch n-ch v lc0 v lc1 v lc2 seg data data output disable v p-ch n-ch in/out dd p-ch p-ch n-ch p-ch n-ch n-ch v lc0 v lc1 v lc2 seg data type 18 p-ch n-ch v lc0 v lc1 v lc2 com out type 19 n-ch out data p-ch p-ch p-ch n-ch n-ch n-ch n-ch
50 pd1615, pd16f15, pd1616 [memo]
51 pd1615, pd16f15, pd1616 3.1 memory space the memory map of the pd1615, pd1616 is shown in figure 3-1. figure 3-1: memory map (pd1615, pd1616) chapter 3 cpu architecture note: the lcd display ram is not available in the pd1616. ffffh ff00h feffh fee0h fedfh f900h f8ffh fa00h f9ffh 8000h 7fffh 0000h 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h lcd display ram 40 x 4 bits internal expansion ram 512 x 8 bits program area callf entry area program area callt table area vector table area special function registers (sfrs) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal rom 32768 x 8 bits not usable not usable not usable ff20h ff1fh fe20h fa28h fa27h fb00h faffh f800h f7ffh f600h f5ffh van udl ram 256 x 8 bits
52 pd1615, pd16f15, pd1616 the memory map of the pd16f15 is shown in figure 3-2. figure 3-2: memory map (pd16f15) ffffh ff00h feffh fee0h fedfh f900h f8ffh fa00h f9ffh f000h efffh 0000h efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h not usable internal expansion ram 1024 x 8 bits program area callf entry area program area callt table area vector table area special function registers (sfrs) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal flash eeprom 61440 x 8 bits lcd display ram not usable ff20h ff1fh fe20h fa28h fa27h fb00h faffh f800h f7ffh f400h f3ffh van udl ram 40 x 4 bits 256 x 8 bits not usable
53 pd1615, pd16f15, pd1616 3.1.1 internal program memory space the internal program memory space stores programs and table data. this is generally accessed by the program counter (pc). the pd1615 subseries have various size of internal roms or flash eprom as shown below. table 3-1: internal rom capacities the internal program memory is divided into three areas: vector table area, callt instruction table area, and callf instruction table area. these areas are described on the next page. part number internal rom type capacity m pd1615 mask rom 32768 x 8-bits m pd1616 mask rom 32768 x 8-bits m pd16f15 flash 61440 x 8-bits
54 pd1615, pd16f15, pd1616 (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses. (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). table 3-2: vectored interrupts vector table address interrupt request 0004h inwdt 0006h intve 0008h intvt 000ah inttvr 000ch intp0 000eh intp1 0010h intp2 0012h inttm00 0014h inttm01 0016h inttm50 0018h inttm51 001ah intwti 001ch intwt 001eh intcsi3 0020h intser 0022h intsr 0024h intst 0026h intad
55 pd1615, pd16f15, pd1616 3.1.2 internal data memory space the pd1615 subseries units incorporate the following rams. (1) internal high-speed ram this is a 1024 x 8-bit configuration in the area fb00h to feffh 4 banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area fee0h to feffh. the internal high-speed ram can also be used as a stack memory. (2) lcd-display ram buffer ram is allocated to the 40 x 4 bits area from fa00h to fa27h. lcd-display ram can also be used as normal ram. the lcd display ram is not available in the pd1616. (3) internal expansion ram internal expansion ram is allocated to the 1024-byte area from f400h to f7ffh for the pd16f15. for the pd1615, pd1616 is the 512-byte area located between f600h and f7ffh. (4) van udl ram the van udl ram is located in a 256-byte area from f800h to f8ffh. 3.1.3 special function register (sfr) area an on-chip peripheral hardware special function register (sfr) is allocated in the area ff00h to ffffh. (refer to table 3-3 ). caution: do not access addresses where the sfr is not assigned.
56 pd1615, pd16f15, pd1616 3.1.4 data memory addressing the pd1615 subseries is provided with a varity of addressing modes which take account of memory manipulability, etc. special addressing methods are possible to meet the functions of the special function registers (sfrs) and general registers. the data memory space is the entire 64k-byte space (0000h to ffffh). figures 3-3 and 3-4 show the data memory addressing modes. for details of addressing, refer to 3.4 operand address addressing . figure 3-3: data memory addressing (pd1615, pd1616) ffffh ff00h feffh fa28h fa27h fee0h fedfh f900h f8ffh 8000h 7fffh 0000h lcd display ram 40 x 4 bits internal expansion ram 512 x 8 bits special function registers (sfrs) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal rom 32768 x 8 bits not usable not usable not usable ff20h ff1fh fe20h fad0h f9ffh fb1fh fb00h faffh f800h f7ffh f600h f5ffh sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing van udl ram 256 x 8 bits
57 pd1615, pd16f15, pd1616 figure 3-4: data memory addressing (pd16f15) ffffh ff00h feffh fa28h fa27h fee0h fedfh f900h f8ffh f000h efffh 0000h lcd display ram 40 x 4 bits internal expansion ram 1024 x 8 bits special function registers (sfrs) 256 x 8 bits general registers 32 x 8 bits internal high-speed ram 1024 x 8 bits internal flash eeprom 61440 x 8 bits not usable not usable not usable ff20h ff1fh fe20h fa00h f9ffh fb1fh fb00h faffh f800h f7ffh f400h f3ffh sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing van udl ram 256 x 8 bits
58 pd1615, pd16f15, pd1616 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 3-6: program status word configuration pc 15 0 70 ie z rbs1 ac rbs0 0 isp cy 3.2 processor registers the pd1615 subseries units incorporate the following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses, and stack memory. the control registers consist of a program counter, a program status word and a stack pointer. (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-5: program counter configuration
59 pd1615, pd16f15, pd1616 (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when 0, the ie is set to interrupt disabled (di) status. all interrupts except non-maskable interrupt are disabled. when 1, the ie is set to interrupt enabled (ei) status and interrupt request acknowledge is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources, and a priority specification flag. the ie is reset to (0) upon di instruction execution or interrupt request acknowledgement and is set to (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when 0, acknowl- edgment of the vectored interrupt request specified to low-order priority with the priority specify flag registers (pr0l, pr0h, and pr1l) is disabled. whether an actual interrupt request is acknowledged or not is controlled with the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift- out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
60 pd1615, pd16f15, pd1616 (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-7: stack pointer configuration the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 3-8 and 3-9. caution: since reset input makes sp contents indeterminate, be sure to initialize the sp before instruction execution. figure 3-8: data to be saved to stack memory 0 15 sp interrupt and brk instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instruction push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 reti and retb instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7 to pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3 figure 3-9: data to be reset to stack memory
61 pd1615, pd16f15, pd1616 3.2.2 general registers a general register is mapped at particular addresses (fee0h to feffh) of the data memory. it consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can also be used as an 8-bit register. two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank. figure 3-10: general register configuration (a) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fee0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h (b) function name
62 pd1615, pd16f15, pd1616 3.2.3 special function register (sfr) unlike a general register, each special function register has special functions. it is allocated in the ff00h to ffffh area. the special function registers can be manipulated in a similar way as the general registers, by using operation, transfer, or bit-manipulate instructions. the special function registers are read from and written to in specified manipulation bit units (1, 8, and/or 16) depending on the register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 3-3 gives a list of special function registers. the meaning of items in the table is as follows. ? symbol the assembler software translates these symbols into corresponding addresses where the special function registers are allocated. these symbols should be used as instruction operands in the case of programming. ? r/w this column shows whether the corresponding special function register can be read or written. r/w : both reading and writing are enabled. r : the value in the register can read out. a write to this register is ignored. w : a value can be written to the register. reading values from the register is impossible. ? manipulation the register can be manipulated in bit units. ? after reset the register is set to the value immediately after the reset signal is input.
63 pd1615, pd16f15, pd1616 table 3-3: special function register list (1/2) address sfr name symbol r/w manipulatable bit unit after 1 bit 8 bits 16 bits reset ff00h port 0 p0 r/w ?? 00h ff01h port 1 p1 r ?? 00h ff04h port 4 p4 r/w ?? 00h ff08h port 8 p8 r/w ?? 00h ff09h port 9 p9 r/w ?? 00h ff0ah port 10 p10 r/w ?? 00h ff0bh port 11 p11 r/w ?? 00h ff0ch port 12 p12 r/w ?? 00h ff10h 8 bit compare register 50 cr50 r/w ? 00h ff11h 8 bit compare register 51 cr51 r/w ? 00h ff12h 8 bit timer/counter 50 tm50 r ? 00h ff13h 8 bit timer/counter 51 tm51 r ? 00h ff14h ff15h 16bit capture/compare register 00 cr00 r/w ? 0000h ff16h ff17h 16bit capture/compare register 01 cr01 r/w ? 0000h ff18h serial shift register sio3 r/w ? 00h transmission shift register txs0 w ? ffh ff1ah reception shift register rxb0 r ? ffh ff1bh a/d conversion result register adcr1 r ? 00h ff20h port mode register 0 pm0 r/w ?? ffh ff24h port mode register 4 pm4 r/w ?? ffh ff28h port mode register 8 pm8 r/w ?? ffh ff29h port mode register 9 pm9 r/w ?? ffh ff2ah port mode register 10 pm10 r/w ?? ffh ff2bh port mode register 11 pm11 r/w ?? ffh ff2ch port mode register 12 pm12 r/w ?? ffh ff40h clock output select register cks r/w ?? 00h ff41h watch timer operation mode register wtm r/w ?? 00h ff42h watchdog timer clock select register wdcs r/w ? 00h ff48h external interrupt rising edge enable register egp r/w ?? 00h ff49h external interrupt falling edge enable register egn r/w ?? 00h ff58h port function register 8 pf8 r/w ?? 00h ff59h port function register 9 pf9 r/w ?? 00h ff5ah port function register 10 pf10 r/w ?? 00h ff5bh port function register 11 pf11 r/w ?? 00h ff5ch port function register 12 pf12 r/w ?? 00h
64 pd1615, pd16f15, pd1616 table 3-3: special function register list (2/2) manipulatable bit unit address sfr name symbol r/w 1 bit 8 bits 16 bits after reset ff60h 16-bit timer mode control register 0 tmc0 r/w ?? 00h ff61h prescaler mode register 0 prm0 r/w ? 00h ff62h capture compare control register 0 crc0 r/w ?? 00h ff63h timer output control register 0 toc0 r/w ?? 00h ff64h ff65h 16-bit timer/counter 0 tm0 r ? 00h ff66h sound generator control register sgcr r/w ?? 00h ff67h sound generator 7-bit amplitude register sgam r/w ?? 00h ff68h sound generator buzzer control register sgbr r/w ?? 00h ff6fh serial i/f mode register csim3 r/w ?? 00h ff70h 8-bit timer mode control register 50 tmc50 r/w ?? 04h ff71h timer clock select register 50 tcl50 r/w ? 00h ff74h 8-bit timer mode control register 51 tmc51 r/w ?? 04h ff75h timer clock select register 51 tcl51 r/w ? 00h ff78h van-udl clock control register udlccl r/w ? 00h ff80h a/d converter mode register 1 adm1 r/w ?? 00h ff81h analog input channel specification register 1 ads1 r/w ? 00h ff82h power fail detector value comparison mode register pfm r/w ? 00h ff83h power fail detector threshold value setting register pft r/w ? 00h ff84h on emulator for power-fail detection dam0 r/w ?? 00h ffa0h asynchronous serial interface mode register asim0 r/w ?? 00h ffa1h asynchronous serial interface status register asis0 r/w ? 00h ffa2h baud rate generator control register brgc0 r/w ? 00h ffb0h lcd display mode register lcdm r/w ?? 00h ffb2h lcd clock control register lcdc r/w ?? 00h ffe0h interrupt request flag register if0l r/w ?? 00h ffe1h interrupt request flag register if0 if0h r/w ?? ? 00h ffe2h interrupt request flag register if1l r/w ?? ? 00h ffe4h interrupt mask flag register mk0l r/w ?? ffh ffe5h interrupt mask flag register mk0 mk0h r/w ?? ? ffh ffe6h interrupt mask flag register mk1l r/w ?? ffh ffe8h priority flag specification register pr0l r/w ?? ffh ffe9h priority flag specification register pr0 pr0h r/w ?? ? ffh ffeah priority flag specification register pr1l r/w ?? 00h fff0h internal memory size switching register ims r/w ? cfh fff4h internal extended ram size switching register ixs r/w ? 0ch fff9h watchdog timer mode register wdtm r/w ?? 00h fffah oscillation stabilisation time select register osts r/w ? 04h fffbh processor clock control register pcc r/w ?? 04h
65 pd1615, pd16f15, pd1616 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. however, when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing. (for details of instructions, refer to 78k/0 user's manual - instructions (u12326e) . 3.3.1 relative addressing the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed twos complement data (-128 to +127) and bit 7 becomes a sign bit. in other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. 15 0 pc + 15 0 876 s 15 0 pc a jdisp8 when s = 0, all bits of a are 0. when s = 1, all bits of a are 1. pc indicates the start address of the instruction after the br instruction. ... figure 3-11: relative addressing
66 pd1615, pd16f15, pd1616 3.3.2 immediate addressing immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can branch to all the memory space. callf !addr11 instruction branches to the area from 0800h to 0fffh. 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10? 11 10 00001 643 callf fa 7? in the case of call !addr16 and br !addr16 instructions figure 3-12: immediate addressing in the case of callf !addr11 instruction
67 pd1615, pd16f15, pd1616 3.3.3 table indirect addressing table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. table indirect addressing is carried out when the callt [addr5] instruction is executed. this instruction can refer to the address stored in the memory table 40h to 7fh and branch to all the memory space. 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4? operation code figure 3-13: table indirect addressing
68 pd1615, pd16f15, pd1616 3.3.4 register addressing register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. 70 rp 07 ax 15 0 pc 87 figure 3-14: register addressing
69 pd1615, pd16f15, pd1616 3.4 operand address addressing the following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 implied addressing the register which functions as an accumulator (a and ax) in the general register is automatically (implicitly) addressed. operand format because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. description example in the case of mulu x with an 8-bit x 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing. table 3-4: implied addressing instruction register to be specified by implied addressing mulu a register for multiplicant and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data which undergoes digit rotation
70 pd1615, pd16f15, pd1616 3.4.2 register addressing the general register is accessed as an operand. the general register to be accessed is specified with register bank select flags (rbs0 and rbs1) and register specify code (rn, rpn) in the instruction code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. operand format 01100010 register specify code operation code 10000100 register specify code operation code r and rp can be described with function names (x, a, c, b, e, d, l, h, ax, bc, de and hl) as well as absolute names (r0 to r7 and rp0 to rp3). description example mov a, c; when selecting c register as r incw de; when selecting de register pair as rp table 3-5: register addressing identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl figure 3-15: register addressing
71 pd1615, pd16f15, pd1616 3.4.3 direct addressing the memory indicated by immediate data in an instruction word is directly addressed. operand format description example mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op code 00000000 00h 11111110 feh table 3-6: direct addressing identifier description addr16 label or 16-bit immediate data
72 pd1615, pd16f15, pd1616 3.4.4 short direct addressing the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space to which this addressing is applied to is the 256-byte space, from fe20h to ff1fh. an internal high-speed ram and a special function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area where short direct addressing is applied (ff00h to ff1fh) is a part of the sfr area. in this area, ports which are frequently accessed in a program, a compare register of the timer/event counter, and a capture register of the timer/event counter are mapped and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to figure 3-16 below. operand format description example mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h. operation code 00010001 op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) illustration when 8-bit immediate data is 20h to ffh, a = 0 when 8-bit immediate data is 00h to 1fh, a = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset a identifier description saddr label of fe20h to ff1fh immediate data saddrp label of fe20h to ff1fh immediate data (even address only) table 3-7: short direct addressing figure 3-16: short direct addressing
73 pd1615, pd16f15, pd1616 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 3.4.5 special function register (sfr) addressing the memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. operand format description example mov pm0, a; when selecting pm0 (fe20h) as sfr operation code 11110110 op code 00100000 20h (sfr-offset) illustration table 3-8: special-function register (sfr) addressing figure 3-17: special-function register (sfr) addressing identifier description sfr special-function register name sfrp 16-bit manipulatable special-function register name (even address only)
74 pd1615, pd16f15, pd1616 3.4.6 register indirect addressing the memory is addressed with the contents of the register pair specified as an operand. the register pair to be accessed is specified with the register bank select flag (rbs0 and rbs1) and the register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. operand format description example mov a, [de]; when selecting [de] as register pair operation code 10000101 illustration 16 0 8 d 7 e memory the contents of addressed memory are transferred memory address specified by register pair de 0 7 7 0 a de table 3-9: register indirect addressing figure 3-18: special-function register (sfr) addressing identifier description [de], [hl]
75 pd1615, pd16f15, pd1616 3.4.7 based addressing 8-bit immediate data is added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. the hl register pair to be accessed is in the register bank specified with the register bank select flags (rbs0 and rbs1). addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. operand format description example mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 table 3-10: based addressing identifier description [hl + byte]
76 pd1615, pd16f15, pd1616 3.4.8 based indexed addressing the b or c register contents specified in an instruction are added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. the hl, b, and c registers to be accessed are registers in the register bank specified with the register bank select flag (rbs0 and rbs1). addition is performed by expanding the contents of the b or c register as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. operand format description example in the case of mov a, [hl + b] operation code 1 0101011 3.4.9 stack addressing the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. description example in the case of push de operation code 1 0110101 table 3-11: based indexed addressing identifier description [hl + b], [hl + c]
77 pd1615, pd16f15, pd1616 [memo]
78 pd1615, pd16f15, pd1616 chapter 4 port functions 4.1 port functions the pd1615 subseries units incorporate four input ports and fifty-three input/output ports. figure 4-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as on-chip hardware input/output pins. figure 4-1: port types port0 port9 port1 p00 p90 p97 p10 p07 p13 p100 p107 port10 p110 p117 port11 p120 p127 port12 port4 p40 p47 p01 p02 p06 port8 p80 p87
79 pd1615, pd16f15, pd1616 table 4-1: pin input/output types pd1615, pd16f15 input / output pin name function alternate function after reset p00 intp0 input p01 intp1 input p02 intp2 input p06 ti50/to50 input input / output p07 port 0 5 bit input / output port input / output mode can be specified bit-wise ti51/to51 input input p10-p13 port 1 4 bit input port input mode can be specified bit-wise ani0-ani3 input p40 - input p41 - input p42 - input p43 - input p44 - input p45 - input p46 sg0a input input / output p47 port 4 8 bit input/output port input / output mode can be specified bit-wise sg0/sg0f input input/ output p80-p87 port 8 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register s39 - s32 input input/ output p90-p97 port 9 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register s31 - s24 input input/ output p100- p107 port 10 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register s23 - s16 input input/ output p110- p117 port 11 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register s15 - s8 input p120 pcl/s7 p121 ti00/to0/s6 p122 ti01/s5 p123 rxd0/s4 p124 txd0/s3 p125 sck3/s2 p126 so3/s1 input/ output p127 port 12 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register si3/s0 input
80 pd1615, pd16f15, pd1616 table 4-2: pin input/output types pd1616 input / output pin name function alternate function after reset p00 intp0 input p01 intp1 input p02 intp2 input p06 ti50/to50 input input / output p07 port 0 5 bit input / output port input / output mode can be specified bit-wise ti51/to51 input input p10-p13 port 1 4 bit input port input mode can be specified bit-wise ani0-ani3 input p40 - input p41 - input p42 - input p43 - input p44 - input p45 - input p46 sg0a input input / output p47 port 4 8 bit input/output port input / output mode can be specified bit-wise sg0/sg0f input input/ output p80-p87 port 8 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register - input input/ output p90-p97 port 9 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register - input input/ output p100- p107 port 10 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register - input input/ output p110- p117 port 11 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register - input p120 pcl p121 ti00/to0 p122 ti01 p123 rxd0 p124 txd0 p125 sck3 p126 so3 input/ output p127 port 12 8 bit input / output port input / output mode can be specified bit-wise this port can be used as segment signal output port or an i/o port in 1-bit units by setting port function register si3 input
81 pd1615, pd16f15, pd1616 4.2 port configuration a port consists of the following hardware: table 4-3: port configuration 4.2.1 port 0 port 0 is an 5-bit input/output port with output latch. p00 to p02 and p06, p07 pins can be specified as input mode/output mode in 1-bit units with the port mode register 0 (pm0). dual-functions include external interrupt request input. reset input sets port 0 to input mode. figure 4-2 shows block diagram of port 0. caution: because port 0 also supports the external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1. item configuration port mode register (pmm: m = 0, 4, 8 to 12) control register port function register (pfm: m = 8 to 12) port total: 57 ports
82 pd1615, pd16f15, pd1616 figure 4-2: p00 to p02 and p06, p07 configurations pm : port mode register rd : port 0 read signal wr : port 0 write signal wr pm wr port rd p00/intp0, p01/intp1, p02/intp02, selector output latch (p00 to p02, p06, p07) pm00 to pm02, p06, p07 internal bus p06/ti50/to50, p07/ti51/to51
83 pd1615, pd16f15, pd1616 4.2.2 port 1 port 1 is a 4-bit input only port. dual-functions include an a/d converter analog input. figure 4-3 shows a block diagram of port 1. figure 4-3 : p10 to p13 configurations rd : port 1 read signal rd p10/ani0 to p13/ani13 internal bus
84 pd1615, pd16f15, pd1616 4.2.3 port 4 port 4 is an 8-bit input/output port with output latch. p40 to p47 pins can specify the input mode/output mode in 1-bit units. dual-function includes the sound generator output. reset input sets port 4 to input mode. figure 4- 4 shows a block diagram of port 4. figure 4-4: p40 to p47 configurations pm : port mode register rd : port 4 read signal wr : port 4 write signal wr pm wr port rd p40 to p45, p46/sgoa, p47/sgo/sgoa selector output latch (p40 to p47) pm40 to pm47 internal bus
85 pd1615, pd16f15, pd1616 4.2.4 port 8 port 8 is an 8-bit input/output port with output latch. p80 to p87 pins can be specified as input mode/ output mode in 1-bit units with the port mode register 8 (pm8). dual-function includes the segment signal outputs of lcd controller driver. the dual-function can be selected with the port function register 8 (pf8). reset input sets port 8 to input mode. figure 4-5 shows a block diagram of port 8. figure 4-5: p80 to p87 configurations pm : port mode register rd : port 8 read signal wr : port 8 write signal note: the lcd controller/driver segment signal output is only valid on the pd1615 and the pd16f15. wr pm wr port rd p80/s39 to p87/s32 selector output latch (p80 to p87) pm80 to pm87 internal bus dual function
86 pd1615, pd16f15, pd1616 4.2.5 port 9 this is an 8-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with a port mode register 9. dual-function includes the segment signal outputs of lcd controller driver. the dual-function can be specified with the port function register 9 (pf9). reset input sets port 9 to input mode. figure 4-6 shows a block diagram of port 9. caution: when used as segment lines, set the port function pf9 according to its functions. figure 4-6: p90 to p97 configurations pm : port mode register rd : port 9 read signal wr : port 9 write signal note: the lcd controller/driver segment signal output is only valid on the pd1615 and the pd16f15. wr pm wr port rd p90/s31 to p97/s24 selector output latch (p90 to p97) pm90 to pm97 internal bus dual function
87 pd1615, pd16f15, pd1616 4.2.6 port 10 this is an 8-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with a port mode register 10. these pins are dual function pins and serve as segment signal output of lcd controller driver. the dual-function can be specified with the port function register 10 (pf10). reset input sets port 10 to input mode. figure 4-7 shows a block diagram of port 10. caution: when used as segment lines, set the port function pf9 according to its functions. figure 4-7: p100 to p107 configurations pm : port mode register rd : port 10 read signal wr : port 10 write signal note: the lcd controller/driver segment signal output is only valid on the pd1615 and the pd16f15. wr pm wr port rd p100/s23 to p107/s16 selector output latch (p100 to p107) pm100 to pm107 internal bus dual function
88 pd1615, pd16f15, pd1616 4.2.7 port 11 this is an 8-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with a port mode register 11. these pins are dual function pins and serve as segment signal output of lcd controller driver. the dual-function can be specified with the port function register 11 (pf11). reset input sets port 11 to input mode. figure 4-8 shows a block diagram of port 11. figure 4-8: p110 to p117 configurations pm : port mode register rd : port 11 read signal wr : port 11 write signal note: the lcd controller/driver segment signal output is only valid on the pd1615 and the pd16f15. wr pm wr port rd p110/s15 to p117/s8 selector output latch (p110 to p117) pm110 to pm117 internal bus dual function
89 pd1615, pd16f15, pd1616 4.2.8 port 12 this is an 8-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with a port mode register 12. these pins are dual function pins and serve as segment signal output of lcd controller driver. the dual-function can be specified with the port function register 12 (pf12). reset input sets port 12 to input mode. figure 4-9 shows a block diagram of port 12. figure 4-9: p120 to p127 configurations pm : port mode register rd : port 12 read signal wr : port 12 write signal note: the lcd controller/driver segment signal output is only valid on the pd1615 and the pd16f15. wr pm wr port rd p120/pcl//s7, p121/ti00/to0/s6, p122/ti01/s5, p123/rxd0/s4, p124/txd0/s3, p125/sck3/s2, p126/so3/s1, p127/si3/s0 selector output latch (p120 to p127) pm120 to pm127 internal bus dual function
90 pd1615, pd16f15, pd1616 4.3 port function control registers the following four types of registers control the ports. ? port mode registers (pm0, pm4, pm8 to pm12) ? port function registers (pfm : m = 8 to 12) (1) port mode registers (pm0, pm4, pm8 to pm12) these registers are used to set port input/output in 1-bit units. pm0, pm4, pm7, pm10 and pm12 are independently set with a 1-bit or 8-bit memory manipulation instruction. reset input sets registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch according to the function. cautions: 1. pins p10 to p13 are input-only pins. 2. as port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.
91 pd1615, pd16f15, pd1616 figure 4-10: port mode register format symbol76543210addressafter resetr/w pm0 pm07 pm06 1 1 1 pm02 pm01 pm00 ff20h ffh r/w pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 ff24h ffh r/w pm8 pm87 pm86 pm85 pm84 pm83 pm82 pm81 pm80 ff28h ffh r/w pm9 pm97 pm96 pm95 pm94 pm93 pm92 pm91 pm90 ff29h ffh r/w pm10 pm107 pm106 pm105 pm104 pm103 pm102 pm101 pm100 ff2ah ffh r/w pm11 pm117 pm116 pm115 pm114 pm113 pm112 pm111 pm110 ff2bh ffh r/w pm12 pm127 pm126 pm125 pm124 pm123 pm122 pm121 pm120 ff2ch ffh r/w pmmn pmmn pin input/output mode selection (m = 0 - 4, 8, 12; n = 0 C 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
92 pd1615, pd16f15, pd1616 3) port function register (pf8 to pf12) this register is used to set lcd segment function of ports 8 to 12. pf8 to pf12 are set with an 1-bit or 8-bit manipulation instruction. reset input set this registors to 00h. figure 4-11: port function register (pf8 to pf12) format caution: for pd1616 it is only allowed to set 00h to the port function register. pf8 pf87 pf86 pf85 pf84 pf83 pf82 pf81 pf80 ff58h 00h r/w pf9 pf97 pf96 pf95 pf94 pf93 pf92 pf91 pf90 ff59h 00h r/w pf10 pf107 pf106 pf105 pf104 pf103 pf102 pf101 pf100 ff5ah 00h r/w pf11 pf117 pf116 pf115 pf114 pf113 pf112 pf111 pf110 ff5bh 00h r/w pf12 pf127 pf126 pf125 pf124 pf123 pf122 pf121 pf120 ff5ch 00h r/w pmmn pfmn port function selection (m = 8 to 12; n = 0 to 7) 0 port function 1 lcd segment function
93 pd1615, pd16f15, pd1616 4.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 writing to input/output port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution: in the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 4.4.2 reading from input/output port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode t he pin status is read by a transfer instruction. the output latch contents do not change. 4.4.3 operations on input/output port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution: in the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
94 pd1615, pd16f15, pd1616 [memo]
95 pd1615, pd16f15, pd1616 chapter 5 clock generator 5.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are available. (1) main system clock oscillator this circuit oscillates at frequencies of 3.9 to 8.1 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register. (2) subsystem clock oscillator the circuit oscillates at a typical frequency of 40 khz. oscillation cannot be stopped.
96 pd1615, pd16f15, pd1616 5.2 clock generator configuration the clock generator consists of the following hardware. table 5-1: clock generator configuration figure 5-1: block diagram of clock generator item configuration control register processor clock control register (pcc) main system clock oscillator oscillator subsystem clock oscillator subsystem clock oscillator main system clock oscillator x2 x1 cl2 cl1 stop mcc cls css pcc2 pcc1 internal bus standby control circuit 2 f x 2 2 f x 2 3 f x 2 4 f x prescaler clock to peripheral hardware prescaler watch timer f x cpu clock (f cpu ) f x f xt processorclock controlregister 1/2 2 f xt pcc0 3 selector
97 pd1615, pd16f15, pd1616 5.3 clock generator control register the clock generator is controlled by the processor clock control register (pcc). (1) processor clock control register (pcc) the pcc selects a cpu clock and the division ratio, determines whether to make the main system clock oscillator operate or stop. the pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the pcc to 04h. figure 5-2: processor clock control register format notes: 1. bit 5 is a read-only bit. 2. when the cpu is operating on the subsystem clock, mcc should be used to stop the main system clock oscillation. a stop instruction should not be used. cautions: 1. bit 3 must be set to 0. 2. when external clock input is used mcc should not be set, because the x2 pin is connected to v dd via a resistor. remarks: 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. figures in parentheses indicate minimum instruction execution time: 2f cpu when oper- ating at f x = 8.0 mhz or f xt = 32.768 khz. symbol 7 6 5 4 3 2 1 0 address after reset r/w pcc mcc 0 cls css 0 pcc2 pcc1 pcc0 fffbh 04h r/w note 1 r/w css pcc2 pcc1 pcc0 cpu clock selection (f cpu ) 000f x (0.25 m s) 001f x /2 (0.5 m s) 0010f x /2 2 (1 m s) 011f x /2 3 (2 m s) 100f x /2 4 (4 m s) 000 001 1010f xt /2 (122 m s) 011 100 other than above setting prohibited r cls cpu clock status 0 main system clock 1 subsystem clock r/w mcc main system clock oscillation control 0 oscillation enable 1 oscillation stopped
98 pd1615, pd16f15, pd1616 5.4 system clock oscillator 5.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.0 mhz) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, the clock signal to the x1 pin and an inversed phase clock signal to the x2 pin. figure 6-3 shows an external circuit of the main system clock oscillator. figure 5-3: external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock caution: do not execute the stop instruction and do not set mcc [bit 7 of processor clock control register (pcc)] to 1 if an external clock is input. this is because when the stop instruction or mcc is set to 1, the main system clock operation stops and the x2 pin is connected to v dd 1 via a pull-up resistor. external clock x2 x1 pd74hcu04 x2 x1 ic crystal or ceramic resonator
99 pd1615, pd16f15, pd1616 5.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a rc-resonator (standard: 40khz) connected to the cl1 and cl2 pins. external clocks can be input to the subsystem clock oscillator. in this case, input a clock signal to the cl1 pin and open the cl2 pin. figure 5-4 shows an external circuit of the subsystem clock oscillator. figure 5-4: external circuit of subsystem clock oscillator (a) rc oscillation (b) external clock caution: when using a main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken-line area in figures 6-3 and 6-4 as follows to prevent any effects from wiring capacities. ? minimize the wiring length. ? do not allow wiring to intersect with other signal conductors. do not allow wiring to come near abruptly changing high current. ? set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground to any ground pattern where high current is present. ? do not fetch signals from the oscillator. take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that current consumption is maintained at low levels. figure 5-5 shows examples of oscillator having bad connection. external clock cl1 cl2 cl1 cl2 r c
100 pd1615, pd16f15, pd1616 figure 5-5: examples of oscillator with bad connection (1/3) (a) wiring of connection (b) a signal line crosses over circuits is too long oscillation circuit lines figure 5-5: examples of oscillator with bad connection (2/3) (c) changing high current is too near a (d) current flows through the grounding line signal conductor of the oscillator (potential at points a, b, and c fluctuate) ic x2 x1 x2 x1 portn (n = 0, 4, 8 to 12) ic ic x2 x1 high current ic x2 ab c pnm v dd high current x1
101 pd1615, pd16f15, pd1616 figure 5-5: examples of oscillator with bad connection (3/3) (e) signals are fetched (f) signal conductors of the main and sub- system clock are parallel and near each other caution: in figure 6-5 (f), cl1 and x1 are wired in parallel. thus, the cross-talk noise of x1 may increase with cl1, resulting in malfunctioning. to prevent that from occurring, it is recommended to wire cl1 and x1 so that they are not in parallel, and to connect the ic pin between cl1 and x1 directly to v ss . 5.4.3 when no subsystem clocks are used if it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the cl1 and cl2 pins as follows. cl1: connect to v dd or g nd cl2: open ic x2 x1 ic x2 x1 cl1 cl2 cl1 and cl2 are wiring in parallel
102 pd1615, pd16f15, pd1616 5.5 clock generator operations the clock generator generates the following various types of clocks and controls the cpu operating mode including the standby mode. ? main system clock f x ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the following clock generator functions and operations are determined with the processor clock control register (pcc). (a) upon generation of reset signal, the lowest speed mode of the main system clock (4 m s when operated at 8.0 mhz) is selected (pcc = 04h). main system clock oscillation stops while low level is applied to reset pin. (b) with the main system clock selected, one of the five cpu clock stages (f x , f x /2, f x /2 2 , f x /2 3 or f x /2 4 ) can be selected by setting the pcc. (c) with the main system clock selected, two standby modes, the stop and halt modes, are available. (d) the pcc can be used to select the subsystem clock and to operate the system with low current consumption (122 m s when operated at 32.768 khz). (e) with the subsystem clock selected, main system clock oscillation can be stopped with the pcc. the halt mode can be used. however, the stop mode cannot be used. (subsystem clock oscillation cannot be stopped.)
103 pd1615, pd16f15, pd1616 5.5.1 main system clock operations when operated with the main system clock (with bit 5 (cls) of the processor clock control register (pcc) set to 0), the following operations are carried out by pcc setting. (a) because the operation guarantee instruction execution speed depends on the power supply voltage, the instruction execution time can be changed by bits 0 to 2 (pcc0 to pcc2) of the pcc. (b) if bit 7 (mcc) of the pcc is set to 1 when operated with the main system clock, the main system clock oscillation does not stop. w hen bit 4 (css) of the pcc is set to 1 and the operation is switched to subsystem clock operation (cls = 1) after that, the main system clock oscillation stops (see figure 6-6). figure 5-6: main system clock stop function (1/2) (a) operation when mcc is set after setting css with main system clock operation (b) operation when mcc is set in case of main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock mcc css cls main system clock oscillation subsystem clock oscillation cpu clock l l oscillation does not stop.
104 pd1615, pd16f15, pd1616 figure 5-6: main system clock stop function (2/2) (c) operation when css is set after setting mcc with main system clock operation 5.5.2 subsystem clock operations when operated with the subsystem clock (with bit 5 (cls) of the processor clock control register (pcc) set to 1), the following operations are carried out. (a) the instruction execution time remains constant (122 m s when operated at 32.768 khz) irrespective of bits 0 to 2 (pcc0 to pcc2) of the pcc. (b) watchdog timer counting stops. caution: do not execute the stop instruction while the subsystem clock is in operation. mcc css cls main system clock oscillation subsystem clock oscillation cpu clock
105 pd1615, pd16f15, pd1616 5.6 changing system clock and cpu clock settings 5.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by means of bit 0 to bit 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc, but operation continues on the pre-switchover clock for several instructions (see table 5-2). determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 (cls) of the pcc register. table 5-2: maximum time required for cpu clock switchover caution: selection of the cpu clock cycle scaling factor (pcc0 to pcc2) and switchover from the main system clock to the subsystem clock (changing css from 0 to 1) should not be performed simultaneously. simultaneous setting is possible, however, for selec- tion of the cpu clock cycle scaling factor (pcc0 to pcc2) and switchover from the subsystem clock to the main system clock (changing css from 1 to 0). remarks: 1. one instruction is the minimum instruction execution time with the pre-switchover cpu clock. set values after switchover set values before switchover mcs css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 00000001001000110100 1xxx x 0 0 0 0 8 instructions 4 instructions 2 instructions 1 instruction 1 instruction 001 16 instructions 4 instructions 2 instructions 1 instruction 1 instruction 010 16 instructions 8 instructions 2 instructions 1 instruction 1 instruction 011 16 instructions 8 instructions 4 instructions 1 instruction 1 instruction 100 16 instructions 8 instructions 4 instructions 2 instructions 1 instruction 11 x x x f x /2f xt instruction f x /4f xt instruction f x /8f xt instruction f x /16f xt instruction f x /32f xt instruction (77 instructions) (39 instructions) (20 instructions) (10 instructions) (5 instructions) 0 f x /4f xt instruction f x /8f xt instruction f x /16f xt instruction f x /32f xt instruction f x /64f xt instruction (39 instructions) (20 instructions) (10 instructions) (5 instructions) (3 instructions)
106 pd1615, pd16f15, pd1616 5.6.2 system clock and cpu clock switching procedure this section describes switching procedure between system clock and cpu clock. figure 5-7: system clock and cpu clock switching (1) the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, main system clock starts oscillation. at this time, oscillation stabilization time (2 17 /f x ) is secured automatically. after that, the cpu starts executing the instruction at the minimum speed of the main system clock (4 m s when operated at 8.0 mhz). (2) after the lapse of a sufficient time for the v dd voltage to increase to enable operation at maximum speeds, the processor clock control register (pcc) is rewritten and the maximum-speed operation is carried out. (3) upon detection of a decrease of the v dd voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). (4) upon detection of v dd voltage reset due to an interrupt request signal, 0 is set to bit 7 (mcc) of pcc and oscillation of the main system clock is started. after the lapse of time required for stabilization of oscillation, the pcc is rewritten and the maximum-speed operation is resumed. caution: when subsystem clock is being operated while main system clock was stopped, if switching to the main system clock is made again, be sure to switch after securing oscillation stable time by software. v dd reset interrupt request signal systemclock cpuclock wait (16.3 ms: 8.0 mhz) internal reset operation minimum speed operation maximum speed operation subsystem clock operation f x f x f xt f x high-speed operation
107 pd1615, pd16f15, pd1616 [memo]
108 pd1615, pd16f15, pd1616 chapter 6 16-bit timer/ event counter 6.1 16-bit timer/event counter function 16-bit timer/event counter (tm0) has the following functions: ? interval timer ? ppg output ? pulse width measurement ? external event counter ? square wave output ? one-shot pulse output (1) interval timer when 16-bit timer/event counter is used as an interval timer, it generates an interrupt request at predetermined time intervals. (2) ppg output 16-bit timer/event counter can output a square wave whose frequency and output pulse width can be freely set. (3) pulse width measurement 16-bit timer/event counter can be used to measure the pulse width of a signal input from an external source. (4) external event counter 16-bit timer/event counter can be used to measure the number of pulses of a signal input from an external source. (5) square wave output 16-bit timer/event counter can output a square wave any frequency. (6) one-shot pulse output 16-bit timer/event counter can output a one-shot pulse with any output pulse width.
109 pd1615, pd16f15, pd1616 6.2 16-bit timer/event counter configuration 16-bit timer/event counter (tm0) consists of the following hardware: table 6-1: configuration of 16-bit timer/event counter (tm0) figure 6-1: block diagram of 16-bit timer/event counter (tm0) item configuration timer register 16 bits x 1 (tm0) register capture/compare register: 16 bits x 2 (cr00, cr01) timer output 1 (to0) 16-bit timer mode control register (tmc0) capture/compare register 0 (crc0) 16-bit timer output control register (toc0) prescaler mode register 0 (prm0) control register port mode register 12 (pm12) internal bus crc02 crc01 crc00 capture/compare control register 0 (crc0) p122/ ti01/ s5 p121/ ti00/ to0/ s6 noise rejection circuit 16-bit capture/compare register 00 (cr00) 16-bit timer register (tm0) 16-bit capture/compare register 01 (cr01) noise rejection circuit clear coincidence coincidence to0/p121/ti00/s6 inttm00 output control circuit inttm01 crc02 2 prescaler mode register 0 (prm0) timermode control register (tmc0) timer output control register (toc0) internal bus selector selector selector prm01 prm00 ovf0 tmc01 tmc02 tmc03 toe0 toc01 lvr0 lvs0 toc04 ospe ospt selector noise rejection circuit fx/2 1 fx/2 3 fx/2 6 fx/2
110 pd1615, pd16f15, pd1616 1) 16-bit timer register (tm0) tm0 is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of an input clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases: <1> reset is input. <2> tmc03 and tmc02 are cleared. <3> valid edge of ti00 is input in the clear & start mode by inputting valid edge of ti00. <4> tm0 and cr00 coincide with each other in the clear & start mode on coincidence between tm0 and cr00. <5> bit 6 of toc0 (ospt) is set or if the valid edge of ti00 is input in the one-shot pulse output mode.
111 pd1615, pd16f15, pd1616 2) capture/compare register 00 (cr00) cr00 is a 16-bit register that functions as a capture register and as a compare register. whether this register functions as a capture or compare register is specified by using bit 0 (crc00) of the capture/compare control register 0. ? when using cr00 as compare register the value set to cr00 is always compared with the count value of the 16-bit timer register (tm0). when the values of the two coincide, an interrupt request (inttm00) is generated. when tm00 is used as an interval timer, cr00 can also be used as a register that includes the interval time. ? when using cr00 as capture register the valid edge of the ti00 or ti01 pin can be selected as a capture trigger. the valid edge of ti00 and ti01 is performed via the prescaler mode register 0 (prm0). tables 6-2 and 6-3 show the conditions that apply when the capture trigger is specified as the valid edge of the ti00 pin and the valid edge of the ti01 pin respectively. table 6-2: valid edge of ti00 pin and valid edge of capture trigger of capture/compare register table 6-3: valid edge of ti01 pin and valid edge of capture trigger of capture/compare register cr00 is set by a 16-bit memory manipulation instruction. after reset input, the value of cr00 is undefined. caution: set a value other than 0000h in cr00. this means, that an 1-pulse count operation cannot be performed when cr00 is used as an event counter. es01 es00 valid edge of ti00 pin capture trigger of cr00 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation es01 es00 valid edge of ti01 pin capture trigger of cr00 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges
112 pd1615, pd16f15, pd1616 (3) capture/compare register 01 (cr01) this is a 16-bit register that can be used as a capture register and a compare register. whether it is used as a capture register or compare register is specified by bit 2 of the capture/compare control register 0 (crc0). ? when using cr01 as compare register the value set to cr01 is always compared with the count value of the 16-bit timer register (tm0). when the values of the two coincide, an interrupt request (inttm01) is generated. ? when using cr01 as capture register the valid edge of the ti00 pin can be selected as a capture trigger. the valid edge of ti00 is specified by using the prescaler mode register 0 (prm0). cr01 is set by a 16-bit memory manipulation instruction. after reset input, the value of cr00 is undefined. caution: set a value other than 0000h in cr01. this means, that an 1-pulse count operation cannot be performed when cr01 is used as an event counter.
113 pd1615, pd16f15, pd1616 6.3 16-bit timer/event counter control register the following four types of registers control 16-bit timer/event counter (tm0). ? 16-bit timer mode control register (tmc0) ? capture/compare control register (crc0) ? 16-bit timer output control register (toc0) ? prescaler mode register 0 (prm0) ? port mode register 12 (pm12) (1) 16-bit timer mode control register (tmc0) this register specifies the operation mode of the 16-bit timer and the clear mode, output timing, and overflow detection of the 16-bit timer register. tmc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc0 to 00h. caution: the 16-bit timer register starts operating when a value other than 0, 0 (operation stop mode) is set to tmc02 and tmc03. to stop the operation, set 0, 0 to tmc02 and tmc03.
114 pd1615, pd16f15, pd1616 figure 6-2: format of 16-bit timer mode control register (tmc0) address: ff60h after reset: 00h r/w symbol 76543210 tmc0 0000tmc03tmc02tmc01 ovf0 tmc03 tmc02 tmc01 000 001 010 011 100 101 110 111 0vf0 detection of overflow of 16-bit timer register 0 overflows. 1 does not overflow. operating mode clear mode and clear mode selection of to0 output timing generation of interrupt not affected coincidence between tm0 and cr00 or coincidence between tm0 and cr01 coincidence between tm0 and cr00, coincidence between tm0 and cr01, or valid edge of ti00 coincidence between tm0 and cr00 or coincidence between tm0 and cr01 coincidence between tm0 and cr00, coincidence between tm0 and cr01, or valid edge of ti00 coincidence between tm0 and cr00 or coincidence between tm0 and cr01 coincidence between tm0 and cr00, coincidence between tm0 and cr01, or valid edge of ti00 does not generate. free running mode clears and starts at valid edge of ti00. clears and starts on coincidence between tm0 and cr00. generates on coincidence between tm0 and cr00 and coincidence between tm0 and cr01. operation stop (tm0 is cleared to 0).
115 pd1615, pd16f15, pd1616 cautions 1. before changing the clear mode and to0 output timing, be sure to stop the timer operation (reset tmc02 and tmc03 to 0, 0). 2. the valid edge of the ti00 pin is selected by using the prescaler mode register 0 (prm0). 3. when a mode in which the timer is cleared and started on coincidence between tm0 and cr00, the ovf0 flag is set to 1 when the count value of tm0 changes from ffffh to 0000h with cr00 set to ffffh. remark: t00 : output pin of 16-bit timer/counter (tm0) ti00 : input pin of 16-bit timer/counter (tm0) tm0 : 16-bit timer register cr00 : compare register 00 cr01 : compare register 01
116 pd1615, pd16f15, pd1616 (2) capture/compare control register 0 (crc0) this register controls the operation of the capture/compare registers (cr00 and cr01). crc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets crc0 to 00h. figure 6-3: format of capture/compare control register 0 (crc0) address: ff62h after reset: 00h r/w symbol 76543210 crc0 00000 crc02 crc01 crc00 crc02 selection of operation mode of cr01 0 operates as compare register 1 operates as capture register crc01 selection of capture trigger of cr00 0 captured at valid edge of ti01 1 captured in reverse phase of valid edge of ti00 crc00 selection of operation mode of cr00 0 operates as compare register 1 operates as capture register cautions: 1. before setting crc0, be sure to stop the timer operation. 2. when the mode in which the timer is cleared and started on coincidence between tm0 and cr00 is selected by the 16-bit timer mode control register (tmc0), do not specify cr00 as a capture register. 3. if valid edge of ti00 is both falling and rising, the capture operation is not available when crc01 = 1.
117 pd1615, pd16f15, pd1616 figure 6-4: format of 16-bit timer output control register (toc0) address: ff63h after reset: 00h r/w symbol 76543210 toc0 0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 ospt output trigger control of one-shot pulse by software 0 no one-shot pulse trigger 1 uses one-shot pulse trigger ospe controls of one-shot pulse output operation 0 continuous pulse output 1 one-shot pulse output toc04 timer output f/f control on coincidence between cr01 and tm0 0 disables inversion timer output 1 enables inversion timer output lvs0 lvr0 set status of timer output f/f of 16-bit timer/counter (tm0) 0 0 not affected 0 1 resets timer output f/f (0) 1 0 sets timer output f/f (1) 1 1 setting prohibited toc01 timer output f/f control on coincidence between cr00 and tm0 0 disables inversion timer output f/f 1 enables inversion timer output f/f toe0 output control of 16-bit timer/counter (tm0) 0 disables output (port mode) 1 enables output cautions: 1. before setting toc0, be sure to stop the timer operation. 2. lvs0 and lvr0 are 0 when read after data have been set to them. 3. ospt is 0 when read because it is automatically cleared after data has been set. (3) 16-bit timer output control register (toc0) this register controls the operation of the 16-bit timer/event counter (tm0) output control circuit by setting or resetting the r-s flip-flop, enabling or disabling reverse output, enabling or disabling output of 16-bit timer/counter (tm0), enabling or disabling one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software. toc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets toc0 to 00h. figure 6-4 shows the format of toc0.
118 pd1615, pd16f15, pd1616 (4) prescaler mode register 0 (prm0) this register selects a count clock of the 16-bit timer/event counter (tm0) and the valid edge of ti00, ti01 input. prm0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets prm0 to 00h. figure 6-5: format of prescaler mode register 0 (prm0) address: ff61h after reset : 00h r/w symbol 76543210 prm0 es11 es10 es01 es00 0 0 prm01 prm00 es11 es10 selection of valid edge of ti01 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es01 es00 selection of valid edge of ti00 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm01 prm00 selection of count clock 00f x /2 1 (4.00 mhz) 01f x /2 3 (1.00 mhz) 10f x /2 6 (125 khz) 1 1 valid edge of ti00 caution: when selecting the valid edge of ti00 as the count clock, do not specify the valid edge of ti00 to clear and start the timer and as a capture trigger. remark: figures in parentheses apply to operation with f x = 8.00 mhz.
119 pd1615, pd16f15, pd1616 (5) port mode register 12 (pm12) this register sets port 12 input/output in 1-bit units. when using the p121/to0/ti00/s6 pin for timer output, set pm121 and the output latch of p121 to 0. pm12 is set with an 1-bit or 8-bit memory manipulation instruction. reset input sets pm12 value to ffh. figure 6-6: port mode register 12 (pm12) format symbol76543210addressafter resetr/w pm12 pm127 pm126 pm125 pm124 pm123 pm122 pm121 pm120 ff2ch ffh r/w pm12n p12n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) (6) port function register 12 (pm12) this register sets the port function of port 12 in 1-bit units. when using the timer for timer output or timer input, the register pf12 has to be set to port function. pm12 is set with an 1-bit or 8-bit memory manipulation instruction. reset input sets pm12 value to 00h. figure 6-7: port function register 12 (pm12) format symbol76543210addressafter resetr/w pf12 pf127 pf126 pf125 pf124 pf123 pf122 pf121 pf120 ff5ch 00h r/w pf12n p12n function selection (n = 0 to 7) 0 port mode 1 lcd mode note: for the pd1616 set always 00h to pf12.
120 pd1615, pd16f15, pd1616 6.4 16-bit timer/event counter operations 6.4.1 operation as interval timer (16 bits) the 16-bit timer/event counter operates as an interval timer when the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) are set as shown in figure 6-8. in this case, 16-bit timer/event counter repeatedly generates an interrupt at the time interval specified by the count value set in advance to the 16-bit capture/compare register 00 (cr00). when the count value of the 16-bit timer register (tm0) coincides with the set value of cr00, the value of tm0 is cleared to 0, and the timer continues counting. at the same time, an interrupt request signal (inttm00) is generated. the count clock of the 16-bit timer/event counter can be selected by bits 0 and 1 (prm00 and prm01) of the prescaler mode register 0 (prm0). figure 6-8: control register settings when timer 0 operates as interval timer (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the interval timer function. for details, refer to figures 6-2 and 6-3. 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00. 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register
121 pd1615, pd16f15, pd1616 figure 6-9: configuration of interval timer figure 6-10: timing of interval timer operation remark: interval time = (n+1) x t: n = 0000h to ffffh fx/2 1 fx/2 3 fx/2 6 ti01 selector 16-bit capture/compare register 00 (cr00) 16-bit timer register (tm0) ovf0 clear circuit inttm00 count starts clear clear interrupt accepted interrupt accepted t 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n interval time interval time interval time count clock tm0 count value cr00 inttm00
122 pd1615, pd16f15, pd1616 6.4.2 ppg output operation the 16-bit timer/counter can be used for ppg (programmable pulse generator) output by setting the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 6-11. the ppg output function outputs a rectangular wave with a cycle specified by the count value set in advance to the 16-bit capture/compare register 00 (cr00) and a pulse width specified by the count value set in advance to the 16-bit capture/compare register 01 (cr01). figure 6-11: control register settings in ppg output operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark: x : dont care on : can be used for other functions caution: make sure that 0000h cr01 < cr00 ffffh is set to cr00 and cr01. 0000 tmc03 1 tmc02 1 tmc01 0 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00. 00000 crc02 0 crc01 crc00 0 crc0 cr00 as compare register cr01 as compare register x 0 ospt 0 ospe 0 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output reverses output on coincidence between tm0 and cr01 disables one-shot pulse output specifies initial value of to0 output f/f reverses output on coincidence between tm0 and cr00
123 pd1615, pd16f15, pd1616 6.4.3 pulse width measurement the 16-bit timer register (tm0) can be used to measure the pulse widths of the signals input to the ti00 and ti01 pins. measurement can be carried out with tm0 used as a free running counter or by restarting the timer in synchronization with the edge of the signal input to the ti00 pin. (1) pulse width measurement with free running counter and one capture register if the edge specified by the prescaler mode register 0 (prm0) is input to the ti00 pin when the 16- bit timer register (tm0) is used as a free running counter (refer to figure 6-12), the value of tm0 is loaded to the 16-bit capture/compare register 01 (cr01), and an external interrupt request signal (inttm01) is set. the edge is specified by using bits 6 and 7 (es10 and es11) of the prescaler mode register 0 (prm0). the rising edge, falling edge, or both the rising and falling edges can be selected. the valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register 0n (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be rejected. figure 6-12: control register settings for pulse width measurement with free running counter and one capture register (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 6-2 and 6-3. 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free running mode 00000 crc02 1 crc01 0/1 crc00 0 crc0 cr00 as compare register cr01 as capture register
124 pd1615, pd16f15, pd1616 figure 6-13: configuration for pulse width measurement with free running counter figure 6-14: timing of pulse width measurement with free running counter and one capture register (with both edges specified) inttm00 fx/2 1 fx/2 3 fx/2 6 selector 16-bit capture/compare register 01 (cr01) 16-bit timer register (tm0) ovf0 ti00 internal bus t (d1 - d0) x t (10000h - d1 + d2) x t (d3 - d2) x t count clock 0000h 0001h d0 d1 0000h d2 d3 tm0 count value d3 ti00 pin input value loaded to cr01 inttm00 ovf0 d0 d1 d2 ffffh
125 pd1615, pd16f15, pd1616 (2) measurement of two pulse widths with free running counter the pulse widths of the two signals respectively input to the ti00 and ti01 pins can be measured when the 16-bit timer register (tm0) is used as a free running counter (refer to figure 6-14). when the edge specified by bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0) is input to the ti00 pin, the value of the tm0 is loaded to the 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (inttm01) is set. when the edge specified by bits 6 and 7 (es10 and es11) of the prescaler mode register 0 (prm0) is input to the ti01 pin, the value of tm0 is loaded to the 16-bit capture/compare register 00 (cr00), and an external interrupt request signal (inttm00) is set. the edges of the ti00 and ti01 pins are specified by bits 4 and 5 (es00 and es01) and bits 6 and 7 (es10 and es11) of prm0, respectively. the rising, falling, or both rising and falling edges can be specified. the valid edge of ti00 pin and ti01 pin is detected through sampling at a count clock cycle selected by the prescaler mode register 0 (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be rejected. fig u re 6-15: control register settings for measurement of two pulse widths with free running counter (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 6-2 and 6-3. 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free running mode 00000 crc02 1 crc01 0 crc00 1 crc0 cr00 as capture register captures valid edge of ti01 pin to cr00. cr01 as capture register
126 pd1615, pd16f15, pd1616 ? capture operation (free running mode) the following figure illustrates the operation of the capture register when the capture trigger is input. figure 6-16: cr01 capture operation with rising edge specified figure 6-17: timing of pulse width measurement with free running counter (with both edges specified) note: d2 + 1 t (d1 - d0) x t (10000h - d1 + d2) x t count clock 0000h 0001h d0 d1 ffffh 0000h d2 d3 tm0 count value d0 d1 d2 d3 ti00 pin input value loaded to cr01 inttm01 ovf0 d1 (10000h - d1 + (d2+1)) x t (d3 - d2) x t ti01 pin input value loaded to cr00 inttm00 note count clock tm0 ti00 rising edge detection cr01 inttm01 n-3 n-2 n-1 n n+1 n
127 pd1615, pd16f15, pd1616 (3) pulse width measurement with free running counter and two capture registers when the 16-bit timer register (tm0) is used as a free running counter (refer to figure 6-17), the pulse width of the signal input to the ti00 pin can be measured. when the edge specified by bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0) is input to the ti00 pin, the value of tm0 is loaded to the 16-bit capture/compare register 01 (cr01), and an external interrupt request signal (inttm01) is set. the value of tm0 is also loaded to the 16-bit capture/compare register 00 (cr00) when an edge reverse to the one that triggers capturing to cr01 is input. the edge of the ti00 pin is specified by bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0). the rising or falling edge can be specified. the valid edge of ti00 pin and ti01 pin is detected through sampling at a count clock cycle selected by the prescaler mode register 0 (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be rejected. caution: if the valid edge of the ti00 pin is specified to be both the rising and falling edges, the capture/compare register 00 (cr00) cannot perform its capture operation. figure 6-18: control register settings for pulse width measurement with free running counter and two capture registers (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 6-2 and 6-3. 0000 tmc03 0 tmc02 1 tmc01 0/1 ovf0 0 tmc0 free running mode 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 as capture register captures to cr00 at edge reverse to valid edge o f ti00 pin. cr01 as capture register
128 pd1615, pd16f15, pd1616 figure 6-19: timing of pulse width measurement with free running counter and two capture registers (with rising edge specified) t (d1 - d0) x t (10000h - d1 + d2) x t count clock 0000h 0001h d0 d1 ffffh 0000h d2 d3 tm0 count value d0 d2 d3 ti00 pin input value loaded to cr01 value loaded to cr00 d1 (d3 - d2) x t inttm01 ovf0
129 pd1615, pd16f15, pd1616 (4) pulse width measurement by restarting when the valid edge of the ti00 pin is detected, the pulse width of the signal input to the ti00n pin can be measured by clearing the 16-bit timer register (tm0) once and then resuming counting after loading the count value of tm0 to the 16-bit capture/compare register 01 (cr01). the edge of the ti00 pin is specified by bits 4 and 5 (es00 and es01) of prm0. the rising or falling edge can be specified. the valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register 0 (prm0), and the capture operation is not performed until the valid level is detected two times. therefore, noise with a short pulse width can be rejected. caution: if the valid edge of the ti00 pin is specified to be both the rising and falling edges, the capture/compare register 00 (cr00) cannot perform its capture operation. figure 6-20: control register settings for pulse width measurement by restarting (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the pulse width measurement function. for details, refer to figures 6-2 and 6-3. 0000 tmc03 1 tmc02 0 tmc01 0/1 ovf0 0 tmc0 clears and starts at valid edge of ti00 pin. 00000 crc02 1 crc01 1 crc00 1 crc0 ncr00 as capture register captures to cr00 at edge reverse to valid edge of ti00. cr01 as capture register
130 pd1615, pd16f15, pd1616 figure 6-21: timing of pulse width measurement by restarting (with rising edge specified) 6.4.4 operation as external event counter 16-bit timer/event counter can be used as an external event counter which counts the number of clock pulses input to the ti00 pin from an external source by using the 16-bit timer register (tm0). each time the valid edge specified by the prescaler mode register 0 (prm0) has been input to the ti00 pin, tm0 is incremented. when the count value of tm0 coincides with the value of the 16-bit capture/compare register 00 (cr00), tm0 is cleared to 0, and an interrupt request signal (inttm00) is generated. the edge of the ti00 pin is specified by bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0). the rising, falling, or both the rising and falling edges can be specified. the valid edge is detected through sampling at a count clock cycle, selected by the prescaler mode register 0 (prm0) and performed until the valid level is detected two times. therefore, noise with a short pulse width can be rejected. t d1 x 1 d2 x 1 count clock 0000h 0001h d0 d1 0000h 0001h d2 0001h tm0 count value d0 d2 ti00 pin input value loaded to cr01 value loaded to cr00 d1 inttm01 0000h
131 pd1615, pd16f15, pd1616 figure 6-22: control register settings in external event counter mode (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) figure 6-23: configuration of external event counter remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the external event counter function. for details, refer to figures 6-2 and 6-3. 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register 16-bit capture/compare register (cr00) 16-bit timer register (tm0) clear ovf0 inttm00 16-bit capture/compare register 01 (cr01) valid edge of ti00 internal bus noise elimination circuit selector fx/2 fx/2 1 fx/2 3 fx/2 6
132 pd1615, pd16f15, pd1616 figure 6-24: timing of external event counter operation (with rising edge specified) caution: read tm0 when reading the count value of the external event counter. 6.4.5 operation to output square wave the 16-bit timer/event counter can be used to output a square wave with any frequency at an interval specified by the count value set in advance to the 16-bit capture/compare register 00 (cr00). by setting bits 0 (toe0) and 1 (toc01) of the 16-bit timer output control register to 1, the output status of the to0 pin is reversed at an interval specified by the count value set in advance to cr00. in this way, a square wave of any frequency can be output. ti00 pin input 0000h 0001h 0003h 0005h n - 1 0001h 0003h tm0 count value n cr00 inttm00 0002h 0004h 0000h 0002h n
133 pd1615, pd16f15, pd1616 figure 6-25: set contents of control registers in square wave output mode (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the square wave output function. for details, refer to figures 6-2, 6-3, and 6-4. figure 6-26: timing of square wave output operation 0000 tmc03 1 tmc02 1 tmc01 0/1 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00. 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 as compare register 0 ospt 0 ospe 0 toc04 0 lvs0 0/1 lv r 0 0/1 toc01 1 toe0 1 toc0 enables to0 output disables one-shot pulse output does not reverse output on coincidence between tm0 and cr01 specifies initial value of to0 output f/f reverses output on coincidence between tm0 and cr00 0000h 0001h n - 1 n 0001h 0002h n - 1 n n count clock tm0 count value cr00 0000h 0000h 0002h inttm00 to0 pin output
134 pd1615, pd16f15, pd1616 6.4.6 operation to output one-shot pulse 16-bit timer/event counter can output a one-shot pulse in synchronization with a software trigger and an external trigger (ti00/to0 pin input). (1) one-shot pulse output with software trigger a one-shot pulse can be output from the to0 pin by setting the 16-bit timer mode control register (tmc0) and by setting bit 6 (ospt) of toc0 by software. by setting ospt to 1, the 16-bit timer/event counter is cleared and started, and its output is asserted active at the count value set in advance to the 16-bit capture/compare register 01 (cr01). after that, the output is deasserted inactive at the count value set in advance to the 16-bit capture/compare register 00 (cr00). even after the one-shot pulse has been output, tm0 continues its operation. to stop tm0, tmc0 must be reset to 00h. caution: do not set ospt to 1 while the one-shot pulse is being output. to output the one- shot pulse again, wait until inttm00, which occurs on coincidence between tm0 and cr00, occurs.
135 pd1615, pd16f15, pd1616 figure 6-27: control register settings for one-shot pulse output with software trigger (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the one-shot pulse output function. for details, refer to figures 6-2, 6-3, and 6-4. caution: set a value in the following range to cr00 and cr01. 0000h - cr01 < cr00 - ffffh 0000 tmc03 1 tmc02 1 tmc01 0 ovf0 0 tmc0 clears and starts on coincidence between tm0 and cr00 00000 crc02 0 crc01 0/1 crc00 0 crc0 cr00 as compare register cr01 as compare register 0 ospt 0 ospe 1 toc04 1 lv s 0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output sets one-shot pulse output mode set to 1 for output specifies initial value of to0 output f/f reverses output on coincidence between tm0 and cr01 reverses output on coincidence between tm0 and cr00
136 pd1615, pd16f15, pd1616 figure 6-28: timing of one-shot pulse output operation with software trigger caution: the 16-bit timer register starts operating as soon as a value other than 0, 0 (operation stop mode) has been set to tmc02 and tmc03. (2) one-shot pulse output with external trigger a one-shot pulse can be output from the to0/ti00 pin by setting the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and 16-bit timer output control register (toc0) as shown in figure 6-28, and by using the valid edge of the to0/ti00 pin as an external trigger. the valid edge of the ti00 pin is specified by bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti00 pin is detected, the 16-bit timer/event counter is cleared and started, and the output is asserted active at the count value set in advance to the 16-bit capture/compare register 01 (cr01). after that, the output is deasserted inactive at the count value set in advance to the 16-bit capture/compare register 00 (cr00). caution: even if the external trigger is generated again while the one-shot pulse is output, it is ignored. sets 0ch to tmc0 (tm0 count starts) count clock 0000h 0001h 0000h tm0 count value m n cr01 set value cr00 set value ospt inttm01 inttm00 to0 pin output n + 1 m - 1 0000h 0001h 0002h m n m n m n nn n - 1 m
137 pd1615, pd16f15, pd1616 figure 6-29: control register settings for one-shot pulse output with external trigger (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) caution: set a value in the following range to cr00 and cr01. 0000h cr01 < cr00 ffffh remark: 0/1: when these bits are reset to 0 or set to 1, the other functions can be used along with the one-shot pulse output function. for details, refer to figures 6-2, 6-3, and 6-4. 0000 tmc03 1 tmc02 0 tmc01 0 ovf0 0 tmc0 clears and starts at valid edge of ti00/to0 pin 00000 crc02 0 crc01 0/1 crc00 0 crc0 cr00 as compare register cr01 as compare register 0 ospt 0 ospe 1 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output set one-shot pulse output mode specifies initial value of to0 output f/f reverses output on coincidence between tm0 and cr00 reverses output on coincidence between tm0 and cr01
138 pd1615, pd16f15, pd1616 figure 6-30: timing of one-shot pulse output operation with external trigger (with rising edge specified) caution: the 16-bit timer register starts operating as soon as a value other than 0, 0 (operation stop mode) has been set to tmc02 and tmc03. sets 08h to tmc0 (tm0 count starts) count clock 0000 0001 0000 tm0 count value m n cr01 set value cr00 set value ti00 pin input inttm01 inttm00 to0 pin output n+1 n+2 m-1 m m n m n m n n m-2 m+1 m+2 m+3
139 pd1615, pd16f15, pd1616 6.5 16-bit timer/event counter operating precautions (1) error on starting timer an error of up to 1 clock occurs before the coincidence signal is generated after the timer has been started. this is because the 16-bit timer register (tm0) is started asynchronously in respect to the count pulse. figure 6-31: start timing of 16-bit timer register remark: n > x > m (2) 16-bit compare register setting set another value than 0000h to the 16-bit captured compare register cr00, cr01. this means, that a 1-pulse count operation cannot be performed, when it is used as event counter. (3) setting compare register during timer count operation if the value to which the current value of the 16-bit capture/compare register 00 (cr00) has been changed is less than the value of the 16-bit timer register (tm0), tm0 continues counting, overflows, and starts counting again from 0. if the new value of cr00 (m) is less than the old value (n), the timer must be restarted after the value of cr00 has been changed. figure 6-32: timing after changing compare register during timer count operation tm0 count value 0000h 0001h 0002h 0004h count pulses timer starts 0003h cr00 nm count pulse tm0 count x - 1 x ffffh 0000h 0001h 0002h
140 pd1615, pd16f15, pd1616 (4) data hold timing of capture register if the valid edge is input to the ti00 pin while the 16-bit capture/compare register 01 (cr01) is read, cr01 performs the capture operation, but this capture value is not guaranteed. however, the interrupt request flag (inttm01) is set as a result of detection of the valid edge. figure 6-33: data hold timing of capture register (5) setting valid edge before setting the valid edge of the ti00 pin, stop the timer operation by resetting bits 2 and 3 (tmc02 and tmc03) of the 16-bit timer mode control register to 0, 0. set the valid edge by using bits 4 and 5 (es00 and es01) of the prescaler mode register 0 (prm0). (6) re-triggering one-shot pulse (a) one-shot pulse output by software when a one-shot pulse is output, do not set ospt to 1. do not output the one-shot pulse again until inttm00, which occurs on coincidence between tm0 and cr00, occurs. (b) one-shot pulse output with external trigger if the external trigger occurs while a one-shot pulse is output, it is ignored. tm0 count n n+1 n+2 m m+1 m+2 n+1 x count pulse edge input interrupt request flag capture read signal cr01 interrupt value capture
141 pd1615, pd16f15, pd1616 7) operation of ovf0 flag the ovf0 flag is set to 1 in the following case: select mode in which 16-bit timer/counter is cleared and started on coincidence between tm0 and cr00. set cr00 to ffffh when tm0 counts up from ffffh to 0000h figure 6-34: operation timing of ovf0 flag (8) contending operations (a) the contending operation between the read time of 16-bit capture/compare register (cr00/ cr01) and capture trigger input (cr00/cr01 used as capture register) capture/trigger input is prior to the other. the data read from cr00/cr01 is not defined. (b) the coincidence timing of contending operation between the write period of 16-bit capture/ compare register (cr00/cr01) and 16-bit timer register (tm0) (cr00/cr01 used as a compare register) the coincidence discriminant is not performed normally. do not write any data to cr00/cr01 near the coincidence timing. ffffh fffeh ffffh 0000h 0001h count pulse cr00 tm0 ovf0 inttm00
142 pd1615, pd16f15, pd1616 [memo]
143 pd1615, pd16f15, pd1616 chapter 7 8-bit timer/event counters 50 and 51 7.1 8-bit timer/event counters 50 and 51 functions the 8-bit timer event counters 50 and 51 (tm50, tm51) have the following functions. ? interval timer ? external event counter ? square-wave output ? pwm output
144 pd1615, pd16f15, pd1616 (1) 8-bit interval timer interrupts are generated at the preset time intervals. table 7-1: 8-bit timer/event counter 50 interval times table 7-2: 8-bit timer/event counter 51 interval times remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. minimum interval width maximum interval width resolution 2 1 x 1/f x (250 ns) 2 9 x 1/f x (64 s) 2 1 x 1/f x (250 ns) 2 3 x 1/f x (1 s) 2 11 x 1/f x (256 s) 2 3 x 1/f x (1 s) 2 5 x 1/f x (4 s) 2 13 x 1/f x (1 ms) 2 5 x 1/f x (4 s) 2 7 x 1/f x (16 s) 2 15 x 1/f x (4 ms) 2 7 x 1/f x (16 s) 2 8 x 1/f x (32 s) 2 16 x 1/f x (8 ms) 2 8 x 1/f x (32 s) 2 11 x 1/f x (256 s) 2 19 x 1/f x (65 ms) 2 11 x 1/f x (256 s) minimum interval width maximum interval width resolution 1/f x (125 ns) 2 8 x 1/f x (32 s) 1/f x (125 ns) 2 4 x 1/f x (2 s) 2 12 x 1/f x (512 s) 2 4 x 1/f x (2 s) 2 6 x 1/f x (8 s) 2 14 x 1/f x (2 ms) 2 6 x 1/f x (8 s) 2 7 x 1/f x (16 s) 2 15 x 1/f x (4 ms) 2 7 x 1/f x (16 s) 2 8 x 1/f x (32 s) 2 16 x 1/f x (8 ms) 2 8 x 1/f x (32 s) 2 10 x 1/f x (128 s) 2 18 x 1/f x (32 ms) 2 10 x 1/f x (128 s)
145 pd1615, pd16f15, pd1616 (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. table 7-3: 8-bit timer/event counter 50 square-wave output ranges remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. (4) pwm output tm50 and tm51 can generate an 8-bit resolution pwm output. table 7-4: 8-bit timer/event counter 50 square-wave output ranges minimum pulse width maximum pulse width resolution 2 1 x 1/f x (250 ns) 2 9 x 1/f x (64 s) 2 1 x 1/f x (250 ns) 2 3 x 1/f x (1 s) 2 11 x 1/f x (256 s) 2 3 x 1/f x (1 s) 2 5 x 1/f x (4 s) 2 13 x 1/f x (1 ms) 2 5 x 1/f x (4 s) 2 7 x 1/f x (16 s) 2 15 x 1/f x (4 ms) 2 7 x 1/f x (16 s) 2 8 x 1/f x (32 s) 2 16 x 1/f x (8 ms) 2 8 x 1/f x (32 s) 2 11 x 1/f x (256 s) 2 19 x 1/f x (65 ms) 2 11 x 1/f x (256 s) minimum pulse width maximum pulse width resolution 1/f x (125 ns) 2 8 x 1/f x (32 s) 1/f x (125 ns) 2 4 x 1/f x (2 s) 2 9 x 1/f x (512 s) 2 1 x 1/f x (2 s) 2 6 x 1/f x (8 s) 2 11 x 1/f x (2 ms) 2 3 x 1/f x (8 s) 2 7 x 1/f x (16 s) 2 13 x 1/f x (4 ms) 2 5 x 1/f x (16 s) 2 8 x 1/f x (32 s) 2 15 x 1/f x (8 ms) 2 7 x 1/f x (32 s) 2 10 x 1/f x (128 s) 2 20 x 1/f x (32 ms) 2 12 x 1/f x (128 s)
146 pd1615, pd16f15, pd1616 7.2 8-bit timer/event counters 50 and 51 configurations the 8-bit timer/event counters 50 and 51 consist of the following hardware. table 7-5: 8-bit timer/event counters 50 and 51 configurations figure 7-1: 8-bit timer/event counter 50 block diagram note: refer to figure 7-2 for details of configurations of 8-bit timer/event counters 50 and 51 output control circuits. item configuration timer register 8 bits x 2 (tm50, tm51) register compare register 8 bits x 2 (cr50, cr51) timer output 2 (to50, to51) timer clock select register 50 and 51 (tcl50, tcl51) 8-bit timer mode control registers 5 and 6 (tmc50, tmc51) control register port mode registers 0 (pm0) ti50/p06/to50 internal bus 8-bit compare register (cr50) match 8-bit timer register n (tm50) 4 selector 2 clear 6 ovf internal bus tcl 502 tcl 501 tcl 500 timer clock select register 50 output control note 8-bit timer mode control register 50 inttm50 tce 50 lvs 50 lvr 50 tmc 501 toe 50 tmc 506 selector fx/2 1 fx/2 3 fx/2 5 fx/2 7 fx/2 8 fx/2 11 to50/p06/ti50
147 pd1615, pd16f15, pd1616 figure 7-2: 8-bit timer/event counter 51 block diagram note: refer to figure 7-3 for details of configurations of 8-bit timer/event counters 50 and 51 output control circuits. ti51/p07/to51 internal bus 8-bit compare register (cr51) match 8-bit timer register n (tm51) 4 selector 2 clear 6 ovf internal bus tcl 512 tcl 511 tcl 510 timer clock select register 51 output control note 8-bit timer mode control register 51 inttm51 tmc 51 lvs 51 lvr 51 tmc 511 toe 51 tce 516 selector fx fx/2 4 fx/2 6 fx/2 7 fx/2 8 fx/2 10 to51/p07/ti51
148 pd1615, pd16f15, pd1616 figure 7-3: block diagram of 8-bit timer/event counters 50 and 51 output control circuit remarks: 1. the section in the line is an output control circuit. 2. n = 50, 51 (1) compare register 50 and 51 (cr50, 51) these 8-bit registers compare the value set to cr50 to 8-bit timer register 5 (tm50) count value, and the value set to cr51 to the 8-bit timer register 51 (tm51) count value, and, if they match, generate interrupts request (inttm50 and inttm51, respectively). cr50 and cr51 are set with an 8-bit memory manipulation instruction. they cannot be set with a 16-bit memory manipulation instruction. the 00h to ffh values can be set. reset input sets cr50 and cr51 values to 00h. caution: to use pwm mode, set crn value before setting tmcn (n = 50, 51) to pwm mode. (2) 8-bit timer registers 50 and 51 (tm50, tm51) these 8-bit registers count count pulses. tm50 and tm51 are read with an 8-bit memory manipulation instruction. reset input sets tm50 and tm51 to 00h. reset lvrn lvsn tmcn1 tmcn6 ovfn inttmn tcen inttmn r s q pwm output circuit timer output f/f2 level f/f r s inv q tmcn1 tmcn6 selector p06, p07 output latch pm06, pm07 to50/p06/ti50, to51/p07/ti51 toen
149 pd1615, pd16f15, pd1616 note: when clock is input from the external, timer output (pwm output) cannot be used. caution: when rewriting tcl50 to other data, stop the timer operation beforehand. remarks: 1. f x : main system clock oscillation frequency 2. ti50: 8-bit timer register 50 input pin 3. values in parentheses apply to operation with f x = 8.0 mhz 7.3 8-bit timer/event counters 50 and 51 control registers the following three types of registers are used to control the 8-bit timer/event counters 50 and 51. ? timer clock select register 50 and 51 (tcl50, tcl51) ? 8-bit timer mode control registers 50 and 51 (tmc50, tmc51) ? port mode register 0 (pm0) (1) timer clock select register 50 (tcl50) this register sets count clocks of 8-bit timer register 50. tcl50 is set with an 8-bit memory manipulation instruction. reset input sets tcl50 to 00h. figure 7-4: timer clock select register 50 format 00000 tcl502 tcl501tcl500 76543210 symbol tcl50 tcl502 tcl501tcl500 0 0 0 ti50 falling edge 0 0 1 ti50 rising edge 010 011 f x /2 (1.0 mhz) 100 f x /2 5 (250 khz) 101 f x /2 7 (62.5 khz) 110 f x /2 8 (31.25 khz) 111 f x /2 11 (3.9 khz) 8-bit timer register 50 count clock selection other than above setting prohibited ff71h 00h r/w address after reset r/w note note 3 f x /2 (4.0 mhz) 1
150 pd1615, pd16f15, pd1616 note: when clock is input from the external, timer output (pwm output) cannot be used. caution: when rewriting tcl51 to other data, stop the timer operation beforehand. remarks: 1. f x : main system clock oscillation frequency 2. ti51: 8-bit timer register 51 input pin 3. values in parentheses apply to operation with f x = 8.0 mhz (2) timer clock select register 51 (tcl51) this register sets count clocks of 8-bit timer register 51. tcl51 is set with an 8-bit memory manipulation instruction. reset input sets tcl51 to 00h. figure 7-5: timer clock select register 51 format 00000 tcl512 tcl511tcl510 76543210 symbol tcl51 tcl512 tcl511tcl510 0 0 0 ti51 falling edge 0 0 1 ti51 rising edge 010 f x 011 f x /2 (500 khz) 100 f x /2 6 (125 khz) 101 f x /2 7 (62.5 khz) 110 f x /2 8 (31.25 khz) 111 f x /2 10 (7.8 khz) 8-bit timer register 51 count clock selection other than above setting prohibited ff75h 00h r/w address after reset r/w (8.0 mhz) note note 4
151 pd1615, pd16f15, pd1616 (3) 8-bit timer mode control register 50 (tmc50) this register enables/stops operation of 8-bit timer register 50, sets the operating mode of 8-bit timer register 50 and controls operation of 8-bit timer/event counter 50 output control circuit. it selects the r-s flip-flop (timer output f/f 1,2) setting/resetting, the active level in pwm mode, inversion enabling/disabling in modes other than pwm mode and 8-bit timer/event counter 5 timer output enabling/ disabling. tmc50 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc50 to 04h. figure 7-6: 8-bit timer output control register 50 format cautions: 1. timer operation must be stopped before setting tmc50. 2. if lvs50 and lvr50 are read after data are set, they will be 0. 3. be sure to set bit 4 and bit 5 to 0. note: if tm50 is used as clock generation for sio30, no clock will be supplied to sio30 unless toe50 is set to 1. in this case a square wave signal is output from the to50 pin. tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 <7> 6 5 4 <3> <2> 1 <0> symbol tmc50 ff70h 04h r/w address after reset r/w toe50 8-bit timer/event counter 50 output control 0 output disabled (port mode) 1 output enabled tmc501 0 active high 1 active low in pwm mode in other mode active level selection timer output f/f1 control inversion operation disabled inversion operation enabled lvs50 lvr50 00 01 10 11 8-bit timer/event counter 50 timer output f/f1 status setting no change timer output f/f1 reset (0) timer output f/f1 set (1) setting prohibited tmc506 8-bit timer/event counter 50 operating mode selection 0 clear & start mode on match of tm50 and cr50 1 pwm mode (free-running) tce50 8-bit timer register 50 operation control 0 operation stop (tm50 clear to 0) 1 operation enable
152 pd1615, pd16f15, pd1616 (4) 8-bit timer mode control register 51 (tmc51) this register enables/stops operation of 8-bit timer register 51, sets the operating mode of 8-bit timer register 51 and controls operation of 8-bit timer/event counter 51 output control circuit. it selects the r-s flip-flop (timer output f/f 1,2) setting/resetting, active level in pwm mode, inversion enabling/disabling in modes other than pwm mode and 8-bit timer/event counter 51 timer output enabling/ disabling. tmc51 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc51 to 04h. figure 7-7: 8-bit timer output control register 51 format cautions 1. timer operation must be stopped before setting tmc51. 2. if lvs51 and lvr51 are read after data are set, they will be 0. 3. be sure to set bit 4 and bit 5 to 0. tce51 tmc516 00 lvs51 lvr6 tmc511 toe51 <7> 6 5 4 <3> <2> 1 <0> symbol tmc51 ff74h 04h r/w address after reset r/w toe51 8-bit timer/event counter 51 output control 0 output disabled (port mode) 6 output enabled tmc511 0 active high 1 active low in pwm mode in other mode active level selection timer output f/f1 control inversion operation disabled inversion operation enabled lvs51 lvr51 00 01 10 11 8-bit timer/event counter 51 timer output f/f1 status setting no change timer output f/f1 reset (0) timer output f/f1 set (1) setting prohibited tmc516 8-bit timer/event counter 51 operating mode selection 0 clear & start mode on match of tm51 and cr51 1 pwm mode (free-running) tce51 8-bit timer register 51 operation control 0 operation stop (tm51 clear to 0) 1 operation enable
153 pd1615, pd16f15, pd1616 (5) port mode register 0 (pm0) this register sets port 0 input/output in 1-bit units. when using the p06/ti50/to50 and p07/ti51/to51 pins for timer output, set pm06, pm07 and output latches of p06 and p07 to 0. pm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm0 to ffh. figure 7-8: port mode register 0 format pm07 7 pm06 6 11 4 1 3210 ff20h address pm0 symbol pm02 pm01 pm00 5 ffh after reset r/w r/w pm0n 0 1 p0n pin input/output mode selection (n=0 to 7) output mode (output buffer on) input mode (output buffer off)
154 pd1615, pd16f15, pd1616 7.4 8-bit timer/event counters 50 and 51 operations 7.4.1 interval timer operations setting the 8-bit timer mode control registers (tmc50 and tmc51) as shown in figure 7-9 allows operation as an interval timer. interrupts are generated repeatedly using the count value preset in 8- bit compare registers (cr50 and cr51) as the interval. when the count value of the 8-bit timer register 50 or 51 (tm50, tm51) matches the value set to cr50 or cr51, counting continues with the tm50 or tm51 value cleared to 0 and the interrupt request signal (inttm50, inttm51) is generated. count clock of the 8-bit timer register 50 (tm50) can be selected with the timer clock select register 50 (tcl50) and count clock of the 8 bit timer register 51 (tm51) can be selected with the timer clock select register 51 (tcl51). figure 7-9: 8-bit timer mode control register settings for interval timer operation remarks: 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see 9.3 (3), (4) for details. 2. n = 50, 51 figure 7-10: interval timer operation timings (1/3) (a) when n = 00h to ffh remarks: 1. interval time = (n + 1) x t: n = 00h to ffh 2. n = 50, 51 3. signal output at to50, when defined as square wave output. 1 tcen 0 tmcn6 0 0 0/1 lvsn lvrn tmcn1 toen tmcn 0/1 0/1 0/1 clear and start on match of tmn and crn tmn operation enable t 00 01 n 00 01 n 00 01 n n n n n clear clear count start interrupt acknowledge interrupt acknowledge interval time interval time interval time count clock tmn count value crn tcen inttmn ton
155 pd1615, pd16f15, pd1616 figure 7-10: interval timer operation timings (2/3) (b) when crn = 00h (c) when crn = ffh remark: n = 50, 51 t count clock tmn crn tcen inttmn tion interval time 00h 00h 00h 00h 00h t count clock tmn crn tcen inttmn tion 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt received interrupt received
156 pd1615, pd16f15, pd1616 figure 7-10: interval timer operation timings (3/3) (d) operated by cr5n transition (m < n) remark: n = 50, 51 (e) operated by cr5n transition (m > n) count clock tmn crn tcen inttmn tion 00h n n m n ffh 00h m 00h m crn transition tmn overflows since m < n count clock tmn crn tcen inttmn tion ne1 n n 00h 01h n me 1 m 00h 01h m crn transition
157 pd1615, pd16f15, pd1616 table 7-6: 8-bit timer/event counters 50 interval times remarks: 1. f x : main system clock oscillation frequency 2. values in parentheses apply to operation with f x = 8.0 mhz. 3. n = 50, 51 table 7-7: 8-bit timer/event counters 51 interval times tcln2 tcln1 tcln0 minimum interval time maximum interval time resolution 0 0 0 tin input cycle 2 8 x tin input cycle tin i nput edge input cycle 0 0 1 tin input cycle 2 8 x tin input cycle tin i nput edge input cycle 0102 1 x 1/f x (250 ns) 2 9 x 1/f x (64 s) 2 1 x 1/f x (250 ns) 0112 3 x 1/f x (1 s) 2 11 x 1/f x (256 s) 2 3 x 1/f x (1 s) 1002 5 x 1/f x (4 s) 2 13 x 1/f x (1 ms) 2 5 x 1/f x (4 s) 1012 7 x 1/f x (16 s) 2 15 x 1/f x (4 ms) 2 7 x 1/f x (16 s) 1102 8 x 1/f x (32 s) 2 16 x 1/f x (8 ms) 2 8 x 1/f x (32 s) 1112 11 x 1/f x (256 s) 2 19 x 1/f x (65 ms) 2 11 x 1/f x (256 s) other than above setting prohibited tcln2 tcln1 tcln0 minimum interval time maximum interval time resolution 0 0 0 tin input cycle 2 8 x tin input cycle tin i nput edge input cycle 0 0 1 tin input cycle 2 8 x tin input cycle tin i nput edge input cycle 0101/f x (125 ns) 2 8 x 1/f x (32 s) 1/f x (125 ns) 0112 4 x 1/f x (2 s) 2 12 x 1/f x (512 s) 2 4 x 1/f x (2 s) 1002 6 x 1/f x (8 s) 2 14 x 1/f x (2 ms) 2 6 x 1/f x (8 s) 1012 7 x 1/f x (16 s) 2 15 x 1/f x (4 ms) 2 7 x 1/f x (16 s) 1102 8 x 1/f x (32 s) 2 16 x 1/f x (8 ms) 2 8 x 1/f x (32 s) 1112 10 x 1/f x (128 s) 2 18 x 1/f x (32 ms) 2 10 x 1/f x (128 s) other than above setting prohibited
158 pd1615, pd16f15, pd1616 7.4.2 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti50/p06/ to50 and ti51/p07/to51 pins with 8-bit timer registers 50 and 51 (tm50 and tm51). tm50 and tm51 are incremented each time the valid edge specified with timer clock select registers 50 and 51 (tcl50 and tcl51) is input. either rising or falling edge can be selected. when the tm50 and tm51 counted values match the values of 8-bit compare registers (cr50 and cr51), tm50 and tm51 are cleared to 0 and the interrupt request signals (inttm50 and inttm51) are generated. figure 7-11: 8-bit timer mode control register setting for external event counter operation remarks: 1. n = 50, 51 2. x: dont care figure 7-12: external event counter operation timings (with rising edge specified) remarks: 1. n = 00h to ffh 2. n = 50, 51 1 tcen 0 tmcn6 00x lvsn lvrn tmcn1 toen tmcn xx0 ton output disable clear & start mode on match of tmn and crn tmn operation enable 00 01 13 n count clock tmn count value crn tcen inttmn 05 n-1 00 02 03 01 02 04 n
159 pd1615, pd16f15, pd1616 7.4.3 square-wave output a square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers (cr50 and cr51). the to50/p06/ti50 or to51/p07/ti51 pin output status is reversed at intervals of the count value preset to cr50 or cr51 by setting bit 1 (tmc501) and bit 0 (toe50) of the 8-bit timer output control register 5 (tmc50), or bit 1 (tmc511) and bit 0 (toe51) of the 8-bit timer mode control register 6 (tmc51) to 1. this enables a square wave of any selected frequency to be output. figure 7-13: 8-bit timer mode control register settings for square-wave output operation caution: when ti50/p06/to50 or ti51/p07/to51 pin is used as the timer output, set port mode register (pm00 or pm07) and output latch to 0. remark: n = 50, 51 figure 7-14: square-wave output operation timing note: ton output initial value can be set by bits 2 and 3 (lvrn, lvsn) of the 8-bit timer mode control register tcmn. remark: n = 50, 51 1 tcen 0 tmcn6 0 0 0/1 lvsn lvrn tmcn1 toen tmcn 0/1 1 1 ton output enable inversion of output on match of tmn and crn specifies to1 output f/f1 initial value clear and start mode on match of tmn and crn tmn operation enable count clock tmn count value crn t0n note count start 00h 01h n-1 n 02h 00h n 02h 00h 01h n-1 n
160 pd1615, pd16f15, pd1616 table 7-8: 8-bit timer/event counters 50 square-wave output ranges remarks: 1. f: main system clock oscillation frequency 2. values in parentheses when operated at f x = 8.0 mhz. 3. n = 50, 51 table 7-9: 8-bit timer/event counters 51 square-wave output ranges minimum pulse time maximum pulse time resolution 2 1 x 1/f x (250 ns) 2 9 x 1/f x (64 s) 2 1 x 1/f x (250 ns) 2 3 x 1/f x (1 s) 2 11 x 1/f x (256 s) 2 3 x 1/f x (1 s) 2 5 x 1/f x (4 s) 2 13 x 1/f x (1 ms) 2 5 x 1/f x (4 s) 2 7 x 1/f x (16 s) 2 15 x 1/f x (4 ms) 2 7 x 1/f x (16 s) 2 8 x 1/f x (32 s) 2 16 x 1/f x (8 ms) 2 8 x 1/f x (32 s) 2 11 x 1/f x (256 s) 2 19 x 1/f x (65 ms) 2 11 x 1/f x (256 s) minimum pulse time maximum pulse time resolution 1/f x (125 ns) 2 8 x 1/f x (32 s) 1/f x (125 ns) 2 4 x 1/f x (2 s) 2 12 x 1/f x (512 s) 2 4 x 1/f x (2 s) 2 6 x 1/f x (8 s) 2 14 x 1/f x (2 ms) 2 6 x 1/f x (8 s) 2 7 x 1/f x (16 s) 2 15 x 1/f x (4 ms) 2 7 x 1/f x (16 s) 2 8 x 1/f x (32 s) 2 16 x 1/f x (8 ms) 2 8 x 1/f x (32 s) 2 10 x 1/f x (128 s) 2 18 x 1/f x (32 ms) 2 10 x 1/f x (128 s)
161 pd1615, pd16f15, pd1616 7.4.4 pwm output operations setting the 8-bit timer mode control registers (tmc50 and tmc51) as shown in figure 7-15 allows operation as pwm output. pulses with the duty rate determined by the values preset in 8-bit compare registers (cr50 and cr51) output from the to50/p06/ti50 or to51/p07/ti51 pin. select the active level of pwm pulse with bit 1 of the 8-bit timer mode control register 50 (tmc50) or bit 1 of the 8-bit timer mode control register 51 (tmc51). this pwm pulse has an 8-bit resolution. the pulse can be converted into an analog voltage by integrating it with an external low-pass filter (lpf). count clock of the 8-bit timer register 50 (tm50) can be selected with the timer clock select register 50 (tcl50) and count clock of the 8-bit timer register 51 (tm51) can be selected with the timer clock select register 51 (tcl51). pwm output enable/disable can be selected with bit 0 (toe50) of tmc50 or bit 0 (toe51) of tmc51. figure 7-15: 8-bit timer control register settings for pwm output operation remarks: 1. n = 50, 51 2. x: dont care 1 tcen 1 tmcn6 00x lvsn lvrn tmcn1 toen tmcn x 0/1 1 ton output enable sets active level pwm mode tmn operation enable
162 pd1615, pd16f15, pd1616 figure 7-16: pwm output operation timing (active high setting) remark: n = 50, 51 figure 7-17: pwm output operation timings (crn0 = 00h, active high setting) remark: n = 50, 51 count clock tmn count value crn tcen inttmn ton 01 02 ff 00 01 02 n n+1 n+2 n+3 00 ovfn mn n 00 inactive level crn changing active level inactive level inactive level (m n) count clock tmn count value crn tcen inttmn ton 01 02 ff 00 01 02 ff 00 01 02 00 ovfn m00 00 00 inactive level crn changing (m 00) inactive level
163 pd1615, pd16f15, pd1616 figure 7-18: pwm output operation timings (crn = ffh, active high setting) remark: n = 50, 51 figure 7-19: pwm output operation timings (crn changing, active high setting) remark: n = 50, 51 caution: if crn is changed during tmn operation, the value changed is not reflected until tmn overflows. count clock tmn count value crn tcen inttmn ton 01 02 ff 00 01 02 ff 00 01 02 00 ovfn ff ff ff 00 inactive level inactive level active level inactive level active level count clock tmn count value crn0 tcen inttmn ton ovfn active level inactive level 00 ff n+2 n+1 n 02 01 00 ff 01 02 m+2 m+1 m m+3 00 active level inactive level crn changing n n mm (n m)
164 pd1615, pd16f15, pd1616 7.5 cautions on 8-bit timer/event counters 50 and 51 (1) timer start errors an error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts. this is because 8-bit timer registers 50 and 51 are started asynchronously with the count pulse. figure 7-20: 8-bit timer registers 50 and 51 start timings remark: n = 50, 51 (2) compare registers 50 and 51 sets the 8-bit compare registers (cr50 and cr51) can be set to 00h. thus, when an 8-bit compare register is used as an event counter, one-pulse count operation can be carried out. figure 7-21: external event counter operation timings remark: n = 50, 51 count pulse tmn count value 00h timer start 01h 02h 03h 04h tin input crn 00h tmn count value 00h 00h 00h 00h ton interrupt request flag
165 pd1615, pd16f15, pd1616 (3) operation after compare register change during timer count operation if the values after the 8-bit compare registers (cr50 and cr51) are changed are smaller than those of 8-bit timer registers (tm50 and tm51), tm50 and tm51 continue counting, overflow and then restarts counting from 0. thus, if the value (m) after cr50 and cr51 change is smaller than that (n) before change it is necessary to restart the timer after changing cr50 and cr51. figure 7-22: timings after compare register change during timer count operation remark: n = 50, 51 count pulse crn n x x-1 ffh 00h 01h m 02h tmn count value
166 pd1615, pd16f15, pd1616 [memo]
167 pd1615, pd16f15, pd1616 chapter 8 watch timer 8.1 watch timer functions the watch timer has the following functions: ? watch timer ? interval timer the watch timer and the interval timer can be used simultaneously. the figure 8-1 shows watch timer block diagram. figure 8-1: block diagram of watch timer f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 0 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector selector selector wtm3
168 pd1615, pd16f15, pd1616 (1) watch timer when the main system clock or subsystem clock is used, interrupt requests (intwt) are generated at 0.5 second intervals. (2) interval timer interrupt requests (intwti) are generated at the preset time interval. table 8-1: interval time selection remark: f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 8.2 watch timer configuration the watch timer consists of the following hardware. table 8-2: watch timer configuration interval time when operated at fx=8.00 mhz when operated at fx t =32.768 khz 2 4 /fw 256 s 488 s 2 5 /fw 512 s 977 s 2 6 /fw 1 ms 1,95 ms 2 7 /fw 2 ms 3,91 ms 2 8 /fw 4 ms 7,81 ms 2 9 /fw 8,19 ms 15,6 ms item configuration counter 5 bits x 1 prescaler 9 bits x 1 control register watch timer mode control register (wtm)
169 pd1615, pd16f15, pd1616 8.3 watch timer mode register (wtm) this register sets the watch timer count clock, the watch timer operating mode, and prescaler interval time and enables/disables prescaler and 5-bit counter operations. wtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wtm to 00h. figure 8-2: watch timer mode control register (wtm) format caution: when the watch timer is used, the prescaler should not be cleared frequently. when rewriting wtm4 to wtm6 to other data, stop the timer operation beforehand. remarks: 1. fw: watch timer clock frequency (fx/2 7 or fxt) 2. fx: main system clock oscillation frequency 3. fxt: subsystem clock oscillation frequency symbol76543210addressafterresetr/w wtm wtm7 wtm6 wtm5 wtm4 wtm3 0 wtm1 wtm0 ff41h 00h r/w wtm7 watch timer count clock selection 0 input clock set to f x /2 7 1 input clock set to f xt wtm6 wtm5 wtm4 prescaler interval time selection f x = 8.00 mhz operation f xt = 32.768 khz operation 0002 4 /fw (256 m s) 2 4 /fw (488 m s) 0012 5 /fw (512 s) 2 5 /fw (977 m s) 0102 6 /fw (1 ms) 2 6 /fw (1.95 ms) 0112 7 /fw (2 ms) 2 7 /fw (3.91 ms) 1002 8 /fw (4 ms) 2 8 /fw (7.81 ms) 1012 9 /fw (8.19 ms) 2 9 /fw (15.6 ms) other than above setting prohibited wtm3 watch operating mode selections 0 normal operating mode (interrupt generation at 2 14 /fw) 1 fast feed operating mode (interrupt generation at 2 5 /fw) wtm1 5-bit counter operation control 0 clear after operation stop 1 operation enable wtm0 prescaler operation control 0 clear after operation stop 1 operation enable
170 pd1615, pd16f15, pd1616 8.4 watch timer operations 8.4.1 watch timer operation when the 32.768-khz subsystem clock is used, the timer operates as a watch timer with a 0.5-second interval. the watch timer is generated interrupt request at the constant time interval. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer mode control register is set to 1, the 5-bit counter is cleared and the count operation stops. for simultaneous operation of the interval timer, zero-second start can be achieved by setting wtm1 to 0. 8.4.2 interval timer operation the watch timer operates as interval timer which generates interrupt request repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm4 to wtm6) of the watch timer mode control register (wtm). table 8-3: interval timer operation remark: f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency wtm6 wtm5 wtm4 interval time fx=8.00 mhz operation fx t =32.768 mhz operation 000 2 4 x 1/fw 256 s 488 s 001 2 4 x 1/fw 512 s 977 s 010 2 4 x 1/fw 1 ms 1.95 ms 011 2 4 x 1/fw 2 ms 3.91 ms 100 2 4 x 1/fw 4 ms 7.81 ms 101 2 4 x 1/fw 8.19 ms 15.6 ms other than above setting prohibited
171 pd1615, pd16f15, pd1616 figure 8-3: operation timing of watch timer/interval timer remark: f w : watch timer clock frequency 0h start overflow overflow 5-bit counter count clock f w watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (0.5s) interval timer (t) t interrupt time of watch timer (0.5s)
172 pd1615, pd16f15, pd1616 [memo]
173 pd1615, pd16f15, pd1616 chapter 9 watchdog timer 9.1 watchdog timer functions the watchdog timer has the following functions: ? watchdog timer ? interval timer caution: select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (wdtm). (1) watchdog timer mode an inadvertent program loop is detected. upon detection of the inadvertent program loop, a non- maskable interrupt request or reset can be generated. table 9-1: watchdog timer inadvertent program overrun detection times remark: figures in parentheses apply to operation with f x = 8.0 mhz. (2) interval timer mode interrupts are generated at the preset time intervals. table 9-2: interval times remark: figures in parentheses apply to operation with f x = 8.0 mhz. runaway detection time 2 12 x 1/f x 2 12 x 1/f x (512 m s) 2 13 x 1/f x 2 13 x 1/f x (1 ms) 2 14 x 1/f x 2 14 x 1/f x (2 ms) 2 15 x 1/f x 2 15 x 1/f x (4 ms) 2 16 x 1/f x 2 16 x 1/f x (8.19 ms) 2 17 x 1/f x 2 17 x 1/f x (16.38 ms) 2 18 x 1/f x 2 18 x 1/f x (32.76 ms) 2 20 x 1/f x 2 20 x 1/f x (131 ms) interval time 2 12 x 1/f x 2 12 x 1/f x (512 m s) 2 13 x 1/f x 2 13 x 1/f x (1 ms) 2 14 x 1/f x 2 14 x 1/f x (2 ms) 2 15 x 1/f x 2 15 x 1/f x (4 ms) 2 16 x 1/f x 2 16 x 1/f x (8.19 ms) 2 17 x 1/f x 2 17 x 1/f x (16.38 ms) 2 18 x 1/f x 2 18 x 1/f x (32.76 ms) 2 20 x 1/f x 2 20 x 1/f x (131 ms)
174 pd1615, pd16f15, pd1616 9.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 9-3: watchdog timer configuration figure 9-1: watchdog timer block diagram item configuration control register timer clock select register (wdcs) watchdog timer mode register (wdtm) prescaler f x 2 1 f x 2 2 f x 2 3 f x 2 4 f x 2 5 f x 2 6 selector watchdog timer mode register internal bus internal bus wdcs2 wdcs1 wdcs0 f x /2 12 f x 2 8 watchdog timer clock selection register 3 wdtm4 wdtm3 8-bit counter tmmk run tmif intwdt maskable interrupt request reset intwdt non-maskable interrupt request control circuit
175 pd1615, pd16f15, pd1616 9.3 watchdog timer control registers the following two types of registers are used to control the watchdog timer. ? watchdog timer clock select register (wdcs) ? watchdog timer mode register (wdtm) (1) watchdog timer clock select register (wdcs) this register sets the watchdog timer count clock. wdcs is set with 8-bit memory manipulation instruction. reset input sets wdcs to 00h. figure 9-2: watchdog timer clock select register format caution: when rewriting wdcs to other data, stop the timer operation beforehand. remarks: 1. fx: main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. symbol76543210addressafterresetr/w wdcs00000wdcs2wdcs1wdcs0ff42h00hr/w wdcs2 wdcs1 wdcs0 overflow time of watchdog 1 interval timer 000f x /2 12 (512 m s) 001f x /2 13 (1 ms) 010f x /2 14 (2 ms) 011f x /2 15 (4 ms) 100f x /2 16 (8.19 ms) 101f x /2 17 (16.38 ms) 110f x /2 18 (32.76 ms) 111f x /2 20 (131 ms)
176 pd1615, pd16f15, pd1616 (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 9-3: watchdog timer mode register format notes: 1. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 2. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. caution: when 1 is set in run so that the watchdog timer is cleared, the actual overflow time is up to 0.5 % shorter than the time set by watchdog timer clock select register. remark: x = don't care. symbol76543210addressafterresetr/w wdtm run 0 0 wdtm4 wdtm3 0 0 0 fff9h 00h r/w wdtm4 wdtm3 watchdog timer operation mode selection note 1 0x interval timer mode (maskable interrupt occurs upon generation of an overflow) 10 watchdog timer mode 1 (non-maskable interrupt occurs upon generation of an overflow) 11 watchdog timer mode 2 (reset operation is activated upon generation of an overflow) run watchdog timer operation mode selection note 2 0 count stop 1 counter is cleared and counting starts
177 pd1615, pd16f15, pd1616 9.4 watchdog timer operations 9.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. the watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (wdcs0 to wdcs2) of the timer clock select register (wdcs). watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set overrun detection time interval. the watchdog timer can be cleared and counting is started by setting run to 1. if run is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable interrupt request is generated according to the wdtm bit 3 (wdtm3) value. the watchdog timer can be cleared when run is set to 1. the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruction. cautions 1. the actual overrun detection time may be shorter than the set time by a maximum of 0.5 %. 2. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. table 9-4: watchdog timer overrun detection time remarks: 1. fx: main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. wdcs2 wdcs1 wdcs0 runaway detection time 000f x /2 12 (512 m s) 001f x /2 13 (1 ms) 010f x /2 14 (2 ms) 011f x /2 15 (4 ms) 100f x /2 16 (8.19 ms) 101f x /2 17 (16.38 ms) 110f x /2 18 (32.76 ms) 111f x /2 20 (131 ms)
178 pd1615, pd16f15, pd1616 9.4.2 interval timer operation the watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval of the preset count value when bit 3 (wdtm3) of the watchdog timer mode register (wdtm) is set to 0, respectively. when the watchdog timer operates as interval timer, the interrupt mask flag (tmmk4) and priority specify flag (tmpr4) are validated and the maskable interrupt request (intwdt) can be generated. among maskable interrupts, the intwdt default has the highest priority. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set bit 7 (run) of wdtm to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions: 1. once bit 4 (wdtm4) of wdtm is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless reset input is applied. 2. the interval time just after setting with wdtm may be shorter than the set time by a maximum of 0.5 %. 3. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. table 9-5: interval timer interval time remarks: 1. fx: main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 8.0 mhz. wdcs2 wdcs1 wdcs0 interval time 000f x /2 12 (512 m s) 001f x /2 13 (1 ms) 010f x /2 14 (2 ms) 011f x /2 15 (4 ms) 100f x /2 16 (8.19 ms) 101f x /2 17 (16.38 ms) 110f x /2 18 (32.76 ms) 111f x /2 20 (131 ms)
179 pd1615, pd16f15, pd1616 [memo]
180 pd1615, pd16f15, pd1616 chapter 10 clock output control circuit 10.1 clock output control circuit functions the clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsi. clocks selected with the clock output selection register (cks) are output from the pcl/p120/s7 pin. follow the procedure below to output clock pulses. (1) select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (ccs0 to ccs2) of cks. (2) set the p120 output latch to 0. (3) set bit 0 (pm120) of port mode register 120 to 0 (set to output mode). (4) set bit 4 (cloe) of clock output selection register to 1. caution: clock output cannot be used when setting the output latch to 1. remark: when clock output enable/disable is switched, the clock output control circuit does not output pulses with small widths (see the portions marked with * in figure 12-1). figure 10-1: remote controlled output application example cloe pcl/p120/s7 pin output * *
181 pd1615, pd16f15, pd1616 10.2 clock output control circuit configuration the clock output control circuit consists of the following hardware. table 10-1: clock output control circuit configuration figure 10-2: clock output control circuit block diagram item configuration control register clock output selection register (cks) port mode register 3 (pm3) internal bus f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 cloe ccs2 ccs1 ccs0 p120 output latch synchronizing circuit 4 pm120 selector clock output selection register port mode register 12 pcl /p120/s7 f x t
182 pd1615, pd16f15, pd1616 10.3 clock output function control registers the following two types of registers are used to control the clock output function. ? clock output selection register (cks) ? port mode register 12 (pm12) (1) clock output selection register (cks) this register sets pcl output clock. cks is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets cks to 00h. caution: when enabling pcl output, set ccs50 to ccs52, then set 1 in cloe with a 1-bit memory manipulation instruction. figure 10-3: clock output selection register format symbol ? 6 5 4 3 2 1 0 address afterreset r/w cks 0 0 0 cloe ccs3 ccs2 ccs1 ccs0 ff40h 00h r/w remarks: 1. fx: main system clock oscillation frequency 2. fx t : subsystem clock oscillation frequency. 3. figures in parentheses apply to operation with f x = 8.0 mhz and fx t = 32.718 khz. ccs3 ccs2 ccs1 ccs0 pcl output clock selection 0000f x (8 mhz) 0001f x /2 1 (4 mhz) 0010f x /2 2 (2 mhz) 0011f x /2 3 (1 mhz) 0100f x /2 4 (500 khz) 0101f x /2 5 (250 khz) 0110f x /2 6 (125 khz) 0111f x /2 7 (62.5 khz) 1000f x t (32.7 khz) other than above setting prohibited cloe pcl output control 0 output disable 1 output enable
183 pd1615, pd16f15, pd1616 ( 2) port mode register 12 (pm12) this register sets port 12 input/output in 1-bit units. when using the p120/pcl/s7 pin for clock output function, set pm120 and output latch of p120 to 0. pm12 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm12 to ffh. figure 10-4: port mode register 12 format symbol76543210addressafterresetr/w pm12 pm127 pm126 pm125 pm124 pm123 pm122 pm121 pm120 ff2ch ffh r/w pm12n p12n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) ( 3) port function register 12 (pf12) this register sets the port function of port 12 in 1-bit units. when using the pcl output, the register pf12 has to be set to port function. pf12 is with an 1-bit or an 8-bit memory manipulation instruction. reset input sets pm12 to 00h. figure 10-5: port function register 12 (pf12) format symbol76543210addressafterresetr/w pf12 pf127 pf126 pf125 pf124 pf123 pf122 pf121 pf120 ff5ch 00h r/w pf12n p12n port function selection (n = 0 to 7) 0 port mode 1 lcd mode note: for the pd1616 set always 00h to pf12.
184 pd1615, pd16f15, pd1616 [memo]
185 pd1615, pd16f15, pd1616 chapter 11 a/d converter 11.1 a/d converter functions the a/d converter is an 8-bit resolution converter that converts analog inputs into digital values. it can control up to 4 analog input channels (ani0 to ani3). this a/d converter has the following functions: (1) a/d conversion with 8-bit resolution one channel of analog input is selected from ani0 to ani3, and a/d conversion is repeatedly executed with a resolution of 8 bits. each time the conversion has been completed, an interrupt request (intad) is generated. (2) power-fail detection function this function is to detect for example a voltage drop in the battery of an automobile. the result of a/d conversion (value of the adcr1 register) and the value of pft register (pft: power-fail compare threshold value register) are compared. if the condition for comparison is satisfied, the intad is generated. figure 11-1: a/d converter block diagram ani0/p10 ani1/p11 ani2/p12 ani3/p13 selector sample & hold circuit voltage comparator successive approximation register (sar) control circuit 3 a/d conversion result register (adcr1) tap selector av dd avss intad a/d converter mode register analog input channel specification register internal bus ads12 ads11 ads10 adcs1 fr12 fr11 fr10 /av ref
186 pd1615, pd16f15, pd1616 figure 11-2: power-fail detection function block diagram 11.2 a/d converter configuration a/d converter consists of the following hardware. table 11-1: a/d converter configuration (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is set (end of a/d conversion), the sar contents are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr1) this register holds the a/d conversion result. each time when the a/d conversion ends, the conversion result is loaded from the successive approximation register. adcr1 is read with an 8-bit memory manipulation instruction. reset input clears adcr1 to 00h. caution: if a write operation is executed to the a/d converter mode register (adm1) and the analog input channel specification register (ads1) the contents of adcr1 are undefined. read the conversion result before a write operation is executed to adm1 and ads1. if a timing other than the above is used, the correct conversion result may not be read. item configuration analog input 8 channels (ani0 to ani7) register successive approximation register (sar) a/d conversion result register (adcr1) control register a/d converter mode register (adm1) analog input channel specification register (ads1) power-fail compare mode register (pfm) power-fail compare threshold value register (pft) ani0/p10 ani1/p11 ani2/p12 ani3/p13 multiplex er selector a/d converter internal bus power-fail compare mode register (pfm) comparator pfen pfcm power-fail compare threshold value register (pft) intad pfen pfcm
187 pd1615, pd16f15, pd1616 (3) sample & hold circuit the sample & hold circuit samples each analog input sequentially applied from the input circuit, and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is in av dd to av ss , and generates a voltage to be compared to the analog input. (6) ani0 to ani3 pins these are four analog input pins to input analog signals to the a/d converter. ani0 to ani3 are alternate-function pins that can also be used for digital input. caution: use ani0 to ani3 input voltages within the specification range. if a voltage higher than av dd or lower than av ss is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (7) av dd /av ref pin this pin inputs the a/d converter reference voltage and is used as the ad-converter power supply pin. the supply power has to be connected when the a/d converter is used. it converts signals input to ani0 to ani3 into digital signals according to the voltage applied between av dd /av ref and av ss . (8) av ss pin this is the gnd potential pin of the a/d converter. always keep it at the same potential as the v ss pin even when not using the a/d converter.
188 pd1615, pd16f15, pd1616 11.3 a/d converter control registers the following 4 types of registers are used to control a/d converter. ? a/d converter mode register (adm1) ? analog input channel specification register (ads1) ? power-fail compare mode register (pfm) ? power-fail compare threshold value register (pft) (1) a/d converter mode register (adm1) this register sets the conversion time for analog input to be a/d converted, conversion start/stop and external trigger. adm1 is set with an 8-bit memory manipulation instruction. reset input clears adm1 to 00h. figure 11-3: a/d converter mode register (adm1) format note: set fr10 to fr12 that the a/d conversion time is 15 s or more. caution: bits 0 to 2 and bit 6 must be set to 0. remark: fx: main system clock oscillation frequency adcs1 a/d conversion operation control 0 stop conversion operation 1 enable conversion operation fr12 fr11 fr10 conversion time selection note 000144/fx 001120/fx 01096/fx 100288/fx 101240/fx 110192/fx other than above setting prohibited symbol76543210addressafter resetr/w adm1 adcs1 0 fr12 fr11 fr10 0 0 0 ff80h 00h r/w
189 pd1615, pd16f15, pd1616 (2) analog input channel specification register (ads1) this register specifies the analog voltage input port for a/d conversion. ads1 is set with an 8-bit memory manipulation instruction. reset input clears ads1 to 00h. figure 11-4: analog input channel specification register (ads1) format caution: bits 2 to 7 must be set to 0. symbol76543210addressafter resetr/w ads1000000ads11ads10ff81h00hr/w ads11 ads10 analog input channel specification 00ani0 01ani1 10ani2 11ani3
190 pd1615, pd16f15, pd1616 (3) power-fail compare mode register (pfm) the power-fail compare mode register (pfm) controls a comparison operation. reset input clears pfm to 00h. figure 11-5: power-fail compare mode register (pfm) format caution: bits 0 to 5 must be set to 0. (4) power-fail compare threshold value register (pft) the power-fail compare threshold value register (pft) sets a threshold value against which the result of a/d conversion is to be compared. pft is set with an 8-bit memory manipulation instruction. reset input clears pft to 00h. figure 11-6: power-fail compare threshold value register (pft) pfen enables power-fail comparison 0 disables power-fail comparison (used as normal a/d converter) 1 enables power-fail comparison (used to detect power failure) pfcm power-fail compare mode selection 0 adcr1 3 pft generates interrupt request signal intad 0 adcr1 < pft does not generate interrupt request signal intad 1 adcr1 3 pft does not generate interrupt request signal intad 1 adcr1 < pft generates interrupt request signal intad symbol76543210addressafter resetr/w pfmpfenpfcm000000ff82h00hr/w symbol76543210addressafter resetr/w pft pft7 pft6 pft5 pft4 pft3 pft2 pft1 pft0 ff83h 00h r/w
191 pd1615, pd16f15, pd1616 11.4 a/d converter operations 11.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with the analog input channel specification register (ads1). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> bit 7 of the successive approximation register (sar) is set internally so that the tap selector starts with a series resistor string voltage tap of (1/2) av dd . <5> the voltage difference between the series resistor string voltage tap and analog input is compared with the voltage comparator. if the analog input is greater than (1/2) av dd , the msb of sar remains set. if the analog input is smaller than (1/2) av dd , the msb is reset. <6> next, bit 6 of sar is automatically set, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 7, as described below. ? bit 7 = 1: (3/4) av dd ? bit 7 = 0: (1/4) av dd the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated as follows. ? analog input voltage 3 voltage tap: bit 6 = 1 ? analog input voltage < voltage tap: bit 6 = 0 <7> comparison is continued in this way up to bit 0 of sar. <8> upon completion of the comparison of 8 bits, an effective digital result value remains in sar, and the result value is transferred to and latched in the a/d conversion result register (adcr1). at the same time, the a/d conversion end interrupt request (intad) can also be generated. caution: the first a/d conversion value just after a/d conversion is undefined.
192 pd1615, pd16f15, pd1616 figure 11-7: basic operation of 8-bit a/d converter a/d conversion operations are performed continuously until bit 7 (adcs1) of the a/d converter mode register (adm1) is reset (to 0) by software. if a write operation to the adm1 and analog input channel specification register (ads1) is performed during an a/d conversion operation, the conversion operation is initialized, and if the adcs1 bit is set (to 1), conversion starts again from the beginning. reset input sets the a/d conversion result register (adcr1) to 00h. conversion time sampling time sampling a/d conversion undefined 80h c0h or 40h conversion result a/d converter operation sar adcr1 intad conversion result
193 pd1615, pd16f15, pd1616 11.4.2 input voltage and conversion results the relation between the analog input voltage input to the analog input pins (ani0 to ani3) and the a/d conversion result (stored in the a/d conversion result register (adcr1)) is shown by the following expression. adcr1 = int ( vin x 256 + 0.5) av dd or (adcr1 C 0.5) x av dd - v in < (adcr1 + 0.5) x av dd 256 256 where, int( ) : function which returns integer part of value in parentheses v in : analog input voltage av dd :av dd pin voltage adcr1 : a/d conversion result register (adcr1) value figure 11-8 shows the relation between the analog input voltage and the a/d conversion result. figure 11-8: relation between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr1) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av dd
194 pd1615, pd16f15, pd1616 11.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one analog input channel is selected from among ani0 to ani3 with the analog input channel specification register (ads1) and a/d conversion is performed. the following two types of functions can be selected by setting the pfen flag of the pfm register. (1) normal 8-bit a/d converter (pfen = 0) (2) power-fail detection function (pfen = 1) (1) a/d conversion (when pfen = 0) when bit 7 (adcs1) of the a/d converter mode register (adm1) is set to 1 and bit 7 of the power- fail compare mode register (pfm) is set to 0, a/d conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ads1) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr1), and the interrupt request signal (intad) is generated. after one a/d conversion operation is started and ended, the next conversion operation is immediately started. a/d conversion operations are repeated until new data is written to ads1. if ads1 is rewritten during a/d conversion operation, the a/d conversion operation under execution is stopped, and a/d conversion of a newly selected analog input channel is started. if data with adcs1 set to 0 is written to adm1 during a/d conversion operation, the a/d conversion operation stops immediately. (2) power-fail detection function (when pfen = 1) when bit 7 (adcs1) of the a/d converter mode register (adm1) and bit 7 (pfen) of the power- fail compare mode register (pfm) are set to 1, a/d conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ads1) starts. upon the end of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr1), compared with the value of the power-fail compare threshold value register (pft), the intad is generated under the condition specified by the pfcm flag of the pfm register. caution: when executing power-fail comparison, the interrupt request signal (intad) is not generated on completion of the first conversion after adcs1 has been set to 1. intad is valid from completion of the second conversion.
195 pd1615, pd16f15, pd1616 figure 11-9: a/d conversion remarks: 1. n = 0, 1, ..., 7 2. m = 0, 1, ..., 7 adm1 rewrite adcs1 = 1 ads1 rewrite adcs1 = 0 a/d conversion adcr1 intad (pfen = 0) intad (pfen = 1) anin anin anin anim anim stop anin anin anim conversion suspended; conversion results are not stored first conversion condition satisfied
196 pd1615, pd16f15, pd1616 11.5 a/d converter precautions (1) current consumption in standby mode a/d converter stops operating in the standby mode. at this time, current consumption can be reduced by setting bit 7 (adcs1) of the a/d converter mode register (adm1) to 0 to stop conversion. figure 11-10 shows how to reduce the current consumption in the standby mode. figure 11-10: example method of reducing current consumption in standby mode (2) input range of ani0 to ani3 the input voltages of ani0 to ani3 should be within the specification range. in particular, if a voltage higher than av dd /av ref or lower than av ss is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) contending operations <1> contention between a/d conversion result register (adcr1) write and adcr1 read by instruction upon the end of conversion adcr1 read is given priority. after the read operation, the new conversion result is written to adcr1. <2> contention between adcr1 write and a/d converter mode register (adm1) write or analog input channel specification register (ads1) write upon the end of conversion adm1 or ads1 write is given priority. adcr1 write is not performed, nor is the conversion end interrupt request signal (intad) generated. a v dd av ss p-ch series resistor string adcs1 av ref av dd ad-converter power supply av ref /
197 pd1615, pd16f15, pd1616 (4) noise countermeasures to maintain 8-bit resolution, attention must be paid to noise input to pin av dd /av ref and pins ani0 to ani3. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in the figure 11-11 to reduce noise. figure 11-11: analog input pin handling (5) ani0 to ani3 the analog input pins (ani0 to ani3) also function as input port pins (p10 to p13). when a/d conversion is performed with any of pins ani0 to ani3 selected, do not execute a port input instruction while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (6) av dd /av ref pin input impedance a series resistor string of approximately 21 k w is connected between the av dd /av ref pin and the av ss pin. therefore, if the output impedance of the reference voltage is high, this will result in parallel connection to the series resistor string between the av dd pin and the av ss pin, and there will be a large reference voltage error. reference voltage input c = 100 to 1000 pf if there is a possibility that noise equal to or higher than av dd /a v ref or equal to or lower than av ss may enter, clamp with a diode with a small v f v alue (0.3 v or lower). av dd av ss v ss ani0 to ani3 analog power supply and av ref /
198 pd1615, pd16f15, pd1616 (7) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the analog input channel specification register (ads1) is changed. caution is therefore required if a change of analog input pin is performed during a/d conversion. the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads1 rewrite, if the adif is read immediately after the ads1 rewrite, the adif may be set despite to the fact that the a/d conversion for the post-change analog input has not ended. when the a/d conversion is stopped and then resumed, clear adif before the a/d conversion operation is resumed. figure 11-12: a/d conversion end interrupt request generation timing remarks: 1. n = 0, 1, ..., 7 2. m = 0, 1, ..., 7 (8) read of a/d conversion result register (adcr1) when a write operation is executed to a/d converter mode register (adm1) and analog input channel specification register (ads1), the contents of adcr1 are undefined. read the conversion result before write operation is executed to adm1, ads1. if a timing other than the above is used, the correct conversion result may not be read. ads1 rewrite (start of anin conversion) a/d conversion adcr1 intad anin anin anim anim anin anin anim anim ads1 rewrite (start of anim conversion) adif is set but anim conversion has not ended.
199 pd1615, pd16f15, pd1616 11.6 cautions on emulation to perform debugging with an in-circuit emulator (ie-78001-r-a), the d/a converter mode register (dam0) must be set. dam0 is a register used to set the i/o board (ie-78k0-ns-p04). 11.6.1 d/a converter mode register (dam0) dam0 is necessary if the power-fail detection function is used. unless dam0 is set, the power-fail detection function cannot be used. dam0 is a write-only register. because the ie-78k0-ns-p04 uses an external analog comparator and a d/a converter to implement part of the power-fail detection function, the reference voltage must be controlled. therefore, set bit 0 (dace) of dam0 to 1 when using the power-fail detection function. figure 11-13: d/a converter mode register (dam0) format cautions: 1. dam0 is a special register that must be set when debugging is performed with an in-circuit emulator. even if this register is used, the operation of the pd1615 subseries is not affected. however, delete the instruction that manipulates this register from the program at the final stage of debugging. 2. bits 7 to 1 must be set to 0. dace reference voltage control 0 disabled 1 enabled (when power-fail detection function is used) symbol76543210addressafter resetr/w dam00000000daceff84h00hw
200 pd1615, pd16f15, pd1616 [memo]
201 pd1615, pd16f15, pd1616 chapter 12 serial interface outline 12.1 serial interface outline the pd1615 subseries incorporates two channels of serial interfaces. table 12-1: differences between the serial interface channels remark: : provided : not provided serial transfer mode pd1615 pd16f15 pd1616 sio 30 (3-wire serial i/o) ??? uart ???
202 pd1615, pd16f15, pd1616 [memo]
203 pd1615, pd16f15, pd1616 chapter 13 serial interface sio30 13.1 serial interface channel 30 functions the sio30 has the following two modes. ? operation stop mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used if serial transfer is not performed. for details, see 15.5.1 operation stop mode . (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck3), serial output line (so3), and serial input line (si3). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit in the 8-bit data in serial transfers is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clock-synchronous serial interface, like a display controller, etc. for details see 13.5.2 three-wire serial i/o mode . figure 13-1 shows a block diagram of the sio30. figure 13-1: block diagram of sio30 internal bus 8 8 direction control circuit serial clock control circuit serial clock counter interruption request signal generator selector serial i/o shift register 30 (sio30) si3/p127/s0 so3/p126/s1 sck3/p125/s2 intcsi3 f x /2 2 f x /2 4 tm50 csie30 mode0 scl301 scl300
204 pd1615, pd16f15, pd1616 13.2 serial interface channel 30 configuration the sio30 includes the following hardware. table 13-1: composition of sio30 item configuration registers serial i/o shift register 30 (sio30) control registers serial operation mode register 30 (csim30) (1) serial i/o shift register 30 (sio30) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. sio30 is set by an 8-bit memory manipulation instruction. when 1 is set to bit 7 (csie30) of the serial operation mode register 30 (csim30), a serial operation can be started by writing data to or reading data from sio30. when transmitting, data written to sio30 is output via the serial output (so3). when receiving, data is read from the serial input (si3) and written to sio30. the reset signal resets the register value to 00h. caution: do not access sio30 during a transmit operation unless the access is triggered by a transfer start. (read is disabled when mode = 0 and write is disabled when mode = 1.) 13.3 list of sfrs (special function registers) table 13-2: list of sfrs (special function registers) sfr name symbol r/w units available for bit manipulation value when reset 1 bit 8 bits 16 bits serial operation mode register 30 csim30 r/w 00h serial i/o shift register 30 sio30
205 pd1615, pd16f15, pd1616 13.4 serial interface control registers the sio3 uses the following type of register for control functions. ? serial operation mode register 30 (csim30) (1) serial operation mode register 30 (csim30) this register is used to enable or disable sio30s serial clock, operation modes, and specific operations. csim30 can be set via a 1-bit or 8-bit memory manipulation instruction. the reset input sets the value to 00h. figure 13-2: format of serial operation mode register 30 (csim30) address: ff6fh when reset: 00h r/w symbol 76543210 csim30 csie30 0 0 0 0 mode0 scl301 scl300 csie30 enable/disable specification for sio30 shift register operation serial counter port note 1 0 operation stop clear port function 1 operation enable count operation enable serial operation + port function mode0 transfer operation modes and flags operation mode transfer start trigger p126/so3/sa 0 transmit/receive mode write to sio30 so3 output 1 receive-only mode note 2 read from sio30 port function scl301 scl300 clock selection 0 0 external clock input 0 1 fx/2 2 1 0 fx/2 4 1 1 tm50 output notes: 1. when csie30 = 0 (sio30 operation stop status), the pins connected to si3 and so3 can be used for port functions. 2. when mode0 = 1 (receive mode), pin p126/so3/s1 can be used for port function. caution: if tm50 is used as clock generation for sio30, no clock will be supplied to sio30 unless toe50 is set to 1. in this case a square wave output signal is output from the to50 pin.
206 pd1615, pd16f15, pd1616 13.5 serial interface operations this section explains on two modes of sio30. 13.5.1 operation stop mode this mode is used if the serial transfers are not performed to reduce power consumption. during the operation stop mode, the pins can be used as normal i/o ports as well. (1) register settings the operation stop mode can be set via the serial operation mode register 30 (csim30). csim30 can be set via 1-bit or 8-bit memory manipulation instructions. the reset input sets the value to 00h. figure 13-3: format of serial operation mode register 30 (csim30) address: ff6fh when reset: 00h r/w symbol 76543210 csim30 csie30 0 0 0 0 mode0 scl301 scl300 csie30 sio30 operation enable/disable specification shift register operation serial counter port note 0 operation stop clear port function 1 operation enable count operation enable serial operation + port function note: when csie30 = 0 (sio30 operation stop status), the pins connected to si3 and so3 can be used for port functions.
207 pd1615, pd16f15, pd1616 13.5.2 three-wire serial i/o mode the three-wire serial i/o mode is useful when connecting a peripheral i/o device that includes a clock- synchronous serial interface, a display controller, etc. this mode executes the data transfer via three lines: a serial clock line (sck3), serial output line (so3), and serial input line (si3). (1) register settings the 3-wire serial i/o mode is set via serial operation mode register 30 (csim30). csim30 can be set via 1-bit or 8-bit memory manipulation instructions. the reset input set the value to 00h . figure 13-4: format of serial operation mode register 30 (csim30) address: ff6fh when reset: 00h r/w symbol 76543210 csim30 csie30 0000mode0 scl301 scl300 csie30 enable/disable specification for sio30 shift register operation serial counter port note 1 0 operation stop clear port function 1 operation enable count operation enable serial operation + port function mode0 transfer operation modes and flags operation mode transfer start trigger p126/so3/s1 0 transmit/receive mode write to sio30 so3 output 1 receive-only mode note 2 read from sio30 port function scl301 scl300 clock selection (f x = 8.00 mhz) 0 0 external clock input 0 1 fx/2 2 1 0 fx/2 4 1 1 tm50 output note: 1. when csie30 = 0 (sio30 operation stop status), the pins connected to si3 and so3 can be used for port functions. 2. when m0de0 = 1 (receive mode), pin p126/so3/s1 can be used for port function. caution: if tm50 is used as clock generation for sio30, no clock will be supplied to sio30 unless toe50 is set to 1. in this case a square wave output signal is output from the to50 pin.
208 pd1615, pd16f15, pd1616 (2) communication operations in the three-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is sent or received synchronized with the serial clock. the serial i/o shift register 30 (sio30) is shifted synchronized with the falling edge of the serial clock. the transmission data is held in the so3 latch and is output from the so3 pin. the data is received via the si30 pin synchronized with the rising edge of the serial clock is latched to sio30. the completion of an 8-bit transfer automatically stops operation of sio30 and sets a serial transfer completion flag. figure 13-5: timing of three-wire serial i/o mode (3) transfer start a serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial i/o shift register 30 (sio30). ? the sio30 operation control bit (csie30) = 1 ? after an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. ? transmit/receive mode when csie30 = 1 and mode0 = 0, transfer starts when writing to sio30. ? receive-only mode when csie30 = 1 and mode0 = 1, transfer starts when reading from sio30. caution: after the data has been written to sio30, the transfer will not start even if the csie30 bit value is set to 1. the completion of an 8-bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag. si3 di7 di6 di5 di4 di3 di2 di1 di0 serial transfer completion flag serial clock 1 so3 do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronized with the serial clocks falling edge
209 pd1615, pd16f15, pd1616 [memo]
210 pd1615, pd16f15, pd1616 chapter 14 serial interface uart 14.1 serial interface uart functions the serial interface uart has the following two modes. (1) operation stop mode this mode is used if the serial transfer is performed to reduce power consumption. for details, see 14.5.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode enables the full-duplex operation where one byte of data is transmitted and received after the start bit. the on-chip dedicated uart baud rate generator enables communications using a wide range of selectable baud rates. for details, see 14.5.2 asynchronous serial interface (uart) mode . figure 14-1 shows a block diagram of the uart macro. figure 14-1: block diagram of uart internal bus receive buffer rxb0 rxd0/p123/s4 txd0/p124/s3 receive shift register pe0 fe0 ove0 asis0 txs0 intser intst baud rate generator f x /2 - f x /2 8 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 asim0 intsr receive control parity check transmit shift register transmit control parity addition rxs0
211 pd1615, pd16f15, pd1616 14.2 serial interface uart configuration the uart includes the following hardware. table 14-1: configuration of uart item configuration registers transmit shift register 1 (txs0) receive shift register 1 (rxs0) receive buffer register (rxb0) control registers asynchronous serial interface mode register (asim0) asynchronous serial interface status register (asis0) baud rate generator control register (brgc0) (1) transmit shift register 1 (txs0) this register is for setting the transmit data. the data is written to txs0 for transmission as serial data. when the data length is set as 7 bits, bits 0 to 6 of the data written to txs0 are transmitted as serial data. writing data to txs0 starts the transmit operation. txs0 can be written via 8-bit memory manipulation instructions. it cannot be read. when reset is input, its value is ffh. caution: do not write to txs0 during a transmit operation. the same address is assigned to txs0 and the receive buffer register (rxb0). a read operation reads values from rxb0. (2) receive shift register 1 (rxs0) this register converts serial data input via the rxd pin to parallel data. when one byte of the data is received at this register, the receive data is transferred to the receive buffer register (rxb0). rxs0 cannot be manipulated directly by a program. (3) receive buffer register (rxb0) this register is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred from the receive shift register (rxs0). when the data length is set as 7 bits, receive data is sent to bits 0 to 6 of rxb0. the msb must be set to 0 in rxb0. rxb0 can be read to via 8-bit memory manipulation instructions. it cannot be written to. when reset is input, its value is ffh. caution: the same address is assigned to rxb0 and the transmit shift register (txs0). during a write operation, values are written to txs0. (4) transmission control circuit the transmission control circuit controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to the transmit shift register (txs0), based on the values set to the asynchronous serial interface mode register (asim0). (5) reception control circuit the reception control circuit controls the receive operations based on the values set to the asynchronous serial interface mode register (asim0). during a receive operation, it performs error checking, such as parity errors, and sets various values to the asynchronous serial interface status register (asis0) according to the type of error that is detected.
212 pd1615, pd16f15, pd1616 14.4 serial interface control registers the uart uses the following three types of registers for control functions. ? asynchronous serial interface mode register (asim0) ? asynchronous serial interface status register (asis0) ? baud rate generator control register (brgc0) (1) asynchronous serial interface mode register (asim0) this is an 8-bit register that controls the uart serial transfer operation. asim0 can be set by 1-bit or 8-bit memory manipulation instructions. reset input sets the value to 00h. figure 14-2 shows the format of asim0. 14.3 list of sfrs (special function registers) table 14-2: list of sfrs (special function registers) units available for bit manipulation sfr name symbol r/w 1 bit 8 bits 16 bits value when reset transmit shift register txs0 w receive buffer register rxb0 r ffh asynchronous serial interface mode register asim0 r/w asynchronous serial interface status register asis0 w baud rate generator control register brgc 0 r/w 00h
213 pd1615, pd16f15, pd1616 figure 14-2: format of asynchronous serial interface mode register (asim0) address: ffa0h when reset: 00h r/w symbol 76543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 txe0 rxe0 operation mode rxd0/p123/s4pin function txd0/p124/s3pin function 0 0 operation stop port function port function 0 1 uart0 mode serial operation port function (receive only) 1 0 uart0 mode port function serial operation (transmit only) 1 1 uart0 mode serial operation serial operation (transmit and receive) ps01 ps00 parity bit specification 0 0 no parity 0 1 zero parity always added during transmittion no parity detection during reception (parity errors do not occur) 1 0 odd aprity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits sl0 stop bit length specification for transmit data 0 1 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs caution: do not switch the operation mode until after the current serial transmit/receive operation has stopped.
214 pd1615, pd16f15, pd1616 (2) asynchronous serial interface status register (asis0) when a receive error occurs during uart mode, this register indicates the type of error. asis0 can be read using an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 14-3: format of asynchronous serial interface status register (asis0) address: ffa1h when reset: 00h r symbol 76543210 asis0 00000pe0fe0 ove0 pe0 parity error flag 0 no parity error 0 parity error (incorrect parity bit detected) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes: 1. even if a stop bit length of two bits has been set to bit 2 (sl0) in the asynchronous serial interface mode register (asim0), the stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register (rxb0) when an overrun error has occurred. until the contents of rxb0 are read, further overrun errors will occur when receiving data. (3) baud rate generator control register (brgc0) this register sets the serial clock for uart. brgc can be set via an 8-bit memory manipulation instruction. when reset is input, its value is 00h. figure 14-4 shows the format of brgc0.
215 pd1615, pd16f15, pd1616 figure 14-4: format of baud rate generator control register (brgc0) address: ffa2h when reset: 00h r/w symbol 76543210 brgc0 0 tps02 tps01 tps00 m dl03 mdl02 mdl01 mdl00 (f x = 8.00 mhz) tps02 tps01 tps00 source clock selection for 5-bit counter n 000f x /2 1 1 001f x /2 2 2 010f x /2 3 3 011f x /2 4 4 100f x /2 5 5 101f x /2 6 6 110f x /2 7 7 111f x /2 8 8 mdl03 mdl02 mdl01 mdl00 input clock selection for baud rate generator k 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibit caution: writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc0 during a communication operation. remarks: 1. f sck : source clock for 5-bit counter 2. n: value set via tps00 to tps02 (1 n 8) 3. k: value set via mdl00 to mdl03 (0 k 14)
216 pd1615, pd16f15, pd1616 14.5 serial interface operations this section explains the three modes of the uart. 14.5.1 operation stop mode this mode is used when serial transfers are not performed to reduce power consumption. in the operation stop mode, pins can be used as ordinary ports. (1) register settings operation stop mode settings are made via the asynchronous serial interface mode register (asim0). asim0 can be set via 1-bit or 8-bit memory manipulation instructions. when reset is input, its value is 00h. address: ffa0h when reset: 00h r/w symbol 76543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 txe0 rxe0 operation mode rxd0/p123/s4pin functiontxd0/p124/s3pin function 0 0 operation stop port function port function 0 1 uart0 mode serial operation port function (receive only) 1 0 uart0 mode port function serial operation (transmit only) 1 1 uart0 mode serial operation serial operation (transmit and receive) caution: do not switch the operation mode until after the current serial transmit/receive operation has stopped. 14.5.2 asynchronous serial interface (uart) mode this mode enables full-duplex operation where one byte of the data is transmitted or received after the start bit. the on-chip dedicated uart baud rate generator enables communications by using a wide range of selectable baud rates. (1) register settings the uart mode settings are made via the asynchronous serial interface mode register (asim0), asynchronous serial interface status register (asis0), and the baud rate generator control register (brgc0). figure 14-5: register settings
217 pd1615, pd16f15, pd1616 (a) asynchronous serial interface mode register (asim0) asim0 can be set by 1-bit or 8-bit memory manipulation instructions. when reset is input, its value is 00h. address: ffa0h when reset: 00h r/w symbol 76543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 0 txe0 pex0 operation mode rxd0/p123/s4pin function txd0/p124/s3pin function 0 0 operation stop port function port function 0 1 uart0 mode serial operation port function (receive only) 1 0 uart0 mode port function serial operation (transmit only) 1 1 uart0 mode serial operation serial operation (transmit and receive) ps01 ps00 parity bit specification 0 0 no parity 0 1 zero parity always added during transmittion no parity detection during reception (parity errors do not occur) 1 0 odd aprity 1 1 even parity cl0 character length specification 0 7 bits 0 8 bits sl0 stop bit length specification for transmit data 0 1 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt is issued when an error occurs 1 receive completion interrupt is not issued when an error occurs caution: do not switch the operation mode until after the current serial transmit/receive operation has stopped. figure 14-6: asynchronous serial interface mode register (asim0)
218 pd1615, pd16f15, pd1616 (b) asynchronous serial interface status register (asis0) asis0 can be read using an 8-bit memory manipulation instruction. when reset is input, its value is 00h. address: ffa1h when reset: 00h r symbol 76543210 asis000000pe0fe0 ove0 pe0 parity error flag 0 no parity error 1 parity error (incorrect parity bit detected) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register) notes: 1. even if a stop bit length of two bits has been set to bit 2 (sl0) in the asynchronous serial interface mode register (asim0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. be sure to read the contents of the receive buffer register (rxb0) when an overrun error has occurred. until the contents of rxb0 are read, further overrun errors will occur when receiving data. figure 14-7: asynchronous serial interface status register (asis0)
219 pd1615, pd16f15, pd1616 (c) baud rate generator control register (brgc0) brgc0 can be set by an 8-bit memory manipulation instruction. when reset is input, its value is 00h. address: ffa2h when reset: 00h r/w symbol 76543210 brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 (f x = 8.00 mhz) tps02 tps01 tps00 source clock selection for 5-bit counter n 000f x /2 1 1 001f x /2 2 2 010f x /2 3 3 011f x /2 4 4 100f x /2 5 5 101f x /2 6 6 110f x /2 7 7 111f x /2 8 8 mdl03 mdl02 mdl01 mdl00 input clock selection for baud rate generator k 0000f sck /16 0 0001f sck /17 1 0010f sck /18 2 0011f sck /19 3 0100f sck /20 4 0101f sck /21 5 0110f sck /22 6 0111f sck /23 7 1000f sck /24 8 1001f sck /25 9 1010f sck /26 10 1011f sck /27 11 1100f sck /28 12 1101f sck /29 13 1110f sck /30 14 1111 setting prohibit caution: writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. there- fore, do not write to brgc0 during a communication operation. remarks: 1. f sck : source clock for 5-bit counter 2. n: value set via tps00 to tps02 (1 n 8) 3. k: value set via mdl00 to mdl03 (0 k 14) figure 14-8: baud rate generator control register (brgc0)
220 pd1615, pd16f15, pd1616 the transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. ? use of main system clock to generate a transmit/receive clock for baud rate the main system clock is divided to generate the transmit/receive clock. the baud rate generated by the main system clock is determined according to the following formula. [baud rate] = f x [bps] 2 n+1 (k + 16) f x : oscillation frequency of main system clock (in hz) n : value set via tps00 to tps02 (1 n 8) for details, see table 17-3. k : value set via mdl00 to mdl02 (0 k 14) table 17-3 shows the relation between the 5-bit counters source clock assigned to bits 4 to 6 (tps00 to tps02) of brgc0 and the n value in the above formula. table 14-3: relation between 5-bit counters source clock and n value tps02 tps01 tps00 5-bit counters source clock selected n 000f x /2 1 1 001f x /2 2 2 010f x /2 3 3 011f x /2 4 4 100f x /2 5 5 101f x /2 6 6 110f x /2 7 7 111f x /2 8 8 remark: f x : oscillation frequency of main system clock.
221 pd1615, pd16f15, pd1616 ? error tolerance range for baud rates the tolerance range for baud rates depends on the number of bits per frame and the counters division rate [1/(16 + k)]. table 14-4 describes the relation between the main system clock and the baud rate and figure 14-9 shows an example of a baud rate error tolerance range. table 14-4: relation between main system clock and baud rate fx = 8.000 mhz fx = 4.000 mhz baud rate (bps) brgc0 err(%) brgc0 err(%) 600 7ah 0.16 6ah 0.16 1200 6ah 0.16 5ah 0.16 2400 5ah 0.16 4ah 0.16 4800 4ah 0.16 3ah 0.16 9600 3ah 0.16 2ah 0.16 19200 2ah 0.00 1ah 0.00 38400 1ah 0.16 0ah 0.16 76800 0ah 0.16 CC 115200 02h 0.16 CC remarks: 1. f x : oscillation frequency of main system clock 2. n: value set via tps00 to tps02 (1 n 8) 3. k: value set via mdl00 to mdl03 (0 k 14)
222 pd1615, pd16f15, pd1616 figure 14-9: error tolerance (when k = 0), including sampling errors remark: t: 5-bit counters source clock cycle baud rate error tolerance (when k = 0) = 15.5 x 100 = 4.8438 (%) 320 basic timing (clock cycle t) start d0 d7 p stop high-speed clock (clock cycle t) enabling normal reception start d0 d7 p stop low-speed clock (clock cycle t) enabling normal reception start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t
223 pd1615, pd16f15, pd1616 (2) communication operations (a) data format as shown in figure 14-10, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. the asynchronous serial interface mode register (asim0) is used to set the character bit length, parity selection, and stop bit length within each data frame. figure 14-10: format of transmit/receive data in asynchronous serial interface ? start bit ............. 1 bit ? character bits ... 7 bits or 8 bits ? parity bit ........... even parity, odd parity, zero parity, or no parity ? stop bit(s) ........ 1 bit or 2 bits when 7 bits is selected as the number of character bits, only the low-order 7 bits (bits 0 to 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to 0. the asynchronous serial interface mode register (asim0) and the baud rate generator control register (brgc0) are used to set the serial transfer rate. if a receive error occurs, information about the receive error can be recognized by reading the asynchronous serial interface status register (asis0). d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame
224 pd1615, pd16f15, pd1616 (b) parity types and operations the parity bit is used to detect bit errors in transfer data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. when zero parity or no parity is set, errors are not detected. (1)even parity ? during transmission the number of bits in transmit data that includes a parity bit is controlled so that there are an even number of 1 bits. the value of the parity bit is as follows. if the transmit data contains an odd number of 1 bits : the parity bit value is 1 if the transmit data contains an even number of 1 bits: the parity bit value is 0 ? during reception the number of 1 bits is counted among the transfer data that include a parity bit, and a parity error occurs when the result is an odd number. (2)odd parity ? during transmission the number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of 1 bits. the value of the parity bit is as follows. if the transmit data contains an odd number of 1 bits : the parity bit value is 0 if the transmit data contains an even number of 1 bits: the parity bit value is 1 ? during reception the number of 1 bits is counted among the transfer data that include a parity bit, and a parity error occurs when the result is an even number. (3)zero parity during transmission, the parity bit is set to 0 regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will occur regardless of whether the parity bit is a 0 or a 1. (4)no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will occur.
225 pd1615, pd16f15, pd1616 (c) transmission the transmit operation is started when transmit data is written to the transmit shift register (txs0). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting the transmit operation shifts out the data in txs0, thereby emptying txs0, after which a transmit completion interrupt (intst) is issued. the timing of the transmit completion interrupt is shown in figure 14-11. figure 14-11: timing of asynchronous serial interface transmit completion interrupt caution: do not write to the asynchronous serial interface mode register (asim0) during a transmit operation. writing to asim0 during a transmit operation may disable further transmit operations (in such cases, enter a reset to restore normal operation). whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt (intst) or the interrupt request flag (stif) that is set by intst. txd0 (output) d0 d1 d2 d6 d7 parity stop start intst (i) stop bit length: 1 bit txd0 (output) d0 d1 d2 d6 d7 parity start intst (ii) stop bit length: 2 bits stop
226 pd1615, pd16f15, pd1616 (d) reception the receive operation is enabled when 1 is set to bit 6 (rxe0) of the asynchronous serial interface mode register (asim0), and input data via rxd pin is sampled. the serial clock specified by asim0 is used when sampling the rxd0 pin. when the rxd0 pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling is output if half of the specified baud rate time has elapsed. if the sampling of the rxd0 pin input of this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. after the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once the reception of one data frame is completed, the receive data in the shift register is transferred to the receive buffer register (rxb0) and a receive completion interrupt (intsr) occurs. even if an error has occurred, the receive data in which the error occurred is still transferred to rxb0 and intsr occurs (see figure 14-9). if the rxe0 bit is reset (to 0) during a receive operation, the receive operation is stopped immediately. at this time, neither the contents of rxb0 and asis0 do not change, nor does intsr or intser occur. figure 14-12 shows the timing of the asynchronous serial interface receive completion interrupt. figure 14-12: timing of asynchronous serial interface receive completion interrupt caution: be sure to read the contents of the receive buffer register (rxb0) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read. rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr
227 pd1615, pd16f15, pd1616 (e) receive errors three types of errors can occur during a receive operation: parity error, framing error, or overrun error. if, as the result of the data reception, an error flag is set to the asynchronous serial interface status register (asis0), a receive error interrupt (intser) will occur. receive error interrupts are generated before receive interrupts (intsr). table 17-5 lists the causes behind receive errors. as part of receive error interrupt (intser) servicing, the contents of asis0 can be read to determine which type of error occurred during the receive operation (see table 14-5 and figure 14-13). the content of asis0 is reset (to 0) if the receive buffer register (rxb0) is read or when the next data is received (if the next data contains an error, another error flag will be set). table 14-5: causes of receive errors receive error cause asis0 value parity error parity specified during transmission does not match parity of receive data 04h framing error stop bit was not detected 02h overrun error reception of the next data was completed before data was read from the 01h receive buffer register figure 14-13: receive error timing cautions: 1. the contents of asis0 are reset (to 0) when the receive buffer register (rxb0) is read or when the next data is received. to obtain information about the error, be sure to read the contents of asis0 before reading rxb0. 2. be sure to read the contents of the receive buffer register (rxb0) even when a receive error has occurred. overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read. rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr intser intser (when parity error occurs)
228 pd1615, pd16f15, pd1616 14.6 standby function serial transfer operations can be performed during halt mode. during stop mode, serial transfer operations are stopped and the values in the asynchronous serial interface mode register (asim0), transmit shift register (txs0), receive shift register (rxs0), and receive buffer register (rxb0) remain as they were just before the clock was stopped. output from the txd0 pin retains the immediately previous data if the clock is stopped (if the system enters stop mode) during a transmit operation. if the clock is stopped during a receive operation, the data received before the clock was stopped is retained and all subsequent operations are stopped. the receive operation can be restarted once the clock is restarted.
229 pd1615, pd16f15, pd1616 [memo]
230 pd1615, pd16f15, pd1616 chapter 15 van controller 15.1 features - the van uart is compatible with the iso 11519 van standard, part 3, revision 4.00. - the van uart executes all the van frame types: * programmed in autonomous mode (rank bit = 0), it performs the transmission and reception of data frames (transmits from the sof field or from the iden field) and read frames as well as the in frame response. * programmed in synchronous mode (rank bit = 1), it performs the transmission (transmits from the iden field only) and reception of data and read frames as well as the in frame response. - the transmission and reception of these frames can be done up to 500 kts/s for an 8 mhz quartz clock. - the van frame is encoded in enhanced manchester. - in autonomous mode the choice of the bus speed is programmable via a 4 bit prescaler (diag_ctrl_reg register). a bit of this prescaler performing a division by 1,2,3 or 5 permits the use of non binary quartz clocks having a frequency of 3, 5 or 6 mhz. - the van uart carries out the collision detection and goes into receive mode if lost arbitration before the end of the current time slot (ts). the circuit generates an interrupt if required by the user. the collision is not considered as an error. - the van uart re-synchronises the transmission and reception clocks at each edge detected on the bus line. - the van uart incorporates a cell calculating the crc in transmission and in reception. - the van uart integrates the line diagnosis function, which consists of: * the digital filtering of the outputs of the three comparators rxd0, rxd1 and rxd2. * asynchronous diagnosis. * synchronous diagnosis. * transmission diagnosis (with enable bit). * protocol error (8 consecutive dominant ts). * possibility to force one of the three comparators. - the van uart signals the errors that occurred on the van bus and generate an interrupt con- nected to each error if required by the user. 3 bits implanted in the status register stat_reg differentiate the errors in transmission or in reception.
231 pd1615, pd16f15, pd1616 15.2 overview of the van bus 15.2.1 van uart description the van uart cell integrated in this microcontroller is comform to the van standard (iso 11519, part 3, rev 4.00). 15.2.2 van uart interface figure 15-1: van uart interface the van uart is realised with one transmit register and one receive register. the application software may check the status registers in order to get information of the bus state and the re- ceived or transmitted messages. the device has the capability to generate an interrupt as soon as one byte is transmitted or received. care has to be taken when transmitting or receiving in order not to miss the tbe (int1) or rda (int2) interrupts occuring on every byte (tbe means transmit buffer empty and rda means received data available). at each of these interrupts, the application software has to perform a data exchange between the application and the tx/rx register. internal bus udlcken 0 0 0 0 0 0 0 udlccl register udlccl reset x1 bus bridge block wdt interrupt control chip reset status clk reset van-uart txvan rx0van rx1van rx2van udl-i/f udl status data data
232 pd1615, pd16f15, pd1616 interface management logic (iml) : the iml executes the cpus transmission and reception commands and controls the data transfer between cpu, rx/tx and van registers. it provides the van uart interface with rx/tx data from the memory mapped register block. it sets and resets the van status informations and generates interrupts to the cpu. it also generates the bit clock according the divider chosen by application software. figure 15-2: van uart block diagram rko_reg ifr_reg ctrl_reg conf_reg diag_ctrl_reg van uart registers tx/rx shift register crc generator/checker bit time logic bit stream processor error management logic interface management logic diagnosis logic van core internal bus rx0van rx1van rx2van txvan
233 pd1615, pd16f15, pd1616 this divider divides the input clock by the value defined in the van prescaler. the following picture shows the generation of the van clock : the prescaler (ck0-ck3) is chosen in the diag_ctrl_reg register. van core : the van core incorporates two main state machines (transmission and reception) and controls the output driver txvan, the crc logic and the tx/rx shift register. it also controls the synchroniza- tion to the van bus (according to van specifications) by the bit time logic (btl). it also detects all the symbols included in a van frame like the start of frame (sof), the end of data (eod), the acknowledge (ack), the end of frame (eof) or the inter frame separation (ifs). it codes and decodes any van data according to the enhanced-manchester code. bit stream processor (bsp) : the bsp is a sequencer that controls the data stream between the iml (parallel data) and the van bus line (serial data). it controls the btl with regard to transmission, reception, arbitration and generates error signals according to the van bus specifications. error management logic (eml) : the eml is responsible for the fault confinement of the van protocol. it also sets and resets the error flag bits and interrupts and changes the error status bits in the status register. any error on the van bus line generates an interrupt if enabled by the application software (int0 interrupt). figure 15-3: generation of the van clock 1, 2, 3, 5 2 . . . . 2 . . ckco ck3 ck2 ck0 ck1 cpu's
234 pd1615, pd16f15, pd1616 cyclic redundancy check (crc) generator and checker : the crc generator consists of a 15-bit shift register and the logic required to generate the checksum of the bit-stream. it informs the eml about the result of a receiver checksum. the checksum is generated by the polynomial : g(x) = x 15 + x 11 + x 10 + x 9 + x 8 + x 7 + x 4 + x 3 + x 2 + 1 this logic performs the calculation of the crc in transmission and in reception. receive/transmit (rx/tx) register : the rx/tx register is a 8-bit shift register controlled by the van core. it is loaded or read by the iml which holds the data to be transmitted or the data that was received. bit time logic (btl) : the btl is responsible for counting the bits and the bytes. it also resynchronise the bits according to van specifications. diagnosis logic and output driver: the diagnosis logic is responsible to hold the communication whenever one of the two wires of the van bus line (data and /data) is short-circuited to ground or battery or is opened-circuit. it decides on which line rx0van, rx1van or rx2van, the van uart will continue to communicate. operating on the rxd0 line is named ?nominal or differential mode? because there is no default neither on the data line nor on the /data one. operating on the rx1van or rx2van line is named ?degraded mode? since there is a default on data or /data and it is no longer a differential communication. assuming the diagnosis logic decides to put the device in the ?degraded mode?, it can also put it back to the ?differential mode? when the problem on the data or /data has disapeared. van uart registers : the register block consists of 21 registers which are described in more details in the following paragraphs.
235 pd1615, pd16f15, pd1616 15.3 functional description 15.3.1 overview of the van uart registers figure 15-4: overview of the van uart registers rk0_reg f800h tx6 tx5 tx4 tx3 tx2 tx1 tx0 ifr_reg f801h ifr7 ifr6 ifr5 ifr4 ifr3 ifr2 ifr1 ifr0 ctrk_reg f802h 0 0 0 0 stop- tr ack- req last- byte soft- reset config_reg f803h 0 0 0 it12 rank ifr msk1 msk0 diag_ctrl_reg f804h ck3 ck2 ck1 ck0 diag- top enab_ emecb dia1 dia0 msk1_msg_reg f805h msk1_lsg_reg f806h 000 ac1_msg_reg f807h ac1_lsg_reg f808h 000 msk2_msg_reg f809h msk2_lsg_reg f80ah 000 ac2_msg_reg f80bh ac2_lsg_reg f80ch 000 ac3_msg_reg f80dh ac3_lsg_reg f80eh 000 ac4_msg_reg f80fh ac4_lsg_reg f810h 000 stat_reg f811h 0 la_ resp eom la ack err2 err1 err0 rec_reg f812h rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 diag_stat_reg f813h 0 0 0 0 0 sc sb sa int_enable_reg f820h gie rdae tbee fte fre lae eome 0
236 pd1615, pd16f15, pd1616 15.3.2 autonomous mode functions 15.3.2.1 autonomous mode features the user sets the van uart in autonomous mode by setting the rank bit to 0. the transmission clock is the quartz clock divided by the prescaler chosen by the user in the diag_ctrl_reg register. for example: to be able to detect the frames, whose speed is 250 kts/s, the minimum frequency of this quartz clock must be 4 mhz. the component executes all van frame types: * the transmission of data transmit (write) or data request (read) frames (sof included or rank 0) at any speed up to 500 kts/s (with an 8 mhz quartz) depending on the division ratio chosen in the diag_ctrl_reg register. * the reception of data frames at the same speeds depending on the programming of the prescaler. * the transmission of data transmit or data request frames from the address field (synchronisation on the start bit or rank 1) at any speed depending on the programming of the prescaler. * the transmission of in frame responses (or rank 16) at any speed depending on the programming of the prescaler. 15.3.2.2 programming of the prescaler in rank 0 transmission (sof included) programming of the prescaler permits rank 0 frames to be transmitted at different speeds without changing the quartz clock. for example: w hen an 8 mhz quartz clock supplies the uart, it is capable of sweeping the range 62,5 kts/s to 500 kts/s in rank 0 transmission. the prescaler is chosen using the diag_ctrl_reg register with the 4 bits ck3, ck2, ck1 and ck0. the 2 least significant bits ck1 and ck0 are used to program a divider by 1, 2, 3 or 5 whilst the 2 other bits are used to program a divider to a power of 2. figure 15-5: prescaler in rank 0 transmission 1, 2, 3, 5 2 . . . . 2 . . ckcor ck3 ck2 ck0 ck1 cpu's clock
237 pd1615, pd16f15, pd1616 table 15-1: network speeds as a function of the quartz clock and the chosen division ratio quartz (mhz) 1 2 3 4 5 6 8 div ratio network speed (kts) 0000 1 62.5 125 250 500 0001 2 31.25 62.5 125 250 0010 3 62.5 125 0011 5 62.5 0100 2 31.25 62.5 125 250 0101 4 15.625 31.25 62.5 125 0110 6 31.25 62.5 0111 10 31.25 1000 2 31.25 62.5 125 250 1001 4 15.625 31.25 62.5 125 1010 6 31.25 62.5 1011 10 31.25 1100 4 15.625 31.25 62.5 125 1101 8 7.81 15.625 31.25 62.5 1110 12 15.625 31.25 1111 20 15.625 15.3.2.3 transmission features in autonomous mode a transmit request is triggered by writing in the rank0 transmit register rk0_reg when the compo- nent is in receive or in idle (typically after an eom interrupt). a rank 0 transmission start by the transmission of the sof symbol following the detection of the eof symbol (8 recessive ts) followed by the ifs symbol (4 recessive ts). if these 12 recessive ts could not be detected on the network, the component then synchronises itself on the start bit seen on the bus. the transmission request is satisfied but transformed into rank 1 transmission. in the autonomous mode, the component performs also the in frame response (ifr). to do this, the bit ifr must be set to 1 in the ctrl_reg register. in addition, the component must be in reception on the r/w bit of the command field of the van frame (please note that this receive state can be due to a lost of arbitration during the first or the second identifier byte). the van uart compares the received identifier with one or more identifiers located in the msk (mask) and ac (acceptance code) registers and generates or not a received byte interrupt. then, the microcontroller accepts or refuses to respond in the frame (whether this identifier corresponds or not to an in frame response). writing of the first byte of the response in the ifr transmit register ifr_reg shows an acceptation. not writing shows a refusal.
238 pd1615, pd16f15, pd1616 15.3.3 synchronous mode functions 15.3.3.1 synchronous mode features the user sets the van uart in synchronous mode by setting the rank bit to 1 in the control register ctrl_reg. the transmission clock is the quartz clock divided by the prescaler chosen by the user in the diag_ctrl_reg register. for example: to be able to detect the frames, whose speed is 250 kts/s, the minimum frequency of this quartz clock must be 4 mhz. the component can no longer transmit rank 0 frames. however, it can receive data frames. it can transmit rank 1 frames (data frames and read frames synchronised on the start bit) and in frame responses. the range of speeds depends on the frequency of the quartz clock; at 8mhz, the range spreads from 62,5 kts/s to 500 kts/s. 15.3.3.2 transmission features in synchronous mode for rank 1 transmission, the transmit request is still triggered by writing in the rank0 transmit register rk0_reg when the component is in receive or in idle (typically after an eom interrupt). the transmission is triggered after the detection of a start bit. the transmission characteristic of an in frame response is identical to that mentioned in autonomous mode. 15.3.4 handling of a collision the uart automatically goes into reception during a lost arbitration after collision detection. this lost arbitration may be signalled either by interrupt, if it is enabled by the user (lae bit of the int_enable_reg register), or by reading the la bit in the status register stat_reg. 15.3.5 executing the crc 15.3.5.1 crc transmission the transmission of the crc is possible thanks to a crc module integrated in the uart. it is performed by the following way: the last-byte bit in the ctrl_reg register is set when there are no more bytes to transmit. the uart then automatically completes the frame by the two crc bytes followed by the eod symbol. in the case of a read frame, the last-byte bit should be set after the second identifier byte because if the requested node does not send its data, the uart will complete the frame by sending immediately the 2 crc bytes. therefore, such a frame does not contain any data. this case is described in detail further.
239 pd1615, pd16f15, pd1616 15.3.5.2 reception of the crc for high-speed applications, the uart incorporates a crc module, which compares the received crc with the calculated crc. this comparison is carried out in transmission and in reception, giving place, in the latter case, to the transmission of a possible acknowledge. 15.3.6 control of the acknowledge bit in reception, if the eod symbol has been detected and if the crc is correct, then if the ack-req bit is set to 1 in the ctrl_reg register before the end of the eod field, a positive acknowledge is transmitted. otherwise, the uart stays in reception, which is equivalent to a negative acknowl- edge. the acknowledge bit is decoded in transmission as in reception and its value is indicated in the stat_reg register by the ack bit. the microcontroller compares the value of the ack bit with the rak bit received (and memorised) in the command field of the van frame. 15.3.7 error control and interrupt control 15.3.7.1 error control 3 bits err2, err1 and err0 encode any error in transmission or in reception in the status register stat_reg. err2 err1 err0 type of error 0 0 0 no error : initialisation 0 0 1 physical violation 010not used 0 1 1 code violation in reception 100not used 1 0 1 crc error in reception 1 1 0 format error ( ack ) 111 transmission or reception lock up information on the error table: when the code violation received is 00 on the ts 8 and 9 of a byte, the error signalled is a crc error in reception as it is not possible to distinguish this violation from the eod symbol. any other code violation received is signalled by a code violation in reception. table 15-2: error table
240 pd1615, pd16f15, pd1616 15.3.7.2 interrupt control an error is signalled by an interrupt if the user defines it. any interrupt that would have been generated after the detection of an error is deleted. the interrupt sources are listed below: la_resp : lost arbitration in the rtr bit (response) eom : end of message la : lost arbitration ft : failed transmit (refer to err0, err1, err2 for status) fr : failed receive (refer to err0, err1, err2 for status) these sources generate the int0 interrupt. tbe : transmit buffer empty this source generates the int1 interrupt. rda : received data available this source generates the int2 interrupt. - eom interrupt the eom interrupt appears at the end of the acknowledgement field if no error has occurred in the frame. otherwise, it appears as soon as an error is detected. this permits, in particular to detect errors that could occur in the identification field and to synchronise on it. this interrupt is generated on int0. it can be disabled in the int_enable_reg register by the eome bit. it can also be masked by vemk bit in mkol register. - la interrupt the la interrupt appears at the end of the byte where the collision occurred even if the uart has automatically switched to the reception mode in the current time slot. this interrupt is also generated on int0. this interrupt is signalled in the reg-stat register by the la bit. it can be disabled in the int_enable_reg register by the lae bit. - la_resp interrupt the la_resp interrupt appears when the uart performs a read frame and when the collision occurred on the rtr bit. that means that response is in progress. the uart has automatically switched to the reception mode to receive that response. this interrupt is also generated on the int0 pin. this interrupt is signalled in the reg-stat register by the la_resp bit. it can be also disabled in the int_enable_reg register by the lae bit. - tbe interrupt the tbe interrupt appears at the start of the 9th ts of a new byte before the old rk0_reg or ifr_reg register has been loaded in the transmit/receive shift register. this interrupt is generated on int1. it can be disabled in the int_enable_reg register by the tbee bit. it can also be masked by vtmk bit in mkol register.
241 pd1615, pd16f15, pd1616 it signifies that a byte must be loaded into the rk0_reg or ifr_reg register, but can be ignored if the microcontroller has no more bytes to transmit. in this case, it sets the last-byte bit in the control register ctrl_reg for the transmission of the crc. - rda interrupt the rda interrupt appears at the start of the 9th ts of the current byte before the recep_reg register has been loaded by the transmit/receive shift register. this interrupt is generated on int2. it can be disabled in the int_enable_reg register by the bit rdae. it can also be masked by vrmk bit in mkol register. it signifies that the byte contained in the recep_reg register must be read. - case of an in frame response: the user can choose to perform or not the in frame response using the ifr bit in the control register ctrl_reg. if ifr = 0, the component cannot perform the in frame response. if ifr = 1, the component is able to respond in the frame under conditions (see the transmission characteristics of rank 16). the interrupts are generated following two manners: if it12 = 0, the interrupts are generated byte after byte. the comparison of the identifier field is made by uart. if it12 = 1, the interrupts are generated byte after byte except during the second byte of the identifier where one rda interrupt appears at the end of the 12th bit of the van identi fier field. this allows the microcontroller to make the comparison itself. in this case, the uart supplies the byte for the address comparison and helps the microcontroller to search for the byte to be transmitted in the in frame response 0 0 0 0 iden2 4 bits 4 bits after the rda interrupt at the 12th bit, so as to be able to add to an address to point on the table of bytes to be transmitted without needing to mask the 4 most significant bits of this byte. - ft interrupt the ft interrupt appears after a physical violation, a format error (acknowledge error in transmis- sion) or a transmission lock-up (when there is no write access to the transmission register or to the control register between the transmission of two consecutive bytes). in case of a transmission lock-up, the uart does not complete the frame with the two bytes of crc and stops just after the last byte loaded. the bits err2, err1 and err0 signal the error in the status register stat_reg. it is generated on int0. table 15-3: frame responce
242 pd1615, pd16f15, pd1616 it can be disabled in the int_enable_reg register by the fte bit. - fr interrupt the fr interrupt appears after a code violation, a crc error or a format error (acknowledgement error in reception) or a reception lock-up (when there is no read access to the reception register between the reception of two consecutive bytes). in case of a reception lock-up, the uart does not receive the rest of the frame and stops just after the last byte. the bits err2, err1 and err0 signal the error in the status register stat_reg. it is generated on int0. it can be disabled in the int_enable_reg register by the fre bit.
243 pd1615, pd16f15, pd1616 15.4 van uart registers the van uart consists of the following registers. table 15-4: van uart registers manipulatable bit unit address register name symbol after reset r/w 1bit 8bit 16bit f800h rank 0 register rk0_reg ffh r/w o o x f801h in frame transmit register ifr_reg ffh r/w o o x f802h control register ctrl_reg 00h r/w o o x f803h configuration register conf_reg 08h r/w o o x f804h diagnosis control register diag_ctrl_reg 17h r/w o o x f805h mask1 register msk1_msb_reg 00h r/w o o x f806h mask1 register msk1_lsb_reg 00h r/w o o x f807h acceptance code 1 ac1_msb_reg 00h r/w o o x f808h acceptance code 1 ac1_lsb_reg 00h r/w o o x f809h mask2 register msk2_msb_reg 00h r/w o o x f80ah mask2 register msk2_lsb_reg 00h r/w o o x f80bh acceptance code ac2_msb_reg 00h r/w o o x f80ch acceptance code ac2_lsb_reg 00h r/w o o x f80dh acceptance code ac3_msb_reg 00h r/w o o x f80eh acceptance code ac3_lsb_reg 00h r/w o o x f80fh acceptance code ac4_msb_reg 00h r/w o o x f810h acceptance code ac4_lsb_reg 00h r/w o o x f811h status register stat_reg 08h r o o x f812h receive register rec_reg ffh r o o x f813h diagnosis status register diag_stat_reg 00h r o o x f820h interrupt enable register int_enable_reg 00h r/w o o x
244 pd1615, pd16f15, pd1616 15.4.1 rank0 transmission register (rk0_reg) the rank0 transmission register is loaded by the microcontroller to trigger a transmit request. rk0_reg is set with a 1-bit or 8-bit manipulation instruction. reset input set this register to ffh. figure 15-6: rank0 transmission register format symbol 7 6 5 4 3 2 1 0 address after reset r/w rk0_reg tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 f800h ffh r/w it is also loaded each time the int1 interrupt is generated, except if the microcontroller has no more bytes to transmit. in this case, it sets, instead, the last-byte bit in the control register ctrl_reg. for a standard transmission (rank0 or rank1), the microcontroller has up to one byte duration to load this register. for the in frame response, it has up to one byte duration if the it12 bit is set to 0 or up to only 4 ts if the it12 bit is set to 1. the loading limit is 14/16 of the last ts of the byte. if this limit is no met, the component will detect a lock up error and will signal it. the transmission is done msb first (tx7 is transmitted first).
245 pd1615, pd16f15, pd1616 15.4.2 in frame response register (ifr_reg) the ifr transmit register is written when the user wish to transmit an in frame response (ifr). ifr_reg is set with a 1-bit or 8-bit manipulation instruction. reset input set this register to ffh. figure 15-7: frame responce register format symbol 7 6 5 4 3 2 1 0 address after reset r/w ifr_reg ifr7 ifr6 ifr5 ifr4 ifr3 ifr2 ifr1 ifr0 f801h ffh r/w the van uart will receive the identification field (12 bits), compares it with the acceptance codes and start the transmission by the 16th bit of the frame. this kind of transmission is named ?rank16 frame?. no ifr is transmitted if this register is not written. the application software should only write data bytes in this register (28 maximum) and not ad- dress bytes. these datas correspond to the datas to be answered in the ifr. this software must specify the last byte of data in the ctrl_reg register. the device will transmit an in frame response only if the identification field that was received on the van bus matches with one of the acceptance codes. every byte transmitted generates a int1 interrupt corresponding to the tbe status (transmit buffer empty) meaning that the ifr_reg register was loaded in the shift register. a writing in this register resets the internal tbe flag. - case of lost arbitration during the identification field of a rank0 frame the following picture shows an arbitration during the identification field of a rank0 frame. that means the van uart has first tried to transmit a rank0 frame. nevertherless , at the same moment, another van node is also communicating with a higher priority identification field. the van uart looses the arbitration and goes into the receive mode. it can happen that this frame was also a request frame for the van uart. in order to handle these cases, the application software has to write in both registers (rk0 and ifr) to prevent from this kind of arbitration. the van uart will then select automatically the right register. if a lost arbitration has occured, the ifr_reg is selected otherwise the rk0_reg is chosen.
246 pd1615, pd16f15, pd1616 figure 15-8: frame responce register function van uart other 5d 5d a 8f rtr=0 dat=33 in frame responce lost arbitration first byte received write rk0 and ifr registers with first data byte la int0 int1 int2
247 pd1615, pd16f15, pd1616 15.4.3 control register (ctrl_reg ) the control register is used to control the van uart during the transmisision or to initiate a reset. ctrl_reg is set with a 1-bit or 8-bit manipulation instruction. reset input set this register to 00h. figure 15-9: control register format symbol76543210address after reset r/w ctrl_reg 0 0 0 0 stop- tr ack- req last- byte soft- reset f802h 00h r/w note: the bits of this register are set only type bits. they are set by the application software and resetted automatically by the van uart. writing 0 in these bits will have no effect. stop-tr: stop transmit table 15-5: stop transmit stop-tr stop transmit 0 no influence 1 stop the transmission in progress it can be used in any type of transmission. ack-req: acknowledge request table 15-6: acknowledge request ack-req acknowledge request 0 no influence 1 transmit request of an acknowledge bit the microcontroller decodes the value of the rak bit (bit 2 of the 2nd byte of the frame). accord- ing to this value, it will choose to set the ack-req bit in the control register ctrl-reg or not. note that ack-req occupies the same position as rak in the byte.
248 pd1615, pd16f15, pd1616 figure 15-10: control register block diagram therefore, a mask with 04h of the 2nd byte needs to be made and written in the control register. figure 15-11: control register function the last limit for setting the ack-req is 13/16 of the 2nd ts of the eod symbol. following the results of the frame (identifier recognised and correct crc), the acknowledge bit may be transmitted. last-byte: table 15-7: last-byte last-byte last transmission byte 0 no influence 1 sign to the van uart that the current byte is the last one figure 15-12: last-byte 5 67 8 9 crc2 eod ack last limit 3 45 6 7 crc last limit 0 1 2 8 9 0 13/16 data or iden iden3 iden2 iden1 iden0 ext rak r/w rtr stop tr ack req last byte soft reset ctrl_reg of the uart byte 2 of the frame memorised in the microcontroller
249 pd1615, pd16f15, pd1616 the uart places the 2 crc bytes after it. this may occur during a write frame or a read frame: in the case of a write frame, the last byte of data is signalled after the last data is transmitted. in the case of a read frame, the last byte is signalled after loading the 2nd identifier. the last-byte bit must be activated, as, if the response is missing, the crc will be automatically set by the uart following the identifier n2. soft-reset: software reset table 15-8: software reset soft-reset soft reset 0 no influence 1 software reset with the initialisation of the van uart this bit should be used if a major problem is detected during the operation of the van uart, or if it is incorrectly used. the result is the same as a hardware reset. the van uart must be re- configured.
250 pd1615, pd16f15, pd1616 15.4.4 configuration register (conf_reg) the configuration register is used to configure the interrupt generation, the uart mode and response and the mask function. conf_reg is set with a 1-bit or 8-bit manipulation instruction. reset input set this register to 08h. symbol 7 6 5 4 3 2 1 0 address after reset r/w conf_reg 0 0 0 it12 rank ifr msk1 msk0 f803h 08h r/w it12: enable / disable interrupt on the 12th bit of the identifier field. figure 15-13: configuration register (conf_reg) format table 15-9: enable / disable interrupt on the 12th bit of the identifier field it12 interrupt on the 12 th bit of the identifier field 0 disables the interrupt on the 12th bit of the identifier field. the uart only supplies ?byte? interrupts during a frame. 1 enables the interrupt on the 12th bit of the identifier field. this allows the microcontroler to receive the whole identifier and to compare it if necessary. case where it12 = 0 figure 15-14: case where it12 = 0 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 iden1 iden2 + com sof int2 int1 reception ifr "byte" interrupts
251 pd1615, pd16f15, pd1616 case where it12 = 1 figure 15-15: case where it12 = 1 rank: rank 0 / rank 1 mode table 15-10: rank 0 / rank 1 mode rank van uart mode selection 0 van uart in autonomous mode 1 van uart in synchronous mode in autonomous mode, a quartz clock is compulsory for the generation of the sof symbol. the precision needed is +/-1%. remark: on initialisation, the uart is set in synchronous mode and disables the in frame response. ifr: enable / disable in frame response table 15-11: enable / disable in frame response ifr in frame response 0 disables the in frame response 1 enables the in frame response 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 iden1 iden2 + com sof int2 int1 reception ifr "byte" interrupts "nibble" interrupt to the third ts (i.e. to the 1st ts of the manchester bit) to gain one ts at the address comparison level. the uart supplies 0000iden2 to make the responce search easier
252 pd1615, pd16f15, pd1616 msk1, msk0: mask enable / disable table 15-12: mask enable / disable msk1 msk0 function 0 0 masks 1 and 2 activated (all identifiers filtered) 0 1 mask1 inhibited 1 0 mask2 inhibited 1 1 masks 1 and 2 inhibited (all identifiers accepted) msk1 and msk0 combinations allow enabling or disabling all or part of the mask mechanism applied on the identification field described further on.
253 pd1615, pd16f15, pd1616 15.4.5 diagnosis control register (diag_ctrl_reg) the diagnosis control register allows to configure the bus speed, the communication mode and diagnostic functions. diag_ctrl_reg is set with a 1-bit or 8-bit manipulation instruction. reset input set this register to 17h. symbol 7 6 5 4 3 2 1 0 address after reset r/w diag_ct rl_reg ck3 ck2 ck1 ck0 diag- top enab_e mecb dia1 dia0 f804h 17h r/w ck3, ck2, ck1 and ck0: prescaler. the prescaler is used to fix the division ratio between the quartz clock and the speed of the bus. this prescaler is defined in 4 bits. the least significant bits ck3 and ck2 are used to pre-divide by a ratio of 1,2,3 or 5. so, the uart can operate with quartz frequencies other than to the powers of 2. this pre-divider by 3 or 5 permits an operation at round speeds in terms of kbits/s or kts/s with non binary frequencies such as 3, 5, 6 mhz. figure 15-16: diagnosis control register (diag_ctrl_reg) format figure 15-17: prescaler block diagram 1, 2, 3, 5 2 . . . . 2 . . ckcor ck3 ck2 ck0 ck1 cpu's ck
254 pd1615, pd16f15, pd1616 table 15-13: prescaler - network speeds as a function of the quartz clock and the chosen division ratio quartz (mhz) 1 2 3 4 5 6 8 div ratio network speed (kts) 0000 1 62.5 125 250 500 0001 2 31.25 62.5 125 250 0010 3 62.5 125 0011 5 62.5 0100 2 31.25 62.5 125 250 0101 4 15.625 31.25 62.5 125 0110 6 31.25 62.5 0111 10 31.25 1000 2 31.25 62.5 125 250 1001 4 15.625 31.25 62.5 125 1010 6 31.25 62.5 1011 10 31.25 1100 4 15.625 31.25 62.5 125 1101 8 7.81 15.625 31.25 62.5 1110 12 15.625 31.25 1111 20 15.625 diag-top: synchronous diagnosis clock. table 15-14: synchronous diagnosis clock diag-top synchronous diagnosis clock selection 0 no pulse on the internal diag-clock signal 1 pulse on the internal diag-clock signal the pulse on the internal diag-clock signal is used for the synchronous diagnosis clock (see information on the characteristics of the clock diag-clock in the paragraph describing the diag- nosis function). en-emecb: enable the transmit diagnosis. table 15-15: enable the transmit diagnosis en-emecb transmit diagnostic 0 enables the transmission diagnosis 1 disables the transmission diagnosis due to the diagnosis set-up problems in transmission, this bit permits this part of the diagnosis to be disabled or enabled.
255 pd1615, pd16f15, pd1616 dia1, dia0: choice of communication mode table 15-16: choice of communication mode dia1 dia0 communication mode 0 0 forced operation on rxd0 0 1 forced operation on rxd1 1 0 forced operation on rxd2 1 1 automatic operation the 2 least significant bits dia1 and dia0 allow the user to choose the communication mode.
256 pd1615, pd16f15, pd1616 15.4.6 mask1 registers (msk1_msb_reg, msk1_lsb_reg) these 2 registers allow to compare the 12 bits of the van identification field plus the ext bit. msk1_msb_reg, msk1_lsb_reg is set with a 1-bit or 8-bit manipulation instruction. reset input sets these registers to 00h. figure 15-18-1: mask1 register msk1_msb_reg format figure 15-18-2: mask1 register msk1_lsb_reg format writing ?0? enables the comparison of the corresponding bit. writing ?1? disables the comparison of the corresponding bit that becomes a ?dont care bit?. symbol 76543210address after reset r/w msk_msb_reg b11 b10 b9 b8 b7 b6 b5 b4 f805h 00h r/w symbol 76543210address after reset r/w msk_lsb_reg b3 b2 b1 b0 ext 0 0 0 f806h 00h r/w
257 pd1615, pd16f15, pd1616 15.4.7 acceptance code 1 registers (ac1_msb_reg, ac1_lsb_reg) these 2 registers allow to choose the code acceptance which is the value of the identification field that the user wish to match with. they work together with the msk1 registers. ac1_msb_reg, ac1_lsb_reg is set with a 1-bit or 8-bit manipulation instruction. reset input sets these registers to 00h. figure 15-19-1: acceptance code 1 register ac1_msb_reg figure 15-19-2: acceptance code 1 register ac1_lsb_reg the behaviour of the receive interrupt (int2) according this comparison is described in the para- graph ?receive interrupt behaviour?. symbol 76543210address after reset r/w ac1_lsb_reg f808h 00h r/w symbol 76543210address after reset r/w ac1_msb_reg f807h 00h r/w
258 pd1615, pd16f15, pd1616 15.4.8 mask2 registers (msk2_msb_reg, msk2_lsb_reg) these 2 registers allow to compare the 12 bits of the van identification field plus the ext bit. msk1_msb_reg, msk1_lsb_reg is set with a 1-bit or 8-bit manipulation instruction. reset input sets these registers to 00h. figure 15-20-1: mask2 register msk2_msb_reg format figure 15-20-2: mask2 register msk2_lsb_reg format writing ?0? enables the comparison of the corresponding bit. writing ?1? disables the comparison of the corresponding bit that becomes a ?dont care bit?. symbol 7 6 5 4 3 2 1 0 address after reset r/w m sk2_lsb _ reg b3 b2 b1 b0 ext 0 0 0 f80ah 00h r/w symbol76543210address after reset r/w msk2_msb _reg b11 b10 b9 b8 b7 b6 b5 b4 f809h 00h r/w
259 pd1615, pd16f15, pd1616 15.4.9 acceptance code 2, 3 and 4 registers (ac2_msb_reg, ac2_lsb_reg, ac3_msb_reg, ac3_lsb_reg, ac4_msb_reg, ac4_lsb_reg) these 6 registers allow to choose the code acceptance which is the value of the identification field that the user wish to match with. they work together with the msk2 registers. ac2_msb_reg, ac2_lsb_reg, ac3_msb_reg, ac3_lsb_reg, ac4_msb_reg, ac4_lsb_reg are set with a 1-bit or 8-bit manipulation instruction. reset input sets these registers to 00h. the behaviour of the receive interrupt (int2) according this comparison is described in the paragraph ?receive interrupt behaviour?. symbol 7 6 5 4 3 2 1 0 address after reset r/w ac2_msb_reg b11 b10 b9 b8 b7 b6 b5 b4 f80bh 00h r/w symbol 7 6 5 4 3 2 1 0 address after reset r/w ac2_lsb_reg b3 b2 b1 b0 ext 0 0 0 f80ch 00h r/w symbol 7 6 5 4 3 2 1 0 address after reset r/w ac3_msb_reg b11 b10 b9 b8 b7 b6 b5 b4 f80dh 00h r/w symbol 7 6 5 4 3 2 1 0 address after reset r/w ac3_lsb_reg b3 b2 b1 b0 ext 0 0 0 f80eh 00h r/w symbol 7 6 5 4 3 2 1 0 address after reset r/w ac4_msb_reg b11 b10 b9 b8 b7 b6 b5 b4 f80fh 00h r/w symbol 7 6 5 4 3 2 1 0 address after reset r/w ac4_lsb_reg b3 b2 b1 b0 ext 0 0 0 f810h 00h r/w figure 15-21: acceptance code 2, 3 and 4 registers format
260 pd1615, pd16f15, pd1616 15.4.10 status register (stat_reg) this register allows to control a lost arbitration, the end of message, the acknowledge and the error type during a transmission or a reception. stat_reg can be read with a 1-bit or an 8-bit manipulation instruction. reset input sets this register to 08h. figure 15-22: status register (stat_reg) format symbol 76543210address after reset r/w stat_reg 0 la_r esp eom la ack err 2 err 1 err 0 f811h 08h r la_resp, la: la_resp lost arbitration information 0 arbitration is not lost during rtr bit 1 arbitration lost during the rtr bit of the command field. it is considered as a lost arbitration due to a response. la lost arbitration information 0 arbitration is not lost 1 arbitration lost not in the rtr bit of the command field table 15-17: la_resp, la the uart automatically goes into reception after loosing arbitration during a collision. these 2 kinds of collision may be signalled either by interrupt (int0), if enabled by the user (lae bit of the int_enable_reg register), or by reading these 2 bits in the status register stat_reg. it is worthwhile noting that reading the status register causes all the bits to be reset to 0 (except ack, which is set to 1). eom: table 15-18: eom eom end of message 0 end of message as not given under a.) or b.). 1 a.) if the frame is correct, the eom flag is set after the eod symbol and the err2, err1, err0 bits show 000. b.) if the frame is not correct, the eom flag is also set when the error is detected and the err2, err1, err0 bits show this error.
261 pd1615, pd16f15, pd1616 the eom flag is set when a van frame is transmitted or received correctly or incorrectly. these 2 kinds of eom may be signalled either by interrupt (int0), if enabled by the user (eome bit of the int_enable_reg register), or by reading the eom bit in the status register stat_reg. during an eom interrupt (int0), the microcontroller can read: - la: signals a possible collision with lost arbitration in the current frame. the application software should memorise this information to retry the transmission of this frame. - la_resp:indicates a lost arbitration during the rtr bit. this lost arbitration is due to a response. - ack: indicates the value of the acknowledge bit: 0: positive 1: no acknowledge the ack bit is described in the paragraph control of the acknowledge bit . - err: signals the type of transmit or receive error. the errx bits are described in the paragraph error control where the bit combina tion are given.
262 pd1615, pd16f15, pd1616 15.4.11 receive register (rec_reg) this register is used as receive register of a reception. stat_reg can be read with a 1-bit or an 8-bit manipulation instruction. reset input sets this register to ffh. symbol 7 6 5 4 3 2 1 0 address after reset r/w rec_reg rx7 rx6 rx5 rx4 rx3 rx2 rx1 rx0 f812h ffh r the receive register is read by the microcontroller each time the rda interrupt (int2) is generated by the uart indicating that a new byte is received. the reading limit of the receive register is 13/16 of the last ts of the byte or 13/16 of the third ts of the second byte of identifier in case of it12 is set. if this limit is not met, the component will detect an overrun and will signal a lock up error. the reception is done msb first (rx7 is received first). receive interrupt behaviour : the rda receive interrupt (int2) is generated only if the received van identifier matches with one of the identifiers written in the acx registers. the ac1 registers work with the msk1 mask regis- ters and the ac2, ac3 and ac4 registers work with the msk2 mask registers. since the van identifier is built with 12 bits, it is received over 2 bytes. three cases can occur : * the received identifier does not match at all. the van uart does not produce any interrupt. * the first byte matches but not the second one. the van uart generates the first receive inter- rupt (int2) but since the second identifier byte does not match, the uart will wait for the end of the current frame to generate the eom interrupt (int0). * the whole received identifier matches. the van uart generates all the receive interrups and the eom interrupt. figure 15-23: receive register (rec_reg) format
263 pd1615, pd16f15, pd1616 15.4.12 diagnosis status register (diag_stat_reg) this register is used for the diagnose of the receive lines. diag_stat_reg can be read with a 1-bit or an 8-bit manipulation instruction. reset input sets this register to 00h. figure 15-24: diagnosis status register (diag_stat_reg) format symbol 76543210address after reset r/w diag_stat _reg 0 0 0 0 0 sc sb sa f813h 00h r the bits sa and sb indicate the line chosen by the diagnosis circuit. table 15-19: the bits sa and sb sb sa line chosen 0 0 differential mode ( rx0van )-- no fault 0 1 datab mode ( rx2van ) -- fault on data 1 0 data mode ( rx1van ) -- fault on datab 1 1 major error to perform this diagnosis, the circuit needs the synchronous diagnosis clock (sdc). the synchronous diagnosis circuit is necessary to go back to the nominal mode, which is the differential mode. if no fault is detected between two edges of this clock, the circuit goes back to the nominal mode (line rx0van). this delay of one synchronous diagnosis clock period, is used to solve bad contact problems (on connectors for example). thus, it is equal to a few milliseconds or even a few dozen milliseconds. anyway, this is very large comparing to the ts clock (duration of ts). to generate it, the user must set diag-top to 1 in the diagnosis control register diag_ctrl_reg. table 15-20: the bit sc sc van uart comparator comparison 1 discrepancy between the 3 comparator rx0van, rx1van and rx2van during the reception. 0 no discrepancy between the 3 comparator rx0van, rx1van and rx2van during the reception. in normal operation, the sc bit equals 0, the 3 comparators give an identical result.
264 pd1615, pd16f15, pd1616 15.4.13 interrupt enable register (int_enable_reg) this register allows to enable/disable the interrupt sources of the van uart. int_enable_reg is set with a 1-bit or an 8-bit manipulation instruction. reset input sets this register to 00h. figure 15-25: interrupt enable register (int_enable_reg) format symbol 7 6 5 4 3 2 1 0 address after reset r/w int_ena ble_reg gie rda e tbe e fte fre lae eom e 0 f820h 00h r/w gie : global interrupt enable table 15-21: interrupt enable register (int_enable_reg) (1/2) gie global interrupt enable 0 disables all the interrupt sources 1 enables interrupt sources which can be disabled one by one with the following bits rdae: rda enable rdae receive interrupt 0 receive interrupt disabled 1 receive interrupt enabled tbee: tbe enable tbee transmit interrupt 0 transmit interrupt disabled 1 transmit interrupt enabled fte: ft enable fte fail transmit interrupt 0 failed transmit interrupt disabled 1 failed transmit interrupt enabled
265 pd1615, pd16f15, pd1616 table 15-21: interrupt enable register (int_enable_reg) (2/2) this interrupt will coincide with an eom interrupt, as an error will cause a premature end of message. fre: fr enable fre fail receive interrupt 0 failed receive interrupt disabled 1 failed receive interrupt enabled this interrupt will coincide with an eom interrupt, as an error will cause a premature end of message. lae: la enable lae lost arbitration interrupt 0 lost arbitration interrupt disabled 1 lost arbitration interrupt enabled eome: eom enable eome end of message interrupt 0 end of message interrupt disabled 1 end of message interrupt enabled this interrupt occurs in the case of an end of message, i.e. after the acknowledge field or during an error (premature end of message).
266 pd1615, pd16f15, pd1616 15.4.14 van clock selection register (udlccl) this sfr register enables the clock suppply to the van uart. udlccl is set with a 1-bit or an 8-bit manipulation instruction. reset input sets this register to 00h. figure 15-26: van clock selection register (udlccl) format symbol 7 6543210 addres s after reset r/w udlccludlcken0000000ff78h00hr/w udlcken van udl clock control 0 disable van clock supply 1 enable van clock supply table 15-22: van clock selection register (udlccl) caution : the van uart clock is disable at reset. application software must enable it in order to handle van frame.
267 pd1615, pd16f15, pd1616 15.5 van uart initialisation 1) enable the clock via udlccl sfr register. 2) configure the component: a) choose the uart mode of operation owing to the rank bit in the configuration register b) enable or disable the in frame response using the ifr bit in the same register c) enable or disable the generation of the it12 interrupt using the it12 bit in the same register d) enable or disable the identifier filtering mechanism using the msk1 and msk0 bits in the same register e) program the mskx and acx registers if filtering is enabled. 3) program the prescaler to choose the network communication speed. 4) enable the interrupts for the micro and the van uart.
268 pd1615, pd16f15, pd1616 [memo]
269 pd1615, pd16f15, pd1616 chapter 16 lcd controller/driver 16.1 lcd controller/driver functions the functions of the lcd controller/driver incorporated in the pd1615 subseries are shown below. (1) automatic output of segment signals and common signals is possible by automatic writing of the display data memory. (2) any of five display modes can be selected. ? static ? 1/2 duty (1/2 bias) ? 1/3 duty (1/2 bias) ? 1/3 duty (1/3 bias) ? 1/4 duty (1/3 bias) (3) any of four frame frequencies can be selected in each display mode. (4) maximum of 40 segment signal outputs (s0 to s39); 4 common signal outputs (com0 to com3). the prt function register (pf) has to be set to lcd mode to allow the segment signal output. this lcd mode can be set bit-wise. the maximum number of displayable pixels in each display mode is shown in table 16-1. table 16-1: maximum number of display pixels bias method time division common signals used maximum number of pixels - static com0 (com1, 2, 3) 40 (40 segments x 1 common) 2 com0, com1 80 (40 segments x 2 commons) 1/2 3 3 com0 - com2 120 (40 segments x 3 commons) 1/3 4 com0 - com3 160 (40 segments x 4 commons)
270 pd1615, pd16f15, pd1616 16.2 lcd controller/driver configuration the lcd controller/driver is composed of the following hardware. table 16-2: lcd controller/driver configuration figure 16-1: lcd controller/driver block diagram item configuration display outputs segment signals : 40 segment signal input/output port dual function : 40 common signals : 4 (com0 to com3) control registers lcd display mode register (lcdm) lcd display control register (lcdc) note: segment driver internal bus fa00h 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 fa27h 7 6 5 4 3 2 1 0 display data memory 3 2 1 0 selector 3 2 1 0 selector 3 2 1 0 selector 3 2 1 0 selector ... ... ... ... ... ... note note note note s23/p100 s0/p127 ... ... ... ... ... ... ... ... ... ... ... ... ... ... s24/p97 s39/p80 common driver com0 com3 com1 com2 v lc1 ldon lcdm2 lcdm1 lcdm0 lcd clock selector f lcd 3 lcd display mode register (lcdm) lcd display control register (lcdc) ... ... ... ... ... ... ... ... timing controller lcd driver voltage controller v lc0 v lc2 lips lcdc1 lcdc2
271 pd1615, pd16f15, pd1616 figure 16-2: lcd clock select circuit block diagram remarks: 1. lcdcl : lcd clock 2. f ldc : lcd clock frequency prescaler f lcd /2 3 fx/2 14 f lcd /2 2 f lcd /2 f lcd selector lcdc3 lcdc2 2 lcdcl lcd display mode register internal bus
272 pd1615, pd16f15, pd1616 16.3 lcd controller/driver control registers the lcd controller/driver is controlled by the following two registers. ? lcd display mode register (lcdm) ? lcd display control register (lcdc) (1) lcd display mode register (lcdm) this register sets display operation enabling/ disabling, the lcd driving power and the lcd display mode. lcdm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdm to 00h. figure 16-3: lcd display mode register format lips lcd driving power supply selection 0 does not supply power to lcd 1 supplies power to lcd from v dd pin selects display mode of lcd controller/driver lcdm2 lcdm1 lcdm0 time division bias mode 0004 1/3 0013 1/3 0102 1/2 0113 1/2 1 0 0 static display mode other than above setting prohibited symbol76543210addressafterresetr/w lcdm lcdon 0 0 lips 0 lcdm2 lcdm1 lcdm0 ffb0h 00h r/w lcdon lcd display enable/disable 0 display off 1 display on
273 pd1615, pd16f15, pd1616 table 16-3: frame frequencies (hz) remark: 1.figures in parentheses apply to operation with fx = 4.0 mhz or fx = 8.0 mhz. frame frequency (hz) f x=4.0 mhz f x=8.0 mhz lcdc3 lcdc2 static 1/2 1/3 1/4 static 1/2 1/3 1/4 0 0 244 122 81.4 61 488 244 162.8 122 0 1 122 61 40.7 30.5 244 122 81.4 61 1 0 61 30.5 20.3 15.3 122 61 40.7 30.5 1 1 30.5 15.3 10.2 7.6 61 30.5 20.3 15.3
274 pd1615, pd16f15, pd1616 (2) lcd display clock control register (lcdc) this register sets the lcd clock. lcdc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets lcdc to 00h. figure 16-4: lcd display clock control register format symbol76543210addressafterresetr/w lcdc0000l cdc3 lcdc2 0 0 ffb2h 00h r/w lcdc3 lcdc2 selection of lcd clock 00 fx/2 17 01 fx/2 16 10 fx/2 15 10 fx/2 14
275 pd1615, pd16f15, pd1616 16.4 lcd controller/driver settings lcd controller/driver settings should be performed as shown below. when the lcd controller/driver is used, the watch timer should be set to the operational state beforehand. <1>set the initial value in the display data memory (fa00h to fa27h). <2>set the pins to be used as segment outputs in the port function registers (pf8 to pf12). <3>set the display mode, operating mode in the lcd display mode register (lcdm), and the lcd clock in the lcd clock control register (lcdc). next, set data in the display data memory according to the display contents.
276 pd1615, pd16f15, pd1616 16.5 lcd display data memory the lcd display data memory is mapped onto addresses fa00h to fa27h. the data stored in the lcd display data memory can be displayed on an lcd panel by the lcd controller/driver. figure 16-5 shows the relationship between the lcd display data memory contents and the segment outputs/common outputs. any area not used for display can be used as normal ram. figure 16-5: relationship between lcd display data memory contents and segment/common outputs caution: the higher 4 bits of the lcd display data memory do not incorporate memory. be sure to set them to 0. s0 s1 s2 s3 s37 s38 s39 com3 com2 com1 com0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address fa27h fa26h fa25h fa24h fa02h fa01h fa00h
277 pd1615, pd16f15, pd1616 16.6 common signals and segment signals an individual pixel on an lcd panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the lcd drive voltage v lcd ). as an lcd panel deteriorates if a dc voltage is applied in the common signals and segment signals, it is driven by ac voltage. (1) common signals for common signals, the selection timing order is as shown in table 16-4 according to the number of time divisions set, and operations are repeated with these as the cycle. in the static display mode, the same signal is output to com0 through com3. with 2-time-division operation, pins com2 and com3 are left open, and with 3-time-division operation, the com3 pin is left open. table 16-4: com signals (2) segment signals segment signals correspond to a 40-byte lcd display data memory. each display data memory bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the com0, com1, com2 and com3 timings respectively, and if the value of the bit is 1, it is converted to the selection voltage. if the value of the bit is 0, it is converted to the non-selection voltage and output to a segment pin (s0 to s39). consequently, it is necessary to check what combination of front surface electrodes (correspond- ing to the segment signals) and rear surface electrodes (corresponding to the common signals) of the lcd display to be used form the display pattern, and then write bit data corresponding on a one-to-one basis with the pattern to be displayed. in addition, because lcd display data memory bits 1 and 2 are not used with the static display mode, bits 2 and 3 are not used with the 2-time-division method, and bit 3 is not used with the 3-time-division method, these can be used for other than display purposes. bits 4 to 7 are fixed at 0. com signal time division static 2-time division 3-time division 4-time division open open open com0 com1 com2 com3
278 pd1615, pd16f15, pd1616 (3) common signal and segment signal output waveforms the voltages shown in table 16-5 are output in the common signals and segment signals. the v lcd on voltage is only produced when the common signal and segment signal are both at the selection voltage; other combinations produce the off voltage. table 16-5: lcd drive voltages a) static display mode (b) 1/2 bias method (c) 1/3 bias method se g ment select non-select common v ss1, v lc0 v lc0 , v ss1 v lc0 , v ss1 -v lcd , +v lcd 0 v, 0 v segment select non-select common v ss1, v lc0 v lc0 , v ss1 select level v lc0 , v ss1 -v lcd , +v lcd 0 v, 0 v non-select level v lc1 = v lc2 -1/2 v lcd , +1/2 v lcd +1/2 v lcd , -1/2 v lcd segment select non-select common v ss1, v lc0 v lc1 , v lc2 select level v lc0 , v ss1 -v lcd , +v lcd -1/3 v lcd , +1/3 v lcd non-select level v lc2 , v lc1 -1/3 v lcd , +1/3 v lcd -1/3 v lcd , +1/3 v lcd
279 pd1615, pd16f15, pd1616 figure 16-6 shows the common signal waveform, and figure 16-7 shows the common signal and segment signal voltages and phases. figure 16-6: common signal waveform (a) static display mode remarks: 1.t: one lcdcl cycle 2.tf: frame frequency (b) 1/2 bias method remarks: 1.t: one lcdcl cycle 2.tf: frame frequency (c) 1/3 bias method remarks: 1.t: one lcdcl cycle 2.tf: frame frequency comn (static) t f = t v lc0 v ss1 v lcd comn (divided by 2) t f = 2 x t v lc0 v ss1 v lcd v lc2 comn (divided by 3) t f = 3 x t v lc0 v ss1 v lcd v lc2 comn (divided by 3) t f = 3 x t v lc0 v ss1 v lcd v lc1 v lc2 t f = 4 x t comn (divided by 4) v lc0 v ss1 v lcd v lc1 v lc2
280 pd1615, pd16f15, pd1616 figure 16-7: common signal and static signal voltages and phases (a) static display mode remark: t : one lcdcl cycle (b) 1/2 bias method remark: t : one lcdcl cycle (c) 1/3 bias method remark: t : one lcdcl cycle selected not selected common signal segment signal v lc0 v ss1 v lcd v lc0 v ss1 v lcd tt selected not selected common signal segment signal v lc0 v ss1 v lcd v lc0 v ss1 v lcd tt v lc2 v lc2 selected not selected common signal segment signal v lc0 v ss1 v lcd v lc0 v ss1 v lcd tt v lc2 v lc2 v lc1 v lc1
281 pd1615, pd16f15, pd1616 16.7 supply of lcd drive voltages v lc0 , v lc1 , v lc2 the split resistors makes it possible to produce lcd drive voltages appropriate to the various bias methods shown in table 16-6 without using external split resistors. table 16-6: lcd drive voltages (with on-chip split resistor)connected externally an example of supply of the lcd drive voltage from off-chip is shown in figure 16-9. stepless lcd drive voltages can be supplied by means of variable resistor r. note: the 1615 subseries has no split resistors inside. the split resistors have to be set externally for the different lcd voltages. bias method lcd drive voltage no bias (static mode) 1/2 bias 1/3 bias v lc0 v lcd v lcd v lcd v lc1 2/3 v lcd 2/3 v lcd v lc2 1/3 v lcd 1/2 v lcd 1/3 v lcd
282 pd1615, pd16f15, pd1616 figure 16-8: lcd drive power supply connection examples (with external split resistor) (a) static display mode note (example with v dd 1 = 5 v, v lcd = 5 v) note: lips should always be set to 1 (including in standby mode). (b) 1/2 bias method (c) 1/3 bias method (example with vdd1 = 5 v, vlcd = 5 v) (example with vdd1 = 5 v, vlcd = 5 v) caution: the lcd split resistors have to be set externally. p-ch v dd1 lips v lc0 v lc1 v lc2 v ss1 v ss1 v lcd p-ch v dd1 lips v lc0 v lc1 v lc2 v ss1 v ss1 v lcd r r p-ch v dd1 lips v lc0 v lc1 v lc2 v ss1 v ss1 v lcd r r r
283 pd1615, pd16f15, pd1616 figure 16-9: example of lcd drive voltage supply from off-chip caution: the lcd split resistors have to be set externally. p-ch v dd1 lips v lc0 v lc1 v lc2 v ss1 v ss1 v lcd v dd1 = v lcd r r r 3r 3r + r
284 pd1615, pd16f15, pd1616 16.8 display modes 16.8.1 static display example figure 16-11 shows the connection of a static type 5-digit lcd panel with the display pattern shown in figure 16-10 with segment (s0 to s39) and common (com0) signals. the display example is 123.45, and the display data memory contents (addresses fa68h to fa27h) correspond to this. an explanation is given here taking the example of the third digit 3. ( ). in accordance with the display pattern in figure 16-10, selection and non-selection voltages must be output to pins s16 through s23 as shown in table 16-7 at the com0 common signal timing. table 16-7: selection and non-selection voltages (com0) s: selection, ns: non-selection from this, it can be seen that 10101111 must be prepared in the bit0 bits of the display data memory corresponding to s16 to s23. the lcd drive waveforms for s19, s20, and com0 are shown in figure 16-12. when s19 is at the selection voltage at the timing for selection with com0, it can be seen that the +v lcd /Cv lcd ac square wave, which is the lcd illumination (on) level, is generated. shorting the com0 through com3 lines increases the current drive capability because the same waveform as com0 is output to com1 through com3. figure 16-10: static lcd display pattern and electrode connections n = 0 to 4 s 8n+3 s 8n+2 s 8n+5 s 8n+1 s 8n s 8n+4 s 8n+6 s 8n+7 com0 segment common s16 s17 s18 s19 s20 s21 s22 s23 com0 s s s s ns s ns s
285 pd1615, pd16f15, pd1616 figure 16-11: static lcd panel connection example lcd panel timing strobes com3 com2 com1 com0 bit0 bit1 bit2 bit3 s0 s1 s2 0 x x fa27h 1 x x 6 0 x x 5 1 x x 4 s3 s4 s5 s6 1 x x 3 1 x x 2 0 x x 1 1 x x 0 s7 s8 s9 s10 0 x x fa1fh 1 x x e 1 x x d 0 x x c s11 s12 s13 s14 1 x x b 1 x x a 0 x x 9 0 x x 8 s15 s16 s17 s18 1 x x 7 1 x x 6 x x 5 1 x x data memor y address x x x x x x x x x x x x x x x x x x x s20 s19 s21 0 x x 3 1 x x 2 0 x x 1 s22 s23 s24 s25 1 x x 0 0 x x fa0fh 0 x x e 1 x x d s26 s27 s28 s29 x x x c 0 x x b 0 x x a 1 x x 9 s30 s31 s32 s33 x x x 8 x 0 x 7 1 1 x 6 x x x 5 s34 s35 s36 s37 x 0 x 0 x x 3 0 x x 2 0 x x x x x x x x 1 x x x 1 x x x x x x x x 4 4 1 fa00h x x x 0 s38 s39 1 x can be shorted
286 pd1615, pd16f15, pd1616 figure 16-12: static lcd drive waveform examples t f v lc0 v ss1 com0 v lc0 v ss1 s19 v lc0 v ss1 s20 +v lcd 0 com0-s20 ? lcd +v lcd 0 com0-s19 ? lcd
287 pd1615, pd16f15, pd1616 16.8.2 2-time-division display example figure 16-14 shows the connection of a 2-time-division type 10-digit lcd panel with the display pattern shown in figure 16-13 with segment signals (s0 to s39) and common signals (com0, com1). the display example is 123456.7890, and the display data memory contents correspond to this. an explanation is given here taking the example of the eighth digit 3 ( ). in accordance with the display pattern in figure 16-13, selection and non-selection voltages must be output to pins s28 through s31 as shown in table 16-8 at the com0 and com1 common signal timings. table 16-8: selection and non-selection voltages (com0, com1) s: selection, ns: non-selection from this, it can be seen that, for example, xx10 must be prepared in the display data memory corresponding to s31. examples of the lcd drive waveforms between s31 and the common signals are shown in figure 16-15. when s31 is at the selection voltage at the com1 selection timing, it can be seen that the +v lcd /Cv lcd ac square wave, which is the lcd illumination (on) level, is generated. figure 16-13: 2-time-division lcd display pattern and electrode connections n = 0 to 9 s 4n + 2 s 4n + 3 s 4n + 1 s 4n com0 com1 segment common s28 s29 s30 s31 com0 s s ns ns com1 ns s s s
288 pd1615, pd16f15, pd1616 figure 16-14: 2-time-division lcd panel connection example remark: in bits marked x, any data can be stored because this is a 2-time-division display. lcd panel timing strobes com3 com2 com1 com0 bit0 bit1 bit2 bit3 s0 s1 s2 1 x x fa27h 1 x x 6 1 x x 5 1 x x 4 s3 s4 s5 s6 1 x x 3 1 x x 2 1 x x 1 0 x x 0 s7 s8 s9 s10 1 x x fa1fh 1 x x e 1 x x d 1 x x c s11 s12 s13 s14 1 x x b 1 x x a 1 x x 9 0 x x 8 s15 s16 s17 s18 1 x x 7 0 x x 6 x x 5 1 x x data memor y address 0 0 1 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 1 s20 s19 s21 1 x x 3 0 x 1 2 1 x x 1 s22 s23 s24 s25 0 x x 0 1 x x fa0fh 1 x x e 1 x x d s26 s27 s28 s29 0 x x c 1 x x b 1 x x a 0 1 x 9 s30 s31 s32 s33 x x x 8 x 0 x 7 1 0 x 6 x x x 5 s34 s35 s36 s37 x 1 x 1 x x 3 1 x x 2 0 x x 0 x 1 1 0 1 0 0 1 0 0 1 0 1 1 1 0 0 0 4 4 1 fa00h x x 0 0 s38 s39 1 1 open open
289 pd1615, pd16f15, pd1616 figure 16-15: 2-time-division lcd drive waveform examples (1/2 bias method) t f v lc0 v ss1 com0 v lc0 v ss1 v lc0 v ss1 s31 +v lcd 0 com1-s31 ? lcd +v lcd 0 com0-s31 ? lcd v lc1 (v lc2 ) com1 +1/2v lcd +1/2v lcd ?/2v lcd ?/2v lcd v lc1 (v lc2 ) v lc1 (v lc2 )
290 pd1615, pd16f15, pd1616 16.8.3 3-time-division display example figure 16-17 shows the connection of a 3-time-division type 13-digit lcd panel with the display pattern shown in figure 16-16 with segment signals (s0 to s38) and common signals (com0 to com2). the display example is 123456.7890123, and the display data memory contents correspond to this. an explanation is given here taking the example of the eighth digit 6. ( ) . in accordance with the display pattern in figure 16-16, selection and non-selection voltages must be output to pins s21 through s23 as shown in table 16-9 at the com0 to com2 common signal timings. table 16-9: selection and non-selection voltages (com0 to com2) s: selection, ns: non-selection from this, it can be seen that x110 must be prepared in the display data memory (address fa12h) corresponding to s21. examples of the lcd drive waveforms between s21 and the common signals are shown in figure 16-18 (1/2 bias method) and figure 16-19 (1/3 bias method). when s21 is at the selection voltage at the com1 selection timing, and s21 is at the selection voltage at the com2 selection timing, it can be seen that the +v lcd /Cv lcd ac square wave, which is the lcd illumination (on) level, is generated. figure 16-16: 3-time-division lcd display pattern and electrode connections n = 0 to 12 s 3n + 2 s 3n com0 com2 s 3n + 1 com1 segment common s21 s22 s23 com0 ns s s com1 s s s com2 s s -
291 pd1615, pd16f15, pd1616 figure 16-17: 3-time-division lcd panel connection example remarks: 1. x : irrelevant bits because they have no corresponding segment in the lcd panel 2. x : irrelevant bits because this is a 3-time-division display timing strobes com3 com2 com1 com0 bit0 bit1 bit2 bit3 s0 s1 s2 s3 1 0 x f a27h 1 1 x 0 x x 1 0 x s4 s5 s6 s7 0 0 x 0 x x 1 0 x 0 0 x s8 s9 s10 s11 0 x x 1 0 x 1 1 x 1 x x s12 s13 s14 s15 1 0 x a 1 0 x 9 1 x x 8 1 0 x 7 s16 s17 s18 s19 1 1 x 1 x x 1 0 x 1 0 x data memor y address lcd panel 1 1 0 0 0 0 1 0 0 1 0 1 1 1 0 1 1 1 1 0 1 x x 0 1 x 1 1 x 1 x x 0 0 x 1 1 x 1 x x 1 0 x 0 0 x 1 x x 1 0 x 1 1 x 0 x x 1 0 x 1 1 x 0 x x 1 0 x 0 0 x 0 x x 0 1 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 6 5 4 3 2 1 fa1fh e d c b 6 5 4 3 2 1 0 fa0fh e d c b a 9 8 7 6 5 4 3 2 1 fa00h s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 s32 s33 s34 s35 s36 s37 s38 open 0
292 pd1615, pd16f15, pd1616 figure 16-18: 3-time-division lcd drive waveform examples (1/2 bias method) t f v lc0 v ss1 com0 v lc0 v ss1 v lc0 v ss1 com2 +v lcd 0 com1-s21 ? lcd +v lcd 0 com0-s21 ? lcd com1 +1/2v lcd +1/2v lcd ?/2v lcd ?/2v lcd v lc0 v ss1 s21 +v lcd 0 com2-s21 ? lcd +1/2v lcd ?/2v lcd v lc1 (v lc2 ) v lc1 (v lc2 ) v lc1 (v lc2 ) v lc1 (v lc2 )
293 pd1615, pd16f15, pd1616 figure 16-19: 3-time-division lcd drive waveform examples (1/3 bias method) v lc0 v lc2 com0 +v lcd 0 com0-s21 ? lcd v lc1 +1/3v lcd ?/3v lcd v ss1 v lc0 v lc2 com1 v lc1 v ss1 v lc0 v lc2 com2 v lc1 v ss1 v lc0 v lc2 s21 v lc1 v ss1 +v lcd 0 com1-s21 ? lcd +1/3v lcd ?/3v lcd +v lcd 0 com2-s21 ? lcd +1/3v lcd ?/3v lcd t f
294 pd1615, pd16f15, pd1616 16.8.4 4-time-division display example figure 16-21 shows the connection of a 4-time-division type 20-digit lcd panel with the display pattern shown in figure 16-20 with segment signals (s0 to s39) and common signals (com0 to com3). the display example is 123456.78901234567890, and the display data memory contents correspond to this. an explanation is given here taking the example of the 15th digit 6. ( ). in accordance with the display pattern in figure 16-20, selection and non-selection voltages must be output to pins s28 and s29 as shown in table 16-10 at the com0 to com3 common signal timings. table 16-10: selection and non-selection voltages (com0 to com3) s: selection, ns: non-selection from this, it can be seen that 1101 must be prepared in the display data memory (address fa0bh) corresponding to s28. examples of the lcd drive waveforms between s28 and the com0 and com1 signals are shown in figure 16-22 (for the sake of simplicity, waveforms for com2 and com3 have been omitted). when s28 is at the selection voltage at the com0 selection timing, it can be seen that the +v lcd /Cv lcd ac square wave, which is the lcd illumination (on) level, is generated. figure 16-20: 4-time-division lcd display pattern and electrode connections n = 0 to 18 com0 s 2n com1 s 2n + 1 com2 com3 segment common s28 s29 com0 s s com1 ns s com2 s s com3 s s
295 pd1615, pd16f15, pd1616 figure 16-21: 4-time-division lcd panel connection example timing strobes com3 com2 com1 com0 bit0 bit1 bit2 bit3 s0 s1 s2 1 1 0 fa27h 1 1 1 6 1 1 0 5 1 0 0 4 s3 s4 s5 s6 1 1 0 3 1 1 1 2 1 1 0 1 1 0 0 0 s7 s8 s9 s10 1 1 0 fa1fh 1 1 1 e 1 1 0 d 1 0 1 c s11 s12 s13 s14 0 1 0 b 1 0 0 a 1 1 0 9 0 0 1 8 s15 s16 s17 s18 1 0 0 7 0 1 1 6 1 0 5 0 0 0 data memor y address lcd panel 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 0 timing strobes s20 s19 s21 1 1 0 3 1 1 0 2 1 0 0 1 s22 s23 s24 s25 1 1 0 0 1 1 1 fa0fh 1 1 0 e 1 0 0 d s26 s27 s28 s29 1 1 0 c 1 1 1 b 1 1 1 a 1 0 1 9 s30 s31 s32 s33 0 1 0 8 1 0 0 7 1 1 0 6 0 0 1 5 s34 s35 s36 s37 1 0 0 1 0 0 3 0 1 1 2 0 1 0 data memor 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 4 4 1 fa00h 0 0 0 0 s38 s39 0 1
296 pd1615, pd16f15, pd1616 figure 16-22: 4-time-division lcd drive waveform examples (1/3 bias method) t f v lc0 v lc2 com0 +v lcd 0 com0-s28 ? lcd v lc1 +1/3v lcd ?/3v lcd v ss1 v lc0 v lc2 com1 v lc1 v ss1 v lc0 v lc2 com2 v lc1 v ss1 v lc0 v lc2 com3 v lc1 v ss1 +v lcd 0 com1-s28 ? lcd +1/3v lcd ?/3v lcd v lc0 v lc2 s28 v lc1 v ss1
297 pd1615, pd16f15, pd1616 [memo]
298 pd1615, pd16f15, pd1616 chapter 17 sound generator 17.1 sound generator function the sound generator has the function to sound the buzzer from an external speaker, and the following two signals are output. (1) basic cycle output signal (with/without amplitude) a buzzer signal with a variable frequency in a range of 0.25 to 7.3 khz (at fx = 8.00 mhz) can be output. the amplitude of the basic cycle output signal can be varied by anding the basic cycle output signal with the 7-bit-resolution pwm signal, to enable control of the buzzer sound volume. (2) amplitude output signal a pwm signal with a 7-bit resolution for variable amplitude can be independently output. figure 17-1 shows the sound generator block diagram and figure17-2 shows the concept of each signal. figure 17-1: sound generator block diagram internal bus internal bus sound generator control register (sgcr) tce sgob sgcl2 sgcl1sgcl0 2 4 7 q f x f sg1 f sg2 1/2 1/2 selector prescaler selector selector 5-bit counter comparator comparator sgo/ sgof/ p47 sgoa/ p46 clear pwm amplitude s r sgob sgcl0 sgbr3 sgbr2 sgbr1 sgbr0 sgam6 sgam5 sgam4 sgam3 sgam2sgam1sgam0 p46 output latch pm46 sound generator buzzer control register (sgbr) sound generator amplitude register (sgam) port mode register 4 (pm4)
299 pd1615, pd16f15, pd1616 figure 17-2: concept of each signal 17.2 sound generator configuration the sound generator consists of the following hardware. table 17-1: sound generator configuration item configuration counter 8 bits x 1, 5 bits x 1 sg output sgo/sgof (with/without append bit of basic cycle output) sgoa (amplitude output) control register sound generator control register (sgcr) sound generator buzzer control register (sgbr) sound generator amplitude register (sgam) basic cycle output sgof (without amplitude) amplitude output sgoa basic cycle output sgo (with amplitude)
300 pd1615, pd16f15, pd1616 17.3 sound generator control registers the following three types of registers are used to control the sound generator. ? sound generator control register (sgcr) ? sound generator buzzer control register (sgbr) ? sound generator amplitude control register (sgam) (1)sound generator control register (sgcr) sgcr is a register which sets up the following four types. ? controls sound generator output ? selects output of sound generator ? selects sound generator input frequency f sg 1 ? selects 5-bit counter input frequency f sg 2 sgcr is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sgcr to 00h. figure 17-3 shows the sgcr format.
301 pd1615, pd16f15, pd1616 figure 17-3: sound generator control register (sgcr) format caution: before setting the tce bit, set all the other bits. remark: sgof: basic cycle signal (without amplitude) sgo: basic cycle signal (with amplitude) sgoa: amplitude signal cautions: 1. when rewriting sgcr to other data, stop the timer operation (tce = 0) beforehand. 2. bits 4 to 6 must be set to 0. sgob sound generator output selection 0 selects sgof and sgoa outputs 1 selects sgo and pcl outputs sgcl2 sgcl1 5-bit counter input frequency f sg 2 selection 00f sg 2 = f sg 1 /2 5 01f sg 2 = f sg 1 /2 6 10f sg 2 = f sg 1 /2 7 11f sg 2 = f sg 1 /2 8 sgcl0 sound generator input frequency selection 0f sg 1 = f x /2 7 1f sg 1 = f x /2 8 symbol76543210addressafter resetr/w sgcr tce 0 0 0 sgob sgcl2 sgcl1 sgcl0 ff66h 00h r/w tce sound generator output selection 0 timer operation stopped sgof/sgo and sgoa for low-level output 1 sound generator operation sgof/sgo and sgoa for output
302 pd1615, pd16f15, pd1616 the sound generator output frequency f sg can be calculated by the following expression. f sg = 2 (sgcl0 C sgcl1 C 2 x sgcl2 C 7) x {fx/(sgbr + 17)} substitute set 0 or 1 to sgcl0 to sgcl2 in the above expression. substitute a decimal value to sgbr. where fx = 8 mhz, sgcl0 to sgcl2 is (1, 0, 0), and sgbr0 to sgbr3 is (1, 1, 1, 1), sgbr = 15. therefore, f sg = 2 (1 C 0 C 2 x 0 C 7) x {fx/(15 + 17)} = 3.906 khz (2) sound generator buzzer control register (sgbr) sgbr is a register that sets the basic frequency of the sound generator output signal. sgbr is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sgbr to 00h. figure 17-4 shows the sgbr format. figure 17-4: sound generator buzzer control register (sgbr) format symbol 76543210addressafter resetr/w sgbr 0000sgbr3sgbr2sgbr1sgbr0ff68h00hr/w cautions: 1. when rewriting sgbr to other data, stop the timer operation (tce = 0) beforehand. 2. bits 4 to 7 must be set to 0.
303 pd1615, pd16f15, pd1616 (3) sound generator amplitude register (sgam) sgam is a register that sets the amplitude of the sound generator output signal. sgam is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sgam to 00h. figure 17-6 shows the sgam format. figure 17-5: sound generator frequency selection sgbr sgcl2,1 (hz) sgcl0 4-bit comparator 00 01 10 11 0000 7352.9 3676.5 1838.2 919.1 0001 6944.4 3472.2 1736.1 868.1 0010 6578.9 3289.5 1644.7 822.4 0011 6250.0 3125.0 1562.5 781.3 0100 5952.4 2976.2 1488.1 744.0 0101 5681.8 2840.9 1420.5 710.2 0110 5434.8 2717.4 1358.7 679.3 0111 5208.3 2604.2 1302.1 651.0 1000 5000.0 2500.0 1250.0 625.0 1001 4807.7 2403.8 1201.9 601.0 1010 4629.6 2314.8 1157.4 578.7 1011 4464.3 2232.1 1116.1 558.0 1100 4310.3 2155.2 1077.6 538.8 1101 4166.7 2083.3 1041.7 520.8 1110 4032.3 2016.1 1008.1 504.0 0 1111 3906.3 1953.1 976.6 488.3 0000 3676.5 1838.2 919.1 459.6 0001 3472.2 1736.1 868.1 434.0 0010 3289.5 1644.7 822.4 411.2 0011 3125.0 1562.5 781.3 390.6 0100 2976.2 1488.1 744.0 372.0 0101 2840.9 1420.5 710.2 355.1 0110 2717.4 1358.7 679.3 339.7 0111 2604.2 1302.1 651.0 325.5 1000 2500.0 1250.0 625.0 312.5 1001 2403.8 1201.9 601.0 300.5 1010 2314.8 1157.4 578.7 289.4 1011 2232.1 1116.1 558.0 279.0 1100 2155.2 1077.6 538.8 269.4 1101 2083.3 1041.7 520.8 260.4 1110 2016.1 1008.1 504.0 252.0 1 1111 1953.1 976.6 488.3 244.1
304 pd1615, pd16f15, pd1616 figure 17-6: sound generator amplitude register (sgam) format cautions: 1. when rewriting the contents of sgam, the timer operation does not need to be stopped. however, note that a high level may be output for one period due to rewrite timing. 2. bit 7 must be set to 0. symbol76543210addressafter resetr/w sgam 0 sgam6 sgam5 sgam4 sgam3 sgam2 sgam1 sgam0 ff67h 00h r/w sgam6 sgam5 sgam4 sgam3 sgam2 sgam1 sgam0 amplitude 00000000/128 00000012/128 00000103/128 00000114/128 00001005/128 00001016/128 00001107/128 00001118/128 00010009/128 000100110/128 000101011/128 000101112/128 000110013/128 000110114/128 000111015/128 000111116/128 001000017/128 001000118/128 001001019/128 001001120/128 001010021/128 001010122/128 001011023/128 001011124/128 001100025/128 001100126/128 001101027/128 001101128/128 001110029/128 001110130/128 001111031/128 || 0111111 128/128
305 pd1615, pd16f15, pd1616 17.4 sound generator operations 17.4.1 to output basic cycle signal sgof (without amplitude) select sgof output by setting bit 3 (sgob) of the sound generator control register (sgcr) to 0. the basic cycle signal with a frequency specified by the sgcl0 to sgcl2 and sgbr0 to sgbr3 is output. at the same time, the amplitude signal with an amplitude specified by the sgam0 to sgam6 is output from the sgoa pin. figure 17-7: sound generator output operation timing without amplitude 17.4.2 to output basic cycle signal sgo (with amplitude) select sgo output by setting bit 3 (sgob) of the sound generator control register (sgcr) to 1. the basic cycle signal with a frequency specified by the sgcl0 to sgcl2 and sgbr0 to sgbr3 is output. when sgo output is selected, the sgoa pin can be used as a pcl output (clock output) or i/o port pin. figure 17-8: sound generator output operation timing with amplitude timer comparator 1 coincidence sgof sgoa nnnnnn timer comparator 1 coincidence sgof sgoa sgo nnnnnn
306 pd1615, pd16f15, pd1616 [memo]
307 pd1615, pd16f15, pd1616 chapter 18 interrupt functions 18.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even in a disabled state. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. it generates a standby release signal. the non-maskable interrupt has one source of interrupt request from the watchdog timer. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register (pr0l, pr0h, and pr1l). multiple high priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupts has a predetermined priority (see table 18-1). a standby release signal is generated. the maskable interrupt has seven sources of external interrupt requests and fifteen sources of internal interrupt requests. (3) software interrupt this is a vectored interrupt to be generated by executing the brk instruction. it is acknowledged even in a disabled state. the software interrupt does not undergo interrupt priority control.
308 pd1615, pd16f15, pd1616 18.2 interrupt sources and configuration there are total of 24 non-maskable, maskable, and software interrupts in the interrupt sources. table 18-1: interrupt source list notes: 1. default priorities are intended for two or more simultaneously generated maskable interrupt requests. 0 is the highest priority and 26 is the lowest priority. 2. basic configuration types (a) to (d) correspond to (a) to (d) of figure 18-1. interrupt type priority (default) interrupt request source vector code address basic struct ure type resetting - reset reset input 0000h non- maskable -intwdt watchdog timer overflow (when non-maskable interrupt is selected) ( a ) 0intwdt watchdog timer overflow (when interval timer is selected) 0004h 1intve intve ? van-end of message 0006h 2intvt intvt ? van-emission 0008h 3intvr intvr ? van-reception 000ah ( b ) 4 intp0 000ch 5 intp1 000eh 6intp2 external interrupt pin input edge detection 0010h ( c ) 7 inttm00 agreement between tm00 and cr00 (when compare register is specified) ti01 valid edge detection (when capture register is specified) 0012h 8 inttm01 agreement between tm00 and cr01 (when compare register is specified) ti00 valid edge detection (when capture register is specified) 0014h 9 inttm50 agreement between tm50 and cr50 0016h 10 inttm51 agreement between tm51 and cr51 0018h 11 intwti watch timer interval interrupt 001ah 12 intwt watch interrupt 001ch 13 intcsi3 sio30 transfer completion 001eh 14 intser uart0 reception error occurrence 0020h 15 intsr uart0 reception completion 0022h 16 intst uart0 transmission completion 0024h maskable 17 intad a/d conversion end 0026h ( b) software - brk execution of brk instruction 003eh ( d)
309 pd1615, pd16f15, pd1616 figure 18-1: basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt if : interrupt request flag ie : interrupt enable flag isp : inservice priority flag mk : interrupt mask flag pr : priority specify flag internal bus priority control circuit vector table address generator standby release signal interrupt request internal bus ie pr isp mk if interrupt request priority control circuit vector table address generator standby release signal
310 pd1615, pd16f15, pd1616 figure 18-1: basic configuration of interrupt function (2/2) (c) external maskable interrupt (except intp0) (d) software interrupt if : interrupt request flag ie : interrupt enable flag isp : inservice priority flag mk : interrupt mask flag pr : priority specify flag external interrupt mode register (egn, egp) edge detector interrupt request ie pr isp mk if priority control circuit vector table address generator standby release signal internal bus internal bus priority control circuit vector table address generator interrupt request
311 pd1615, pd16f15, pd1616 18.3 interrupt function control registers the following six types of registers are used to control the interrupt functions. ? interrupt request flag register (if0l, if0h, if1l) ? interrupt mask flag register (mk0l, mk0h, mk1l) ? priority specify flag register (pr0l, pr0h, pr1l) ? external interrupt mode register (egp, egn) ? program status word (psw) table 18-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corresponding to interrupt request sources. table 18-2: various flags corresponding to interrupt request sources interrupt request signal name interrupt request flag interrupt mask flag priority specify flag intwdt wdtif wdtmk wdtpr intve veif vemk vepr intvt vtif vtmk vtpr intvr vrif vrmk vrpr intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 inttm00 tmif00 tmmk00 tmpr00 inttm01 tmif01 tmmk01 tmpr01 intm50 tmif50 tmmk50 tmpr50 intm51 tmif51 tmmk51 tmpr51 intwti wtiif wtimk wtipr intwt wtif wtmk wtpr intcsi3 csiif3 csimk3 csipr3 intser serif sermk serpr intsr srif srmk srpr intst stif stmk stpr intad adif admk adpr
312 pd1615, pd16f15, pd1616 (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. it is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h and if1l are set with a 1-bit or 8-bit memory manipulation instruction. if if0l and if0h are used as a 16-bit register if0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to 00h. figure 18-2: interrupt request flag register format cautions: 1. wdtif flag is r/w enabled only when a watchdog timer is used as an interval timer. if used in the watchdog timer mode 1, set wdtif flag to 0. 2. set always 0 in if1l bit 2 to bit 7. 7 srif symbol if0h 654 wtif 3 wtiif 2 tmif51 1 tmif50 0 tmif01 address ffe1h 00h after reset r/w r/w xxifx 0 1 interrupt request flag no interrupt request signal interrupt request signal is generated; interrupt request state if1l 0 0 adif ffe2h 00h r/w tmif00 if0l pif2 pif1 veif wdtif ffe0h 00h r/w pif0 vrif vtif serif csiif3 0 0 0 stif 0
313 pd1615, pd16f15, pd1616 (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. mk0l, mk0h and mk1l are set with a 1-bit or 8-bit memory manipulation instruction. if if0l and if0h are used as a 16-bit register mk0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 18-3: interrupt mask flag register format cautions: 1. if wdtmk flag is read when a watchdog timer is used as a non-maskable interrupt, mk0 value becomes undefined. 2. set always 1 in mk1l bit 2 to bit 7. xx mk x 0 1 interrupt servicing control interrupt servicing enabled interrupt servicing disabled 7 symbol mk0h 65432 10 address ffe5h 00h after reset r/w r/w mk1l admk ffe6h 00h r/w mk0l ffe4h 00h r/w stmk 1 1 1 1 1 1 srmk sermk csimk3 wtmk wtimk tmmk51 tmmk50tmmk01 tmmk00 pmk2 pmk1 pmk0 vrmk vtmk vemk wdtmk
314 pd1615, pd16f15, pd1616 (3) priority specify flag registers (pr0l, pr0h, pr1l) the priority specify flag is used to set the corresponding maskable interrupt priority orders. pr0l, pr0h and pr1l are set with a 1-bit or 8-bit memory manipulation instruction. if if0l and if0h are used as a 16-bit register pr0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 18-4: priority specify flag register format cautions: 1. when a watchdog timer is used as a non-maskable interrupt, set 1 in wdtpr flag. 2. set always 1 in pr1l bit 2 to bit 7. 0 1 priority level selection high priority level low priority level 7 symbol pr0h 65432 10 address ffe9h 00h after reset r/w r/w pr1l ffeah 00h r/w pr0l ppr1 ffe8h 00h r/w ppr0 xxprx ppr2 tmpr00 vrpr vtpr vepr wdtpr srpr serpr csipr3 wtpr wtipr tmpr51 tmpr50 tmpr01 stpr adpr 0 0 0 0 0 0
315 pd1615, pd16f15, pd1616 (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) egp and egn specify the valid edge to be detected on pins p00 to p02. egp and egn can be read or written to with a 1-bit or 8-bit memory manipulation instruction. these registers are set to 00h when the reset signal is output. figure 18-5: formats of external interrupt rising edge enable register and external inter- rupt falling edge enable register egpn egnn valid edge of intpn pin (n = 0 C 4) 0 0 interrupt disable 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges symbol76543210addresson resetr/w egp00000egp2egp1egp0ff48h00hr/w symbol76543210addresson resetr/w egn00000egn2egn1egn0ff49h00hr/w
316 pd1615, pd16f15, pd1616 (5) program status word (psw) the program status word is a register to hold the instruction execution result and the current status for interrupt request. the ie flag to set maskable interrupt enable/disable and the isp flag to control multiple interrupt servicing are mapped. besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, and when the brk instruction is executed, the contents of psw automatically is saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the isp flag. the acknowledged contents of psw is also saved into the stack with the push psw instruction. it is reset from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 18-6: program status word format 7 ie psw 6 z 5 rbs1 4 ac 3 rbs0 2 0 <1> isp <0> cy 02h after reset isp 0 used when normal instruction is executed priority of interrupt currently being received high-priority interrupt servicing (low-priority interrupt disable) 1 interrupt request not acknowledged or low-priority interrupt servicing (all-maskable interrupts enable) ie interrupt request acknowledge enable/disable 0 disable 1 enable
317 pd1615, pd16f15, pd1616 18.4 interrupt servicing operations 18.4.1 non-maskable interrupt request acknowledge operation a non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. it does not undergo interrupt priority control and has highest priority over all other interrupts. if a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stacks, psw and pc, in that order, the ie and isp flags are reset to 0, and the vector table contents are loaded into pc and branched. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction is executed. if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution.
318 pd1615, pd16f15, pd1616 figure 18-7: flowchart from non-maskable interrupt generation to acknowledge wdtm: watchdog timer mode register wdt: watchdog timer figure 18-8: non-maskable interrupt request acknowledge timing wdtif: w atchdog timer interrupt request flag wdtm4 = 1 (with watchdog timer mode selected)? overflow in wdt? wdtm3 = 0 (with non-maskable interrupt selected)? interrupt request generation wdt interrupt servicing? interrupt control register unaccessed? interrupt service start interrupt request held pending reset processing interval timer start no ye s ye s no ye s no ye s no ye s no instruction instruction cpu instruction wdtif psw and pc save, jump to interrupt servicing interrupt sevicing program
319 pd1615, pd16f15, pd1616 figure 18-9: non-maskable interrupt request acknowledge operation (a) if a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution nmi request nmi request 1 instruction execution main routine nmi request reserve reserved nmi request processing nmi request nmi request 1 instruction execution main routine reserved although two or more nmi requests have been generated, only one request has been acknowledged. nmi request reserved
320 pd1615, pd16f15, pd1616 18.4.2 maskable interrupt request acknowledge operation a maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (mk) flag is cleared to 0. a vectored interrupt request is acknowledged in an interrupt enable state (with ie flag set to 1). however, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with isp flag reset to 0). wait times maskable interrupt request generation to interrupt servicing are as follows. table 18-3: times from maskable interrupt request generation to interrupt service minimum time maximum time note when xxprx = 0 7 clocks 32 clocks when xxprx = 1 8 clocks 33 clocks note: if an interrupt request is generated just before a divide instruction, the wait time is maximized. remark: 1 clock: (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specify flag is acknowledged first. if two or more requests are specified for the same priority with the priority specify flag, the interrupt request with the higher default priority is acknowledged first. any reserved interrupt requests are acknowledged when they become acknowledgeable. figure 18-10 shows interrupt request acknowledge algorithms. when a maskable interrupt request is acknowledged, the contents of program status word (psw) and program counter (pc) are saved to stacks, in this order. then, the ie flag is reset (to 0), and the value of the acknowledged interrupt priority specify flag is transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into pc and branched. return from the interrupt is possible with the reti instruction. f cpu 1
321 pd1615, pd16f15, pd1616 figure 18-10: interrupt request acknowledge processing algorithm xxif : interrupt request flag xxmk : interrupt mask flag xxpr : prio rity specify flag ie : flag to control maskable interrupt request acknowledge isp : flag to indicate the priority of interrupt being serviced (0 = an interrupt with higher priority is being serviced, 1 = interrupt request is not acknowledged or an interrupt with lower priority is being serviced) start xxif = 1? xxmk = 0? xxpr = 0? any simultaneously generated xxpr = 0 interrupts? ie = 1? isp = 1? vectored interrupt servicing interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve vectored interrupt servicing any high- priority interrupt among simultaneously generated xxpr = 0 interrupts? ie = 1? yes (high priority) ye s no ye s no no no yes (interrupt request generation) no ye s no (low priority) ye s ye s no ye s ye s no no any simultaneously generated high-priority interrupts?
322 pd1615, pd16f15, pd1616 figure 18-11: interrupt request acknowledge timing (minimum time) remark: 1 clock: (f cpu : cpu clock) figure 18-12: interrupt request acknowledge timing (maximum time) remark: 1 clock: (f cpu : cpu clock) f cpu 1 f cpu 1 18.4.3 software interrupt request acknowledge operation a software interrupt request is acknowledged by brk instruction execution. software interrupt cannot be disabled. if a software interrupt is acknowledged, the contents of program status word (psw) and program counter (pc) are saved to stacks, in this order. then the ie flag is reset (to 0), and the contents of the vector tables (003eh and 003fh) are loaded into pc and branched. return from the software interrupt is possible with the retb instruction. caution: do not use the reti instruction for returning from the software interrupt. instruction instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 8 clocks 7 clocks cpu processing xxif (xxpr = 1) xxif (xxpr = 0) instruction divide instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 33 clocks 32 clocks cpu processing xxif (xxpr = 1) xxif (xxpr = 0) 25 clocks
323 pd1615, pd16f15, pd1616 18.4.4 multiple interrupt servicing a multiple interrupt consists in acknowledging another interrupt during the execution of the interrupt. a multiple interrupt is generated only in the interrupt request acknowledge enable state (ie = 1) (except non-maskable interrupt). as soon as an interrupt request is acknowledged, it enters the acknowledge disable state (ie = 0). therefore, in order to enable a multiple interrupt, it is necessary to set the interrupt enable state by setting the ie flag (1) with the ei instruction during interrupt servicing. even in an interrupt enabled state, a multiple interrupt may not be enabled. however, it is controlled according to the interrupt priority. there are two priorities, the default priority and the programmable priority. the multiple interrupt is controlled by the programmable priority control. if an interrupt request with the same or higher priority than that of the interrupt being serviced is generated, it is acknowledged as a multiple interrupt. in the case of an interrupt with a priority lower than that of the interrupt being processed, it is not acknowledged as a multiple interrupt. interrupt request not acknowledged as a multiple interrupt due to interrupt disable or a low priority is reserved and acknowledged following one instruction execution of the main processing after the completion of the interrupt being serviced. during non-maskable interrupt servicing, multiple interrupts are not enabled. table 18-4 shows an interrupt request enabled for multiple interrupt during interrupt servicing, and figure 18-13 shows multiple interrupt examples. table 18-4: interrupt request enabled for multiple interrupt during interrupt servicing maskable interrupt request xxpr = 0 xxpr = 1 ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt d d d d d isp = 0 e e d d d isp = 1 e e d e d software interrupt e e d e d remarks: 1. e: multiple interrupt enable 2. d: multiple interrupt disable 3. isp and ie are the flags contained in psw isp = 0: an interrupt with higher priority is being serviced isp = 1: an interrupt request is not accepted or an interrupt with lower priority is being serviced ie = 0: interrupt request acknowledge is disabled ie = 1: interrupt request acknowledge is enabled 4. xxpr is a flag contained in pr0l, pr0h, and pril xxpr = 0: higher priority level xxpr = 1: lower priority level non-maskable interrupt request multiple interrupt request interrupt being serviced maskable interrupt
324 pd1615, pd16f15, pd1616 figure 18-13: multiple interrupt example (1/2) example 1. two multiple interrupts generated during interrupt intxx servicing, two interrupt requests, intyy and intzz are acknowledged, and a multiple interrupt is generated. an ei instruction is issued before each interrupt request acknowledge, and the interrupt request acknowledge enable state is set. example 2. multiple interrupt is not generated by priority control the interrupt request intyy generated during interrupt intxx servicing is not acknowledged because the interrupt priority is lower than that of intxx, and a multiple interrupt is not generated. intyy request is retained and acknowledged after execution of 1 instruction execution of the main processing. pr = 0 : higher priority level pr = 1 : lower priority level ie = 0 : interrupt request acknowledge disable main processing ei intxx (pr = 1) intyy (pr = 0) ie = 0 ei reti intxx servicing intzz (pr = 0) ie = 0 ei reti intyy servicing ie = 0 reti intzz servicing main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 1) ei ie = 0 ei reti reti
325 pd1615, pd16f15, pd1616 figure 18-13: multiple interrupt example (2/2) example 3. a multiple interrupt is not generated because interrupts are not enabled because interrupts are not enabled in interrupt intxx servicing (an ei instruction is not issued), interrupt request intyy is not acknowledged, and a multiple interrupt is not generated. the intyy request is reserved and acknowledged after 1 instruction execution of the main processing. pr = 0 : higher priority level ie = 0 : interrupt request acknowledge disable main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 0) ie = 0 reti reti ei
326 pd1615, pd16f15, pd1616 18.4.5 interrupt request reserve some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interupt request is generated during the execution. the following shows such instructions (interrupt request reserve instruction). ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw.bit, cy ? mov1 cy, psw.bit ? and1 cy, psw.bit ? or1 cy, psw.bit ? xor1 cy, psw.bit ? set1/clr1 psw.bit ? retb ? reti ? push psw ? pop psw ? bt psw.bit, $addr16 ? bf psw.bit, $addr16 ? btclrpsw.bit, $addr16 ?ei ?di ? manipulate instructions for if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, pr1l, intm0, intm1 registers caution: brk instruction is not an interrupt request reserve instruction described above. however, in a software interrupt started by the execution of brk instruction, the ie flag is cleared to 0. therefore, interrupt requests are not acknowledged even when a maskable interrupt request is issued during the execution of the brk instruction. however, non-maskable interrupt requests are acknowledged. figure 18-14 shows the interrupt request hold timing. figure 18-14: interrupt request hold remarks: 1. instruction n: instruction that holds interrupts requests 2. instruction m: instructions other than interrupt request pending instruction 3. the xxpr (priority level) values do not affect the operation of xxif (interrupt request). cpu processing xxif instruction n instruction m save psw and pc, jump to interrupt service interrupt service program
327 pd1615, pd16f15, pd1616 [memo]
328 pd1615, pd16f15, pd1616 chapter 19 standby function 19.1 standby function and configuration 19.1.1 standby function the standby function is designed to decrease power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. system clock oscillator continues oscillation. in this mode, current consumption cannot be decreased as in the stop mode. the halt mode is valid to restart immediately upon interrupt request and to carry out intermittent operations such as watch applications. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscillator stops and the whole system stops. cpu current consumption can be considerably decreased. data memory low-voltage hold (down to v dd = 2.0 v) is possible. thus, the stop mode is effective to hold data memory contents with ultra-low current consumption. because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is necessary to secure an oscillation stabilization time after the stop mode is cleared, select the halt mode if it is necessary to start processing immediately upon interrupt request. in any mode, all the contents of the register, flag, and data memory just before standby mode setting are held. the input/output port output latch and output buffer statuses are also held. cautions: 1. the stop mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). the halt mode can be used with either the main system clock or the subsystem clock. 2. when proceeding to the stop mode, be sure to stop the peripheral hardware operation and execute the stop instruction. 3. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (cs) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction.
329 pd1615, pd16f15, pd1616 19.1.2 standby function control register a wait time after the stop mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, it takes 2 17 /fx until the stop mode is cleared by reset input. figure 19-1: oscillation stabilization time select register format caution: the wait time after stop mode clear does not include the time (see a in the illustration below) from stop mode clear to clock oscillation start, regardless of clearance by reset input or by interrupt generation. remarks: 1. fx: main system clock oscillation frequency 2. values in parentheses apply to operating at fx = 8.00 mhz stop mode clear x1 pin voltage waveform v ss a address fffah 04h after reset r/w r/w 0 0 0 0 1 selection of oscillation stabilization time when stop mode is released 2 12 /f x 2 14 /f x 2 15 /f x 2 16 /f x 2 17 /f x osts2 7 0 symbol osts 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 0 0 1 1 0 other than above osts1 (512 s) (2 ms) (4.1 ms) (8.19 ms) (16.38 ms) 0 1 0 1 0 osts0 setting prohibited
330 pd1615, pd16f15, pd1616 19.2 standby function operations 19.2.1 halt mode (1) halt mode set and operating status the halt mode is set by executing the halt instruction. it can be set with the main system clock or the subsystem clock. the operating status in the halt mode is described below. table 19-1: halt mode operating status halt mode setting halt execution during main halt execution during system clock operation subsystem clock operation item (main system clock stops) clock generator both main and subsystem clocks can be oscillated / clock supply to the cpu stops cpu operation stops port (output latch) status before halt mode setting is held 16-bit timer /event counter (tm0) operable operable when ti00 is selected as count clock 8-bit timer event counter (tm50/tm51) operable operable when ti00 is selected as count clock watch timer operable operable when fxt is selected as count clock watchdog timer operable operation stops a/d converter operation stops serial i/f - sio30 operable operable at external sck serial i/f - uart operable operation stops van operable operation stops sound generator operable operation stops external interrupt (intp0 to intp2) operable lcd operable operation stops
331 pd1615, pd16f15, pd1616 (2) halt mode clear the halt mode can be cleared with the following four types of sources. (a) clear upon unmasked interrupt request an unmasked interrupt request is used to clear the halt mode. if interrupt acknowledge is enabled, vectored interrupt service is carried out. if disabled, the next address instruction is executed. figure 19-2: halt mode clear upon interrupt generation remarks: 1. the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. 2. wait time will be as follows: ? when vectored interrupt service is carried out: 8 to 9 clocks ? when vectored interrupt service is not carried out: 2 to 3 clocks (b) clear upon non-maskable interrupt request the halt mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled. halt instruction wait standby release signal operating mode clock halt mode wait oscillation operating mode
332 pd1615, pd16f15, pd1616 (c) clear upon reset input as is the case with normal reset operation, a program is executed after branch to the reset vector address. figure 19-3: halt mode release by reset input remarks: 1. fx: main system clock oscillation frequency 2. values in parentheses apply to operation at fx = 8.0 mhz table 19-2: operation after halt mode release release source mkxx prxx ie isp operation 0 0 0 x next address instruction execution 0 0 1 x interrupt service execution 0 1 0 1 0 1 x 0 next address instruction execution 0 1 1 1 interrupt service execution maskable interrupt request 1 x x x halt mode hold non-maskable interrupt request - - x x interrupt service execution reset input - - x x reset processing x: don't care. halt instruction reset signal operating mode clock reset period halt mode oscillation oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 16.3 ms)
333 pd1615, pd16f15, pd1616 19.2.2 stop mode (1) stop mode set and operating status the stop mode is set by executing the stop instruction. it can be set only with the main system clock. cautions: 1. when the stop mode is set, the x2 pin is internally connected to v dd via a pull- up resistor to minimize leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait set using the oscillation stabilization time select register (osts), the operating mode is set. the operating status in the stop mode is described below. table 19-3: stop mode operating status stop mode setting with subsystem clock without subsystem clock item clock generator only main system clock stops oscillation cpu operation stops port (output latch) status before stop mode setting is held 16-bit timer /event counter (tm0) operable when ti00 is selected as c ount clock 8-bit timer event counter 5 and 6 operable when ti50 or ti51 are selected as count clock watch timer operable when fxt is selected as count clock operation stops watchdog timer operation stops a/d converter operation stops serial i/f - sio30 operable at external sck serial i/f - uart operation stops van operation stops sound generator operation stops external interrupt (intp0 to intp2) operable lcd operation stops
334 pd1615, pd16f15, pd1616 (2) stop mode release the stop mode can be cleared with the following three types of sources. (a) release by unmasked interrupt request an unmasked interrupt request is used to release the stop mode. if interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 19-4: stop mode release by interrupt generation remark: the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. stop instruction wait (time set by osts) oscillation stabilization wait status operating mode oscillation operationg mode stop mode oscillation stop oscillation standby release signal clock
335 pd1615, pd16f15, pd1616 (b) release by reset input the stop mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. figure 19-5: release by stop mode reset input remarks 1. fx: main system clock oscillation frequency 2. values in parentheses apply to operation at fx = 5.0 mhz table 19-4: operation after stop mode release release source mkxx prxx ie isp operation 0 0 0 x next address instruction execution 0 0 1 x interrupt service execution 0 1 0 1 0 1 x 0 next address instruction execution 0 1 1 1 interrupt service execution maskable interrupt request 1 x x x stop mode hold non-maskable interrupt request - - x x interrupt service execution reset input - - x x reset processing x: dont care. reset signal operating mode clock reset period stop mode oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 16.3 ms) stop instruction oscillation
336 pd1615, pd16f15, pd1616 [memo]
337 pd1615, pd16f15, pd1616 chapter 20 reset function 20.1 reset function the following two operations are available to generate the reset signal. (1) external reset input with reset pin (2) internal reset by watchdog timer overrun time detection external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in table 20-1. each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. when a high level is input to the reset input, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (2 17 /fx). the reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (2 17 /fx) (see figure 20-2 to 20-4). cautions: 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pin becomes high-impedance. figure 20-1: block diagram of reset function reset count clock reset control circuit watchdog timer stop over- flow reset signal interrupt function
338 pd1615, pd16f15, pd1616 figure 20-2: timing of reset input by reset input figure 20-3: timing of reset due to watchdog timer overflow figure 20-4: timing of reset input in stop mode by reset input reset internal reset signal port pin delay delay high impedance x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 normal operation watchdog timer overflow internal reset signal port pin reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) high impedance reset internal reset signal port pin delay delay high impedance x1 normal operation normal operation (reset processing) stop instruction execution reset period (oscillation stop) oscillation stabilization time wait stop status (oscillation stop)
339 pd1615, pd16f15, pd1616 notes: 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remains unchanged after reset. 2. the post-reset status is held in the standby mode. table 20-1: hardware status after reset (1/2) hardware status after reset program counter (pc) note 1 the contents of reset vector tables (0000h and 0001h) are set stack pointer (sp) undefined program status word (psw) 02h data memory undefined) note 2 ram general register undefined) note 2 port (output latch) ports 0, 4, 8 to 12 (p0, p4, p8 to p12) 00h port mode register (pm0, pm4, pm8 to pm12) ffh port function register (pf8 to pf12) 00h processor clock control register (pcc) 04h memory size switching register (ims) cfh internal expansion ram size switching register (ixs) 0ch oscillation stabilization time select register (osts) 04h timer register (tm0) 0000h capture/compare register (cr00, cr01) 00h prescaler selection register (prm0) 00h mode control register (tmc0) 00h capture/compare control register 0 (crc0) 00h 16-bit timer/event counter 0 output control register (toc0) 00h timer register (tm50, tm51) 00h compare register (cr50, cr51) 00h clock select register (tlc50, tlc51) 00h 8-bit timer/event counters 50 and 51 mode control register (tmc50, tmc51) 04h watch timer mode register (wtm) 00h clock selection register (wdcs) 00h watchdog timer mode register (wdtm) 00h pcl clock output clock output selection register (cks) 00h control register (sgcr) 00h amplitude control register (sgam) 00h sound generator buzzer control register (sgbc) 00h
340 pd1615, pd16f15, pd1616 table 20-1: hardware status after reset (2/2) hardware status after reset operating mode register 0 (csim30) 00h shift register 0 (csio30) 00h operating mode register 1 (csim31) 00h shift register 1 (csio31) 00h asynchronous mode register (asim0) 00h asynchronous status register (asis0) 00h baudrate generator control register (brgc0) 00h transmit shift register (txs0) serial interface receive buffer register (rxb0) ffh mode register (adm1) 00h conversion result register (adcr1) 00h input select register (ads1) 00h power fail comparator mode (pfm) 00h a/d converter power fail threshold register (pft) 00h mode register (lcdm) 00h lcd controller/driver control register (lcdc) 00h request flag register (if0l, if0h, if1l) 00h mask flag register (mk0l, mk0h, mk1l) ffh priority specify flag register (pr0l, pr0h, pr1l) ffh external interrupt rising edge register (egp) 00h interrupt external interrupt falling edge register (egn) 00h van udl clock control register (udlccl) 00h
341 pd1615, pd16f15, pd1616 [memo]
342 pd1615, pd16f15, pd1616 chapter 21 pd16f15 the pd16f15 replaces the internal mask rom of the pd1615 / pd1616 with flash memory to which a program can be written, deleted and overwritten while mounted on the substrate. table 21-1 lists the differences among the pd16f15 and the mask rom versions. table 21-1: differences among pd16f15 and mask rom versions caution: flash memory versions and mask rom versions differ in their noise tolerance and noise emission. if replacing flash memory versions with mask rom versions when changing from test production to mass production, be sure to perform sufficient evaluation with cs versions (not es versions) of mask rom versions. item pd16f15 mask rom versions ic pin none available v pp pin available none electrical characteristics see data sheet of each product
343 pd1615, pd16f15, pd1616 21.1 memory size switching register (ims) this register specifies the internal memory size by using the memory size switching register (ims), so that the same memory map as on the mask rom version can be achieved. ims is set with an 8-bit memory manipulation instruction. reset input sets this register to cfh. figure 21-1: memory size switching register format note: the values after reset depend on the product (see table 21-2). table 21-2: values of the memory size switching register for the different devices part number value pd1615, pd1616 c8h pd16f15 cfh 7 ram2 symbol ims 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 address fff0h note after reset r/w r/w internal rom size selection rom3 60 kbytes 1 rom2 1 rom1 1 rom0 1 setting prohibited other than above ram2 ram1 ram0 internal high-speed ram size selection 1024 bytes 110 setting prohibited other than above 1 32 kbytes 000 caution: when the pd1615/16f15 and the pd1616 are used, be sure to set the value of the ims register as given in the table 21-2.
344 pd1615, pd16f15, pd1616 21.2 internal extension ram size switching register the pd16f15 allow users to define its internal expansion ram size by using the internal expansion ram size switching register (ixs), so that the same memory mapping as that of a mask rom version with a different internal extension ram is possible. the ixs is set by an 8-bit memory manipulation instruction. reset signal input sets ixs to 0ch. caution: when the pd1615/pd16f15 and the pd1616 are used, be sure to set the value specified in the table 21-3 to ixs. other settings are prohibited. figure 21-2: internal extension ram size switching register format table 21-3: examples of internal extension ram size switching register settings the value whitch is set in the ixs that has the identical memory map to the mask rom versions is given in the table 21-3. symbol 7 6 5 4 3 2 1 0 address after reset r/w ixs 0 0 0 0 ixram3 ixram2 ixram1 ixram0 fff4h 0ch w ixram3 ixram2 ixram1 ixram0 internal extension ram capacity selection 1 0 1 1 512 bytes 1 0 1 0 1024 bytes other than above setting prohibited relevant mask rom version ixs setting pd1615, pd1616 0bh pd16f15 0ah caution: when the pd1615/16f15 and the pd1616 are used, be sure to set the value of the ixs register as given in the table 21-3.
345 pd1615, pd16f15, pd1616 21.3.2 initialization of the programming mode when v pp reaches up to 10 v with reset terminal activated, on-board programming mode becomes available. after release of reset, the programming mode is selected by the number of v pp pulses. 21.3 flash memory programming on-board writing of flash memory (with device mounted on target system) is supported. on-board writing is done after connecting a dedicated flash writer to the host machine and target system. moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to the flash programmer. 21.3.1 selection of transmission method writing to flash memory is performed using flashpro and serial communication. select the transmission method for writing from table 21-4. for the selection of the transmission method, a format like the one shown in figure 21-3 is used. the transmission methods are selected with the v pp pulse numbers shown in table 21-4. table 21-4 transmission method list cautions: 1. be sure to select the number of vpp pulses shown in table 25-3 for the transmission method. 2. if performing write operations to flash memory with the uart transmission method, set the main system clock oscillation frequency to 4 mhz or higher. figure 21-3: transmission method selection format transmission method number of channels pin used number of v pp pulses 3-wire serial i/o 1 si3/p127 so3/p126 sck3/p125 1 pseudo 3-wire serial i/o 1 p40 (serial clock input) p41(serial data input) p42(serial data input) 12 uart 1 rxd0/p123 txd0/p124 8 10 v v pp reset v dd v ss v dd v ss v pp pulses flash write mode
346 pd1615, pd16f15, pd1616 21.3.3 flash memory programming function flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. the main functions are listed in table 21-5. table 21-5: main functions of flash memory programming function description reset detects write stop and transmission synchronization. batch verify compares entire memory contents and input data. batch delete deletes the entire memory contents. batch blank check checks the deletion status of the entire memory. high-speed write performs writing to flash memory according to write start address and number of write data (bytes). continuous write performs successive write operations using the data input with high-speed write operation. status checks the current operation mode and operation end. oscillation frequency setting inputs the resonator oscillation frequency information. delete time setting inputs the memory delete time. baud rate setting sets the transmission rate when the uart method is used. silicon signature read outputs the device name, memory capacity, and device block information. 21.3.4 flashpro connection connection of flashpro and pd16f15 differs depending on communication method (3-wire serial i/ o, uart). each case of connection shows in figures 21-4, 21-5 and 21-6. figure 21-4: connection of flashpro using 3-wire serial i/o method v pp v dd reset sck so si gnd v pp v dd reset sck3 si3 so3 v ss flash programmer pd 16f15
347 pd1615, pd16f15, pd1616 figure 21-5: flashpro connection using uart method figure 21-6: flashpro connection using pseudo 3-wire serial i/o v pp : 10.3 v applied from the on-board programming tool. reset: a reset is generated and the device is set to the on-board programming mode. system clock: the cpu clock for the device may be supplied by the on-board program tool. alternatively the crystal or ceramic oscillator on the target h/w can be used in the on-board programming mode. the external system clock has to be connected with the x1 pin on the device. v dd : the power supply for the device may be supplied by the on-board program tool. alternatively the power supply on the target h/w can be used in the on-board programming mode. gnd: ground level v ss . sck: serial clock generated by the on-board programming tool. si: serial data sent by the on-board programming tool. so: serial data sent by the device. r x d0: serial data sent by the on-board programming tool. t x d0: serial data sent by the device. 21.3.5 flash programming precautions ? please make sure that the signals used by the on-board programming tool do not conflict with other devices on the target h/w. ? a read functionality is not supported because of software protection. only a verify operation of the whole flash eprom is supported. in verify mode data from start address to final address (efffh) has to be supplied by the programming tool. the device compares each data with on-chip flash content and replies with a signal for o.k. or not o.k. v pp v dd reset so si gnd v pp v dd reset rxd0 txd0 v ss pd 16f15 flash programmer v pp v dd reset sck so si gnd v pp v dd reset (serial clock input) (serial data input) (serial data output) v ss pd 16f15 flash programmer
348 pd1615, pd16f15, pd1616 [memo]
349 pd1615, pd16f15, pd1616 chapter 22 instruction set this chapter describes each instruction set of the pd1615 subseries as list table. for details of its operation and operation code, refer to the separate document 78k/0 series users manual - instruction (u12326e) .
350 pd1615, pd16f15, pd1616 22.1 legends used in operation list 22.1.1 operand identifiers and description methods operands are described in operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. each symbol has the following meaning. ? # : immediate data specification ? ! : absolute address specification ? $ : relative address specification ? [ ] : indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 22-1: operand identifiers and description methods identifier description method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h-ff1fh immediate data or labels saddrp fe20h-ff1fh immediate data or labels (even address only) addr16 0000h-ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h-0fffh immediate data or labels addr5 0040h-007fh immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note: addresses from ffd0h to ffdfh cannot be accessed with these operands. remark: for special-function register symbols, refer to "table 3-3: special-function register list".
351 pd1615, pd16f15, pd1616 22.1.2 description of operation column a : a register; 8-bit accumulator x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag rbs : register bank select flag ie : interrupt request enable flag nmis : non-maskable interrupt servicing flag ( ) : memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16 : 16-bit immediate data or label jdisp8 : s igned 8-bit data (displacement value) 22.1.3 description of flag operation column (blank) : not affected 0 : cleared to 0 1 : set to 1 x : set/cleared according to the result r : previously saved value is restored
352 pd1615, pd16f15, pd1616 22.2 operation list clock flag note 1 note 2 zaccy r, #byte 2 4 C r ? byte saddr, #byte 3 6 7 (saddr) ? byte sfr, #byte 3 C 7 sfr ? byte a, r note 3 12 Ca ? r r, a note 3 12 Cr ? a a, saddr 2 4 5 a ? (saddr) saddr, a 2 4 5 (saddr) ? a a, sfr 2 C 5 a ? sfr sfr, a 2 C 5 sfr ? a a, !addr16 3 8 9 + n a ? (addr16) !addr16, a 3 8 9 + m (addr16) ? a psw, #byte 3 C 7 psw ? byte x x x a, psw 2 C 5 a ? psw psw, a 2 C 5 psw ? axxx a, [de] 1 4 5 + n a ? (de) [de], a 1 4 5 + m (de) ? a a, [hl] 1 4 5 + n a ? (hl) [hl], a 1 4 5 + m (hl) ? a a, [hl + byte] 2 8 9 + n a ? (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) ? a a, [hl + b] 1 6 7 + n a ? (hl + b) [hl + b], a 1 6 7 + m (hl + b) ? a a, [hl + c] 1 6 7 + n a ? (hl + c) [hl + c], a 1 6 7 + m (hl + c) ? a a, r note 3 12 Ca ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 C 6 a ? (sfr) a, !addr16 3 8 10 + n + m a ? (addr16) xch a, [de] 1 4 6 + n + m a ? (de) a, [hl] 1 4 6 + n + m a ? (hl) a, [hl + byte] 2 8 10 + n + m a ? (hl + byte) a, [hl + b] 2 8 10 + n + m a ? (hl + b) a, [hl + c] 2 8 10 + n + m a ? (hl + c) notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed. 3. except r = a remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group 8-bit data transfer mov
353 pd1615, pd16f15, pd1616 clock flag note 1 note 2 zaccy rp, #word 3 6 C rp ? word saddrp, #word 4 8 10 (saddrp) ? word sfrp, #word 4 C 10 sfrp ? word ax, saddrp 2 6 8 ax ? (saddrp) saddrp, ax 2 6 8 (saddrp) ? ax movw ax, sfrp 2 C 8 ax ? sfrp sfrp, ax 2 C 8 sfrp ? ax ax, rp note 3 1 4 C ax ? rp rp, ax note 3 1 4 C rp ? ax ax, !addr16 3 10 12 + 2n ax ? (addr16) !addr16, ax 3 10 12 + 2m (addr16) ? ax xchw ax, rp note 3 1 4 C ax rp a, #byte 2 4 C a, cy ? a + byte x x x saddr, #byte 3 6 8 (saddr), cy ? (saddr) + byte x x x a, r note 4 2 4 C a, cy ? a + r x x x r, a 2 4 C r, cy ? r + a x x x a, saddr 2 4 5 a, cy ? a + (saddr) x x x a, !addr16 3 8 9 + n a, cy ? a + (addr16) x x x a, [hl] 1 4 5 + n a, cy ? a + (hl) x x x a, [hl + byte] 2 8 9 + n a, cy ? a + (hl + byte) x x x a, [hl + b] 2 8 9 + n a, cy ? a + (hl + b) x x x a, [hl + c] 2 8 9 + n a, cy ? a + (hl + c) x x x a, #byte 2 4 C a, cy ? a + byte + cy x x x saddr, #byte 3 6 8 (saddr), cy ? (saddr) + byte + cy x x x a, r note 4 2 4 C a, cy ? a + r + cy x x x r, a 2 4 C r, cy ? r + a + cy x x x a, saddr 2 4 5 a, cy ? a + (saddr) + cy x x x a, !addr16 3 8 9 + n a, cy ? a + (addr16) + cy x x x a, [hl] 1 4 5 + n a, cy ? a + (hl) + cy x x x a, [hl + byte] 2 8 9 + n a, cy ? a + (hl + byte) + cy x x x a, [hl + b] 2 8 9 + n a, cy ? a + (hl + b) + cy x x x a, [hl + c] 2 8 9 + n a, cy ? a + (hl + c) + cy x x x notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except r = a remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group 16-bit data transfer add addc 8-bit operation
354 pd1615, pd16f15, pd1616 clock flag note 1 note 2 zaccy a, #byte 2 4 C a, cy ? a C byte x x x saddr, #byte 3 6 8 (saddr), cy ? (saddr) C byte x x x a, r note 3 2 4 C a, cy ? a C r x x x r, a 2 4 C r, cy ? r C a x x x a, saddr 2 4 5 a, cy ? a C (saddr) x x x a, !addr16 3 8 9 + n a, cy ? a C (addr16) x x x a, [hl] 1 4 5 + n a, cy ? a C (hl) x x x a, [hl + byte] 2 8 9 + n a, cy ? a C (hl + byte) x x x a, [hl + b] 2 8 9 + n a, cy ? a C (hl + b) x x x a, [hl + c] 2 8 9 + n a, cy ? a C (hl + c) x x x a, #byte 2 4 C a, cy ? a C byte C cy x x x saddr, #byte 3 6 8 (saddr), cy ? (saddr) C byte C cy x x x a, r note 3 2 4 C a, cy ? a C r C cy x x x r, a 2 4 C r, cy ? r C a C cy x x x a, saddr 2 4 5 a, cy ? a C (saddr) C cy x x x a, !addr16 3 8 9 + n a, cy ? a C (addr16) C cy x x x a, [hl] 1 4 5 + n a, cy ? a C (hl) C cy x x x a, [hl + byte] 2 8 9 + n a, cy ? a C (hl + byte) C cy x x x a, [hl + b] 2 8 9 + n a, cy ? a C (hl + b) C cy x x x a, [hl + c] 2 8 9 + n a, cy ? a C (hl + c) C cy x x x a, #byte 2 4 C a ? a byte x saddr, #byte 3 6 8 (saddr) ? (saddr) byte x a, r note 3 24 Ca ? a rx r, a 2 4 C r ? r ax a, saddr 2 4 5 a ? a (saddr) x a, !addr16 3 8 9 + n a ? a (addr16) x a, [hl] 1 4 5 + n a ? a [hl] x a, [hl + byte] 2 8 9 + n a ? a [hl + byte] x a, [hl + b] 2 8 9 + n a ? a [hl + b] x a, [hl + c] 2 8 9 + n a ? a [hl + c] x mnemonic operands byte operation instruction group sub subc and 8-bit operation notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from.
355 pd1615, pd16f15, pd1616 clock flag note 1 note 2 zaccy a, #byte 2 4 C a ? a byte x saddr, #byte 3 6 8 (saddr) ? (saddr) byte x a, r note 3 24 Ca ? a rx r, a 2 4 C r ? r ax a, saddr 2 4 5 a ? a (saddr) x a, !addr16 3 8 9 + n a ? a (addr16) x a, [hl] 1 4 5 + n a ? a (hl) x a, [hl + byte] 2 8 9 + n a ? a (hl + byte) x a, [hl + b] 2 8 9 + n a ? a (hl + b) x a, [hl + c] 2 8 9 + n a ? a (hl + c) x a, #byte 2 4 C a ? a byte x saddr, #byte 3 6 8 (saddr) ? (saddr) byte x a, r note 3 24 Ca ? a rx r, a 2 4 C r ? r ax a, saddr 2 4 5 a ? a (saddr) x a, !addr16 3 8 9 + n a ? a (addr16) x a, [hl] 1 4 5 + n a ? a (hl) x a, [hl + byte] 2 8 9 + n a ? a (hl + byte) x a, [hl + b] 2 8 9 + n a ? a (hl + b) x a, [hl + c] 2 8 9 + n a ? a (hl + c) x a, #byte 2 4 C a C byte x x x saddr, #byte 3 6 8 (saddr) C byte x x x a, r note 3 24 Ca C r xxx r, a 2 4 C r C a x x x a, saddr 2 4 5 a C (saddr) x x x a, !addr16 3 8 9 + n a C (addr16) x x x a, [hl] 1 4 5 + n a C (hl) x x x a, [hl + byte] 2 8 9 + n a C (hl + byte) x x x a, [hl + b] 2 8 9 + n a C (hl + b) x x x a, [hl + c] 2 8 9 + n a C (hl + c) x x x notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. mnemonic operands byte operation instruction group or xor cmp 8-bit operation
356 pd1615, pd16f15, pd1616 clock flag note 1 note 2 zaccy addw ax, #word 3 6 C ax, cy ? ax + word x x x subw ax, #word 3 6 C ax, cy ? ax C word x x x cmpw ax, #word 3 6 C ax C word x x x mulu x 2 16 C ax ? a x x divuw c 2 25 C ax (quotient), c (remainder) ? ax c r12Cr ? r + 1 x x saddr 2 4 6 (saddr) ? (saddr) + 1 x x r12Cr ? r C 1 x x saddr 2 4 6 (saddr) ? (saddr) C 1 x x incw rp 1 4 C rp ? rp + 1 decw rp 1 4 C rp ? rp C 1 ror a, 1 1 2 C (cy, a 7 ? a 0 , a m C 1 ? a m ) x 1 time x rol a, 1 1 2 C (cy, a 0 ? a 7 , a m + 1 ? a m ) x 1 time x rorc a, 1 1 2 C (cy ? a 0 , a 7 ? cy, a m C 1 ? a m ) x 1 time x rolc a, 1 1 2 C (cy ? a 7 , a 0 ? cy, a m + 1 ? a m ) x 1 time x a 3 C 0 ? (hl) 3 C 0 , (hl) 7 C 4 ? a 3 C 0 , (hl) 3 C 0 ? (hl) 7 C 4 a 3 C 0 ? (hl) 7 C 4 , (hl) 3 C 0 ? a 3 C 0 , (hl) 7 C 4 ? (hl) 3 C 0 decimal adjust accumulator after addition decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy ? (saddr.bit) x cy, sfr.bit 3 C 7 cy ? sfr.bit x cy, a.bit 2 4 C cy ? a.bit x cy, psw.bit 3 C 7 cy ? psw.bit x cy, [hl].bit 2 6 7 + n cy ? (hl).bit x saddr.bit, cy 3 6 8 (saddr.bit) ? cy sfr.bit, cy 3 C 8 sfr.bit ? cy a.bit, cy 2 4 C a.bit ? cy psw.bit, cy 3 C 8 psw.bit ? cy x x [hl].bit, cy 2 6 8 + n + m (hl).bit ? cy notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. ror4 [hl] 2 10 12 + n + m rol4 [hl] 2 10 12 + n + m adjba 24 C xxx adjbs 24 C xxx mnemonic operands byte operation instruction group inc 16-bit operation increment/ decrement dec rotate bcd adjust mov1 bit manipu- late multiply/ divide
357 pd1615, pd16f15, pd1616 clock flag note 1 note 2 zaccy cy, saddr.bit 3 6 7 cy ? cy (saddr.bit) x cy, sfr.bit 3 C 7 cy ? cy sfr.bit x and1 cy, a.bit 2 4 C cy ? cy a.bit x cy, psw.bit 3 C 7 cy ? cy psw.bit x cy, [hl].bit 2 6 7 + n cy ? cy (hl).bit x cy, saddr.bit 3 6 7 cy ? cy (saddr.bit) x cy, sfr.bit 3 C 7 cy ? cy sfr.bit x or1 cy, a.bit 2 4 C cy ? cy a.bit x cy, psw.bit 3 C 7 cy ? cy psw.bit x cy, [hl].bit 2 6 7 + n cy ? cy (hl).bit x cy, saddr.bit 3 6 7 cy ? cy (saddr.bit) x cy, sfr.bit 3 C 7 cy ? cy sfr.bit x xor1 cy, a.bit 2 4 C cy ? cy a.bit x cy, psw. bit 3 C 7 cy ? cy psw.bit x cy, [hl].bit 2 6 7 + n cy ? cy (hl).bit x saddr.bit 2 4 6 (saddr.bit) ? 1 sfr.bit 3 C 8 sfr.bit ? 1 set1 a.bit 2 4 C a.bit ? 1 psw.bit 2 C 6 psw.bit ? 1 xxx [hl].bit 2 6 8 + n + m (hl).bit ? 1 saddr.bit 2 4 6 (saddr.bit) ? 0 sfr.bit 3 C 8 sfr.bit ? 0 clr1 a.bit 2 4 C a.bit ? 0 psw.bit 2 C 6 psw.bit ? 0 xxx [hl].bit 2 6 8 + n + m (hl).bit ? 0 set1 cy 1 2 C cy ? 11 clr1 cy 1 2 C cy ? 00 not1 cy 1 2 C cy ? cy x notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. mnemonic operands byte operation instruction group bit manipu- late
358 pd1615, pd16f15, pd1616 mnemonic operands byte operation instruction group call !addr16 3 7 C callt [addr5] 1 6 C retb 16 C rrr ret 16 C rp 1 4 C rp 1 4 C push pop uncondi- tional branch stack manipu- late conditional branch call/return clock flag note 1 note 2 zaccy (sp C 1) ? (pc + 3) h , (sp C 2) ? (pc + 3) l , pc ? addr16, sp ? sp C 2 (sp C 1) ? (pc + 2) h , (sp C 2) ? (pc + 2) l , callf !addr11 2 5 C pc 15 C 11 ? 00001, pc 10 C 0 ? addr11, sp ? sp C 2 (sp C 1) ? (pc + 1) h , (sp C 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp C 2 (sp C 1) ? psw, (sp C 2) ? (pc + 1) h , brk 1 6 C (sp C 3) ? (pc + 1) l , pc h ? (003fh), pc l ? (003eh), sp ? sp C 3, ie ? 0 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 pc h ? (sp + 1), pc l ? (sp), reti 1 6 C psw ? (sp + 2), sp ? sp + 3, r r r nmis ? 0 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3 psw 1 2 C (sp C 1) ? psw, sp ? sp C 1 (sp C 1) ? rp h , (sp C 2) ? rp l , sp ? sp C 2 psw 1 2 C psw ? (sp), sp ? sp + 1 r r r rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 sp, #word 4 C 10 sp ? word movw sp, ax 2 C 8 sp ? ax ax, sp 2 C 8 ax ? sp !addr16 3 6 C pc ? addr16 br $addr16 2 6 C pc ? pc + 2 + jdisp8 ax 2 8 C pc h ? a, pc l ? x bc $addr16 2 6 C pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 C pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 C pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 C pc ? pc + 2 + jdisp8 if z = 0 notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program.
359 pd1615, pd16f15, pd1616 clock flag note 1 note 2 zaccy saddr.bit, $addr16 3 8 9 pc ? pc + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 C 11 pc ? pc + 4 + jdisp8 if sfr.bit = 1 bt a.bit, $addr16 3 8 C pc ? pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 C 9 pc ? pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 + n pc ? pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc ? pc + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 C 11 pc ? pc + 4 + jdisp8 if sfr.bit = 0 bf a.bit, $addr16 3 8 C pc ? pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 C 11 pc ? pc + 4 + jdisp8 if psw. bit = 0 [hl].bit, $addr16 3 10 11 + n pc ? pc + 3 + jdisp8 if (hl).bit = 0 pc ? pc + 4 + jdisp8 saddr.bit, $addr16 4 10 12 if(saddr.bit) = 1 then reset(saddr.bit) pc ? pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit btclr pc ? pc + 3 + jdisp8 if a.bit = 1 then reset a.bit pc ? pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit pc ? pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b ? b C 1, then pc ? pc + 2 + jdisp8 if b 1 0 c ? c C1, then pc ? pc + 2 + jdisp8 if c 1 0 (saddr) ? (saddr) C 1, then pc ? pc + 3 + jdisp8 if(saddr) 1 0 sel rbn 2 4 C rbs1, 0 ? n nop 1 2 C no operation ei 2 C 6 ie ? 1(enable interrupt) di 2 C 6 ie ? 0(disable interrupt) halt 2 6 C set halt mode stop 2 6 C set stop mode notes: 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks: 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the pcc register. 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. sfr.bit, $addr16 4 C 12 a.bit, $addr16 3 8 C psw.bit, $addr16 4 C 12 x x x [hl].bit, $addr16 3 10 12 + n + m b, $addr16 2 6 C dbnz c, $addr16 2 6 C saddr. $addr16 3 8 10 mnemonic operands byte operation instruction group cpu control conditional branch
360 pd1615, pd16f15, pd1616 22.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz
361 pd1615, pd16f15, pd1616 second operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none first operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note: except r = a
362 pd1615, pd16f15, pd1616 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note: only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 #word ax rp note sfrp saddrp !addr16 sp none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none
363 pd1615, pd16f15, pd1616 ax !addr16 !addr11 [addr5] $addr16 (4) call/instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
364 pd1615, pd16f15, pd1616 [memo]
365 pd1615, pd16f15, pd1616 appendix a development tools the following development tools are available for the development of systems that employ the pd1615 subseries. figure a-1 shows the development tool configuration. figure a-1: development tool configuration ?realtime os, os ?fuzzy inference development support system language processing software ?assembler package ?c compiler package ?c library source file ?system simulator ?integrated debugger ?device file embedded software flash memory write adapter in-circuit emulator cpu core board probe board emulation probe conversion socket or conversion adapter target system host machine (pc or ews) interface adapter i/o board on-chip flash memory version flash memory flash writer
366 pd1615, pd16f15, pd1616 a.1 language processing software ra78k/0 assembler package cc78k/0 c compiler package df1615 note 1, 2 device file cc78k/0-l c library source file notes: 1. used in common with ra78k/0, cc78k0, sm78k0 and id78k0. 2. under development remark: xxxx in the part number differs depending on the host machine and os used. sxxxxra78k0 sxxxxcc78k0 sxxxxdf780948 sxxxxcc78k0-l xxxx host m achine os supply medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver.3.30 to ver.6.2 note ) 5-inch 2hd 7b13 ibm pc/at or compatible see a.4 3.5-inch 2hd 7b10 5-inch 2hd 3h15 hp9000 series 300 tm hp-ux tm (rel.7.05b) cartrige tape (qic-24) 3p16 hp9000 series 700 tm hp-ux (rel.9.01) digital audio tape (dat) 3k15 sparcstation tm sunos tm (rel.4.1.1) cartridge tape (qic-24) 3m15 ews4800 series (risc) ews-ux/v (rel.4.0) note: the task swap function is not supported by the software listed above, although it is provided in ms-dos version 5.0 and later. this assembler converts programs written in mnemonics into an object code executable with a microcomputer. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler is used in combination with an optional device file (df780949). part number: sxxxxra78k0 this compiler converts programs written in c language into object code executable with a microcomputer. this compiler is used in combination with an optional assembler package (ra78k/0) and device file (1615). part number: sxxxxcc78k0 this file contains information peculiar to the device. this file is used in combination with the ra78k/0, cc78k/0, sm78k0, and id78k0. part number: sxxxxdf1615 this is a source program of functions configuring the object library included in the c compiler package (cc78k/0). it is required for matching the object library included in the cc78k/0 with to the customers specifications. part number: sxxxxcc78k0-l
367 pd1615, pd16f15, pd1616 a.2 flash memory writing tools flashpro flash writer flash memory writing adapter fa-80gc-sl a.3 debugging tools a.3.1 hardware dedicated flash writer for microcontrollers with on-chip flash memory. flashpro is a product of naitoudensei machida seisakusho, co., ltd. pd1615 subseries flash memory writing adapter used connected to flashpro. these are products of naitoudensei machida seisakusho, co., ltd. ? fa-80gc-sl: 80-pin plastic qfp (14 x 14 mm) note: under development. ie-78001-r-a note in-circuit emulator in-circuit emulator serves to debug hardware and software when developing application systems using the 78k/0 series. it corresponds to integrated debugger id78k0. this emulator is used in combination with an emulation probe an interface adapter for connection to a host mashine. ie-70000-pc-if-c interface adapter this adapter is required when using an ibm pc/at or compatible as the ie- 780000-sl host mashine. ie-78k/0-ns-p04 note i/o board this board is used to perform emulation of device specific peripheral hardware. this board is used in combination with an in-circuit emulator and probe board. ie-1615-ns-em4 probe board this board is used to perform pin connection changes. ie-78k0-r-ex1 probe extender board this board is used for a pin connection change betwwen the probe board and the probe. ep-78230gc-r emulation probe this probe is used to connect the in-circuit emulator and the target system. it is for 80-pin plastic qfp. an 80-pin conversion socket is included to facilitate target system development. ev-9200gc-80 this conversion socket is used to connect a target system substrate designed to allow mounting of the 80-pin plastic qfp and the ep-78230gc-r.
368 pd1615, pd16f15, pd1616 a.3.2 software (1/2) sm78k0 this system simulator is used to perform debugging at c source level or assembler system simulator level while simulating the operatin of the target system on a host machine. the sm78k0 operates on windows. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. part number: sxxxxsm78k0-l remark: xxxx in the part number differs depending on the host machine and os used. sxxxxsm78k0 xxxx h ost machine os supply medium aa13 pc-9800 series ms-dos (ver.3.30 to ver.6.2 note ) + 3.5-inch 2hd windows (ver. 3.0 to ver. 3.1) ab13 ibm pc/at and compatible see a.4 3.5-inch 2hc (windows japanese version) bb13 ibm pc/at and compatible 3.5-inch 2hc (windows english version) note: 1. the task swap funtion is not supported by the software listed above, although it is provided in ms-dos version 5.0 and later. 2. the system simulator does not support the pd1615 subseries.
369 pd1615, pd16f15, pd1616 a.3.2 software (2/2) id78k0 integrated debugger df1615 notes 1, 2 device file notes: 1. the df1615 can be used in conjunction with the ra78k/0, cc78k/0, sm78k0 and id78k0. 2. under development. remark: xxxx in the part number differs depending on the host machine and os used. sxxxxid78k0 sxxxxdf1615 xxxx host machine os supply medium aa13 pc-9800 series ms-dos (ver.3.30 to ver.6.2 note ) + 3.5-inch 2hd windows (ver. 3.1) ab13 ibm pc/at or compatible see a.4 3.5-inch 2hc (japanese windows) bb13 ibm pc/at or compatible 3.5-inch 2hc (english windows) 3p16 hp9000 series 700 hp-ux (rel.9.01) digital audio tape (dat) 3k15 sparcstation sunos (rel.4.1.1) cartridge tape (qic-24) 3k13 3.5-inch 2hc 3r16 news tm (risc) news-os tm (6.1x) 1/4 inch cgmt 3r13 3.5-inch 2hc 3m15 ews4800 series (risc) ews-ux/v (rel.4.0) cartridge tape (qic-24) note: the task swap function is not supported by the software listed above, although it is provided in ms-dos version 5.0 and later. this is a control program used to debug the 78k/0 series. the graphical user interfaces employed are windows for personal computers and osf/motif for ewss, offering the standard appearance and operability typical of these interfaces. further, debugging functions supporting c language are rein- forced, and the trace result can be displayed in c language level by using a window integrating function that associates the source program, disassemble display, and memory display with the trace result. in addition, it can enhance the debugging efficiency of a program using a real-time os by incorporating function expansion modules such as a task debugger and system performance analyzer. this debugger is used in combination with an optional device file. part number: s xxxx id78k0 file containing information peculiar to the device. used in combination with optional ra78k/0, cc78k/0, sm78k0, or id78k0. part number: s xxxx df1615.
370 pd1615, pd16f15, pd1616 a.4 os for ibm pc the following oss for ibm pcs are supported. to operate sm78k0, id78k0, and fe9200 (see b.2 fuzzy inference development support system ), windows (ver. 3.0 to ver. 3.1) is necessary. os version pc dos ver. 5.02 to ver. 6.3 j6.1/v note to j6.3v note ibm dos tm j5.02/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note note: only english mode is supported. caution: alt hough ver. 5.0 and above have a task swapping function, this function cannot be used with this software.
371 pd1615, pd16f15, pd1616 a.5 development environment when using ie-78001-r-a when using the ie-78001-r-a as the in-circuit emulator, the following debugging tools are required. ie-78001-r-a in-circuit emulator in-circuit emulator is used to debug hardware and software when an application systems using the 78k/0 series is developed. it suports the integrated debugger id78k0. this emulator is used in combination with an emulation probe and an interface adapter that connects the emulator with the host mashine.. ie-70000-98-if-b ie-70000-98n-in ie-70000-pc-if-c interface adapter see a.3.1 hardware e-78000-r-sv3 interface adapter adapter cable necessary when using an ews as the host mashine of the ie- 780000-r-a. this cable is connected to the board in the ie-780000-r-a. as ethernet tm , 10base-5 is supported. if other methods are used, a commercially available conversion adapter is necessary. ie-78k/0-ns-p04 i/o board ie-1615-ns-em4 probe board ie-78k0-r-ex1 probe extender board ep-78230gc-r emulation probe ev-9200gc-80 see also a.3.1 hardware
372 pd1615, pd16f15, pd1616 [memo]
373 pd1615, pd16f15, pd1616 appendix b embedded software for efficient development and maintenance of the pd1615 subseries, the following embedded software products are available.
374 pd1615, pd16f15, pd1616 b.1 real-time os (1/2) rx78k/0 rx78k/0 is a real-time os conforming with the itron specifications. real-time os tool (configurator) for generating nucleus of rx78k/0 and plural information tables is supplied. used in combination with an optional assembler package (ra78k/0) and device file. part number: sxxxxrx78013- dddd caution: when purchasing the rx78k/0, fill in the purchase application form in advance and sign the user agreement. remark: xxxx and ddd in the part number differ depending on the host machine and os used. s xxxx mx78013- dddd dddd product outline upper limit of mass-production quantity 001 evaluation object do not use for mass-produced products. 100k object for mass-produced product 0.1 million units 001m 1 million units 010m 10 million units s01 source program source program for mass-produced object xxxx h ost machine os supply medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver. 3.30 to ver.6.2 note ) 5-inch 2hd 7b13 ibm pc/at and compatible see a.4. 3.5-inch 2hc 7b10 5-inch 2hc 3h15 hp9000 series 300 hp-ux (rel.7.05b) cartrige tape (qic-24) 3p16 hp9000 series 700 hp-ux (rel.9.01) digital audio tape (dat) 3k15 sparcstation sunos (rel.4.1.1) cartridge tape (qic-24) 3m15 ews4800 series (risc) ews-ux/v (rel.4.0) note: the task swap function is not supported by the software listed above, although it is provided in ms-dos version 5.0 and later.
375 pd1615, pd16f15, pd1616 b.1 real-time os (2/2) mx78k0 tron specification subset os. nucleus of mx78k0 is supplied. os this os performs task management, event management, and time management. it controls the task execution sequence for task management and selects the task to be executed next. part number: sxxxxmx78k0- ddd remark: xxxx and ddd in the part number differ depending on the host machine and os used. s xxxx mx78k0- ddd ddd product outline note 001 evaluation object use for trial product. x x object for mass-produced product use for mass-produced product. s01 source program can be purchased only when object for mass-produced product is purchased. xxxx h ost machine os supply medium 5a13 pc-9800 series ms-dos 3.5-inch 2hd 5a10 (ver. 3.30 to ver.6.2 note ) 5-inch 2hd 7b13 ibm pc/at and compatible see a.4. 3.5-inch 2hc 7b10 5-inch 2hc 3h15 hp9000 series 300 hp-ux (rel.7.05b) cartrige tape (qic-24) 3p16 hp9000 series 700 hp-ux (rel.9.01) digital audio tape (dat) 3k15 sparcstation sunos (rel.4.1.1) cartridge tape (qic-24) 3m15 ews4800 series (risc) ews-ux/v (rel.4.0) note: the task swap function is not supported by the software listed above, although it is provided in ms-dos version 5.0 and later.
376 pd1615, pd16f15, pd1616 b.2 fuzzy inference development support system fe9000/fe9200 program that supports input, edit, and evaluation (simulation) of fuzzy knowledge fuzzy knowledge data creation tool data (fuzzy rule and membership function). fe9200 works on windows. part number: sxxxxfe9000 (pc-9800 series) sxxxxfe9200 (ibm pc/at and compatible machines) ft9080/ft9085 program that translates fuzzy knowledge data obtained by using fuzzy knowledge translator data creation tool into assembler source program for ra78k0. part number: sxxxxft9080 (pc-9800 series) sxxxxft9085 (ibm pc/at and compatible machines) fi78k0 program that executes fuzzy inference. executes fuzzy inference when linked with fuzzy inference module fuzzy knowledge data translated by translator. part number: sxxxxfi78k0 (pc-9800 series, ibm pc/at and compatible machines) fd78k0 support software for evaluation and adjustment of fuzzy knowledge data by using fuzzy inference debugger in-circuit emulator and at hardware level. part number: sxxxxfd78k0 (pc-9800 series, pc/at and compatible machines) remark: xxxx in the part number differs depending on the host machine and the os used. sxxxxfe9000 sxxxxft9080 sxxxxfi78k0 sxxxxfd78k0 xxxx host machine os supply media 5a13 pc-9800 series ms-dos 3.5" 2hd 5a10 (ver. 3.30 to ver. 6.2 note ) 5" 2hd note: ms-dos ver. 5.0 and later have the task swap function, but this function cannot be used for the above software. sxxxxfe9200 sxxxxft9085 sxxxxfi78k0 sxxxxfd78k0 xxxx host machine os supply media 7b13 ibm pc/at and compatible see a.4. 3.5" 2hc 7b10 machines 5" 2hc
377 pd1615, pd16f15, pd1616 [memo]
378 pd1615, pd16f15, pd1616 appendix c register index c.1 register index (in alphabetical order with respect to register names) [a] a/d conversion result register 1 (adcr1) 186 a/d converter mode register (adm1) 188 analog input channel specification register (ads1) 189 asynchronous serial interface mode register (asim0) 212, 213, 216, 217 asynchronous serial interface status register (asis0) 214, 218 [b] baud rate generator control register (brgc0) 214, 216, 219 [c] capture/compare control register (crc0) 113, 116, 120, 122, 123, 125, 129, 133 capture/compare register 00 (cr00) 111, 129 capture/compare register 01 (cr01) 112, 126 clock output selection register (cks) 182 [d] d/a converter mode register (dam0) 199 [e] 8-bit compare register 50 (cr50) 148 8-bit compare register 51 (cr51) 148 8-bit counter 50 (tm50) 144, 145, 146, 158 8-bit counter 51 (tm51) 144, 145, 146, 158 8-bit timer mode control register 50 (tmc50) 149, 154 8-bit timer mode control register 51 (tmc51) 150, 154 external interrupt falling edge register (egn) 313, 317 external interrupt rising edge register (egp) 313, 317 [i] internal extension ram size switching register (ixs) ... 341 interrupt mask flag register 0h (mk0h) 313, 315 interrupt mask flag register 0l (mk0l) 313, 315 interrupt mask flag register 1l (mk1l) 313, 315 interrupt request flag register 0h (if0h) 313, 314 interrupt request flag register 0l (if0l) 313, 314 interrupt request flag register 1l (if1l) 313, 314 [l] lcd display mode register (lcdm) ... 334, 345 lcd display control register (lcdc) ... 335
379 pd1615, pd16f15, pd1616 m] memory size switching register (ims) 382, 406 [o] oscillation stabilization time selection register (osts) 331 [p] port 0 (p0) 81 port 1 (p1) 83 port 4 (p4) 84 port 8 (p8) 85 port 9 (p9) 86 port 10 (p10) 87 port 11 (p11) 88 port 12 (p12) 89 port function register 8 (pf8) 90, 92 port function register 9 (pf9) 90, 92 port function register 10 (pf10) 90, 92 port function register 11 (pf11) 90, 92 port function register 12 (pf12) 90, 92, 117, 183 port mode register 0 (pm0) 90, 91, 113, 153 port mode register 4 (pm4) 90, 91 port mode register 8 (pm8) 90, 91 port mode register 9 (pm9) 90, 91 port mode register 10 (pm10) 90, 91 port mode register 11 (pm11) 90, 91 port mode register 12 (pm12) 90, 91, 117, 183 power-fail compare mode register (pfm) ... 190 power-fail compare threshold value register (pft) ... 190 prescaler selection register (prm0) 113, 118 priority specify flag register 0h (pr0h) 313, 316 pirority specify flag register 0l (pr0l) 313, 316 priority specify flag register 1l (pr1l) 313, 316 processor clock control register (pcc) 97 program status word (psw) 313, 318 [r] receive buffer register (rxb0) 211 receive shift register (rxs0) 211
380 pd1615, pd16f15, pd1616 [s] serial i/o shift register 30 (sio30) 203, 204, 208 serial operation mode register 30 (csim30) 205, 206, 207 16-bit timer mode control register (tmc0) 113, 114, 120, 122, 123, 125, 129, 133 16-bit timer output control register (toc0) 113, 117, 122, 133 16-bit timer register (tm0) 109 sound generator control register (sgcr) ... 303 sound generator buzzer control register (sgbr) ... 304, 305 sound generator amplitude register (sgam) ... 306 successive approximation register (sar) ... 186 [t] timer clock selection register 50 (tcl50) 149 timer clock selection register 51 (tcl51) 150 transmit shift register (txs0) 211 [v] van uart rank0 transmission register (rk0_reg) 244 van uart in frame response register (ifr_reg) 245, 246 van uart control register (ctrl_reg) 247, 248 van uart configuration register (conf_reg) 250 van uart diagnosis control register (diag_ctrl_reg) 253 van uart mask1 register (msk1_msb_reg ) 256 van uart mask2 register (msk2_msb_reg) 258 van uart mask1 register ( msk1_lsb_reg) 256 van uart mask2 register (msk2_lsb_reg) 258 van uart acceptance code 1 register (ac1_msb_reg) 257 van uart acceptance code 1 register ( ac1_lsb_reg) 257 van uart acceptance code 2 register (ac2_msb_reg) 259 van uart acceptance code 2 register (ac2_lsb_reg) 259 van uart acceptance code 3 register (ac3_msb_reg) 259 van uart acceptance code 3 register (ac3_lsb_reg) 259 van uart acceptance code 4 register (ac4_msb_reg) 259 van uart acceptance code 4 register (ac4_lsb_reg) 259 van uart receive register (rec_reg) 262 van uart diagnosis status register (diag_stat_reg) 263 van uart interrupt enable register (int_enable_reg) 264 van clock selection register (udlccl) 265 van uart status register (stat_reg) 260 [w] watch timer mode control register (wtm) 169 watchdog timer clock selection register (wdcs) 175 watchdog timer mode register (wdtm) 176
381 pd1615, pd16f15, pd1616 c.2 register index (in alphabetical order with respect to register symbol) adcr1 : a/d conversion result register 1 adm1 : a/d converter mode register ads1 : analog input channel specification register asim0 : asynchronous serial interface mode register asis0 : asynchronous serial interface status register brgc0 : baud rate generator control register cks : clock output selection register cr00 : capture/compare register 00 cr01 : capture/compare register 01 cr50 : 8-bit compare register 50 cr51 : 8-bit compare register 51 crc0 : capture/compare control register csim30 : serial operation mode register 0 dam0 : d/a converter mode register egn : external interrupt falling edge enable register egp : external interrupt rising edge enable register if0h : interrupt request flag register 0h if0l : interrupt request flag register 0l if1l : interrupt request flag register 1l ims : memory size switching register ixs : internal extension ram size switching register lcdc : lcd display control register lcdm : lcd display mode register mk0h : interrupt mask flag register 0h mk0l : interrupt mask flag register 0l mk1l : interrupt mask flag register 1l osts : oscillation stabilization time selection register
382 pd1615, pd16f15, pd1616 p0 : port 0 p1 : port 1 p4 : port 4 p8 : port 8 p9 : port 9 p10 : port 10 p11 : port 11 p12 : port 12 pcc : processor clock contrtol register pf8 : port function register 8 pf9 : port function register 9 pf10 : port function register 10 pf11 : port function register 11 pf12 : port function register 12 pfm : power-fail compare mode register pft : power-fail compare threshold value register pm0 : port mode register 0 pm4 : port mode register 4 pm8 : port mode register 8 pm9 : port mode register 9 pm10 : port mode register 10 pm11 : port mode register 11 pm12 : port mode register 12 pr0h : priority specify flag register 0h pr0l : priority specify flag register 0l pr1l : priority specify flag register 1l prm0 : prescaler mode register 0 psw : program status word rxb0 : receive buffer register rxs0 : receive shift register
383 pd1615, pd16f15, pd1616 sar : successive approximation register sgam : sound generator amplitude register sgbc : sound generator buzzer control register sgcr : sound generator control register sio30 : serial i/o shift register 30 tcl50 : timer clock selection register 50 tcl51 : timer clock selection register 51 tm0 : 16-bit timer register 0 tm50 : 8-bit counter 50 tm51 : 8-bit counter 51 tmc0 : 16-bit timer mode control register 0 tmc50 : 8-bit timer mode control register 50 tmc51 : 8-bit timer mode control register 51 toc0 : 16-bit timer output control register txs0 : transmit shift register udlccl : udl clock control register wdcs : watchdog timer clock selection register wdtm : watchdog timer mode register wtm : watch timer mode control register
384 pd1615, pd16f15, pd1616 [memo]
385 pd1615, pd16f15, pd1616 appendix d revision history the following shows the revision history up to present. application portions signifies the chapter of each edition. edition no. major items revised revised sections
386 pd1615, pd16f15, pd1616 appendix d revision history edition no. major items revised revised sections
387 pd1615, pd16f15, pd1616 [memo]
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