data sheet july 1997 revision 1.0 1 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh sdc3uv6482-(67/84/100/125)t-s 24mbyte (3m x 64) cmos synchronous dram module general description the sdc3uv6482-(67/84/100/125)t-s is a high performance, 24-megabtye synchronous, dynamic ram module organized as 3m words by 64 bits, in a 168-pin, dual-in-line memory module (dimm) package. the module utilizes eight fujitsu mb81117822a-(67/84/100/125)fn cmos 2mx8 and four fujitsu mb811171622a-(67/84/100/ 125)fn cmos 1mx16 synchronous dynamic rams in surface mount package (tsop) on an epoxy laminated substrate. each device is accompanied by a decoupling capacitor for improved noise immunity. a 256 byte serial eeprom contains the module configuration information. features ? high density 24mbyte ? cycle time: 8ns (125mhz), 10ns (100mhz), 12ns (84mhz), 15ns (67mhz) ? low power: active 5.0w (125mhz), 4.6w (100mhz), 4.3w (84mhz), 4.0w (67mhz) ? lvttl-compatible inputs and outputs ? separate power and ground planes to improve noise immunity ? single power supply of 3.3v 0.3v ? height: 1.150 inch absolute maximum ratings recommended dc operating conditions (t a = 0 to +70 c) item symbol ratings unit voltage on any pin relative to v ss v t -0.5 to +4.6 v power dissipation p t 15.6 w operating temperature t opr 0 to +70 c storage temperate t stg -55 to +125 c short circuit output current i os 50 ma symbol parameter min typ max unit v cc supply voltage 3.0 3.3 3.6 v v ss ground 0 0 0 v v ih input high voltage 2.0 - v cc +0.5 v v il input low voltage -0.5 - 0.8 v
sdc3uv6482-(67/84/100/125)t-s july 1997 revision 1.0 2 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh functional diagram 1. cke has a 10k ohm pull-up to vcc. 2. data and clks are terminated using 10 ohm series resistors. 3. each 2mx16 block comprises of two 2mx8 devices 4. dqms vs. data i/os dqmb0 controls dq0~dq7 dqmb1 controls dq8~dq15,c0~c7 dqmb2 controls dq16~dq23 dqmb3 controls dq24~dq31 dqmb4 controls dq32~dq39 dqmb5 controls dq40~dq47 dqmb6 controls dq48~dq55 dqmb7 controls dq56~dq63 5. clock wiring 2mx16 block 2mx16 block 2mx16 block 2mx16 block dqmb1 cke0 dq0~dq15 dq0~dq63 sa0-sa2 scl a0-a2 scl sda eeprom sda v cc v ss decoupling capacitors to all devices dq32~dq47 dq48~dq63 1mx16 sdram 1mx16 sdram 1mx16 sdram 1mx16 sdram dq16~dq31 (all specifications of the device are subject to change without notice.) dqmb6 dqmb7 dqmb3 dqmb2 cs3* cke1 clk1 cs0* ba0 cs1* 0.01 m f dqmb0 dqmb5 dqmb4 clk0 cs2* clk2 clk3 bank 2 bank 1 notes: clk1, clk3 sdram1 sdram2 10 w 5pf clk0, clk2 sdram1 sdram2 10 w sdram3 sdram4 10 w
july 1997 revision 1.0 sdc3uv6482-(67/84/100/125)t-s 3 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh pin name a0~a10/ap addresses cs0*~cs3* chip select ba0 bank select address we* write enable dq0~dq63 data inputs/outputs sa0~sa2 decode input clk0~clk3 clock inputs scl serial clock ras* row address strobes sda serial data input/output cas* column address strobes v cc power supply cke0, cke1 clock enables v ss ground dqmb0-dqmb7 dq mask enables nc no connection pin no. pin designation pin no. pin designation pin no. pin designation pin no. pin designation 1 v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 cs2* 87 dq33 129 cs3* 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 v cc 48 nc 90 v cc 132 nc 7 dq4 49 v cc 91 dq36 133 v cc 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 nc 94 dq39 136 nc 11 dq8 53 nc 95 dq40 137 nc 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v cc 101 dq45 143 v cc 18 v cc 60 dq20 102 v cc 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 nc 63 cke1 105 nc 147 nc 22 nc 64 v ss 106 nc 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 v cc 68 v ss 110 v cc 152 v ss 27 we* 69 dq24 111 cas* 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 cs0* 72 dq27 114 cs1* 156 dq59 31 nc 73 v cc 115 ras* 157 v cc 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 clk2 121 a9 163 clk3 38 a10 / ap (note) 80 nc 122 ba0 164 nc 39 nc 81 nc 123 nc 165 sa0 40 v cc 82 sda 124 v cc 166 sa1 41 v cc 83 scl 125 clk1 167 sa2 42 clk0 84 v cc 126 nc 168 v cc note: a10 / ap initiates auto-precharge
sdc3uv6482-(67/84/100/125)t-s july 1997 revision 1.0 4 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh serial pd information function supported hex value byte# function described 125 mhz 100 mhz 84 mhz 67 mhz 125 mhz 100 mhz 84 mhz 67 mhz 0 # bytes written into serial memory at module mfr 128 bytes 80h 1 total # bytes of spd memory device 256 bytes 08h 2 fundamental memory type sdram 04h 3 # row address on this assembly 11,11 bbh 4 # column addresses on this assembly 8,9 89h 5 # module banks on this assembly 2 02h 6 data width of this assembly 64 bits 40h 7 data width of this assembly (continued) 00h 8 voltage interface standard of this assembly lvttl 01h 9 sdram cycle time at cl=3 (tclk) 8ns 10ns 12ns 15ns 80h a0h c0h f0h 10 sdram access from clock at cl=3 (tac) 7.5ns 8.5ns 8.5ns 9.0ns 75h 85h 85h 90h 11 dimm configuration type non-parity 00h 12 refresh rate/type s/r, normal 15.6 ms 80h 13 sdram width primary dram x8,x16 88h 14 ecc sdram data width n/a 00h 15 min. clock delay, back to back random column addresses (iccd) 1clk 01h 16 burst length supported 1, 2, 4, 8 & full 8fh 17 # banks on each sdram device 2 02h 18 cas# latency 2, 3 06h 19 cs# latency 0 01h 20 write latency 0 01h 21 sdram module attribute non-buffered/registered 00h 22 sdram device attribute vcc, b/r, s/w, p/a, a/p 0eh 23 min clock cycle time at cl=2 (tclk) 12ns 15ns 17ns 20ns c0h f0h 20h 50h 24 max. data access time from clock at cl=2 (tac) 9.0ns 9.0ns 9.0ns 10ns 90h 90h 90h a0h 25 min clock cycle time at cl=1 (tclk) n/a ffh 26 max. data access time from clock at cl=1 (tac) n/a ffh 27 min. row precharge time (trp) 27ns 30ns 35ns 40ns 1bh 1eh 23h 28h 28 min. row active delay (trrd) 24ns 30ns 30ns 30ns 18h 1eh 1eh 1eh 29 min. ras to cas delay (trcd) 24ns 30ns 30ns 30ns 18h 1eh 1eh 1eh 30 min. ras pulse width (tras) 48ns 60ns 65ns 70ns 30h 3ch 41h 46h 31 module bank density 16mb, 8mb 3ch 32-61 superset information ffh 62 spd revision rev. 1 01h 63 checksum for bytes 0-62
july 1997 revision 1.0 sdc3uv6482-(67/84/100/125)t-s 5 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh serial pd information (continued) function supported hex value byte# function described 125 mhz 100 mhz 84 mhz 67 mhz 125 mhz 100 mhz 84 mhz 67 mhz 64 manufacturers jedec id code per jep-106e continuation code 7fh 65 manufacturers jedec id code per jep-106e smart?s id 94h 66-71 manufacturers jedec id code per jep-106e none ffh 72 manufacturing location mfr specific data 73 manufacturer?s part number s 53h 74 manufacturer?s part number d 44h 75 manufacturer?s part number c 43h 76 manufacturer?s part number 3 33h 77 manufacturer?s part number u 55h 78 manufacturer?s part number v 56h 79 manufacturer?s part number 6 36h 80 manufacturer?s part number 4 34h 81 manufacturer?s part number 8 38h 82 manufacturer?s part number 2 32h 83 manufacturer?s part number 1 1 8 6 31h 31h 38h 36h 84 manufacturer?s part number 2 0 4 7 32h 30h 34h 37h 85 manufacturer?s part number 5 0 t t 35h 30h 54h 54h 86 manufacturer?s part number t t s s 54h 54h 53h 53h 87 manufacturer?s part number s s none none 53h 53h ffh ffh 88 manufacturer?s part number none ffh 89 manufacturer?s part number none ffh 90 manufacturer?s part number none ffh 91 revision code mfr specific data mfr specific data 92 revision code none ffh 93 manufacturing date date date 94 manufacturing date date date 95-98 assembly serial number serial number s.no. 99 manufacturer specific data s 53h 100 manufacturer specific data m 4dh 101 manufacturer specific data a 41h 102 manufacturer specific data r 52h 103 manufacturer specific data t 54h 104 manufacturer specific data m 4dh 105 manufacturer specific data o 6fh 106 manufacturer specific data d 64h 107 manufacturer specific data u 75h 108 manufacturer specific data l 6ch 109 manufacturer specific data a 61h 110 manufacturer specific data r 72h 111 manufacturer specific data t 54h 112 manufacturer specific data e 65h 113 manufacturer specific data c 63h 114 manufacturer specific data h 68h 115 manufacturer specific data n 6eh 116 manufacturer specific data o 6fh 117 manufacturer specific data l 6ch 118 manufacturer specific data o 6fh 119 manufacturer specific data g 67h 120 manufacturer specific data i 69h 121 manufacturer specific data e 65h 122 manufacturer specific data s 73h 123 manufacturer specific data none ffh 124 manufacturer specific data none ffh 125 manufacturer specific data none ffh 126 (*) intel specification frequency 66 mhz 66h 127 (*) intel specification cas# latency support 2,3 06h 128-255 open for cpq use for read & write none ffh (*) intel specification extension: these bytes are required for compatibility with previously released systems.
sdc3uv6482-(67/84/100/125)t-s july 1997 revision 1.0 6 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh dc characteristics (v cc = 3.3v 0.3v, v ss = 0v, t a = 0 to +70 c) ?cl = cas* latency notes: 1. i cc depends on output load condition when the device is selected i cc (max.) is specified at the output open condition. 2. an initial pulse of 200 m s is required after power-up followed by a minimum of eight auto-refresh-cycles. capacitance (ta =+25 c, vcc = 3.3v 0.3v) notes: 1. capacitance is measured with boonton meter or effective capacitance method. 2. cas* - v ih to disable d out . parameter symbol test condition 125 100 84 67 unit note min. max. min. max. min. max. min. max. operating current i cc1 no burst, t ck = min. t rc = min. - 920 - 880 - 840 - 800 ma 1, 2 no burst, t ck = min., t rc = min. all banks active - 1320 - 1240 - 1160 - 1080 ma 1, 2 precharge standby current i cc2 cke -v il , t ck = min. all banks idle - 24 - 24 - 24 - 24 ma 1, 2 cke = v ih , t ck = min. all banks idle - 360 - 360 - 360 - 360 ma 1.2 active standby current i cc3 cke = v il , t ck = min. any bank active - 360 - 360 - 360 - 360 ma 1, 2 cke = v ih , t ck = min. any bank active - 600 - 600 - 600 - 600 ma 1, 2 burst mode current i cc4 t ck = min. - 1400 - 1280 - 1200 - 1120 ma 1, 2 refresh current i cc5 t ck = min., t rc = min., t rrd = min. auto refresh - 1160 - 1080 - 1000 - 920 ma 1, 2 self refresh current i cc6 cke - v il - 24 - 24 - 24 - 24 ma 1, 2 input leakage i li 0v v in v cc -120 120 -120 120 -120 120 -120 120 m a output leakage current i lo 0v v out v cc d out = disable -20 20 -20 20 -20 20 -20 20 m a output high voltage v oh high i out = -2ma 2.4 - 2.4 - 2.4 - 2.4 - v output low voltage v ol low i out = 2 ma - 0.4 - 0.4 - 0.4 - 0.4 v parameter symbol max. unit note input capacitance (address, we*, cke, ras*, cas*) c i1 53 pf 1 input capacitance (dqmbs) c i2 17 pf 1 input capacitance (cs0*,cs2*,clk0,clk2) c i3 21 pf 1 input capacitance (clk1,clk3,cs1*,cs3*) c i4 13 pf 1 input/output capacitance (dq0~dq63) c i/o 19 pf 1, 2
july 1997 revision 1.0 sdc3uv6482-(67/84/100/125)t-s 7 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh ac characteristics (ta = 0 to +70 c, v cc = 3.3v 0.3v, v ss = 0v) notes: 1. an initial pulse of at least 200 m s is required after power-up followed by a minimum of eight auto refresh cycles. 2. ac characteristics assume t t = 1ns and 50pf capacitive load. if t t is longer than 1ms, reference level for measuring time of input signal is v ih (min.) and v il (max.). 3. 1.4v is the reference level for measuring timing of input signals. 4. t hz and t oh defines the time at which the outputs achieve 200mv. 5. actual clock output of t rc will be sum clock of t ras and t rp . 6. 20ns is not supported in spd. parameter symbol unit 125 100 84 67 notes clock period cl=3 t clk ns 8 - 10 - 12 - 15 - 1, 2, 3, 6 cl=2 12 - 15 - 17 - 20 - transition time t t ns 0.5 2 0.5 2 0.5 2 0.5 2 1, 2, 3 clock high time t ch ns 3.5 - 4 - 4 - 4 - 1, 2, 3 clock low time t cl ns 3.5 - 4 - 4 - 4 - 1, 2, 3 cs setup time t sc ns 3.0 - 3.0 - 3.0 - 3.0 - 1, 2, 3 cs hold time t hc ns 1.0 - 1.0 - 1.0 - 1.0 - 1, 2, 3 input setup time t si ns 3.0 - 3.0 - 3.0 - 3.0 - 1, 2, 3 input hold time t hi ns 1.0 - 1.0 - 1.0 - 1.0 - 1, 2, 3 output valid from clock cl=3 t ac ns - 7.5 - 8.5 - 8.5 - 9.0 1, 2, 3 cl=2 - 9 9 - 9 - 10 output in low-z t olz ns 2 - 3 - 3 - 3 - 1, 2, 3 output in high-z t ohz ns 2 - 3 - 3 - 3 - 1, 2, 3, 4 output hold time t oh ns 2 - 3 - 3 - 3 - 1, 2, 3 time between refresh t ref ms - 32.8 - 32.8 - 32.8 - 32.8 1, 2, 3 ras cycle time t rc ns 75 - 90 - 100 - 110 2 1, 2, 3, 5 ras access time t rac ns - 45 - 54 - 56 - 60 1, 2, 3 cas access time t cac ns - 21 - 24 - 26 - 30 1, 2, 3 ras precharge time t rp ns 27 - 30 - 35 - 40 - 1, 2, 3 ras active time t ras ns 48 10000 60 10000 65 - 70 10000 1, 2, 3 ras to cas delay time t rcd ns 24 - 30 - 30 - 30 - 1, 2, 3 write recovery time t wr ns 8 - 10 - 12 - 15 - 1, 2, 3 write to precharge lead time t rwl ns 8 - 10 - 12 - 15 - 1, 2, 3 ras to ras delay time t rrd ns 24 - 30 - 30 - 30 - 1, 2, 3 power-down exit time t pde ns 3 - 3 - 4 - 5 - 1, 2, 3 cke to clock disable i cke cycle 1 1 1 1 dqm to output in high-z i dqz cycle 2 2 2 2 dqm to input data delay i dqd cycle 0 0 0 0 last output to write command delay i owd cycle 2 2 2 2 write command to input data delay i dwd cycle 0 0 0 0 precharge to output in high-z delay cl=3 i roh cycle 3 3 3 3 cl=2 2 2 2 2 mode register access to bank active (min.) i mrd cycle 2 2 2 2 cas to cas delay i ccd cycle 1 1 1 1 cas bank delay i cbd cycle 1 1 1 1
sdc3uv6482-(67/84/100/125)t-s july 1997 revision 1.0 8 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh physical dimensions 168-pin (84x2) dimm notes: 1. all dimensions are in inches. 2. pin 85 is behind pin 1 on the back side. 5.250 5.171 5.014 1 . 1 5 0 0 . 7 0 0 0 . 1 1 8 0.158 ? 0.118 2.507 4.550 (ref.) 5.014 1.700 1.450 2.150 0.450 0.250 0.250 0.350 0.150 max 0.050 +0.004/-0.003 front view 0.123 0.079 detail ?a? ?a? ?a?
july 1997 revision 1.0 sdc3uv6482-(67/84/100/125)t-s 9 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh (1) memory type s : sdram g : sgram (2) module shape s : simm d : dimm o : small outline dimm (3) module pin count a : 72-pin b : 144-pin c : 168-pin d : 200-pin (4) word depth 1 : 1m 2 : 2m 4 : 4m 8 : 8m 256 : 256k 512 : 512k . (5) buffer type b : buffered u : unbuffered (6) operating voltage & power consumption v : 3.3v & standard power l : 3.3v & low power (7) data width (ex. 64=x64, 72=x72 etc.) (8) device configuration 4 : x4 8 : x8 1 : x16 3 : x32 (8a) refresh 2 : 2krf 4 : 4krf s d c 3 u v 64 8 2 - 100 t - s (1) (2) (3) (4) (5) (6) (7) (8) (8a) (9) (10) (11) (12) (13) (14) ordering information (9) interface level blank : lvttl s : sstl (10) module revision / applied ?standard? *1 blank : rev. 0 a : rev. 1 b : rev. 2 (etc.) *1 when dram device or pcb is revised, the revision is changed (11) clock frequency 67 : 67mhz 84 : 84mhz 100 : 100mhz 125 : 125mhz (12) package of component j : soj t : tsop (13) private brand name *2 blank : common products g : fmg brand *2 this column is applicable to custom modules, not applicable to jedec standard commodity products (14) assembly & test site s : smart modular technologies
sdc3uv6482-(67/84/100/125)t-s july 1997 revision 1.0 10 fujitsu microelectronics, inc./fujitsu mikroelektronik gmbh japan north and south america europe asia fujitsu microelectronics, inc. 3545 north first street san jose, ca 95134-1804, usa. tel : +1-408-922-9000 fax : +1-408-922-9179 customer response center (mon-fri: 7am-5pm (pst)) tel : +1-800-866-8608 fax : +1-408-922-9179 internet: http://www.fujitsumicro.com/ fujitsu microelectronics asia pte limited #05-08, 151 lorong chuan newtechpark singapore 556741 tel : +65-281-0770 fax : +65-281-0220 internet: http://www.fsl.com.sg/ fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich?buchschlag germany tel : +49-6103-690-0 fax : +49-6103-690-122 internet: http://www.fujitsu-ede.com/ fujitsu limited memory marketing dept. 4-1-1, kamikodanaka nakahara-ku, kawasaki 211-88, japan tel : +81-44-754-3767 fax : +81-44-754-3343 internet: http://www.fujitsu.co.jp/ for further information please contact: fujitsu limited all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor appli- cations. complete information sufficient for construc- tion purposes is not necessarily given. the information given in this document have been carefully checked and is believed to be reliable. how- ever, fujitsu assumes no responsibility for inaccura- cies. the information contained in this document does not convey any licence under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifi- cations without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equip- ments, undersea repeaters, nuclear control systems or medical equipments for life support. ? fujitsu limited 1997 mp-dramm-ds-20539-7/97
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