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description these units are single, dual and quad channel, hermetically sealed optocouplers. the products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full mil-prf-38534 class level h or k testing or from the ap - propriate dscc drawing. all devices are manufactured and tested on a mil-prf-38534 certifed line and are included in the dscc qualifed manufacturers list qml-38534 for hybrid microcircuits. hermetically sealed, transistor output optocouplers for analog and digital applications 4n55*, 5962-87679, hcpl-553x, hcpl-653x, hcpl-257k, hcpl-655x, 5962-90854, hcpl-550x *see matrix for available extensions. data sheet features ? dual marked with device part number and dscc drawing number ? manufactured and tested on a mil-prf-38534 certifed line ? qml-38534, class h and k ? five hermetically sealed package confgurations ? performance guaranteed over full military temperature range: -55c to +125c ? high speed: typically 400 kbit/s ? 9 mhz bandwidth ? open collector output ? 2-18 volt v cc range ? 1500 vdc withstand test voltage ? high radiation immunity ? 6n135, 6n136, hcpl-2530/2531, function compatibility ? reliability data the connection of a 0.1 f bypass capacitor between v cc and gnd is recommended. applications ? military and space ? high reliability systems ? vehicle command, control, life critical systems ? line receivers ? switching power supply ? voltage level shifting ? analog signal ground isolation (see figures 7, 8, and 13) ? isolated input line receiver ? isolated output line driver ? logic ground isolation ? harsh industrial environments ? isolation for test equipment systems caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd.
truth table (positive logic) functional diagram multiple channel devices available input output on (h) l off (l) h v cc gnd v o v b each channel contains a gaasp light emitting diode which is optically coupled to an integrated photon detector. separate connections for the photodiodes and output transistor collectors improve the speed up to a hundred times that of a conventional phototransistor optocoupler by reducing the base-collector capacitance. these devices are suitable for wide bandwidth analog applications, as well as for interfacing ttl to lsttl or cmos. current transfer ratio (ctr) is 9% minimum at i f = 16 ma. the 18 v v cc capability will enable the designer to interface any ttl family to cmos. the availability of the base lead allows optimized gain/ bandwidth adjust - ment in analog applications. the shallow depth of the ic photodiode provides better radiation immunity than conventional phototransistor couplers. these products are also available with the transistor base node not connected to improve common mode noise immunity and esd susceptibility. in addition, higher ctr minimums are available by special request. package styles for these parts are 8 and 16 pin dip through hole (case outlines p and e respectively), 16 pin dip fat pack (case outline f), and leadless ceramic chip carrier (case outline 2). devices may be purchased with a variety of lead bend and plating options, see selection guide table for details. standard microcircuit drawing (smd) parts are available for each package and lead style. because the same functional die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifcations, and perfor - mance characteristics shown in the fgures are identical for all parts. occasional exceptions exist due to package variations and limitations and are as noted. additionally, the same package assembly processes and materials are used in all devices. these similarities give justifcation for the use of data obtained from one part to represent other parts performance for die related reliability and certain limited radiation test results.
selection guideCpackage styles and lead confguration options package 16 pin dip 8 pin dip 8 pin dip 16 pin flat pack 20 pad lccc lead style through hole through hole through hole unformed leads surface mount channels 1 4 common channel wiring none none v cc gnd v cc gnd none avago part no. and options commercial 4n55 (1) hcpl-5500 hcpl-550 hcpl-6550 hcpl-650 mil-prf-854 class h 4n55/88b hcpl-5501 hcpl-551 hcpl-6551 hcpl-651 mil-prf-854 class k hcpl-57k hcpl-550k hcpl-55k hcpl-655k hcpl-65k standard lead finish gold plate gold plate gold plate gold plate solder pads * solder dipped * option 00 option 00 option 00 butt joint/gold plate option 100 option 100 option 100 gull wing/soldered* option 00 option 00 option 00 class h smd part # prescript for all below 596- 596- 596- 596- 596- either gold or soldered 8767901ex 9085401hpx 876790px 8767904fx 876790x gold plate 8767901ec 9085401hpc 876790pc 8767904fc solder dipped* 8767901ea 9085401hpa 876790 pa 876790a butt joint/gold plate 8767901uc 9085401hyc 876790yc butt joint/soldered* 8767901ua 9085401hya 876790 ya gull wing/soldered* 8767901ta 9085401hxa 876790xa class k smd part # prescript for all below 596- 596- 596- 596- 596- either gold or soldered 8767905kex 9085401kpx 8767906kpx 8767908kfx 8767907kx gold plate 8767905kec 9085401kpc 8767906kpc 8767908kfc solder dipped * 8767905kea 9085401kpa 8767906kpa 8767907ka butt joint/gold plate 8767905kuc 9085401kyc 8767906kyc butt joint/soldered* 8767905kua 9085401kya 8767906kya gull wing/soldered* 8767905kta 9085401kxa 8767906kxa 1. jedec registered part. * solder contains lead
4 outline drawings 16 pin dip through hole, 2 channels 8 pin ceramic dip single channel schematic note: 8 pin dip and fat pack devices have common v cc and ground. 16 pin dip and lccc (leadless ceramic chip carrier) packages have isolated channels with separate v cc and ground connections. functional diagrams anode 3 cathode 6 5 v o gnd i o i f 2 + - v f 8 v cc 7 v b i b i cc 16 pin dip 8 pin dip 8 pin dip 16 pin flat pack 0 pad lccc through hole through hole through hole unformed leads surface mount channels 1 channel channels 4 channels channels 1 4 8 6 7 5 v cc gnd v out v b 1 4 8 6 7 5 v cc gnd v o v o1 5 7 6 8 1 10 11 9 gnd v o4 v o 1 4 16 14 15 1 v cc v o v o1 gnd 1 v b 19 0 v o1 8 7 v cc v cc1 10 gnd 15 1 1 14 v o v b1 9 5 7 6 8 1 10 11 9 gnd v cc v b 1 4 16 14 15 1 v cc1 gnd v o1 v o v b1 0.20 (0.008 ) 0.33 (0.013 ) 4.45 (0.175) max. 20.06 (0.790) 20.83 (0.820) 0.51 (0.020 ) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.89 (0.035 ) 1.65 (0.065 ) 8.13 (0.320) max. note: dimensions in millimeters (inches) . 3.81 (0.150 ) min. note, base is pin 7.
5 leaded device marking leadless device marking outline drawings 16 pin flat pack, 4 channels compliance indicator,* date code, suffix (if needed) a qyywwz xxxxxx xxxxxxx xxx xxx 50434 country of mfr. avago cage code* avago designator dscc smd* pin one/ esd ident avago p/n dscc smd* * qualified parts only compliance indicator,* date code, suffix (if needed) a qyywwz xxxxxx xxxx xxxxxx xxx 50434 dscc smd* avago cage code* avago designator country of mfr. avago p/n pin one/ esd ident dscc smd* * qualified parts only 8.13 (0.320) max. 5.23 (0.206) max. 2.29 (0.090) max. 7.24 (0.285) 6.99 (0.275) 1.27 (0.050) ref. 0.46 (0.018) 0.36 (0.014) 11.13 (0.438) 10.72 (0.422) 2.85 (0.112) max. 0.89 (0.035) 0.69 (0.027) 0.31 (0.012) 0.23 (0.009) 0.88 (0.0345) min. 9.02 (0.355) 8.76 (0.345) note: dimensions in millimeters (inches). 20 terminal lccc surface mount, 2 channels 8 pin dip through hole, 1 and 2 channel 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 1.02 (0.040) (3 plcs) 4.95 (0.195) 5.21 (0.205) 8.70 (0.342) 9.10 (0.358) 1.78 (0.070) 2.03 (0.080) 0.51 (0.020) 0.64 (0.025) (20 plcs) 1.52 (0.060) 2.03 (0.080) metalized castillations (20 plcs) 2.16 (0.085) terminal 1 identifier note: dimensions in millimeters (inches). solder thickness 0.127 (0.005) max. 1.14 (0.045) 1.40 (0.055) 3.81 (0.150) min. 4.32 (0.170) max. 9.40 (0.370) 9.91 (0.390) 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.76 (0.030) 1.27 (0.050) 8.13 (0.320) max. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 7.16 (0.282) 7.57 (0.298) note: dimensions in millimeters (inches).
6 option description 100 surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. this op - tion is available on commercial and hi-rel product in 8 and 16 pin dip (see drawings below for details). 200 lead fnish is solder dipped rather than gold plated. this option is available on commercial and hi-rel product in 8 and 16 pin dip. dscc drawing part numbers contain provisions for lead fnish. all leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. 300 surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. this option is available on commercial and hi-rel product in 8 and 16 pin dip (see drawings below for details). this option has solder dipped leads. hermetic optocoupler options 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 1.40 (0.055) 1.65 (0.065) 4.57 (0.180) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.51 (0.020) min. 4.57 (0.180) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 9.65 (0.380) 9.91 (0.390) 5? max. 4.57 (0.180) max. note: dimensions in millimeters (inches). 0.20 (0.008) 0.33 (0.013) note: solder contains lead.
7 recommended operating conditions esd classifcation (mil-std-883, method 3015) single channel 8 pin, dual channel 16 pin, and lccc only absolute maximum ratings no derating required up to +125 c. parameter symbol min. max. units storage temperature range t s -65 +150 c operating ambient temperature t a -55 +125 c junction temperature t j +175 c case temperature t c +170 c lead solder temperature (1.6 mm below seating plane) 260 for 10 s c average input forward current i f avg 20 ma peak forward input current (each channel, 1 ms duration) i fpk 40 ma reverse input voltage bv r see electrical characteristics average output current, each channel i o 8 ma peak output current, each channel i o 16 ma supply voltage v cc -0.5 20 v output voltage v o -0.5 20 v input power dissipation, each channel 36 mw output power dissipation, each channel 50 mw package power dissipation, each channel p d 200 mw parameter symbol min. max. units emitter base reverse voltage v ebo 3 v base current, each channel i b 5 ma 4n55, 4n55/883b, hcpl-257k, hcpl-5500/01/0k, and HCPL-6530/31/3k ( ), class 1 hcpl-5530/31/3k, hcpl-6550/51/5k (dot), class 3 parameter symbol min. max. units input current, low level i fl 250 a input current, high level i fh 12 20 ma supply voltage, output v cc 2 18 v d
8 electrical characteristics t a = -55 c to +15 c, unless otherwise specifed. see note 1. parameter symbol group a, sub- group test conditions limits units fig. notes min. typ.* max. current transfer ratio ctr 1, 2, 3 v o = 0.4v, i f = 16 ma, v cc = 4.5v 9 20 % 2, 3 1, 2, 10 logic high output current i oh 1, 2, 3 i f = 0, i f (other channels) = 20 ma v o = v cc = 18 v 5 100 m a 4 1 output leakage current i oleak 1, 2, 3 i f = 250 m a, i f (other channels) = 20 ma, v o = v cc = 18 v 30 250 m a 4 1 input-output insulation leakage current i i-o 1 v i-o = 1500 vdc, rh 65%, t a = 25c, t = 5 s 1.0 m a 3, 9 input forward voltage v f 1, 2, 3 i f = 20 ma 1.55 1.8 v 1 1, 14 1.9 1, 13 reverse breakdown voltage bv r 1, 2, 3 i r = 10 m a 5 v 1, 14 3 1, 13 logic high supply current single channel i cch 1, 2, 3 v cc = 18 v, i f = 0 ma 0.1 10 m a 1 dual channel v cc = 18 v, i f = 0 ma (all channels) 0.2 20 1,4 quad channel v cc = 18 v, i f = 0 ma (all channels) 0.4 40 1 logic low supply current single channel i ccl 1, 2, 3 v cc = 18 v, i f = 20 ma 35 200 m a 1 dual channel v cc = 18 v, i f1 = i f2 = 20 ma 70 400 1, 4 quad channel v cc = 18 v, i f1 = i f2 = i f3 = i f4 = 20 ma 140 800 1 propagation delay time to logic high at output t plh 9, 10, 11 r l = 8.2 k w , c l = 50 pf, i f = 16 ma, v cc = 5 v 1.0 6.0 m s 6, 9 1, 6 propagation delay time to logic low at output t phl 0.4 2.0 *all typical values are at v cc = 5 v, t a = 5c.
9 notes: 1. each channel of a multi-channel device. 2. current transfer ratio is defned as the ratio of output collector current, i o , to the forward led input current, i f , times 100%. ctr is known to degrade slightly over the units lifetime as a function of input current, temperature, signal duty cycle, and system on time. refer to application note 1002 for more detail. ln short, it is recommended that designers allow at least 20-25% guardband for ctr degradation. 3. all devices are considered two-terminal devices; measured between all input leads or terminals shorted together and all output leads or terminals shorted together. 4. the 4n55, 4n55/883b, hcpl-257k, HCPL-6530, hcpl-6531, and hcpl-653k dual channel parts function as two independent single channel units. use the single channel parameter limits. i f = 0 ma for channel under test and i f = 20 ma for other channels. 5. measured between adjacent input pairs shorted together for each multichannel device. 6. t phl propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 v point on the leading edge of the output pulse. the t plh propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 v point on the trail - ing edge of the output pulse. 7. cm l is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (v o < 0.8 v). cm h is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (v o > 2.0 v). 8. bandwidth is the frequency at which the ac output voltage is 3 db below the low frequency asymptote. for the hcpl-5530 the typical bandwidth is 2 mhz. 9. this is a momentary withstand test, not an operating condition. 10. higher ctr minimums are available to support special applications. 11. measured between each input pair shorted together and all output connections for that channel shorted together. 12. standard parts receive 100% testing at 25c (subgroups 1 and 9). smd and 883b parts receive 100% testing at 25, 125, and -55c (subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 13. not required for 4n55, 4n55/883b, hcpl-257k, 5962-8767901, and 5962-8767905 types. 14. required for 4n55, 4n55/883b, hcpl-257k, 5962-8767901, and 5962-8767905 types only. typical characteristics all typical values are at t a = 25c, v cc = 5 v, unless otherwise specifed. parameter symbol test conditions typ. units fig. notes input capacitance c in v f = 0 v, f = 1 mhz 60 pf 1 input diode temperature coefcient d v f / d t a i f = 20 ma -1.5 mv/c 1 resistance (input-output) r i-o v i-o = 500 v 10 12 w 3 capacitance (input-output) c i-o f = 1 mhz 1.0 pf 1, 11 transistor dc current gain h fe v o = 5 v, i o = 3 ma 250 - 1 small signal current transfer ratio d i o / d i f v cc = 5 v, v o = 2 v 21 % 7 1 common mode transient immu - nity at logic high level output |cm h | i f = 0 ma, r l = 8.2 k w , v o (min) = 2.0 v, v cm = 10 v p-p 1000 v/ m s 10 1, 7 common mode transient immu - nity at logic low level output |cm l | i f = 16 ma, r l = 8.2 k w , v o (max) = 0.8 v, v cm = 10 v p-p -1000 v/ m s 10 1, 7 bandwidth bw 9 mhz 8 8 multi-channel product only parameter symbol test conditions typ. units notes input-input insulation leakage current i i-i rh 65%, v i-i = 500 v, t = 5 s 1 pa 5, 9 resistance (input-input) r i-i v i-i = 500 v 10 12 w 5 capacitance (input-input) c i-i f=1 mhz 0.8 pf 5
figure 1. input diode forward current vs. for - ward voltage. figure 2. dc and pulsed transfer character - istic. figure 3. normalized current transfer ratio vs. input diode forward current. figure 4. logic high output current vs. tem - perature. figure 5. logic low supply current vs. input diode forward current. figure 6. propagation delay vs. temperature. figure 7. normalized small signal current transfer ratio vs. quiescent input current. i oh - logic high output current - a -60 140 100 0.001 t a - temperature - ?c -40 20 40 60 10 1 0.1 120 0.01 -20 80 0 100 i f = 250 a , i f (other channels) = 20 ma i f = 0 a , i f (other channels) = 20 ma i f = i f (other channels ) = 0 ma v cc = v o = 18 v
11 figure 8. frequency response. figure 9. switching test circuit.* *jedec registered data. gn d v cc i f +5 v v o d.u.t. 100 ? i f monitor pulse gen . z o = 50 ? t r = 5 ns c l * = 50 pf 10 % duty cycle 1/f < 100 s r l notes: * c l includes probe and stray wiring capacitance. base lead not connected. single channel or common v cc devices gnd v cc +12 v v o (1 m ? , 12 pf test input) d.u.t. r f v in 9.1 k ? single channel testing, independent v cc devices 1 k ? 2.1 k ? +12 v q 1 47 f 0.01 f q 3 q 2 0.01 f 1.2 k ? 15 k ? 47 0 ? 100 ? v b v o 51 ? 22 ? 100 ? 0.1 f 0.1 f trim for unity gai n q 1 , q 2 , q 3 : 2n3904 typical linearity = +3 % at v in = 1 v p-p typical snr = 50 db typical r f = 375 ? typical v o dc = 3.8 v typical i f = 9 ma 1n4150 gnd v cc +15 v v o d.u.t. 100 ? ac input 100 ? common v cc device s 560 ? 20 k ? +5 v set i f 2n3053 1.6 vdc 0.25 v p- p ac 0.1 f normalized response - db 0.1 100 +1 5 -20 f - frequency - mhz +1 0 +5 -5 -15 1.0 10 -10 0 t a = 25 ?c independent v cc device s common v cc devices
1 figure 11. recommended logic interface. figure 12. operating circuit for burn-in and steady state life tests. all channels tested simultaneously. v ff gnd v cc i f v cm r l +5 v v o + pulse gen. note: base lead not connected. a b d.u.t. r m single channel or common v cc devices - figure 10. test circuit for transient immunity and typical waveforms. gnd v cc d.u.t. r l 220 ? 5 v v cc logic gate 0.01 f each channel ttl gnd v cc v o d.u.t. * note: base lead not connected. t a = +125 ?c v oc nominal conditions per channel: i f = 20 ma i o = 4 ma i cc = 30 a v cc v in + (each output) (each input) 0.1 f - *the equivalent output load resistance is afected by the lsttl input current and is approximately 8.2 k?. this is a worst case design which takes into account 25% degradation of ctr. see app. note 1002 to assess actual degradation and lifetime. logic family lsttl cmos device no. 54ls14 cd40106bm v cc 5 v 5 v 15 v r l 5% tolerance 18 k w * 8. k w k w
mil-prf-38534 class h, class k, and dscc smd test program avago technologiess hi-rel optocouplers are in compli - ance with mil-prf-38534 classes h and k. class h and class k devices are also in compliance with dscc draw - ings 5962-87679, and 5962-90854. testing consists of 100% screening and quality conformance inspection to mil-prf-38534. description the schematic uses a dualchannel, high-speed optocou - pler (hcpl-5530) to function as a servo type dc isolation amplifer. this circuit operates on the principle that two optocouplers will track each other if their gain changes by the same amount over a specifc operating region. performance of circuit ? 1% linearity for 10 v peak-to-peak dynamic range ? gain drift: -0.03%/c ? ofset drift: 1 mv/c ? 25 khz bandwidth (limited by op-amps u1, u2) figure 13. isolation amplifer application circuit. v out i f 3 r 1 2 3 4 8 7 6 5 1 i f 2 v in u 1 2 u 3 -15 v - + - + i c 2 -15 v i cc 6 ma i c 1 = k 1 i f 1 i n 1 i c 2 = k 2 i f 2 i n 2 hcpl-5530 2 u 4 - + 2 5 k ? gain adjust r 4 1 k ? 5 r 5 k ? offset adjust i c 1 220 ? r 2 2.7 k ? r 1 2.7 k ? + u 2 - + - u 1 , u 2 , u 3 , u 4 , lm307 50 k ? f 1 f 2 for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countries. data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. 5989-1659en - june 13, 2007

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