description: the memory stack? series is a family of interchangeable memory modules. the 128 megabit double data rate synchronous dram module is a member of this family which utilizes the space saving lp-stack? tsop stacking technology. the devices are constructed with two 16 meg x 4 ddr drams. the 64 megabit based lp-stack? module, dpdd16mx8rsay5, has been designed to fit the same footprint as the 16 meg x 4 ddr sdram tsop monolithic. this allows for system upgrade without electrical or mechanical redesign, providing an immediate and low cost memory solution. features: configuration available: 16 meg x 8 (2 banks of 4 meg x 4 bit x 4 banks) clock frequency: 100, 125, 133, 143, 167 mhz 2.5 volt dq supply jedec standard sstl_2 interface for all inputs/outputs four bank operation programmable burst type: burst length and read latency refresh: 4096 cycles/64ms refresh types: auto and self jedec approved footprint and pinout ipc-a-610 manufacturing standards package: 66-pin leaded tsop stack 1 (top view) 60 n.c. vdd 1 2 54 n.c. vddq 3 53 n.c. 4 52 vssq dq1 5 51 dqs vssq 6 50 n.c. n.c. 7 49 vref 8 48 vss vddq 9 47 n.c. 10 46 ck dq3 11 45 ck vssq 12 44 cke n.c. 13 43 n.c. n.c. 14 42 n.c. vddq 15 41 a11 n.c. 16 40 a9 n.c. 17 39 a8 vdd 18 38 a7 *nu/qfc 19 37 a6 n.c. 20 36 a5 we 21 35 a4 cas 22 34 vss ras 23 59 dq5 cs 24 58 vssq n.c. 25 57 n.c. ba0 26 56 dq4 ba1 27 55 vddq dq2 dq0 dm n.c. 33 vdd 32 a3 31 a2 30 a1 29 a0 28 a10/ap vddq 61 dq6 62 n.c. 63 vssq 64 dq7 65 vss 66 a0-a11 row address: a0-a11 column address: a0-a8 ba0,ba1 bank select address a10/ap auto precharge dq0-dq7 data in/data out cas column address strobe cs chip select ras row address strobe we data write enable ck, ck differential clock inputs cke clock enable dqs data strobe dm data mask qfc dq fet switch control v dd power supply (+2.5v) vss ground v ddq dq power supply (+2.5v) vss q dq ground v ref reference voltage for inputs n.c. no connect nu not used, electrical connect is present 30a223-00 rev. d 3/02 this document contains information on a product presently under development at dpac technologies. dpac reserves the right to change products or specifications herein without prior notice. 128 megabit cmos ddr sdram dpdd16mx8rsay5 preliminary dm cas we dq4-dq7 cs ras ck dqs ck a0-a11 vref cke ba0-ba1 dq0-dq3 qfc (4 meg x 4 bits x 4 banks) 64 mb ddr sdram (4 meg x 4 bits x 4 banks) 1 pin names pin-out diagram functional block diagram advanced components packaging * this pin is a no connect for some manufacturers.
20 15 dp xx - cas double data rate synchronous dram prefix cas latency 1.5 cas latency 2.0 dd 16m x 8 y5 package memory desig memory type memory module without support logic depth width desig r 64 megabit based stackable tsop manufacturer code* xx - mfr id supplier dp supplier code* i/o type s sstl inputs/outputs width device a x4 memory based cas latency 3.0 30 cycle xx time latency 60 6ns (166mhz) 7ns (143mhz) 7.5ns (133mhz) 8ns (125mhz) 10ns (100mhz) 10 75 08 70 cas latency 2.5 25 ordering information 30a223-00 rev. d 3/02 2 1 .015 [.18] .0256 [.65] .102 max pin 1 index top view side view bottom view end view .502.008 .885.010 .427 [10.85] .417 [10.59] .527 [13.39] .517 [13.13] .0256 [.65] bsc .016 [.41] standard tsop pad layout is acceptable, however, when possible, the following pad layout is recommended for optimal manufacture and inspection. see application note 53a001-00 for further information. [12.75.20] [22.48.25] [2.59 max] .819 [20.80] bsc .020 [.51] typ typ dpac technologies products & services for the integration age 7321 lincoln way, garden grove, ca 92841 te l 714 898 0007 fax 714 897 1772 www.dpactech.com nasdaq: dpac ?2002 dpac technologies, all rights reserved. dpac technologies?, memory stack?, system stack?, cs stack? are trademarks of dpac technologies corp. dpdd16mx8rsby5 128 megabit cmos ddr sdram preliminary mechanical drawing * contact your sales representative for supplier and manufacturer codes.
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