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32-channel, 14-bit voltage-output dac ad5532 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2010 analog devices, inc. all rights reserved. features high integration: 32-channel dac in 12 mm 12 mm cspbga adjustable voltage output range guaranteed monotonic readback capability dsp/microcontroller compat ible serial interface output impedance: 0.5 (ad5532-1, ad5532-2) 500 (ad5532-3) 1 k (ad5532-5) output voltage span: 10 v (ad5532-1, ad5532-3, ad5532-5) 20 v (ad5532-2) infinite sample-and-hold capability to 0.018% accuracy temperature range ? 40c to +85c applications automatic test equipment optical networks level setting instrumentation industrial control systems data acquisition low cost i/o general description the ad5532 1 is a 32-channel, 14-bit voltage-output dac with an additional infinite sample-and-hold mode. the selected dac register is written to via the 3-wire serial interface; v out for this dac is then updated to reflect the new contents of the dac register. dac selection is accomplished via address bits a0Ca4. the output voltage range is determined by the offset voltage at the offs_in pin and the gain of the output amplifier. it is restricted to a range from v ss + 2 v to v dd C 2 v because of the headroom of the output amplifier. the device is operated with av cc = 5 v 5%; dv cc = 2.7 v to 5.25 v; v ss = ? 4.75 v to ? 16.5 v; and v dd = 8 v to 16.5 v. the ad5532 requires a stable 3 v reference on ref_in as well as an offset voltage on offs_in. product highlights 1. 32-channel, 14-bit dac in one package, guaranteed monotonic. 2. available in a 74-lead cspbga package with a body size of 12 mm 12 mm. 3. droopless/infinite sample-and-hold mode. 1 protected by u.s. patent no. 5,969,657; other patents pending. 00939-c-001 sclk d in d out a4?a0 cal offset_sel ad5532 address input register dac dac adc mux dac mode 14-bit bus v in track/reset busy dac_gnd agnd dgnd interface control logic ser/par dv cc v out 0 offs_out v out 31 av cc ref_in ref_out offs_in v dd v ss wr sync/cs figure 1. functional block diagram
ad5532 rev. d | page 2 of 20 table of contents specifications ..................................................................................... 3 isha mode .................................................................................... 5 timing characteristics ..................................................................... 6 parallel interface ........................................................................... 6 parallel interface timing diagrams ........................................... 6 serial interface .............................................................................. 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 terminology .................................................................................... 11 dac mode .................................................................................... 11 isha mode .................................................................................. 11 typical performance characteristics ........................................... 12 functional description .................................................................. 14 output buffer stagegain and offset.................................... 14 offset voltage channel .............................................................. 14 reset function ............................................................................ 14 isha mode ................................................................................. 14 analog input (isha mode) ...................................................... 14 track function (isha mode) .............................................. 15 modes of operation ................................................................... 15 serial interface ............................................................................ 16 parallel interface (isha mode only) ...................................... 17 microprocessor interfacing ....................................................... 17 application circuits ................................................................... 18 power supply decoupling ......................................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 6/10data sheet changed from rev. c to rev. d changes to table 5 ...................................................................... 8 changes to ordering guide .................................................... 20 6/04data sheet changed from rev. b to rev. c updated format ........................................................... universal changed lfbga to cspbga .................................... universal changes to outline dimensions ............................................. 24 changes to ordering guide .................................................... 24 6/02data sheet changed from rev. a to rev. b term sha changed to isha ........................................... global changes to absolute maximum ratings ................................. 6 changes to ordering guide ...................................................... 6 changes to functional description ....................................... 11 changes to tabl e 8 .................................................................... 11 changes to isha mode ........................................................... 11 added figure 27 and accompanying text .............................. 15 changes to power supply decoupling section ..................... 15
ad5532 rev. d | page 3 of 20 specifications v dd = 8 v to 16.5 v, v ss = C4.75 v to C16.5 v; av cc = 4.75 v to 5.25 v; dv cc = 2.7 v to 5.25 v; agnd = dgnd = dac_gnd = 0 v; ref_in = 3 v; output range from v ss + 2 v to v dd ? 2 v. all outputs unloaded. all specifications t min to t max , unless otherwise noted. table 1. a version 1 parameter 2 ad5532-1/-3/-5 ad5532-2 only unit conditions/comments dac dc performance resolution 14 14 bits integral nonlinearity (inl) 0.39 0.39 % of fsr max 0.15% typ differential nonlinearity (dnl) 1 1 lsb max 0.5 lsb typ, monotonic offset 90/170/250 180/350/500 mv min/typ/max see figure 8 gain 3.52 7 typ full scale error 2 2 % of fsr max voltage reference ref_in nominal input voltage 3.0 3.0 v typ input voltage range 3 2.85/3.15 2.85/3.15 v min/max input current 1 1 a max < 1 na typ ref_out output voltage 3 3 v typ output impedance 3 280 280 k typ reference temperature coefficient 3 60 60 ppm/c typ analog outputs (v out 0C31) output temperature coefficient 3 , 4 10 10 ppm/c typ dc output impedance 3 ad5532-1 0.5 0.5 typ ad5532-3 500 typ ad5532-5 1 k typ output range v ss + 2/v dd ? 2 v ss + 2 /v dd ? 2 v min/max resistive load 3 , 5 5 5 k min capacitive load 3 , 5 ad5532-1 500 500 pf max ad5532-3 15 nf max ad5532-5 40 nf max short-circuit current 3 7 7 ma typ dc power-supply rejection ratio 3 ? 70 ? 70 db typ v dd = +15 v 5% ? 70 ? 70 db typ v ss = ? 15 v 5% dc crosstalk 3 250 1800 v max analog output (offs_out) output temperature coefficient 3 , 4 10 10 ppm/c typ dc output impedance 3 1.3 1.3 k typ output range 50 to ref_in ? 12 50 to ref_in ? 12 mv typ output current 10 10 a max source current capacitive load 100 100 pf max digital inputs 3 input current 10 10 a max 5 a typ input low voltage 0.8 0.8 v max dv cc = 5 v 5% 0.4 0.4 v max dv cc = 3 v 10% input high voltage 2.4 2.4 v min dv cc = 5 v 5% 2.0 2.0 v min dv cc = 3 v 10% input hysteresis (sclk and cs only) 200 200 mv typ
ad5532 rev. d | page 4 of 20 a version 1 parameter 2 ad5532-1/-3/-5 ad5532-2 only unit conditions/comments input capacitance 10 10 pf max digital outputs ( busy , d out ) 3 output low voltage, dv cc = 5 v 0.4 0.4 v max sinking 200 a. output high voltage, dv cc = 5 v 4.0 4.0 v min sourcing 200 a. output low voltage, dv cc = 3 v 0.4 0.4 v max sinking 200 a. output high voltage, dv cc = 3 v 2.4 2.4 v min sourcing 200 a. high impedance leakage current 1 1 a max d out only. high impedance output capacitance 15 15 pf typ d out only. power requirements power-supply voltages v dd 8/16.5 8/16.5 v min/max v ss ? 4.75/ ? 16.5 ? 4.75/ ? 16.5 v min/max av cc 4.75/5.25 4.75/5.25 v min/max dv cc 2.7/5.25 2.7/5.25 v min/max power-supply currents 6 i dd 15 15 ma max 10 ma typ. all channels full scale. i ss 15 15 ma max 10 ma typ. all channels full scale. aicc 33 33 ma max 26 ma typ. dicc 1.5 1.5 ma max 1 ma typ. power dissipation 6 280 280 mw typ v dd = 10 v, v ss = ? 5 v. ac characteristics 3 output voltage settling time 22 30 s max 500 pf, 5 k load. full-scale change. offs_in settling time 10 25 s max 500 pf, 5 k load; 0 v to 3 v step. digital-to-analog glitch impulse 1 1 nv-s typ 1 lsb change around. major carry. digital crosstalk 5 5 nv-s typ analog crosstalk 1 1 nv-s typ digital feedthrough 0.2 0.2 nv-s typ output noise spectral density @ 1 khz 400 400 nv/(hz) typ 1 a version: industrial temperature range -40c to +85c; typical at +25c. 2 see terminology section. 3 guaranteed by design and characterization, not production tested. 4 ad780 as reference for the ad5532. 5 ensure that you do not exceed t j (max). see absolute maximum ratings section. 6 output unloaded.
ad5532 rev. d | page 5 of 20 isha mode table 2. a version 1 parameter 2 ad5532-1/-3/-5 ad5532-2 only unit conditions/comments analog channel v in to v out nonlinearity 3 0.018 0.018 % max 0.006% typ after offset and gain adjustment. offset error 50 75 mv max 10 mv typ. see figure 9 . gain 3.46/3.52/3.6 6.96/ 7/7.02 min/typ/max see figure 9 analog input (v in ) input voltage range 0 to 3 0 to 3 v nominal input range. input lower dead band 70 70 mv max 50 mv typ. referred to v in . see figure 9 . input upper dead band 40 40 mv max 12 mv typ. referred to v in . see figure 9 . input current 1 1 a max 100 na typ. v in acquired on 1 channel. input capacitance 4 20 20 pf typ analog input (offs_in) input current 1 1 a max 100 na typ. input voltage range 0/4 0/4 vmin/max output range restricted from v ss + 2 v to v dd ? 2 v. ac characteristics output settling time 4 3 3 s max output unloaded. acquisition time 16 16 s max ac crosstalk 4 5 5 nv-s typ 1 a version: industrial temperature range -40c to +85c; typical at +25c. 2 see terminology section. 3 input range 100 mv to 2.96 v. 4 guaranteed by design and characterization, not production tested.
ad5532 rev. d | page 6 of 20 timing characteristics parallel interface table 3. parameter 1 , 2 limit at t min , t max (a version) unit conditions/comments t 1 0 ns min cs to wr setup time t 2 0 ns min cs to wr hold time t 3 50 ns min cs pulse width low t 4 50 ns min wr pulse width low t 5 20 ns min a4Ca0, cal, offs_sel to wr setup time t 6 7 ns min a4Ca0, cal, offs_sel to wr hold time 1 see figure 2 and figure 3, the pa rallel interface timing diagrams. 2 parallel interface timing diagrams guaranteed by design and characterization, not production tested. 00939-c-002 a4?a0, cal, offs_sel t 1 t 3 t 2 t 4 t 5 t 6 cs wr figure 2. parallel write (isha mode only) 00939-c-003 200 ai ol 200 ai oh 1.6v to output pin c l 50pf figure 3. load circuit for d out timing specifications
ad5532 rev. d | page 7 of 20 serial interface table 4. parameter 1 , 2 limit at t min , t max (a version) unit conditions/comments f clkin 3 14 mhz max sclk frequency t 1 28 ns min sclk high pulse width t 2 28 ns min sclk low pulse width sync falling edge to sclk falling edge setup time t 3 15 ns min sync low time t 4 50 ns min t 5 10 ns min d in setup time t 6 5 ns min d in hold time sync falling edge to sclk rising edge setup time for read back t 7 5 ns min t 8 4 20 ns max sclk rising edge to d out valid t 9 4 60 ns max sclk falling edge to d out high impedance 10th sclk falling edge to sync falling edge for read back t 10 400 ns min 24th sclk falling edge to sync falling edge for dac mode write t 11 400 ns min sclk falling edge to sync falling edge setup time for read back t 12 5 7 ns min 00939-c-004 t 1 t 3 t 2 msb lsb sclk 1234567891 0 sync d in t 4 t 5 t 6 figure 4. 10-bit write (isha mo de and both readback modes) 00939-c-005 sclk 12345 2 12 22 32 4 1 d in sync t 1 t 3 t 2 t 4 t 5 t 6 lsb msb t 11 figure 5. 24-bit write (dac mode) 00939-c-006 sclk 10 1234567891011121314 msb lsb d out sync t 7 t 1 t 2 t 12 t 4 t 8 t 10 t 9 figure 6. 14-bit read (both readback modes) 1 see figure 4, figure 5, and figure 6. 2 guaranteed by design and characterization, not production tested. 3 in isha mode the maximum sc lk frequency is 20 mhz and the minimum pulse width is 20 ns. 4 these numbers are measured with the load circuit of figure 3. 5 sync should be taken low while sclk is low for read back.
ad5532 rev. d | page 8 of 20 absolute maximum ratings t a = 25c unless otherwise noted. table 5. parameter 1 rating v dd to agnd ? 0.3 v to +17 v v ss to agnd +0.3 v to ? 17 v av cc to agnd, dac_gnd ? 0.3 v to +7 v dv cc to dgnd ? 0.3 v to +7 v digital inputs to dgnd ? 0.3 v to dv cc + 0.3 v digital outputs to dgnd ? 0.3 v to dv cc + 0.3 v ref_in to agnd, dac_ gnd ? 0.3 v to av cc + 0.3 v v in to agnd, dac_gnd ? 0.3 v to av cc + 0.3 v v out 0C31 to agnd v ss ? 0.3 v to v dd + 0.3 v offs_in to agnd v ss ? 0.3 v to v dd + 0.3 v offs_out to agnd agnd - 0.3 v to av cc + 0.3 v agnd to dgnd ? 0.3 v to +0.3 v operating temperature range industrial ? 40c to +85c storage temperature range ? 65c to +150c junction temperature (t j max) 150c 74-lead cspbga package, ja thermal impedance 41c/w reflow soldering peak temperature ad5532abc-x 220c ad5532abcz-x 260c time at peak temperature 10 sec to 40 sec max power dissipation (150c ? t a )/ ja mw 2 max continuous load current at t j = 70c, per channel group 15 ma 3 1 transient currents of up to 100 ma do not cause scr latch-up. 2 this limit includes load power. 3 this maximum allowed continuous load current is spread over 8 channels and channels are grouped as follows: group 1: channels 3, 4, 5, 6, 7, 8, 9, 10 group 2: channels 14, 16, 18, 20. 21, 24, 25, 26 group 3: channels 15, 17, 19, 22, 23, 27, 28, 29 group 4: channels 0, 1, 2, 11, 12, 13, 30, 31 stresses above those listed u nder absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is no t implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for higher junction temperatures derate as follows: tj (c) max continuous load current per group (ma) 70 15.5 90 9.025 100 6.925 110 5.175 125 3.425 135 2.55 150 1.5 esd caution
ad5532 rev. d | page 9 of 20 pin configuration and fu nction descriptions 00939-c-028 a b c d e f g h j k l a 1234567891011 1234567891011 b c d e f g h j k l top view figure 7. 74-lead cspbga ball configuration table 6. 74-lead cspbga ball configuration cspbga number ball name cspbga number ball name cspbga number ball name a1 not connected c10 av cc 1 j10 vo9 a2 a4 c11 ref_out j11 vo11 a3 a2 d1 vo20 k1 vo17 a4 a0 d2 dac_gnd2 k2 vo15 a5 cs / sync d10 av cc 2 k3 vo27 a6 dv cc d11 offs_out k4 v ss 3 a7 sclk e1 vo26 k5 v ss 1 a8 offset_sel e2 vo14 k6 v ss 4 a9 busy e10 agnd1 k7 v dd 2 a10 track / reset e11 offs_in k8 vo2 a11 not connected f1 vo25 k9 vo10 b1 vo16 f2 vo21 k10 vo13 b2 not connected f10 agnd2 k11 vo12 b3 a3 f11 vo6 l1 not connected b4 a1 g1 vo24 l2 vo28 b5 wr g2 vo8 l3 vo29 b6 dgnd g10 vo5 l4 vo30 b7 d in g11 vo3 l5 v dd 3 b8 cal h1 vo23 l6 v dd 1 b9 ser/ par h2 vin l7 v dd 4 b10 dout h10 vo4 l8 vo31 b11 ref_in h11 vo7 l9 vo0 c1 vo18 j1 vo22 l10 vo1 c2 dac_gnd1 j2 vo19 l11 not connected c6 not connected j6 v ss 2
ad5532 rev. d | page 10 of 20 table 7. pin function descriptions pin function agnd (1C2) analog gnd pins. av cc (1C2) analog supply pins. voltage range from 4.75 v to 5.25 v. v dd (1C4) v dd supply pins. voltage range from 8 v to 16.5 v. v ss (1C4) v ss supply pins. voltage range from C4.75 v to C16.5 v. dgnd digital gnd pins. dv cc digital supply pins. voltage range from 2.7 v to 5.25 v. dac_gnd (1C2) reference gnd supply for all dacs. ref_in reference voltage for channels 0C31. ref_out reference output voltage. v out (0C31) analog output volt ages from the 32 channels. v in analog input voltage. connect this to agnd if operating in dac mode only. a4Ca1, a0 parallel interface: 5 address pins for 32 channels. a4 = msb of channel address. a0 = lsb. internal pull-up devices on these logic inputs. therefore, they can be left floa ting and default to a logic high condition. cal parallel interface: control input that allows all 32 channels to acquire v in simultaneously. internal pull-down devices on these logic inputs. therefore, they can be left floating and default to a logic low condition cs / sync this is the active low chip select pin fo r the parallel interface and the frame sync hronization pin for the serial interface. wr parallel interface: write pin; active low. this is used in conjunction with the cs pin to address the device using the parallel interface. internal pull-down devices on th ese logic inputs. therefore, they can be left floating and default to a logic low condition. offset_sel parallel interface: offset select pin; acti ve high. this is used to select the offset channel. internal pull-down devices on these logic inputs. therefore, they can be left floating and default to a logic low condition sclk serial clock input for serial in terface. this operates at clock speeds up to 14 mhz (20 mhz in isha mode). d in data input for serial interface. data must be valid on the falling edge of sclk. internal pull-up devices on these logic inputs. therefore, they can be left floating and default to a logic high condition. d out output from the dac registers for read back . data is clocked out on the rising edge of sclk and is valid on the falling edge of sclk. ser/ par this pin allows the user to select whether the serial or para llel interface is used. if the pi n is tied low, the parallel int erface is used. if it is tied high, the serial interface is used. internal pull-down device s on these logic inputs. therefore, they ca n be left floating and defaul t to a logic low condition. offs_in offset input. the user can supply a voltag e here to offset the output span. offs_out can also be tied to this pin if the user wants to drive this pi n with the offset channel. offs_out offset output. this is the acquired/programmed offset voltage which can be tied to offs_i n to offset the span. busy this output tells the user when the input voltage is being acquired. it goes low during acquisition and returns high when the acquisition operation is complete. track / reset if this input is held high, v in is acquired once the channel is addressed. whil e it is held low, the input to the gain/offset stage is switched directly to v in . the addressed channel begins to acquire v in on the rising edge of track . see track input section for further information. this input can also be used as a means of resetting the complete device to its power-on-reset conditions. this is achiev ed by applying a low-going pulse of be tween 90 ns and 200 ns to this pin. see section on reset function for further details. internal pull-up device s on these logic inputs. therefore, they can be left floating and default to a logic high condition. 00939-c-008 v out ideal transfer function upper dead band lower dead band offset error actual transfer function gain error + offset error v in 2.96 3v 70mv 0v 00939-c-007 dac code 0 16k output voltage ideal transfer function ideal gain refin ideal gain 50mv full-scale error range offset range figure 8. dac transfer function (offs_in=0) figure 9. isha transfer function
ad5532 rev. d | page 11 of 20 terminology dac mode integral nonlinearity (inl) this is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is expressed as a percentage of full-scale span. differential nonlinearity (dnl) this is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified dnl of 1 lsb maximum ensures monotonicity. offset offset is a measure of the output with all zeros loaded to the dac and offs_in = 0. because the dac is lifted off the ground by approximately 50 mv, this output is typically mv50 = gain v out full-scale error this is a measure of the output error with all 1s loaded to the dac. it is expressed as a percentage of full-scale range. see figure 8 . it is calculated as ( ) refin gainideal verrorscalefull scalefullout ? = ? ? )( where 25532adfor7 5/3/15532adfor52.3 ? = ??? = gainideal gainideal output settling time this is the time taken from when the last data bit is clocked into the dac until the output has settled to within 0.39%. offs_in settling time the time taken from a 0 v to 3 v step change in input voltage on offs_in until the output has settled to within 0.39%. digital-to-analog glitch impulse this is the area of the glitch injected into the analog output when the code in the dac register changes state. it is specified as the area of the glitch in nv-secs when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale while a full-scale code change (all 1s to all 0s and vice versa) is written to another dac. it is expressed in nv-secs. analog crosstalk this is the area of the glitch transferred to the output (v out ) of one dac due to a full-scale change in the output (v out ) of another dac. the area of the glitch is expressed in nv-secs. digital feedthrough this is a measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to, i.e., cs / sync is high. it is specified in nv-secs and is measured with a worst-case change on the digital input pins, for example, from all 0s to all 1s and vice versa. output noise spectral density this is a measure of internally generated random noise. random noise is characterized as a spectral density (voltage per root hertz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/( hz ). output temperature coefficient this is a measure of the change in analog output with changes in temperature. it is expressed in ppm/c. dc power-supply rejection ratio (psrr) dc power-supply rejection ratio is a measure of the change in analog output for a change in supply voltage (v dd and v ss ). it is expressed in dbs. v dd and v ss are varied 5%. dc crosstalk this is the dc change in the output level of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and an output change of all other dacs. it is expressed in v. isha mode v in to v out nonlinearity the measure of the maximum deviation from a straight line passing through the endpoints of the v in versus v out transfer function. it is expressed as a percentage of the full-scale span. offset error this is a measure of the output error when v in = 70 mv. ideally, with v in = 70 mv: ( ) ( ) ( ) mv 1 70 _ inoffs out vgain gain v ? ? = offset error is a measure of the difference between v out (actual) and v out (ideal). it is expressed in mv and can be positive or negative. see figure 9 . gain error this is a measure of the span error of the analog channel. it is the deviation in slope of the transfer function expressed in mv. see figure 9 . it is calculated as gain error = actual full-scale output ? ideal full-scale output ? offset error where: ( ) ( ) inoffs vgain gain outputscalefullideal _ 1 96.2 ? ?= ? ac crosstalk this is the area of the glitch that occurs on the output of one channel while another channel is acquiring. it is expressed in nv-secs. output settling time this is the time taken from when busy goes high to when the output has settled to 0.018%. acquisition time this is the time taken for the v in input to be acquired. it is the length of time that busy stays low.
ad5532 rev. d | page 12 of 20 typical performance characteristics 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 12k 10k 8k6k4k2k 14k 16k 00939-c-009 dac code dnl error (lsb) v refin = 3v v offs_in = 0v t a = 25 c figure 10. typical dnl plot 1.0 ?1.0 ?0.5 0 0.5 0.2 ?0.2 ?0.1 0 0.1 ?40 40 08 0 00939-c-010 temperature (c) dnl error (lsb) inl error (% fsr) dnl min inl min dnl max inl max figure 11. inl error an dnl error vs. temperature 5.325 5.275 5.285 5.295 5.305 5.315 ?40 40 08 00939-c-011 temperature ( c) v out (v) 0 dac loaded to midscale v refin = 3v v offs_in = 0v figure 12. v out vs. temperature 3.535 3.520 3.525 3.530 6420?2?4? 00939-c-012 sink/source current (ma) v out (v) 6 t a = 25 c v refin = 3v figure 13. v out source and sink capability 10 ?2 0 2 4 6 8 00939-c-013 time base (2 s/div) v out (v) t a = 25 c v refin = 3v v offs_in = 0.5v figure 14. full-scale settling time 5.309 5.308 5.307 5.306 5.305 5.304 5.303 5.302 5.301 00939-c-014 time base (50ns/div) v out (v) t a = 25 c v refin = 3v v offs_in = 0v figure 15. major code transition glitch impulse
ad5532 rev. d | page 13 of 20 0.024 ?0.024 ?0.020 ?0.016 ?0.012 ?0.008 ?0.004 0 0.004 0.008 0.012 0.016 0.020 0.10 2.96 00939-c-015 v in (v) v out error (%) t a = 25 c v refin = 3v v offs_in = 0v figure 16. v in to v out accuracy after offset an d gain adjustment (isha mode) 00939-c-016 t a = 25 c v refin = 3v v in = 0 1.5v 2 s 1v 5v 100 90 10 0% v out busy figure 17. acquisition time and output settling time (isha mode) 70k 0 10k 20k 30k 40k 50k 60k 5.2670 5.2676 5.2682 00939-c-017 v out (v) frequency t a = 25 c v refin = 3v v in = 1.5v v offs_in = 0v 63791 1545 200 figure 18. isha-mode repeatability (64 k acquisitions)
ad5532 rev. d | page 14 of 20 functional description the ad5532 consists of 32 dacs and an adc (for isha mode) in a single package. in dac mode, a 14-bit digital word is loaded into one of the 32 dac registers via the serial interface. this is then converted (with gain and offset) into an analog output voltage (v out 0Cv out 31). to update a dacs output voltage, the required dac is addressed via the serial port. when the dac address and code have been loaded, the selected dac converts the code. at power-on, all the dacs, including the offset channel, are loaded with zeros. each of the 33 dacs is offset internally by 50 mv (typ) from gnd, so the outputs v out 0 to v out 31 are 50 mv (typ) at power-on if the offs_in pin is driven directly by the on-board offset channel (offs_out), i.e. if offs_in is 50 mv, v out = (gain v dac ) C (gain C 1) v offs_in = 50 mv. output buffer stagegain and offset the function of the output buffer stage is to translate the 50 mvC3 v output of the dac to a wider range. this is done by gaining up the dac output by 3.52/7 and offsetting the voltage by the voltage on offs_in pin. ad5532-1/ad5532-3/ad5532-5: inoffs dac out v v v _ 52.2 52.3 ?= ad5532-2: inoffs dac out v v v _ 6 7 ?= v dac is the output of the dac. v offs_in is the voltage at the offs_in pin. the following table shows how the output range on v out relates to the offset voltage supplied by the user. table 8. sample output voltage ranges v offs_in v dac v out v out (v) (v) (ad5532-1/-3/-5) (ad5532-2) 0.5 0.05 to 3 ? 1.26 to +9.3 headroom limited 1 0.05 to 3 ? 2.52 to +8.04 ? 6 to +15 v out is limited only by the headroom of the output amplifiers. v out must be within maximum ratings. offset voltage channel the offset voltage can be externally supplied by the user at offs_in or it can be supplied by an additional offset voltage channel on the device itself. the offset can be set up in two ways. in isha mode, the required offset voltage is set up on v in and acquired by the offset channel. in dac mode, the code corresponding to the offset value is loaded directly into the offset dac. this offset channels dac output is directly connected to offs_out. by connecting offs_out to offs_in this offset voltage can be used as the offset voltage for the 32 output amplifiers. it is important to choose the offset so that v out is within maximum ratings. reset function the reset function on the ad5532 can be used to reset all nodes on this device to their power-on reset condition. this is implemented by applying a low-going pulse of between 90 ns and 200 ns to the track / reset pin on the device. if the applied pulse is less than 90 ns, it is assumed to be a glitch and no operation takes place. if the applied pulse is wider than 200 ns, this pin adopts its track function on the selected channel, v in is switched to the output buffer, and an acquisition on the channel does not occur until a rising edge of track . isha mode in isha mode, the input voltage v in is sampled and converted into a digital word. the noninverting input to the output buffer (gain and offset stage) is tied to v in during the acquisition period to avoid spurious outputs, while the dac acquires the correct code. this is completed in 16 s max. the updated dac output then assumes control of the output voltage. the output voltage of the dac is connected to the noninverting input of the output buffer. because the channel output voltage is effectively the output of a dac, there is no droop associated with it. as long as power is maintained to the device, the output voltage is constant until this channel is addressed again. because the internal dacs are offset by 70 mv (max) from gnd, the minimum v in in isha mode is 70 mv. the maximum v in is 2.96 v due to the upper dead band of 40 mv (max). analog input (isha mode) figure 19 shows the equivalent analog input circuit. the capacitor c1 is typically 20 pf and can be attributed to pin capacitance and 32 off-channels. when a channel is selected, an extra 7.5 pf (typ) is switched in. this capacitor c2 is charged to the previously acquired voltage on that particular channel so it must charge/discharge to the new level. the external source must be able to charge/discharge this additional capacitance within 1 sC2 s of channel selection so that v in can be acquired accurately. thus, a low impedance source is suggested. 00939-c-018 v in c2 7.5pf c1 20pf addressed channel figure 19. analog input circuit large source impedances significantly affect the performance of the adc. an input buffer amplifier may be required.
ad5532 rev. d | page 15 of 20 track function (isha mode) typically in isha mode of operation track is held high and the channel begins to acquire when it is addressed. however, if track is low when the channel is addressed, v in is switched to the output buffer and an acquisition on the channel does not occur until a rising edge of track . at this stage, the busy pin goes low until the acquisition is complete, at which point the dac assumes control of the voltage to the output buffer and v in is free to change again without affecting this output value. this is useful in an application where the user wants to ramp up v in until v out reaches a particular level (see figure 20 ). v in does not need to be acquired continuously while it is ramping up. track can be kept low and only when v out has reached its desired voltage is track brought high. at this stage, the acquisition of v in begins. in the example shown, a desired voltage is required on the output of the pin driver. this voltage is represented by one input to a comparator. the microcontroller/microprocessor ramps up the input voltage on v in through a dac. track is kept low while the voltage on v in ramps up so that v in is not continually acquired. when the desired voltage is reached on the output of the pin driver, the comparator output switches. the c/p then knows what code is required to be input to obtain the desired voltage at the dut. the track input is now brought high and the part begins to acquire v in . at this stage busy goes low until v in has been acquired. the output buffer is then switched from v in to the output of the dac. modes of operation the ad5532 can be used in four different modes of operation. these modes are set by two mode bits, the first two bits in the serial word. table 9. modes of operation mode bit 1 mode bit 2 operating mode 0 0 isha mode 0 1 dac mode 1 0 acquire and read back 1 1 read back 1. isha mode in this mode, a channel is addressed and that channel acquires the voltage on v in . this mode requires a 10-bit write (see figure 21 a) to address the relevant channel (v out 0Cv out 31, offset channel or all channels). msb is written first. 2. dac mode in this standard mode, a selected dac register is loaded serially. this requires a 24-bit write (10 bits to address the relevant dac plus an extra 14 bits of dac data). msb is written first. the user must allow 400 ns (min) between successive writes in dac mode. 3. acquire and readback mode this mode allows the user to acquire v in and read back the data in a particular dac register. the relevant channel is addressed (10-bit write, msb first) and v in is acquired in 16 s (max). following the acquisition, after the next falling edge of sync , the data in the relevant dac register is clocked out onto the d out line in a 14-bit serial format. the full acquisition time must elapse before the dac register data can be clocked out. 4. readback mode again, this is a readback mode but no acquisition is performed. the relevant channel is addressed (10-bit write, msb first) and on the next falling edge of sync , the data in the relevant dac register is clocked out onto the d out line in a 14-bit serial format. the user must allow 400 ns (min) between the last sclk falling edge in the 10-bit write and the falling edge of sync in the 14-bit read back. the serial write and read words can be seen in . figure 21 this feature allows the user to read back the dac register code of any of the channels. in dac mode, this is useful in verification of write cycles. in isha mode, readback is useful if the system has been calibrated and the user wants to know what code in the dac corresponds to a desired voltage on v out . if this voltage is required again, the user can input the code directly to the dac register without going through the acquisition sequence. 00939-c-019 track v in dac acquisition circuit v out 1 busy output stage controller pin driver device under test threshold voltage only one channel shown for simplicity ad5532 figure 20. typical ate circuit using track input
ad5532 rev. d | page 16 of 20 serial interface the serial interface allows easy interfacing to most micro- controllers and dsps, such as the pic16c, pic17c, qspi, spi, dsp56000, tms320, and adsp-21xx, without the need for any glue logic. when interfacing to the 8051, the sclk must be inverted. the microprocessor interfacing section explains how to interface to some popular dsps and microcontrollers. figure 4, figure 5 , and figure 6 show the timing diagram for a serial read and write to the ad5532. the serial interface works with both a continuous and a noncontinuous serial clock. the first falling edge of sync resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. any further edges on sync are ignored until the correct number of bits are shifted in or out. once the correct number of bits for the selected mode has been shifted in or out, the sclk is ignored. in order for another serial transfer to take place the counter must be reset by the falling edge of sync . in readback, the first rising sclk edge after the falling edge of sync causes d out to leave its high impedance state and data is clocked out onto the d out line and also on subsequent sclk rising edges. the d out pin goes back into a high impedance state on the falling edge of the 14th sclk. data on the d in line is latched in on the first sclk falling edge after the falling edge of the sync signal and on subsequent sclk falling edges. during read-back d in is ignored. the serial interface does not shift data in or out until it receives the falling edge of the sync signal. table 10 pin description ser/ par this pin is tied high to enable the serial interface and to disable the parallel interface. the serial interface is controlled by th e four pins that follow. sync , d in , sclk standard 3-wire interface pins. the sync pin is shared with the cs function of the parallel interface. d out data out pin for reading ba ck the contents of the dac registers. the data is clocked out on the rising edge of sclk and is valid on the falling edge of sclk. mode bits the four different modes of operation are described in the modes of operation section. cal bit in dac mode, this is a test bit. when high, it loads all 0s or all 1s to the 32 dacs simultaneously. in isha mode, all 32 channels acquire v in at the same time when this bit is high. in isha mode, the acquisition time is then 45 s (typ ) and accuracy may be reduced. this bit is set low for normal use. offset sel bit if this is set high, the offs et channel is selected and bits a4Ca0 are ignored. test bit must be set low for correct operation of the part. a4Ca0 used to address any one of the 32 channels (a4 = msb of address, a0 = lsb). db13C db0 used to write a 14-bit word into the addressed dac register. only valid when in dac mode. 00939-c-020 offset_sel a4?a0 cal 0 0 msb lsb mode bit 1 mode bit 2 mode bits 0 test bit offset_sel a4?a0 cal 1 0 msb lsb mode bits db13?db0 0 test bit a. 10-bit serial write word (isha mode) b. 24-bit input serial write word (dac mode) c. input serial interface (acquire and read-back mode) d. input serial interface (read-back mode) offset_sel a4?a0 cal 0 1 msb lsb mode bits db13?db0 0 test bit 10-bit serial word written to part 14-bit data read from part after next falling edge of sync (db13 = msb of dac word) msb lsb 10-bit serial word written to part 14-bit data read from part after next falling edge of sync (db13 = msb of dac word) offset_sel a4?a0 cal 1 1 msb lsb mode bits db13?db0 0 test bit msb lsb figure 21. serial interface formats
ad5532 rev. d | page 17 of 20 parallel interface (isha mode only) the ser/ par bit must be tied low to enable the parallel interface and disable the serial interface. the parallel interface is controlled by nine pins, as described in . table 1 1 table 11. pin description cs active low package select pin. this pin is shared with the sync function for the serial interface. wr active low write pin. the values on the address pins are latched on a rising edge of wr . a4Ca0 five address pins (a4 = msb of address, a0 = lsb). these are used to address the relevant channel (out of a possible 32). offset_sel offset select pin. this has the same function as the offset_sel bit in the serial interface. when it is high, the offset cha nnel is addressed. the address on a4Ca0 is ignored in this case. cal when this pin is high, all 32 channels acquire vin simultaneously. the acquisition time is then 45 s (typ) and accuracy may be reduced. microprocessor interfacing ad5532 to adsp-21xx interface adsp-21xx dsps are easily interfaced to the ad5532 without the need for extra logic. a data transfer is initiated by writing a word to the tx register after the sport has been enabled. in a write sequence, data is clocked out on each rising edge of the dsp serial clock and clocked into the ad5532 on the falling edge of its sclk. in readback, 16 bits of data are clocked out of the ad5532 on each rising edge of sclk and clocked into the dsp on the rising edge of sclk. d in is ignored. the valid 14 bits of data is centered in the 16-bit rx register in this configuration. the sport control register should be set up as in table 12 . table 12. tfsw = rfsw = 1 alternate framing invrfs = invtfs = 1 active low frame signal dtype = 00 right justify data isclk = 1 internal serial clock tfsr = rfsr = 1 frame every word irfs = 0 external framing signal itfs = 1 internal framing signal slen = 1001 10-bit data-words (isha mode write) slen = 0111 3 8-bit data-words (dac mode write) slen = 1111 16-bit data-words (readback mode) figure 22 shows the connection diagram. 00939-c-021 d out ad5532* *additional pins omitted for clarity sync d in sclk dr tfs dt rfs sclk adsp-2101/ adsp-2103* figure 22. ad5532 to adsp -2101/adsp-2103 interface ad5532 to mc68hc11 the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr)see the 68hc11 user manual . sck of the 68hc11 drives the sclk of the ad5532, the mosi output drives the serial data line (d in ) of the ad5532, and the miso input is driven from d out . the sync signal is derived from a port line (pc7). when data is being transmitted to the ad5532, the sync line is taken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to transmit 10 data bits in isha mode, it is important to left-justify the data in the spdr register. pc7 must be pulled low to start a transfer. it is taken high and pulled low again before other read/write cycles can take place. shows a connection diagram. figure 23 00939-c-022 ad5532* *additional pins omitted for clarity mc68hc11* d out miso d in mosi sclk sck pc7 sync figure 23. ad5532 to mc68hc11 interface
ad5532 rev. d | page 18 of 20 ad5532 to pic16c6x/7x the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit = 0. this is done by writing to the synchronous serial port control register (sspcon). see the pic16/17 microcontroller user manual . in this example, the i/o port ra1 is being used to pulse sync and enable the serial port of the ad5532. this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two or three consecutive read/write operations are needed depending on the mode. shows the connection diagram. figure 24 00939-c-023 ad5532* *additional pins omitted for clarity pic16c6x/7x* sclk sck/rc3 d out sdo/rc5 d in sdi/rc4 ra1 sync figure 24. ad5532 to pic16c6x/7x interface ad5532 to 8051 the ad5532 requires a clock synchronized to the serial data. the 8051 serial interface must therefore be operated in mode 0. in this mode, serial data enters and exits through rxd and a shift clock is output on txd. figure 25 shows how the 8051 is connected to the ad5532. because the ad5532 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. the ad5532 requires its data with the msb first. because the 8051 outputs the lsb first, the transmit routine must take this into account. 00939-c-024 ad5532* *additional pins omitted for clarity 8051* sclk txd d out rxd d in p1.1 sync figure 25. ad5532 to 8051 interface application circuits ad5532 in a typical ate system the ad5532 is ideally suited for use in automatic test equipment. several dacs are required to control pin drivers, comparators, active loads, and signal timing. traditionally, sample-and-hold devices were used in this application. the ad5532 has several advantages: no refreshing is required, there is no droop, pedestal error is eliminated, and there is no need for extra filtering to remove glitches. overall a higher level of integration is achieved in a smaller area (see figure 26 ). 00939-c-025 dacs active load parametric measurement unit driver comparator compare register stored data and inhibit pattern period generation and delay timing formatter system bus dac system bus dut dac dac dac dac dac dac figure 26. ad5532 in an ate system typical application circuit (dac mode) the ad5532 can be used in many optical networking applications that require a large number of dacs to perform control and measurement functions. in the example shown in figure 27 , the outputs of the ad5532 are amplified and used to control actuators that determine the position of mems mirrors in an optical switch. the exact position of each mirror is measured using sensors. the sensor readings are muxed using four dual, 4-channel matrix switches (adg739) and fed back to an 8-channel, 14-bit adc (ad7856). the control loop is driven by an adsp-2191m, a 16-bit fixed- point dsp with 3 sport interfaces and 2 spi ports. the dsp uses some of these serial ports to write data to the dac, control the multiplexer, and read back data from the adc. 00939-c-026 adsp-2191m ad5532 adg739 4 ad8544 2 ad7856 1 32 1 32 1 8 mems mirror array s e n s o r figure 27. typical optical control and measurement application circuit
ad5532 rev. d | page 19 of 20 typical application circuit (isha mode) the ad5532 can be used to set up voltage levels on 32 channels as shown in the circuit that follows. an ad780 provides the 3 v reference for the ad5532 and for the ad5541 16-bit dac. a simple 3-wire interface is used to write to the ad5541. because the ad5541 has an output resistance of 6.25 k ?? (typ), the time taken to charge/discharge the capacitance at the v in pin is significant. hence an ad820 is used to buffer the dac output. note that it is important to minimize noise on v in and refin when laying out the circuit. 00939-c-027 ad5532* offs_in offs_out refin v in sclk din sync av cc dv cc v out 0?v out 31 v ss v dd ad820 cs din sclk *additional pins omitted for clarity ad780* v out ad5541* ref av cc figure 28. typical application circuit (isha mode) power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5532 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5532 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. for supplies with multiple pins (v ss , v dd , av cc ) it is recom- mended to tie those pins together. the ad5532 should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. the power supply lines of the ad5532 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. a ground line routed between the d in and sclk lines helps reduce crosstalk between them (not required on a multilayer board as there is a separate ground plane, but separating the lines helps). note it is essential to minimize noise on v in and refin lines. particularly for optimum isha performance, the v in line must be kept noise free. depending on the noise performance of the board, a noise filtering capacitor may be required on the v in line. if this capacitor is necessary, then for optimum throughput it may be necessary to buffer the source which is driving v in . avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a micro-strip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. as is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of the package during the assembly process.
ad5532 rev. d | page 20 of 20 outline dimensions compliant to jedec standards mo-192-abd-1 061306-a a b c d e f g h j k l 1110987654321 1.00 bsc bottom view top view detail a 1.70 max 12.00 bsc sq 10.00 bsc sq a 1 corne r index area ball diameter 0.30 min 0.70 0.60 0.50 1.10 0.25 0.20 coplanarity ball a1 indicator seating plane detail a figure 29. 74-ball chip scale package ball grid array [csp_bga] (bc-74) dimensions shown in millimeters ordering guide model 1 temperature range function output impedance output voltage span package description package option ad5532abc-1 ? 40c to +85c 32 dacs, 32-channel isha 0.5 typ 10 v 74-ball csp_bga bc-74 ad5532abc-1reel ? 40c to +85c 32 dacs, 32-channel isha 0.5 typ 10 v 74-ball csp_bga bc-74 ad5532abc-2 ? 40c to +85c 32 dacs, 32-channel isha 0.5 typ 20 v 74-ball csp_bga bc-74 ad5532abc-3 ? 40c to +85c 32 dacs, 32-channel isha 500 typ 10 v 74-ball csp_bga bc-74 ad5532abc-3reel ? 40c to +85c 32 dacs, 32-channel isha 500 typ 10 v 74-ball csp_bga bc-74 ad5532abc-5 ? 40c to +85c 32 dacs, 32-channel isha 1 k typ 10 v 74-ball csp_bga bc-74 ad5532abc-5reel ? 40c to +85c 32 dacs, 32-channel isha 1 k typ 10 v 74-ball csp_bga bc-74 ad5532abcz-1 ? 40c to +85c 32 dacs, 32-channel isha 0.5 typ 10 v 74-ball csp_bga bc-74 ad5532abcz-1reel ? 40c to +85c 32 dacs, 32-channel isha 0.5 typ 10 v 74-ball csp_bga bc-74 ad5532abcz-2 ? 40c to +85c 32 dacs, 32-channel isha 0.5 typ 20 v 74-ball csp_bga bc-74 ad5532abcz-3 ? 40c to +85c 32 dacs, 32-channel isha 500 typ 10 v 74-ball csp_bga bc-74 ad5532abc-5 ? 40c to +85c 32 dacs, 32-channel isha 1 k typ 10 v 74-ball csp_bga bc-74 eval-ad5532ebz evaluation board 1 z = rohs compliant part. ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00939-0-6/10(d)

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