the udn5822a, ucn5822lw, and a5822slw are discontinued product for reference only 2 3 4 5 6 7 8 serial data out serial data in output enable logic supply strobe logic ground clock clk v st oe dd 1 sub power ground shift register latches 9 10 11 12 13 14 15 16 out 1 out 2 out 3 dwg. pp-026a out 8 out 7 out 6 out 5 out 4 bimos ii 8-bit serial-input, latched drivers always order by complete part number, e.g., ucn5821a . data sheet 26185.12f 5821 and 5822 note the dip package and the soic package are electrically identical and share common terminal number assignments. a merged combination of bipolar and mos technology gives these devices an interface flexibility beyond the reach of standard logic buffers and power driver arrays. the ucn5821a, ucn5821lw, UCN5822A, and ucn5822lw each have an eight-bit cmos shift register and cmos control circuitry, eight cmos data latches, and eight bipolar current-sinking darlington output drivers. the ucn5821a/lw and UCN5822A/lw are identical except for rated output voltage. bimos ii devices have much higher data-input rates than the original bimos circuits. with a 5 v logic supply, they will typically operate at better than 5 mhz. with a 12 v supply, significantly higher speeds are obtained. the cmos inputs are compatible with standard cmos and nmos logic levels. ttl circuits may require the use of appropriate pull-up resistors. by using the serial data output, the drivers can be cascaded for interface applications requiring additional drive lines. the ucn5821/22a are furnished in a standard 16-pin plastic dip; the ucn5821/22lw are in a 16-lead wide-body soic for surface-mount applications. the ucn5821a is also available for operation from -40 c to +85 c. to order, change the prefix from ucn to ucq. features to 3.3 mhz data input rate cmos, nmos, ttl compatible internal pull-down resistors low-power cmos logic & latches high-voltage current-sink outputs automotive capable absolute maximum ratings at 25 c free-air temperature output voltage, v out ucn5821a & ucn5821lw ..... 50 v UCN5822A & ucn5822lw ..... 80 v logic supply voltage, v dd ............. 15 v input voltage range, v in .................. -0.3 v to v dd + 0.3 v continuous output current, i out ..................................... 500 ma package power dissipation, p d package code ? .................. 2.1 w package code ?w ............... 1.5 w operating temperature range, t a ............................ -20 c to +85 c storage temperature range, t s .......................... -55 c to +150 c caution: cmos devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. www.allegromicro.com
5821 and 5822 8-bit serial-input, latched drivers 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 mos bipolar out 1 out 2 logic ground strobe output enable (active low) serial data out 5 7 6 dwg. fp-013a out 3 clock serial data in serial-parallel shift register latches v dd logic supply 1 2 3 16 out 6 out 7 out 8 15 14 11 10 9 out 4 out 5 13 12 8 4 power ground sub functional block diagram typical input circuits dwg. no. a-14,314 dwg. ep-010-3 in v dd dwg. ep-010-4a in v dd strobe & output enable clock & serial data in copyright ? 1985, 2004 allegro microsystems, inc. number of outputs on ucn5821a max. allowable duty cycle (i out = 200 ma at ambient temperature of v dd = 12 v) 25 c40 c50 c60 c70 c 8 90% 79% 72% 65% 57% 7 100% 90% 82% 74% 65% 6 100% 100% 96% 86% 76% 5 100% 100% 100% 100% 91% 4 100% 100% 100% 100% 100% 3 100% 100% 100% 100% 100% 2 100% 100% 100% 100% 100% 1 100% 100% 100% 100% 100% number of outputs on ucn5821lw max. allowable duty cycle (i out = 200 ma at ambient temperature of v dd = 12 v) 25 c40 c50 c60 c70 c 8 67% 59% 54% 49% 43% 7 77% 68% 62% 56% 49% 6 90% 79% 72% 65% 57% 5 100% 95% 86% 78% 68% 4 100% 100% 100% 98% 86% 3 100% 100% 100% 100% 100% 2 100% 100% 100% 100% 100% 1 100% 100% 100% 100% 100% typical output driver out sub 7.2k 3k note there is an indeterminate resistance between logic ground and power ground. for proper operation, these terminals must be externally connected together.
5821 and 5822 8-bit serial-input, latched drivers www.allegromicro.com limits characteristic symbol test conditions min. max. units output leakage i cex ucn5821a/lw, v out = 50 v 50 a current UCN5822A/lw, v out = 80 v 50 a ucn5821a/lw, v out = 50 v, t a = +70 c 100 a UCN5822A/lw, v out = 80 v, t a = +70 c 100 a collector-emitter v ce(sat) i out = 100 ma 1.1 v saturation voltage i out = 200 ma 1.3 v i out = 350 ma, v dd = 7.0 v 1.6 v input voltage v in(0) 0.8 v v in(1) v dd = 12 v 10.5 v v dd = 5.0 v 3.5 v input resistance r in v dd = 12 v 50 k ? v dd = 5.0 v 50 k ? supply current i dd(on) one driver on, v dd = 12 v 4.5 ma one driver on, v dd = 10 v 3.9 ma one driver on, v dd = 5.0 v 2.4 ma i dd(off) v dd = 5.0 v, all drivers off, all inputs = 0 v 1.6 ma v dd = 12 v, all drivers off, all inputs = 0 v 2.9 ma electrical characteristics at t a = +25 c, v dd = 5 v, (unless otherwise specified).
5821 and 5822 8-bit serial-input, latched drivers 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 timing conditions (v dd = 5.0 v, t a = +25 c, logic levels are v dd and ground) a. minimum data active time before clock pulse (data set-up time) ....................................................................... 75 ns b. minimum data active time after clock pulse (data hold time) ........................................................................... 75 ns c. minimum data pulse width .............................................................. 150 ns d. minimum clock pulse width ............................................................ 150 ns e. minimum time between clock activation and strobe ....................... 30 ns f. minimum strobe pulse width ........................................................... 100 ns g. typical time between strobe activation and output transition .......................................................................... 1.0 s truth table serial shift register contents serial latch contents output contents data clock data strobe output input input i 1 i 2 i 3 .............. i 8 output input i 1 i 2 i 3 .............. i 8 enable i 1 i 2 i 3 .............. i 8 hhr 1 r 2 .............. r 7 r 7 llr 1 r 2 .............. r 7 r 7 xr 1 r 2 r 3 .............. r 8 r 8 xxx..............x x l r 1 r 2 r 3 .............. r 8 p 1 p 2 p 3 .............. p 8 p 8 hp 1 p 2 p 3 .............. p 8 lp 1 p 2 p 3 .............. p 8 xxx.. ............ x h h h h .............. h l = low logic level h = high logic level x = irrelevant p = present state r = previous state dwg. no. a-12,627 serial data present at the input is transferred to the shift register on the logic 0 to logic 1 transition of the clock input pulse. on succeeding clock pulses, the registers shift data information towards the serial data output. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is transferred to its respective latch when the strobe is high (serial-to-parallel con- version). the latches will continue to accept new data as long as the strobe is held high. applications where the latches are bypassed (strobe tied high) will require that the enable input be high during serial data entry. when the enable input is high, all of the output buffers are disabled (off) without affecting the information stored in the latches or shift register. with the enable input low, the outputs are controlled by the state of the latches. a d b c e f clock data in strobe output enable out n g
5821 and 5822 8-bit serial-input, latched drivers www.allegromicro.com notes: 1. lead thickness is measured at seating plane or below. 2. lead spacing tolerance is non-cumulative. 3. exact body and lead configuration at vendors option within limits shown. 0.014 0.008 0.300 bsc dwg. ma-001-16a in 0.430 max 16 1 8 0.280 0.240 0.210 max 0.070 0.045 0.015 min 0.022 0.014 0.100 bsc 0.005 min 0.150 0.115 9 0.775 0.735 0.355 0.204 7.62 bsc dwg. ma-001-16a mm 10.92 max 16 1 8 7.11 6.10 5.33 max 1.77 1.15 0.39 min 0.558 0.356 2.54 bsc 0.13 min 3.81 2.93 9 19.68 18.67 ucn5821a and UCN5822A dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only)
5821 and 5822 8-bit serial-input, latched drivers 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 notes: 1. lead spacing tolerance is non-cumulative. 2. exact body and lead configuration at vendors option within limits shown. ucn5821lw and ucn5822lw dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions) 1 2 3 0.2992 0.2914 0.4133 0.3977 0.419 0.394 0.020 0.013 0.0926 0.1043 0.0040 min. 0.0125 0.0091 0.050 0.016 0 to 8 dwg. ma-008-16a in 0.050 bsc 16 9 9 16 1 2 3 7.60 7.40 10.50 10.10 10.65 10.00 0.51 0.33 2.65 2.35 0.10 min. 0.32 0.23 1.27 0.40 0 to 8 dwg. ma-008-16a mm 1.27 bsc
5821 and 5822 8-bit serial-input, latched drivers www.allegromicro.com the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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