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| ? maps an asynchronous 139.264 mbit/s tributary into an au-4/vc-4 sts-3c/spe. nibble or byte 139.264 mbit/s line interface - g.751 receive and transmit performance monitoring (frame alignment, distant alarm indication) sdh/sonet bus access - drop/add byte buses - optional drop bus au-4 pointer tracking with framing delay compensation sdh/sonet timing mode - drop bus timing - add bus timing - external timing with framing delay compensation microprocessor access - intel i/o with separate address/data buses - motorola i/o with separate address/data buses - motorola i/o with multiplexed bus - interrupt capability with individual mask bits poh byte processing enhanced desynchronizer access testing features - line loopback - sdh/sonet loopback -2 23 -1 test generator and analyzer boundary scan capability (ieee 1149.1) 144-pin plastic quad flat package the l4m device maps a 139.264 mbit/s asynchronous line signal into an au-4 vc-4/sts-3c spe signal. the sdh/sonet signal is transmitted via the add bus with timing derived from the drop bus, add bus, or external clock source. the l4m can compensate for up to a frame offset when using external timing and an external c1 pulse. an option is provided to generate toh bytes, such as the a1 and a2 framing bytes, a c1 byte, and the h1 and h2 pointer bytes only in drop bus and external timing modes. the vc-4/spe can be fixed to a known j1 reference when add bus timing is selected, or it can be positioned with a pointer value of 0 or 522 when drop bus or external timing is selected. in the drop direction, an optional pointer tracking machine is provided. in this mode, the l4m can compen- sate for up to a frame in offset. external access is pro- vided for the poh bytes, in addition to internal processing capability. serial access is provided for the overhead communications bits in the format. an alarm indication port is provided for ring configuration applica- tions. add/drop multiplexers digital cross-connect systems broadband switching systems transmission equipment l4m device level 4 mapper txc-03456 document number: txc-03456-mb ed. 1a, january 2000 poh i/o interface p control ?o?-bits indication add bus transmit clock in transmit nibble vcxo sdh/sonet side alarm interface line side scan boundary receive nibble drop bus port or byte data or byte data receive clock out receive clock in control level 4 mapper l4m txc-03456 u.s. patents no.: 4,967,405; 5,040,170; 5,265,096; 5,548,534 u.s. and/or foreign patents issued or pending copyright ? 2000 transwitch corporation transwitch and txc are registered trademarks of transwitch corporation data sheet applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
- 2 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 table of contents section page block diagram ................................................................................................................. ..................... 3 block diagram description ..................................................................................................... .............. 4 pin diagram ................................................................................................................... ....................... 7 pin descriptions .............................................................................................................. ...................... 8 absolute maximum ratings ...................................................................................................... .......... 19 thermal characteristics ....................................................................................................... ............... 19 power requirements ............................................................................................................ .............. 19 input, output and i/o parameters .............................................................................................. ......... 20 timing characteristics ........................................................................................................ ................ 22 operation ..................................................................................................................... .................. 40-61 internal device operation ..................................................................................................... ......... 40 external device operation ..................................................................................................... ........ 57 memory map .................................................................................................................... ................... 62 memory map descriptions ....................................................................................................... ........... 66 package information ........................................................................................................... ................ 89 ordering information .......................................................................................................... ................. 90 related products .............................................................................................................. .................. 90 standards documentation sources ............................................................................................... ..... 91 list of data sheet changes .................................................................................................... ........... 93 documentation update registration form* ................................................................................... 95 * please note that transwitch provides documentation for all of its products. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. list of figures figure page 1 l4m txc-03456 block diagram ....................................................................................... 3 2 l4m txc-03456 pin diagram .......................................................................................... 7 3 transmit line interface timing ....................................................................................... 22 4 receive line interface timing ........................................................................................ 23 5 add bus interface timing (add bus) .............................................................................. 24 6 add bus interface timing (external clock) ..................................................................... 25 7 add bus interface timing (drop bus clock and c1) ...................................................... 26 8 drop bus interface timing .............................................................................................. 27 9 transmit overhead comm channel timing ................................................................... 28 10 receive overhead comm channel timing .................................................................... 28 11 transmit path overhead interface timing ...................................................................... 29 12 receive path overhead interface timing ....................................................................... 30 13 transmit alarm indication port timing ........................................................................... 31 14 receive alarm indication port timing ............................................................................ 32 15 microprocessor timing read cycle - intel ...................................................................... 33 16 microprocessor timing write cycle - intel ...................................................................... 34 17 microprocessor timing read cycle - motorola .............................................................. 35 18 microprocessor timing write cycle - motorola ............................................................... 36 19 microprocessor timing read cycle multiplex bus - motorola ........................................ 37 20 microprocessor timing write cycle multiplex bus - motorola ........................................ 38 21 boundary scan timing .................................................................................................... 39 22 pointer interpretation state diagram .............................................................................. 41 23 test generator, analyzer and loopback......................................................................... 49 24 boundary scan schematic .............................................................................................. 52 25 phase-locked loop......................................................................................................... 57 26 l4m 140 mbit/s line interface ........................................................................................ 58 27 use of two l4m devices in ring configuration .............................................................. 60 28 l4m txc-03456 144-pin plastic quad flat package .................................................... 89 - 3 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 block diagram figure 1. l4m txc-03456 block diagram motorola p i/o intel d7 - d0 unused a7 - a0 sel rd wr rdy int moto madbus d7 - d0 unused a7 - a0 sel unused dtack irq desync block rxdn rxci rxco destuff block decode block pointer tracking ram alarm indication port overhead comm channel i/o pten dclk dc1j1 dspe ddn dpar drop block 8 sdh/sonet side line side highz block output block 8 desync signals receive ais detector receive frame alignment raipd taipd taipc taipf reset tochc tochd rochc rochd poh i/o rpohf rpohd rpohc tpohf tpohd tpohc add block ac1j1 ac1 aspe add adn apar dropt exc1 extc enabt aclk 8 block build block sync nib txc txdn exlos block input 8 stuff/ detector ais transmit alignment frame transmit ramci rd/wr motorola mad7 - mad0 as unused sel ds dtack irq rd/wr 8 8 dc1 note: n = 7 - 0 detector performance monitoring detector performance monitoring tck tdi tms boundary scan trs tdo (two buses) ( multiplex ed) 6 pohdis aisind alarms 5 - 4 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 block diagram description a simplified block diagram of the l4m device is shown in figure 1. a byte-wide or nibble-wide 139.264 mbit/s signal (txdn) is connected to the input block. the nibble interface is selected by placing a high on the lead designated as nib. data is clocked into the l4m on positive transitions of the clock signal txc. a control bit is provided which enables data to be clocked into the l4m on negative transitions of the clock. the l4m input block also terminates an external loss of signal (exlos ) indication. a low placed on this lead indicates that an external line interface device, such as a cmi interface device, has detected a loss of signal. this signal is reported as an alarm within the l4m for the microprocessor, and can generate an interrupt and a 140 mbit/s ais when enabled. the 140 mbit/s transmit line signal is monitored by the two transmit performance monitoring blocks for itu-t g.751 frame alignment and a distant alarm status. a distant alarm is defined as a 1 in bit 13 of the g.751 frame format. this alarm can generate an interrupt indication when enabled. when frame alignment is estab- lished, framing errors are counted in a 16-bit performance counter. the 140 mbit/s line signal is also monitored for an alarm indication signal (ais). the ais detection circuit can be enabled to work in conjunction with the frame alignment circuit. an ais condition is reported as an alarm, and can generate an interrupt when enabled. the stuff/sync block contains a fifo and is controlled by write timing from the input block, and by read timing from the build block. the fifo accommodates input and timing jitter as specified in itu-t recommendation g.823. the fifo is protected against overflow and underflow conditions by reporting a fifo error alarm, and will automatically recenter when a fifo underflow or overflow alarm has been detected. the reset is held for approximately one frame before the fifo is released for operation. upon power-up, or on applying a reset, the transmit fifo is also recentered. the stuffing algorithm uses one set of five control bits (c-bits) with one stuff opportunity bit (s-bit) per subframe (nine subframes) for frequency justification. the build block, with timing signals exchanged with the stuff/sync block, constructs the vc-4 format as illus- trated below. the l4m can build the 261 column by 9 row vc-4 format without or with path overhead bytes, and "o"-bits, depending on the features selected. the addition of poh bytes to the vc-4 format is disabled by applying a low to the pin designated pohdis (also applying a low to pohdis disables receive vc-4 poh processing). the starting position of the vc-4 j1 bytes can be synchronized to the add bus j1 pulse, when add bus timing is selected, or have a starting location of 0 or 522, when drop bus or the external timing modes are selected. the l4m can also generate an unequipped or supervisory unequipped vc-4. an unequipped vc-4 is defined as all zeros for the poh and payload bytes, while a supervisory unequipped vc-4 is defined as having valid poh bytes, but the payload bytes equal to zero. the build block is also responsible for multiplexing individual j1 p o h subframe 1 subframe 2 subframe 9 r: fixed stuff bits c: justification control bits s: justification opportunity bits o: overhead bits i: information bits 1 1 9 139.264 mbit/s build format 261 96i y poh 96i y 96i x 96i y 96i w 96i x 96i y 96i y 96i y 96i x 96i y 96i x 96i y 96i y 96i y 96i z 96i y 96i y 96i x 96i y w=iiiiiiii x = crrrrroo y = rrrrrrrr z=iiiiiisr - 5 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 poh bytes from the path overhead interface, or from ram locations written to by the microprocessor, into the add bus data stream. the rdi state and febe count may be provided from a mate l4m for path-protected ring configurations. the add block uses drop bus timing signals, add bus timing signals, or external timing signals for outputting the sdh/sts-3c data signal and parity to the add bus. a feature is also provided that generates the a1, a2, c1 and h1/h2 transport (sdh section) overhead bytes, depending upon the timing mode selected. the c1 byte value may be a fixed or a microprocessor-written value. the ss-bits in the transmitted pointer may be fixed or written by the microprocessor. unused transport overhead bytes can be selected to be three-stated or forced to zero. in the add bus timing mode, the clock and c1j1 signals are monitored for operation. in the external timing mode, an option is provided which can compensate up to a frame for the position of the c1 byte framing pulse (exc1). the add block interface for the add bus timing mode consists of an input clock (aclk), input c1 and j1 indica- tor (ac1j1), a separate c1 input (ac1) when enabled, an input spe indicator (aspe), output byte data (ad7- ad0), output parity indication (apar), and an output add data to bus indicator (add ). when the l4m is config- ured to operate in the external timing mode, the add bus signals consist of: external reference input clock (extc) and framing signal (exc1) (optional), an output clock (aclk), output c1 and j1 indicator (ac1j1), an output spe indicator (aspe), output byte data (ad7-ad0), output parity indication (apar), and an output add data to bus indicator (add ). when the l4m is configured to operate in the drop bus timing mode, the add bus signals consist of: an output clock (aclk), output c1 and j1 indicator (ac1j1), an output spe indicator (aspe), output byte data (ad7-ad0), output parity indication (apar), and an output add data to bus indicator (add ). odd parity may be calculated over all add bus signals (except the add indicator), or data only. the drop block terminates the drop bus signals. the drop bus signals consists of an input clock (dclk), input c1 and j1 indicator (dc1j1), an input spe indicator (dspe), input byte data (dd7-dd0), input parity indica- tion (dpar), and an optional framing pulse (dc1). when the pointer tracking machine feature is enabled, the j1 signal in the c1j1 signal must not be present. odd parity may be checked over all of the drop bus signals, or for the data byte only. when the pointer tracking machine is enabled, the relative position of c1 can be com- pensated up to one frame. the pointer tracking block is enabled by placing a high on the lead designated as pten. the pointer tracking machine meets the pointer tracking requirements specified in etsi 1015. the pointer tracking block deter- mines the starting location of the j1 byte in the vc-4 format. the s-bit transition check in the h1 pointer byte may be disabled in the pointer tracking block. when enabled, the s-bit check can be a fixed value or a value written by the microprocessor. in addition, the ais to lop transition can be disabled to have the pointer track- ing state machine conform to bellcore standards. the pointer tracking block monitors the pointer bytes for a path ais and lop alarm. positive, negative and ndf occurrences are counted in 8-bit performance counters. having established the starting location of the vc-4, the decode block performs path overhead byte process- ing. the poh bytes are written into ram locations for a microprocessor read cycle in addition to being pro- vided at a poh interface for external access. capability is also provided in the l4m for performing the path trace message comparison for the j1 byte. b3 bip-8 parity errors and the input febe count in the g1 byte are counted as bit or block errors. the status of the rdi bit is also checked, and an alarm indication provided. the febe count is also provided, along with an rdi indication (as a result of local alarms) to an alarm indication port for path-protected ring operation. a bit stuffing ais feature is also provided in addition to using an external ais clock to generate line ais as a result of receive alarms. the desynchronizer block is based on a proprietary transwitch design. the desynchronizer block removes the effect on the output signal of systemic jitter due to signal mapping and pointer movements, and consists of two fifos. the fifos are monitored for overflow and underflow alarms, and reset automatically when an alarm is detected. a 15-bit pointer leak register is provided for a microprocessor-written value. the following six desynchronizer signals are provided: positive and negative phase detector outputs (ctrl and ctrl ), a stuff indicator (stuff) that provides the status of the stuff (justification) on a per-subframe basis, positive and neg- ative justification indicator bits (pj and nj), and a pointer leak counter equal to zero indication (pleq0). in - 6 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 addition, the desynchronizer pointer offset counter (9 bits plus sign value) is provided in the memory map for a microprocessor read, if required. the output of the desynchronizer block is connected to the l4m output block, receive frame alignment detector block and receive ais detector block. the 140 mbit/s receive line signal is monitored by the receive frame alignment detector block for itu-t g.751 frame alignment and the distant alarm status. a distant alarm is defined as a 1 in bit 13 of the g.751 frame format. this alarm can generate an interrupt indication when enabled. when frame alignment is established, framing errors are counted in a 16-bit performance counter. the 140 mbit/s line signal is also monitored for an alarm indication signal (ais). the ais detection circuit can be enabled to work in conjunction with the frame alignment circuit. an ais condition is reported as an alarm, and can generate an interrupt when enabled. the receive frame alignment detector and receive ais detec- tor blocks are disabled when the bit stuffing approach for generating 140 mbit/s ais is enabled and when the l4m generates a receive line ais. ais using a bit stuffing approach is implemented in the decode block prior to the desynchronizer block. a byte-wide or nibble-wide 139.264 mbit/s signal (rxdn) is provided as an output from the output block. a nib- ble interface is selected by placing a high on the lead designated as nib. data is normally clocked out of the l4m on negative transitions of the clock signal rxco. a control bit is provided which enables data to be clocked out of the l4m on positive transitions of the clock. external access to the path overhead bytes is provided by the poh i/o block. the nine receive poh bytes present in the serial data channel (rpohd) are clocked out on negative transitions of the gapped clock (rpohc). a framing pulse (rpohf), one clock cycle wide, identifies the starting location of the poh bytes, with bit 1 in the j1 byte. in the transmit direction, a gapped clock (tpohc), and framing pulse (tpohf) are provided. serial data containing the poh bytes is clocked into the l4m on positive transitions of the clock. the b3 byte is present in the serial bit stream, but it is ignored by the l4m, and is recalculated. the framing pulse is one clock cycle wide and identifies the starting location of the poh bytes, with bit 1 in the j1 byte. an external ais input is provided for generating a received 140 mbit/s ais and an rdi indication, if the poh bytes are processed externally. the overhead communications channel i/o block provides an asynchronous interface for the 90 "o"-bits found in the sdh/sonet format. serial data (rochd) which contains the "o"-bits, is clocked out of the l4m on negative transitions of the gapped clock (rochc). the received "o"-bits are not synchronized with the starting location of the frame. in the transmit direction, the "o"-bits (tochd) are clocked into the l4m by the gapped output clock (tochc). the alarm indication port data output signal (raipd), consisting of the febe count and rdi indication, is clocked out of the l4m on negative transitions of the receive poh clock (rpohc). the serial data consists of nine bytes each frame. the first four bits correspond to the febe count, which has been derived from the b3 bip-8 parity check. the next bit, bit 5, corresponds to the rdi indication. bits 6 and 7 are set to 0, while bit 8 is set to a 1. the received poh framing pulse (rpohf) identifies the starting location of bit 1 in the first byte. in the transmit direction, the received serial data, framing pulse, and clock from the mate l4m become the data input (taipd), framing pulse input (taipf), and clock input (taipc). when the ring mode is selected, the mate l4m febe count and rdi indication are transmitted in the g1 byte. an upstream ais indication may be inputted into the l4m using the e1 byte in the transport (section) over- head bytes, or the external istat, pais, and stai pins. the upstream ais indication can generate a 140 mbit/s ais, and a transmit rdi indication. the l4m supports three types of microprocessor interfaces: intel microprocessor with separate address and data buses, motorola microprocessor with separate address and data buses, and a motorola microprocessor with a multiplexed address/data bus interface. the boundary scan block provides a mechanism for external access to the input and output pins of the device, so that they may be observed and tested. the structure and operation of this block are described in the opera- tion section. - 7 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 pin diagram figure 2. l4m txc-03456 pin diagram (top view) l4m 2 4 10 12 20 22 30 34 112 100 94 90 86 80 74 140 136 130 128 120 114 110 40 46 50 56 60 66 70 enabt stuff ad1 tochc test ad0 txd3 txd4 a2 aisck pa i s stai reset vdd a3 gnd moto gnd ad4 vdd ad6 exc1 gnd d0/mad0 rxd3 rxd7 rxd6 rxd5 d1/mad1 rxd4 ad2 tms ad7 add vdd apar ac1 aclk aspe ac1j1 gnd extc dc1 dc1j1 dpar dspe vdd test dclk dd0 rpohc rxd2 d2/mad2 wr /ds a4 ta i p c test dd2 pten dropt gnd nj rxci vdd rxco aisind rxd0 rxd1 txd5 pohdis trs pj ctrl ctrl exais gnd highz vdd rpohf rpohd raipd rochd rochc gnd d6/mad6 test pleq0 a1 vdd dd7 dd6 dd5 dd4 dd3 dd1 gnd ta i p f tochd ta i p d tpohd vdd tpohc tpohf test tdo test gnd txc exlos txd7 txd6 vdd txd2 txd1 txd0 gnd nib a6 vdd a7 a5 a0 madbus as vdd rd ,rd/wr sel gnd ramci d3/mad3 d4/mad4 vdd d5/mad5 d7/mad7 int/irq rdy/dtack gnd istat 6 8 14 16 18 24 28 26 32 38 36 42 44 48 54 52 58 64 62 68 72 78 82 76 84 88 92 98 96 102 104 106 108 118 116 122 124 126 132 134 138 142 144 tdi test tck gnd ad3 ad5 txc-03456 pin diagram - 8 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 pin descriptions power supply and ground *note: i = input; o = output; p = power 140 mbit/s line interface symbol pin no. i/o/p* type name/function vdd 10, 22, 34, 46, 58, 70, 82, 94, 106, 118, 130, 142 p vdd: +5 volt supply voltage, 5% gnd 4, 16, 28, 40, 52, 54, 64, 76, 88, 100, 112, 124, 136 p ground: 0 volt reference. symbol pin no. i/o/p type* name/function txc 87 i ttl transmit 140 mbit/s line clock: the clock rate is 34.816 mhz (nibble rate), or 17.408 mhz (byte rate). byte or nibble-wide line data is clocked into the l4m on positive transitions of this clock when control bit tinvc is a 0 . data is clocked in on negative transitions of this clock when control bit tinvc is a 1. txdn (n=7-0) 84, 83, 81-77, 75 i ttl transmit 140 mbit/s line data: txd7 (pin 84) is defined as the msb for the byte interface, and is the first bit transmitted. for the nibble interface, txd3 (pin 79) is defined as the msb. txd0 (pin 75) is the lsb for both the byte and nibble interfaces. exlos 85 i ttlp external 140 mbit/s loss of signal: an optional low input sig- nal to report an external transmit 140 mbit/s line loss of signal. if this lead is not used it must be connected to vdd. rxdn (n=7-0) 33-29 27-25 o ttl4ma receive 140 mbit/s line data: rxd7 (pin 33) is defined as the msb for the byte interface, and is the first bit received. for the nibble interface, rxd3 (pin 29) is defined as the msb. rxd0 (pin 25) is the lsb for both the byte and nibble interfaces. rxco 23 o ttl4ma receive 140 mbit/s line output clock: the clock rate is 34.816 mhz (nibble rate), or 17.408 mhz (byte rate). byte or nibble-wide line data is clocked out of the l4m on negative tran- sitions of this clock when control bit rinvc is a 0 . data is clocked out on positive transitions of this clock when control bit rinvc is a 1. this clock is derived from the receive line input clock (rxci). rxci 21 i ttl receive 140 mbit/s line input clock: byte (17.408 mhz) or nibble (34.816 mhz) clock used by the internal desynchronizer for sourcing data. this clock is used to derive the receive line output clock (rxco). nib 74 i ttl nibble/byte data selection: common control lead for both the transmit and receive 140 mbit/s interfaces. a high selects the interfaces as nibble, while a low selects the interfaces as byte. *note: see input, output and i/o parameters section for type definitions. - 9 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 sdh/sonet drop bus interface symbol pin no. i/o/p type name/function dclk 131 i ttl drop bus clock: byte-wide data (dd7-dd0), parity (dpar), payload indicator (dspe), and the c1 and j1 pulses (dc1j1) are clocked into the l4m on negative transitions of this clock, which has a rate of 19.44 mhz. the clock signal is used for receive timing, and is monitored for loss of clock. dpar 128 i ttl drop bus parity bit: this input represents an odd parity cal- culation for each data byte, the dspe signal, and the dc1j1 signal. when the internal pointer tracking feature is enabled, parity is calculated for data and the c1 pulse only. when a 1 is written to control bit pardo, parity is calculated for the data byte only. dc1j1 127 i ttl drop bus c1j1 indicator: the c1 pulse is an active high, one clock cycle wide timing pulse, that indicates the starting location of the first c1 byte time slot in the stm-1 or sts-3c frame when dspe is low. when the pointer tracking feature is disabled, a j1 pulse, also one clock cycle wide, must be present to identify the starting location of the j1 byte in the au-4 vc-4, or in the sts-3c spe signal when dspe is high. if the j1 pulse is not present, the pointer tracking feature must be enabled. the c1 pulse must be provided on this signal lead, or on the dc1 signal lead. up to a frame in offset delay for the c1 byte can be compensated for when the pointer tracking mode is enabled . the receive offset delay is con- trolled by bit rc1dc in the memory map. dspe 129 i ttl drop bus spe indicator: a signal that is active high during the au-4/sts-3c spe time when the pointer tracking feature is disabled. this signal is not required when the pointer tracking feature is enabled. ddn (n=7-0) 141-137 135-133 i ttl drop bus byte: byte-wide data that corresponds to the au-4/ sts-3c signal from the drop bus. the first bit dropped corre- sponds to dd7 (pin 141). dc1 126 i ttl drop bus c1 pulse: an external positive c1 pulse that may be provided on this pin instead of in the dc1j1 signal. this signal is or-gated internally with the dc1j1 signal to form a composite c1j1. when this signal lead is not used, it must be grounded. - 10 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 sdh/sonet add bus interface symbol pin no. i/o/p type name/function aclk 121 i/o ttl4ma add bus clock: the add clock is used for build timing, trans- mit fifo, and for sourcing the add bus byte-wide data (ad7- ad0) and parity (apar), when add bus timing is selected. when external timing or drop timing mode is selected, this sig- nal becomes an output. the add bus clock rate is 19.44 mhz. ac1j1 123 i/o ttl4ma add bus c1j1 indicator: the c1 pulse is an active high, one clock cycle wide, timing pulse that identifies the starting loca- tion of the first c1 byte time slot in the stm-1 or sts-3c frame. the c1 pulse may be provided on a separate lead (ac1) when the add bus timing mode is selected. a j1 pulse, also one clock cycle wide, identifies the starting location of the j1 byte in the au-4 vc-4 or sts-3c spe signal when the poh bytes are used. when the poh feature is disabled, the j1 pulse is not required. when external timing or drop timing is enabled this signal becomes an output. the c1j1 pulses correspond to the c1 and j1 bytes present on ad(7-0). when a 1 is written to control bit ac1en, the c1 pulse may be provided on a sepa- rate lead (ac1) instead of in the ac1j1 signal. apar 119 o ttl4ma add bus parity bit: this output bit represents the odd parity calculation for each data byte (and spe and c1j1, including ac1, when they are outputs). when a 1 is written to control bit pardo, parity is calculated for the data byte only. apar is not calculated over the unused toh byte times. aspe 122 i/o ttl4ma add bus spe indicator: an input signal in add timing mode that is high during the au-4/sts-3c spe time. when the exter- nal timing or drop timing modes are enabled, this signal becomes an output. adn (n=7-0) 116-113 111-108 ottl4ma add data byte: byte-wide data that corresponds to the au-4/ sts-3c signal to be placed on the add bus. the first bit trans- mitted corresponds to ad7 (pin 116). data is three-stated dur- ing periods of no activity (e.g., during unused toh times). add 117 o ttl4ma add indicator: an active low signal that identifies the time slots corresponding to the output data (ad7-ad0). ac1 120 i/o ttl4ma add bus c1 pulse: this lead provides the c1 pulse as an output when the drop bus timing or external timing modes are enabled, and when the ac1en control signal is a 1. the ac1j1 signal will contain the c1 pulse. when the add bus tim- ing mode is enabled, this lead may be used as the c1 input, independent of the ac1en control bit. this signal is or-gated internally with the ac1j1 signal in the add bus timing mode to form a composite c1j1signal. if this signal lead is not used in the add bus timing mode, it must be grounded. - 11 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 receive and transmit path overhead byte interface symbol pin no. i/o/p type name/function rpohf 9 o ttl4ma receive path overhead framing: a positive, one clock cycle wide, framing pulse that is synchronous with bit 1 in the j1 byte in the poh interface data. rpohd 8 o ttl4ma receive path overhead data: the serial output for the nine path overhead bytes: j1, b3, c2, g1, f2, h4, z3, z4, and z5 bytes. the bytes are clocked out, starting with bit 1 in j1, on negative transitions of the clock signal (rpohc) when the poh feature is enabled. rpohc 11 o ttl4ma receive path overhead clock: the nine poh bytes and raipd data are clocked out on negative transitions of this clock signal (rpohc). tpohf 92 o ttl4ma transmit path overhead framing: a positive, one clock cycle wide, framing pulse that is synchronous with bit 1 in the j1 byte in the poh interface data. tpohd 95 i ttl transmit path overhead data: a serial input for the path overhead bytes: j1, c2, g1, f2, h4, z3, z4, and z5 bytes. the b3 byte time slot must be provided, but the contents are ignored by the l4m. the bytes are clocked in, starting with bit 1 in j1, on positive transitions of the clock signal (tpohc). 8 bits are clocked in during the b3 byte time, but they are ignored by the l4m device. the l4m recalculates the b3 byte parity value. the poh bytes are ignored when a low is placed on the pohdis lead (pin 19). tpohc 93 o ttl transmit path overhead clock: the transmit clock used for clocking in the path overhead bytes. data is clocked in on positive transitions of the clock. - 12 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 receive and transmit overhead comm channel interface external timing for add bus symbol pin no. i/o/p type name/function tochc 107 o ttl4ma transmit overhead comm channel clock: an output clock provided for sourcing the transmit overhead communications channel data ("o"-bits). this clock has an effective data trans- fer rate of 720 khz (8 khz per bit, times 90 bits). tochd 97 i ttl transmit overhead comm channel data: data is clocked in on positive transitions of the clock signal (tochc). the data is unaligned in relationship to the overhead communications channel data bit placement in the sdh/sonet format. rochc 5 o ttl4ma receive overhead comm channel clock: a clock provided for outputting the transmit overhead communications channel data. this clock has an effective data transfer rate of 720 khz (8 khz per bit, times 90 bits). rochd 6 o ttl4ma receive overhead comm channel data: data is clocked out on negative transitions of the clock signal (rochc). the data output for the overhead communications channel from the format is unaligned in relationship with the sdh/sonet frame. symbol pin no. i/o/p type name/function extc 125 i ttl external clock input: enabled by placing a high on the enabt lead (pin 36). used for deriving output timing for the add bus. a clock rate of 19.44 mhz is required for au-4/ sts-3c operation. this clock input is monitored for loss of clock. exc1 105 i ttl external c1 input: enabled by placing a high on the enabt lead (pin 36). an optional c1 input signal that can be used for frame alignment. in addition, an option is provided for the pointer tracking feature which can compensate up to a frame in offset delay. if this pin is not used, it should be grounded. - 13 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 receive desynchronizer symbol pin no. i/o/p type name/function ctrl 14 o cmos4ma phase detector output positive: normally connected to low pass filter as part of the desynchronizer phase-locked loop. see figure 25. ctrl 15 o cmos4ma phase detector output negative: normally connected to low pass filter as part of the desynchronizer phase-locked loop. see figure 25. stuff 72 o ttl4ma stuff (justification) opportunity indication: this lead pro- vides a status of the stuff (justification) s-bit in the z byte for each row in the nine subframes in the 140 mbit/s sdh/sonet format. the pin is high for one sonet/sdh row when there is a stuff indication, and low when this bit is information. the out- put on this pin is updated each row based on majority voting of the five c-bits. pj 13 o ttl4ma positive justification indication: this lead provides a posi- tive pulse when a positive pointer movement is detected. the pulse width is one dclk cycle wide. nj 20 o ttl4ma negative justification indication: this lead provides a posi- tive pulse when a negative pointer movement is detected. the pulse width is one dclk cycle wide. pleq0 143 o ttl4ma pointer leak counter equal to zero indication: this lead provides a positive indication when the internal pointer leak counter is equal to zero. this signal is reset to zero when the internal counter is preset. a positive pulse, one dclk cycle wide, is then output for each time a bit is leaked out of the l4m ? s desynchronizer. the last bit leaked out is represented by the last rising edge of the pleq0 signal lead. - 14 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 receive and transmit alarm indication port boundary scan symbol pin no. i/o/p type name/function raipd 7 o ttl4ma receive alarm indication port data: a serial output that pro- vides the four-bit febe count (received b3 bip-8 parity errors, bits 1-4), and path rdi alarm indication (bit 5) for ring opera- tion. bits 6, 7, and 8 are set to 0, 0, 1, respectively. this lead is normally connected to the taipd lead at the mate 140 mbit/s mapper for ring operation. the rpohc signal is used to clock out this signal. the rpohf signal is used to provide the frame reference signal. the data output is disabled (forced to 0) when an active low is placed on the pohdis lead. taipd 96 i ttl transmit alarm indication port data: this serial input lead is normally connected to the raipd lead at the mate l4m for ring operation. provides an input for the four-bit febe count (received b3 bip-8 parity errors), and path rdi alarm indication from the mate l4m. the data input is disabled when an active low is placed on the pohdis lead. taipc 99 i ttl transmit alarm indication port clock: this clock input is nor- mally connected to the rpohc clock lead at the mate l4m for ring operation. transmit alarm data (taipd) is clocked into the l4m on positive transitions of the clock. this clock input is mon- itored for loss of clock. taipf 98 i ttl transmit alarm indication port framing pulse: normally connected to rpohf lead at the mate l4m for ring operation. used to indicate the start of the external alarm indications for ring operation. symbol pin no. i/o/p type name/function tck 101 i ttl test boundary scan clock: the input clock for boundary scan testing. the tdi and tms states are clocked in on positive transitions. tdi 103 i ttlp test boundary data input: serial data input for boundary scan test messages. tdo 90 o 3-state ttl4ma test boundary data output: serial data output whose infor- mation is clocked out on negative transitions of tck. this pin requires a 4.7 k ? pull-up resistor if it is used. tms 102 i ttlp test boundary mode select: the signal present on this lead is used to control test operations. trs 12 i ttlp test boundary scan reset: an active low asynchronous reset signal. this lead should be held low if the boundary scan is not being used. - 15 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 other pins symbol pin no. i/o/p type name/function enabt 36 i ttl enable add bus timing: works in conjunction with the dropt lead. the following table is the definition of the timing modes: enabt dropt action 1 x external timing. add bus timing derived from the external clock (extc) and the external framing pulse (exc1). the aspe, ac1j1, aclk and ac1 signal leads become output leads. 0 0 add bus timing. data derived from the add bus clock, aspe, and ac1j1 input signals. note: aspe, ac1j1, ac1 and aclk are inputs. 0 1 drop bus timing. data, aspe, ac1j1, and aclk output signals are derived from the drop bus clock (dclk) and c1 pulse in the drop bus dc1j1 signal. dropt 35 i ttl drop timing mode enabled: works in conjunction with the enabt lead. see table above. istat 37 i ttl external sts alarm indication: the purpose of this lead is to provide an upstream ais indication for the l4m. this pin is enabled by writing a 1 to the eape control bit. a high on this lead generates ais, and path rdi, when enabled. pa i s 3 8 i t t l external path ais indication: the purpose of this lead is to provide an upstream ais indication for the l4m. this pin is enabled by writing a 1 to the eape control bit. a high generates line ais, and path rdi, when enabled. stai 39 i ttl sts network alarm indication: this pin is enabled by writing a 1 to the xrdien control bit. a high generates a path rdi, when enabled. aisck 71 i cmos ais clock input: enabled when control bit bsaise is a 0. this clock is used to generate transmit and receive 140 mbit/s ais on defined alarms. the clock frequency must be 34.816 mhz +/- 15 ppm for a nibble interface, and 17.408 mhz +/- 15 ppm for a byte interface. if ais bit stuffing is used to generate ais (control bit bsaise is written with a 0), this clock is not required. exais 17 i ttlp external ais alarm input: a low causes a receive 140 mbit/s ais when enabled, and a path rdi to be generated. may be used when processing received poh bytes via external cir- cuitry (e.g., c2 byte). - 16 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 microprocessor interface pohdis 19 i ttlp path overhead byte processing disabled: a low disables the insertion of the poh bytes (they are tri-stated) into the spe from either the memory map ram or the poh interface. it also disables the processing of the poh bytes in the receive direc- tion and their subsequent actions. aisind 24 o ttl receive ais indication output: a low indicates that 140 mbit/s ais is being generated in the receive path. this pin is disabled when the bsaise control bit=1 and the rlaisd alarm=1. however, when the l4m generates a receive line ais, this pin will go low even if bsaise=1 and rlaisd=1. highz 18 i ttlp high impedance enable: a low causes all output and bi-directional pins to three-state for test purposes. pten 2 i ttl pointer tracking enable: a high enables the internal pointer tracking feature. the pointer tracking feature determines the starting location of j1 in the dropped signal. the c1 pulse must be provided as the dc1, or dc1j1 signal. the j1 pulse must not be provided. the dspe lead is ignored when the pointer tracking machine feature is enabled. a low requires the dc1j1 and dspe signals to be provided as inputs. reset 1 i ttlp hardware reset: a low clears all performance counters, and presets the internal fifos and counters. all control bits (10h- 1fh) are preset to 0 except for bit 3 of register 13h and bit 0 of registers 1ah and 1bh. these 3 bits are preset to 1. this pulse must be present for a minimum of 200 nanoseconds. note: the l4m requires approximately 1 microsecond upon power-up for stabilization before a low can be applied to this pin. symbol pin no. i/o/p type name/function a(7-0) 69-65 63-61 ittl address bus (motorola/intel buses): these are address line inputs that are used for accessing a ram location for a read/ write cycle. a0 is the least significant bit. high is logic 1. as 59 i ttl address select (multiplex bus): a low is used for address select when the multiplex bus mode is selected. d(7-0) mad(7-0) 49-47 45-41 i/o ttl8ma data bus: bi-directional data lines used for transferring data. d0 is the least significant bit. can also be used as multiplexed address and data bus with motorola interface. high is logic 1. sel 55 i ttlp select: a low will enable data transfers between the processor and the l4m ram during a read/write cycle. rd rd/wr 56 i ttl read (intel mode) or read/write (motorola mode): intel mode - an active low signal generated by the microproces- sor for reading the l4m ram locations. motorola and multiplex mode - an active high signal generated by the microprocessor for reading the l4m ram locations. an active low signal is used to write to l4m ram locations. symbol pin no. i/o/p type name/function - 17 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 wr ds 57 i ttl write (intel mode): intel mode - an active low signal generated by the microproces- sor for writing to the mapper ram locations. motorola mode - not used. for the multiplex mode, this lead is used for the data select control. rdy/ dtack 51 o ttl8ma 3-state ready (intel mode) or data transfer acknowledge (motorola modes): this lead is three-stated. intel mode - a high is an acknowledgment from the addressed ram location that the transfer can be completed. a low indi- cates that the l4m cannot complete the transfer cycle, and microprocessor wait states must be generated. motorola and multiplex mode - during a read bus cycle, a low signal indicates that the information on the data bus is valid. during a write bus cycle, a low signal acknowledges the accep- tance of data. int/ irq 50 o ttl4ma interrupt: intel mode - a high on this output pin signals an interrupt request to the microprocessor. motorola mode - a low on this output pin signals an interrupt request to the microprocessor. moto 73 i ttl motorola/intel microprocessor select: this lead works in conjunction with the madbus lead. a high selects a motorola microprocessor compatible bus interface. a low selects the intel microprocessor compatible bus interface. the following table summarizes the microprocessor selection. moto madbus action 0 x intel microprocessor interface, separate address/data buses. 1 0 motorola microprocessor interface, sepa- rate address/data buses. 1 1 motorola microprocessor interface, multi- plexed address/data buses. madbus 60 i ttl multiplexed address/data bus: when the moto lead is high, a high on this lead selects a multiplexed address/data bus interface, while a low selects separate address/data buses. this lead is disabled when moto is low. ramci 53 i cmos ram clock input: asynchronous clock input used for the inter- nal l4m ram operation. this clock must be connected to the microprocessor clock that has an operating rate of between 12 and 25 mhz with a duty cycle of 50 10%. this clock is also used as an internal time base for the loss of signal detectors. symbol pin no. i/o/p type name/function - 18 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 manufacture test pins symbol pin no. i/o/p type name/function test 144 i ttlp test pin for manufacture testing: for normal operation this pin must be grounded. test 89 i ttlp test pin for manufacture testing. for normal operation this pin must be grounded. test 91 o ttl4ma test pin for manufacture testing: for normal operation this pin must be left unconnected. test 104 i ttlp test pin for manufacture testing: for normal operation this pin must be grounded. test 86 i ttlp test pin for manufacture testing: for normal operation this pin must be grounded. test 132 i ttlp test pin for manufacture testing: for normal operation this pin must be grounded. test 3 i ttlp test pin for manufacture testing: for normal operation this pin must be grounded. - 19 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 absolute maximum ratings *note: operating conditions exceeding those listed in absolute maximum ratings may cause permanent failure. exposure to absolute maximum ratings for extended periods may impair device reliability. thermal characteristics power requirements parameter symbol min* max* unit supply voltage v dd -0.3 +7.0 v dc input voltage v in -0.5 v dd + 0.5 v ambient operating temperature t a -40 85 o c storage temperature range t s -55 150 o c parameter min typ max unit test conditions thermal resistance - junction to ambient 23.0 o c/w parameter min typ max unit test conditions v dd 4.75 5.00 5.25 v i dd 251 320 ma p dd 1.27 1.68 w inputs switching - 20 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 input, output and i/o parameters input parameters for cmos input parameters for ttl input parameters for ttlp note: input has a 9k (nominal) internal pull-up resistor. output parameters for cmos4ma parameter min typ max unit test conditions v ih 3.15 v 4.75 < v dd < 5.25 v il 1.65 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 3.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 3.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 0.5 1.4 ma v dd = 5.25; input = 0 volts input capacitance 3.5 pf parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 2.5 5.5 9.9 ns c load = 15pf t fa l l 2.0 3.9 8.0 ns c load = 15pf - 21 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 output parameters for ttl4ma input/output parameters for ttl8ma parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -2.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -2.0 ma t rise 2.5 5.5 10.0 ns c load = 15pf t fa l l 1.0 2.0 4.0 ns c load = 15pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 ma v dd = 5.25 input capacitance 3.5 pf v oh v dd - 0.5 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -4.0 ma t rise 1.9 4.5 8.0 ns c load = 25pf t fa l l 0.8 1.5 3.1 ns c load = 25pf - 22 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 timing characteristics detailed timing diagrams for the l4m device are illustrated in figures 3 through 21, with values of the timing parameters following each figure. all output times are measured with a maximum 75 pf load capacitance. tim- ing parameters are measured at (v oh + v ol )/2 or (v ih + v il )/2 as applicable. please note that all of the timing parameters in this document are subject to change contingent on the results of characterization. figure 3. transmit line interface timing * nibble interface: 28.7224 ns, byte interface: 57.4449 ns. parameter symbol min typ max unit txc clock period t cyc *ns txc duty cycle, t pwh /t cyc 40 60 % data input set up time for txc t su 5.0 ns data input hold time after txc t h 10.0 ns txc txd(8-0) t su note: shown for tinvc equal to 0. data is clocked in on negative transitions when control bit tinvc is equal to 1. t h t pwh t cyc (input) (input) - 23 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 4. receive line interface timing * nibble interface: 28.7224 ns, byte interface: 57.4449 ns. parameter symbol min typ max unit rxci clock period t cyc *ns rxci duty cycle t pwh /t cyc 40 60 % rxco delay after rxci t d(1) 23.0 ns data output delay after rxco t d(2) -2.0 9.5 ns rxci rxco t d(1) t pwl t cyc (output) (input) rxd(7-0) (output) t pwh note: shown for rinvc equal to 0. data is clocked out on positive transitions when control bit rinvc is equal to 1. t d(2) - 24 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 5. add bus interface timing (add bus) parameter symbol min typ max unit add clock period t cyc 51.44 ns add clock duty cycle, t pwh /t cyc 40 50 60 % ac1j1 set-up time to aclk t su(1) 3.0 ns ac1j1 hold time after aclk t h(1) 7.0 ns aspe set-up time to aclk t su(2) 10.0 ns aspe hold time after aclk t h(2) 5.0 ns add low output delay from aclk t d(1) 7.5 33.0 ns data output delay from aclk t d(2) 7.0 28.0 ns apar output delay from aclk t d(3) (not shown) 10.0 37.0 ns aclk aspe t d(1) t h(1) (input) (input) ac1j1 (input) note: the relationship between j1 and the spe signals is shown for illustration purposes only, and will be a function of the pointer offset. the apar signal is not shown. ad7-ad0 (output) add (output) t su(1) c1(1) data data data j1 or stuff data data j1 t d(2) t su(2) t h(2) t pwh t cyc - 25 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 6. add bus interface timing (external clock) parameter symbol min typ max unit external clock period t cyc 51.44 ns duty cycle, t pwh /t cyc 40 50 60 % set up time for exc1 for extc t su 4.0 ns hold time for exc1 after extc t h 7.0 ns delay aclk from extc t d(1) 12.0 28.0 ns delay aspe from aclk t d(2) -6.0 6.0 ns delay ac1j1 from aclk t d(3) -6.0 6.0 ns delay, data from aclk t d(4) -6.0 6.0 ns delay, add from aclk t d(5) -6.0 6.0 ns delay, apar from aclk t d(6) (not shown) -6.0 11 ns add (output) exc1 (input) data c1 t su note: shown for the tohout control bit equal to 1 and the relationship to an optional external c1 pulse. the apar signal is not shown. ac1j1 (output) aspe (output) aclk (output) extc (input) j1 c1(1) a2(3) a2(2) a2(1) a1(3) a1(2) c1 j1 t h t d(4) t d(3) t d(2) t d(1) t pwl t pwh t cyc ad7-ad0 (output) t d(5) - 26 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 7. add bus interface timing (drop bus clock and c1) parameter symbol min typ max unit drop clock period t cyc 51.44 ns duty cycle, t pwh /t cyc 40 50 60 % set-up time for dc1j1 to dclk t su 3.0 ns hold time for dc1j1 after dclk t h 7.0 ns delay aclk from dclk t d(1) 12.0 28.0 ns delay aspe from aclk t d(2) -6.0 6.0 ns delay ac1j1 from aclk t d(3) -6.0 6.0 ns delay, data from aclk t d(4) -6.0 6.0 ns delay, add from aclk t d(5) -6.0 6.0 ns delay, apar from aclk t d(6) (not shown) -6.0 11 ns ad7-ad0 (output) add (output) note: the c1 and j1 pulses must be present in the dc1j1 signal if the pointer tracking state machine is turned off. the add bus j1 pulse is shown for the svc4h control bit set to 0. the apar signal is not shown. ac1j1 (output) aspe (output) aclk (output) dc1j1 (input) dclk (input) j1 c1 t d(1) t pwl t cyc data data data data data t h t su c1 j1 j1 t pwh t d(2) t d(3) t d(4) t d(5) - 27 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 8. drop bus interface timing parameter symbol min typ max unit drop clock period t cyc 51.44 ns duty cycle, t pwh /t cyc 40 50 60 % data set up time for dclk t su(1) 4.0 ns data hold time after dclk t h(1) 7.0 ns dspe set up time for dclk t su(2) 15.0 ns dspe hold time after dclk t h(2) 4.0 ns dpar set up time for dclk t su(4) not shown 3.0 ns dpar hold time after dclk t su(4) not shown 7.0 ns dc1j1 set up time for dclk t su(3) 4.0 ns dc1j1 hold time after dclk t h(3) 7.0 ns note: the relationship between j1 and the spe signals is shown for illustration purposes only, and will be a function of the pointer offset. for the au-4/sts-3c format there will be one j1 pulse, which indicates the start of the vc-4 that carries the 140 mbit/s poh bytes and payload. the c1 pulse is shown dotted because the c1 pulse may be provided on the dc1 signal lead. if the dc1 signal lead is not used it must be grounded. when the pointer tracking machine is selected, the j1 pulse and spe signal are not required. the dpar signal is not shown. dc1j1 (input) dspe (input) dclk (input) c1(3) t h(2) t h(3) t su(3) t cyc dd7-dd0 (input) j1 c 1 ( 1 ) c 1 ( 2 ) c 1 ( 3 ) data data data j 1 d ata data d ata t h(1) t su(1) t su(2) t pwh - 28 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 9. transmit overhead comm channel timing figure 10. receive overhead comm channel timing parameter symbol min typ max unit tochc clock low time t pwl 668.7 1183.1 ns tochc clock high time t pwh 668.7 ns tochd data set up time for tochc t su 10.0 ns tochd data hold time after tochc t h 7.0 ns parameter symbol min typ max unit rochc clock low time t pwl 668.7 1183.1 ns rochc clock high time t pwh 668.7 ns rochd data output delay from rochc t d -4.0 5.0 ns note: the clock will be non-symmetrical. tochd (input) tochc (output) t pwh t h t su t pwl note: the clock will be non-symmetrical. rochd (output) rochc (output) t pwh t pwl t d - 29 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 11. transmit path overhead interface timing parameter symbol min typ max unit tpohc clock high time t pwh 668.7 1337.4 ns tpohc clock low time t pwl 668.7 1337.4 ns tpohf framing pulse output delay for tpohc t d -2.0 5.0 ns tpohd data in set up time for tpohc t su 10.0 ns tpohd data in hold time after tpohc t h 7.0 ns tpohf pulse width t pw 1388.8 ns note: the clock will be non-symmetrical. tpohd (input) tpohf (output) t pwh t pw t d tpohc (output) t pwl t su t h bit 1 byte j1 bit 2 byte j1 - 30 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 12. receive path overhead interface timing parameter symbol min typ max unit rpohc clock high time t pwh 668.7 1337.4 ns rpohc clock low time t pwl 668.7 1337.4 ns rpohf framing pulse output delay from rpohc t d(1) -2.0 5.0 ns rpohd data output delay from rpohc t d(2) -2.0 5.0 ns rpohf pulse width t pw 1388.8 ns note: the clock will be non-symmetrical. rpohf (output) t pwh t pw t d(1) rpohc (output) t pwl t d(2) bit 2 byte j1 bit 1 byte j1 rpohd (output) bit 8 byte z5 - 31 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 13. transmit alarm indication port timing parameter symbol min typ max unit taipc clock high time t pwh 617.3 1388.8 ns taipc clock low time t pwl 771.6 ns taipd data set up time for taipc t su(1) 3.0 ns taipd data hold time after taipc t h(1) 7.0 ns taipf framing pulse set up time for ta i p c t su(2) 3.0 ns taipf framing pulse hold time after ta i p c t h(2) 7.0 ns note: alarm indication byte consists of eight bits repeated, nine times. bit 8 in each byte is stretched. the first four bits correspond to the febe count (bits 1 through 4 in g1), bit 5 is the path rdi value, and bits 6 and 7 are set to 0, while bit 8 is set to 1. ta i p d (input) ta i p f (input) t pwh ta i p c (input) t pwl t su(1) t h(1) bit 1 of byte 1 bit 2 of byte 1 t su(2) t h(2) - 32 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 14. receive alarm indication port timing parameter symbol min typ max unit rpohc clock high time t pwh 617.3 1388.8 ns rpohc clock low time t pwl 771.6 ns rpohf framing pulse output delay from rpohc t d(1) -2.0 5.0 ns raipd data output delay from rpohc t d(2) -2.0 5.0 ns rpohf pulse width t pw 1388.8 ns note: alarm indication byte consists of eight bits repeated, nine times. bit 8 in each byte is stretched. the first four bits correspond to the febe count (bits 1 through 4 in g1), bit 5 is the path rdi value, and bits 6 and 7 are set to 0, while bit 8 is set to 1. rpohf (output) t pwh t pw t d(1) rpohc (output) t pwl t d(2) bit 2 of byte 1 bit 1 of byte 1 raipd (output) bit 8 of byte 9 - 33 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 15. microprocessor timing read cycle - intel parameter symbol min typ max unit address set up time to sel t su(1) 10.0 ns data valid delay after rdy t d(1) 5.0 ns data float time after rd t f 0.0 11.0 ns sel set up time for rd t su(2) 0.0 ns rd pulse width t pw(1) 40.0 ns sel hold time after rd t h(1) 0.0 ns rdy delay after rd t d(2) 0.0 30.0 ns rdy pulse width t pw(2) 0.0 4.0 s address hold time after rd t h(2) 5.0 ns rdy rd sel a(7-0) d(7-0) t d(2) t su(1) t su(2) t pw(2) t pw(1) t h(1) t f t d(1) t h(2) - 34 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 16. microprocessor timing write cycle - intel parameter symbol min typ max unit address hold time after wr t h(1) 0.0 data hold time after wr t h(2) 5.0 ns data valid set up time to wr t su(1) 20.0 ns address valid set up time for sel t su(2) 10.0 ns sel set up time for wr t su(3) 0.0 ns wr pulse width t pw(1) 40.0 ns rdy delay after wr t d 0.0 30.0 ns rdy pulse width t pw(2) 0.0 4 us sel hold time after wr t h(3) 3.0 ns rdy to wr t wh 0.0 ns rdy wr sel a(7-0) d(7-0) t d t su(3) t pw(2) t pw(1) t su(1) t h(1) t wh t h(3) t h(2) t su(2) - 35 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 17. microprocessor timing read cycle - motorola parameter symbol min typ max unit address hold time after sel t h(1) 5.0 data float time after sel t f(1) 0.0 13.0 ns address valid set up time for sel t su(1) 10.0 ns read set up time for sel t su(2) 5.0 ns select pulse width t pw(1) 40.0 ns dtack pulse width t pw(2) 0.0 4 us data output delay after dtack t d 0.0 ns dtack float time after sel t f(2) 0.0 10.0 ns dtack rd/wr sel a(7-0) d(7-0) t su(2) t su(1) t f(2) t f(1) t h(1) t pw(2) t d t pw(1) - 36 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 18. microprocessor timing write cycle - motorola parameter symbol min typ max unit address hold time after sel t h(1) 5.0 ns data hold time after sel t h(2) 3.0 ns rd/wr hold time after sel t h(3) 0.0 ns data valid set up time for sel t su(1) 20.0 ns address valid set up time for sel t su(2) 10.0 ns write set up time for sel t su(3) 5.0 ns select pulse width t pw(1) 40.0 ns dtack pulse width t pw(2) 0.0 4 us dtack float time after sel t f 0.0 10.0 ns dtack rd/wr sel a(7-0) d(7-0) t pw(2) t h(3) t su(2) t f t su(3) t su(1) t pw(1) t h(2) t h(1) - 37 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 19. microprocessor timing read cycle multiplex bus - motorola parameter symbol min typ max unit sel to as , setup time t su(1) 20.0 ns rd/wr (read) to ds , setup time t su(2) 20.0 ns as time t pw(1) 20.0 ns as to ds , setup time t su(3) 20.0 ns mad(7-0) three-state to ds setup time t su(4) 20.0 ns data out delay from ds t d(1) 250.0 ns dtack active out delay from ds t d(2) 330.0 ns dtack inactive out delay from ds t d(3) 20.0 ns data out hold time after ds t h(1) 20.0 ns as hold time after ds t h(2) 0.0 ns rd/wr (read) hold time after ds t h(3) 0.0 ns sel hold time after ds t h(4) 0.0 ns mad(7-0) dtack ds rd/wr as t d(3) t d(1) t su(3) sel address data t h(1) t d(2) t su(4) t pw(1) t h(2) t h(3) t h(4) t su(2) t su(1) - 38 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 20. microprocessor timing write cycle multiplex bus - motorola parameter symbol min typ max unit sel to as , setup time t su(1) 20.0 ns rd/wr (write) to ds , setup time t su(2) 20.0 ns as time t pw(1) 20.0 ns as to ds , setup time t su(3) 20.0 ns dtack active out delay from ds t d(2) 330.0 ns dtack inactive out delay from ds t d(3) 20.0 ns data in valid setup time for ds t su(6) 20.0 ns data in hold time after ds t h(6) 0.0 ns as hold time after ds t h(2) 0.0 ns rd/wr (read) hold time after ds t h(3) 0.0 ns sel hold time after ds t h(4) 0.0 ns address valid setup time for as t su(5) 20.0 ns address hold time after as t h(5) 0.0 ns mad(7-0) dtack ds rd/wr as t d(3) t su(3) sel address data t h(6) t d(2) t su(6) t pw(1) t h(2) t h(3) t h(4) t su(2) t su(1) t h(5) t su(5) - 39 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 21. boundary scan timing parameter symbol min max unit tck clock high time t pwh 50 ns tck clock low time t pwl 50 ns tms setup time to tck t su(1) 3.0 - ns tms hold time after tck t h(1) 2.0 - ns tdi setup time to tck t su(2) 3.0 - ns tdi hold time after tck t h(2) 2.0 - ns tdo delay from tck t d -7.0ns tms tdi tdo* t d tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl *note: tdo is a three-state output. if this pin is used, it should be connected via a 4.7 k ? resistor to the +5 volt supply. - 40 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 operation the operations section is divided into two major sections: internal device operation, and external device interfaces. internal device operation timing modes the l4m supports the following timing modes: drop bus, add bus, and external timing modes. in the drop bus timing mode, the drop bus clock (dclk) and the c1 pulse (dc1j1 or dc1) before or after framing reference compensation, provide the time base for deriving the add bus signals which consist of clock (aclk), data (ad(7-0)), c1 and j1 indicator (ac1j1 and ac1), spe indicator (aspe), add indicator (add ), and parity (apar). the add side j1 pulse is derived internally. the add bus starting location for the spe may have a pointer value equal to 0 or 522. in the add bus timing mode, add bus timing signals are independent of the drop bus signals. add bus timing is derived from add bus input signals which consists of a clock (aclk), c1 and j1 indicator (ac1j1 and ac1), and spe indicator (aspe). the output signals consists of data (ad(7-0)), add indicator (add ), and parity (apar). the starting location of the spe (j1 byte) is determined by the input j1 pulse (ac1j1), and spe indi- cator (aspe). in the external timing mode, the external timing signals are independent of the drop bus timing. the external timing signals consist of an external clock (extc) and optional frame reference pulse (exc1). the l4m can also compensate for up to one frame of offset delay for the external c1 pulse. add bus output timing is derived from the two external signals and consists of a clock (aclk), c1 and j1 indicator (ac1j1 and ac1), spe indi- cator (aspe), data (ad(7-0)), add indicator (add ), and parity (apar). the add bus starting location for the spe may have a pointer value equal to 0 or 522. the three timing modes are selected using two control pins, designated as dropt (pin 35) and enabt (pin 36). the following table lists the control lead states for selecting the timing mode. receive c1 reference delay when the pointer tracking feature is enabled by placing a high on the pten lead (pin 2), and control bit rc1dc (bit 3 in 18h) is written with a 1, a 12-bit register location (19h and 18h) is enabled which can com- pensate for up to 2429 positions (270 columns x 9 rows) for a dropped c1 reference pulse. for example, if a binary 0 is written into the 12-bit register by the microprocessor, the c1 pulse (in dc1j1 or dc1) must be in the c11 time slot (the correct time slot). when the binary value of 1 is written into the 12-bit register, it is assumed that the c1 pulse is shifted one time slot (one clock cycle) into the time slot that corresponds to the c12 byte. this means that the starting point for the frame reference should be one byte earlier. values written into the 12-bit register greater than 2429 will be counted as a delay equal to 0. dropt pin enabt pin timing mode low low add bus timing x high external timing high low drop bus timing - 41 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 22. pointer interpretation state diagram pointer tracking feature the pointer tracking feature is enabled by placing a high on the pten lead (pin 2). the au-4 pointer is carried in the h1 and h2 bytes. the starting location for the frame is determined by the c1 pulse present in the dc1j1 or dc1 signal lead. when the pointer tracking feature is enabled, the j1 pulse in the dc1j1 signal must not be present, nor is the dspe signal required. the pointer tracking machine derives the starting location of the j1 byte and the other vc-4 bytes. the pointer tracking state machine is compliant with the etsi state machine specified in the etsi 1015 document. a logic diagram of the state machine is shown in figure 22. no addi- tional states or transitions have been added to the pointer state machine. for north american applications, a control bit is provided for disabling the ais to lop transition, which is shown as a dotted line in figure 22. this transition is disabled by writing a 1 to control bit pads (bit 1 in 18h). in addition, control bits are provided which permit the value of the s-bits (h1 byte) in the pointer tracking machine to be disabled, equal to 10, or to a microprocessor-written value. inc lop ndf dec ais norm 8*ndf_enable offset undefined 3*new_point accept new offset 8*inv_point offset undefined inc_ind incr. offset 3*new_point accept new offset dec_ind decr. offset ndf_enable accept new offset 3*new_point accept new offset 3*any_point accept new offset 3*ais_ind offset undefined from all states note: the ais to lop transition is not specified for north american applications, and can be disabled by setting the pads control bit to a 1. - 42 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 the following table lists the control states associated with the ss-bits. path ais and loss of pointer alarms are provided. in addition, pointer increments, decrements, and ndfs are counted in 8-bit performance counters. upstream receive ais indication an upstream ais indication can be provided for the l4m in one of two ways: using the e1 byte in the transport overhead bytes, or control lead indications. the upstream ais indication can generate a 140 mbit/s line ais and transmit path rdi, when enabled. writing a 0 to control bit eape enables using the e1 byte for the upstream ais indication. for example, the transwitch sot-3 generates an ais signal (all ones) in the e1 byte when a loss of frame, loss of signal, loss of pointer, or line or path ais are detected. the l4m uses majority logic (five out eight ones) to determine if the e1 byte has an ais indication (e1ais alarm). the first and subse- quent indications indicate the alarm condition. recovery occurs on the first indication that the e1 byte does not have an all ones (ais) state. this indication is to be used by the l4m to generate a receive ais indication and path rdi, when enabled. when a 1 is written to the eape control bit it disables the detection of all ones in the e1 byte, and enables the istat and pais leads. an active high on the istat or pais lead causes the xistat and xpais alarms, and a 140 mbit/s line ais and path rdi when enabled. receive path overhead byte processing the path overhead bytes consist of the j1, b3, c2, g1, f2, h4, z3, z4, and the z5 bytes. all poh bytes are provided at the external poh interface, including the b3 byte. the poh bytes are also written into the l4m memory map for a microprocessor read cycle. path overhead byte processing is inhibited (and functions reset) when an active low is placed on the pohdis lead (pin 19). poh processing (for c2 and j1) is also inhibited when any of the following alarms are detected: - drop bus of the j1 pulse (dbloj1) when the pten pin is low - drop bus loss of clock (dbloc) - e1ais detected (e1ais) when eape control bit is 0 - pais alarm pin equal to 1 (xpais alarm) when eape control bit is 1 - istat alarm pin equal to 1 (xistat alarm) when eape control bit is 1 - receive loss of pointer (rlop) when pten pin is high - receive path ais (rpais) when pten pin is high rpsds rpssel action 00 pointer tracking machine uses 10 as the ss-bit value in the state machine. 0 1 pointer tracking machine uses microprocessor-written value for ss-bit check in state machine. 1 x ss-bit check in pointer tracking machine disabled. pointer tracking machine ignores the ss-bits in the transition state definitions. - 43 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 receive j1 byte processing there are two possible received j1 message sizes, 16 bytes (itu-t), or 64 bytes (ansi). the l4m is capable of dimensioning the transmit (and receive) ram memory segment to the two sizes (16-byte or 64-byte). in addition, two modes of operation are provided for the 16-byte (itu-t) format: a microprocessor read mode, and a compare read mode. the following table lists the various control states associated with j1 processing. ccitt j1com action 0 x transmit and receive j1 segments are configured for the 64-byte j1 message size. no relationship is required between the memory segment and the mes- sage written for transmission or for the message received. 1 0 transmit and receive j1 segments are configured for the 16-byte j1 message size. no relationship is required between the memory segment and the mes- sage written for transmission or the message received. 1 1 transmit and receive j1 segments are configured for the 16-byte j1 message size. no relationship is required between the memory segment and the mes- sage written for transmission. for the receive j1 bytes, a 16-byte microproces- sor message is written into a 16-byte segment for comparison against the received message. the written message must start with the multiframe indicator written into the starting location of the segment. the l4m does not perform the crc check in the 16-byte message. - 44 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 the itu-t defined 16-byte message consists of an alignment signal of (10000000 00000000) in the most sig- nificant bit (bit 1) of the message. the remaining 7 bits in each frame consists of a data message, as illustrated below. itu-t 16-byte j1 message format the j1 16-byte message comparison works according to the following steps: 1. assume that the l4m j1 detector is out of lock, and there is no mismatch alarm. 2. a 16-byte reference message is written into the memory map by the microprocessor. 3. the incoming message is received, and the j1 comparison circuit searches for the multiframe pattern (1000...0 pattern). 4. multiframe is found. 5. the incoming (received) 16-byte message is then checked for three consecutive 16-byte message repeats. 6. if an error occurs before step 5 is completed, the sequence repeats, starting at step 3. 7. if the incoming 16-byte message repeats three times in row (after the multiframe is detected) without an error, the internal memory map segment is updated. this is an in-lock condition, and the j1 loss of lock alarm is reset. 8. this stable message is compared against the microprocessor-written message, byte for byte for 16-bytes (the length of the multiframe message). if they compare, a match is declared. no mismatch alarm. if they do not compare a mismatch alarm is declared. a j1 mismatch alarm results in rdi and ais being sent continuously, when enabled. there is no out-of-lock alarm because the received message is stable. 9. if the microprocessor-writes a new byte, a j1 trace identifier mismatch (j1tim) alarm will also occur because the receive message is stable but there is mismatch between the two locations. a mismatch alarm is declared, and rdi and ais are sent continuously, when enabled. there is no out-of-lock alarm because the received message is stable. 10. if the receive message changes for three consecutive 16-byte messages, an out of lock alarm occurs. however, the mismatch alarm resets. 11. the sequence repeats. when the j1 is not in lock (j1 lock equal to 0), a j1 loss of lock alignment alarm (j1lol) is declared. this pro- cess is inhibited and reset during an incoming ais condition. bit12345678 1 16-byte j1 message 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 45 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 receive c2 byte the l4m provides c2 signal label mismatch detection between the received c2 byte, and a microprocessor- written value and also a fixed 01h value in hardware, when enabled. when control bit c2fvd is written with a 1, the detection of the 01 value is disabled, and detection depends solely on the register value written by the microprocessor. five or more consecutive mismatched signal labels in the c2 byte from the microprocessor- written value or a label not equal to the 01h (when c2fvd=0) results in a path signal label error (pslerr) alarm. the alarm state is exited when five or more consecutive matches, or the 01h value (when c2fvd=0) are received correctly. the l4m also provides an unequipped indication (c2eq0) when the incoming c2 byte matches an internal 00h value for five consecutive frames. the alarm is exited when the c2 byte does not equal a 00h value for five or more consecutive frames. please note that if the accepted path signal label value is all zeros (c2 unequipped), or an 01 (if c2fvd=0), a mismatch alarm (pslerr) is not declared. the c2 mismatch detection and unequipped indication are disabled when any of the following alarms are detected. - loss of drop bus j1 pulse (dbloj1) when the pten pin is low - e1 ais (e1ais) (from the drop bus) when eape is 0 - istat is a 1 when eape is 1 - pais is a 1 when eape is 1 - receive loss of pointer (rlop) when the pten pin is high - receive path ais (rpais) when the pten pin is high receive g1 byte the received states of the g1 byte are provided for a microprocessor read cycle, and are also provided at the path overhead byte interface, for external processing as required. bits 1 through 4 in the g1 byte convey a febe count. there are nine possible valid febe values, 0 through 8. other values are detected as a zero count. the febe value received is the count of interleaved bit blocks that have been detected in error in the received path bip-8 code at the far end. a 16-bit counter is provided for counting the number of febe bits or blocks received in error. up to eight errors per frame may be counted. bit 5 is the defined as the path far end receive defect indication alarm (path rdi) indication. a receive path rdi alarm indication (rrdi) occurs when the l4m detects a one for five or ten consecutive frames. recovery occurs when the l4m detects a zero for five or ten consecutive frames. writing a 1 to control bit rdi10 selects the detect and recovery value of 10 consecutive events. bits 6, 7, and 8 in the g1 byte are unassigned and are normally received as 0s. they are provided for both a microprocessor read cycle and at the external poh interface. receive desynchronizer the rate at which the pointer leak buffer is to be leaked is written to the 15-bit pointer leak rate register. if enhanced desynchronizer operation is required, the following additional signals are provided: a stuff indica- tion lead, positive and negative justification indications, and a pointer leak counter equal to zero indication lead. for controls, a loaden control bit and a 9-bit (plus sign bit) pointer offset counter are provided, in addition to the 15-bit pointer leak rate register. - 46 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 receive 140 mbit/s line ais generation the l4m provides two techniques for generation of line ais. the first approach uses an external clock, and the second approach uses a bit stuffing technique. the use of an external stable clock for ais permits the receive performance monitoring circuit to be used (i.e., receive ais detector and receive frame alignment detector), while the bit stuffing ais approach disables the receive performance monitoring circuit when the l4m is gener- ating a receive line ais. line ais is defined as all ones in the data signal. in addition, in the receive direction, when bsaise=1 line ais cannot be generated when the drop bus clock is lost, since this clock is required for generating line ais. when the bit stuffing ais approach is not used and the l4m generates an rxais signal, the external pll will lose lock. in this case the aisind pin can be used with some external logic to cause the external 139.264 mhz vcxo to lock onto the ais clock to maintain proper synchronization of the 139.264 mhz vcxo clock. using an external clock for ais generation is enabled by writing a 0 to control bit bsaise (bit 0 in 1ch). please note that control bit bsaise is 0 upon power-up. the ais clock is either 17.408 mhz for byte operation, or 34.816 mhz for nibble operation. the ais clock is monitored for operation and an alarm indication (laisc) pro- vided when this clock is not functioning. loss of ais clock also prevents the l4m from generating a line ais in either the transmit or receive directions. when the l4m is required to generate either a transmit or receive line ais the external aisck clock input is used as the timebase. the bit stuffing approach does not require an external clock. the capability to generate line ais on alarm indi- cations is enabled by writing a 1 to control bit bsaise. in the transmit direction, line ais is generated by bit stuffing 7/9 of the time using an all ones pattern for data. the actual technique consists of performing stuffing for the first four rows of the 9 subframes (ccccc=1, and the s-bit is 0). frequency justification is performed for row 5, bit stuffing for rows 6, 7, and 8, followed by frequency justification for row 9. in the receive direction, the approach is the same, bit stuffing is multiplexed into the format prior to the desynchronizer. in the transmit direction, line ais cannot be transmitted when the drop clock is lost in the drop bus timing modes, in the add bus timing mode when the add bus clock is lost, or when the external clock is lost in the external timing mode. receive and transmit performance monitoring the l4m provides 139.264 mbit/s receive and transmit performance monitoring. performance monitoring includes frame alignment, providing the status of the remote indication alarm bit, counting framing errors and, when enabled, works in conjunction with the ais detector circuits. the l4m monitors the receive and transmit data for frame alignment as specified in itu-t recommendation g.751. the frame structure consists of 2928 bits, starting with bit 1. the frame alignment pattern is carried in bits 1 through 12, and has the following frame alignment pattern: 111110100000. after frame alignment, a 16-bit performance counter counts the number of errored frames (one or more bits in the frame alignment pat- tern is in error) in both the transmit and receive directions. in addition, the status of the distant alarm indication (bit 13 in the format) is provided. a 1 causes a tdai alarm (bit 5 in 28/29h), or a rdai alarm (bit 4 in 28/29h), and an interrupt if the mask bit is enabled, and the hardware interrupt is enabled. no other action is taken upon detection of distant alarm indication. an enable bit (lfaise) is provided to generate a 140 mbit/s ais, when loss of frame alignment is detected. the frame alignment detection can be coupled with the ais recovery cir- cuit by setting the fdaen control bit to 1. in the receive direction, the performance monitoring circuit (i.e., receive ais detector and receive frame alignment detector) is disabled when the bit stuffing ais feature is enabled and the l4m is generating a receive line ais; also, the receive frame error counter is inhibited on a rlof alarm or dbloc alarm and the transmit frame error counter is inhibited on a tlof alarm. - 47 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 transmit unequipped channel generation the l4m provides the capability of generating an unequipped channel or a supervisory unequipped channel. the following table lists the control bit states for generating the two types of unequipped channels and the pri- ority associated with path ais. transmit poh bytes the insertion of the transmit poh bytes is enabled by placing a high on the signal lead labeled pohdis (pin 19). this signal lead has priority over the control bits such as the poh enable control bit for unequipped status (poheuq). when an active low is placed on this pin, the insertion of poh bytes into the spe is disabled. however, the poh ram locations may still be written to by the microprocessor. the starting location of the payload (without the poh bytes) will be still determined by the j1 pulse (add bus timing), or at the 0 or 522 location (drop bus or external timing modes), determined by the svc4h control bit. when enabled (pohdis is high), the l4m has the capability of inserting the path overhead bytes from ram locations, or from an external poh interface (except the b3 byte). the individual ram locations are allowed to be updated during operation. the l4m is also equipped with a control bit (pohram) that permits the path overhead bytes (except the b3 byte) from the transmit poh interface (when selected) to be written into common ram locations (or micropro- cessor-written values) in addition to being transmitted. the following are the control states associated with the pohram and exbn control bits. this feature allows the microprocessor to read selected transmitted poh interface bytes prior to transmission for test purposes. in addition, this feature permits the user to switch back and forth between a selected poh i/o byte and the ram location, without having to reinitialize the ram poh byte locations during switch-over. tuneq poheuq paisg action 0 x 0 normal operation 1 0 0 transmit unequipped channel. poh bytes and payload bytes are equal to zero. 1 1 0 transmit supervisory unequipped channel. poh are transmitted (if enabled). payload bytes are transmitted as zero. x x 1 transmit path ais. poh (when enabled) and payload bytes transmit- ted as 1. pohram exbn action 1 1 the external interface poh byte that is selected is transmitted and is also written into ram. for example, when exf2 is a 1, the external interface f2 byte is trans- mitted and written into the ram each frame. 0 1 the external poh byte that is selected is transmitted. the microprocessor can write a value to ram as required. for example, when exf2 is a 1, the external interface f2 byte is transmitted each frame, but is not written to the ram location. x 0 microprocessor-written poh byte is transmitted, except b3 and g1 bytes. see ring, febeen and rdien control bits for more information. - 48 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 transport (section) overhead bytes the l4m provides an option in the drop bus and external timing modes to provide selected transport (section) overhead bytes. this feature is selected by writing a 1 to control bit tohout (bit 5 in 14h). the selected toh bytes are the six a1 and a2 framing bytes, c1 byte, and the h1 and h2 pointer bytes (including y and 1s pointer bytes). the a11, a12, and a13 bytes are equal to f6h, while a21, a22, and a23 are equal to 28h. when control bit upc1 is a 0, the value 01h is transmitted as the c1 byte. when upc1 is a 1, the micropro- cessor-written value in 17h is transmitted as the c1 byte. the pointer values h1 and h2 correspond to h11 and h21 in the au-4 pointer (h11, h12, h13, h21, h22, h23), as illustrated below. the h11 and h21 bytes carry the pointer value that corresponds to 522 or 0, depending on the state of the svc4h control bit. the h12 and h13 bytes carry the value 1001ss11. the h22, and h23 bytes are specified as all ones. note: nnnn is equal to 0110. when control bit tpssel is a 0, the ss-bits are transmitted as a 10, while the ss-bits in h12 and h13 are undefined and are transmitted as 00. when a 1 is written into the transmit pointer s-bit select control bit tpssel, the microprocessor is able to program the ss and ss bits. register 1dh has the following structure: transmit c1 reference delay (external timing mode only) when the external timing mode is selected, and control bit tc1dc (bit 3 in 16h) is written with a 1, a 12-bit register location (19h and 18h) is enabled which can compensate for up to 2429 positions (270 columns x 9 rows) for the external c1 reference pulse. for example, if a binary 0 is written into the 12-bit register by the microprocessor, the external c1 pulse (in exc1) is in the c11 time slot (the correct time slot). when the binary value of 1 is written into the 12-bit register, it is assumed that the c1 pulse is shifted one time slot (one clock cycle) into the time slot that corresponds to c12 byte. this means that the starting point for the transmit frame reference should be one byte earlier. values written into the 12-bit register other than 2429 will be counted with a delay equal to 0. add bus c1 input/output pulse when control bit ac1en is a 1, in the drop timing mode and external timing modes, the c1 indicator pulse is provided as a separate output lead (ac1) instead of being in the c1j1 signal. in this mode, the c1j1 signal will carry the j1 pulse only. in the add bus timing mode, the ac1 lead is or-gated with the ac1j1 signal to form a composite internal c1j1 signal. the ac1 option is selected using the states defined in the table below: h11 h12 h13 h21 h22 h23 nnnnssid 1001ss11 1001ss11 idididid 11111111 11111111 bit76543210 ts ts ts ts ts ts rs rs transmit h11 transmit h12 transmit h13 receive h11 ac1en ac1 pin action 0 low normal operation. pin is grounded. c1 is provided in the ac1j1 signal. 1 c1 pulse in the drop timing and external timing modes, c1 is provided as a separate output signal. the ac1j1 signal contains the j1 signal only. in the add bus timing mode, the c1 signal may be provided in the ac1j1 signal or as a separate signal. - 49 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 test generator and analyzer the l4m is equipped with a transmit test generator and receive analyzer. a simplified block diagram of the test generator and analyzer is shown in figure 23 below. the transmit clock (txc) must be present in order for the 2 23 -1 test generator to function. the test generator sequence is specified in itu-t recommendation o.151. the test generator is enabled by writing a 1 to control bit tgen (bit 2 in 14h). the byte or nibble transmit input is disabled and the test sequence is enabled. the test generator can be also be enabled when the l4m is in line loopback. the 2 23 -1 test analyzer samples the receive data for operation. the test analyzer is enabled by writing a 1 to control bit anaen (bit 1 in 14h). the test analyzer monitors the incoming test sequence for lock, using consecutive 1000-bit blocks (not a sliding window). an out of lock alarm (anool) is detected when 30 bits in a 1000-bit sequence are detected in error. recovery occurs when the first 24 bits in the test sequence match. errors are counted in a 16-bit performance counter (locations 44 and 45h). the counter is inhibited when out of lock or when the analyzer is disabled. figure 23. test generator, analyzer and loopback output block input block receive te s t analyzer transmit te s t generator xmit data (byte/nibble) xmit clock rec data (byte/nibble) rec clock nib lead data clock nib lead loopback enable test generator enable data clock clock data clock te s t pattern xmit fifo test analyzer enable data desync circuit clock data - 50 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 performance counters all 16-bit performance counters have a special 16-bit read operation which allows uninterrupted access, with- out the danger of one byte changing while the other byte is read. to perform a 16-bit read operation, the low order byte is read first. the read operation freezes the count in the high order byte. the high order byte should be read next. all the performance counters can also be configured to be either saturating or non-saturating. when a 0 is writ- ten to control bit cor (bit 0 in 13h), the performance counters are configured to be saturating, with the counters stopping at their maximum count. an 8-bit or 16-bit counter is reset on a microprocessor read cycle. counts that occur during the read cycle are held, and the counter updated afterwards. when a 1 is written to control bit cor, the performance counters are configured to be non-saturating, and roll over after the maxi- mum count in the counter is reached. in this mode, the counters do not clear on a microprocessor read cycle, but continue to count. all the performance counters can be reset simultaneously by writing a 1 to control bit rsetc (bit 7 in 1ch). this bit is self clearing, and does not require the microprocessor to write a 0 into this location afterwards. in addition, a performance counter can also be cleared by writing the value of 00h to the low byte, immediately followed by writing a 00h to address n+1. the n+1 address location contains the high order byte of the 16-bit performance counter. all performance counters (except the receive framing error counter and the transmit framing error counter) are inhibited when any of the following alarms occur, and released for operation after the last alarm clears. - loss of drop bus j1 pulse (dbloj1) when pten pin is low. - receive loss of pointer alarm (rlop) when pten pin is high. - receive path ais alarm (rpais) when pten pin is high. - loss of drop bus clock (dbloc). - e1 byte ais detected (e1ais) when external alarm enable (eape) control bit is 0. - external alarm istat pin is high (xistat) when external alarm enable (eape) control bit is 1. - external alarm pais pin is high (xpais) when external alarm enable (eape) control bit is 1. - j1 loss of lock (j1lol) alarm and control bit j1len is a 1 (and pohdis is a 1). - j1 trace identifier mismatch (j1tim) alarm and control bit j1ten is a 1 (and pohdis is a 1). - received active low on the external ais lead (xais alarm). - path signal label enable control bit (psler) is a 1, and either a pslerr or c2eq0 alarm occurs. the receive framing counters and transmit framing counters are inhibited on loss of frame alignment. - 51 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 boundary scan introduction the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and controllability for the l4m device ? s interface pins. the boundary scan block consists of a test access port (tap) controller, instruction and data registers, and a boundary scan path bordering the input and output pins. the boundary scan test bus interface consists of four input signals (test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs ) and a test data output (tdo) output signal. the tap controller receives external control information via a test clock (tck) signal and a test mode select (tms) signal, and sends control signals to the internal scan paths. the scan path architecture consists of a two-bit serial instruction register and two or more serial data registers. the instruction and data registers are connected in parallel between the serial test data input (tdi) and test data output (tdo) signals. the test data input (tdi) signal is routed to both the instruction and data registers and is used to transfer serial data into a register during a scan operation. the test data output (tdo) is selected to send data from either regis- ter during a scan operation. when boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the l4m device ? s internal logic, as illustrated in figure 24. during boundary scan testing, the boundary scan register disables the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. a timing diagram for the boundary scan feature is provided in figure 21. boundary scan support the maximum frequency the l4m device will support for boundary scan is 10 mhz. the l4m device performs the following boundary scan test instructions: -extest - sample/preload -bypass extest test instruction: one of the required boundary scan tests is the external boundary test (extest) instruction. when this instruction is shifted in, the l4m device is forced into an off-line test mode. while in this test mode, the test bus can shift data through the boundary scan registers to control the external l4m input and output leads. sample/preload test instruction: when the sample/preload instruction is shifted in, the l4m device remains fully operational. while in this test mode, l4m input data, and data destined for device outputs, can be captured and shifted out for inspec- tion. the data is captured in response to control signals sent to the tap controller. bypass test instruction: when the bypass instruction is shifted in, the l4m device remains fully operational. while in this test mode, a scan operation will transfer serial data from the tdi input, through an internal scan cell, to the tdo pin. the purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested to only a single clock delay. - 52 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 24. boundary scan schematic tap controller bypass register instruction register tdi tdo in out controls boundary scan serial test data core logic of l4m boundary scan register signal input and output pins 3 device - 53 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 boundary scan chain there are 124 scan cells in the l4m boundary scan chain. bidirectional signals require two scan cells. addi- tional scan cells are used for direction control as needed. the following table shows the listed order of the scan cells and their function. scan cell no. i/o pin no. symbol comments 1 input 104 test should be set to 0. 2 input 105 exc1 3 output 107 tochc 4 output 108 ad0 5 output 109 ad1 6 output 110 ad2 7 output 111 ad3 8gzadb output enable for ad0...ad7 9 output 113 ad4 10 output 114 ad5 11 output 115 ad6 12 output 116 ad7 13 output 117 add 14 output 119 apar 15 gzbida output enable for ac1, aclk, aspe, and ac1j1. 0=output, 1=input 16 bidirectional 120 ac1 17 bidirectional 121 aclk 18 bidirectional 122 aspe 19 bidirectional 123 ac1j1 20 input 125 extc 21 input 126 dc1 22 input 127 dc1j1 23 input 128 dpar 24 input 129 dspe 25 input 131 dclk 26 input 132 test should be set to 0. 27 input 133 dd0 28 input 134 dd1 29 input 135 dd2 30 input 137 dd3 - 54 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 31 input 138 dd4 32 input 139 dd5 33 input 140 dd6 34 input 141 dd7 35 output 143 pleq0 36 input 144 test 37 input 1 reset 38 input 2 pten 39 input 3 test should be set to 0. 40 output 5 rochc 41 output 6 rochd 42 output 7 raipd 43 output 8 rpohd 44 output 9 rpohf 45 output 11 rpohc 46 highze hi-z enable. set to 0 to not tri-state. 47 gzoshared output enable for pj. 0=output, 1=input 48 output 13 pj 49 output 14 ctrl 50 output 15 ctrl 51 input 17 exais 52 input 18 highz 53 input 19 pohdis 54 gzbdshared output enable for nj. 0=output, 1=input 55 bidirectional 20 nj 56 input 21 rxci 57 gzrxco output enable for rxco. 58 output 23 rxco 59 output 24 aisind 60 output 25 rxd0 61 output 26 rxd1 62 output 27 rxd2 63 output 29 rxd3 64 gzrxdc output enable for rxd0...rxd1 scan cell no. i/o pin no. symbol comments - 55 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 65 output 30 rxd4 66 output 31 rxd5 67 output 32 rxd6 68 output 33 rxd7 69 input 35 dropt 70 input 36 enabt 71 input 37 istat 72 input 38 pais 73 input 39 stai 74 bidirectional 41 d0 75 bidirectional 42 d1 76 bidirectional 43 d2 77 bidirectional 44 d3 78 gzdup output enable for d0...d7. 0=ouput, 1=input. 79 bidirectional 45 d4 80 bidirectional 47 d5 81 bidirectional 48 d6 82 bidirectional 49 d7 83 output 50 int/irq 84 gzrdy output enable for rdy/dtack 85 output 51 rdy/dtack 86 input 53 ramci 87 input 55 sel 88 input 56 rd 89 input 57 wr 90 input 59 as 91 input 60 madbus 92 input 61 a0 93 input 62 a1 94 input 63 a2 95 input 65 a3 96 input 66 a4 97 input 67 a5 98 input 68 a6 scan cell no. i/o pin no. symbol comments - 56 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 99 input 69 a7 100 input 71 aisck 101 output 72 stuff 102 input 73 moto 103 input 74 nib 104 input 75 txd0 105 input 77 txd1 106 input 78 txd2 107 input 79 txd3 108 input 80 txd4 109 input 81 txd5 110 input 83 txd6 111 input 84 txd7 112 input 85 exlos 113 input 86 test should be set to 0. 114 input 87 txc 115 input 89 test should be set to 0. 116 gzscan output enable for tests. 117 output 91 test should be set to 0. 118 output 92 tpohf 119 output 93 tpohc 120 input 95 tpohd 121 input 96 taipd 122 input 97 tochd 123 input 98 taipf 124 input 99 taipc scan cell no. i/o pin no. symbol comments - 57 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 external device operation phase-locked loop the phase-locked loop (pll) circuit for the l4m is shown in figure 25. the bandwidth (bw hz) of the pll is given by the following equation. bw = k d k o k h /2 where, ko = (30ppm/v) x (139.264 hz/ppm) x (2 ) kd = 5v/[(2 ) x (256)] kh = 39/[2 x (15 + 36/2)] = 0.591 the bandwidth of the pll is equal to 7.7 hz. figure 25. phase-locked loop to ensure that the l4m meets the jitter performance outlined in the ets1015 document, an adaptive fifo leak rate algorithm must be employed to dynamically adjust the value written to the flr register (1ah). an applica- tion note on this subject entitled ? jitter test results for the l4m device - application note ? , document number txc-03456-0001-an, edition 1.0, february 7, 1995 is available upon request. 139.264 mhz vcxo 30 ppm divided by 4 for nibble i/o by 8 for byte i/o l4m ctrl ctrl rxci 14 15 21 ttl 36k 36k 2.2k +2.0v ttl ecl 741 39k 0.1 f 2 f 15k e.g., connor-winfield edv54-120-31 - + txc-03456 te r m i n a t i o n resistor - 58 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 140 mbit/s line interface figure 26 is a simplified view of the 140 mbit/s line interface. the nib control lead selects whether the receive and transmit line interface is nibble- or byte-wide. the ais clock (aisck) should be connected to a stable 34.816 mhz frequency source for nibble interface operation, or to a 17.408 mhz frequency source for byte interface operation. the ais indication lead (aisind ) provides an external indication when ais is generated. figure 26. l4m 140 mbit/s line interface cmi interface l4m rxdn rxco rxci 21 loop filter receive serial data ctrl ctrl aisind aisck nib txdn txc vcxo cmi interface transmit serial data transmit clock nibble or byte data nibble/byte selection ais clock (as required) ais indication receive clock in receive clock out 23 14 15 24 71 74 87 nibble or byte data txc-03456 - 59 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 ring configuration figure 27 shows two l4m devices arranged in a ring configuration. the two l4ms exchange path febe and rdi information using the alarm indication port. the receive alarm indication port clock and framing pulse are shared with the receive poh byte interface clock and framing pulse signals. this feature is disabled when an active low is placed on the pohdis lead. data (raipd), as a repetitive byte, is clocked out of the l4m using the path overhead interface clock (rpohc). the path overhead frame pulse rpohf indicates the start of the repetitive data byte (raipd). in normal operation, receive alarm indication port data (raipd) is connected to its mate transmit alarm indica- tion port (taipd). the receive clock (rpohc) is connected to transmit clock taipc at its mate, and the receive framing pulse rpohf is connected to the transmit frame pulse input (taipf). likewise, the mate l4m ? s receive data is connected to the transmit alarm interface port. the clock present at taipc is monitored for operation. an alarm indication port loss of clock alarm causes the febe count to be transmitted as 0, and rdi to be transmitted as 0. writing a 1 to the ring control bit selects the ring mode of operation. the alarm indication byte is sent in the following way: the byte is repeated nine times. the information sent via the alarm indication port is: - febe count - path rdi/ferf indication whose value is set by: - received active low on the external ais lead (xais alarm). - received e1 byte indication (e1ais), and control bit eape is a 0. - external istat pin (xistat) alarm, when control bit eape is a 1. - external pais pin (xpais) alarm, when control bit eape is a 1. - drop bus loss of j1 (dbloj1) when pten is low. - receive loss of pointer (rlop) alarm when pten is high. - receive path ais (rpais) alarm when pten is high. - path signal label enable control bit (pslen) is a 1, and either a pslerr or c2eq0 alarm occurs. - control bit j1ten is a 1, and a j1tim alarm occurs. - control bit j1len is a 1, and a j1lol alarm occurs. bits 1-4 bit 5 bit 8 b3 count path rdi 0 0 1 - 60 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 figure 27. use of two l4m devices in ring configuration raipd rpohf rpohc taipd taipf taipc l4m taipd taipf taipc raipd rpohf rpohc l4m 98 9 96 7 11 99 9 98 99 11 7 96 txc-03456 txc-03456 - 61 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 overhead communication channel interface the 139.264 mbit/s format has ten overhead communication channel bits ("o"-bits) per subframe or 90 bits per frame. the "o"-bit receive and transmit interfaces are treated as an asynchronous serial data communications channel. in the transmit direction, the "o"-bit interface consists of an output clock (tochc) and data input lead (tochd). data is clocked into the 140 mbit/s mapper on positive transitions of the clock. the clock is non-sym- metrical. in the receive direction, the interface consists of an output clock (rochc) and data output signal (rochd). data is clocked out of the l4m on negative transitions of the clock. the clock is non-symmetrical. path overhead interface in the transmit direction, timing is provided for clocking in the nine poh bytes. the insertion of poh data from the poh interface is disabled when an active low is placed on the pohdis lead. when enabled, the transmit poh interface b3 byte position is masked out by the l4m. a b3 test byte may be written by the microprocessor into the l4m ram and transmitted in place of the calculated b3 byte, or it may function as a b3 error mask. a transmit non-symmetrical clock (tpohc) and framing pulse (tpohf) are provided for sourcing the path over- head bytes (tpohd) from the external circuitry. the framing pulse is one clock cycle wide and occurs in the first bit time of the j1 byte. in the receive direction all nine path overhead bytes are clocked out at the poh interface. the receive timing is asynchronous in relationship to transmit timing. a receive clock (rpohc) and framing pulse (rpohf) are pro- vided for outputting the path overhead bytes (rpohd) for external circuitry. the framing pulse is one clock cycle wide and occurs in the first bit time of the j1 byte. - 62 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 memory map the following definitions are used for the microprocessor access modes of the memory address locations in the tables below: r/w (read/write), r (read only), r(l) (read latched bit position). control bits address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10 r/w tinvc tlais ring exob testb3 xrdien poheuq addz 11 r/w pslen rdien trdi febeen eape raisen raisg rinvc 12 r/w exz5 exz4 exz3 exh4 exf2 exg1 exc2 exj1 13 r/w j1com ccitt tuneq pohram lhz llbk slbk cor 14 r/w eaisen tcaisen tohout j1len j1ten tgen anaen svc4h 15 r/w lfaise fdaen tpssel rpsds rpssel fbtoz c2fvd upc1 transmit c1 offset 16 r/w 2048 1024 512 256 tc1dc paisg transmit c1 offset 17 r/w 128 64 32 16 8 4 2 1 receive c1 offset 18 r/w 2048 1024 512 256 rc1dc rdi10 pads febebc receive c1 offset 19 r/w 128 64 32 16 8 4 2 1 1a r/w fifo leak rate register 1b r/w fifo leak rate register loaden 1c r/w resetc resetd resets pardo ac1en bsaise 1d r/w ts ts ts ts ts ts rs rs 1e r/w bit 1------------------------------transmit c1 value------------------------------bit 7 1f r/w pldinv - 63 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 status bits interrupt mask bits transmit path overhead bytes address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 20 r anool tlaisd tfifoe abloj1 laisc xais dbloj1 e1ais 21 r(l) anool tlaisd tfifoe abloj1 laisc xais dbloj1 e1ais 22 r buserr rfifoe rrdi pslerr c2eq0 j1lol j1tim rlaisd 23 r(l) buserr rfifoe rrdi pslerr c2eq0 j1lol j1tim rlaisd 24 r tloc abloc dbloc rloc 1sfou xstai xistat xpais 25 r(l) tloc abloc dbloc rloc 1sfou xstai xistat xpais 26 r sint extlos aiploc new 27 r(l) extlos aiploc new 28 r tlof rlof tdai rdai rlop rpais 29 r(l) tlof rlof tdai rdai rlop rpais address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 30 r/w anool tlaisd tfifoe abloj1 laisc xais dbloj1 e1ais 31 r/w buserr rfifoe rrdi pslerr c2eq0 j1lol j1tim rlaisd 32 r/w tloc abloc dbloc rloc xstai xistat xpais 33 r/w hint extlos aiploc new 34 r/w tlof rlof tdai rdai rlop rpais address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 68 r/w b3 test mask and test byte bit 1-----------------------------------------------------------------------------------------------bit 8 69 r/w c2 signal label (microprocessor or poh interface) bit 1-----------------------------------------------------------------------------------------------bit 8 6a r/w transmit febe count (g1 byte) transmit unassigned bit 1----------------------------------bit 4 rdi bit 6---------------------bit 8 6b r/w f2 byte (microprocessor or poh interface) 6c r/w h4 byte (microprocessor or poh interface) 6d r/w z3 byte (microprocessor or poh interface) 6e r/w z4 byte (microprocessor or poh interface) 6f r/w z5 byte (microprocessor or poh interface) 80 to bf r/w j1 byte (64 or 16 bytes of ram) microprocessor or poh interface - 64 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 receive path overhead bytes address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 75 r/w c2 microprocessor-written value for mismatch bit 1-----------------------------------------------------------------------------------------------bit 8 78 r b3 received byte bit 1-----------------------------------------------------------------------------------------------bit 8 79 r c2 received byte bit 1-----------------------------------------------------------------------------------------------bit 8 7a r received febe count (g1 byte) receive unassigned bit 1----------------------------------bit 4 rdi/ferf bit 6---------------------bit 8 7b r f2 byte (microprocessor read) 7c r h4 byte (microprocessor read) 7d r z3 byte (microprocessor read) 7e r z4 byte (microprocessor read) 7f r z5 byte (microprocessor read) c0 to ff or r j1 byte 64 bytes (or 16 bytes) received message c0 to cf bit 1-----------------------------------------------------------------------------------------------bit 8 f0 to ff r/w j1 byte (16 bytes of ram) j1 microprocessor written value for mismatch bit 1-----------------------------------------------------------------------------------------------bit 8 - 65 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 performance counters address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40 r/w b3 counter (low byte) 41 r/w b3 counter (high byte) 42 r/w febe counter (low byte) 43 r/w febe counter (high byte) 44 r/w receive analyzer counter (low byte) 45 r/w receive analyzer counter (high byte) 46 r/w transmit framing pattern error counter (low byte) 47 r/w transmit framing pattern error counter (high byte) 48 r/w receive framing pattern error counter (low byte) 49 r/w receive framing pattern error counter (high byte) 4a r/w b3 block errors (8-bits) 4b r/w positive justification counter (8-bits) 4c r/w negative justification counter (8-bits) 4d r/w ndf counter 4e r desynchronizer pointer offset counter (plboc) 4f r not used plboc sign bit plboc bit 9 - 66 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 memory map descriptions device identifier the device identifier (id) is based on the manufacturer id found in ieee standard 1149.1 on boundary scan, and the id assigned by the solid state products engineering council (jedec). the serial format for this id is shown below: the device identifier is not currently provided as a boundary scan message. however, the manufacturer id and part number are implemented with read-only capability for microprocessor read access. the manufacturer id given for all transwitch chips is 107 (06b hex.). the part number of the l4m device is 03456 (0d80 hex.) in binary. in addition, the read-only segment is expanded to include a 4-bit mask level field and a 4-bit future growth field as shown below: msb lsb version part number manufacturer identify 1 4-bits 16-bits 11-bits address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 004 r mask level growth 003 r revision (version) level 0 0 0 0 002r1101100 0 001r0000000 0 000r1101011 1 - 67 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 control register bit descriptions address bit symbol description 10 7 tinvc transmit invert line clock: a 0 enables byte- or nibble-wide data (txdn) to be clocked into the l4m on positive transitions of the clock (txc). a 1 enables byte- or nibble-wide data to be clocked in on nega- tive transitions of the clock. 6tlais transmit line ais: a 1 enables the l4m to generate and insert an all ones line signal (140 mbit/s ais) in the transmit direction, independent of the state of the enable ais bits and alarms. transmit line ais is gener- ated under the following conditions: - external loss of signal alarm (extlos) when eaisen is a 1, - loss of transmit clock alarm (tloc) when tcaisen is a 1, - loss of 140 mbit/s frame alignment when lfaise is a 1, - microprocessor writes a 1 to this bit position. 5ring path protected ring mode: the l4m must be connected to a mate l4m for this mode. a 1 enables the transmit alarm indication port to control the febe (when febeen=1) and rdi (when rdien=1) that are transmitted in the g1 byte. 4exob external "o"-bit interface: a 1 enables the overhead communication channel data interface for transmitting the 90 overhead communication channel bits ("o"-bits) specified in the 140 mbit/s sdh/sonet format. the interface bits are inserted asynchronously into the sdh/sonet for- mat with respect to the nine subframes. a 0 causes zeros to be transmit- ted for all of the "o"-bits. 3testb3 test b3 byte: a 1 enables a microprocessor-written byte (location 68h) to be the transmitted b3 byte. a 0 enables the microprocessor-written byte in location 68h to work as a b3 error mask. a 1 written into one or more bit positions will cause that bit position to be transmitted inverted from its calculated value, until the bit position is written with a 0. 2 xrdien external rdi enable: a 1 in this bit and the rdien bit enables a path rdi (bit 5 in g1) to be generated and transmitted when a high is placed on the stai pin. a 0 disables the logic level placed on the stai pin from controlling the state of path rdi. 1poheuq poh bytes enabled during unequipped status: this bit works in conjunction with control bit tuneq for generating an unequipped chan- nel. the path overhead byte enable feature must be enabled (pohdis lead is high). tuneq poheuq action 0 x normal operation 1 0 unequipped channel. poh and payload bytes are transmitted as 0. 1 1 supervisory unequipped channel. poh enabled. payload bytes transmitted as 0. - 68 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 10 0 addz add bus force high impedance state: works in conjunction with the control bit fbtoz for controlling the add bus signal states. assuming that there is no drop or add bus alarms, the following states are possible: addz fbtoz action 0 0 normal operation. unused bytes (toh and poh bytes when disabled) are transmitted in the high impedance state. 0 1 normal operation. unused bytes (toh and poh bytes when disabled) are transmitted as 0s. add is forced to 0. 1 0 all add bus bytes (time slots) forced to the high impedance state. note: when add bus timing is selected, data only will be forced to the high impedance state. the c1j1 and spe signals are inputs. in the other two timing modes, add bus and external timing modes, the add bus clock (aclk), spe indicator, c1j1 will be forced to 0. add is forced to 1. 1 1 all add bus bytes (time slots) forced to the zero state. note: when add bus timing is selected, data only will be forced to the zero state. the c1j1 and spe signals are inputs. in the other two timing modes, add and external, the add bus clock, spe, c1j1 will be forced to 0. add is forced to 0. when there is an alarm for the clock that sources the add bus data, the operation in the table below occurs: address bit symbol description action for timing modes addz fbtoz add bus drop bus external 0 0 add bus data forced to hi-z state. add =1. add bus data is forced to its hi-z state. aspe, aclk, ac1j1 forced to 0. add =1. add bus data is forced to its hi-z state. aspe, aclk, ac1j1 forced to 0. add =1. 0 1 add bus data forced to 0 state. add =0. add bus data is forced to 0 state. aspe, ac1j1, aclk, add are forced to 0 state. add bus data is forced to 0 state. aspe, ac1j1, aclk, add are forced to 0 state. 1 0 add bus data is forced to hi-z state. add =1. add bus data is forced to hi-z state. aspe, aclk, ac1j1 forced to 0. add =1. add bus data is forced to hi-z state. aspe, aclk, ac1j1 forced to 0. add =1. 1 1 add bus data and add are forced to the 0 state. add bus data is forced to 0 state. aclk, aspe, ac1j1, and add are forced to 0. add bus data is forced to 0 state. aclk, aspe, ac1j1, and add are forced to 0. - 69 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 11 7 pslen path signal label alarm enable: a 1 enables a 140 mbit/s receive line ais, and path rdi to be generated and sent when a c2 mismatch alarm (plserr) or unequipped (c2eq0) alarm occurs. 6 rdien far end receive failure enable: a 1 enables the internal alarms to determine the state of the transmitted rdi bit, while a 0 disables the internal alarms from controlling the state of the rdi bit. when written with a 0, the microprocessor must write the state of the rdi bit by writing a 1 or 0 to control bit trdi or bit 3 in the g1 poh byte register location 7ah. the following table is a summary of the various conditions that generates an rdi. - external g1 byte, when exg1 is a 1 - rdien is a 1 and ring and exg1 are 0: - dbloc alarm=1 and dropt pin is low -low on exais (pin 17) - e1 byte ais indication, when eape is a 0 - high on istat (pin 37), when eape is a 1 - high on pais (pin 38), when eape is a 1 - high on stai (pin 39), when xrdien is a 1 - drop bus loss of j1 alarm (dbloj1) when pten (pin 2) is low - path signal label mismatch (pslerr), when pslen is a 1 - unequipped status (c2eq0), when pslen is a 1 - j1 loss of lock (j1lol), when j1len is a 1 - j1 trace message mismatch (j1tim), when j1ten is a 1 - loss of pointer (rlop), when pten (pin 2) is high - path ais (rpais), when pten (pin 2) is high. - ring and rdien are a 1, and exg1 is 0: - rdi status via alarm indication port (no aiploc alarm). -rdien and exg1 are 0: - bit 3 in 6ah is a 1 (transmit g1 byte in ram). - trdi is a 1. 5 trdi transmit rdi: a 1 generates an rdi (bit 5 in the transmit g1 byte is set to 1) when control bit rdien bit is 0. this bit is orred with the micropro- cessor-written ram g1 value for rdi (bit 3) in location 6ah. 4 febeen far end block error enable: a 1 enables the received b3 value to gen- erate the transmitted febe count. a 0 enables a microprocessor-written value (bits 7 - 4 in register location 6ah) to be transmitted as the febe count. the febe count is sent under the following conditions: - via external g1 byte, when exg1 is a 1. - microprocessor-written value in bits 7-4 in 6ah, when febeen is a 0. - received b3 bip-8 errors, when febeen is a 1, and ring and exg1 are 0. - received b3 bip-8 errors via alarm indication port, when febeen and ring are 1, and exg1 is 0. address bit symbol description - 70 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 11 3 eape external alarm pin enable: a 1 enables the external istat (pin 37) and pais (38) pins to function in place of the e1 byte ais detection cir- cuit (out of band ais indication). a 0 disables the external alarm pins and enables the e1 byte ais detection circuit (in band ais indication). the e1 byte may be used to carry an in band upstream ais indication. the e1 byte ais detection circuitry uses majority logic to determine if the byte is carrying an ais indication. 2 raisen receive line ais enable: a 1 enables internal (and external) alarms to generate a receive 140 mbit/s line ais. a 0 disables the ability of the internal alarms to generate a 140 mbit/s line ais. the following table is a summary of the various conditions that generates a 140 mbit/s line ais, and provides an ais indication (pin 24). -raisen is a 1: -low on exais (pin 17) - e1 byte ais indication, when eape is a 0 - high on istat (pin 37), when eape is a 1 - high on pais (pin 38), when eape is a 1 - drop bus loss of j1 alarm (dbloj1) when pten (pin 2) is low - drop bus loss of clock (dbloc), when bsaise is a 0 - path signal label mismatch (pslerr), when pslen is a 1 - unequipped status (c2eq0), when pslen is a 1 - j1 loss of lock (j1lol), when j1len is a 1 - j1 trace message mismatch (j1tim), when j1ten is a 1 - loss of pointer (rlop), when pten (pin 2) is high - path ais (rpais), when pten (pin 2) is high. -raisen is a 0: - the microprocessor writes a 1 to raisg. note. the microprocessor may write to control bit raisg at any time to generate a line ais. however, writing a 0 to raisen pre- vents contention between the internal alarms and the micropro- cessor for generation of line ais. - receive loss of line frame alignment (rlof), when lfaise is a 1 and bsaise is a 0. 1raisg generate receive ais: a 1 causes a receive 140 mbit/s line ais to be generated independent of the internal alarms. note: the microprocessor may write to control bit raisg at any time for generating a line ais. however, writing a 0 to raisen prevents contention between the inter- nal alarms and the microprocessor for generation of line ais. 0rinvc receive invert line clock: byte- or nibble-wide data is clocked out of the l4m on negative transitions of the clock (rxco) when this bit is a 0. a 1 enables the byte or nibble line signal to be clocked out of the l4m on positive transitions of the clock. address bit symbol description - 71 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 12 7 exz5 transmit external z5 byte: a 1 enables the z5 byte from the external poh interface to be transmitted. a 0 enables the microprocessor-written value in register location 6fh to be transmitted. 6exz4 transmit external z4 byte: a 1 enables the z4 byte from the external poh interface to be transmitted. a 0 enables the microprocessor-written value in register location 6eh to be transmitted. 5exz3 transmit external z3 byte: a 1 enables the z3 byte from the external poh interface to be transmitted. a 0 enables the microprocessor-written value in register location 6dh to be transmitted. 4exh4 transmit external h4 byte: a 1 enables the h4 byte from the external poh interface to be transmitted. a 0 enables the microprocessor-written value in register location 6ch to be transmitted. 3exf2 transmit external f2 byte: a 1 enables the f2 byte from the external poh interface to be transmitted. a 0 enables the microprocessor-written value in register location 6bh to be transmitted. 2exg1 transmit external g1 byte: a 1 enables the g1 byte from the external poh interface to be transmitted. a 0 selects the states of the g1 byte to be written by internal logic, or by the microprocessor, as enabled. 1exc2 transmit external c2 byte: a 1 enables the c2 byte from the external poh interface to be transmitted. a 0 enables the microprocessor-written value in register location 69h to be transmitted. 0exj1 transmit external j1 byte: a 1enables the j1 byte from the external poh interface to be transmitted. a 0 enables the microprocessor-written value to be transmitted. 13 7 j1com j1 message comparison mode: works in conjunction with the ccitt control bit according to the following table: ccitt j1com action 0 x transmit and receive j1 memory segments are configured for 64 bytes. incoming messages are written in a rotating fashion with no defined start- ing address. 1 0 transmit and receive j1 memory segments are configured for 16 bytes. incoming messages are written in a rotating fashion with no defined start- ing address. 1 1 transmit and receive j1 memory segments are configured for 16 bytes. j1 incoming message comparison feature enabled. the microprocessor writes the expected 16-byte message into ram. after multiframe alignment is established, the j1 bytes in the message are compared against the microprocessor-written bytes, located in register location f0 to ffh. 6 ccitt j1 memory size: a 1 dimensions the transmit and receive memory seg- ment size to 16 bytes, while a 0 dimensions the memory segment to 64 bytes. address bit symbol description - 72 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 13 5 tuneq transmit unequipped status: this bit works in conjunction with control bit poheuq for generating an unequipped channel. the path overhead byte enable feature must be enabled (pohdis lead is high). tuneq poheuq action 0 x normal operation 1 0 unequipped channel. poh and payload bytes are transmitted as 0. 1 1 supervisory unequipped channel. poh bytes enabled. payload bytes transmitted as 0. 4 pohram path overhead bytes to ram : a 1 enables the transmit poh bytes (e.g. exh4 is equal to 1) from the external poh interface to be written into ram prior to transmission. a 0 still enables selected external inter- face poh bytes to be transmitted, but the ram locations are not written with the value of the external poh byte. instead, the ram locations will hold the microprocessor-written values. 3lhz force receive line to high impedance: a 1 forces the receive byte or nibble data (rxdn), and line output clock (rxco) to a high impedance state, until this bit is written with a 0. this bit is set to 1 after a device reset. 2llbk line loopback: a 1 written into this location enables the received line signal to be looped back as the transmit line signal. the received data and clock are provided at either the byte or nibble receive line interfaces. 1slbk sdh/sonet loopback: a 1 written into this location enables a vc-4/ spe loopback. this feature is not valid when the pten pin is set to 1. 0cor non-saturating performance counters enable: a 1 enables the per- formance counters to be non-saturating with roll over capability. a 0 causes all performance counters to be saturating, stopping at their max- imum value, with clear on read capability. 14 7 eaisen external loss of signal ais enable: a 1 enables a 140 mbit/s ais to be transmitted when a low is applied to exlos (pin 85). a 0 disables an external loss of signal indication from transmitting an ais. 6tcaisen transmit loss of clock ais enable: a 1 enables the l4m to send a 140 mbit/s ais when a transmit loss of clock alarm (tloc) is detected. a 0 disables a transmit loss of clock alarm (tloc) from transmitting an ais. address bit symbol description - 73 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 14 5 tohout transport overhead bytes output enabled: a 1 enables the l4m to generate the three a1 and a2 framing bytes, the c1 byte, and the h1 and h2 bytes, according to the following table. this feature in enabled in the drop bus and external timing modes only. tohout upc1 svc4h action 0 x 0 no toh bytes. the spe starting location (starting with j1) equals 522 when drop or the external timing mode is selected. for add bus timing, the starting location is determined by the j1 pulse (ac1j1). 0 x 1 no toh bytes. the spe starting location (starting with j1) equals 0 when drop or the external timing mode is selected. for add bus timing, the starting location is determined by the j1 pulse (ac1j1). 1 0 0 a1, a2, c11, and h1/h2 byte generated. the c11 byte (first c1 byte) is fixed as 01h. the pointer value is equal to 522, the starting location of the spe. the generation of the toh bytes is disabled in the add bus timing mode. 1 0 1 a1, a2, c11, and h1/h2 byte generated. the c11 byte (first c1 byte) is fixed as 01h. the pointer value is equal to 0, the starting location of the spe. the genera- tion of the toh bytes is disabled in the add bus timing mode. 1 1 0 a1, a2, c11, and h1/h2 byte generated. the c11 byte (first c1 byte) is the micro- processor-written value (location 1eh). the pointer value is equal to 522, the starting location of the spe. the genera- tion of the toh bytes is disabled in the add bus timing mode. 1 1 1 a1, a2, c11, and h1/h2 byte generated. the c11 byte (first c1 byte) is the micro- processor-written value (location 1eh). the pointer value is equal to 0, the start- ing location of the spe. the generation of the toh bytes is disabled in the add bus timing mode. 4j1len j1 loss of lock alarm action enable: a 1 enables the l4m to gener- ate a receive 140 mbit/s ais (when ais is enabled; raisen is a 1), and path rdi is enabled and the l4m is not in a path protection ring configu- ration (when rdien is a 1 and ring is 0) when a j1 loss of lock is detected. address bit symbol description - 74 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 14 3 j1ten j1 trace identifier mismatch alarm action enable: a 1 enables the l4m to generate a receive 140 mbit/s ais (when ais is enabled; raisen is a 1), and path rdi is enabled and the l4m is not in a path protection ring configuration (when rdien is a 1 and ring is 0) when a j1 a trace identifier mismatch is detected. 2tgen transmit test generator enable: a 1 enables the transmit 2 23 -1 test pseudo random generator. the transmit clock signal (txc) must be present. byte or nibble interface data is disabled. 1anaen test analyzer enable: a 1 enables the 2 23 -1 pseudo random test ana- lyzer. the test analyzer samples the receive data. errors are counted in a 16-bit performance counter after alignment is established. 0 svc4h start transmit vc-4 after h3 byte: this feature is operational in the drop timing and external timing modes only. a 1 enables the vc-4 (start- ing with the j1 byte) to start after the h3 byte. the h1/h2 pointer value is set to 0 when the toh feature is enabled (tohout is a 1). a 0 enables the vc-4 to start after the c1 byte with a pointer value equal to 522. in the add bus timing mode, an add bus j1 pulse (in ac1j1) deter- mines the starting location of the spe. 15 7 lfaise loss of frame ais enable: a common control bit for both the receive and transmit performance monitoring circuits. a 1 enables a receive or transmit loss of frame alarm to generate a receive or transmit 140 mbit/s ais. the generation of ais in the receive direction is disabled when the bit stuffing ais feature is enabled (bsaise is a 1). a 0 disables a loss of frame alarm from generating ais. 6fdaen frame alignment ais enable: a 1 enables frame alignment to work in conjunction with the ais detector. the ais detection occurs when ais is detected and loss of frame has occurred. ais recovery occurs when frame alignment occurs or the ais condition goes away. a 0 disables the frame alignment from working with the ais detection circuit, that is, ais can be declared even if a loss of frame condition is not present. 5 tpssel transmit pointer s-bit select: enabled when control bit tohout is a 1 in the drop bus and external timing modes. a 1 permits the micropro- cessor to write the value of the transmit s-bits in the h11, h12, and h13 bytes. a 0, forces the s-bits in h11 to be sent as 10, and the s-bits in h12 and h13 to be sent as 00. see register 1dh. 4rpsds receive pointer s-bit disabled: enabled when pten (pin 2) is high enabling the pointer tracking machine. this bit also works in conjunction with the rpssel bit according to the following table. rpsds rpssel action 0 0 pointer byte h11 s-bits are checked in pointer tracking machine against the value 10. 0 1 pointer byte h11 s-bits are checked in pointer tracking machine against a microprocessor-writ- ten value in bits 1 and 0 in 1dh. 1 x the s-bit check is disabled in the pointer tracking machine. address bit symbol description - 75 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 15 3 rpssel receive pointer s-bit select: enabled when pten (pin 2) is high enabling the pointer tracking machine. this bit works in conjunction with the rpsds bit according to the table given above. 2fbtoz force unused bytes to zero: a 1 forces the unused toh bytes and poh bytes (when disabled) to 0. a 0 forces the unused bytes to a high impedance state. 1c2fvd c2 fixed value disabled: a 1 disables the comparison of the received c2 byte against the fixed hardware value of 01h in the c2 mismatch detection circuit. the c2 mismatch comparison is performed against the microprocessor-written value only. 0upc1 microprocessor writes c1 value: enabled when control bit tohout is a 1 in the drop bus and external timing modes. a 1 enables the micro- processor to write the value of the transmitted c1 byte. a 0 generates the value of 01h for the transmitted c1 byte. 16 17 7-4 7-0 transmit c1 offset transmit c1 offset register: enabled in the external timing mode only, when a high is placed on enabt (pin 36), and when control bit tc1dc is a 1. the 12-bit register location compensates for the position of the c1 pulse in the exc1 signal (pin 105). the lsb is bit 0 in 17h, and the msb is bit 7 in 16h. the register compensates for up to 2429 (270 columns x 9 rows - 1). for example, if the c1 pulse is in the correct position, zeros are written to the register. the correct position of the framing reference is when c1 corresponds to the c11 position in the sdh/sonet format. when a binary 1 is written to the register (bit 0 in 17h is a 1), it is assumed that the position of the c1 pulse present in the exc1 signal is shifted in time one byte and the input pulse corresponds to the c12 byte position in the sdh/sonet frame. this means that the starting point for the frame should be one byte earlier. values written into the register greater than a binary value of 2429 will be counted as zero delay. 16 3 tc1dc transmit c1 delay control: enabled in the external timing mode only, when a high is placed on enabt (pin 36). a 1 enables the transmit 12-bit c1 offset register in locations 16h and 17h to compensate for a c1 offset delay in the transmit direction. 0paisg path ais generator enable: a 1 causes path ais to be generated in the transmit direction. the transmitted payload and poh bytes are forced to the 1 state (if pohdis =1), in addition to the toh bytes (when enabled). address bit symbol description - 76 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 18 19 7-4 7-0 receive c1 offset receive c1 offset register: enabled when a high is placed on the pointer tracking machine control lead pten (pin 2), and when control bit rc1dc is a 1. the 12-bit register location compensates the position of the c1 pulse in the dc1j1 or dc1 signal (pin 127, 126). the lsb is bit 0 in 19h, and the msb is bit 7 in 18h. the register compensates for up to 2429 (270 columns x 9 rows - 1). for example, if the c1 pulse is in the correct position, zeros are written to the register. the correct position of the framing reference is when c1 corresponds to the c11 position in the sdh/sonet format. when a binary 1 is written to the register (bit 0 in 19h is a 1), it is assumed that the position of the c1 pulse present in the dc1 signal is shifted in time one byte and the input pulse corresponds to the c12 byte position in the sdh/sonet frame. this means that the starting point for the frame should be one byte earlier. values written into the register greater than a binary value of 2429 will be counted as zero delay. 18 3 rc1dc receive c1 delay control: enabled when the pointer tacking machine is selected, when a high is placed on pten (pin 2). a 1 enables the receive 12-bit register in locations 18 and 19h to compensate for a c1 offset delay in the receive direction. 2rdi10 rdi/ferf recovery/detection 10 consecutive enable: a 1 selects 10 consecutive events as the value for detection and recovery. a 0 selects 5 consecutive events as the value for detection and recovery. 1pads pointer tracking machine ais to lop transition disabled: a 1 dis- ables the ais to lop transition in the pointer tracking state machine. a 0 enables the ais to lop transition in the pointer tracking machine. 0 febebc febe block count enable: a 1 enables the febe counter to be con- figured to count febe blocks instead of febes. a valid count (between 1 and 8) will increment the 16-bit counter once. a 0 configures the febe counter to count febes. 1a 1b 7-0 7-1 pointer leak rate register fifo leak rate register: the 15-bit value written into registers 1a and 1bh is used for presetting the internal pointer leak counter. the value written into this register is based on the rate of occurrence of pointer movements from the number of counts read from positive/negative stuff counters, and the nj/pj indication pins. this count will represent the average leak rate. a count of 1 will decrement the pointer leak counter every three rows. thus the minimum time to leak out one pointer move- ment is 8 frames or 1 millisecond, since each pointer movement is 24 bits. bit 7 in register 1bh is assigned as the msb, and represents bit 15 in the string, as shown below: | register 1b | register 1a | bit 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0 a pin (pleq0) is provided that will give a positive indication when the pointer leak counter is equal to zero. this indication is reset to zero when the pointer leak counter is preset. register 1ah is preset to 01h after a device reset. address bit symbol description - 77 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 1b 0 loaden load enable: used for desynchronizer operation. the internal pointer leak counter shall be preset with the 15-bit leak rate value using the fol- lowing steps: 1. write the value to the seven upper bits (with 7 being the msb), and a 0 to this bit. 2. write the 8-bit value into the lower register (1a). 3. write a 1 to this bit, or write the seven upper bits in this register, along with a 1 to this bit. the internal counter will preset with the 15-bit value on the 0 to 1 transition. this bit is set to 1 after a device reset. 1c 7 resetc reset counters : a 1 causes the performance counters to reset. when the reset is completed, this bit is self clearing and this bit position becomes a 0. 6 resetd reset mapper: a 1 resets the mapper. the mapper will remain reset until the processor writes a 0 into this location. 5resets reset desynchronizer: a 1 resets the two fifos in the desynchronizer to mid-range values. 2pardo parity data byte only: a common bit for both the drop and add buses, and valid for all timing modes. a 1 enables parity to be calculated for data bytes only. a 0 enables parity to be calculated for the add bus out- put signals, and drop bus input signals. 1ac1en add bus c1 pulse enable: a 1 enables the c1 pulse to be transmitted as a separate signal instead of in the ac1j1 signal in the external and drop timing modes. a 0 enables the ac1j1 signal to carry both the c1 and j1 signals. in the add bus timing mode, the c1 signal can be applied on the ac1 pin instead of in the c1j1 signal independent of the state of this bit. 0 bsaise bit stuffing ais enable: a 1 causes an internal bit stuffing implementa- tion to be used for the transmit and receive 140 mbit/s line ais genera- tion instead of using the external ais clock. this bit is set to 0 upon power-up (selecting the external ais clock). when the bit stuffing ais feature is selected, the receive performance monitor circuit and ais detection circuits are disabled when receive ais is generated automati- cally by the l4m. please note that the loss of the drop bus clock will dis- able the generation of receive ais based on bit stuffing. address bit symbol description - 78 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 1d 7-0 s-bits p control pointer s-bit microprocessor-written values: the bits in this location are the microprocessor-written s-bits in the transmit pointer bytes, and the s-bits used in the receive pointer tracking machine. the transmit s-bits in this location are enabled when control bits tpssel and tohout are 1. in the receive direction, the s-bits in this location are enabled when control bit rpssel is 1 and rpsds is 0. the bits are defined as: bit 7 is the s-bit state in bit 5 in the transmitted h11 byte. bit 6 is the s-bit state in bit 6 in the transmitted h11 byte. bit 5 is the s-bit state in bit 5 in the transmitted h12 byte. bit 4 is the s-bit state in bit 6 in the transmitted h12 byte. bit 3 is the s-bit state in bit 5 in the transmitted h13 byte. bit 2 is the s-bit state in bit 6 in the transmitted h13 byte. bit 1 is the s-bit state used to compare bit 5 in the received h11 byte in the pointer state machine. bit 0 is the s-bit state used to compare bit 6 in the received h11 byte in the pointer state machine. 1e 7-0 c1 c1 microprocessor-written value: when control bits tohout and upc1 are equal to 1, the transmitted c1 value is the value written into this location by the microprocessor. when control bit tohout is a 1 and upc1 is a 0, a fixed value of 01h is transmitted, and this register location is disabled. 1f 0 pldinv phase-locked loop detector invert control bit: a 1 inverts the sense of one of the phase-locked loop internal phase detector ? s inputs. this bit should be set to 1 for normal operation. address bit symbol description - 79 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 status register bit descriptions the unlatched alarms are allocated to even numbered hexadecimal address locations, while the latched alarm bit positions are allocated to odd numbered register locations. a latched bit sets on the positive level of the alarm. a latched bit position clears on a microprocessor read cycle. if the alarm is active after the read cycle, the bit position will relatch. address bit symbol description 20 21 7 anool analyzer out of lock: when enabled, an alarm occurs when the 2 23 -1 analyzer is out of lock. an out of lock alarm occurs when 30 bits in a 1000 bits are received in error. in lock occurs when the first 24 bits in the pattern are received correctly. an out of lock disables the analyzer error 16-bit counter. this bit is forced to 0 when the anaen control bit is set to 0. 6tlaisd transmit line ais detected: an alarm occurs when a 140 mbit/s ais has been detected (all ones in the transmit bit stream). when control bit fdaen is a 0, an ais is detected when the incoming signal has five or less zeros in each of two consecutive frame periods (2928 bits per frame). recovery occurs when if each of two consecutive frame periods contains six or more zeros. when control bit fdaen is a 1, ais is detected when the incoming signal has five or less zeros in each of two consecutive frame periods, and a loss of frame alignment has been detected. recovery occurs when each of two consecutive frame periods contains six or more zeros, or frame align- ment has occurred. other than reporting the alarm, no action is taken. 5 tfifoe transmit fifo error detected: an alarm occurs when an overflow or underflow condition has taken place in the transmit fifo. the fifo recenters automatically after the fifo error. other than reporting the alarm, and recentering the fifo, no action is taken. 4abloj1 add bus loss of j1 : an alarm occurs when, in add bus timing mode, the j1 pulse in the ac1j1 signal is missing for 8 consecutive frames. recovery occurs when the j1 pulse in the ac1j1 signal is present for 8 consecutive frames. 3 laisc loss of ais clock: an alarm occurs when the ais input clock (aisck) is stuck high or low for 12-34 consecutive clock cycles of the ram clock (ramci). recovery occurs on the first clock transition. this clock is used to generate the 140 mbit/s line ais when control bit bsaise is a 0. 2 xais external ais indication: an indication occurs when an active low is present on the exais pin. when control bit raisen is a 1, a receive 140 mbit/s ais is generated, and a path rdi is generated when rdien=1. 1dbloj1 drop bus loss of j1: an alarm occurs when the j1 pulse in the dc1j1 sig- nal is missing for 8 consecutive frames. recovery occurs when the j1 pulse in the dc1j1 pulse is present for 8 consecutive frames. when the pointer tracking feature is enabled (pten is high), the detection of this alarm is dis- abled. 0e1ais ais detected in the e1 byte: an alarm occurs when a majority of all ones (5 out of 8 bits are a 1) has been detected in the incoming e1 byte once. recovery occurs when a majority of ones is not detected once. this provides a means of signaling the 140 mbit/s mapper that an upstream sdh/sonet loss of frame and other alarms have occurred. - 80 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 22 23 7 buserr received parity error detected: an alarm indicates that a parity error has been detected in the drop bus signals. the drop bus data, spe signal and composite c1j1 pulse are calculated for odd parity and compared against the parity bit input for parity errors when the pointer tracking feature is dis- abled (pten lead is low). the drop bus data, and c1 pulse is calculated for odd parity and compared against the parity bit input for parity errors when the pointer tracking feature is enabled (pten lead is high). when a 1 is writ- ten to control bit pardo, the parity calculation and comparison is for the data byte only regardless of the state of the pten lead. no other action is taken, other than the alarm indication. 6 rfifoe receive fifo error: an alarm occurs when the receive second stage fifo in the desynchronizer has either underflowed or overflowed. the fifo is recentered automatically. no other action is taken. 5 rrdi receive rdi alarm detected: an alarm occurs when a path rdi alarm has been detected in bit 5 of the received g1 byte. control bit rdi10 determines whether the consecutive event requirement for detection and recovery is 5 or 10. 4 pslerr path signal label mismatch detected: an alarm indicates that the received c2 byte did not match the microprocessor-written value in location 75h, nor did it match the internal 01h value (when control bit c2fvd is a 0) for 5 consecutive frames. recovery occurs when a match occurs in the c2 comparison byte (75h) or internal 01h value (when enabled), for 5 consecu- tive frames. when control bit c2fvd is a 1, the comparison against the inter- nal 01h value is disabled. this alarm is disabled if a c2 unequipped alarm occurs. 3c2eq0 c2 byte equal to zero: an alarm occurs when the received c2 byte is all zeros for 5 consecutive frames, indicating that the vc-4/spe is carrying an unequipped channel status (poh bytes and payload bytes are equal to zero). recovery occurs when the received c2 byte is not all zeros for 5 con- secutive frames. 2j1lol j1 loss of lock alarm: an alarm occurs when the alignment of the j1 trace identifier label (message) has not been established. the j1 detection circuit is enabled when control bits j1com and ccitt are a 1. the j1lol alarm will become momentarily active when the following alarms are exited: dbloj1 when pten pin is low; e1ais when eape bit is 0; xpais or xistat when eape bit is 1; rlop or rpais when pten pin is high. 1j1tim j1 trace identifier mismatch: an alarm indicates that the received stable 16-byte message did not match for one message time. recovery from this alarm occurs when the j1 state machine losses lock (j1lol) and then acquires lock with a 16-byte stable j1 message that matches the j1 compar- ison message in registers f0h to ffh. address bit symbol description - 81 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 22 23 0rlaisd receive line ais detected: the alarm detection is enabled when control bit bsaise is a 0 (bit stuffing ais disabled), or when bsaise=1 and the l4m is not generating a receive ais based upon received alarms. when control bit fdaen is a 0, a 140 mbit/s line ais is detected when the receive line sig- nal (after the desynchronizer) has five or less zeros in two consecutive frame periods. recovery occurs if each of the two consecutive frame periods has six or more zeros. when control bit fdaen is a 1, an alarm occurs when the receive line signal has five or less zeros in two consecutive periods, and loss of frame has occurred. recovery occurs if each of two consecutive frame periods has six or more zeros, or frame alignment has been detected. 24 25 7tloc transmit loss of clock: an alarm occurs when the transmit line clock (txc) is stuck high or low for 13-34 or more consecutive clock cycles of the ram clock (ramci). recovery occurs on the first clock transition. 6abloc add bus loss of clock: an alarm occurs when the add bus input clock (aclk) in the add bus timing mode is stuck high or low for 13-34 or more consecutive clock cycles of the ram clock (ramci). recovery occurs on the first clock transition. 5dbloc drop bus loss of clock: an alarm occurs when the drop bus input clock (dclk) is stuck high or low for 13-34 or more consecutive clock cycles of the ram clock (ramci). recovery occurs on the first clock transition. 4rloc receive line loss of clock: an alarm occurs when the receive line input clock (rxci) is stuck high or low for 12-35 or more consecutive clock cycles of the ram clock (ramci). recovery occurs on the first clock transition. 31sfou first stage fifo overflow or underflow: an alarm occurs when the 1st stage receive fifo in the desynchronizer has either underflowed or over- flowed. the fifo is recentered automatically. no other action is taken. the 1st stage fifo will overflow or underflow if the value in register 1ah and 1bh is too large, such that the pointer movements are not leaked out as fast as they are arriving. 2xstai sdh/sonet network alarm indication: an indication occurs when an active high is present on the stai pin. when control bits xrdien and rdien are set to 1, a path rdi is transmitted for the duration of the alarm. 1xistat external sdh/sonet alarm: an indication occurs when an active high is present on the istat pin. when control bit eape is a 1, path rdi is transmit- ted and a receive ais is generated for the duration of the alarm. 0xpais external path ais alarm: an indication occurs when an active high is present on the pais pin. when control bit eape is a 1, path rdi is transmit- ted and a receive ais is generated for the duration of the alarm. address bit symbol description - 82 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 26 7 sint software interrupt: a software interrupt indication occurs when one or more interrupt mask bit positions are written with a 1, and the corresponding alarms for those interrupt mask bits occur. the sint state is exited when the latched alarm causing the interrupt is cleared or the alarm ? s corresponding interrupt mask bit is written with a 0. 26 27 6extlos external transmit loss of signal alarm: an alarm occurs when a low is present on the exlos pin. when control bit eaisen is a 1, a transmit line ais is generated. 5aiploc alarm indication port loss of clock: an alarm occurs when the taipc clock (which is connected to the mate l4m) has been stuck high or low for 113-764 or more consecutive ram clock (ramci) periods. febe and rdi are transmitted as 0 in the g1 byte. recovery occurs on the first clock transi- tion. 2new new alarm: when the pointer tracking feature is disabled (pten pin is low), this alarm indicates that the j1 pulse has jumped more than three byte posi- tions or has made an illegal increment or decrement. when the pointer track- ing feature is enabled (pten pin is high), this alarm indicates that 3 x new pointers has been detected. 28 29 7tlof transmit 140 mbit/s loss of frame alarm: an alarm occurs when four consecutive errored frame alignment patterns (based on g.751) are detected. recovery occurs when three consecutive frame alignment pat- terns without errors are detected. 6rlof receive 140 mbit/s loss of frame alarm: an alarm occurs when four con- secutive frame alignment patterns (based on g.751) are detected incorrectly. recovery occurs when three consecutive frame alignment patterns are detected correctly. 5tdai transmit distant alarm indication: a 1 indicates that bit 13 in the transmit- ted 140 mbit/s g.751 format is a 1. this alarm is inhibited when loss of frame alignment ( tlof ), or when a transmit 140 mbit/s ais is detected, or when an errored transmit frame is detected (only for that particular errored frame). 4 rdai receive distant alarm indication: a 1 indicates that bit 13 in the received 140 mbit/s g.751 format is a 1. this alarm is inhibited on a loss of frame alignment (rlof), or when a receive 140 mbit/s ais is detected, or when an errored receive frame is detected (only for that particular errored frame). 3rlop receive loss of pointer alarm: enabled when the pointer tracking feature is enabled (pten lead is high). an alarm occurs when loss of pointer has been detected in the pointer tracking machine. 2 rpais receive path ais alarm: enabled when the pointer tracking feature is enabled (pten lead is high). an alarm occurs when path ais has been detected in the h1 and h2 bytes. address bit symbol description - 83 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 interrupt mask bit definitions the interrupt mask bits work in conjunction with the latched bit positions to provide a hardware and global soft- ware interrupt indication. writing a 1 to one or more mask bits, when the corresponding alarm occurs, will cause the global software interrupt (sint, address 26h, bit 7) to occur, and will cause a hardware interrupt to occur by setting the hint control bit (address 33h, bit 7) to 1. the hardware interrupt pin will be turned off when the latched alarm bit causing the interrupt is cleared, or when the corresponding interrupt mask bit is set to 0, or the hint bit is set to 0. the bit positions in the mask bit segment locations correspond to the bit posi- tions in the status register segment locations. address bit symbol description 30 7 anool analyzer out of lock 6 tlaisd transmit line 140 mbit/s ais detected 5 tfifoe transmit fifo error (underflowed or overflowed) 4 abloj1 add bus loss of j1 3 laisc loss of ais clock 2 xais external ais generate signal on exais pin 1 dbloj1 drop bus loss of j1 0 e1ais ais detected in the e1 byte (transport overhead) 31 7 buserr drop bus parity error 6 rfifoe receive fifo error (underflowed or overflowed) 5 rrdi receive rdi/ferf (bit 5 in g1) 4 pslerr path signal label error 3 c2eq0 unequipped c2 status (00h) 2 j1lol j1 loss of lock (alignment unstable) 1 j1tim j1 trace identifier mismatch 0 rlaisd receive line ais detected 32 7 tloc transmit line loss of clock 6 abloc add bus loss of clock 5 dbloc drop bus loss of clock 4 rloc receive line loss of clock 2 xstai external network alarm 1 xistat external sts alarm 0 xpais external path ais alarm 33 7 hint hardware interrupt enable 6 extlos external loss of signal alarm 5 aiploc alarm indication port loss of clock alarm 2 new 3 consecutive new pointers received - 84 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 transmit poh register descriptions the transmission of the poh byte in the add direction, and the processing of the poh bytes in the drop direc- tion are enabled when a high is placed on the pohdis lead. 34 7 tlof transmit 140 mbit/s loss of frame alarm 6 rlof receive 140 mbit/s loss of frame alarm 5 tdai transmit 140 mbit/s distant alarm indication 4 rdai receive 140 mbit/s distant alarm indication 3 rlop receive loss of pointer 2 rpais receive path ais address bit symbol description 68 7-0 b3 error mask b3 error mask and test byte: when control bit testb3 is written with a 0, a 1 written to any of the bit locations will generate a continuous bit error in the corresponding b3 bit position. internally, this ram location is exclusive- or gated with the calculated b3 byte prior to transmission. the b3 errors are transmitted until this location is rewritten with a 00h. bit 7 in this location cor- responds to bit 1 in the transmitted b3 byte. when control bit testb3 is writ- ten with a 1, the bits written into this location are transmitted as the b3 byte. 69 7-0 c2 signal label c2 signal label byte: when control bit exc2 is a 0, the bits written into this location are transmitted as the c2 byte. when control bits exc2 and pohram are a 1, the external poh interface c2 byte is written into this location, and is also transmitted. when control bit exc2 is a 1, and pohram is a 0, the external poh interface c2 byte is transmitted and this location holds the microprocessor-written c2 value. bit 7 in this location cor- responds to bit 1 in the transmitted c2 byte. 6a 7-0 transmit g1 byte transmit g1 byte: bits 7-0 provide the states of the external poh byte or microprocessor-written values, according to the following: 1 2 3 4 5 6 7 8 g1 byte 7 6 5 4 3 2 1 0 this location febe rdi unassigned when control bits exg1, rdien, and febeen are 0, the microprocessor writes the transmitted febe state and path rdi state. the unassigned bits are always written by the microprocessor unless exg1 is a 1. when control bits exg1 and pohram are a 1, the external poh interface g1 byte is writ- ten into this location, and is also transmitted. when control bit exg1 is a 1, and pohram is a 0, the external poh interface g1 byte is transmitted and this location holds the microprocessor-written g1 value. the unassigned bits for transmission must always be written into bits 2 through 0 in this location, otherwise the transmitted states of these bits are undetermined. see also febeen, rdien and ring control bits. address bit symbol description - 85 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 6b 7-0 f2 user channel: when control bit exf2 is a 0, the bits written into this loca- tion are transmitted as the f2 byte. when control bits exf2 and pohram are a 1, the external poh interface f2 byte is written into this location, and is also transmitted. when control bit exf2 is a 1, and pohram is a 0, the external poh interface f2 byte is transmitted and this location holds the microprocessor-written f2 value. bit 7 in this location corresponds to bit 1 in the transmitted f2 byte. 6c 7-0 h4 h4 byte: when control bit exh4 is a 0, the bits written into this location are transmitted as the h4 byte. when control bits exh4 and pohram are a 1, the external poh interface h4 byte is written into this location, and is also transmitted. when control bit exh4 is a 1, and pohram is a 0, the external poh interface h4 byte is transmitted and this location holds the micropro- cessor-written h4 value. bit 7 in this location corresponds to bit 1 in the transmitted h4 byte. 6d 7-0 z3 z3 byte: when control bit exz3 is a 0, the bits written into this location are transmitted as the z3 byte. when control bits exz3 and pohram are a 1, the external poh interface z3 byte is written into this location, and is also transmitted. when control bit exz3 is a 1, and pohram is a 0, the external poh interface z3 byte is transmitted and this location holds the microproces- sor-written z3 value. bit 7 in this location corresponds to bit 1 in the transmit- ted z3 byte. 6e 7-0 z4 z4 byte: when control bit exz4 is a 0, the bits written into this location are transmitted as the z4 byte. when control bits exz4 and pohram are a 1, the external poh interface z4 byte is written into this location, and is also transmitted. when control bit exz4 is a 1, and pohram is a 0, the external poh interface z4 byte is transmitted and this location holds the microproces- sor-written z4 value. bit 7 in this location corresponds to bit 1 in the transmit- ted z4 byte. 6f 7-0 z5 z5 byte: when control bit exz5 is a 0, the bits written into this location are transmitted as the z5 byte. when control bits exz5 and pohram are a 1, the external poh interface z5 byte is written into this location, and is also transmitted. when control bit exz5 is a 1, and pohram is a 0, the external poh interface z5 byte is transmitted and this location holds the microproces- sor-written z5 value. bit 7 in this location corresponds to bit 1 in the transmit- ted z5 byte. 80 to bf 7-0 j1 path trace message: the bytes written into this memory segment (16 or 64 bytes determined by the ccitt control bit) will provide a repetitive 64-or 16- byte fixed length message for transmission. the 16-byte message is allocated to the 80 to 8fh segment. the remaining segment 90 to bfh is not used. the starting address is not set for transmission. the message is transmitted in a rotating fashion. when control bit exj1 is a 0, the bits written into these locations are transmitted as the j1 byte stream. when control bits exj1 and pohram are a 1, the external poh interface j1 bytes are written into these locations, and are also transmitted. when control bit exj1 is a 1, and pohram is a 0, the external poh interface j1 bytes are transmitted and this location holds the microprocessor-written j1 values. bit 7 in this location corresponds to bit 1 in the transmitted j1 byte. address bit symbol description - 86 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 receive poh register descriptions the transmission of the poh byte in the add direction, and the processing of the poh bytes in the drop direc- tion is enabled when a high is placed on the pohdis lead. address bit symbol description 75 7-0 c2 compare byte c2 path signal label compare byte: the bits in this location are written by the microprocessor and are compared against the received c2 value for path signal label mismatch detection. bit 7 in this location corresponds to bit 1 in the c2 byte. 78 7-0 b3 byte b3 received byte: this location contains the received b3 parity byte value received each frame. bit errors are counted in a 16-bit counter located at 40h (low order byte) and 41h (high order byte). block errors (one or more parity errors) are counted in an 8-bit counter located at 4ah. bit 7 in this location corresponds to bit 1 in the b3 byte. 79 7-0 c2 received signal label c2 received signal label byte: this location is the received c2 byte value received each frame. the received c2 byte is compared against the micro- processor-written value in location 75h. bit 7 in this location corresponds to bit 1 in the c2 byte. 7a 7-0 received g1 byte received g1 byte: this location is the received g1 byte value received each frame. the bit relationship is the following. 1 2 3 4 5 6 7 8 g1 byte 7 6 5 4 3 2 1 0 this location febe rdi unassigned 7b 7-0 f2 f2 received byte: this location is the received f2 byte value received each frame. bit 7 in this location corresponds to bit 1 in the f2 byte. 7c 7-0 h4 h4 received byte: this location is the received h4 byte value received each frame. bit 7 in this location corresponds to bit 1 in the h4 byte. 7d 7-0 z3 z3 received byte: this location is the received z3 byte value received each frame. bit 7 in this location corresponds to bit 1 in the z3 byte. 7e 7-0 z4 z4 received byte: this location is the received z4 byte value received each frame. bit 7 in this location corresponds to bit 1 in the z4 byte. 7f 7-0 z5 z5 received byte: this location is the received z5 byte value received each frame. bit 7 in this location corresponds to bit 1 in the z5 byte. c0 to ff 7-0 received j1 message path trace message microprocessor read feature: the received j1 mes- sage bytes are stored into this memory segment. the 16-byte message is allocated to the c0h to cfh memory segment, when control bit ccitt is a 1. when ccitt is 0, the memory segment is configured for 64 bytes. the incoming message is written in with no specific starting address, and in a rotating fashion, and any incoming j1 byte is written into the next sequential ram location. however, when ccitt and j1com are both set to 1 and the received 16-byte j1 message has a valid multiframe alignment pattern and is stable (j1lol=0), the bits written into c0h-cfh will be aligned such that the j1 byte with the start of multiframe indication will be in location c0h. the values in c0h to cfh will be the ? debounced ? stable message. - 87 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 performance counters descriptions all performance counters globally can be configured to be either saturating or non-saturating with a roll over in count. writing a 1 to control bit cor (bit 0 in register location 13h) conditions all counters to be non-saturating. reading a non-saturating counter will not clear the counter. when the counters are configured to be saturating, the counter will clear on a microprocessor read cycle. all performance counters are cleared simultaneously when a 1 is written to control bit rsetc. this bit is self clearing and does not require a 0 to be written to it. when reading a 16-bit counter, the low order byte must be read first. f0 to ff 7-0 compare j1 message path trace message compare feature: the microprocessor writes into this 16-byte memory segment the expected j1 message (multiframe bits and crc as required) when ccitt is 1 and j1com is 1. this message is then compared against the received j1 byte for the correct message. the starting address of the message must be written to location f0h (multiframe value of 1). the l4m performs the alignment of the incoming message against this message segment. address bit symbol description 40 41 7-0 b3 counter b3 byte parity error 16-bit counter : counts the number of b3 bip-8 parity error indications that have been detected between the received b3 value and the calculated value. the low order counter value is held in location 40h. the high order counter value is in held in location 41h. bit 0 in 40h is the lsb. 42 43 7-0 febe counter far end block error 16-bit counter: when control bit febebc is a 0, this counter counts the number of febe error count indications received in bits 1 through 4 of the g1 byte. the maximum number of errors counted per frame is 8. values other than between 1 thru 8 are counted as 0 errors. the low order counter value is held in location 42h. the high order counter value is in held in location 43h. when control bit febebc is a 1, the number of febe blocks in error are counted instead of the febe count. bit 0 in 42h is the lsb. 44 45 7-0 analyzer counter analyzer 16-bit error counter: enabled when control bit anaen is a 1, and when the analyzer is in lock. counts the number of errors received in the received 2 23 -1 prbs pattern. the low order counter value is held in location 44h. the high order counter value is in held in location 45h. bit 0 in 44h is the lsb. 46 47 7-0 transmit framing error counter transmit 140 mbit/s framing pattern 16-bit error counter: after frame alignment, this counter counts the number of transmit errored framing pat- terns in the g.751 signal. the low order counter value is held in location 46h. the high order counter value is in held in location 47h. bit 0 in 46h is the lsb. 48 49 7-0 receive framing error counter receive 140 mbit/s framing pattern 16-bit error counter: enabled when control bit bsaise is a 0 or when bsaise is 1 and the l4m is not generating a receive ais. after frame alignment, this counter counts the number of received errored framing patterns in the g.751 signal. the low order counter value is held in location 48h. the high order counter value is in held in location 47h. bit 0 in 48h is the lsb. address bit symbol description - 88 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 4a 7-0 b3 block counter b3 8-bit block error counter: counts the number of b3 blocks that are received in error. bit 0 is the lsb. 4b 7-0 positive justification counter positive justification 8-bit counter: counts the number of positive justi- fications based on the incoming j1 pulse. when the pointer tracking fea- ture is enabled, counts the number of pointer increments. bit 0 is the lsb. 4c 7-0 negative justification counter negative justification 8-bit counter: counts the number of negative justifications based on the incoming j1 pulse. when the pointer tracking feature is enabled, counts the number of pointer decrements. bit 0 is the lsb. 4d 7-0 ndf counter new data flag 8-bit counter. enabled when a high is placed on pten (pin2), the pointer tracking feature. counts the number of received ndf (1001, 0001, 1101, 1011, and 1000) detected in bits 1-4 of h11. this counter does not count the ndf in the ais to ndf state transition of the pointer tracking state machine. 4e 4f 7-0 1-0 desyn pointer offset counter desynchronizer pointer offset counter: a 9-bit counter, plus a sign bit, that provides the count of the internal pointer offset counter (i.e., pointer leak buffer offset counter, which is the number of bits that have to be leaked out if the sign bit is 0, or the number of leak times not to leak out a bit if the sign bit is 1) for a microprocessor read cycle, when required. the msb bit is located in bit 0 in 4fh, followed by bit 7 in 4eh. the sign bit is located in bit 1 in 4fh. the value provided is in the 2's complement form, with a zero value equal to 0. this counter can be used in setting the flr registers. further information on this subject is provided in a transwitch application note, document number txc-03456-0001-an, ed. 1, february 7, 1995. address bit symbol description - 89 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 package information the l4m device is packaged in a 144-pin plastic quad flat package (pqfp) suitable for socket or surface mounting, as illustrated in figure 28. figure 28. l4m txc-03456 144-pin plastic quad flat package 108 73 72 37 36 1 144 109 pin #1 index 22.75 (sq) 28.00 (sq) 31.20 (sq) 0.65(typ) 0.22(min) 0.38(max) 4.07 (max) 0.25 (min) 3.42 see detail ? a ? 0.16 typ. 0.80 typ. 0 -7 degrees typ. detail ? a ? see details ? b ? and ? c ? detail ? b ? detail ? c ? (typ) notes: 1. all linear dimensions are in millimeters. 2. all dimensions are nominal unless otherwise indicated. 3. falls within jedec mo-108. transwitch TXC-03456AIPQ - 90 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 ordering information part number: TXC-03456AIPQ 144-pin plastic quad flat package related products txc-02302b, syn155c vlsi device (155-mbit/s synchronizer, clock and data output). this device is similar to the syn155. it has both clock and data outputs on the line side. txc-03003b, sot-3 vlsi device (stm-1/sts-3/sts-3c overhead terminator). this is a dual-mode device, which can be configured either to emulate the txc-03003 device or to provide additional capabilities. - 91 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: 212-642-4900 11 west 42nd street fax: 212-302-1286 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 2570 west el camino real tel: 650-949-6700 suite 304 fax: 650-949-6705 mountain view, ca 94040 web: www.atmforum.org atm forum europe office av. de tervueren 402 tel: 2 761 66 77 1150 brussels fax: 2 761 66 79 belgium web: www.euroinfo@atmforum.ocm atm forum asia-pacific office hamamatsucho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsucho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan web: www.apinfo@atmforum.com bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: 800-854-7179 (within u.s.a.) global engineering documents tel: 314-726-0444 (outside u.s.a.) 7730 carondelet avenue, suite 407 fax: 314-726-6418 clayton, mo 63105-3329 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 22 650 route des lucioles fax: 4 92 94 43 33 06921 sophia antipolis cedex web: www.etsi.org france - 92 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: 800-669-6857 (within u.s.a.) tel: 903-769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: 508-650-1375 washington, dc 20007 web: www.mvip.org itu-t (international): publication services of international telecommunication union tel: 22 730 5111 telecommunication standardization sector fax: 22 733 7256 place des nations, ch 1211 web: www.itu.int geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: 215-697-2179 building 4 / section d fax: 215-697-1462 700 robbins avenue web: www.dodssp.daps.mil philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: 800-433-5177 (within u.s.a.) 2575 ne kathryn street #17 tel: 503-693-6232 (outside u.s.a.) hillsboro, or 97124 fax: 503-693-8344 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: 800-521-core (within u.s.a.) attention - customer service tel: 908-699-5800 (outside u.s.a.) 8 corporate place fax: 908-336-2559 piscataway, nj 08854 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunications technology committee tel: 3 3432 1551 fax: 3 3432 1553 2nd floor, hamamatsucho - suzuki building, web: www.ttc.or.jp 1 2-11, hamamatsu-cho, minato-ku, tokyo - 93 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 list of data sheet changes this change list identifies those areas within this updated l4m data sheet that have significant differences rel- ative to the previous, and now superseded, l4m data sheet: updated l4m data sheet: edition 1a, january 2000. previous l4m data sheet: preliminary edition 1, june 1995. the page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. page number of updated data sheet summary of the change all changed edition number and date. all removed preliminary document status markings (and associated explanatory text on pages 1 and 93). 2 updated table of contents. 19 deleted third and fifth row of first table. changed max value and deleted typ value in second table. 89 added part number to diagram for figure 28. 90 changed content of ? related products ? section. 91 changed content of ? standards documentation sources ? section. 93 added ? list of data sheet changes ? section. 95 changed content of ? documentation update registration form ? section. transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. - 94 - transwitch corporation ? 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 - 95 - txc-03456-mb ed. 1a, january 2000 data sheet l4m txc-03456 documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: ________________________________________________________________________________ company: ___________________________________________ title: ______________________________ dept./mailstop: __________________________________________________________________________ street: ________________________________________________________________________________ city/state/zip: __________________________________________________________________________ if located outside u.s.a., please add - country: _______________ postal code: ___________________ telephone: ________________________ ext.: _____________ fax: __________________________ e-mail: ________________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: _____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453. please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this transwitch product as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a. transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required |
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