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?2003 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 features ? complete pwm control and house keeping circuitry ? few external components ? precision voltage reference trimmed to 2% ? dual output for push-pull operation ? each output tr for 200ma sink current ? variable duty cycle by dead time control ? soft start capability by us ing dead time control ? double pulse suppression logic ? over voltage protection for 3.3v/5v/12v ? under voltage protection for 3.3v/5v/12v ? over current protection for 3.3v/5v/12v ? one more external input for various protection (pt) ? remote on/off control function (ps-on) ? latch function controlled by remote and protection input ? power good signal gene rator with hysteresis typical application ? pc power supply description the fan7585 is a fixed frequency improved performance pulse width modulation control circuit with complete house- keeping circuitry for use in the secondary side of smps (switched mode power supply). it contains various func- tions, which are overvoltage pr otection, undervoltage protec- tion, over current protection, remote on/off control, power good signal generator, etc. ovp (over voltage protection) section it has ovp functions for +3.3v,+5v,+12v outputs and pt. the circuit is made up of a comparator with four detecting inputs and without hys teresis voltage. esp ecially, pt (pin19) is prepared for an extra ovp input or another protection signal. uvp (under voltage protection) section it also has uvp functions for +3.3v, +5v, +12v outputs. the block is made up of a comparator with three detecting inputs and without hysteresis voltage. ocp (over current protection) section it has precision ocp functions for +3.3v, +5v, +12v out- puts. the block is made up of three comparators with current source setting function. two inputs of each ocp comparator are connected to both sides of cu rrent sensing inductor that is located in the secondary output of smps. remote on/off section the remote on/off section is used to control smps exter- nally. if a high signal or open st ate is supplied to the remote on/off input, pwm signal become s a high state and all sec- ondary outputs are grounded. the remote on/off signal is transferred with some on-delay and off-delay time of 8ms, 24ms respectively. precision reference section the reference voltage is trimmed to 2%. (4.9v vref 5.1v) pg (power good signal generator) section the power good signal generator is to monitor the voltage level of power supply for safe operation of a microprocessor having some delay time at turn-on. the power good output should be low state before the output voltatge is out of regu- lation at turn-off. 24-sdip 1 fan7585 intelligent voltage mode pwm ic
fan7585 2 internal block diagram oscillator pwm control q r s delay controller vref start up 22 24 5 6 19 18 16 14 20 9 1 12 21 4 3 2 7 d q ck q vref vref dead time controler ovp comp uvp comp pg generator comp3 comp2 internal bias v5 v5 ichag 1.8v !" 0.6v 1.8v !" 0.6v 1.25v 0.1v 1.4v 1.25v 1.25v c1 c2 pg t rem rem (ps-on) pt v12 v5 v33 gnd t uvp t pg r t /c t comp vref vcc det e/a(-) e/a(+) vref dtc 11 10 8 ri 15 13 17 is33 is5 is12 iref1=vref/ri iref1*5 23 ocp h l l l l h h l l l l l l l h h l l l l
fan7585 3 pin definition pin description pin number pin name i/o pin function description pin number pin name i/o pin function description 1v cc i supply voltage 13 is33 i ocp input for +3.3v 2 comp o e/a output 14 v33 i o vp, uvp input for +3.3v 3 e/a(-) i e/a (-) input 15 is5 i ocp input for +5v 4 e/a(+) i e/a (+) input 16 v5 i ovp, uvp input for 5v 5t rem - remote on/off delay 17 i s12 i ocp input for +12v 6 rem i remote on/off input 18 v12 i ovp, uvp input for +12v 7r t /c t - oscillation freq. setting r,c 19 pt i extra protection input 8 ri - ocp current setting r 20 t uvp - uvp delay 9 det i detect input 21 dtc i deadtime control input 10 t pg - pg delay 22 c2 o output 2 11 pg o power good signal output 23 gnd - ground 12 vref o precision reference voltage 24 c1 o output 1 vcc 8 7 6 5 4 3 2 1 24 23 22 21 20 19 18 17 fan7585 comp e/a(-) e/a(+) t rem rem r t /c t ri pt dtc v12 t uvp c2 gnd c1 12 11 10 9 16 15 14 13 det t pg pg is33 vref is5 v33 v5 is12
fan7585 4 pin function pin number pin name pin function description 1v cc supply voltage. operating range is 15v~30v. test condition : v cc =20v, ta=25 c. 2comp error amplifier output. it is connected to non-inverting input of pulse width modulator comparator. 3 e/a(-) error amplifier inverting input. its reference voltage is always 1.25v. 4e/a(+) error amplifier non-inverting input feedback voltage. this pin may be used to sense power supply output voltages. 5t rem remote on/off delay. ton/toff=8ms/24ms (t yp.) with c=0.1uf. its high/low threshold voltages are 1.8v/0.6v. 6rem remote on/off input. it is ttl operation and its threshold voltage is 1.4v. voltage at this pin can reach normal 4.6v, wit h absolute maximum voltage, 5.25v. if rem = ? low ? , pwm = ? low ? , that means the main smps is operational. when rem = ? high ? , then pwm = ? high ? and the main smps is turned-off. 7r t /c t oscillation frequency setting r, c.(test condition r t =10k ? ) 8ri ocp current setting pin. you can fix the oc p reference current (i ref1) by using ri resistor. 9 det ac input under voltage detection pi n. its threshold voltage is 1.25v typ. 10 t pg pg delay. td =260m s (typ.) with c tpg = 2.2uf. the high/low threshold voltages are 1.8v/0.6v and the voltage of pin10 is clamped to 2.9v for noise margin. 11 pg power good output signal. pg = ? high ? means that the power is ? good ? for operation and pg = ? low ? means ? power fail ? . 12 vref precision voltage reference is trimmed to 2% (typical value = 5v). 13 is33 current sense input for +3.3v output. this pin is connected to the current sensing resistor or inductor. you can define ocp offs et voltage for +3.3v by using ri resistor externally. if you connect 62k ? at pin 8 to ground, the reference current(iref1) should be 20ua. after that , you can make a constant ocp offset voltage(v offset =r offset *5*20ua). in case the voltage drop(i o.33 *rs) of the sense resistor or inductor is larger than offset voltage, after ocp delay time the main smps is turned off. so the over current level is determined by the following equation. i o.33 =v offset /rs. 14 v33 ovp, uvp input for +3.3v output (typical value = 4.1v/2.3v). 15 is5 current sense input for +5v output. you can make +5v ocp function as the previous method in is5(pin15). 16 v5 ovp, uvp input for +5v output (typical value = 6.4v/4.0v). 17 is12 current sense input for +12v output. you can make +12v ocp function as the previous method in is12(pin17). 18 v12 ovp, uvp input for 12v output (typical value = 14.2v/10v). 19 pt this is prepared for an extra ovp input or another protection signal (typical value = 1.25v). 20 t uvp timing delay pin for under voltage protection and over current protection. its threshold voltage is 1.8v and clamped to 2.9v after full charging. target of delay time is 38ms and it is realized through external capacitor (c tuvp = 0.47uf). 21 dtc deadtime control input. the deadtime control comparator has an effective 120mv input offset which limits the mini mum output dead time. dead time may be imposed on the output by setting the dead time control input to a fixed voltage, ranging from 0v to 3.3v. 22 c2 output drive pin for push-pull operation. 23 gnd ground. 24 c1 output drive pin for push-pull operation.
fan7585 5 absolute maximum ratings temperature characteristics characteristics symbol value unit supply voltage v cc 40 v collector output voltage v c1 ,v c2 40 v collector output current i c1 ,i c2 200 ma power dissipation (fan7585) p d 1.5 w operating temperature range t opr -25 to 85 c storage temperature range t stg -65 to 150 c characteristics symbol min. typ. max. unit temperature coeffici ent of vref (-25 c ta 85 c) ? vref/ ? t - 0.01 - %/ c
fan7585 6 electrical characteristics (v cc =20v, t a =25 c, unless otherwise specified) parameter symbol condition min. typ. max. unit reference section reference output voltage vref iref=1ma 4.9 5 5.1 v line regulation ? vref. line 15v v cc 30v - 2.0 25 mv load regulation ? vref. load 1ma iref 10ma - 1.0 15 mv temperature coefficient of vref (1) ? vref/ ? t-25 c ta 85 c - 0.01 - %/ c short circuit output current i sc vref = 0 153575ma oscillator section oscillation frequency fosc c t =0.01uf, r t =12k - 9.4 - khz frequency change with temperature (1) fosc/t c t =0.01uf, r t =12k - 2 - % dead time control section input bias current i b(dt) - - -2.0 -10 ua maximum duty voltage dc max pin21 (dtc)=0v 45 48 50 % input threshold voltage v th(dt) zero duty cycle - 3.0 3.3 v max. duty cycle 0 - - error amp section inverting reference voltage vref(ea) - 1.20 1.25 1.30 v input bias current i b(ea) v comp =2.5v - -0.1 -1.0 ua open-loop voltage gain (1) g vo 0.5v v comp 3.5v 70 95 - db unit-gain bandwidth (1) bw - - 650 - khz output sink current i sink v comp = 0.7v 0.3 0.9 - ma output source current i source v comp = 3.5v -2.0 -4.0 - ma pwm comparator section input threshold voltage v th(pwm) zero duty cycle - 4 4.5 v output section output saturation voltage v ce(sat) i c = 200ma - 1.1 1.3 v collector off-state current i c(off) v cc =v c =30v, v e =0v - 2 100 ua rising time (1) t r - - 100 200 ns falling time (1) t f --50200ns
fan7585 7 electrical characteristics (continued) (v cc =20v, t a =25 c, unless otherwise specified) note: 1. these parameters, although guaranteed over their recomm ended operating conditions are not 100% tested in production. 2. rem on delay time (pin6 rem: ? l ? ? h ? ), rem off delay time (pin6 rem: ? h ? ? l ? ) parameter symbol condition min. typ. max. unit protection section over voltage protection for +3.3v v ovp1 - 3.8 4.1 4.3 v over voltage protection for +5v v ovp2 -6.06.46.8v over voltage protection for +12v v ovp3 - 13.5 14.2 15.0 v input threshold voltage for pt v pt - 1.201.251.30 v under voltage protection for +3.3v v uvp1 -2.12.32.5v under voltage protection for +5v v uvp2 -3.74.04.3v under voltage protection for +12v v uvp3 - 9.2 10 10.8 v voltage for current reference v ri 1.21 1.25 1.29 v current reference (1) iref1 10 - 65 ua charging current for uvp, ocp delay i chg.uvp c=0.47uf -16 -21 -28 ua uvp, ocp delay time t d.uvp c=0.47uf, v th =1.8v 243857ms offset voltage of ocp comparator v offset -5 - 5 mv remote on/off section rem on input voltage v remh i rem = -200ua 2.0 - - v rem off input voltage v reml ---0.8v rem off input bias current i reml v rem = 0.4v - - -1.6 ma rem on open voltage v rem(open) - 2.0 - 5.25 v rem on delay time ton c=0.1uf 4 8 14 ms rem off delay time toff c=0.1uf 16 24 34 ms remote on/off section (2) detecting input voltage v in(det) - 1.201.251.30 v detecting v5 voltage v5 (det) -4.14.34.5v hysteresis voltage 1 hy1 comp1, 2 10 40 80 mv hysteresis voltage 2 hy2 comp3 0.6 1.2 - v pg output load resistor r pg -0.512k ? charging current for pg delay i chg.pg c=2.2uf -10 -15 -23 ua pg delay time t d.pg c=2.2uf, v th =1.8v 100 260 500 ms pg output saturation voltage v sat(pg) i pg =10ma - 0.2 0.4 v total device standby supply current i cc --1020ma
fan7585 8 application informations 23456789 10 20 30 40 50 1 10 100 timing resistance vs frequency 0.2 ct=1nf ct=2.2nf ct=4.7nf ct=10nf ct=20nf ct=50nf ct=100nf frequency(khz) rt(kohm) fig 1. timing resistance vs frequency feedback dead-time control ck q q output q1 output q2 rt/ct fig 2. operating waveform
fan7585 9 1. ovp block the ovp function is simply realized by c onnecting pin14, pin16, pin18 to each secondary outputs. r1, r2, r3, r4, r5, r6 are internal resistors of the ic. ea ch ovp level is determined by re sistor ratio and the typical va lues are 4.1v/6.4v/14.2v respec- tively. ? ovp detecting voltage for +3.3v ? ovp detecting voltage for +5v ? ovp detecting voltage for +12v especially, pin19(pt) is prepared for extra ovp input or another protecti on signal. that is, if you want over voltage protectio n of extra output voltage, then you can make a function with two external resistors. ? ovp detecting voltage for pt in the case of ovp, a system designer should know a fact that the main power ca n be dropped after a li ttle time because of system delay, even if pwm is triggered by ovp. so when the ovp level is tested with a set, you should check the secondary outputs(+3.3v/+5v/+12v) and pg(pin11) si multaneously. then you can know the each ovp level as checking each output voltage in just time that pg(pin11 ) is triggered from high to low. 12v pt r101 r102 d 1.2 5v r1 r2 r3 r4 r5 r6 ovp comp vref=5v set of r/s latch a c b 3.3v 5v 19 r102, r102 : external components vo 18 14 16 v ovp1 +3.3v () r 1 r 2 + r 2 --------------------- - v a r 1 r 2 + r 2 --------------------- - vref 4.1v = = = v ovp2 +5v () r 3 r 4 + r 4 --------------------- - v b r 3 r 4 + r 4 --------------------- - vref 6.4v = = = v ovp3 +12v () r 5 r 6 + r 6 --------------------- - v c r 5 r 6 + r 6 --------------------- - vref 14.2v = = = pt r 101 r 102 + r 102 ----------------------------------- v d r 101 r 102 + r 102 ----------------------------------- = vref =
fan7585 10 2. uvp block the block is made up of a comparator with three detectin g inputs and without hysteresis voltage. each uvp level is determined by resistor ratio and the typical values are 2.3v/4.0v/10v respectively. ? uvp detecting voltage for +3.3v ? uvp detecting voltage for +5v ? uvp detecting voltage for +12v in the case of uvp, a system designer should know a fact that the main power ca n be dropped after some delay. (38msec@ c tuvp =0.47uf) so when the uvp level is tested with a set, you should remove pr otection delay capaci tor(pin20) and check pg(pin11). you can know the each uvp level as checking each output voltage in just time that pg(pin11) is triggered from high to low. 12v 1.2 5v r1 r2 r3 r4 r5 r6 uvp comp vref=5v set of r/s latch a c b 3.3v 5v 18 14 16 v uvp1 +3.3v () r 1 r 2 + r 2 --------------------- - v a r 1 r 2 + r 2 --------------------- - = vref 2.3v == v uvp2 +5v () r 3 r 4 + r 4 --------------------- - v b r 3 r 4 + r 4 --------------------- - = vref 4v == v uvp3 +12v () r 5 r 6 + r 6 --------------------- - v c r 5 r 6 + r 6 --------------------- - = vref 10v ==
fan7585 11 3. ocp block it also has ocp function for +3.3v,+5v, +12v outputs. the block is made up of three comparators. pin17(is12), pin15(is5) and pin13(is33) are current sense inputs for +12v, +5v and +3.3 v outputs respectively. these pi ns are connected to the cur- rent sensing resistor or inductor. each ocp level is determined by ri resistor , so you can define over current protection level by changing ri resistor. pin8(ri) voltage is always 1.25v, so if you connect 62k ? resistor, the referenc e current is 20ua(iref1). if the voltage drop of the sense resistor or inductor is larger th an offset voltage (v offset = r offset 5 iref1), the dtc becomes "high" after some delay(38ms at c tuvp =0.47uf)and the main smps is turned of f. that means the output voltage(+3.3v, +5v, +12v) will be ground level. after main power is turned off at ocp and initialized by rem, if rem signal is changed from "high" to "low", main power becomes operational. for example, if you want to define 5v output ocp level at 10a in the c ondition of equivalent resistor(rs)= 5m ? , you can determine the offset voltage resistor(r offset ) as following method. - iref1 = 1.25v / 62k ? = 20ua - v offset = r s 5 iref1 = 5m ? 10a = 50mv - therefore, r offset = 50mv / (5 iref1) = 500 ? by the way, ocp output signal can be delayed by protection delay capacitor(c tuvp ) and its delay time is decided by the value of c tuvp . if you use too small (or large) capacitor, the charging time would decrease (or in crease) very much and it can cause malfunction at the transient t ime. so you have to choose the reasonable delay time for system optim ization by changing the external capacitor value. is12 is33 is5 15 17 comp1 comp2 comp3 13 iref 5 iref1 5 (100ua) ovp output vs12 18 vs5 16 vs33 14 sense inductor equivalent resistor(rs) ? 5m ? roffset (offset voltage resistor) iref 5 iref 5 (100ua) iref1 5 (100ua) iref1 5 iref1=20 a at ri=62k ? io t pr ot tuvp c tuvp * ? v ? i ---------------------------- - 0.47uf*1.7v 21ua ---------------------------------- - 38msec ==
fan7585 12 4. remote on/off & delay block remote on/off section is controlled by a microprocessor. if a high signal is supplied to the re mote on/off input(pin6), the output of comp6 becomes high status. the output signal is transferred to on/off delay block and pg block. if no signal is supplied to pin6, pin6 maintains high status(=5v ) for pull-up resistor, rpull. when remote on/off is high, it produces pwm(pin6) "high" signal after on dela y time (about 8ms with c trem =0.1uf) for stabilizing system. then, all output s (+3.3v, +5v, +12v) are grounded. when remote on/off is changed to "low", it produc es pwm "low" signal after of f delay time (about 24ms with c trem =0.1uf) for stabilizing the system. if rem is low, then pwm is low. that means the main smps is operational. when rem is high, pwm is high and the main smps is turned off. remote on/off delay time can be calculated by following equation. k1, k2: constant value gotten by test in above equation, a typical capacitor valu e is 0.1uf. if the capacitor is changed to larger value, it ca n cause malfunction in case of ac power on at "rem=high". be cause pwm maintains low status and main power turns on for on delay time. so you should use 0.1uf or smaller capacitor. ioff = irem - ion ? von=2v, ? voff=2.1v ion+ioff 2.2 v 0.6 v ? 1.8v comp trem 0.1 uf ion irem q1 q2 a c b 5 trem comp6 12 vref pg block 1.2 5v 6 rem 5v rpull remote on/off ton toff rem pwm ton k 1 c trem ? von ion ---------------------------------------- 0.95 0.1uf 2v 23ua ----------------------------- - 8msec == toff k 2 c trem ? voff ioff ---------------------------------------- 0.8 0.1uf 2.1v 7ua ---------------------------------- - 24msec ==
fan7585 13 5. power good signal generator power good signal generator circuit generates "on or off" signal depending on the status of output voltage to prevent the malfunctions of following systems like microprocessor, etc. caused by the output instability at power on or off . at power on, it produces pg "high" signal after some delay time(about 260ms with c tpg =2.2uf) for stabilizing output volt- age. at power off, it produces pg "low" signal without delay time by sensing the status of power source for protecting follow- ing systems. vcc detection poi nt(pin9) can be calcu lated by following equation. recommended values of r11, r12 are determined by the following equation. the comp3 creates pg "low" without delay wh en +5v output falls to less than 4.0v to prevent some malfunction at transient status, thus it impr oves system stability. when remote on/off signal is high, it ge nerates pg "low" signal wit hout delay. it means that pg becomes "low" before main power is grounded. pg delay time(t pg ) is determined by capacitor value(c tpg ), threshold voltage of comp3 and the charging current and its euqation is as following. considering the lightning surge and noise, th ere are two types of protections. one is a few time delay betw een tpg and pg for safe operation and a nother is some noise margin of pin10. noise_margin_of_t pg = v pin10 (max)- vth(l) = 2.9v - 0.6v = 2.3v vcc q2 pg det ichg 12 vref comp3 t pg c pg 2.2 uf 11 r15 1k ? q3 16 +5v 9 0.6 v 1.8v 1.2 5v comp1 comp2 vref vref r13 r12 r14 remote on/off 10 r11 60k ? pg comp 4.7k ? det 1.25v = 1 r11 r12 ---------- - + ?? ?? 17.2v = t pg c tpg ? v ichg ---------------------------- - = c tpg vth ichg ------------------------------ 2.2uf 1.8v 15ua ---------------------------------- - = 260msec
fan7585 14 typical application circuit c24 r6 u3 1 2 3 4 r49 is33 co8 fan7585 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vcc comp ea(-) ea(+) tr em rem(pson) rt/ct ri det tp g pg vref is33 v33 is5 v5 is12 v12 pt tu vp dtc c2 gnd c1 t2 4 8 2 1 5 3 7 6 r31 r5 c12 rs3 r43 rs1 r28 c14 rd2 q1 q5 ka431 r48 d16 d23 c11 d19 co6 l4 l8 c16 ac_input 1 2 3 r8 q4 r52 r30 co12 r24 d25 d15 cs1 +5vs b d5 -+ bd1 1 2 3 4 t rt1 q3 co2 r38 l1 pson co9 d13 r25 vdd r51 is5 r50 q2 f1 t3 2 7 5 8 11 6 9 10 is12 co10 r47 l3 r29 ka431 b+ r58 d9 c20 d26 r55 d24 co4 r53 t1 4 8 2 1 5 3 7 6 10 9 r42 + c2 r12 110vac (short) rs2 d4 cd1 +5v lm1 1 2 r23 pg c15 c3 d14 c17 220vac (open) +12v r33 d6 line filter cy2 cs3 d1 d29 r36 c10 l1-1 co7 d17 c21 vr1 r40 +3.3v l7 r21 r3 r44 c7 is5 r10 r56 r46 l2 c8 l1-3 c22 d30 r37 is12 c5 r4 d11 c18 l1-4 r57 + c4 d27 c23 r32 r22 d12 5h0165 1 2 3 4 gnd d vcc fb r20 r1 vdd l5 r2 vr2 cy1 d21 co3 d28 l1-2 +12v +5v d22 b+ cx1 cx2 +3.3v d18 l6 cd2 co5 is33 r54 r45 r35 sw1 co11 d10 r39 rd1 r34 d20 c6 d8 -5v r7 co1 -12v r9 d3 l9 c13 c100 r41 r11 r27 c101 c19 cs2 r26 d2 + c1
fan7585 15 mechanical dimensions package dimensions in millimeters 24-sdip
fan7585 5/13/03 0.0m 001 stock#dsxxxxxxxx ? 2003 fairchild semiconductor corporation life support policy fairchild?s products are not auth orized for use as critical compon ents in life support devices or systems without the express written approval of the pr esident of fairch ild semiconductor corporation. as used herein: 1. life support devices or syst ems are devices or systems which, (a) are intended for surg ical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause t he failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve re liability, function or design. fairchild does not assume any liability arising out of the applic ation or use of any product or circuit described herein; neither does it convey any license under its pat ent rights, nor the rights of others. ordering information product number package operating temperature fan7585 24-sdip -25 c ~ 85 c
careers | sitema go datasheets, samples, buy technical information applications design center support company investors my f a home >> find products >> fan7585 pwm and secondary combo ic general description back to top features contents ? general description ? features ? applications ? product status/pricing/packaging ? order samples ? qualification support the fan7585 is a fixed frequency improved performance pulse width modulation control circuit with complete housekeeping circuitry for use in the secondary side of smps (switiched mode power supply). it contains various functions, which are overvoltage protection, undervoltage protection, over current protection, remove on/off control, power good signal generator, etc. z complete pwm control and house keeping circuitry z few external components z precision voltage reference trimmed to 2% z dual output for push-pull operation z each output tr for 200ma sink current z variable duty cycle by dead time control z soft start capability by using dead time control z double pulse suppression logic z over voltage protection for 3.3v/5v/12v z under voltage protection for 3.3v/5v/12v z over current protection for 3.3v/5v/12v z one more external input for various protection (pt) z remote on/off control function (ps-on) z latch function controlled by remote and protection input z power good signal generator with hysteresis datasheet download this datasheet e - mail this datasheet this page print version related links request samples how to order products product change notices (pcns) support sales support quality and reliability design cente r pa g e 1 of 2 product folder - fairchild p/n fa n7585 - pwm and secondary combo ic 16-au g -2007 mhtml:file://c:\temp\fan7585sn.mht
product status/pricing/packaging back to top qualification support click on a product for detailed qualification data back to top back to top applications back to top z pc power supply product product status pb-free status pricing* package type leads packing method fan7585sn full production $1.14 dip 24 rail * fairchild 1,000 piece budgetary pricing ** a sample button will appear if the part is available through fa irchild's on-line samples program. if there is no sample butt on, please contact a fairchild distributor to obtain samples indicates product with pb -free second-level interconne ct. for more information click here. product fan7585sn ? 2007 fairchild semiconductor products | design center | support | company news | investors | my fairchild | contact us | site index | privacy policy | site terms & conditions | standard terms & conditions o pa g e 2 of 2 product folder - fairchild p/n fa n7585 - pwm and secondary combo ic 16-au g -2007 mhtml:file://c:\temp\fan7585sn.mht

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