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february, 1999 data sheet general description features lxt982/982a single-speed, 5-port fast ethernet repeater for 100base-tx/fx applications the lxt982 is a 5-port 100 mbps class ii repeater that is fully compliant with ieee 802.3 standards. four ports directly support 100base-tx copper media or 100base- fx fiber media via pseudo-ecl (pecl) interfaces. the fifth port, a 100 mbps media independent interface (mii), connects to media access controllers macs) for bridge/ switch applications. the mii can also be configured to interface to another phy device, such as the lxt970. this data sheet applies to all lxt982 products (lxt982, lxt982a, and any subsequent variants), except as specifically noted. the lxt982 provides an inter-repeater backplane (irb) for expansion, operating at 100 mbps. up to 240 ports can logically be combined into one repeater using this bus. the lxt982 is an advanced cmos device packaged in a 208-pin pqfp which operates from a single 5v power supply. ? four 100base-tx ports with complete twisted-pair phys including integrated filters. ? optional support for 100base-fx pecl interfaces. ? 100 mbps mii port connection to either mac or phy enables system to meet class ii repeater requirements. ? cascadable backplane for high-density designs. ? integrated led drivers with user-selectable modes. ? available in 208-pin pqfp package. ? case temperature range: 0-115 c. revision 1.2 mode control 100base-t repeater mii led drivers 100mbps e'net phy 100mbps e'net phy 100mbps e'net phy 100mbps e'net phy inter- repeater backplane mode control 100m irb reversible mii port status indicators twisted pair_i/o fiber_i/o twisted pair_i/o fiber_i/o twisted pair_i/o fiber_i/o twisted pair_i/o fiber_i/o system clock 25mhz clock lxt982/982a block dia g ram refer to www.level1.com for most current information. )
lxt982/982a single-speed, 5-port fast ethernet repeater 2 table of contents pin assignments and signal descriptions ........................................................................................ ............. 4 functional description ......................................................................................................... .......................... 11 introduction ............................................................................................................................... ................................... 11 port configuration ............................................................................................................. ..................................... 11 interface descriptions......................................................................................................... .................................... 11 100base-tx interface ........................................................................................................... ......................... 11 100base-fx interface ........................................................................................................... .........................12 media independent interface (mii) .............................................................................................. ....................13 inter-repeater backplane ....................................................................................................... ........................13 repeater operation ............................................................................................................. ...................................13 requirements ................................................................................................................... ..........................14 power .......................................................................................................................... ...........................................14 clock .......................................................................................................................... ............................................14 bias current ................................................................................................................... ........................................14 reset .......................................................................................................................... ............................................14 irb bus pull-ups ............................................................................................................... .....................................14 led operation.................................................................................................................. ..........................14 power-up and reset conditions .................................................................................................. ..........................14 port leds ...................................................................................................................... .........................................14 global leds .................................................................................................................... .......................................14 irb operation.................................................................................................................. ...........................15 irb isolation .................................................................................................................. ........................................ 15 mii port operation ............................................................................................................. .........................17 phy mode operation ............................................................................................................. ................................17 mac mode operation............................................................................................................. ................................17 mii port timing considerations ................................................................................................. .............................17 application information........................................................................................................ ..........................19 general design guidelines...................................................................................................... ...................19 power supply filtering ......................................................................................................... ................19 power and ground plane considerations.......................................................................................... ..20 mii terminations............................................................................................................... ....................20 the rbias pin .................................................................................................................. ...................20 the twisted-pair interface ..................................................................................................... ..............20 the fiber interface............................................................................................................ ................... 20 magnetics information.......................................................................................................... ................ 21 typical application circuitry.................................................................................................. ......................21
3 lxt982/982a table of contents test specifications ............................................................................................................ ............................. 27 absolute maximum ratings ....................................................................................................... ................ 27 recommended operating conditions ............................................................................................... ......... 27 input clock requirements....................................................................................................... ................... 27 i/o electrical characteristics ................................................................................................. ..................... 28 irb electrical characteristics................................................................................................. .................... 28 100base-tx transceiver electrical characteristics.............................................................................. .... 29 100base-fx transceiver electrical characteristics.............................................................................. .... 29 port-to-port delay timing...................................................................................................... ..................... 30 100base-tx transmit timing - phy mode mii...................................................................................... ... 31 100base-tx receive timing - phy mode mii ....................................................................................... .. 32 100base-tx transmit timing - mac mode mii ...................................................................................... .. 33 100base-tx receive timing - mac mode mii ....................................................................................... .. 33 100base-fx transmit timing - phy mode mii...................................................................................... ... 34 100base-fx receive timing - phy mode mii ....................................................................................... .. 35 100base-fx transmit timing - mac mode mii ...................................................................................... .. 36 100base-fx receive timing - mac mode mii ....................................................................................... .. 36 irb timing ..................................................................................................................... ............................ 37 mechanical specifications...................................................................................................... ....................... 38 revision history ............................................................................................................... .............................. 39
lxt982/982a single-speed, 5-port fast ethernet repeater 4 pin assignments and signal descriptions figure 1: pin assignments reset ..... 53 clk25 ..... 54 n/c ..... 55 n/c ..... 56 vcc ..... 57 n/c ..... 58 n/c ..... 59 n/c ..... 60 n/c ..... 61 n/c ..... 62 n/c ..... 63 n/c ..... 64 n/c ..... 65 n/c ..... 66 n/c ..... 67 n/c ..... 68 n/c ..... 69 n/c ..... 70 fps ..... 71 gnd ..... 72 gnd ..... 73 gnd ..... 74 gnd ..... 75 vcc ..... 76 n/c ..... 77 n/c ..... 78 n/c ..... 79 n/c ..... 80 n/c ..... 81 gnd ..... 82 gnd ..... 83 vcc ..... 84 n/c ..... 85 col_led ..... 86 n/c ..... 87 gnd ..... 88 vcc ..... 89 n/c ..... 90 act_led ..... 91 n/c ..... 92 gnd ..... 93 vccv ..... 94 gndv ..... 95 vcc ..... 96 n/c ..... 97 n/c ..... 98 port5_sel ..... 99 n/c ..... 100 n/c ..... 101 n/c ..... 102 n/c ..... 103 gndr ..... 104 208 .......ledsel0 207 .......ledsel1 206 .......vcc 205 .......vcc 204 .......vcc 203 .......vcc 202 .......gnd 201 .......vcc 200 .......gnd 199 .......n/c 198 .......n/c 197 .......n/c 196 .......n/c 195 .......n/c 194 .......n/c 193 .......n/c 192 .......n/c 191 .......n/c 190 .......n/c 189 .......port1_sel 188 .......vcc 187 .......port2_sel 186 .......vcc 185 .......port3_sel 184 .......vcc 183 .......port4_sel 182 .......vcc 181 .......port1_led1 180 .......port1_led2 179 .......n/c 178 .......gnd 177 .......port2_led1 176 .......port2_led2 175 .......n/c 174 .......gnd 173 .......port3_led1 172 .......port3_led2 171 .......n/c 170 .......vcc 169 .......vccv 168 .......gndv 167 .......gnd 166 .......port4_led1 165 .......port4_led2 164 .......n/c 163 .......gnd 162 .......port5_led1 161 .......port5_led2 160 .......n/c 159 .......gnd 158 .......gnd 157 .......fibip1 52 ......... irclk 51 ......... vcc 50 ......... gnd 49 ......... irdat4 48 ......... n/c 47 ......... n/c 46 ......... irdat3 45 ......... irdat2 44 ......... irdat1 43 ......... irdat0 42 ......... irdv 41 ......... irden 40 ......... ircol 39 ......... n/c 38 ......... irsngl 37 ......... ircfsbp 36 ......... ircfs 35 ......... vcc 34 ......... gnd 33 ......... mii_rxd3 32 ........ mii_rxd2 31 ......... n/c 30 ......... mii_rxd1 29 ......... mii_rxd0 28 ......... vcc 27 ......... gnda 26 ......... mii_rxdv 25 ......... mii_rxclk 24 ......... mii_rxer 23 ......... n/c 22 .........mii_txer 21 ......... mii_txclk 20 .........mii_txen 19 ......... mii_txd0 18 ......... mii_txd1 17 ......... mii_txd2 16 ......... mii_txd3 15 ......... n/c 14 ......... mii_col 13 ......... mii_crs 12 ......... vcc 11 ......... gnd 10 ......... n/c 9 ........... n/c 8 ........... n/c 7 ........... n/c 6 ........... n/c 5 ........... n/c 4 ........... n/c 3 ........... n/c 2 ........... gnd 1 ........... n/c tpip4 ..... 105 tpin4 ..... 106 vccr ..... 107 tpop4 ..... 108 gndt ..... 109 tpon4 ..... 110 vcct ..... 111 fibop4 ..... 112 fibon4 ..... 113 sigdet4 ..... 114 fibin4 ..... 115 fibip4 ..... 116 gndr ..... 117 tpip3 ..... 118 tpin3 ..... 119 vccr ..... 120 tpop3 ..... 121 gndt ..... 122 tpon3 ..... 123 vcct ..... 124 fibop3 ..... 125 fibon3 ..... 126 sigdet3 ..... 127 fibin3 ..... 128 fibip3 ..... 129 gnda ..... 130 rbias ..... 131 gndr ..... 132 tpip2 ..... 133 tpin2 ..... 134 vccr ..... 135 tpop2 ..... 136 gndt ..... 137 tpon2 ..... 138 vcct ..... 139 fibop2 ..... 140 fibon2 ..... 141 sigdet2 ..... 142 fibin2 ..... 143 fibip2 ..... 144 gndr ..... 145 tpip1 ..... 146 tpin1 ..... 147 vccr ..... 148 tpop1 ..... 149 gndt ..... 150 tpon1 ..... 151 vcct ..... 152 fibop1 ..... 153 fibon1 ..... 154 sigdet1 ..... 155 fibin1 ..... 156 xxxx xxxx lxT982AHC/ lxt982qc xxxxxx (date code) (part#) (trace code) lot#)
5 lxt982/982a pin assignments and signal descriptions table 1: mode control signal descriptions pin symbol type 1 description 189 187 185 183 port1_sel port2_sel port3_sel port4_sel input ttl, pu latched on reset mode select - ports 1 through 4. these pins determine operating mode (copper or fiber) for the associated port as follows: low = fx high = tx 99 port5_sel input ttl, pu mode select - port 5. selects operating mode of the mii interface. pin is monitored at power-up and reset. subsequent changes have no effect. high = phy mode (lxt982 acts as phy side of the mii) low = mac mode (lxt982 acts as mac side of the mii) 1. nc = no clamp. pad will not clamp input in the absence of power. pu = input contains pull-up. pd = input contains pull-down. i/o = input / output. ttl = transistor-transistor logic. table 2: twisted-pair port signal descriptions pin symbol type description 149, 151 136, 138 121, 123 108, 110 tpop1, tpon1 tpop2, tpon2 tpop3, tpon3 tpop4, tpon4 output analog twisted-pair outputs - ports 1 through 4. these pins are the positive and negative outputs from the respective ports twisted-pair line drivers. these pins can be left open when not used. 146, 147 133, 134 118, 119 105, 106 tpip1, tpin1 tpip2, tpin2 tpip3, tpin3 tpip4, tpin4 input analog twisted-pair inputs - ports 1 through 4. these pins are the positive and negative inputs to the respective ports twisted-pair receivers. these pins can be left open when not used.
lxt982/982a single-speed, 5-port fast ethernet repeater 6 table 3: fiber port signal descriptions pin symbol type description 153, 154 140, 141 125, 126 112, 113 fibop1, fibon1 fibop2, fibon2 fibop3, fibon3 fibop4, fibon4 output pecl fiber outputs - ports 1 through 4. these pins are the positive and negative outputs from the respective ports pecl drivers. these pins can be left open when not used. 157, 156 144, 143 129, 128 116, 115 fibip1, fibin1 fibip2, fibin2 fibip3, fibin3 fibip4, fibin4 input pecl fiber inputs - ports 1 through 4. these pins are the positive and negative inputs to the respective ports pecl receivers. they can be left open when not used. 155 142 127 114 sigdet1 sigdet2 sigdet3 sigdet4 input pecl signal detect - ports 1 through 4. signal detect for the fiber ports. these pins can be left open when not used. 1. pecl = pseudo ecl. table 4: phy mode mii interface signal descriptions pin symbol type 1 description 29 30 32 33 mii_rxd0 mii_rxd1 mii_rxd2 mii_rxd3 output, ttl receive data. the lxt982 transmits received data to the controller on these outputs. data is driven on the falling edge of mii_rxclk. 26 mii_rxdv output, ttl receive data valid. active high signal, synchronous to mii_rxclk, indicates valid data on mii_rxd<3:0>. 25 mii_rxclk output, ttl receive clock. mii receive clock for expansion port. this is a 2.5 or 25 mhz clock derived from the clk25 input (refer to table 9 on page 10). 24 mii_rxer output, ttl receive error. active high signal, synchronous to mii_rxclk, indicates invalid data on mii_rxd<3:0>. 22 mii_txer input, ttl transmit error. the mac asserts this input when an error has occurred in the transmit data stream. the lxt982 responds by sending invalid code symbols on the line. 21 mii_txclk output, ttl transmit clock. 25 mhz continuous output derived from the 25 mhz input clock. 20 mii_txen input, ttl transmit enable. external controllers drive this input high to indicate that data is being transmitted on the mii_txd<3:0> pins. tie this input low if it is unused. 1. mii interface pins reverse direction based on phy/mac mode. direction listed is for phy mode. 2. ttl = transistor-to-transistor logic.
7 lxt982/982a pin assignments and signal descriptions 19 18 17 16 mii_txd0 mii_txd1 mii_txd2 mii_txd3 input, ttl transmit data. external controllers use these inputs to transmit data to the lxt982. the lxt982 samples mii_txd<3:0> on the rising edge of mii_txclk, when mii_txen is high. 14 mii_col output, ttl collision. the lxt982 drives this signal high to indicate that a collision has occurred. 13 mii_crs output, ttl carrier sense. active high signal indicates that the lxt982 is transmitting or receiving. table 5: mac mode mii interface signal descriptions pin symbol type 1 description 29 30 32 33 mii_rxd0 mii_rxd1 mii_rxd2 mii_rxd3 input, ttl receive data. the lxt982 receives data from the phy on these pins. data is sampled on the rising edge of mii_rxclk. 26 mii_rxdv input, ttl receive data valid. active high signal, synchronous to mii_rxclk, indicates valid data on mii_rxd<3:0>. 25 mii_rxclk input, ttl receive clock. mii receive clock for expansion port. this is a 25 mhz clock. 24 mii_rxer input, ttl receive error. active high signal, synchronous to mii_rxclk, indicates invalid data on mii_rxd<3:0>. 22 mii_txer output, ttl transmit error. the lxt982 asserts this signal when an error has occurred in the transmit data stream. 21 mii_txclk input, ttl transmit clock. 25 mhz continuous input clock. must be supplied from same source as clk25 system clock. 20 mii_txen output, ttl transmit enable. the lxt982 drives this output high to indicate that data is being transmitted on the mii_txd<3:0> pins. 19 18 17 16 mii_txd0 mii_txd1 mii_txd2 mii_txd3 output, ttl transmit data. the lxt982 drives these outputs to transmit data to the phy. the device drives mii_txd<3:0> on the rising edge of mii_txclk, when mii_txen is high. 14 mii_col input, ttl collision. high input indicates that a collision has occurred. 13 mii_crs input, ttl carrier sense. high indicates that the lxt982 is transmitting or receiving. 1. mii interface pins reverse direction based on phy/mac mode. direction listed is for mac mode. 2. ttl = transistor-to-transistor logic. table 4: phy mode mii interface signal descriptions C continued pin symbol type 1 description 1. mii interface pins reverse direction based on phy/mac mode. direction listed is for phy mode. 2. ttl = transistor-to-transistor logic.
lxt982/982a single-speed, 5-port fast ethernet repeater 8 table 6: inter-repeater backplane signal descriptions pin symbol type 1 description 2 43 44 45 46 49 irdat0 irdat1 irdat2 irdat3 irdat4 i/o cmos tri-state schmitt pu irb data. these bidirectional signals carry data on the 100 mbps irb. data is driven on the falling edge and sampled on the rising edge of irclk. these signals can be buffered between boards. 52 irclk i/o cmos tri-state schmitt pd irb clock. this bidirectional, non-continuous, 25 mhz clock is recovered from received network traffic. this signal must be pulled to vcc when idle. one 1 k w pull-up resistor on both sides of a 245 buffer is recommended. 41 irden output ttl, od irb driver enable. this output provides directional control for an external bidirectional transceiver (245) used to buffer the 100 mbps irb in multi- board applications. it must be pulled up by a 330 w resistor. when there are multiple devices on one board, tie all irden outputs together. if irden is tied directly to the dir pin on a 245, attach the on-board irdat, irclk and irdv signals to the b side of the 245, and connect the off-board signals to the a side of the 245. 42 irdv i/o cmos schmitt od, pu irb data valid. an active low signal indicating repeater port activity. irdv frames the clock and data of the packet on the backplane. this signal requires a 120 w pull-up resistor. 36 ircfs i/o analog irb collision force sense. this three-level signal determines the number of active ports on the logical repeater. high level (5v) indicates no ports active; mid-level (approx. 2.8v) indicates one port active; low level (0v) indicates more than one port active, resulting in a collision. ircfs connects between chips on the same board. do not connect between boards. this signal requires a 240 w pull-up resistor. 37 ircfsbp i/o analog nc irb collision force sense - backplane. a three-level signal that functions the same as ircfs ; however, ircfspb connects between chips with chipid = 0, on different boards. this signal requires a single 91w pull-up resistor on each stack. 38 irsngl i/o cmos schmitt, pu irb single driver state. this active low signal is asserted by the device with fps low when a packet is being received from one or more ports. it should not be connected between boards. 40 ircol i/o cmos schmitt, pu irb multiple driver state. this active low signal is asserted by the device with fps low when a packet is being received from more than one port (collision). it should not be connected between boards. 1. nc = no clamp. pad will not clamp input in the absence of power. pu = input contains pull-up pd = input contains pull-down i/o = input / output od = open drain 2. even if the irb is not used, required pull-up resistors must be installed as listed above.
9 lxt982/982a pin assignments and signal descriptions table 7: led signal descriptions pin symbol type description 208 207 ledsel0 ledsel1 input ttl, pd led mode select . must be static. 00 = mode 1, 01 = mode 2, 10 = mode 3 181 177 173 166 162 port1_led1 port2_led1 port3_led1 port4_led1 port5_led1 output ttl led driver 1 - ports 1 through 5. programmable led driver. active low. see per port leds on page 14. 180 176 172 165 161 port1_led2 port2_led2 port3_led2 port4_led2 port5_led2 output, ttl led driver 2 - ports 1 through 5. programmable led driver. active low. see per port leds on page 14. 86 col_led output, ttl collision led driver. active low indicates collisions. 91 act_led output, ttl activity led driver. active low indicates activity. 1. ttl = transistor-to-transistor logic. table 8: power supply and indication signal descriptions pin symbol type description 12, 28, 35, 51, 57, 76, 84, 89, 96, 170, 182, 184, 186, 188, 201, 203-206 vcc digital power supply inputs. each of these pins must be connected to a common +5 vdc power supply. a de-coupling capacitor to digital ground should be supplied for every one of these pins. 2, 11, 34, 50, 72-75, 82, 83, 88, 93, 158, 159, 163, 167, 174, 178, 200, 202 gnd digital ground. connect each of these pins to ground. for lxt982, chip id 1 is pin 72; chip id 2 is pin 73. if using an lxt982 device in an lxt981-based design, these pins do not have to be tied to ground. 94, 169 vccv analog vco supply inputs. each of these pins must be connected to a common +5 vdc power supply. a de-coupling capacitor to gndv should be supplied for every one of these pins. 95, 168 gndv analog vco ground . 111, 124, 139, 152 vcct analog transmitter supply inputs. each of these pins must be connected to a common +5 vdc power supply. a de-coupling capacitor to gndt should be supplied for every one of these pins.
lxt982/982a single-speed, 5-port fast ethernet repeater 10 109, 122, 137, 150 gndt analog transmitter ground. 107, 120, 135, 148 vccr analog receiver supply inputs. each of these pins must be connected to a common +5 vdc power supply. a de-coupling capacitor to gndr should be supplied for every one of these pins 104, 117, 132, 145, gndr analog receiver ground. 131 rbias analog rbias. used to provide bias current for internal circuitry. the 100 m a bias current is provided through an external 22.1 k w, 1% resistor to gnda. 27, 130 gnda analog analog ground. table 9: miscellaneous signal descriptions pin symbol type description 53 reset input cmos schmitt, nc reset. this active low input causes internal circuits, state machines and counters to reset (address tracking registers do not reset). on power-up, devices should not be brought out of reset until the power supply has stabilized and reached 4.5 v. when there are multiple devices, it is recommended that all be supplied by a common reset that is driven by an ls14 or similar device. 54 clk25 input cmos schmitt 25 mhz system clock. drive with mos levels. 71 fps input, ttl first position select. set low for first device on pcb. set high for all other devices on pcb. if using an lxt982 device in an lxt981-based design, fps is analogous to chip id 0 on the lxt981. 1, 3-10, 15, 23, 31, 39, 47, 48, 55, 56, 58-70, 77-81, 85, 87, 90, 92, 97, 98, 100-103, 160, 164, 171, 175, 179, 190-199 nc - no connects. leave these pins unconnected. 1. nc = no clamp. pad will not clamp input in the absence of power. table 8: power supply and indication signal descriptions C continued pin symbol type description
lxt982/982a functional description 11 functional description introduction as a fully integrated ieee 802.3 repeater capable of 100 mbps functionality, the lxt982 is a very versatile device allowing great flexibility in ethernet design solutions. figure 2 shows a typical application, and figure 3 shows a more complete i/o circuit. refer to application information (page 19) for specific circuit implementations. this multi-port repeater provides four 100base-tx/ 100base-fx ports. in addition, there is a bidirectional media independent interface (mii) expansion port that may be connected to either a 100 mbps mac, or to a 100 mbps phy. the lxt982 provides a repeater state machine and an inter-repeater backplane (irb). the 100 mbps repeater fully meets ieee 802.3 class ii requirements. port configuration the lxt982 reads the hardware configuration pins at power-up, hardware reset or software reset (but not at repeater reset), to determine operating conditions for each of its ports. each of the four media ports has its own configuration pin (port n _sel) to select 100tx or 100fx operation (high = tx, low = fx). interface descriptions 100base-tx interface the twisted-pair interface for each port consists of two differential signal pairs ? one for transmit and one for receive. the transmit signal pair is tpop/tpon, the receive signal pair is tpip/tpin. refer to table 2 for 100base-t port pin assignments and signal descriptions. the twisted-pair interface for a given port is always enabled except when 100fx is selected. figure 2: typical repeater architectures lxt982 100base-t repeater mii led drivers 100 mbps e'net phy 100 mbps e'net phy 100 mbps e'net phy 100 mbps e'net phy 100 mbps backplane lxt982 100base-t repeater mii led drivers 100 mbps e'net phy 100 mbps e'net phy 100 mbps e'net phy 100 mbps e'net phy 100 mbps backplane lxt982 100base-t repeater mii led drivers 100 mbps e'net phy 100 mbps e'net phy 100 mbps e'net phy 100 mbps e'net phy 100 mbps backplane led banks 100m backplane 100m backplane buffer chassis backplane
12 lxt982/982a single-speed, 5-port fast ethernet repeater the transmitter is current driven and requires magnetics with 2:1 turns ratio. a 400 w resistive load should be placed across the tpop/n pair, in parallel with the magnetics. the center tap of the primary side of the transmit winding must be tied to a quiet vcc for proper operation. when the twisted-pair interface is disabled, the transmitter outputs are tri-stated. the receiver requires magnetics with a 1:1 turns ratio, and a load of 100 w . when the twisted-pair port is enabled, the receiver actively biases its inputs to approximately 2.8v. when the twisted-pair interface is disabled, no biasing is provided. a 4 k w load is always present across the tpip/tpin pair. the lxt982 sends and receives a continuous, scrambled 125mbaud mlt-3 waveform on this interface. in the absence of data, idle symbols are sent and received in order to keep the link up. 100base-fx interface each fiber interface consists of the fibop/fibon (transmit) and fibip/fibin (receive) signal pair. refer to table 3 for 100base-fx port pin assignments and signal descriptions. each interface also provides a signal detect input that can be tied to the corresponding output on the fiber transceiver for determining signal presence and quality. figure 3: typical application block diagram tpop1 tpon1 tpip1 tpin1 tp2 tp3 tp4 xfmrs rj45s resistor pack vcc irsngl irdat irclk irden ircfs irdv ircol ircfsbp '245 inter- module irb to stack connector local irb to on- board lxt982 per port leds lxt982 4 100 m tp ports port1_led1 port1_led2 port2_led1 port2_led2 port3_led1 port3_led2 port4_led1 port4_led2 port5_led1 port5_led2 fibop1 fibon1 fibip1 fibin1 fo2 fo3 fo4 fiber module 4 100 m fo ports sigdet1 col_led act_led mii_txclk mii_txd<3:0> mii_rxclk mii_rxd<3:0> mii_rxdv mii_rxer mii_col mii (port 5, phy mode) mii_txen mii_crs mii_txer
13 lxt982/982a functional description the transmit pair is biased to approximately 1.5v and generally must be ac-coupled to the transceiver. the receive pair will accommodate an input bias in the 2v- 5v range, and can be dc-coupled to the transceiver. refer to figure 10 on page 24 for a typical interface circuit. the fiber interface for each port is enabled when the mode select is set to 100fx, and is disabled in all other cases. when a fiber port is disabled, its outputs are pulled to ground, and its inputs are tri-stated. the input and output pins on unused fiber ports may be left unconnected. each fiber port transmits and receives a continuous, 1v peak-to-peak, non-scrambled, nrzi waveform. the lxt982 does not support scrambling on the fiber interface. remote fault reporting the sd pin detects signal quality and reports a remote fault if the signal quality starts to degrade. loss of signal quality will also block any further data from being received and causes loss of the link. the remote fault code consists of 84 consecutive 1s followed by a single 0, and is transmitted at least three times. the lxt982 transmits the remote fault code when both of the following conditions are true: ? fiber mode is selected. ? signal detect indicates no signal, or the receive pll cannot lock. media independent interface the lxt982 supports a standard media independent interface (mii) interface. this interface can be programmed to operate either as the phy side of the interface (phy mode) or as the mac side of the interface (mac mode). the mii always operates as a nibble-wide (4b) interface. symbol mode (5b interface) is not supported on the lxt982 mii. note: the mii does not auto-negotiate, auto-speed select, or partition. inter-repeater backplane the lxt982 provides an inter-repeater backplane (irb) that allows multiple cascaded lxt982 devices to function as one large repeater. up to 240 ports can be supported in a single cascade (192 tp ports + 48 mii ports). this provides support for stackable and modular hub architectures. refer to table 6 for irb pin assignments and signal descriptions. repeater operation the lxt982 contains a complete 100 mbps repeater state machine that is fully ieee 802.3 class ii compliant. multiple lxt982s can be cascaded on the irb and operate as one repeater segment. data from any port will be forwarded to any other port in the cascade. the irb is a 5-bit symbol-mode interface. it is designed to be stackable. the lxt982 performs the following 100 mbps repeater functions: ? signal amplification, wave-shape restoration, and data-frame forwarding. ? handling received code violations. the lxt982 substitutes the h symbol for all invalid received codes. ? sop, soj, eop, eoj delay <46 bt (class ii compliant). ? collision enforcement. during a collision, the lxt982 drives a 1010 jam signal (encoded as data 5 on tx links) to all ports until the collision ends. there is no minimum enforcement time. ? partition. the lxt982 partitions any port that participates in excess of 60 consecutive collisions or one collision that is approximately 575.2 m s long. once partitioned, the lxt982 continues monitoring and transmitting to the port, but will not repeat data received from the port until it properly unpartitions. ? un-partition. the lxt982 un-partitions a port only when data can be transmitted to the port for 450-560 bit times without a collision on that port. ? isolate. the lxt982 will isolate any port that transmit more than two successive false carrier events. a false carrier event is defined as a packet that does not start with a /j/k symbol pair. note: this is not the same function as the irb isolate function, which involves segmenting the backplane. ? un-isolate. the lxt982 will un-isolate a port that remains in the idle state for 33000 +/- 25% bt or that receives a valid frame at least 450-500bt in length. ? jabber. the lxt982 ignores any receiver that remains active for more than 57,500 bit times. the lxt982 exits this state when all jabbering receivers return to the idle condition. the isolate and symbol error functions do not apply to the mii port.
lxt982/982a single-speed, 5-port fast ethernet repeater 14 requirements power the lxt982 has four types of +5v power supply input pins (vcc, vccv, vccr, and vcct). these inputs may be supplied from a single power supply although ferrites should be used to filter the analog and digital power planes. as a matter of good practice, these supplies should be as clean as possible. specific operating recommendations are shown in the test specifications section, table 15 on page 27. each supply input should be decoupled to its respective ground. refer to table 6 on page 8 for power and ground pin assignments, and to the design recommendations section on page 19. clock a stable, external 25 mhz system clock source (cmos) is required by the lxt982. this is connected to the clk25 pin. refer to test specifications, table 16 on page 27, for clock input requirements. bias current the lxt982 requires a 22.1 k w, 1% resistor connecting its rbias input to ground. reset at power-up, the reset input must be held low until vcc reaches at least 4.5v. an ls14 or equivalent should be used to drive reset if there are multiple lxt982 devices. refer to figure 13 on page 26 for circuit details. irb bus pull-ups even when the lxt982 is used in a stand-alone configuration, pull-up resistors are required on the following irb signals: ircfs, ircfsbp, irclk, and irdv. refer to table 6 for irb pin assignments and signal descriptions. see figure 12 on page 26 for sample circuits. led operation the lxt982 provides 2 mode-selectable per-port led drivers (10 total), and 2 global led drivers. refer to table 7 for led interface pin assignments and signal descriptions. power-up and reset conditions during reset or power-up, all leds turn on solid and remain on for approx. 2 seconds after reset goes away. per port leds the per port leds apply to the four twisted-pair ports and the mii port. the lxt982 has 2 led driver pins for each port as described in table 7. these pins can drive standard leds (see table 10). global leds these outputs can directly drive leds to indicate activity and collision status. pulse stretchers extend the on-time for these leds. collision led the collision led will turn on for approximately 120 m s when the lxt982 detects a collision. during the time that the collision led is on, any additional collisions will be ignored by the collision led logic. activity led the activity led will turn on for approximately 4 ms when the lxt982 detects any activity. during the time that the activity led is on, any additional activity will be ignored by the activity led logic. table 10: led indicators (per port) mode port led led state indication 1 1 on link is good, port is not par- titioned and not isolated. 2 on link is good and port is par- titioned or isolated. 21 on steady port enabled, link is good, port is not partitioned and not isolated. 1.6s blink link is good, port enabled, (partitioned or isolated). 2offalways off. 3 1 on link is good, and port is not isolated and not partitioned. 2 on 20 ms pulse for receive activity on port. 3 on link is good and port is par- titioned or isolated.
lxt982/982a functional description 15 irb operation the inter repeater backplane (irb) allows multiple devices to operate as a single logical repeater, exchanging data collision status information. this backplane uses a combination of digital and analog signals. irb signals can be characterized by connection type as local (connected between devices on the same board), stack (connected between boards) or full (connected between devices on the same board and between different boards). refer to tables 11 and 12 for details on buffering and pull-up require- ments, and to figure 12 on page 26 for application cir- cuitry. irb isolation the isolate output is provided to control the enable pin of an external bidirectional transceiver. in multi-board applications, it can be used to isolate one board from the rest of the system. only one device (the device with fps low) can control these signals. the output states of this pin are controlled by the internal repeater state machine. inter-board analog signals are isolated internally by the device. if an lxt982 device is used in an lxt981-based design, chip id 0 of the lxt981 is renamed fps for the lxt982. table 11: irb signal types connection type connections between devices (same board) connections between boards full connect all. connect using buffers. local connect all. do not connect. stack for devices with fps high, pull-up at each device and do not interconnect. connect devices with fps low between boards. use one pull-up resistor per stack. special (xxiso) for devices with fps high, leave open. for device with fps low, connect to buffer enable. do not connect. table 12: irb signal details name pad type buffer pull-up connection type irdat<4:0> digital yes no full irclk digital yes 1 k w full irdv digital, open drain yes 120 w full ircfs analog no 240 w , 1% local ircfsbp analog no 91 w , 1% 2 stack ircol digitalnonolocal irsngl digitalnonolocal irden digital, open drain n/a 1 330 w local iriso digital n/a 1 no special 1. isolate and driver enable signals are provided to control an external bidirectional transceiver. 2. 91 w resistors provide greater noise immunity. systems using 91 w resistors are backwards stackable with systems using 100 w resistors.
lxt982/982a single-speed, 5-port fast ethernet repeater 16 figure 4: irb block diagram digital irb signals include irdat, irden and irclk. local analog irb signals include ircol, irsngl and ircfs. inter-board analog irb signals include ircfsbp. hub board 1 hub board 2 hub board n '245 lxt982 lxt982 lxt982 digital irb signals analog irb signals irden '245 lxt982 lxt982 lxt982 digital irb signals analog irb signals irden '245 lxt982 lxt982 lxt982 digital irb signals analog irb signals irden
lxt982/982a functional description 17 mii port operation the lxt982 mii allows a mac or phy to directly connect into the repeater environment. the lxt982 can emulate either the phy (phy mode) or mac (mac mode) side of the mii as shown in figure 5. mode control is provided via the port5_sel pin (high = phy mode, low = mac mode). phy mode operation phy mode allows the lxt982 to interface to a 100 mbps mac. the lxt982 passes the full 56 bits of preamble through before sending the sfd. mac mode operation mac mode allows the user to attach an additional phy to the lxt982. in this mode the phy provides both mii_txclk and mii_rxclk. the mii_txclk must be frequency-locked to the 25 mhz oscillator used by the lxt982. the lxt982 does not provide an elasticity buffer to compensate for frequency differences. when operating in mac mode, the lxt982 generates the full 56 bits of preamble before sending the sfd across the mii. mii port timing considerations the ieee 802.3u specification provides propagation delay constraints for standard phy devices in section 24.6, and for repeater devices in section 27. the lxt982 mii port is a hybrid that does not fit either of these categories. the critical consideration that applies to the lxt982 mii port is the overall end-to-end system propagation delay (132 bit times maximum). the lxt982 supports the intent of the class ii repeater application. figure 6 summarizes the propagation delay issues relevant to the lxt982 mii port. figure 5: mii (port 5) operation mii_txd<3:0> mii_txen mii_txer mii_txclk mii_rxclk mii_rxd<3:0> mii_rxdv mii_rxer mii_crs mii_col mii_txclk mii_rxclk mii_rxd<3:0> mii_rxdv mii_rxer mii_txd<3:0> mii_txen mii_txer mii_crs mii_col lxt982 mac phy the lxt982 mii port is revers- ible. when phy mode is selected, the lxt982 acts as the phy side of the mii. in this mode an external mac sends txdata to the lxt982 to be repeated to the network. the lxt982 re- peats network data to the mac via the rxdata lines. when mac mode is selected, the lxt982 acts as the mac side of the mii. in this mode the lxt982 repeats network data to the phy via the tx data lines. port 1 port 2 port 3 port 4 port 5 phy mode tp mii port lxt982 port 1 port 2 port 3 port 4 port 5 mac mode tp mii port
18 lxt982/982a single-speed, 5-port fast ethernet repeater the lxt982 architecture treats the mii port as a fifth repeater port. the timing delay (latency) from the mii port to any other port meets the requirements for a class ii repeater ( 46 bt). it does not meet the requirements for a standard mii-phy interface (20 - 24 bt). when operating in mac mode with a phy connected to the lxt982 mii port (figure 6b), the fifth tp port does not have the latency characteristics of a class ii repeater with respect to the other ports. with a mac connected to the lxt982 mii port (figure 6d), the maximum latency to any other mac is 112 bt (not including cable delay). the mac connected to the lxt982 has an advantage relative to other macs because it has one less transceiver delay. figure 6: mii timing issues a c b d mii tp phy prop delay 20 bt mac mii tp phy prop delay 20 bt mac class ii rptr prop delay 46 bt tp mii* mac class ii rptr prop delay 46 bt mii tp phy prop delay 20 bt mac mii tp phy prop delay 20 bt mac class ii rptr prop delay 46 bt tp mii* class ii rptr prop delay 46 bt phy prop delay 20 bt prop delay 112 bt tp tp tp lxt982 port 5 (mii) operating in mac mode, connected to a phy device. tp ports phy lxt982 meets class ii rptr prop delay ( 46 bt ) tp port mii port does not meet class ii rptr prop delay p1 p2 p3 p4 p5 mii port mii tp phy prop delay 20 bt mac mii tp phy prop delay 20 bt mac class ii rptr prop delay 46 bt class ii rptr prop delay 46 bt mii-to-mii prop delay 132 bt tp propagation delay requirements per ieee 802.3u: - phy prop delay (mii-tp) must be 20 bt - class ii repeater prop delay (tp-tp) must be 46 bt lxt982 port 5 (mii) operating in phy mode, connected to a mac device. phy-to-mac prop delay 132 bt
19 lxt982/982a application information application information design recommendations the lxt982 has been designed to comply with ieee requirements and to provide outstanding receive ber and long-line-length performance. lab testing has shown that the lxt982 can perform well beyond the required distance of 100m. as with any finely crafted device, reaping the full benefits of the lxt982 requires attention to detail and good design practice. general design guidelines adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. up to 50 mv of noise is considered acceptable. 50 to 80 mv of noise is considered marginal. high-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: ? fill in unused areas of the signal planes with solid copper and attach them with vias to a vcc or ground plane that is not located adjacent to the signal layer. ? use ample bulk and decoupling capacitors throughout the design (a value of .01 m f is recommended for decoupling caps). ? provide ample power and ground planes. ? provide termination on all high-speed switching signals and clock lines. ? provide impedance matching on long traces to prevent reflections. ? route high-speed signals next to a continuous, unbroken ground plane. ? filter and shield dc-dc converters, oscillators, etc. ? do not route any digital signals between the lxt982 and the rj45 connectors at the edge of the board. ? do not extend any circuit power or ground plane past the center of the magnetics or to the edge of the board. use this area for chassis ground, or leave it void. power supply filtering power supply ripple and digital switching noise on the vcc plane can cause emi problems and degrade line performance. it is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having these problems: ? poorly-regulated or over-burdened power supplies. ? wide data busses (>32-bits) running at a high clock rate. ? dc-to-dc converters. many of these issues can be improved just by following good general design guidelines. in addition, level one also recommends filtering between the power supply and the analog vcc pins of the lxt982. filtering has two benefits. first, it keeps digital switching noise out of the analog circuitry inside the lxt982, which helps line performance. second, if the vcc planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing emi problems. the recommended implementation is to divide the vcc plane into two sections. the digital section supplies power to the digital vcc pin, mii vcc pin, and to the external components. the analog section supplies power to vcch, vcct, and vccr pins of the lxt982. the break between the two planes should run under the device. in designs with more than one lxt982, a single continuous analog vcc plane can be used to supply them all. the digital and analog vcc planes should be joined at one or more points by ferrite beads. the beads should produce at least a 100 w impedance at 100 mhz. the beads should be placed so that current flow is evenly distributed. the maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. each lxt982 draws a maximum of 500 ma from the analog supply so beads rated at 750 ma should be used. a bulk cap (2.2 -10 m f) should be placed on each side of each ferrite bead to stop switching noise from traveling through the ferrite. in addition, a high-frequency bypass cap (.01 m f) should be placed near each analog vcc pin. ground noise the best approach to minimize ground noise is strict use of good general design guidelines and by filtering the vcc plane.
lxt982/982a single-speed, 5-port fast ethernet repeater 20 power and ground plane layout considerations great care needs to be taken when laying out the power and ground planes. the following guidelines are recommended: ? follow the guidelines in the lxt980 design and lay- out guide for locating the split between the digital and analog vcc planes. ? keep the digital vcc plane away from the tpop/n and tpip/n signals, away from the magnetics, and away from the rj45 connectors. ? place the layers so that the tpop/n and tpip/n sig- nals can be routed near or next to the ground plane. for emi reasons, it is more important to shield tpop and tpip/n. chassis ground for esd reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. chassis ground should extend from the rj45 connectors to the magnetics, and can be used to terminate unused signal pairs (bob smith termination). in single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kv isolation capacitor. in multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kv isolation to the bob smith termination. mii terminations series termination resistors are recommended on all mii signals driven by the lxt982. the proper value equals nominal trace impedance minus 13 w . if the nominal trace impedance is not known, use 55 w . the rbias pin the lxt982 requires a 22.1 k w, 1% resistor directly con- nected between the rbias pin and ground. place the rbias resistor as close to the rbias pin as possible. run an etch directly from the pin to the resistor, and sink the other side of the resistor to a ground. surround the rbias trace with a ground; do not run high-speed signals next to rbias. the twisted-pair interface because the lxt982 transmitter uses 2:1 magnetics, sys- tem designers must take extra precautions to minimize par- asitic shunt capacitance in order to meet return loss specifications. these steps include: ? use compensating inductor in the output stage (see figure 11). ? place magnetics as close as possible to the lxt982. ? keep transmit pair traces short. ? do not route transmit pair adjacent to a ground plane. if possible, eliminate planes under the transmit traces completely. otherwise, keep planes 3-4 layers away. ? some magnetic vendors are producing magnetics with higher than average return loss performance. use of these improved magnetics increases the return loss budget available to the system designer. ? improve emi performance by filtering the output centertap. a single ferrite bead may be used to supply centertap current to all four ports. in addition, follow all the standard guidelines for a twisted- pair interface: ? route the signal pairs differentially, close together. allow nothing to come between them. ? keep distances as short as possible; both traces should have the same length. ? avoid vias and layer changes as much as possible. ? keep the transmit and receive pairs apart to avoid cross-talk. ? if possible, place entire receive termination network on one side and transmit on the other. ? keep termination circuits close together and on the same side of the board. ? always put termination circuits close to the source end of any circuit. ? bypass common-mode noise to ground on the in- board side of the magnetics using 0.01 m f capacitors. the fiber interface the fiber interface consists of a pseudo-ecl (pecl) trans- mit and receive pair to an external fiber optic transceiver. the transmit pair should be ac coupled to the transceiver, and biased to 3.7v with a 50 w equivalent impedance. the receive pair can be dc-coupled, and should be biased to 3.0v with a 50 w equivalent impedance. figure 10 on page 24 shows the correct bias networks to achieve these requirements.
21 lxt982/982a application information magnetics information the lxt982 requires a 1:1 ratio for the receive transform- ers and a 2:1 ratio for the transmit transformers. the trans- former isolation voltage should be rated at 2 kv to protect the circuitry from static voltages across the connectors and cables. refer to tables 13 for specifications. refer to mag- netic manufacturers for networking product applications (app. note 73) for a reference list of compatible magnetic components from various manufacturers. before commit- ting to a specific component, designers should test and val- idate the magnetics in the specific application to verify that system requirements are met. table 13: magnetics specifications parameter min nom max units test condition rx turns ratio C 1 : 1 C C tx turns ratio C 2 : 1 C C insertion loss 0.0 C 1.1 db 80 mhz primary inductance 350 C C m h transformer isolation C 2 C kv differential to common mode rejection C C -40 db .1 to 60 mhz C C -35 db 60 to 100 mhz return loss - standard C C -16 db 30 mhz C C -10 db 80 mhz return loss - improved C C -20 db 30 mhz C C -15 db 80 mhz
lxt982/982a single-speed, 5-port fast ethernet repeater 22 typical application circuitry figures 7 and 8 are simplified block diagrams showing typical applications. figures 9 through 13 show application circuitry details. figure 7: typical repeater stack figure 8: hybrid switch/repeater application tp/fiber ports 16 100-x ports tp/fiber ports leds 100m irb 100m irb mii inter-repeater backplanes mii leds tp/fiber ports tp/fiber ports leds 100m irb 100m irb mii inter-repeater backplanes mii leds lxt982 lxt982 lxt982 lxt982 16 100-x ports tp/fiber ports mii 100m irb ethernet switch memory control tp/fiber ports mii 100m irb tp/fiber ports mii 100m irb tp/fiber ports mii 100m irb 100 mbps mac 100 mbps mac 100 mbps mac 100 mbps mac lxt982 lxt982 lxt982 lxt982
23 lxt982/982a application information figure 9: power and ground connections rbias vccv gndv gnda vccr gndr .01 m f 22.1 k w 1% gnd vcc 0.1 m f + ferrite beads 10 m f +5v lxt982 vcct gndt 10 m f .01 m f .1 m f .1 m f digital supply plane analog supply plane .01 m f .1 m f to output magnetics centertap
lxt982/982a single-speed, 5-port fast ethernet repeater 24 figure 10: typical fiber port interface fibon n 191 : fibop n fibin n fibip n 191 : 69 : 69 : fiber txcvr to fiber network 0.1 p f 130 : 130 : 80 : 80 : +5 v 0.1 p f td td rd rd 3 0.01 m f 0.01 m f gnda gnda gnda gnda vccr 1 vcct +5 v 2 sigdet n lxt982 1. suggested supply layout for fiber-only applications. in combination twisted-pair and fiber applications, use vccd/gndd. 2. if the fiber interface is not used, fibin, fibip, fibon, fibop and sigdet may be left unconnected. 3. refer to fiber transceiver manufacturers recommendations for termination circuitry. suitable fiber transceivers include the hfbr-5103 and hfbr-5105.
25 lxt982/982a application information figure 11: typical twisted-pair port interface 1. receiver common mode bypass cap may improve ber performance in systems with noisy power supplies. 2. a single ferrite bead may be used to supply center tap current to all 4 ports. tpip tpin rj45 tpop tpon 75 w vcct gndt 75 w 0.1 m f 0.001 m f/2kv .01 m f 1 50 w 1% 50 w 1% 0.1 m f gndr to twisted-pair network 3 6 1 2 1:1 2:1 lxt982 output stage with compensating inductor 200 w 1% 200 w 1% 320 nh 50 w 50 w 50 w 50 w 50 w 50 w 4 5 8 7 2
lxt982/982a single-speed, 5-port fast ethernet repeater 26 figure 12: typical irb implementation figure 13: typical reset circuit lxt982 chip id 1 lxt982 chip id 2 +5v 240 w 1% 120 w irdv\ irdat <4:0> ircfs\ ircol\ irsngl '245 irdatbp irdvbp\ dir ena irclkbp ab lxt982 chip id 0 ircfsbp\ irden\ isolate 91 w 1%* +5v 330 w irclk irden\ irdv\ irdat stack or segment connector ircfsbp\ +5v 91 w 91 w 2 1 +5v 1 k w +5v 1 k w vcc c r1 r2 '14 t(cr1) > power supply ramp up time r2 discharges c when supply goes away. '14 needed for multiple lxt982s. d 1. in stacked configurations, all devices with ffs = low are tied together at ir10cfsbp . the entire stack must be pulled up by only one resis- tor per signal. pull-up resistors are installed in the base board only. 2. all devices with fps = high require individual pull-up resistors at ircfsbp . 91 w resistors provide greater noise immunity. systems using 91 w resistors are backwards stackable with systems using 100 w resistors.
27 lxt982/982a test specifications test specifications note tables 14 through 30 and figures 14 through 23 represent the performance specifications of the lxt982/982a and are guaranteed by test except, where noted, by design. the minimum and maximum values listed in tables 16 through 30 are guaranteed over the recommended operating conditions specified in table 15 table 14: absolute maximum ratings parameter symbol min max units supply voltage v cc -0.3 6 v operating temperature ambient t opa -15 +80 oc case t opc C+130oc storage temperature t st -65 +150 oc caution exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 15: operating conditions parameter sym min typ max units recommended supply voltage v cc 4.75 5.0 5.25 v v ccv 4.75 5.0 5.25 v v ccr 4.75 5.0 5.25 v v cct 4.75 5.0 5.25 v recommended operating temperature ambient t opa 0C70c case t opc 0C115c power consumption 100base-tx, 4 ports active p c CC3.5w 100base-fx, 4 ports active p c CC3.0w table 16: input clock requirements parameter 1 min typ 2 max units frequency C 25 C mhz frequency tolerance C C 100 ppm duty cycle 40 C 60 % 1. this table lists requirements which apply to the external clock supplied to the lxt982, not to lxt982 test specifications. 2. typical values are at 25c and are for design aid only. not guaranteed and not subject to production testing.
lxt982/982a single-speed, 5-port fast ethernet repeater 28 table 17: i/o electrical characteristics parameter sym min typ 1 max units test conditions input low voltage v il C C 0.8 v ttl inputs CC30% v cc cmos inputs 2 CC1.0v schmitt triggers 3 input high voltage v ih 2.0 C C v ttl inputs 70 C C % v cc cmos inputs 2 v cc -1.0 C C v schmitt triggers 3 hysteresis voltage C 1.0 C C v schmitt triggers 3 output low voltage v ol CC0.4vi ol = 1.6 ma output low voltage (led) v oll CC1.0vi oll = 10 ma output high voltage v oh 2.4 C C v i oh = 40 m a input low current i il -100 C C m aC input high current i ih CC100 m aC output rise / fall time C C 3 10 ns c l = 15 pf 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. does not apply to irb pins. refer to table 18 for irb i/o characteristics. 3. applies to reset and clk25 pins only. table 18: 100 mbps irb electrical characteristics parameter symbol min typ 1 max units test conditions output low voltage v ol C.3.7vr l = 330 w output rise or fall time t rf C410nsc l = 15 pf input high voltage v ih v cc - 2.0 C C v cmos inputs v cc - 1.0 C C v ir100clk (schmitt trigger) input low voltage v il C C 2.0 v cmos inputs C C 1.0 v ir100clk (schmitt trigger) hysteresis voltage C 1.0 C C v ir100clk (schmitt trigger) ircfs current single drive C 7.0 C 9.0 ma r l = 240 w collision C C C 20.5 ma r l = 240 w ircfsbp current single drive C 20.0 C 25.0 ma r l = 91 w 2 collision C C C 55.0 ma r l = 91 w 2 ircfsbp voltage single drive C 3.4 C 4.35 v C collision C 1.4 C 1.9 v C 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. 91 w resistors provide greater noise immunity. systems using 91 w resistors are backwards stackable with systems using 100 w resistors.
29 lxt982/982a test specifications table 19: 100base-tx transceiver electrical characteristics parameter symbol min typ 1 max units test conditions peak differential output voltage (single ended) v p 0.95 1.0 1.05 v note 2 signal amplitude symmetry C 98 C 102 % note 2 signal rise/fall time t rf 3.0 C 5.0 ns note 2 rise/fall time symmetry t rfs C C 0.5 ns note 2 duty cycle distortion C C C +/- 0.5 ns offset from 8 ns pulse width at 50% of pulse peak, overshoot v o CC5%C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. measured at line side of transformer, line replaced by 100 w ( 1%) resistor. table 20: 100base-fx transceiver electrical characteristics parameter symbol min typ 1 max units test conditions transmitter peak differential output voltage (single ended) v op 0.6 C 1.0 v C signal rise/fall time t rf C C 1.6 ns 10 <-> 90%, 2.0 pf load jitter (measured differentially) C C C 1.3 ns C receiver peak differential input voltage v ip 0.55 C 1.5 v C common mode input range v cmir 2.25 C v cc - 0.5 v C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
lxt982/982a single-speed, 5-port fast ethernet repeater 30 figure 14: 100 mbps port-to-port delay timing table 21: 100 mbps port-to-port delay timing parameters parameter sym min typ 1 max units 2 test conditions tpip/n or fibip/n to tpop/n or fibop/n, start of transmission t 1a CC46btC tpip/n or fibip/n to tpop/n or fibop/n, end of transmission t 1b CC46btC tpip/n or fibip/n collision to tpop/n or fibop/n, start of jam t 1c CC46btC tpip/n or fibip/n idle to tpop/n or fibop/n, end of jam t 1d CC46btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and the reciprocal of the bit rate. bt for 100base-t = 10 -8 s or 10 ns. tp / fib input #2 t 1c tp / fib input #1 tp / fib output jam t 1d t 1a tp / fib input tp / fib output t 1b normal propagation collision jamming
31 lxt982/982a test specifications figure 15: 100base-tx transmit timing - phy mode mii table 22: 100base-tx transmit timing parameters - phy mode mii parameter sym min typ 1 max units 2 test conditions txd, tx_en, tx_er setup to tx_clk high t 2a 10 C C ns C txd, tx_en, tx_er hold from tx_clk high t 2b 5CC nsC tx_en sampled to crs asserted t 2c 0C4btC tx_en sampled to crs de-asserted t 2d 0C16btC tx_en sampled to tpop/n active (tx latency) t 2e CC46btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and the reciprocal of the bit rate. bt for 100base-t = 10 -8 s or 10 ns. tx_clk txd, tx_en, tx_er crs tpop/n t 2a t 2b t 2c t 2d t 2e
lxt982/982a single-speed, 5-port fast ethernet repeater 32 figure 16: 100base-tx receive timing - phy mode mii table 23: 100base-tx receive timing parameters - phy mode mii parameter sym min typ 1 max units 2 test conditions tpip/n in to crs asserted t 3a CC46 bt C tpip/n quiet to crs de- asserted t 3b CC46 bt C crs asserted to rxd, rx_dv, rx_er t 3c 1C4 bt C crs de-asserted to rxd, rx_dv, rx_er de- asserted t 3d CC3 bt C rx_clk falling edge to rxd, rx_dv, rx_er valid t 3e CC10 ns C tpip/n in to col asserted t 3f CC46 bt C tpip/n quiet to col de- asserted t 3g CC46 bt C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and the reciprocal of the bit rate. bt for 100base-t = 10 -8 s or 10 ns. rx_clk rxd, rx_dv, rx_er crs tpip/n col t 3a t 3b t 3c t 3d t 3f t 3g t 3e
33 lxt982/982a test specifications figure 17: 100base-tx transmit timing - mac mode mii figure 18: 100base-tx receive timing - mac mode mii table 24: 100base-tx transmit timing parameters - mac mode mii parameter sym min typ 1 max units 2 test conditions rxd, rx_dv, rx_er setup to rx_clk high t 4a 10 C C ns C rxd, rx_dv, rx_er hold from rx_clk high t 4b 5C C nsC rxd sampled to tpo asserted t 4c CC 46 btC rxd sampled to tpo de-asserted t 4d CC 46 btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and the reciprocal of the bit rate. bt for 100base-t = 10 -8 s or 10 ns. table 25: 100base-tx receive timing - mac mode mii parameter sym min typ 1 max units 2 test conditions tpip/n in to txd, tx_en, tx_er t 5a CC46 btC tpip/n quiet to txd de-asserted t 5b 13C46 bt C tx_clk rising edge to txd, tx_en, tx_er valid t 5c 0 C 25 ns C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and the reciprocal of the bit rate. bt for 100base-t = 10 -8 s or 10 ns. rx_clk rxd, rx_dv, rx_er tpop/n t 4a t 4b t 4c t 4d tx_clk txd, tx_en, tx_er tpip/n t 5a t 5c t 5b
lxt982/982a single-speed, 5-port fast ethernet repeater 34 figure 19: 100base-fx transmit timing - phy mode mii table 26: 100base-fx transmit timing parameters - phy mode mii parameter sym min typ 1 max units 2 test conditions txd, tx_en, tx_er setup to tx_clk high t 6a 10 C C ns C txd, tx_en, tx_er hold from tx_clk high t 6b 5CC nsC tx_en sampled to crs asserted t 6c 0C4btC tx_en sampled to crs de-asserted t 6d 0C16btC tx_en sampled to fibop/n out (tx latency) t 6e CC46btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and the reciprocal of the bit rate. bt for 100base-t = 10 -8 s or 10 ns. tx_clk txd, tx_en, tx_er crs fibop/n t 6a t 6b t 6b t 6d t 6e
35 lxt982/982a test specifications figure 20: 100base-fx receive timing - phy mode mii table 27: 100base-fx receive timing - phy mode mii parameter sym min typ 1 max units 2 test conditions fibip/n in to crs asserted t 7a CC46 btC fibip/n quiet to crs de-asserted t 7b CC46 btC crs asserted to rxd, rx_dv, rx_er t 7c 1C4 btC crs de-asserted to rxd, rx_dv, rx_er de-asserted t 7d CC3 btC rx_clk falling edge to rxd, rx_dv, rx_er valid t 7e C C 10 ns C fibip/n in to col asserted t 7f CC46 btC fibip/n quiet to col de-asserted t 7g CC46 btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and the reciprocal of the bit rate. bt for 100base-t = 10 -8 s or 10 ns. rx_clk rxd, rx_dv, rx_er crs fibip/n col t 7a t 7b t 7c t 7d t 7f t 7g t 7e
lxt982/982a single-speed, 5-port fast ethernet repeater 36 figure 21: 100base-fx transmit timing - mac mode mii figure 22: 100base-fx receive timing - mac mode mii table 28: 100base-fx transmit timing - mac mode mii parameter sym min typ 1 max units 2 test conditions rxd, rx_dv, rx_er setup to rx_clk high t 8a 10 C C ns C rxd, rx_dv, rx_er hold from rx_clk high t 8b 5CC nsC rxd sampled to fibop/n asserted t 8c CC46btC rxd sampled to fibop/n de-asserted t 8d CC46btC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and the reciprocal of the bit rate. bt for 100base-t = 10 -8 s or 10 ns. table 29: 100base-fx receive timing - mac mode mii parameter sym min typ 1 max units test conditions fibip/n in to txd, tx_en, tx_er t9a C C 46 bt C fibip/n quiet to txd de-asserted t9b C C 46 bt C tx_clk rising edge to txd, tx_en, tx_er valid t9c 0 C 25 ns C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. rx_clk rxd, rx_dv, rx_er fibop/n t 8a t 8b t 8d t 8c tx_clk txd, tx_en, tx_er fibip/n t 9a t 9c t 9b
37 lxt982/982a test specifications figure 23: 100 mbps irb timing table 30: 100 mbps irb timing parameters 1 parameter sym min typ 1 max units 2 test conditions tpip/n or fibp/n to irdv low t 10a 18 24 30 bt C irdat to irclk setup time. t 10b C10C ns C irdat to irclk hold time. t 10c C0C ns C 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and the reciprocal of the bit rate. bt for 100base-t = 10 -8 s or 10 ns. tpip/n fibip/n ir100dv ir100cfs 1r100col ir100dat<4:0> t 10a t 10b ir100clk t 10c
lxt982/982a single-speed, 5-port fast ethernet repeater 38 mechanical specifications figure 24: package specifications dim millimeters min max a-4.10 a1 0.25 - a2 3.20 3.60 b 0.17 0.27 d 30.30 30.90 d 1 27.70 28.30 e 30.30 30.90 e 1 27.70 28.30 e .50 b asic l 0.50 0.75 l 1 1.30 ref q0 7 q 2 5 16 q 3 5 16 e / 2 a 1 a 2 l a b l 1 q 3 q 2 q d d 1 e e 1 e 208-pin plastic quad flat package ? part numbers ? lxt982qc ? lxT982AHC ? commercial temperature range (0 c to 70 c)
39 lxt982/982a revision history revision history this revision history assumes a baseline of revision 1.0. table 32: changes from rev. 1.0 to rev. 1.1 (12/98) table 31: changes from rev. 1.1 to rev. 1.2 (02/99) section page change description general description 1 add to the first paragraph, add the following sentence: this data sheet applies to all lxt982 products (lxt982, lxt982a, and any subse- quent variants), except as specifically noted. signal descriptions 5-10 modify add editorial clean-up: re-order, clarify information in type column. irb signal description 8 modify for ircfsbp signal, change pull-up resistor value from 82 w to 91 w . power supply signal desc. 9 rewrite gnd desc.: for lxt982, chip id 1 is pin 72; chip id 2 is pin 73. if using an lxt982 device in an lxt981-based design, these pins do not have to be tied to ground. misc. signal desc 10 add add to fps description: if using an lxt982 device in an lxt981- based design, fps is analogous to chip id 0 on the lxt981. led operation table 10 14 modify correct and re-write mode 2 and mode 3 indications. irb signal details table 12 15 for ircfsbp signal, change pull-up resistor value from 82 w to 91 w . typ. irb implementation fig. 12 26 correct figure 12 to include ircfsbp signals for chip id 1 and 2. add notes. for ircfsbp signal, change pull-up resistor value from 82 w to 91 w . correct notes 1,2: chipid = 0 should read ffs = low; chipid 1 0 should read fps = high. 100 mbps irb elect. char. 28 for ircfsbp signal, change pull-up resistor value from 82 w to 91 w . backpage 44 update. section page # change description cover page subtitle 1 delete remove and 10base-t applications from subtitle. features modify change 0 - 70 temperature range to case temperature range: 0 - 115?. 100m irb sigs table 6 8 add add schmitt mos pu to ir100sngl, ir100col, ir100dv, ir100dat<0:4>. add pd to ir100clk. add a 1 k w pull-up resistor to irclk line. modify rewrite and expand signal descriptions for irdv , ircfsbp , and ircfsbp .
lxt982/982a single-speed, 5-port fast ethernet repeater 40 power supply and indication signals table 8 9 modify replace - marks under type column with appropriate analog and digital indications. 10 change external resistor value from 22 k w to 22.1 k w . pin assignments/ misc. signals table 9 delete delete pins 182, 184, 186 & 188 from the no connect listing. these pins are correctly identified as vcc in figure 1 and in table 8. add add pins 48 and 100 to nc indicated listing. remote fault reporting 13 delete remove . . . sets the associated interrupts . . . phrase. repeater operation add the lxt982 partitions any port that participates in excess of . . .one collision that is approximately 575.2 m s long. bias current 14 modify change external resistor value from 22 k w to 22.1 k w . irb bus pull-ups 15 add add irclk to listing of irb signals requiring pull-up resistor. irb signals table 12 modify change no to yes in pull-up column for irclk. ircfsbp pull-up resister = 82 w mii port timing 17-18 modify rewrite to clarify mii port timing considerations section. figure 6 clarify mii-to-mii, phy-to-mac prop. delay graphics. general design guidelines entire section 19-20 update section, removing references to separate analog & digital ground planes and associated ferrite bead filter. rbias pin 20 modify rbias pin: change external resistor value from 22 k w to 22.1 k w . magnetics information table 13 21 update suggested magnetics list and magnetics specifications. move differential to cmr from min to max column; indicate as -40 and -35 for .1 to 60 mhz and 60 to 100 mhz, respectively. table 13 (former) 21 delete delete suggested magnetics list power and gnd connections figure 9 23 modify update per changes to general design guidelines section, removing elements showing separate analog & digital ground planes and associ- ated ferrite bead filter. twisted-pair i/f figure 11 25 correct reverse rj45 connections to show repeater i/f, not nic. should be: tpop = 3, tpon = 6 tpip = 1, tpin = 2 typical irb implementation figure 12 26 add add two 1 k w pull-up resistors to irclk signal line, on either side of the 245 buffer. modify ircfsbp pull-up resistor = 82 w section page # change description
41 lxt982/982a revision history . test specifications 27 modify delete re-write note; delete over recommended range from all table titles (17-30). absolute max ratings table 14 modify increase max case temp to 130. revise warning to address immediate eos damage. 100 mbps irb elect. char. 29 ircfsbp current test conditions rl value = 82 w test spec tables 21 - 30 30 - 38 modify clarify definition of bit times (bt) for both 10 and 100base-tx. this appears as a note to the unit column. change timing parameter symbol convention. test spec figures 14 - 23 modify figures to correspond to timing parameter convention changes. 100 irb timing table 30 figure 23 38 delete modify delete ir100ena asserted to tpop/n or fibop/n active and corre- sponding figure element. tpip/n or fibp/n to ir100dv low: change min, typ, and max val- ues. throughout all modify replace module with board where appropriate. all light editing throughout. backpage 42 update. section page # change description
lxt982/982a single-speed, 5-port fast ethernet repeater 42 notes
43 lxt982/982a notes notes
east west asia/pacific europe eastern area headquarters & northeastern regional office western area headquarters asia / pacific area headquarters european area headquarters 234 littleton road, unit 1a westford, ma 01886 usa tel: (978) 692-1193 fax: (978) 692-1124 3375 scott blvd., #110 santa clara, ca 95054 usa tel: (408) 496-1950 fax: (408) 496-1955 101 thomson road united square #08-01 singapore 307591 thailand tel: +65 353 6722 fax: +65 353 6711 parc technopolis-bat. zeta 3, avenue du canada - z.a. de courtaboeuf les ulis cedex 91974 france tel: +33 1 64 86 2828 fax: +33 1 60 92 0608 north central regional office south central regional office central asia/pacific regional office central and southern europe regional office one pierce place suite 500e itasca, il 60143 usa tel: (630) 250-6044 fax: (630) 250-6045 800 east campbell road suite 199 richardson, tx 75081 usa tel: (972) 680-5207 fax: (972) 680-5236 suite 305, 4f-3, no. 75, hsin tai wu road sec. 1, hsi-chih, taipei county, taiwan tel: +886 22 698 2525 fax: +886 22 698 3017 feringastrasse 6 d-85774 muenchen- unterfoerhring, germany tel: +49 89 99 216 375 fax: +49 89 99 216 319 southeastern regional office southwestern regional office northern asia/pacific regional office northern europe regional office 4020 westchase blvd suite 100 raleigh, nc 27607 usa tel: (919) 836-9798 fax: (919) 836-9818 28202 cabot road suite 300 laguna niguel, ca 92677 usa tel: (949) 365-5655 fax: (949) 365-5653 nishi-shinjuku, mizuma building 8f 3-3-13, nishi-shinjuku, shinjuku-ku tokyo, 160-0023 japan tel: +81 3 3347-8630 fax: +81 3 3347-8635 torshamnsgatan 35 164/40 kista/stockholm, sweden tel: +46 8 750 3980 fax: +46 8 750 3982 latin/south america 9750 goethe road sacramento, ca 95827 usa tel: (916) 855-5000 fax: (916) 854-1102 revision date status 1.2 02/99 document changes due to a8 design revisions. 1.1 12/98 additions to signal descriptions; correct pin assignments; correct twisted-pair i/f figure; change max. case temperature. 1.0 02/98 initial release, preliminary information. copyright ? 1999 level one communications, inc., an intel company. specifications subject to change without notice. all rights reserved. printed in the united states of america. ds-t982-r1.2-0299 this product is covered by one or more of the following patents. additional patents pending. the products listed in this publication are covered by one or more of the following patents. additional patents pending. 5,008,637; 5,028,888; 5,057,794; 5,059,924; 5,068,628; 5,077,529; 5,084,866; 5,148,427; 5,153,875; 5,157,690; 5,159,291; 5,162,746; 5,166,635; 5,181,228; 5,204,880; 5,249,183; 5,257,286; 5,267,269; 5,267,746; 5,461,661; 5,493,243; 5,534,863; 5,574,726; 5,581,585; 5,608,341; 5,671,249; 5,666,129; 5,701,099 corporate headquarters 9750 goethe road sacramento, california 95827 telephone: (916) 855-5000 fax: (916) 854-1101 web: www.level1.com international the americas

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