chip card & security sle 88c n f x 66 0 2 p 32 - bit security controller optimized for mobile nfc applications with high level of security 2 56 kb yte s rom 660 kb yte s flexible eeprom 32 kb yte s ram swp interface common criteria eal5+ ( high ) and em vco (targeted) short product information 12 . 20 0 9
important : further information is confidential and on request. please contact: infineon technologies ag in munich, germany, chip card & security e mail: security.chipcard.ics@infineon.com www.infineon.com/security publish ed by infineon technologies ag, 81726 munich, germany ? infineon technologies ag 200 9 all rights reserved. attentio n please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limit ed to warranties of non - infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please con tact your nearest infineon technologies office in germany or our infineon technologies representatives world - wide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in questi on please contact your nearest infineon technologies office. infineon technologies components may only be used in life - support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life - support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustai n and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
sle 88c n f x 660 2p short product information 3 / 9 12 .200 9 general features dedicated 32 - bit smart card core designed in cost - optimized 0.13 m technology pipelined 32 - bit ris c cpu with proprietary instruction set specific instructions for virtual machine implementation like java card u ltra low power consumption design very fast t ask s witching supported by hardware mechanism for pre - emptive multitasking support maxi mum performa nce cpu supplied by 2 cache memories for fast instruction fetch and data access in ternal clock generation up to 33 mhz intelligent power m anage r which adjusts automatically and efficiently the internal clock according to a dedicated power class secure multi - application with memory management and protection unit (mmu) 256 packages separated and secured by hardware firewalls data and code access controlled by hardware memory and peripherals access m anaged with hardware supervisor components memory 66 0 kb ytes eeprom flash functionality and free partitioning between code and data 8 kbytes reserved for emulation of up to 8 mifare? 1k cards 32 kbytes ram for local variables, buffers, and stacks 2 56 kbytes rom for user code memories encrypted by med (memory encryption/decryption) device memories protected by hardware error correction code interfaces smartcard uart for handling serial interface in accordance with iso/iec 7816 part 3 supporting tra nsmission protocols t=1 and t=0 , s upport of clock division factor of 8 (pps97 ) single wire protocol with baud rate up to 1.7 mbit/s, support of the clt protocol
sle 88c n f x 660 2p short product information 4 / 9 12 .200 9 eeprom technology very fast programming: write/e rase time < 2 ,3 ms flash functionality w ith 4k s ector flash and erase in one shot eeprom page programming from 1 to 128 byte s very high endurance: min. 500,000 write/erase cycles @ 25c per page max. 16,500,000 write/erase cycles @ 25c per 4k sector data retention: min. 10 years @ 25c securi ty features 32 - bit proprietary instruction set memory and cpu error detection memory - , bus - and sfr - encryption dpa / spa , dema / sema countermeasures incl. dual rail logic security sensors (v oltage , f requency , light , temperature , glitch ) active shield tr ue rng according to ais31 m emory management and protection unit with leve l concept chip id, unique chip identification number for each chip coprocessors and peripherals high performance crypto engine for pki, rsa, ec calculations 1408 - bit crypto engine dedicated 704 bytes of crypto - coprocessor ram optimized for rsa up to 2048 bit and for ecc up to 521 bit (gf(p) and gf(2 m )) hardware des accelerator for des and triple des calculations true random number generator for true random number generation pseudo random number generator for very fast random number generation three 16 - bit a uto r eload timers for protocol implementation, event monitoring crc hardware module for fast crc calculations required for e.g. in contact - less protocols
sle 88c n f x 660 2p short product information 5 / 9 12 .200 9 tools and support so ftware development kit, sdk 88 fpga based emulator (same as sle 7x emulator) flash samples for immediate test and validation, enabling short time - to - market ready to use low level software drivers (platform support layer) for peripherals, smartcard and cryp tographic software: t=0, t=1, rsa, des, aes, ec,? worldwide application engineer team & customer dedicated field application engineers . regular customer trainings on hardware & software tools , o n - site trainings available on request . document references hardware reference manual programmer?s refe re nce manual with complete set of application notes and program examples production and personalization manual for flash loading and production optimization chip qualification report chip delivery specification for wafer with chip - layout (die size, orientation, step size) module specification containing description of package module qualification report electrical characteristics external clock frequency: 1 to 10 mhz supply voltage range: 1.62 v to 5.5 v temp erature range: - 25c to +85c esd protection > 6 kv ( hbm) max. sleep mode current (typical) < 100 a in clock off mode supported standard iso/iec 7816 gsm 11.11, 11.12, 11.18 etsi ts 102 221 etsi ts 102 613 release 7
sle 88c n f x 660 2p short product information 6 / 9 12 .200 9 ordering information type package 1 voltage range temperature range frequency range (ext. clock frequency) sle 88 c nfx6602 p c die (sawn, unsawn) sle 88cnfx6602p mxxx m5. x mfc xxx 1.62 v - 5.5 v ? 25c to + 85c 1 mhz - 10 mhz 1 available as flip chip module (mfc), wire - bonde d module (m5) , die (c) for customer packaging flash initialization/personalization available upon request. for ordering information please contact your infineon local sales representative . pin description and packaging electrical characteristics pin symbol function v cc operating voltage rst reset input clk processor clock input gnd ground i/o iso7816 - 3 bi - directional da ta port swio single wire protocol (swp) interface data port v cc gnd clk i /o sle 88 cnfx6602p rst sw io m5.3 mfc5.3
sle 88c n f x 660 2p short product information 7 / 9 12 .200 9 general description the sle 88 products family is the infineon?s state of the art 32 - bit platform , designed in cost optimized 130nm technology, with: high s ecurity level enabling secure mul ti - application and multitasking high p erformance for sim/uicc applications with a fast internal frequency (33 - 66mhz) high quality eeprom with 500,000 cycles p rogramming endurance high flexibility with a freely configurable memory in code and data the sle 88 cnf x 6602p brings a significant layer of security and convenience to mobile applications based on nfc (near field communication). with its flash capability, it offer s a decisive time - to - market advantage to card vendors and service providers in the laun ch of gsm/uicc applications. technical description multistage 32 - bit cpu caches sensor s filter s active shield intelligent power manager scalable clk eeprom ram rom crypto engine & des accelerator trng 32 - bit bus med memory management and protection unit crc three 16 - bit timers prng uart swp
sle 88c n f x 660 2p short product information 8 / 9 12 .200 9 the sle 88 family fully meets the requirements for real multi - application operating systems . the advanced 0.13m technology, the integral security concept, the low pow er optimised 32 - bit core supported by various powerful peripherals, and the possibility to adapt the performance to application requirements establish the foundation for a completely new chip card generation. the high p erformance is en sured by the 32 - bit risc architecture that processes instructions and data 32 - bit wise supplied by 2 dedicated caches. a very efficient context/application switching mechanism allows fast switching between multiple tasks . an integral security concept , based on the entire int egration of security measures at each hardware and software des ign phase , has been used for the development of the sle 88 family. an in terrupt control u nit supports a programmable interrupt system with uart, timers , and the other peripherals as interrupt sources. a variety of different tr ap v ectors informs the operating system about exceptions (e.g. access violation). the architecture allows the linear addressing of large memories for a more convenient code implementation. the memory management and protec tion unit (mmu) handles a virtual address range of 4 gbytes, and serves as a hardware firewall to enable secure separation of adjacent application codes and data. program and data modules are organised as packages. e ach package has a defined memory range o f 16 mbytes with dedicated access rights for memories and peripherals. with the 0.13m process, the sle 88 family offers large on - chip memories (rom, eeprom, ram). the eeprom space is the basis of infineon technologies ?flash? concept where the entire ee prom is freely configurable in code and data sections , and so can be used to store an operating system, as well as application code and data. this customization provides added value to the system and the possibility to serve multiple projects with the same platform. this concept offers the flexibility and convenience of flash memory, but takes advantage of the eeprom cell quality (timing, cycling and endurance) . a number of powerful peripherals offer hardware support for time and code intensive operations . : crypto@1408 for all known public - key algorithms based on large integer modular arithmetic with configurable register lengths of up to 1408 bits. des accelerator for symmetric crypto operations based on des and triple des true random number generator ( trng) to supply the cpu with true random numbers whose quality is tested according to ais - 3 1 strict evaluation guidelines pseudo random number generator (prng) for very fast generation of random numbers intelligent power manage r which automatically adjusts the internal frequency accordingly to the power classes a,b,c three 16 - bit timers for protocol implementation, event monitoring, etc? crc hardware module for fast crc calculation s required for e.g. in contact - less protocol s
sle 88c n f x 660 2p short product information 9 / 9 12 .200 9 glossary ais - 31 functi onality classes and evaluation methodology guidelines for physical random number generators defined by the german institute for the security of the information technology. caches cache memories are fast ram memories integrated into the cpu (faster acce ss than external ram) clt means contactless tunneling, protocol necessary for mifare? implementation over swp crc cyclic redundancy check cpu central processing unit cmos complementary metal - oxide semiconductor (technology used to manufacture most of today's chips) des data encryption standard ec elliptic curves e e prom electrically erasable programmable read - only memory (equivalent to nvm) esd electrostatic discharge, release of static electricity that can damage a chip etsi european telecom munication standards institute fpga field programmable gate array gsm global system for mobile communication hbm human body model iso/iec international organization for standardization/international electrotechnical commission med memory encryptio n decryption unit mmu memory management unit nvm non volatile memory os operating system prng pseudo random number generator ram random access memory risc reduced instruction set computer rom read - only memory rsa rivest, shamir and adleman, i nventors of the rsa cryptosystem swp single wire protocol t=0, t=1 communication protocols defined in iso 7816 standard t rng true random number generator uart universal asynchronous receiver/transmitter uicc universal integrated circuit card sales code name sle 88 c 400 0 .. sle: ifx name s: solitary digital circuits l: free selectable e: temperature r ange ( - 25c up to +85c) features: f: flash product l: contact - less interface u: usb interface n: swp interface ordinal number : e.g. : 0,2 c: controller eeprom size : 256 : 256 kbytes 400 : 400 kbytes 1m: 1mb 1m5: 1.5mb add. features p : pl us x ? x : crypto c ontroller chip family : 66: 8 - bit /16 - bit 76: 16 - bit 78: dual 16 - bit 88: 32 - bit
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