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rt8208a/b 1 ds8208a/b-04 may 2011 www.richtek.com programmable output voltage single synchronous buck controller general description the rt8208a/b is a constant-on-time pwm controller which provides four resistor programmable dc output voltages by controlling the g0 and g1 digital input. the output voltage is programmable from 0.75v to 3.3v. the rt8208a/b offers the lowest total solution cost in systems where need output voltage slewing. the rt8208a/b provides an automatic masking power good output during output voltage transition. the constant-on-time pwm control scheme handles wide input/output ratios with ease and provides 100ns ? instant- on ? response to load transient while maintaining a relatively constant frequency. it provides the high efficiency, excellent transient response, and dc output accuracy needed for stepping down high voltage batteries to generate low voltage cpu core, graphics, i/o and chipset ram supplies in notebook computers. the rt8208a/b achieves high efficiency at a reduced cost by eliminating the current sense resistor in traditional current mode pwms. efficiency is further enhanced by its ability to drive very large synchronous rectifier mosfets. the buck conversion allows this device to directly step down from high voltage batteries for the highest possible efficiency. additional features include soft-start, under voltage protection, programmable over current protection and non-overlapping gate drive. the rt8208a/ b is available in a wqfn-16l 3x3 package. features z z z z z ultra-high efficiency z z z z z resistor programmable output voltage from 0.75v to 3.3v with integrated transition support z z z z z quick load step response within 100ns z z z z z 1% v fb accuracy over line and load z z z z z 4.5v to 26v battery input range z z z z z resistor programmable frequency z z z z z integrated bootstrap switch z z z z z resistor programmable positive current limit by low side r ds(on) sense (lossless limit) z z z z z negative current limiter z z z z z voltage transient overshoot eliminator* z z z z z over voltage protection z z z z z under voltage protection z z z z z 4 steps current limit during soft-start z z z z z power good indicator z z z z z rohs compliant and halogen free applications z notebook computers z system power supplies z i/o supplies z programmable-output power supplies ordering information * paten pending note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations wqfn-16l 3x3 (top view) pgood fb vout vdd ugate phase vddp cs d1 g0 d0 lgate ton en/dem boot g1 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 gnd 17 rt8208 package type qw : wqfn-16l 3x3 (w-type) turn-on d0/d1 mosfet a : g0/g1 high b : g0/g1 low lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free)
rt8208a/b 2 ds8208a/b-04 may 2011 www.richtek.com typical application circuit marking information ff= : product code ymdnn : date code rt8208agqw fg= : product code ymdnn : date code ff : product code ymdnn : date code fg : product code ymdnn : date code rt8208azqw RT8208BGQW rt8208bzqw ff=ym dnn ff ym dnn fg=ym dnn fg ym dnn functional pin description pin no. pin name pin function 1 vout output voltage pin. connect to the output of pwm converter. vout is an input of the pwm controller. 2 vdd analog supply voltage input for the internal analog integrated circuit. bypass to gnd with a 1 f ceramic capacitor. 3 fb feedback input pin. connect fb to a resistor voltage divider from vout to gnd to adjust output voltage from 0.75v to 3.3v 4 pgood power good signal open-drain output of pwm converter. this pin w ill be pulled high when the output voltage is within the target range. 5 d1 drain of the internal mosfet which is controlled by g1. 6 d0 drain of the internal mosfet which is controlled by g0. to be continued v i n p g o o d v d d p r 2 r 1 c 2 r 3 q 1 q 2 c 1 v o u t = 0 . 9 v r 6 2 5 0 k 1 0 1 0 0 k 1 f 1 8 k 0 r 4 r 5 c 3 0 0 . 1 f 4 . 5 v t o 2 6 v b s c 1 1 9 n 0 3 s c 4 1 0 f r 7 c 7 r 8 r 9 l 1 1 h c 5 * c 6 * 2 2 0 f 1 0 1 2 1 1 8 3 v d d p c s u g a t e f b rt8208a/b l g a t e 9 1 3 b o o t p h a s e v o u t 1 v d d 2 p g o o d 4 t o n 1 6 r 1 0 0 1 2 k c c m / d e m en/dem 1 5 g n d 1 7 ( e x p o s e d p a d ) * : o p t i o n a l 6 0 k 7 g 0 g 0 1 4 g 1 g 1 5 d 1 6 d 0 r 1 1 * r 1 2 * b s c 1 1 9 n 0 3 s
rt8208a/b 3 ds8208a/b-04 may 2011 www.richtek.com function block diagram min. t off qtrig 1-shot + - + - gm 0.75v v ref sq latch sq latch + - ov + - uv 125% v ref 70% v ref + - 90% v ref ss timer thermal shutdown diode emulation drv drv on-time compute 1-shot cs fb vout vdd ugate phase vddp pgood gnd lgate ton boot trig en r q s ss (internal) control logic g0 g1 d0 d1 r r g0, g1 counter blanking signal en - + gm + - 10a pin no. pin name pin function 7 g0 control input pin for the d0 mosfet. a logic high for rt8208a and low for rt8208b turn on the d0 mosfet on, pulling d0 to the ground. 8 lgate low side n-mosfet gate driver output for pwm. this pin swings between gnd and vddp. 9 vddp vddp is the gate driver supply for external mosfets. bypass to gnd with a 1 f ceramic capacitor. 10 cs over current trip point set input. connect a resistor from this pin to signal ground to set threshold for both over current and negative over current limit. 11 phase the ugate high side gate driver return. also serves as anode of over current comparator. 12 ugate high side n-mosfet floating gate driver output for the pwm converter. this pin swings between phase and boot. 13 boot boost capacitor connection for pwm converter. connect to an external ceramic capacitor to phase. 14 g1 control input pin for the d1 mosfet. a logic high for rt8208a and low for rt8208b turn on the d1 mosfet on, pulling d1 to the ground. 15 en/dem enable/diode emulation mode control input. connect to vdd for diode?emulation mode, connect to gnd for shutdown and floating the pin for ccm mode. 16 ton on time/frequency adjustment pin. connect to phase through a resistor. ton is an input for the pwm controller. 17 (exposed pad) gnd the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
rt8208a/b 4 ds8208a/b-04 may 2011 www.richtek.com electrical characteristics parameter symbol test conditions min typ max unit pwm cont roller quiescent supply current i q vdd + vddp, v fb = 0.8v -- -- 1250 a v dd + v ddp -- 1 10 shutdown current i shdn en/dem = gnd ? 10 ? 1 -- a fb reference voltage v ref v dd = 4.5v to 5.5v 0.742 0.750 0.758 v fb input bias current v fb = 0.75v ? 1 0.1 1 a output voltage range v out 0.75 -- 3.3 v to be continued recommended operating conditions (note 4) z input voltage, v in ---------------------------------------------------------------------------------------------------------- 4.5v to 26v z supply voltage, v dd , v ddp ---------------------------------------------------------------------------------------------- 4.5v to 5.5v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z boot to gnd -------------------------------------------------------------------------------------------------------------- ? 0.3v to 38v z boot to phase ---------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z phase to gnd dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 32v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 8v to 38v z ugate to phase dc ----------------------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 5v to 7.5v z lgate to gnd dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 6 < 20ns ---------------------------------------------------------------------------------------------------------------------- - ? 2.5v to 7.5v z vdd, vddp, vout, en/dem, fb, pgood, to n to gnd ------------------------------------------------------- ? 0.3v to 6v z cs to gnd ------------------------------------------------------------------------------------------------------------------ ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wqfn ? 16l 3x3 ------------------------------------------------------------------------------------------------------------ 1.471w z package thermal resistance (note 2) wqfn ? 16l 3x3, ja ------------------------------------------------------------------------------------------------------ 68 c/w wqfn ? 16l 3x3, jc ------------------------------------------------------------------------------------------------------ 7.5 c/w z lead temperature (soldering, 10 se c.) ------------------------------------------------------------------------------- 260 c z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v (v in = 15v, v dd = v ddp = 5v, t a = 25 c, unless otherwise specified)
rt8208a/b 5 ds8208a/b-04 may 2011 www.richtek.com parameter symbol test conditions min typ max unit d0 pull-down resistance d0 to gnd, g0 = 5v -- 10 -- d1 pull-down resistance d1 to gnd, g1 = 5v -- 10 -- on-time v phase = 12v, v out = 2.5v, r ton = 250k 336 420 504 ns minimum off-time 250 400 550 ns vout shutdown discharge resistance en/dem = gnd -- 20 -- ? current sensing current limiter source current cs to gnd 9 10 11 a current comparator offset ? 10 -- 10 mv zero crossing threshold phase to gnd, en/dem = 5v ? 10 -- 5 mv fault protection gnd to phase, v cs = 50mv 40 50 60 current limit (threshold) gnd to phase, v cs = 200mv 190 200 210 mv current limit setting range cs to gnd 50 -- 200 mv output uv threshold uvp detection 60 70 80 % ovp threshold v fb_ovp ovp detection 120 125 130 % ov fault delay fb forced above ov threshold -- 20 -- s rising edge, pwm disabled below this level 4.1 4.3 4.5 v vdd under voltage lockout threshold hysteresis -- 80 -- mv current limit step duration at soft-start each step -- 128 -- clks uvp blanking time from en signal going high -- 512 -- clks thermal shutdown t sh dn -- 155 -- c thermal shutdown hysteresis -- 10 -- c driver on-resistance ugate drive source r ugatesr boot to phase = 5v -- 2 5 ugate drive sink r ugatesk boot to phase = 5v -- 1 5 lgate drive source r lgatesr lgate, high state -- 1 5 lgate drive sink r lgatesk lgate, low state -- 0.5 2.5 ugate gate driver source/sink current ugate to phase = 2.5v, boot to phase = 5v -- 1 -- a lgate gate driver source current lgate forced to 2.5v -- 1 -- a lgate gate driver sink current lgate forced to 2.5v -- 3 -- a lgate rising (phase = 1.5v) -- 30 -- dead time ugate rising -- 30 -- ns internal boost charging switch on-resistance vddp t o boot, 10ma -- -- 80 ? to be continued
rt8208a/b 6 ds8208a/b-04 may 2011 www.richtek.com parameter symbol test conditions min typ max unit logi c i /o en/dem low - - -- 0.8 en/dem high 2.9 -- -- en/dem logic input voltage en/dem floating -- 2 -- v g0 low -- -- 0.8 g0 logic input voltage g0 high 2 -- -- v g1 low -- -- 0.8 g1 logic input voltage g1 high 2 -- -- v en/dem = vdd - - 1 5 en/dem = 0 ? 5 1 -- logic input current g0 = g1 = vdd or gnd ? 1 -- 5 a pgood v fb with respect to reference, pgood from low to high 87 90 93 v fb with respect to reference, pgood from high to low -- 125 -- pgood thr eshold hysteresis -- 3 -- % fault propagation delay falling edge, fb forced below pgood trip threshold -- 2.5 -- s output low voltage i sink = 1ma -- -- 0.4 v leakage current high state, forced to 5v -- -- 1 a ? note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a four layers high effective thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
rt8208a/b 7 ds8208a/b-04 may 2011 www.richtek.com typical operating characteristics switching frequency vs. output current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 ccm dem v in = 15v, v out = 1.8v, en = vdd / floating switching frequency vs. output current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 ccm dem v in = 15v, v out = 1.8v, en = vdd / floating switching frequency vs. output current 0 50 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 ccm dem v in = 19v, v out = 1.8v, en = vdd / floating 1.8v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) ccm dem v in = 10v, v out = 1.8v en = vdd / floating 1.8v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 loan current (a) efficiency (%) ccm dem v in = 15v, v out = 1.8v en = vdd / floating 1.8v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 19v, v out = 1.8v en = vdd / floating dem ccm
rt8208a/b 8 ds8208a/b-04 may 2011 www.richtek.com time (400 s/div) v out (1v/div) en (2v/div) pgood (5v/div) ugate (10v/div) en = floating, v in = 12v v out = 0.9v, no load power on from en (ccm) power on from en (dem) time (400 s/div) v out (1v/div) ugate (10v/div) en (5v/div) pgood (5v/div) en = vdd ,v in = 12v v out = 0.9v, no load shutdown input current vs. input voltage 0 0.2 0.4 0.6 0.8 1 7 9 11 13 15 17 19 21 23 25 input voltage (v) shutdown input current ( a) 1 en = gnd, no load 0.9v load transient response time (25 s/div) v in = 12v, en = floating, ccm mode, v out = 0.9v v out (100mv/div) i out (10a/div) ugate (20v/div) lgate (5v/div) uvp waveforms time (20 s/div) v in = 12v, v out = 0.9v no load, en = floating (ccm mode) v out (500mv/div) ugate (20v/div) lgate (5v/div) i l (10a/div) time (40 s/div) v out (500mv/div) ugate (10v/div) lgate (5v/div) ovp waveforms v in = 12v, v out = 0.9v, load en = vdd (dem mode)
rt8208a/b 9 ds8208a/b-04 may 2011 www.richtek.com time (20 s/div) v out (1v/div) g1 (5v/div) ugate (20v/div) lgate (5v/div) v out down transient (load=10a) v in = 12v, en = floating (ccm mode) v out = 1.5v to 0.9v rt8208a v out (1v/div) g1 (5v/div) ugate (20v/div) lgate (5v/div) v in = 12v, en = floating (ccm mode) v out = 1.5v to 0.9v time (20 s/div) v out down transient (no load) rt8208a v out (1v/div) g1 (5v/div) ugate (20v/div) lgate (5v/div) time (20 s/div) v in = 12v, en = floating (ccm mode) v out = 0.9v to 1.5v v out up transient (load=10a) rt8208a v out (1v/div) g1 (5v/div) ugate (20v/div) lgate (5v/div) time (20 s/div) v in = 12v, en = floating (ccm mode) v out = 0.9v to 1.5v v out up transient (no load) rt8208a
rt8208a/b 10 ds8208a/b-04 may 2011 www.richtek.com application information the rt8208a/b is a constant-on-time pwm controller which provides four resistor-programmable dc output voltages by controlling the g0 and g1 digital input. the output voltage is programmable from 0.75v to 3.3v. the constant on-time pwm control scheme handles wide input/ output rations with ease and providing 100ns ? instant-on ? response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the topology circumvents the poor load transient timing problems of fixed-frequency current mode pwms while avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant off-time pwm schemes. the drv tm mode pwm modulator is specifically designed to have better noise immunity for such a single output application. pwm operation the mach response tm , drv tm mode controller relies on the output filter capacitor ? s effective series resistance (esr) to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp signal. refer to the function diagrams of the rt8208a/b, the synchronous high-side mosfet is turned on at the beginning of each cycle. after the internal one-shot timer expires, the mosfet is turned off. the pulse width of this one shot is determined by the converter ? s input and output voltages to keep the frequency fairly constant over the input voltage range. another one-shot sets a minimum off-time (400ns typ.). on-time control (t on ) the on-time one-shot comparator has two inputs. one input monitors the output voltage, while the other input samples the input voltage and converts it to a current. this input voltage proportional current is used to charge an internal on-time capacitor. the on-time is the time required for the voltage on this capacitor to charge from zero volts to vout, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. the implementation results in a nearly constant switching frequency without the need of a clock generator. t on = 9.6p x r ton x (v out + 0.1) / (v in ? 0.3) + 50ns although this equation provides a good approximation to start with, the accuracy depends on each design and selection of the high side mosfet. and then the switching frequency (f) is: r ton is a resistor connected from the phase to ton pin. mode selection (en) operation the en pin enables the supply. when en/dem is tied to vdd, the controller is enabled and operates in diode- emulation mode. when the en pin is floating, the rt8208a/b will operate in forced-ccm mode. diode-emulation mode (en = high) in diode-emulation mode, the rt8208a/b automatically reduces switching frequency at light-load conditions to maintain high efficiency. this reduction of frequency is achieved smoothly and without increasing vout ripple or load regulation. as the output current decreases from heavy-load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low side mosfet allows only partial of negative current when the inductor freewheeling current reach negative. as the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level than requires the next ? on ? cycle. the on-time is kept the same as that in the heavy-load condition. in reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. the transition load point to the light-load operation can be calculated as follows (figure 1) : ? ? in out load on (v v ) i t 2l where t on is on-time. out in on v f = vt
rt8208a/b 11 ds8208a/b-04 may 2011 www.richtek.com figure 1. boundary condition of ccm/dem i l t 0 t on slope = (v in -v out ) / l i l, peak i load = i l, peak / 2 the switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in dem noise vs. light-load efficiency is made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. the disadvantages for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels). forced-ccm mode (en = floating) the low noise, forced-ccm mode (en=floating) disables the zero-crossing comparator, which controls the low side switch on-time. this causes the low side gate drive waveform to become the complement of the high side gate-drive waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop to maintain a duty ratio vout/vin. the benefit of forced- ccm mode is to keep the switching frequency fairly constant, but it comes at a cost: the no-load battery current can be up to 10ma to 40ma, depending on the external mosfets. output voltage setting (fb) the output voltage can be adjusted from 0.75v to 3.3v by setting the feedback resistor r1 and r2, see figure 2. with g0 and g1 in low state, the output voltage is at the lowest value. choose r2 to be approximately 20k , and solve for r1 using the equation : ?? ?? ?? out ref r1 v = v 1+ r2 where v ref is 0.75v in typical. phase lgate v out v in ugate vout gnd g1 g0 r1 r2 fb figure 2. setting v out with a resistor divider output voltage transition control the rt8208a/b provides two digital control input g0 and g1 to allow selection among four output voltages. the output voltage is regulated by comparing the fb pin (connected to vout via an external resistor divider) to the internal 0.75v reference. the g0 and g1 digital input control the gate of internal respective mosfet whose drain is connected to d0 and d1 respectively. using gx, the user controls whether dx is grounded or open, which then controls the resistor divider ratio for v out . a logic high signal on gx will connect dx to ground. when the gx input changes state, this change quickly causes three actions: 1. d0 changes state. 2. the power good pgood output is temporarily latched into its present state. this prevents chattering or false tripping while v out moves to the new level. 3. when the gx changes state whether dem is set or not, then enter the pwm mode and counts 32 clock cycles. for the duration of 32 clock cycles, the ovp and uvp function is masked. this behavior allows the output to slew down to the new level without tripping the ovp or uvp function when the gx change causes rapid change of dx, which in turns cause a rapid change at fb. output voltage is regulated through the fb pin via resistors r1 through r4 as shown in figure 3.
rt8208a/b 12 ds8208a/b-04 may 2011 www.richtek.com figure 3. output voltage selection by g0 and g1 input the following table shows the equations for vout as a function of digital control input g0 and g1. rt8208a rt8208b g0 g1 g0 g1 output voltage equation 0 0 1 1 out r1+r2 v = x 0.75 r2 1 0 0 1 out r1+(r2//r3) v = x 0.75 (r2//r3) 0 1 1 0 out r1+(r2//r4) v = x 0.75 (r2//r4) 1 1 0 0 out r1+(r2//r3//r4) v = x 0.75 (r2//r3//r4) note that the r ds(on) of the internal mosfet is in series with external resistor, which adds typically 10 in series. output voltage transition operation the digital input control pin gx allows vout to transition to both higher and lower values. for a down transition, the rapid change gx from high to low as sudden release either of external resistors (r3 or r4) will cause fb to go above the 0.75v threshold. at this time, the lgate will drive high to turn on the low side mosfet and draw current from the output capacitor via the inductor. lgate will remain on until fb falls to 0.75v, at which point a normal ugate switching cycle begins, see figure4. for a down transition, the low side mosfet stays on before fb reaches to 0.75v, thus the negative inductor current will be increased. if the negative current is too large to trigger nocp, the low side mosfet is turned off which can avoid too much negative current to damage component. refer to the negative over current limit section for a full description. gx gnd fb lgate ugate v out initial v out final v out figure 4. output voltage down transition figure 5. output voltage up transition lgate gx fb ugate v out gnd initial v out final v out minimum off-time fb threshold gnd fb d1 d0 r2 r1 r3 r4 v out 0.75v g0 g1 control logic ton gnd fb d1 d0 r2 r1 r3 r4 v out g0 g1 control logic
rt8208a/b 13 ds8208a/b-04 may 2011 www.richtek.com for an up transition (from lower to higher vout) as shown in figure5, the gx change affects dx and causes fb to drop below the 0.75v trip point. this quickly trips the fb comparator regardless of whether dem is active or not, generating an ugate on-time and a subsequent lgate will be turned on. at the end of the minimum off-time (400ns), if fb is still below 0.75v then another ugate on-time is started. this sequence continues until the fb pin exceeds 0.75v. figure 6. output voltage up transition with overshooting if the vout change is significant, there can be several consecutive cycle of ugate on-time followed by minimum lgate time. this can cause a rapid increase in inductor current: typically it takes only a few switching cycles for inductor current to rise up to the current limit. at some point the fb voltage will rise up to the 0.75v reference and the ugate pulses will cease, but the inductor ? s li 2 energy must then flow into the output capacitor. this can create a significant overshoot as shown in figure6. the overshooting can be approximated by the following equation, where i cl is the current limit, v final is the desired set point for the final voltage, l is in h and c out is in f. 2 2 cl max fianl out il v = ( ) + v c ?? ?? ?? ?? the overshoot eliminator (patent pending) prevents output voltage overshooting after rapid changes of gx. this results in a gradual change from v out(initial) to v out(final) and prevents the buildup of high inductor current and reducing overshoot. current limit setting (ocp) rt8208a/b has cycle-by-cycle current limiting control. the current limit circuit employs a unique ? valley ? current sensing algorithm. if the magnitude of the current sense signal at cs is above the current limit threshold, the pwm is not allowed to initiate a new cycle (figure 7).in order to provide both good accuracy and a cost effective solution, the rt8208a/b supports temperature compensated mosfet r ds(on) sensing. the cs pin should be connected to gnd through the trip voltage setting resistor, r cs . the cs terminal source 10 a i cs current, and the trip level is set to the cs trip voltage, v cs as in the following equation. ( ) cs cs v(mv) = r(k) x 10a inductor current is monitored by the voltage between the pgnd pin and the phase pin. so the phase pin should be connected to the drain terminal of the low-side mosfet. i cs has temperature coefficient to compensate the temperature dependency of the r ds(on) . pgnd is used as the positive current sensing node. so pgnd should be connected to the source terminal of the bottom mosfet. as the comparison is done during the off state, v cs sets the valley level of the inductor current. thus, the load current at over current threshold, i load_oc , can be calculated as follows ; in an over current condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall. eventually, it crosses the under-voltage protection threshold and shutdown. lgate gx fb ugate v out gnd initial v out final v out minimum off-time fb threshold () ? cs ripple load_oc ds(on) in out out cs ds(on) in vi i = + r2 vv v v 1 = + r2lf v
rt8208a/b 14 ds8208a/b-04 may 2011 www.richtek.com i l t 0 i l, peak i lim i load figure 7. ? valley ? current limit negative over current limit (ccm mode only) the rt8208a/b also supports cycle-by-cycle negative over current limiting in ccm mode only. the over-current limit is set to be negative but is the same absolute value as the positive over current limit. if output voltage continues to rising, the low side moseft stays on, thus inductor current is reduced and reverses direction after it reaches zero. when there is too much negative current in the inductor, the low side mosfet is turned off and the current flows to vin through the body diode of the high side mosfet. because this protection limits current to discharge the output capacitor, output voltage tends to rise, eventually hitting the over-voltage protection threshold and shutdown. in order to prevent false ovp from triggering, the low side mosfet is turned on again 400ns after it is turned off. if the device hits the negative over-current threshold again before output voltage is discharged to the target level, the low side mosfet is turned off and process repeats. it ensures maximum allowable discharge capability when output voltage continues to rise. on the other hand, if the output is discharged to the target level before negative current threshold is reached, the low side mosfet is turned off, the high side mosfet is then turn on, and the device resumes normal operation. mosfet gate driver (ugate, lgate) the high-side driver is designed to drive high current, low r ds(on) n-mosfet(s). when configured as a floating driver, 5v bias voltage is delivered from vddp supply. the average drive current is proportional to the gate charge at v gs = 5v times switching frequency. the instantaneous drive current is supplied by the flying capacitor between boot and phase pins. a dead time to prevent shoot through is internally generated between high-side mosfet off to low side mosfet on, and low-side mosfet off to high side mosfet on. the low-side driver is designed to drive high current, low r ds(on) n-mosfets. the internal pull-down transistor that drives lgate low is robust, with a 0.6 typical on resistance. a 5v bias voltage is delivered from vddp supply. the instantaneous drive current is supplied by the flying capacitor between vddp and pgnd. for high current applications, some combinations of high and low side mosfets might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, emi-producing shoot-through currents. this is often remedied by adding a resistor in series with boot, which increases the turn-on time of the high-side mosfet without degrading the turn-off time (figure 8). boot ugate phase r v in figure 8. reducing the ugate rise time power good output (pgood) the power good output is an open-drain output and requires a pull-up resistor. when the output voltage is 25% above or 10% below its set voltage, pgood will be pulled low. it is held low until the output voltage returns to within these tolerances once more. in soft-start, pgood is actively held low and is allowed to transition high until soft-start is over and the output reaches 93% of its set voltage. there is a 2.5 s delay built into pgood circuitry to prevent false transition. when gx changes state, pgood is immediately latched into its present state for 32 clock cycle while vout and fb are changed to the new level. after that the latch will be disabled.
rt8208a/b 15 ds8208a/b-04 may 2011 www.richtek.com por, uvlo and soft-start power on reset (por) occurs when vdd rises above to approximately 4.3v. after por is triggered. and then, the rt8208a/b will reset the fault latch and prepare the pwm for operation. below 4.1v (min), the vdd under voltage lockout (uvlo) circuitry inhibits switching by keeping ugate and lgate low. a built-in soft-start is used to prevent surge current from power supply input after en is enabled. the maximum allowed current limit is segmented in 4 steps: 25%, 50%, 75% and 100% during this period, each step is 128 ugate clks. the current limit steps can eliminate the v out folded-back in the soft-start duration. output over voltage protection (ovp) the output voltage can be continuously monitored for over voltage protection. when the output voltage exceeds 25% of the its set voltage threshold, over voltage protection is triggered and the low side mosfet is latched on. this activates the low side mosfet to discharge the output capacitor. the rt8208a/b is latched once ovp is triggered and can only be released by vdd or en power on reset. there is 20 s delay built into the over voltage protection circuit to prevent false transitions. when gx changes state, the ovp function is masked for 32 clock cycle while vout and fb are changed to the new level. after that the mask will be disabled. output under voltage protection (uvp) the output voltage can be continuously monitored for under voltage protection. when the output voltage is less than 70% of its set voltage threshold, under voltage protection is triggered and then both ugate and lgate gate drivers are forced low. in order to remove the residual charge on the output capacitor during the under voltage period, if phase is greater than 1v, the lgate is forced high until phase is lower than 1v. there is 2.5 s delay built into the under voltage protection circuit to prevent false transitions. during soft-start, the uvp blanking time is 512 ugate clks. when gx changes state, the uvp function is masked for 32 clock cycle while vout and fb change to the new level, after which the mask is disable. output inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as follows : ( ) ? on in out ir load(max) tvv l = li where l ir is the ratio of peak-to-peak ripple current to the maximum average inductor current. find a low-pass inductor having the lowest possible dc resistance that fits in the allowed dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough and not to saturate at the peak inductor current (i peak ) : ?? ?? ?? ?? ?? ?? ir peak load(max) load(max) l i = i + i 2 output capacitor selection the output filter capacitor must have low enough equivalent series resistance (esr) to meet output ripple and load- transient requirements, yet have high enough esr to satisfy stability requirements. the output capacitance must also be high enough to absorb the inductor energy while transiting from full-load to no-load conditions without tripping the overvoltage fault latch. although mach response tm drv tm dual ramp valley mode provides many advantages such as ease-of-use, minimum external component configuration, and extremely short response time, due to not employing an error amplifier in the loop, a sufficient feedback signal needs to be provided by an external circuit to reduce the jitter level. the required signal level is approximately 15mv at the comparing point. this generates v ripple = (v out / 0.75) x 15mv at the output node. the output capacitor esr should meet this requirement. output capacitor stability stability is determined by the value of the esr zero relative to the switching frequency. the point of instability is given by the following equation : sw esr out f 1 f = 2 esr c 4 do not put high value ceramic capacitors directly across the outputs without taking precautions to ensure stability.
rt8208a/b 16 ds8208a/b-04 may 2011 www.richtek.com layout considerations layout is very important in high frequency switching converter design. if designed improperly, the pcb could radiate excessive noise and contribute to the converter instability. for best performance of the rt8208a/b, the following guidelines should be strictly followed. ` connect an rc low pass filter from vddp to vdd, 1 f and 10 are recommended. place the filter capacitor close to the ic. ` keep current limit setting network as close as possible to the ic. routing of the network should be kept away from to high voltage switching nodes to prevent it from coupling. ` connections from the drivers to the respective gate of the high side or the low side mosfet should be as short as possible to reduce stray inductance. figure 9. derating curve for rt8208a/b package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four layers pcb large ceramic capacitors can have a high-esr zero frequency and cause erratic and unstable operation. however, it is easy to add sufficient series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting vout or fb divider close to the inductor. there are two related but distinct ways including double-pulsing and feedback loop instability to identify the unstable operation. double-pulsing occurs due to noise on the output or because the esr is too low that there is not enough voltage ramp in the output voltage signal. this ? fools ? the error comparator into triggering a new cycle immediately after 400ns minimum off-time period has expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it may indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillation at the output after line or load perturbations that can trip the over voltage protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for stability checking is to apply a very zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. it helps to simultaneously monitor the inductor current with ac probe. do not allow more than one ringing cycle after the initial step-response under- or over-shoot. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of the rt8208a/b, the maximum junction temperature of the die is 125 c. the junction to ambient thermal resistance ja is layout dependent. for wqfn-16l 3x3 packages, the thermal resistance ja is 68 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c)/(68 c/w) = 1.471w for wqfn-16l 3x3 package the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for rt8208a/b package, the figure 9 of derating curve allows the designer to see the effect of rising ambient temperature on the maximum power allowed.
rt8208a/b 17 ds8208a/b-04 may 2011 www.richtek.com ` all sensitive analog traces and components such as vout, fb, gnd, en/dem, pgood, oc, vdd, and ton should be placed away from high voltage switching nodes such as phase, lgate, ugate, or boot nodes to prevent it from coupling. use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ` current sense connections must always be made using kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. ` power sections should connect directly to ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). power components should be placed to minimize loops and reduce losses.
rt8208a/b 18 ds8208a/b-04 may 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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