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kbc00a6a0m revision 1.1 october 2003 - 1 - preliminary mcp memory document title multi-chip package memory 128m bit (8mx16) nand flash memory / 64m bit (4mx16) u t ram / 32m bit (2mx16) u t ram / 8m bit ( 512kx16 ) sram revision history revision no. 0.0 1.0 1.1 remark preliminary final final history initial draft. finalize - correct the some minor mis-spelling <64m utram> - changed power up sequence and wake up sequence - changed operation current(max)- i cc2 from 40ma to 35ma - corrected the flash read1 operation(read one page) timing in page 24. draft date november 22, 2002 may 20. 2003 october 28. 2003 the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. note : for more detailed features and specifications including faq, please refer to samsung?s web site. http://samsungelectronics.com/semiconductors/products/products_index.html
kbc00a6a0m revision 1.1 october 2003 - 2 - preliminary mcp memory multi-chip package memory 128m bit (8mx16) nand flash memory / 64m bit (4mx16) u t ram / 32m bit (2mx16) u t ram / 8m bit ( 512kx16 ) sram the kbc00a6a0m is a multi chip package memory which combines 128mbit nand flash and 64mbit unit transistor cmos ram and 32mbit unit transistor cmos ram and 8mbit sram. 128mbit nand flash memory is organized as 8m x16 bit and 64mbit u t ram is organized as 4m x16 bit and 32mbit u t ram is organized as 2m x16 bit and 8mbit sram is organized as 512k x16 bit. in 128mb nand flash a 264-word page program can be typically achieved within 200us and an 8k-word block erase can be typically achieved within 2ms. in serial read operation, a word can be read by 50ns. dq pins serve as the ports for address and data input/output as well as command inputs. even the write-intensive systems can take advantage of the flash s extended reliability of 100k program/erase cycles by providing ecc(error correcting code) with real time mapping- out algorithm. these algorithms have been implemented in many mass storage applications. the 64mbit(32mbit) u t ram is fabricated by samsung s advanced cmos technology using one transistor memory cell. the device supports deep power down mode for low standby current. the 8mbit sram is fabricated by samsung s advanced full cmos process technology. the device supports low data retention voltage for battery back-up operation with low data retention current. the kbc00a6a0m is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. this device is available in 87-ball tbga type. features power supply voltage - flash : 2.7 ~ 3.1v - u t ram(32m, 64m) : 2.7 ~ 3.1v - sram : 2.7 ~ 3.1v organization - flash : (8m + 256k)bit x 16bit - u t ram(64m) : 4m x 16 bit - u t ram(32m) : 2m x 16 bit - sram : 512k x 16 bit access time - flash : random access : 10us(max.), serial page access : 50ns(min.) - u t ram(64m) : 70ns - u t ram(32m) : 85ns - sram : 55ns power consumption (typical value) - flash read current : 10 ma(@20mhz) program/erase current : 10 ma standby current : 10 m a - u t ram(64m) operating current : 35ma standby current : 80 m a - u t ram(32m) operating current : 30ma standby current : 80 m a - sram operating current : 30ma standby current : 0.5 m a flash automatic program and erase page program : (256 + 8)word block erase : (8k + 256)word flash fast write cycle time program time : 200us(typ.) block erase time : 2ms(typ.) u t ram support deep power down : memory cell data holds invalid sram low data retention voltage : 1.5v(min.) flash endurance : 100,000 program/erase cycles minimum flash data retention : 10 years operating temperature : -25 c ~ 85 c package : 87 - ball tbga type - 10 x 12mm, 0.8 mm pitch general description samsung electronics co., ltd. reserves the right to change products and specifications without notice.
kbc00a6a0m revision 1.1 october 2003 - 3 - preliminary mcp memory pin configuration 87-tbga: top view (ball down) dnu 1 2 3 4 5 6 a b c d e f g h dnu dnu dnu a13 r/ b cs2s vccu nc cle nc a14 a9 we vcc f ale a6 a15 a10 nc a18 a7 a11 lb a21 re a8 ce wp a17 a16 nc nc cs u1 cs u2 dq14 dq5 vccqu dq10 dq 1 dq6 dq13 nc vcc f nc dq3 dq9 dnu dnu dnu a4 7 8 10 9 j k l m dq15 dq7 dq12 vccu vccs dq11 dq2 dnu dnu dnu dnu dq0 dnu dnu dnu dnu n nc vss a20 ub a19 zz 1 nc cs 1s zz 2 vss dq4 a3 a2 a1 a5 a0 oe dq8 a12 nc
kbc00a6a0m revision 1.1 october 2003 - 4 - preliminary mcp memory ordering information k b c 00 a 6 a 0 m - t 403 samsung mcp(4 chip) memory device type nand flash+u t ram+u t ram +sram nor flash density , vcc , org. 00 : none sram density , vcc , org. a : 8mbit, 3.0v, x16 sdram density , vcc , org. 0 : none access time 403 : nand flash: 50ns u t ram(64mbit): 70ns u t ram(32mbit): 85ns sram: 55ns u t ram density , vcc/vccq , org. 6 : 64mbit+32mbit, 3.0v/3.0v, x16 version m : 1st generation nand flash density , vcc , org. a : 128mbit, 3.0v, x16 package t : tbga pin description 1. u t ram1: 64mbit u t ram, u t ram2: 32mbit u t ram ball name description ball name description a 0 to a 18 address input balls (u t ram1,u t ram2,sram) r/ b ready/busy (flash memory) a 19 to a 20 address input balls (u t ram1, u t ram2) zz 1 deep power down (u t ram1) a 21 address input balls (u t ram1) zz 2 deep power down (u t ram2) dq 0 to dq 15 data input/output balls (common) ce chip enable (flash memory) wp write protection (flash memory) cs u1 chip select (u t ram1) v ccf power supply (flash memory) cs u2 chip select (u t ram2) vccu power supply (u t ram1,u t ram2) cs 1s chip select (sram) vccs power supply (sram) cs2s chip select (sram) vccqu data out power (u t ram1,u t ram2) we write enable (common) vss ground (common) oe output enable (u t ram1,u t ram2, sram) ub upper byte enable (u t ram1,u t ram2, sram) re read enable (flash memory) lb lower byte enable (u t ram1,u t ram2, sram) nc no connection ale address latch enable (flash memory) dnu do not use cle command latch enable (flash memory)
kbc00a6a0m revision 1.1 october 2003 - 5 - preliminary mcp memory figure 1. functional block diagram ub cs u1 vccu lb r/ b wp ce ale address(a0 to a18) 128m bit flash memory 64m bit u t ram cle we re vcc f vss dq 0 to dq 15 dq 0 to dq 15 vss vccqu vccs 8m bit vss sram oe cs 1s dq 0 to dq 15 zz 1 cs2s address(a19 to a20) vccu vss vccqu 32m bit u t ram dq 0 to dq 15 dq 0 to dq 15 address(a21) zz 2 cs u2
kbc00a6a0m revision 1.1 october 2003 - 6 - preliminary mcp memory figure 2. flash array organization 256word 8 word note : column address : starting address of the register. * l must be set to "low". dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq8 to 15 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 l* 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 l* 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 l* l* page register (=256 words) 32k pages (=1,024 blocks) 256 word 16 bit 8 word 1 block =32 pages = (8k + 256) word dq 0 ~ dq 15 1 page = 264 word 1 block = 264 word x 32 pages = (8k + 256) word 1 device = 264words x 32pages x 1024 blocks = 132 mbits column address row address (page address) page register
kbc00a6a0m revision 1.1 october 2003 - 7 - preliminary mcp memory nand flash product introduction table 1. command sets caution : any undefined command inputs are prohibited except for above command set of table1. function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h - read 2 50h - read id 90h - reset ffh - o page program 80h 10h block erase 60h d0h read status 70h - o the nand flash memory is a 132mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 264 columns. spare eight col- umns are located from column address of 256~263. a 264-word data register is connected to memory cell arrays accommodating data transfer between the dq buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected like nand structure. each of the 16 cells resides in a different page. a block consists of the 32 pages formed by one nand structures, totaling 8448 nand structures of 16 cells. the array organization is shown in figure 2. pr o- gram and read operations are executed on a page basis, while erase operation is executed on a block basis. the memory array con- sists of 1024 blocks, and a block is separately erasable by 8k-word unit. it indicates that the bit by bit erase operation is prohibited on the nand flash memory. the nand flash memory has addresses multiplexed with lower 8 dq s. the nand flash allows sixteen bit wide data transport into and out of page registers. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by mainta in- ing consistency in system board design. command, address and data are all written through dq s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the dq pins. all commands require one bus cycle except page program command and block erase command which require two cycles: one cycle for setup and another for execution. the 32k-word physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high row address, in that order. page read and page program need the same three address cycles following required command input. in block erase operation, however, only two row address cycles are used. device operations are selected by writing specific command s into command register. table 1 defines the specific commands of the flash memory.
kbc00a6a0m revision 1.1 october 2003 - 8 - preliminary mcp memory table 2. flash memory operations table note: 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode h l l h x read mode command input l h l h x address input(3clock) h l l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by table 3. u t ram operations table 1. x means v il or v ih. cs u zz oe we lb ub dq 0~7 dq 8~15 mode power h h x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected deep power down l h x 1) x 1) h h high-z high-z deselected standby l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active table 4. sram operations table 1. x means v il or v ih. cs 1s cs 2s oe we lb ub dq 0~7 dq 8~15 mode power h x 1) x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) x 1) x 1) x 1) h h high-z high-z deselected standby l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active
kbc00a6a0m revision 1.1 october 2003 - 9 - preliminary mcp memory flash memory operation page read upon initial device power up, the device status defaults to read1 mode. this operation is also initiated by writing 00h to the com- mand register along with three address cycles. once the command is latched, it does not need to be written for the following pag e read operation. two types of operation are available : random read, serial page read. the random read mode is enabled when the page address is changed. the 264 words of data within the selected page are transferred to the data registers in less than 10 m s(tr). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data starting from the selected column address up to the last column address. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area(256 to 263 words) may be selectively accessed by writing the read2 command. addresses a 0 to a 2 set the starting address of spare area while addresses a 3~ a 7 must be "l". read1 command(00h) is needed to move the pointer back to the main area. figures 3, 4 show typical sequence and timings for each read operation. figure 3. read1 operation start add.(3cycle) 00h data output(sequential) ce cle ale r/ b we dq 0 ~ 15 re t r a 0 ~ a 7 & a 9 ~ a 23 (00h command) main array data field spare field
kbc00a6a0m revision 1.1 october 2003 - 10 - preliminary mcp memory figure 5. program & read status operation 80h dq 0 ~ 15 r/ b address & data input dq 0 pass 10h 70h fail t prog figure 4. read2 operation 50h a 0 ~ a 2 & a 9 ~ a 23 data output(sequential) spare field ce cle ale r/ b we data field spare field start add.(3cycle) (a 3 ~ a 7 : "l") dq 0 ~ 15 re t r page program the device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecu tive bytes/words up to 264 (x16 device) , in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. the addres s- ing may be done in any random order in a block. a page program cycle consists of a serial data loading period in which up to 264 words of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is pro- grammed into the appropriate cell. about the pointer operation, please refer to the attached technical notes. the serial data loading period begins by inputting the serial data input command(80h), followed by the three cycle address input and then serial data loading. the words other than those to be programmed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate the pro- gramming process. the internal write controller automatically executes the algorithms and timings necessary for program and veri fy, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered, with re and ce n low, to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/ b n output, or the status bit(dq 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit(dq 0) may be checked(figure 5). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remain s in read status command mode until another valid command is written to the command register.
kbc00a6a0m revision 1.1 october 2003 - 11 - preliminary mcp memory figure 6. block erase operation 60h block add. : a 9 ~ a 23 dq 0 ~ 15 r/ b address input(2cycle) dq 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to command register, a read cycle outputs th e content of the status register to the dq pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 5 for specific status register definitions. the command register remai ns in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. table 5. read status register definition dq # status definition dq 0 program / erase "0" : successful program / erase "1" : error in program / erase dq 1 reserved for future use "0" dq 2 "0" dq 3 "0" dq 4 "0" dq 5 "0" dq 6 device operation "0" : busy "1" : ready dq 7 write protect "0" : protected "1" : not protected dq 8~15 not use don?t care block erase the erase operation is done on a block basis. block address loading is accomplished in two cycles initiated by an erase setup co m- mand(60h). only address a 14 to a 23 is valid while a 9 to a 13 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures th at memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bit(dq 0) may be checked. figure 6 details the sequence.
kbc00a6a0m revision 1.1 october 2003 - 12 - preliminary mcp memory figure 7. read id operation read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code (53h) respectively. the command regis- ter remains in read id mode until further commands are issued to it. figure 7 shows the operation sequence. figure 8. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 6 for device status after reset operation. if the device is already in reset state, new reset command will not be accepted by the command register. the r/ b pin transitions to low for trst after the reset command is written. reset command is not necessary for normal operation. refer to figure 8 below. table 6. device status after power-up after reset operation mode read 1 waiting for next command ffh dq 0 ~ 15 r/ b t rst ce cle dq 0 ~ 15 ale re we 90h 00h ech address. 1cycle maker code device code t cea t ar t rea 53h t whr
kbc00a6a0m revision 1.1 october 2003 - 13 - preliminary mcp memory ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. it returns to high when the internal controller has finished the operatio n. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 9). its value ca n be determined by the following guidance. v cc r/ b open drain output device gnd where i l is the sum of the input currents of all devices tied to the r/ b pin. rp t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr rp value guidance rp(max) is determined by maximum permissible limit of tr ibusy rp = v cc (max.) - v ol (max.) i ol + s i l = 2.7v 8ma + s i l busy ready vcc @ vcc = 3.3v, ta = 25 c , c l = 100pf 2.0v tf tr 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 96 tf 189 290 381 4.2 4.2 4.2 4.2 3.3 1.65 1.1 0.825 0.8v figure 9. rp vs tr ,tf & rp vs ibusy
kbc00a6a0m revision 1.1 october 2003 - 14 - preliminary mcp memory the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 1.3v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 10 m s is required before internal circuit gets ready for any command sequences as shown in figure 10. the two step command sequence for program/erase provides additional software protection. figure 10. ac waveforms for power transition v ccf wp high ? ? we ~ 2.5v ~ 2.5v ? 10 m s data protection & powerup sequence
kbc00a6a0m revision 1.1 october 2003 - 15 - preliminary mcp memory flash absolute maximum ratings note: 1. minimum dc voltage is -0.6v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in/out -0.6 to + 4.6 v v cc -0.6 to + 4.6 temperature under bias t bias -40 to +125 c operating temperature t a -25 to +85 c storage temperature t stg -65 to +150 c u t ram absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than 1 second may affect reli- ability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v cc +0.3v v voltage on vcc supply relative to vss v cc -0.2 to 3.6v v power dissipation p d 1.0 w operating temperature t a -25 to 85 c storage temperature t stg -65 to 150 c sram absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than 1 second may affect reli- ability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.5 to v cc +0.3v v voltage on vcc supply relative to vss v cc -0.3 to 3.6 v power dissipation p d 1.0 w operating temperature t a -25 to 85 c storage temperature t stg -65 to 150 c
kbc00a6a0m revision 1.1 october 2003 - 16 - preliminary mcp memory flash/u t ram/sram recommended operating conditions (t a =-25 to 85 c) parameter symbol min typ. max unit supply voltage v cc 2.7 2.9 3.1 v ground v ss 0 0 0 v flash dc and operating characteristics (recommended operating conditions) parameter symbol test conditions min typ max unit input leakage current i li v in =0 to vcc(max) - - 10 m a output leakage current i lo v out =0 to vcc(max) - - 10 operating current sequential read i cc 1 trc=50ns, ce =v il i out =0ma - 10 20 ma program i cc 2 - - 10 20 erase i cc 3 - - 10 20 input high voltage v ih - 2.0 - v cc +0.3 v input low voltage, all inputs v il - -0.3 - 0.8 output high voltage level v oh i oh =-400 m a 2.4 - - output low voltage level v ol i ol =2.1ma - - 0.4 output low current(r/ b ) i ol (r/ b ) v ol =0.4v 8 10 - ma stand-by current(ttl) i sb 1 ce =v ih , wp =0v/v cc - - 1 ma stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 10 50 m a
kbc00a6a0m revision 1.1 october 2003 - 17 - preliminary mcp memory 64mbit u t ram dc and operating characteristics 1. typical values are tested at v cc =2.9v, t a =25 c and not guaranteed. 2. in case that the device maintains standby state without any read or write activity after power up, the standby current will b e increased and so the device may not meet the specification presented above.[see page 33 "timing waveform of power up"] 3. overshoot: vcc+1.0v in case of pulse width 20ns. 4. undershoot: -1.0v in case of pulse width 20ns. 5. overshoot and undershoot are sampled, not 100% tested. item symbol test conditions min typ 1) max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih, zz =v ih , oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 0.2v, zz 3 vcc-0.2v, v in 0.2v or v in 3 v cc -0.2v - 3 7 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs =v il , zz =v ih, v in =v il or v ih - 35 40 ma input high voltage v ih - 2.2 - vcc+0.3 2) v input low voltage v il - -0.3 3) - 0.6 v output high voltage v oh i oh =-1.0ma 2.4 - - v output low voltage v ol i ol =2.1ma - - 0.4 v standby current(cmos) i sb1 cs 3 vcc-0.2v, zz 3 vcc-0.2v, other inputs=vss to vcc - 80 100 m a deep power down i sbd zz 0.2v, other inputs=vss to vcc - - 20 m a 32mbit u t ram dc and operating characteristics 1. typical values are tested at v cc =2.9v, t a =25 c and not guaranteed. 2. in case that the device maintains standby state without any read or write activity after power up, the standby current will b e increased and so the device may not meet the specification presented above.[see page 33 "timing waveform of power up"] 3. overshoot: vcc+1.0v in case of pulse width 20ns. 4. undershoot: -1.0v in case of pulse width 20ns. 5. overshoot and undershoot are sampled, not 100% tested. item symbol test conditions min typ 1) max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih, zz =v ih , oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 0.2v, zz 3 vcc-0.2v, v in 0.2v or v in 3 v cc -0.2v - 4 7 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs =v il , zz =v ih, v in =v il or v ih - 30 35 ma input high voltage v ih - 2.2 - vcc+0.3 3) v input low voltage v il - -0.3 4) - 0.6 v output high voltage v oh i oh =-1.0ma 2.4 - - v output low voltage v ol i ol =2.1ma - - 0.4 v standby current(cmos) i sb1 2) cs 3 vcc-0.2v, zz 3 vcc-0.2v, other inputs=vss to vcc - 80 100 m a deep power down i sbd zz 0.2v, other inputs=vss to vcc - 5 10 m a
kbc00a6a0m revision 1.1 october 2003 - 18 - preliminary mcp memory sram dc and operating characteristics (v cc =2.7~3.1v, t a =-25 to 85 c) 1. typical values are measured at v cc =2.9v, t a =25 c and not 100% tested. 2. overshoot: v cc +2.0v in case of pulse width 20ns. 3. undershoot: -2.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol test conditions min typ 1) max unit input leakage current i li v in =vss to v cc -1 - 1 m a output leakage current i lo cs 1 =v ih or cs 2 =v il or oe =v ih or we =v il or lb = ub =v ih , v io =vss to v cc -1 - 1 m a average operating current i cc1 cycle time=1 m s, 100%duty, i io =0ma, cs 1 0.2v, lb 0.2v or/and ub 0.2v, cs 2 3 v cc -0.2v, v in 0.2v or v in 3 v cc -0.2v - - 3 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs 1 0.2v, lb 0.2v or/and ub 0.2v, cs 2 3 v cc -0.2v, v in 0.2v or v in 3 v cc -0.2v - 30 35 ma input high voltage v ih - 2.2 - v cc +0.3 2) v input low voltage v il - -0.3 3) - 0.6 v output high voltage v oh i oh = -1.0ma 2.4 - - v output low voltage v ol i ol = 2.1ma - - 0.4 v standby current(cmos) i sb1 other input =0~vcc 1) cs 1 3 v cc -0.2v, cs 2 3 v cc -0.2v( cs 1 controlled) or 2) 0v cs 2 0.2v(cs 2 controlled) - 0.5 15 m a
kbc00a6a0m revision 1.1 october 2003 - 19 - preliminary mcp memory capacitance (t a = 25 c, f = 1.0mhz) note: capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c dq v il =0v - 40 pf input capacitance c in v in =0v - 40 pf valid block(flash) note: 1. the flash memory may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid blocks is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not try to access these invalid blocks for program and erase. refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correcti on. parameter symbol min typ. max unit valid block number n vb 1004 - 1024 blocks standby mode state machines(u t ram) standby mode characteristic(64mbit u t ram) power mode memory cell data standby current( m m a) wait time( m m s) standby valid 100 0 deep power down invaild 20 200 standby mode characteristic(32mbit u t ram) power mode memory cell data standby current( m m a) wait time( m m s) standby valid 100 0 deep power down invaild 10 200 zz =v il cs =v ih zz =v il cs =v il , ub or/and lb =v il zz =v ih cs =v ih , zz =v ih power on initial state (wait 200 m s) active standby mode deep power down mode zz =v ih cs =v ih and zz =v ih
kbc00a6a0m revision 1.1 october 2003 - 20 - preliminary mcp memory flash ac test condition parameter value input pulse levels 0.4v to 2.4v input rise and fall times 5ns input and output timing levels 1.5v output load 1 ttl gate and cl=50pf flash program/erase characteristics parameter symbol min typ max unit program time t prog - 200 500 m s number of partial program cycles in the same page main array nop - - 2 cycles spare array - - 3 cycles block erase time t bers - 2 3 ms flash ac timing characteristics for command / address / data input note: 1. if tcs is set less than 10ns, twp must be minimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol min max unit cle set-up time t cls 0 - ns cle hold time t clh 10 - ns ce setup time t cs 0 - ns ce hold time t ch 10 - ns we pulse width t wp (1) 25 - ns ale setup time t als 0 - ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 45 - ns we high hold time t wh 15 - ns
kbc00a6a0m revision 1.1 october 2003 - 21 - preliminary mcp memory flash ac characteristics for operation note: 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. parameter symbol min max unit data transfer from cell to register t r - 10 m s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 25 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns ce access time t cea - 45 ns re access time t rea - 30 ns re high to output hi-z t rhz - 30 ns ce high to output hi-z t chz - 20 ns re or ce high to output hold t oh 15 - ns re high hold time t reh 15 - ns output hi-z to re low t ir 0 - ns we high to re low t whr 60 - ns device resetting time (read/program/erase) t rst - 5/10/500 (1) m s
kbc00a6a0m revision 1.1 october 2003 - 22 - preliminary mcp memory flash command latch cycle ce we cle ale dq 0 ~ 15 command t cls t cs t clh t ch t wp t als t alh t ds t dh flash address latch cycle ce we cle ale dq 0 ~ 15 a 0 ~a 7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh a 9 ~a 16 t wc t wp t ds t dh t alh t als t wh a 17 ~a 23 t wp t ds t dh t alh
kbc00a6a0m revision 1.1 october 2003 - 23 - preliminary mcp memory flash input data latch cycle ce cle we dq 0 ~ 15 din 0 din 1 din 263 ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp ? ? ? flash serial access cycle after read (cle=l, we =h, ale=l) dq 0 ~ 15 notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. re ce r/ b dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz* ? ? ? ? t rhz* t chz* t rp
kbc00a6a0m revision 1.1 october 2003 - 24 - preliminary mcp memory flash status read cycle dq 0 ~ 15 flash read1 operation (read one page) ce cle r/ b dq 0 ~ 15 we ale re busy 00h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 23 dout n dout n+1 dout n+2 dout n+3 column address page(row) address t wb t ar t r t rc t rhz t chz dout 263 t wc t rr ? ? ? ce we cle re 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir t oh t oh t whr t cea t cls t rhz t chz t oh n address t oh
kbc00a6a0m revision 1.1 october 2003 - 25 - preliminary mcp memory flash read1 operation (intercepted by ce ) ce n cle r/ b n we ale re busy dout n dout n+1 dout n+2 dout n+3 page(row) address address column t wb t ar t chz t r t rr t rc n address 00h dq 0 ~ 15 a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 23 t oh flash read2 operation (read one page) ce cle r/ b dq 0 ~ 15 we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 23 dout dout 263 m address a 0 ~ a 2 :valid address a 3 ~ a 7 :"l" 256+m dout 256+m+1 t ar t r t wb t rr ? ? ? selected row start address m 256 8
kbc00a6a0m revision 1.1 october 2003 - 26 - preliminary mcp memory flash page program operation ce cle r/ b dq 0 ~ 15 we ale re 80h 70h dq 0 din n din din 10h 263 n+1 a 0 ~ a 7 a 17 ~ a 23 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 264 word data sequential input program command read status command dq 0 =0 successful program dq 0 =1 error in program t prog t wb t wc t wc t wc ? ? ? flash block erase operation (erase one block) ce cle r/ b dq 0 ~ 15 we ale re 60h a 17 ~ a 23 a 9 ~ a 16 auto block erase erase command read status command dq 0 =1 error in erase doh 70h dq 0 busy t wb t bers dq 0 =0 successful erase page(row) address t wc ? setup command
kbc00a6a0m revision 1.1 october 2003 - 27 - preliminary mcp memory flash manufacture & device id read operation ce cle dq 0 ~ 15 we ale re 90h read id command maker code device code 00h ech 53h t rea address 1st cycle t ar
kbc00a6a0m revision 1.1 october 2003 - 28 - preliminary mcp memory 64mbit u t ram ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage: 1.5v output load: c l =50pf 64mbit u t ram ac characteristics (vcc=2.7~3.1v, t a =-25 to 85 c) 1. t wp (min)=70ns for continuous write operation over 50 times. parameter list symbol speed units 70ns min max read read cycle time t rc 70 - ns address access time t aa - 70 ns chip select to output t co - 70 ns output enable to valid output t oe - 35 ns ub , lb access time t ba - 70 ns chip select to low-z output t lz 10 - ns ub , lb enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz 0 25 ns ub , lb disable to high-z output t bhz 0 25 ns output disable to high-z output t ohz 0 25 ns output hold from address change t oh 5 - ns write write cycle time t wc 70 - ns chip select to end of write t cw 60 - ns address set-up time t as 0 - ns address valid to end of write t aw 60 - ns ub , lb valid to end of write t bw 60 - ns write pulse width t wp 55 1) - ns write recovery time t wr 0 - ns write to output high-z t whz 0 25 ns data to write time overlap t dw 30 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns
kbc00a6a0m revision 1.1 october 2003 - 29 - preliminary mcp memory 32mbit u t ram ac characteristics (vcc=2.7~3.1v, t a =-25 to 85 c) 1. t wp (min)=85ns for continuous write operation over 50 times. parameter list symbol speed bins units 85ns 1) min max read read cycle time t rc 85 - ns address access time t aa - 85 ns chip select to output t co - 85 ns output enable to valid output t oe - 40 ns ub , lb access time t ba - 85 ns chip select to low-z output t lz 10 - ns ub , lb enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz 0 25 ns ub , lb disable to high-z output t bhz 0 25 ns output disable to high-z output t ohz 0 25 ns output hold from address change t oh 5 - ns write write cycle time t wc 85 - ns chip select to end of write t cw 70 - ns address set-up time t as 0 - ns address valid to end of write t aw 70 - ns ub , lb valid to end of write t bw 70 - ns write pulse width t wp 60 1) - ns write recovery time t wr 0 - ns write to output high-z t whz 0 25 ns data to write time overlap t dw 35 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns 32mbit u t ram ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage: 1.5v output load: c l =50pf
kbc00a6a0m revision 1.1 october 2003 - 30 - preliminary mcp memory u t ram timing diagrams address data out previous data valid data valid timing waveform of read cycle(1) (address controlled , cs = oe =v il , zz = we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( zz = we =v ih ) t aa t rc t oh (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. 3. t oe (max) is met only when oe becomes enabled after t aa (max). 4. if invalid address signals shorter than min. t rc are continuously repeated for over 4us, the device needs a normal read timing(t rc ) or needs to sustain standby state for min. t rc at least once in every 4us. data valid high-z t rc1 t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t rc2 t co address cs ub , lb oe data out
kbc00a6a0m revision 1.1 october 2003 - 31 - preliminary mcp memory t as(3) timing waveform of write cycle(1) ( we controlled , zz =v ih ) timing waveform of write cycle(2) ( cs controlled , zz =v ih ) address data undefined ub , lb we data in data out t wc t cw(2) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) cs t wr(4)
kbc00a6a0m revision 1.1 october 2003 - 32 - preliminary mcp memory timing waveform of write cycle(3) ( ub , lb controlled , zz =v ih ) (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs timing waveform of deep power down mode zz mode deep power down mode normal operation 0.5 m s 200 m s normal operation suspend wake up ? ? cs (deep power down mode) 1. when you toggle zz pin low, the device gets into the deep power down mode after 0.5 m s suspend period. 2. to return to normal operation, the device needs wake up period. 3. wake up sequence is just the same as power up sequence.
kbc00a6a0m revision 1.1 october 2003 - 33 - preliminary mcp memory min. 200 m s v cc zz cs timing waveform of power up ? (power up) 1. after v cc reaches v cc (min.), wait 200 m s with cs and zz high. then you get into the normal operation. v cc(min) ? ? normal operation power up sequence 1. apply power. 2. maintain stable power(vcc min.=2.7v) for a minimum 200 m s with cs and zz high. min. 0ns power up mode min. 0ns
kbc00a6a0m revision 1.1 october 2003 - 34 - preliminary mcp memory sram ac operating conditions test conditions (test load and input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage: 1.5v output load(see right): c l =30pf+1ttl data retention characteristics 1. 1) cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or 2) 0 cs 2 0.2v(cs 2 controlled) 2. typical value is measured at t a =25 c and not 100% tested. item symbol test condition min typ 2) max unit vcc for data retention v dr cs 1 3 vcc-0.2v 1) 1.5 - 3.1 v data retention current i dr vcc=1.5v, cs 1 3 vcc-0.2v 1) - 0.5 6 m a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr trc - - sram ac characteristics (vcc=2.7~3.1v, t a =-25 to 85 c) parameter list symbol speed bins units 55ns min max read read cycle time t rc 55 - ns address access time t aa - 55 ns chip select to output t co - 55 ns output enable to valid output t oe - 25 ns ub , lb access time t ba - 55 ns chip select to low-z output t lz 10 - ns ub , lb enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz 0 20 ns ub , lb disable to high-z output t bhz 0 20 ns output disable to high-z output t ohz 0 20 ns output hold from address change t oh 10 - ns write write cycle time t wc 55 - ns chip select to end of write t cw 45 - ns address set-up time t as 0 - ns address valid to end of write t aw 45 - ns ub , lb valid to end of write t bw 45 - ns write pulse width t wp 40 - ns write recovery time t wr 0 - ns write to output high-z t whz 0 20 ns data to write time overlap t dw 25 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns c l 1) 1. including scope and jig capacitance r 2 2) r 1 2) v tm 3) 2. r 1 =3070 w , r 2 =3150 w 3. v tm =2.8v
kbc00a6a0m revision 1.1 october 2003 - 35 - preliminary mcp memory sram timing diagrams address data out previous data valid data valid timing waveform of read cycle(1) (address controlled , cs 1 = oe =v il , cs 2 = we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( we =v ih ) data valid high-z t rc cs 1 address ub , lb oe data out t aa t rc t oh t oh t aa t co t ba t oe t olz t blz t lz t ohz t bhz t hz notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2
kbc00a6a0m revision 1.1 october 2003 - 36 - preliminary mcp memory timing waveform of write cycle(2) ( cs 1 controlled) address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) t as(3) cs 1 cs 2 timing waveform of write cycle(1) ( we controlled) address cs 1 data undefined ub , lb we data in data out t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs 2
kbc00a6a0m revision 1.1 october 2003 - 37 - preliminary mcp memory address data valid ub , lb we data in data out high-z high-z timing waveform of write cycle(3) ( ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs 1 and low we . a write begins when cs 1 goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest tran- sition when cs 1 goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs 1 going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs 1 or we going high. t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw data retention wave form cs 1 controlled v cc 2.7v 2.2v v dr cs 1 gnd data retention mode cs 1 3 v cc - 0.2v t sdr t rdr t as(3) cs 1 cs 2 cs 2 controlled v cc 2.7v 0.4v v dr cs 2 gnd data retention mode t sdr t rdr cs 2 0.2v
kbc00a6a0m revision 1.1 october 2003 - 38 - preliminary mcp memory nand flash technical notes identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nfor- mation regarding the invalid block(s) is so called as the invalid block information. devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the perf or- mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system d esign must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is fully guar- anteed to be a valid block, does not require error correction. all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 1st & 6th word(x16 device) in the spare area. samsung makes sure that either the 1st or 2nd pa ge of every invalid block has non-ffffh(x16 device) data at the column address of 256 and 261(x16 device). since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block tabl e via the following suggested flow chart(figure 11). any intentional erasure of the original invalid block information is prohibited. * check "ffh" at the column address figure 11. flow chart to create invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table of the 1st and 2nd page in the block 256 and 261(x16 device)
kbc00a6a0m revision 1.1 october 2003 - 39 - preliminary mcp memory nand flash technical notes figure 12. flash program flow chart start dq 6 = 1 ? write 00h dq 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status registe write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation over its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for the actual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, so you can execute block replacement on a page basis with a page sized buffer. t o improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be recla imed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
kbc00a6a0m revision 1.1 october 2003 - 40 - preliminary mcp memory nand flash technical notes figure 13. flash erase flow chart start dq 6 = 1 ? dq 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes figure 14. flash read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes figure 15. flash block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not further erase block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { ~ 1st (n-1)th nth (page) { ~ an error occurs.
kbc00a6a0m revision 1.1 october 2003 - 41 - preliminary mcp memory samsung nand flash(x16) has two address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255word), and ?50h? command sets the pointer to ?b? area(256~263word). with these com- mands, the starting column address can be set to any of a whole page(0~263word). ?00h? or ?50h? is sustained until another addre ss pointer command is inputted. to program data starting from ?a? or ?b? area, ?00h? or ?50h? command must be inputted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. pointer operation of nand flash figure 16. block diagram of pointer operation nand flash technical notes table 7. destination of the pointer command pointer position area 00h 50h 0 ~ 255 word 256 ~ 263 word main array(a) spare array(b) "a" area 256 word (00h plane) "b" area (50h plane) 8 word "a" "b" internal page register pointer select command (00h, 50h) pointer 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 50h (2) command input sequence for programming ?b? area address / data input 80h 10h 50h 80h 10h address / data input only ?b? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?b? area(256~263), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b? area can be programmed.
kbc00a6a0m revision 1.1 october 2003 - 42 - preliminary mcp memory nand flash technical notes ce we t wp t ch t cs start add.(3cycle) 80h data input ce cle ale we dq 0 ~ 15 data input ce don?t-care ? ? 10h for an easier system interface, ce may be inactive during data-loading or sequential data-reading as shown below. the internal 264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition , for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant saving in power consumption. start add.(3cycle) 00h ce cle ale we dq 0 ~ 15 data output(sequential) ce don?t-care ? r/ b t r re t cea out t rea ce re dq 0 ~ 15 figure 17. program operation with ce don?t-care. figure 18. read operation with ce don?t-care. system interface using ce don?t-care.
kbc00a6a0m revision 1.1 october 2003 - 43 - preliminary mcp memory package dimension 87 -ball tape ball grid array package (measured in millimeters) top view bottom view side view 10.00 0.10 1 2 . 0 0 0 . 1 0 #a1 a b c e g d f h 0.80x9=7.20 a 0 . 8 0 x 1 2 = 9 . 6 0 87- ? 0.45 0.05 j 4 . 8 0 0 . 8 0 b 0.20 m a b ? (datum a) (datum b) 1 4 2 7 6 5 3 8 3.60 #a1 index mark(optional) l k m n 0 . 8 0 10.00 0.10 1 2 . 0 0 0 . 1 0 9 10 0.08 max 0.45 0.05 0 . 3 2 0 . 0 5 1 . 3 0 0 . 1 0 12.00 0.10

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