aerospace electronics advance information features general description the 512k x 8 radiation tolerant static ram is a high performance 524,288 word x 8-bit static random access memory with optional industry-standard functionality. it is fabricated with honeywell?s radiation hardened technol- ogy, and is designed for use in low voltage systems operating in radiation environments. the ram operates over the full military temperature range and requires only a single 3.3 v 0.3v power supply. power consumption is typically less than 9.5 mw/mhz in operation, and less than 6 mw when de-selected. honeywell?s enhanced soi ricmos? v (radiation in- sensitive cmos) technology is radiation hardened through the use of advanced and proprietary design, layout and process hardening techniques. the ricmos? v low power process is a simox cmos technology with a 80 ? gate oxide and a minimum drawn feature size of 0.35 m. additional features include tungsten via and contact plugs, honeywell?s proprietary sharp planarization process and a lightly doped drain (ldd) structure for improved short channel reliability. a seven transistor (7t) memory cell is used for superior single event upset hardening, while three layer metal power busing and the low collection volume simox substrate provide improved dose rate hardening. radiation ? fabricated with ricmos? v silicon on insulator (soi) 0.35 m process (l eff = 0.28 m) ? total dose hardness 3x10 5 rad(sio 2 ) (optional 1x10 6 rad(sio 2 ) ? neutron hardness 1x10 14 cm -2 ? dynamic and static transient upset hardness 1x10 10 rad(si)/s (3.3 v) ? dose rate survivability 1x10 12 rad(si)/s ? soft error rate upsets/bit-day 1x10 -10 (3.3 v) ? no latchup other ? read/write cycle times 20 ns, (3.3 v), 0 to 80 c 25 ns, (3.3 v), -55 to 125 c ? typical operating power 9.5 mw/mhz (3.3 v) ? asynchronous operation ? cmos compatible i/o ? single power supply, 3.3 v 0.3 v ? operating range is -55 c to +125 c ? package options: ? 36-lead flat pack ? optional low power sleep mode 512k x 8 static ram?soi hx6408 solid state electronics center ? 12001 state highway 55, plymouth, mn 55441 ? (800) 238-1502 ? http://www.ssec.honeywell. com
hx6408 2 signal definitions a: 0-18 address input pins which select a particular eight-bit word within the memory array. dq: 0-7 bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. ncs negative chip select, when at a low level allows normal read or write operation. when at a high level ncs forces the sram to a precharge condition, holds the data output drivers in a high impedance state. if this signal is not used it must be connected to vss. nwe negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. when at a high level nwe allows normal read operation. noe negative output enable, when at a high level holds the data output drivers in a high impedance state. when at a low level, the data output driver state is defined by ncs, nwe and nsl. if this signal is not used it must be connected to vss. this signal is asynchronous. nsl not sleep, when at a high level allows normal operation. when at a low level nsl forces the sram to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the ncs and noe input buffers. if this signal is not used it must be connected to vdd. this signal is asynchronous. the hx6408 may be ordered without the sleep mode option and pin 36 is then a nc. truth table functional diagram x: vi=vih or vil, noe=h: high z output state maintained for ncs=x, ce=x, nwe=x ncs nsl nwe noe mode dq l h h l read data out l h l x write data in h x x x deselected high z x l x x sleep high z nsl an nwe we ? cs address decoder memory array all controls must be enabled for a signal to pass. (#: number of buffers, default = 1) # signal 1 = enabled signal dq:0-7 8 ncs noe nwe ? cs 8 timing / control
3 hx6408 total dose 3x10 5 (optional 1x10 6 ) rad(sio 2 ) transient dose rate upset 1x10 10 rad(si)/s transient dose rate survivability 1x10 12 rad(si)/s soft error rate <1x10 -10 upsets/bit-day neutron fluence 1x10 14 n/cm 2 parameter limits (2) test conditions radiation hardness ratings (1) units t a =25 c total ionizing radiation dose the sram will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. all electrical and timing performance parameters will remain within speci- fications after rebound at vdd = 3.6 v and t =125 c ex- trapolated to ten years of operation. total dose hardness is assured by wafer level testing of process monitor transistors and ram product using 10 kev x-ray and co60 radiation sources. transistor gate threshold shift correlations have been made between 10 kev x-rays applied at a dose rate of 1x10 5 rad(sio 2 )/min at t = 25 c and gamma rays (cobalt 60 source) to ensure that wafer level x-ray testing is consistent with standard military radiation test environments. transient pulse ionizing radiation the sram is capable of writing, reading, and retaining stored data during and after exposure to a transient ioniz- ing radiation pulse, up to the specified transient dose rate upset specification, when applied under recommended operating conditions. to ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation is 10%), it is suggested that stiffening capacitance be placed near the package vdd and vss, with a maximum inductance between the package (chip) and stiffening ca- pacitance of 0.7 nh per part. if there are no operate- through or valid stored data requirements, typical circuit board mounted de-coupling capacitors are recommended. the sram will meet any functional or electrical specifica- (1) device will not latch up due to any of the specified radiation exposure conditions. (2) operating conditions (unless otherwise specified): vdd=3.0 v to 3.6 v, ta=-55 c to 125 c. 1 mev equivalent energy, unbiased, t a =25 c t a =85 c, adams 90% worst case environment pulse width 50 ns, x-ray, vdd=3.6 v, t a =25 c pulse width 50 ns vdd>3.6v, ta=25 c radiation characteristics tion after exposure to a radiation pulse up to the transientdose rate survivability specification, when ap- plied under recommended operating conditions. note that the current conducted during the pulse by the ram inputs, outputs, and power supply may significantly ex- ceed the normal operating levels. the application design must accommodate these effects. neutron radiation the sram will meet any functional or timing specification after exposure to the specified neutron fluence under recommended operating or storage conditions. this as- sumes an equivalent neutron energy of 1 mev. soft error rate the sram is capable of meeting the specified soft error rate (ser), under recommended operating conditions. this hardness level is defined by the adams 90% worst case cosmic ray environment for geosynchronous orbits. latchup the sram will not latch up due to any of the above radiation exposure conditions when applied under recom- mended operating conditions. fabrication with the simox substrate material provides oxide isolation between adja- cent pmos and nmos transistors and eliminates any potential scr latchup structures. sufficient transistor body tie connections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs.
hx6408 4 parameter max symbol test conditions worst case units capacitance (1) symbol test conditions min max typical (1) units vdr data retention voltage 2.25 v idr data retention current 1 ma (1) this parameter is tested during initial design characterization only. recommended operating conditions symbol max typ description parameter min worst case (2) units vdd supply voltage (referenced to vss) 3.0 3.3 3.6 v ta ambient temperature -55 25 125 c vpin voltage on any pin (referenced to vss) -0.3 vdd+0.3 v min typical (1) ci input capacitance 7 pf vi=vdd or vss, f=1 mhz co output capacitance 9 pf vio=vdd or vss, f=1 mhz (1) typical operating conditions: ta= 25 c, pre-radiation. (2) worst case operating conditions: ta= -55 c to +125 c, post total dose at 25 c. data retention characteristics parameter (1) stresses in excess of those listed above may result in permanent damage. these are stress ratings only, and operation at the se levels is not implied. frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) voltage referenced to vss. (3) ram power dissipation (iddsb + iddop) plus ram output driver power dissipation due to external loading must not exceed this specification. (4) class 2 electrostatic discharge (esd) input protection. tested per mil-std-883, method 3015 by desc certified lab. absolute maximum ratings (1) ncs=vdd=vdr vi=vdr or vss ncs=vdr vi=vdr or vss vdd supply voltage range (2) -0.5 4.6 v vpin voltage on any pin (2) -0.5 vdd+0.5 v tstore storage temperature (zero bias) -65 150 c tsolder soldering temperature (5 seconds) 270 c pd maximum power dissipation (3) 2 w iout dc or average output current 25 ma vprot esd input protection voltage 2000 v 36 pin fp 2 tj junction temperature 175 c parameter symbol jc thermal resistance (jct-to-case) c/w units rating min max
5 hx6408 dc electrical characteristics (1) worst case operating conditions: vdd=3.0 v to 3.6 v, -55 c to +125 c, post total dose at 25 c. (2) all inputs switching. dc average current. dut output valid low output vref1 c l > 50 pf* 249 ? tester equivalent load circuit 2.2 v valid high output vref2 - + - + *c l = 5 pf for twlqz, tshqz, tplqz, and tghqz l o b m y sr e t e m a r a p e s a c t s r o w ) 1 ( s t i n us n o i t i d n o c t s e t n i mx a m b s d d it n e r r u c y l p p u s c i t a t s5a m e l b a t s s t u p n i , a m 0 = t u o i , x a m = d d v l s d d iw o l l s n h t i w t n e r r u c y l p p u s c i t a t s5a m x a m f = f , a m 0 = t u o i , x a m = d d v w p o d d i) e t i r w ( d e t c e l e s , t n e r r u c y l p p u s c i m a n y d3z h m / a m z h m 1 = f , a m 0 - t u o i , x a m = d d v ) 1 ( l i v = s c n , h i v = l s n r p o d d i) d a e r ( d e t c e l e s , t n e r r u c y l p p u s c i m a n y d3z h m / a m ) z h m 1 = f , a m 0 - t u o i , x a m = d d v ) 1 ( l i v = s c n , h i v = l s n p o d d id e t c e l e s e d , t n e r r u c y l p p u s c i m a n y d1a m z h m 1 = f , a m 0 - t u o i , x a m = d d v ) 2 ( h i v = s c n = l s n i it n e r r u c e g a k a e l t u p n i5 -5a d d v i v s s v z o it n e r r u c e g a k a e l t u p t u o0 1 -0 1a d d v o i v s s vz h g i h = t u p t u o l i ve g a t l o v t u p n i l e v e l - w o l v x 3 . 0 d d v v 0 . 3 = d d v h i ve g a t l o v t u p n i l e v e l - h g i hv x 7 . 0 d d v v 6 . 3 = d d v l o ve g a t l o v t u p t u o l e v e l - w o l4 . 0v a m 8 = l o i , v 0 . 3 = d d v h o ve g a t l o v t u p t u o l e v e l - h g i h4 . 2v a m 4 = h o i , v 0 . 3 = d d v
hx6408 6 tavavr address read cycle time 25 ns tavqv address access time 25 ns taxqx address change to output invalid time 3 ns tslqv chip select access time 25 ns tslqx chip select output enable time 5 ns tshqz chip select output disable time 10 ns tphqv sleep enable access time 25 ns tphqx sleep enable output enable time 5 ns tplqz sleep enable output disable time 10 ns tglqv output enable access time 9 ns tglqx output enable output enable time 0 ns tghqz output enable output disable time 9 ns asynchronous read cycle ac timing characteristics (1) worst case (3) symbol parameter typical -55 to 125 c units (2) min max (1) test conditions: input switching levels,vil/vih=0v/3v, input rise and fall times <1 ns/v, input and output timing reference levels shown in the tester ac timing characteristics table, capacitive output loading c l >50 pf, or equivalent capacitive output loading c l =5 pf for tshqz, tplqz tghqz. for c l >50 pf, derate access times by 0.02 ns/pf (typical). (2) typical operating conditions: vdd=3.3 v, ta=25 c, pre-radiation. (3) worst case operating conditions: vdd=3.0 v to 3.6 v, ta= -55 c to 125 c, post total dose at 25 c. high impedance ncs noe data valid nsl t avavr t avqv t axqx t slqv t slqx t shqz t phqx t phqv t glqx t glqv t ghqz t plqz address (nwe = high) data out
7 hx6408 asynchronous write cycle ac timing characteristics (1) symbol parameter typical -55 to 125 c units (2) min max worst case (3) tavavw write cycle time (4) 25 ns twlwh write enable write pulse width 20 ns tslwh chip select to end of write time 20 ns tdvwh data valid to end of write time 15 ns tavwh address valid to end of write time 20 ns twhdx data hold time after end of write time 0 ns tavwl address valid setup to start of write time 0 ns twhax address valid hold after end of write time 0 ns twlqz write enable to output disable time 0 9 ns twhqx write disable to output enable time 5 ns twhwl write disable to write enable pulse width (5) 5 ns tphwh sleep enable to end of write time 20 ns (1) test conditions: input switching levels, vil/vih=0v/3v, input rise and fall times <1 ns/v, input and output timing reference levels shown in the tester ac timing characteristics table, capacitive output loading >50 pf, or equivalent capacitive load of 5 pf for twlqz. (2) typical operating conditions: vdd=3.3 v, ta=25 c, pre-radiation. (3) worst case operating conditions: vdd=3.0 v to 3.6 v, -55 to 125 c, post total dose at 25 c. (4) tavavw = twlwh + twhwl (5) guaranteed but not tested. nsl address high impedance data out nwe data in data valid t avavw ncs t avwh t wlwh t avwl t wlqz t dvwh t whqx t whdx t slwh t phwh t whax t whwl
hx6408 8 dynamic electrical characteristics asynchronous operation the ram in asynchronous in operation, allows the read cycle to be controlled by address, chip select (ncs), or not sleep (nsl) (refer to read cycle timing diagram). to perform a valid read operation, both chip select and output enable (noe) must be low and not sleep (nsl) and write enable (nwe) must be high. the output drivers can be controlled independently by the noe signal. consecutive read cycles can be executed with ncs held continuously low, and with nsl held continuously high, and toggling the addresses. for an address activated read cycle, ncs and nsl must be valid prior to or coincident with the activating address edge transition(s). any amount of toggling or skew be- tween address edge transitions is permissible; however, data outputs will become valid tavqv time following the latest occurring address edge transition. the minimum address activated read cycle time is tavav. when the ram is operated at the minimum address activated read cycle time, the data outputs will remain valid on the ram i/o until taxqx time following the next sequential ad- dress transition. to control a read cycle with ncs, all addresses and nsl must be valid prior to or coincident with the enabling ncs edge transition. address or nsl edge transitions can occur later than the specified setup times to ncs; how- ever, the valid data access time will be delayed. any address edge transition, which occurs during the time when ncs is low, will initiate a new read access, and data outputs will not become valid until tavqv time following the address edge transition. data outputs will enter a high impedance state tshqz time following a disabling ncs edge transition. to control a read cycle with nsl, all addresses and ncs must be valid prior to or coincident with the enabling nsl edge transition. address or ncs edge transitions can occur later than the specified setup times to nsl; how- ever, the valid data access time will be delayed. any address edge transition which occurs during the time when nsl is high will initiate a new read access, and data outputs will not become valid until tavqv time following the address edge transition. data outputs will enter a high impedance state tplqz time following a disabling nsl edge transition. the write operation is synchronous with respect to the address bits, and control is governed by write enable (nwe), chip select (ncs), or not sleep (nsl) edge tran- sitions (refer to write cycle timing diagrams). to perform a write operation, both nwe and ncs must be low, and nsl must be high. consecutive write cycles can be performed with nwe or ncs held continuously low, or nsl held continuously high. at least one of the control signals must transition to the opposite state between consecutive write operations. the write mode can be controlled via three different control signals: nwe, ncs, and nsl. all three modes of control are similar, except the ncs and nsl controlled modes actually disable the ram during the write recovery pulse. nsl fully disables the ram decode logic and input buffers for power savings. only the nwe controlled mode is shown in the table and diagram on the previous page for simplicity; however, each mode of control provides the same write cycle timing characteristics. thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low. to write data into the ram, nwe and ncs must be held low and nsl must be held high for at least twlwh/ tslsh/tphph time. any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. for consecutive write operations, write pulses must be sepa- rated by the minimum specified twhwl/tshsl/tplpl time. address inputs must be valid at least tavwl/ tavsl/tavph time before the enabling nwe/ncs/nsl edge transition, and must remain valid during the entire write time. a valid data overlap of write pulse width time of tdvwh/tdvsh/tdvpl, and an address valid to end of write time of tavwh/tavsh/tavpl also must be pro- vided for during the write operation. hold times for address inputs and data inputs with respect to the disabling nwe/ ncs/nsl edge transition must be a minimum of twhax/ tshax/tplpx time and twhdx/tshdx/tpldx time, respectively. the minimum write cycle time is tavav.
9 hx6408 tester ac timing characteristics ing the need to create detailed specifications and offer benefits of improved quality and cost savings through standardization. reliability honeywell understands the stringent reliability requirements for space and defense systems and has extensive experi- ence in reliability testing on programs of this nature. this experience is derived from comprehensive testing of vlsi processes. reliability attributes of the ricmos? process were characterized by testing specially designed irradiated and non-irradiated test structures from which specific failure mechanisms were evaluated. these specific mechanisms included, but were not limited to, hot carriers, electromigra- tion and time dependent dielectric breakdown. this data was then used to make changes to the design models and process to ensure more reliable products. in addition, the reliability of the ricmos? process and product in a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dy- namic life test conditions. packages are qualified for prod- uct use after undergoing groups b & d testing as outlined in mil-std-883, tm 5005, class s. the product is quali- fied by following a screening and testing flow to meet the customer?s requirements. quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product. quality and radiation hardness assurance honeywell maintains a high level of product integrity through process control, utilizing statistical process control, a com- plete ?total quality assurance system,? a computer data base process performance tracking system and a radia- tion-hardness assurance strategy. the radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. radiation hardness is assured on every wafer by irradiating test structures as well as sram product, and then monitor- ing key parameters which are sensitive to ionizing radia- tion. conventional mil-std-883 tm 5005 group e testing, which includes total dose exposure with cobalt 60, may also be performed as required. this total quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and con- tinuing through product qualification and screening. screening levels honeywell offers several levels of device screening to meet your system needs. ?engineering devices? are available with limited performance and screening for breadboarding and/or evaluation testing. hi-rel level b and s devices undergo additional screening per the requirements of mil- std-883. as a qml supplier, honeywell also offers qml class q and v devices per mil-prf-38535 and are avail- able per the applicable standard microcircuit drawing (smd). qml devices offer ease of procurement by eliminat- 3 v 0 v vdd/2 vdd/2 0.4 v high z 2.7 v 1.7 v high z input levels* output sense levels high z = 2.2v * input rise and fall times <1 ns/v vdd-0.4v
hx6408 10 ordering information (1) honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. h oneywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. to learn more about honeywell solid state electronics center, visit our web site at http://www.ssec.honeywell.com (1) orders may be faxed to 612-954-2051. please contact our customer service representative at 612-954-2888 for further informat ion. (2) engineering device description: parameters are tested from -55 to 125 c, 24 hr burn-in, iddsb = 10ma, no radiation guaranteed. (3) with the non-sleep mode option, pin 36 is a no-connect (nc), and is not wire bonded to the chip. with the sleep mode option, pin 36 has nsl function. contact factory with other needs. x process x=low power soi part number s screen level v=qml class v q=qml class q s=class s b=class b e=engineering device (2) 900198 rev. d 2/99 packaging 36-lead flat pack pinout the 512k x 8 is offered in a commercially compatible 36- lead flat pack. this package is constructed of multilayer ceramic (al 2 o 3 ) and contains internal power and ground planes. parentheses denote pin options. these pins are available as nc to conform to commercial standards. h source h=honeywell mode (3) n=non-sleep mode m=sleep mode n h total dose hardness r=1x10 5 rad(sio 2 ) f=3x10 5 rad(sio 2 ) h=1x10 6 rad(sio 2 ) n=no level guaranteed (2) 6408 package designation x=36-lead fp k=known good die ? =bare die (no package) x (nsl) an an an an noe i/om i/om vss vdd i/om i/om an an an an an (nc) an an an an an ncs i/om i/om vdd vss i/om i/om nwe an an an an an top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
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