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document # micro-9 rev b revised august 2005 pace1754/sos processor interface circuit (pic) cmos/sos space processor microperipheral features the pace1754 (pic) is a support chip for the pace1750a/ae processors. it eliminates the ssi/msi logic and external system functions required in typical 1750a implementations. provides a significant savings in part-count and power dissipation enhancing reliability and overall system speed performance. provides an optimal interface when used with the pace1753 mmu/combo in a full 1750a implementation. provides the following additional important system functions: ? programmable ready for memory and i/o ? automatic ready during self-test and internal i/o instructions ? 100khz timer clock output provided ? programmable system watchdog?ranges from 1 s to 1 minute ? programmable bus time-out function ? memory parity generation/detection ? error detection of unimplemented memory and/or i/o space addressing ? first failing memory address register for diagnostics ? high drive three-state address latches ? built-in system test program?automatically tests the pace1750a/ae cpus, pace1753 mmu/combo, pace1754 pic and system address lines as well as memory and i/o strobes ? system configuration decoding and buffering ? interrupt acknowledge decoder and strobe ? start up rom support per mil-std-1750a ? memory or i/o read/write three-state strobes with external three-state control for dma applications available with class s manufacturing, screening, and testing. sos insulated substrate technology provides absolute latch-up immunity and excellent seu tolerance. sos devices are fully interchangeable with application-proven smd cmos p1754 devices. 20, 25 and 30 mhz operation over full military temperature range pace1754 processor interface circuit description the pace1754 processor interface circuit (pic) is a single chip implementation of many special system functions that are often required when using the pace1750a/ae, a single chip microprocessor. the pic allows a system designer to design a higher performance, more effecient microprocessor system which uses less power and takes up less board space. the pic provides many important system functions. these functions are governed by respective bit positions in a programmable control register which is incorporated in the pic. the individual bits of the control register are set to select the various features and are set to a specified default value upon reset. single 5v 10% power supply available in: ? 68-lead quad pack with optional gull wing surface mount
pace1754/sos page 2 of 16 document # micro-9 rev b absolute maximum ratings 1 supply voltage range 0.5v to +7.0v input voltage range 0.5v to v cc + 0.5v storage temperature range ?65c to +150c input current range ?30ma to +5ma current applied to any output 3 150ma maximum power dissipation 2 1.5w lead temperature range (soldering 10 seconds) 300c thermal resistance ( jc ): packages ql and qg 8c/w notes: 1. stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. 2. must withstand the added power dissipation due to short circuit test e.g., i os . 3. duration 1 second or less. recommended operating conditions case temperature gnd v cc ?55c to +125c 0 4.5v to +5.5v
pace1754/sos page 3 of 16 document # micro-9 rev b dc electrical specifications (over recommended operating conditions) symbol parameter min max unit conditions 1 v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage ?0.5 0.8 v v cd input clamp diode voltage ?1.2 v v cc = 4.5v, i in = ?18ma 2.4 v v cc = 4.5v, i oh = ?8.0ma v cc ? 0.2 v v in = 0.8v, 2.0v i oh = ?300a output low voltage, 0.5 v v cc = 4.5v, i ol = 8.0ma except a 0 ? a 15 0.2 v v in = 0.8v, 2.0v i ol = 300a output low voltage, 0.5 v v cc = 4.5v, i ol = 20.0ma a 0 ? a 15 0.2 v v in = 0.8v, 2.0v i ol = 300a input high current, i ih except ib 0 ? ib 15 , parity/ib 16 , 300 a v in = v cc , sing err, a 0 /ext ad 0 ,v cc = 5.5v a 1 /ext ad 1 , strba input high current, v in = v cc , i ih ib 0 ? ib 15 , parity/ib 16 , 100 a v cc = 5.5v a 0 /ext ad 0 , a 1 /ext ad 1 input high current, v in = v cc , strba, sing err v cc = 5.5v input low current, i il except ib 0 ? ib 15 , parity/ib 16 , ?50 a v in = gnd, sing err, a 0 /ext ad 0 ,v cc = 5.5v a 1 /ext ad 1 , strbd , test on input low current, v in = gnd, i il ib 0 ? ib 15 , parity/ib 16 , sing err, ?50 a v cc = 5.5v a 0 /ext ad 0 , a 1 /ext ad 1 input low current, v in = gnd, strbd , test on v cc = 5.5v i ozh output three-state current 50 a v out = 2.4v, v cc = 5.5v i ozl output three-state current ?50 a v out = 0.5v, v cc = 5.5v quiescent power v in < 0.2v or > v cc ? 0.2v i ccqc supply current 25 ma f = 0mhz, outputs open, (cmos input levels) v cc = 5.5v quiescent power v in = 3.4v, f = 0mhz, i ccqt supply current 100 ma all inputs, outputs open, (ttl input levels) v cc = 5.5v dynamic power f = 20mhz 90 ma v in = 0v to v cc , i ccd supply current f = 25mhz 100 ma tr = tf = 2.5 ns typ., f = 30mhz 125 ma outputs open, v cc = 5.5v i os output short circuit current 2 ?25 ma v out = gnd, v cc = 5.5v c in input capacitance 10 pf inputs only c out output/bi-directional 15 pf outputs only capacitance (including i/o buffers) notes: 1. 4.5v v cc 5.5v, ?55c t c +125c. unless otherwise specified, testing shall be conducted at worst-case conditions. 2. duration of the short should not exceed one second; only one output may be shorted at a time. v oh output high voltage v ol v ol i il 300 a i ih 300 a
pace1754/sos page 4 of 16 document # micro-9 rev b ac electrical characteristics 1, 2 (v cc = 5v 10% over recommended operating conditions) 20 mhz 25mhz 30 mhz symbol parameter min max min max min max unit tex rdy (rdyd) v time from external ready to 19 15 14 ns ready data valid tc (rdyd) v time from clock read to 29 25 23 ns ready data valid tstrba h (a) v time from strobe address high to 29 25 23 ns address bus valid tiba v (a) v time from information bus address to 31 27 25 ns address bus valid tfc (r) l time from falling clock to 25 21 19 ns read low t strbd h (r) h time from strobe data high to 25 21 19 ns read high t strbd l (w) l time from strobe data low to 27 23 21 ns write low t strbd h (w) h time from strobe data high to 27 23 21 ns write high tibd in ( me pa er ) l time from information bus data into 24 20 18 ns memory parity error low tiba in ( ex ad er ) time from information bus address into 32 28 26 ns external address error t strbd l ? time from strobe data low to 27 23 21 ns (strt rom) v start-up rom valid tfc (ib out) v time from falling clock to 32 28 26 ns information bus valid tc (timer clk) time from rising edge of clock to 32 28 26 ns timer clock tib in v (ib16) time from information bus data to 26 23 21 ns parity valid text ad (clkb3) extended address 10 10 10 ns setup time t ex rdy1 (rdyd) v time from external ready data to 30 26 24 ns ready data valid t strbd h ( scr en ) time from strbd high to scr enable; 32 28 26 ns notes: 1. 4.5v v cc 5.5v, ?55c t c +125c. unless otherwise specified, testing shall be conducted at worst-case conditions. 2. all measurements of delay times on active signals are related to the 1.5v levels.
pace1754/sos page 5 of 16 document # micro-9 rev b case outlines u and y terminal terminal terminal terminal terminal terminal number symbol number symbol number symbol 1 gnd 2sc 0 3sc 1 4 test on 5 reset 6 test end 7 timer clk 8sc 2 9v cc 10 ib 0 11 ib 1 12 ib 2 13 ib 3 14 ib 4 15 lb 5 16 ib 6 17 ib 7 18 ex rdy 1 19 ib 8 20 ib 9 21 gnd 22 ib 10 23 ib 11 24 ib 12 25 ib 13 26 ib 14 27 ib 15 28 parity /ib 16 29 me pa er /ram dis 30 ex ad er /sing err 31 inta 32 strt rom 33 v cc 34 gnd 35 a 15 36 a 14 37 a 13 38 a 12 39 a 11 40 a 10 41 a 9 42 a 8 43 a 7 44 a 6 45 a 5 46 a 4 47 a 3 48 gnd 49 a 2 50 a 1 /ext ad 1 51 a 0 /ext ad 0 52 sc 4 53 sc 3 54 tc 55 cpu clk 56 strba 57 strbd 58 strb en 59 ex rdy 60 rdyd 61 r/ w 62 gnd 63 m/ io 64 memw 65 memr 66 iow 67 ior 68 v cc terminal connections - packages ql and qg
pace1754/sos page 6 of 16 document # micro-9 rev b strt rom timer clk ib bus output (0:15) ex ad er note: all time measurements on active signals relate to 1.5v levels. extended addresses (0:1)
pace1754/sos page 7 of 16 document # micro-9 rev b rdyd timing test end timing 1 notes: 1. the last two instructions executed during system test are: xio ra, 1f44, 0 and jc 7, 0000 hex, 0. after execution of the iow bus cycle, the xio proceeds by filling the instruction pipe with two memory read bus cycles where the opcode 7070 hex and 0000 hex are entered to the processor. as from the end of strbd in the second cycle, test end is asserted. at this point, the execution of ic starts by first issuing two fetch cycles from the "old pc" (from addresses xxxx & xxxx+1). the data will be taken from system memory (because test end is asserted) but both the address and data are irrelevent. following that, ic will start filling the pipe from address 0000 hex a nd 0001 hex, now from the system memory to start user's program execution. 2. all time measurements on active signals relate to 1.5v levels.
pace1754/sos page 8 of 16 document # micro-9 rev b note: all time measurements on active signals relate to 1.5v levels. address bus and strobes
pace1754/sos page 9 of 16 document # micro-9 rev b note: all time measurements on active signals relate to 1.5v levels. parameter v o v mea tplz 3v 0.5v tphz 0v v cc ? 0.5v tpxl v cc /2 1.5v tpxh v cc /2 1.5v test circuits standard output (non three-state) three-state
pace1754/sos page 10 of 16 document # micro-9 rev b pin functions symbol name description cpu clk cpu clock a single-phase input clock signal (0-40mhz, 40% to 60% duty cycle.) strba strobe address an active high input which latches the contents of ib(0:15) into the address latches. strbd strobe data an active low input which is used for writing or reading data to or from the device and also to produce the external memory and i/o strobes. timer clk timer clock a 100khz output (fixed frequency) based on the programmed operating frequency of the cpu clock. memw memory write strobe an active low output produced in memory write cycles. memr memory read strobe an active low output produced in memory read cycles. iow i/o write strobe an active low output produced in output write cycles. ior i/o read strobe an active low output produced in input read cycles. inta interrupt acknowledge an active low output produced after any interrupt, corresponding to strobe an output write to address 1000 (hex). scr en system configuration an active low output (in 64 pin only) produced any time an input read from address 8410 (hex), read system configuration is executed. strb en strobe enable an active low input, enabling the active state of the address outputs and the memr , memq , ior , and iow outputs. when at a logic "1" (if enabled by bits est, ead of the control register) it will correspondingly enable the three-state state of the above signals. ib 0 - ib 15 information bus (0:15) a bi-directional time multiplexed bus. it is an input during the address phase of any bus cycle and also during the data phase when writing. it is an output during the data phase when reading from the device. ib 16 information bus (16) a bi-directional line. it is an output during write cycles and an input during read cycles. it is used to implement the parity function at the system level. a(0:1)/ address bus (0:15) an active high output bus. contains the address of the current bus ex ad(0:1), cycle as latched by the end of strba. in system configurations a(2:15) including the mmu function, the only active lines during memory are a(4:15). in this case, a(2:3) are high impedance (don't care) and a(0:1) turn into inputs called extended addresses, ext adr (0:1). in this case, these two lines supplied by the mmu, will be used to operate the programmable ready generation during bus cycles. m/ io memory i/o an input qualifier indicating the nature of the current bus cycle.
pace1754/sos page 11 of 16 document # micro-9 rev b pin functions (continued) symbol name description r/ w read or write an input qualifier indicating the nature of the current bus cycle, either read (1) or write (0). reset external reset an active low input used to initialize the device's hardware. test on system test enable an active low input used to enable the execution of the system test built into the device, immediately after completion of the p1750a/ae initialization and before fetching any instruction from the user program. test end system test end an active high output indicating whether the system test in the device has been completed. whenever the system test is disabled by the test on signal, the test end output will be at a logical "1" immediately after reset is removed. strt rom start up rom an output following the execution of the esur and dsur, i/o commands as defined in mil-std-1750a. it will be at the logical "1" level after executing esur and at the logical "0" level after executing dsur. initially, it defaults to a logical "1". rdyd ready data an active high output to be connected to the p1750a/ae input to control the bus cycle termination. ex rdy external ready data an active high input which at logical "0" overrides the internal rdyd generation and forces it to a logical "0". ex rdy 1 external ready data an active low input which at logical "1" overrides the internal rdyd generation and forces it to a logical "0". me pa er / memory parity error an active low output indicating a parity error when reading from ram dis memory. it becomes an active high output called ram disable for handshaking with the p1753 mmu when the device is programmed to support edac. ex ad er / illegal address error an active low output indicating an illegal address error when sing err referencing memory or i/o. it becomes an active high output called single error for handshaking with the p1753 mmu when the device is programmed to support edac. tc terminal count an active high output in dicating a bus time out or a watchdog trigger. sc 0 ?sc 4 system configuration inputs which are buffered onto ib 0 ?ib 4 when executing an i/o read from i/o address 8410 (hex), system configuration. gnd ground 0 volts system ground. v cc power supply 5 volts 10% power supply.
pace1754/sos page 12 of 16 document # micro-9 rev b standardized military pyramid semiconductor pyramid semiconductor drawing part number cage number part number 5962-8864201ux 3dtt2 p1754-20qlmb 5962-8864201yx 3dtt2 p1754-20qgmb 5962-8864201zx 3dtt2 p1754-20pgmb 5962-8864202ux 3dtt2 p1754-30qlmb 5962-8864202yx 3dtt2 p1754-30qgmb 5962-8864202zx 3dtt2 p1754-30pgmb 5962-8864203ux 3dtt2 p1754-40qlmb 5962-8864203yx 3dtt2 p1754-40qgmb 5962-8864203zx 3dtt2 p1754-40pgmb 5962-8864204tx 3dtt2 p1754-20gmb 5962-8864204xx 3dtt2 p1754-20cmb 5962-8864205tx 3dtt2 p1754-30gmb 5962-8864205xx 3dtt2 p1754-30cmb 5962-8864206tx 3dtt2 p1754-40gmb 5962-8864206xx 3dtt2 p1754-40CMB ordering information
pace1754/sos page 13 of 16 document # micro-9 rev b case outline 1: 68 lead quad pack with straight leads (ordering code ql) notes: 1) dimensions are in inches. 2) metric equivalents are given for general information only. 3) unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner . 5) corners indicated as notched may be either notched or square. inches m m .002 0.05 .003 0.08 .006 0.15 .010 0.25 .015 0.38 .018 0.45 .050 1.27 .060 1.52 .080 2.03 .095 2.41 .225 5.72 .570 14.48 .800 20.32 .955 24.25
pace1754/sos page 14 of 16 document # micro-9 rev b case outline 2: 68 lead quad pack with gullwing leads (ordering code qg) notes: 1) dimensions are in inches. 2) metric equivalents are given for general information only. 3) unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner . 5) corners indicated as notched my be either notched or square (with radius). 6) case 2 is derived from case 1 by forming the leads to the shown gullwing configuration. inches m m .003 0.08 .010 0.25 .015 0.38 .018 0.45 .020 0.51 .050 1.27 .570 14.48 .800 20.32 .955 24.25 1.230 31.26
pace1754/sos page 15 of 16 document # micro-9 rev b min max a 0.048 0.090 a1 0.011 0.031 b 0.016 0.021 c 0.004 0.008 e1 d 1.210 1.250 d1 0.945 0.965 d2 e 1.210 1.250 e1 0.945 0.965 e2 l* l0 0.120 0.210 l3 0.040 0.050 l4 0.086 0.109 r1 0.018 0.020 r2 0.018 0.020 4 8 -1 7 a0** 0.141 0.270 nominal symbol inches 0.050 bsc 0.800 bsc 0.800 bsc lead form detail 1 2 * lead length in the straight lead configuration, prior to leadforming (used for all test and in-process wip operations). ** measured from the highest of the top of the leads or the top of the lid.
pace1754/sos page 16 of 16 document # micro-9 rev b revisions document number : micro-9 document title : pace1754/sos mmu/combo rev. issue date orig. of change description of change orig may-89 rkk new data sheet a jul-04 jdb added pyramid logo b aug-05 jdb re-created electronic version

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