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features applications description adS5240 sbas326c ? june 2004 ? revised december 2004 4-channel, 12-bit, 40msps adc with serial lvds interface an integrated phase lock loop multiplies the incoming adc sampling clock by a factor of 12. this 12x clock maximum sample rate: 40msps is used in the process of serializing the data output 12-bit resolution from each channel. the 12x clock is also used to generate a 1x and a 6x clock, both of which are no missing codes transmitted as lvds clock outputs. the 6x clock is power dissipation: 607mw denoted by the differential pair lclk p and lclk n , cmos technology while the 1x clock is denoted by adclk p and simultaneous sample-and-hold adclk n . the word output of each adc channel can be transmitted either as msb or lsb first. the bit 70.5dbfs snr at 10mhz if coinciding with the rising edge of the 1x clock output internal and external references is the first bit of the word. data is to be latched by the 3.3v digital/analog supply receiver on both the rising and falling edges of the 6x clock. serialized lvds outputs integrated frame and bit patterns the adS5240 provides internal references, or can optionally be driven with external references. best msb and lsb first modes performance can be achieved through the internal option to double lvds clock output currents reference mode. pin- and format-compatible family the device is available in an htqfp-64 powerpad htqfp-64 powerpad? package package and is specified over a -40 c to +85 c operating range. portable ultrasound systems tape drives test equipment optical networking the adS5240 is a high-performance, 4-channel, 40msps analog-to-digital converter (adc). internal references are provided, simplifying system design requirements. low power consumption allows for the highest of system integration densities. serial lvds (low-voltage differential signaling) outputs reduce the number of interface lines and package size. related products resolution sample rate model (bits) (msps) channels ads5242 (1) 12 65 4 (1) available q1 2005. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. powerpad is a trademark of texas instruments. all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2004, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
1 2 ? b i t a d c p l l s / h s e r i a l i z e r 1 x a d c l k 6 x a d c l k i n 1 p a d c l k i n 1 n o u t 1 p o u t 1 n 1 2 ? b i t a d c s / h s e r i a l i z e r i n 2 p i n 2 n o u t 2 p o u t 2 n 1 2 ? b i t a d c s / h s e r i a l i z e r i n 3 p i n 3 n o u t 3 p o u t 3 n l c l k p l c l k n a d c l k p a d c l k n 1 2 ? b i t a d c s / h s e r i a l i z e r i n 4 p i n 4 n o u t 4 p o u t 4 n r e f e r e n c e r e f t i n t / e x t v c m r e f b r e g i s t e r s s c l k s d a t a c s c o n t r o l r e s e t p d
absolute maximum ratings (1) adS5240 sbas326c ? june 2004 ? revised december 2004 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) specified package temperature package ordering transport product package-lead designator range marking number media, quantity adS5240ipap tray, 160 adS5240 htqfp-64 (2) pap -40 c to +85 c adS5240i adS5240ipapt tape and reel, 1000 (1) for the most current package and ordering information, see the package option addendum located at the end of this data sheet. (2) thermal pad size: 5.29mm 5.29mm (min), 6.50mm 6.50mm (max). supply voltage range, avdd -0.3v to +3.8v supply voltage range, lvdd -0.3v to +3.8v voltage between avss and lvss -0.3v to +0.3v voltage between avdd and lvdd -0.3v to +0.3v voltage applied to external ref pins -0.3v to +2.4v all lvds data and clock outputs -0.3v to +2.4v analog input pins -0.15v to +3.0v peak total input current (all inputs) 30ma junction temperature +105 c operating free-air temperature range, t a -40 c to +85 c lead temperature, 1.6mm (1/16" from case for 10s) 220 c (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. 2 www .ti.com
recommended operating conditions adS5240 sbas326c ? june 2004 ? revised december 2004 adS5240 min typ max units supplies and references analog supply voltage, avdd 3.0 3.3 3.6 v output driver supply voltage, lvdd 3.0 3.3 3.6 v clock input and outputs adclk input sample rate (low-voltage ttl) 20 40 msps low-level voltage clock input 0.6 v high-level voltage clock input 2.2 v adclk p and adclk n outputs (lvds) 20 40 mhz lclk p and lclk n outputs (lvds) (1) 120 240 mhz operating free-air temperature, t a -40 +85 c thermal characteristics: q ja 24 c/w q jc 15 c/w (1) 6 adclk. reference selection mode int/ ext description internal reference 1 full-scale range = 2.0v pp . default with internal pull-up. 0 internal reference is powered down. common mode of external reference should be within external reference 50mv of v cm . v cm is derived from the internal bandgap voltage. 3 www .ti.com
electrical characteristics adS5240 sbas326c ? june 2004 ? revised december 2004 t min = -40 c and t max = +85 c. typical values are at t a = 25 c, clock frequency = 40msps, 50% clock duty cycle, avdd = 3.3v, lvdd = 3.3v differential, transformer coupled inputs, -1dbfs, i set = 56.2k w , internal voltage reference, and ldvs buffer current at 3.5ma per channel, unless otherwise noted. adS5240 parameter test conditions min typ max units dc accuracy no missing codes assured dnl differential nonlinearity f in = 5mhz -0.9 0.4 +0.9 lsb inl integral nonlinearity f in = 5mhz -2.0 0.75 +2.0 lsb offset error (1) -0.75 0.2 +0.75 %fs offset temperature coefficient 14 ppm/ c fixed attenuation in channel (2) 1 %fs variable attenuation in channel (3) 0.2 %fs gain error (4) ref t - ref b -5 1.0 +5 %fs attenuation temperature 44 ppm/ c coefficient (5) power supply i cc total supply current v in = fs, f in = 5mhz 184 ma i(avdd) analog supply current v in = fs, f in = 5mhz 142 ma v in = fs, f in = 5mhz, i(lvdd) digital output driver supply current 42 ma lvds into 100 w load power dissipation 607 650 mw power-down clock running 95 mw reference voltages vref t reference top (internal) 1.95 2.0 2.05 v vref b reference bottom (internal) 0.95 1.0 1.05 v v cm common-mode voltage 1.45 1.5 1.55 v v cm output current (6) 50mv change in voltage 2 ma vref t reference top (external) 1.875 v vref b reference bottom (external) 1.125 v external reference input current (7) 1.0 ma analog input differential input capacitance 4.0 pf analog input common-mode range v cm 0.05 v differential input voltage range 1.5 2.02 v pp differential input signal at 4v pp voltage overhead recovery time 4.0 clk cycles recovery to within 1% of code input bandwidth -3dbfs 300 mhz digital data outputs data bit rate 240 480 mbps (1) offset error is the deviation of the average code from mid-code for a zero input. offset error is expressed in terms of % of full-scale. (2) fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. when the differential voltage at the analog input pins are changed from -v ref to +v ref , the swing of the output code is expected to deviate from the full-scale code (4096lsb) by the extent of this fixed attenuation. note: v ref is defined as (ref t - ref b ). (3) variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation. (4) the reference voltages are trimmed at production so that (vref t - vref b ) is within 50mv of the ideal value of 1v. it does not include fixed attenuation. (5) the attenuation temperature coefficient refers to the temperature coefficient of the attenuation in the channel. it does not account for the variation of the reference voltages with temperature. (6) v cm provides the common-mode current for the inputs of all four channels when the inputs are ac-coupled. the v cm output current specified is the additional drive of the v cm buffer if loaded externally. (7) average current drawn from the reference pins in the external reference mode. 4 www .ti.com
ac characteristics adS5240 sbas326c ? june 2004 ? revised december 2004 t min = -40 c and t max = +85 c. typical values are at t a = 25 c, clock frequency = 40msps, 50% clock duty cycle, avdd = 3.3v, lvdd = 3.3v differential, transformer coupled inputs, -1dbfs, i set = 56.2k w , internal voltage reference, and lvds buffer current at 3.5ma per channel, unless otherwise noted. adS5240 parameter conditions min typ max units dynamic characteristics f in = 1mhz 87 dbc sfdr spurious-free dynamic range f in = 5mhz 78 85 dbc f in = 10mhz 85 dbc f in = 1mhz 95 dbc hd 2 2nd-order harmonic distortion f in = 5mhz 85 95 dbc f in = 10mhz 90 dbc f in = 1mhz 87 dbc hd 3 3rd-order harmonic distortion f in = 5mhz 78 85 dbc f in = 10mhz 85 dbc f in = 1mhz 70.5 dbfs snr signal-to-noise ratio f in = 5mhz 68 70.5 dbfs f in = 10mhz 70 dbfs f in = 1mhz 70 dbfs sinad signal-to-noise and distortion f in = 5mhz 67 70 dbfs f in = 10mhz 69.5 dbfs f 1 = 9.5mhz at -7dbfs dbc imd two-tone intermodulation distortion -88 f 2 = 10.2mhz at -7dbfs enob effective number of bits f in = 5mhz 11.3 bits signal applied to 3 channels; measurement taken -90 dbc crosstalk on the channel with no input signal 5 www .ti.com
lvds digital data and clock outputs switching characteristics adS5240 sbas326c ? june 2004 ? revised december 2004 test conditions at i o = 3.5ma, r load = 100 w , and c load = 6pf. i o refers to the current setting for the lvds buffer. r load is the differential load resistance between the lvds pair. c load is the effective single-ended load capacitance between each of the lvds pins and ground. c load includes the receiver input parasitics as well as the routing parasitics. measurements are done with a transmission line of 100 w characteristic impedance between the device and the load. all lvds specifications are characterized, but not tested at production. parameter conditions min typ max units dc specifications (1) output voltage high, out p or out n r load = 100 w 1% 1375 1500 mv v oh see lvds timing diagram, page 7 v ol output voltage low, out p or out n r load = 100 w 1% 900 1025 mv |v od | output differential voltage, |out p - out n | r load = 100 w 1% 300 350 400 mv v os output offset voltage (2) r load = 100 w 1% 1100 1200 1300 mv see lvds timing diagram, page 7 c o output capacitance (3) v cm = 1.5v 4 pf | d v od | change in |v od | between 0 and 1 r load = 100 w 1% 25 mv d v os change between 0 and 1 r load = 100 w 1% 25 mv isout output short-circuit current drivers shorted to ground 40 ma isout np output current drivers shorted together 12 ma driver ac specifications clock lvds clock duty cycle 6 adclk (lclk p , lclk n ) 45 50 55 % minimum data setup time (4) (5) 650 ps minimum data hold time (4) (5) 650 ps t rise /t fall v od rise time or v od fall time i o = 2.5ma 400 ps i o = 3.5ma 250 ps i o = 4.5ma 200 ps i o = 6ma 150 ps (1) the dc specifications refer to the condition where the lvds outputs are not switching, but are permanently at a valid logic level 0 or 1. (2) v os refers to the common-mode of out p and out n . (3) output capacitance inside the device, from either out p or out n to ground. (4) refer to the lvds application note (sbaa118 ) for a description of data setup and hold times. (5) setup and hold time specifications take into account the effect of jitter on the output data and clock. these specifications also assume that the data and clock paths are perfectly matched within the receiver. any mismatch in these paths within the receiver would appear as reduced timing margins. t min = -40 c and t max = +85 c. typical values are at t a = 25 c, clock frequency = 40msps, 50% clock duty cycle, avdd = 3.3v, lvdd = 3.3v, -1dbfs, i set = 56.2k w , internal voltage reference, and lvds buffer current at 3.5ma per channel, unless otherwise noted. adS5240 parameter conditions min typ max units switching specifications t sample 25 50 ns t d (a) aperture delay 3.1 ns aperture jitter (uncertainty) 1 ps rms t d (pipeline) latency 6.5 cycles t prop propagation delay 5 ns 6 www .ti.com
adS5240 sbas326c ? june 2004 ? revised december 2004 lvds timing diagram (per adc channel) reset timing power-down timing 7 www .ti.com a d c l k 6 x a d c l k s e r i a l d a t a 1 x a d c l k l c l k p l c l k n o u t p o u t n a d c l k p a d c l k n s a m p l e n d a t a i n p u t t p r o p t d ( a ) s a m p l e n s a m p l e n + 6 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 0 d 1 d 2 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 1 d 1 0 t s a m p l e t s 2 t s a m p l e 1 2 d 1 1 d 1 0 d 1 d 0 6 . 5 c l o c k c y c l e s ; t s = 0 v + a v d d 0 v + a v d d p o w e r s u p p l y r e s e t t 1 t 2 t 3 r e g i s t e r w r i t e e n a b l e t 1 > 1 0 m s t 2 > 1 0 0 n s t 3 > 1 0 0 n s p d d e v i c e f u l l y p o w e r s d o w n d e v i c e f u l l y p o w e r s u p 1 0 m s 1 m s
serial interface serial interface timing adS5240 sbas326c ? june 2004 ? revised december 2004 t min = -40 c and t max = +85 c. typical values are at t a = 25 c, clock frequency = maximum specified, 50% clock duty cycle, avdd = 3.3v, lvdd = 3.3v, -1dbfs, i set = 56.2k w , internal voltage reference, and lvds buffer current at 3.5ma per channel, unless otherwise noted. adS5240 parameter test conditions min typ max units sclk serial clock input frequency 20 mhz v in low input low voltage 0 0.6 v v in high input high voltage 2.2 avdd v input current 10 a input pin capacitance 5.0 pf data is shifted in msb first. parameter description min typ max unit t 1 serial clk period 50 ns t 2 serial clk high time 25 ns t 3 serial clk low time 25 ns t 4 minimum data setup time 5 ns t 5 minimum data hold time 5 ns 8 www .ti.com s t a r t s e q u e n c e t 1 m s b d 6 d 5 d 4 d 3 d 2 d 1 d 0 t 2 t 3 t 4 t 5 a d c l k c s s c l k s d a t a o u t p u t s c h a n g e o n n e x t r i s i n g c l o c k e d g e a f t e r c s g o e s h i g h . d a t a l a t c h e d o n e a c h r i s i n g e d g e o f s c l k .
test patterns (1) adS5240 sbas326c ? june 2004 ? revised december 2004 serial interface registers address data description remarks d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 lvds buffers (register 0) 0 0 normal adc output (default after reset) 0 1 deskew pattern patterns get reversed in msb 1 0 sync pattern first mode of lvds 1 1 custom pattern 0 0 output current in lvds = 3.5ma (default after reset) 0 1 output current in lvds = 2.5ma 1 0 output current in lvds = 4.5ma 1 1 output current in lvds = 6.0ma 0 0 0 1 lsb/msb mode (register 1) 0 x x 0 default lvds clock output current i out = 3.5ma 0 x x 1 2x lvds clock output current i out = 7.0ma 0 0 x x lsb first mode (default after reset) 0 1 x x msb first mode 0 0 1 0 power-down adc channels (register 2) 0 1 0 x d2: power-down for channel 2 logic 1 = channel powered down 0 x 0 1 d0: power-down for channel 1 0 0 1 1 power-down adc channels (register 3) 1 0 x 0 d3: power-down for channel 4 logic 1 = channel powered down x 0 1 0 d1: power-down for channel 3 custom pattern (registers 4-6) d3 d2 d1 d0 bits for custom pattern see test patterns 0 1 0 0 x x x x 0 1 0 1 x x x x 0 1 1 0 x x x x deskew 101010101010 sync 000000111111 custom any 12-bit pattern that is defined in the custom pattern registers 4 to 6. the output comes out in the following order: d0(4) d1(4) d2(4) d3(4) d0(5) d1(5) d2(5) d3(5) d0(6) d1(6) d2(6) d3(6) where, for example, d0(4) refers to the d0 bit of register 4, etc. (1) default is lsb first. if msb first is selected, the above patterns will be reversed. 9 www .ti.com
pin configuration adS5240 sbas326c ? june 2004 ? revised december 2004 10 www .ti.com t op v iew htqfp 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 a v d d i n 4 n i n 4 p a v s s a v d d a v s s i n 3 n i n 3 p a v s s a v d d l v s s r e s e t l v s s l v s s a d c l k n a d c l k p a v s s s c l k s d a t a c s a v d d a v s s a v s s a v s s a d c l k a v d d i n t / e x t r e f t r e f b v c m i s e t a v s s n c n c o u t 1 p o u t 1 n l v d d l v s s o u t 2 p o u t 2 n o u t 3 p o u t 3 n l v d d l v s s o u t 4 p o u t 4 n n c n c 12 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 a v d d i n 1 p i n 1 n a v s s a v d d a v s s i n 2 p i n 2 n a v s s a v d d l v s s p d l v s s l v s s l c l k p l c l k n 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 5 3 2 8 2 9 3 0 3 1 3 2 5 2 5 1 5 0 4 9 a d s 5 2 4 0
adS5240 sbas326c ? june 2004 ? revised december 2004 pin descriptions name pin # i/o description avdd 1, 5, 10, 39, 44, 48, 55, 60 i analog power supply in1 p 2 i channel 1 differential analog input high in1 n 3 i channel 1 differential analog input low avss 4, 6, 9, 40, 43, 45, 49, 57-59, 64 i analog ground in2 p 7 i channel 2 differential analog input high in2 n 8 i channel 2 differential analog input low lvss 11, 13, 14, 22, 28, 35, 36, 38 i lvds ground pd 12 i power-down; 0 = normal, 1 = power-down lclk p 15 o positive lvds clock lclk n 16 o negative lvds clock nc 17, 18, 31, 32 ? no connection out1 p 19 o channel 1 positive lvds data output out1 n 20 o channel 1 negative lvds data output lvdd 21, 27 i lvds power supply out2 p 23 o channel 2 positive lvds data output out2 n 24 o channel 2 negative lvds data output out3 p 25 o channel 3 positive lvds data output out3 n 26 o channel 3 negative lvds data output out4 p 29 o channel 4 positive lvds data output out4 n 30 o channel 4 negative lvds data output adclk p 33 o positive lvds adc clock output adclk n 34 o negative lvds adc clock output reset 37 i reset registers to default; 0 = reset, 1 = normal in3 p 41 i channel 3 differential analog input high in3 n 42 i channel 3 differential analog input low in4 p 46 i channel 4 differential analog input high in4 n 47 i channel 4 differential analog input low i set 50 i/o bias current setting resistor of 56.2k w to ground v cm 51 o common-mode output voltage ref b 52 i/o reference bottom voltage (2 w resistor in series with 0.1f capacitor to ground) ref t 53 i/o reference top voltage (2 w resistor in series with 0.1f capacitor to ground) int/ ext 54 i internal/external reference select; 0 = external, 1 = internal adclk 56 i data converter clock input cs 61 i chip-select; 0 = select, 1 = no select sdata 62 i serial data input sclk 63 i serial data clock 11 www .ti.com
definition of specifications adS5240 sbas326c ? june 2004 ? revised december 2004 integral nonlinearity (inl) analog bandwidth inl is the deviation of the transfer function from a the analog input frequency at which the spectral reference line measured in fractions of 1 lsb using a power of the fundamental frequency (as determined best straight line or best fit determined by a least by fft analysis) is reduced by 3db. square curve fit. inl is independent from effects of offset, gain or quantization errors. aperture delay maximum conversion rate the delay in time between one of the edges of the input sampling clock and the actual time at which the the encode rate at which parametric testing is sampling occurs. performed. this is the maximum sampling rate where certified operation is given. aperture uncertainty (jitter) minimum conversion rate the sample-to-sample variation in aperture delay. this is the minimum sampling rate where the adc clock pulse width/duty cycle still works. pulse width high is the minimum amount of time that nyquist sampling the encode pulse should be left in logic '1' state to achieve rated performance. pulse width low is the when the sampled frequencies of the analog input minimum time that the encode pulse should be left signal are below f clock/2 , it is called nyquist sam- in a low state (logic '0'). at a given clock rate, these pling. the nyquist frequency is f clock/2 , which can specifications define an acceptable clock duty cycle. vary depending on the sample rate (f clock ). differential nonlinearity (dnl) offset error an ideal adc exhibits code transitions that are offset error is the deviation of output code from exactly 1 lsb apart. dnl is the deviation of any mid-code when both inputs are tied to com- single lsb transition at the digital output from an mon-mode. ideal 1 lsb step at the analog input. if a device claims to have no missing codes, it means that all propagation delay possible codes (for a 12-bit converter, 4096 codes) this is the delay between the input clock of one of are present over the full operating range. the edges and the time when all data bits are within effective number of bits (enob) valid logic levels. the effective number of bits for a sine wave input at a signal-to-noise and distortion (sinad) given input frequency can be calculated directly from the rms value of the sine wave f in (input sine wave its measured sinad using the following formula: for an adc) to the rms value of the noise of the converter from dc to the nyquist frequency, including harmonic content. it is typically expressed in decibels (db). sinad includes harmonics, but excludes dc. if sinad is not known, snr can be used exception- ally to calculate enob (enob snr ). 12 www .ti.com e n o b s i n a d 1 . 7 6 6 . 0 2 s i n a d 2 0 l o g ( 1 0 ) i n p u t ( v s ) n o i s e h a r m o n i c s
adS5240 sbas326c ? june 2004 ? revised december 2004 signal-to-noise ratio (without harmonics) temperature drift snr is a measure of signal strength relative to temperature drift (for offset error and gain error) background noise. the ratio is usually measured in specifies the maximum change from the initial tem- db. if the incoming signal strength in v is v s and the perature value to the value at t min or t max . noise level (also in v) is v n , then the snr in db is total harmonic distortion (thd) given by the formula: thd is the ratio of the rms signal amplitude of the input sine wave to the rms value of distortion appearing at multiples (harmonics) of the input, typi- cally given in dbc. this is the ratio of the rms signal amplitude, v s (set 1db below full-scale), to the rms value of the sum of two-tone intermodulation distortion rejection all other spectral components, v n , excluding harmon- the ratio of the rms value of either input tone (f 1 , f 2 ) ics and dc. to the rms value of the worst third-order spurious-free dynamic range (sfdr) intermodulation product (2f 1 - f 2 ; 2f 2 - f 1 ). it is reported in dbc. the ratio of the rms value of the analog input sine wave to the rms value of the peak spur observed in the frequency domain. it may be reported in dbc (that is, it degrades as signal levels are lowered), or in dbfs (always related back to converter full-scale). the peak spurious component may or may not be a harmonic. 13 www .ti.com s n r 2 0 l o g ( 1 0 ) v s v n
typical characteristics adS5240 sbas326c ? june 2004 ? revised december 2004 t min = -40 c and t max = +85 c. typical values are at t a = 25 c, clock frequency = maximum specified, 50% clock duty cycle, avdd = 3.3v, lvdd = 3.3v, -1dbfs, i set = 56.2k w , internal voltage reference, and lvds buffer current at 3.5ma per channel, unless otherwise noted. spectral performance spectral performance figure 1. figure 2. spectral performance two-tone intermodulation figure 3. figure 4. differential nonlinearity error integral nonlinearity error figure 5. figure 6. 14 www .ti.com a m p l i t u d e ( d b ) i n p u t f r e q u e n c y ( m h z ) 0 - 2 0 - 4 0 - 6 0 - 8 0 - 1 0 0 - 1 2 0 0 1 2 1 6 4 8 2 0 f i n = 1 m h z ( - 1 d b f s ) s n r = 7 0 . 9 d b f s s i n a d = 7 0 . 8 d b f s s f d r = 8 7 . 1 d b f s a m p l i t u d e ( d b ) i n p u t f r e q u e n c y ( m h z ) 0 - 2 0 - 4 0 - 6 0 - 8 0 - 1 0 0 - 1 2 0 0 1 2 1 6 4 8 2 0 f i n = 5 m h z ( - 1 d b f s ) s n r = 7 0 . 5 d b f s s i n a d = 7 0 . 3 d b f s s f d r = 8 4 . 9 d b f s a m p l i t u d e ( d b ) i n p u t f r e q u e n c y ( m h z ) 0 - 2 0 - 4 0 - 6 0 - 8 0 - 1 0 0 - 1 2 0 0 1 2 1 6 4 8 2 0 f i n = 1 0 m h z ( - 1 d b f s ) s n r = 7 0 . 3 d b f s s i n a d = 7 0 . 2 d b f s s f d r = 8 5 . 4 d b f s a m p l i t u d e ( d b ) i n p u t f r e q u e n c y ( m h z ) 0 - 2 0 - 4 0 - 6 0 - 8 0 - 1 0 0 - 1 2 0 0 1 2 1 6 4 8 2 0 f 1 = 9 . 5 m h z ( - 7 d b f s ) f 1 = 1 0 . 2 m h z ( - 7 d b f s ) i m d = - 8 8 . 2 d b c d n l e r r o r ( l s b ) c o d e 1 . 0 0 . 8 0 . 6 0 . 4 0 . 20 - 0 . 2 - 0 . 4 - 0 . 6 - 0 . 8 - 1 . 0 0 1 5 3 6 2 0 4 8 2 5 6 0 3 0 7 2 3 5 8 4 5 1 2 1 0 2 4 4 0 9 6 f i n = 5 m h z i n l e r r o r ( l s b s ) c o d e 2 . 0 1 . 5 1 . 0 0 . 50 - 0 . 5 - 1 . 0 - 1 . 5 - 2 . 0 0 1 5 3 6 2 0 4 8 2 5 6 0 3 0 7 2 3 5 8 4 5 1 2 1 0 2 4 4 0 9 6 f i n = 5 m h z
adS5240 sbas326c ? june 2004 ? revised december 2004 typical characteristics (continued) t min = -40 c and t max = +85 c. typical values are at t a = 25 c, clock frequency = maximum specified, 50% clock duty cycle, avdd = 3.3v, lvdd = 3.3v, -1dbfs, i set = 56.2k w , internal voltage reference, and lvds buffer current at 3.5ma per channel, unless otherwise noted. swept input power swept input power figure 7. figure 8. iavdd, idvdd vs sample rate dynamic performance vs sample rate figure 9. figure 10. dynamic performance vs sample rate power dissipation vs temperature figure 11. figure 12. 15 www .ti.com s n r ( d b c , d b f s ) i n p u t a m p l i t u d e ( a ) 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 00 - 7 0 - 6 0 - 3 0 - 2 0 - 1 0 - 5 0 - 4 0 0 f i n = 5 m h z s n r ( d b f s ) s n r ( d b c ) s f d r ( d b c ) s n r ( d b c , d b f s ) i n p u t a m p l i t u d e ( a ) 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 00 - 7 0 - 6 0 - 3 0 - 2 0 - 1 0 - 5 0 - 4 0 0 f i n = 1 0 m h z s n r ( d b f s ) s n r ( d b c ) s f d r ( d b c ) i a v d d , i d v d d ( a ) s a m p l e r a t e ( m s p s ) 0 . 3 0 0 . 2 5 0 . 2 0 0 . 1 5 0 . 1 0 0 . 0 50 2 0 3 5 4 0 2 5 3 0 4 5 i a v d d i d v d d f i n = 5 m h z s f d r , s n r , s i n a d ( d b f s ) s a m p l e r a t e ( m s p s ) 9 0 8 5 8 0 7 5 7 0 6 5 6 0 5 5 2 0 3 5 4 0 2 5 3 0 4 5 s f d r s i n a d s n r f i n = 5 m h z p o w e r ( m w ) t e m p e r a t u r e ( c ) 6 2 0 6 1 8 6 1 6 6 1 4 6 1 2 6 1 0 6 0 8 6 0 6 6 0 4 6 0 2 6 0 0 - 4 0 2 0 4 0 - 2 0 0 6 0 8 0 s f d r , s n r , s i n a d ( d b f s ) s a m p l e r a t e ( m s p s ) 9 0 8 5 8 0 7 5 7 0 6 5 6 0 5 5 2 0 3 5 4 0 2 5 3 0 4 5 s f d r s i n a d s n r f i n = 1 0 m h z
adS5240 sbas326c ? june 2004 ? revised december 2004 typical characteristics (continued) t min = -40 c and t max = +85 c. typical values are at t a = 25 c, clock frequency = maximum specified, 50% clock duty cycle, avdd = 3.3v, lvdd = 3.3v, -1dbfs, i set = 56.2k w , internal voltage reference, and lvds buffer current at 3.5ma per channel, unless otherwise noted. output noise histogram figure 13. 16 www .ti.com c o u n t s c o d e 1 2 0 k 1 0 0 k 8 0 k 6 0 k 4 0 k 2 0 k 0 k n - 1 n - 2 n n + 1 n + 2
theory of operation overview driving the analog inputs adS5240 sbas326c ? june 2004 ? revised december 2004 the adS5240 is a 4-channel, high-speed, cmos the analog input biasing is shown in figure 14 . the adc. it consists of a high-performance recommended method to drive the inputs is through sample-and-hold circuit at the input, followed by a ac coupling. ac coupling removes the worry of 12-bit adc. the 12 bits given out by each channel setting the common-mode of the driving circuit, since are serialized and sent out on a single pair of pins in the inputs are biased internally using two 600 w lvds format. all four channels of the adS5240 resistors. operate from a single clock referred to as adclk. the sampling clocks for each of the four channels are generated from the input clock using a carefully matched clock buffer tree. the 12x clock required for the serializer is generated internally from adclk using a phase lock loop (pll). a 6x and a 1x clock are also output in lvds format along with the data to enable easy data capture. the adS5240 operates from internally-generated reference voltages that are trimmed to improve matching across multiple devices on a board. this feature eliminates the need for external routing of reference lines and also improves matching of the gain across devices. the nominal values of ref t and ref b are 2v and 1v, respect- ively. these values imply that a differential input of -1v corresponds to the zero code of the adc, and a differential input of +1v corresponds to the full-scale figure 14. analog input bias circuitry code (4095 lsb). v cm (common-mode voltage of ref t and ref b ) is also made available externally through a pin, and is nominally 1.5v. the sampling capacitor used to sample the inputs is 4pf. the choice of the external ac coupling capacitor the adc employs a pipelined converter architecture is dictated by the attenuation at the lowest desired consisting of a combination of multi-bit and single-bit input frequency of operation. the attenuation re- internal stages. each stage feeds its data into the sulting from using a 10nf ac coupling capacitor is digital error correction logic, ensuring excellent differ- 0.04%. ential linearity and no missing codes at the 12-bit level. the pipeline architecture results in a data if the input is dc-coupled, then the output com- latency of 6.5 clock cycles. mon-mode voltage of the circuit driving the adS5240 should match the v cm (which is provided as an output the output of the adc goes to a serializer that pin) to within 50mv. it is recommended that the operates from a 12x clock generated by the pll. the output common-mode of the driving circuit be derived 12 data bits from each channel are serialized and from v cm provided by the device. sent lsb first. in addition to serializing the data, the serializer also generates a 1x clock and a 6x clock. the sampling circuit consists of a low-pass rc filter these clocks are generated in the same way the at the input to filter out noise components that might serialized data is generated, so these clocks maintain be differentially coupled on the input pins. the inputs perfect synchronization with the data. the data and are sampled on two 4pf capacitors, see figure 15 . clock outputs of the serializer are buffered externally the sampling on the capacitors is done with respect using lvds buffers. using lvds buffers to transmit to an internally-generated common-mode voltage data externally has multiple advantages, such as (incm). the switches connecting the sampling ca- reduced number of output pins (saving routing space pacitors to the incm are opened out first (before the on the board), reduced power consumption, and switches connecting them to the analog inputs). this reduced effects of digital noise coupling to the analog ensures that the charge injection arising out of the circuit inside the adS5240. switches opening is independent of the input signal amplitude to a first-order of approximation. sp refers the adS5240 operates from two sets of supplies and to a sampling clock whose falling edge comes an grounds. the analog supply/ground set is denoted as instant before the sample clock. the falling edge of avdd/avss, while the digital set is denoted by sp determines the sampling instant. lvdd/lvss. 17 www .ti.com c m b u f f e r i n t e r n a l v o l t a g e r e f e r e n c e i n p u t c i r c u i t r y i n + i n - v c m 6 0 0 w 6 0 0 w a d s 5 2 4 0
input over-voltage recovery reference circuit design clocking adS5240 sbas326c ? june 2004 ? revised december 2004 thereby scales down the device operating power. however, it is recommended that the external resistor be within 10% of the specified value of 56.2k w so that the internal bias margins for the various blocks are proper. buffering the internal bandgap voltage also generates a voltage called v cm , which is set to the midlevel of ref t and ref b , and is accessible on a pin. the internal buffer driving v cm has a drive of 2ma. it is meant as a reference voltage to derive the input common-mode in case the input is directly coupled. when using the internal reference mode, a resistor of 2 w should be added between the reference pins (ref t and ref b ) and the decoupling capacitor, as shown in figure 16 . figure 15. input circuitry the differential full-scale input peak-to-peak sup- ported by the adS5240 is 2v. for a nominal value of v cm (1.5v), in p and in n can swing from 1v to 2v. the adS5240 is specially designed to handle an over-voltage differential peak-to-peak voltage of 4v (2.5v and 0.5v swings on in p and in n ). if the input common-mode is not considerably off from v cm during overload (less than 300mv), recovery from an over-voltage input condition is expected to be within 4 figure 16. internal reference mode clock cycles. all of the amplifiers in the sha and adc are specially designed for excellent recovery from an the device also supports the use of external refer- overload signal. ence voltages. this mode involves forcing ref t and ref b externally. in this mode, the internal reference buffer is tri-stated. since the switching current for the four adcs come from the externally-forced refer- the digital beam-forming algorithm relies on gain ences, it is possible for the performance to be slightly matching across all receiver channels. (a typical less than when the internal references are used. it system would have about 128 adcs on the board.) in should be noted that in this mode, v cm and iset such a case, it is critical to ensure that the gain is continue to be generated from the internal bandgap matched, essentially requiring the reference voltages voltage, as in the internal reference mode. it is seen by all the adcs to be the same. matching therefore important to ensure that the common-mode references within the four channels of a chip is done voltage of the externally-forced reference voltages by using a single internal reference voltage buffer. matches to within 50mv of v cm . trimming the reference voltages on each chip during production ensures the reference voltages are well-matched across different chips. the four channels on the chip run off a single adclk all bias currents required for the internal operation of input. to ensure that the aperture delay and jitter are the device are set using an external resistor to same for all the channels, a clock tree network is ground at pin i set . using a 56.2k w resistor on i set used to generate individual sampling clocks to each generates an internal reference current of 20a. this channel. the clock paths for all the channels are current is mirrored internally to generate the bias matched from the source point all the way to the current for the internal blocks. using a larger external sample-and-hold. this ensures that the performance resistor at i set reduces the reference bias current and and timing for all the channels are identical. the use 18 www .ti.com 1 5 w i n - 1 . 5 p f s p s p s p ( d e f i n e s s a m p l i n g i n s t a n t ) i n c m ( i n t e r n a l l y ? g e n e r a t e d v o l t a g e ) i n c m 4 p f s a m p l e 1 5 w i n + 1 . 5 p f 1 . 7 p f 4 p f s a m p l e r e f t v c m r e f b i s e t 0 . 1 m f 2 . 2 m f 2 w 2 w 2 . 2 m f 0 . 1 m f 5 6 . 2 k w a d s 5 2 4 0 + +
lvds buffers noise coupling issues adS5240 sbas326c ? june 2004 ? revised december 2004 of the clock tree for matching introduces an aperture the lvds buffer gets data from a serializer that delay, which is defined as the delay between the takes the output data from each channel and rising edge of adclk and the actual instant of serializes it into a single data stream. for a clock sampling. the aperture delays for all the channels frequency of 40mhz, the data rate output by the are matched. the aperture delays for all channels are serializer is 480mbps. the data comes out lsb first, matched. however, across conditions of temperature, with a register programmability to revert to msb first. supply voltage, and devices, the aperture delay the serializer also gives out a 1x clock and a 6x averages 3.1ns. clock. the 6x clock (denoted as lclk p /lclk n ) is meant to synchronize the capture of the lvds data. the input adclk should ideally have a 50% duty the deskew mode can be enabled as well, using a cycle. however, while routing adclk to different register setting. this mode gives out a data stream of components on board, the duty cycle of the adclk alternate 0s and 1s and can be used determine the reaching the adS5240 could deviate from 50%. a relative delay between the 6x clock and the output smaller (or larger) duty cycle eats into the time data for optimum capture. a 1x clock is also gener- available for sample or hold phases of each circuit, ated by the serializer and transmitted by the lvds and is therefore not optimal. for this reason, the buffer. the 1x clock (referred to as adclk p /adclk n ) internal pll is used to generate an internal clock that is used to determine the start of the 12-bit data has 50% duty cycle. frame. the sync mode (enabled through a register setting) gives out a data of six 0s followed by six 1s. the use of the pll automatically dictates the mini- using this mode, the 1x clock can be used to mum sampling rate to be about 20msps. determine the start of the data frame. in addition to the deskew mode pattern and the sync pattern, a custom pattern can be defined by the user and output the lvds buffer has two current sources, as shown from the lvds buffer. in figure 17 . out p and out n are loaded externally by a resistive load that is ideally about 100 w . depending on the data being 0 or 1, the currents are high-speed mixed signals are sensitive to various directed in one or the other direction through the types of noise coupling. one of the main sources of resistor. while the lower side current source is a noise is the switching noise from the serializer and constant current source, the higher side current the output buffers. maximum care is taken to isolate source is controlled through a feedback loop to these noise sources from the sensitive analog blocks. maintain the output common mode constant. the as a starting point, the analog and digital domains of lvds buffer has four current settings. the default the chip are clearly demarcated. avdd and avss current setting is 3.5ma, and gives a differential drop are used to denote the supplies for the analog of about 350mv across the 100 w resistor. sections, while lvdd and lvss are used to denote the digital supplies. care is taken to ensure that there is minimal interaction between the supply sets within the device. the extent of noise coupled and transmitted from the digital to the analog sections depends on the following: 1. the effective inductances of each of the supply/ground sets. 2. the isolation between the digital and analog supply/ground sets. smaller effective inductance of the supply/ground pins leads to better suppression of the noise. for this reason, multiple pins are used to drive each supply/ground. it is also critical to ensure that the impedances of the supply and ground lines on board are kept to the minimum possible values. use of ground planes in the board as well as large decoup- ling capacitors between the supply and ground lines are necessary to get the best possible snr from the device. figure 17. lvds buffer 19 www .ti.com e x t e r n a l t e r m i n a t i o n r e s i s t o r o u t p h i g h l o w o u t n l o w h i g h
power-down mode layout of pcb with powerpad connecting high-speed, supply sequence adS5240 sbas326c ? june 2004 ? revised december 2004 it is recommended that the isolation be maintained if this sequencing is not possible, then it is rec- onboard by using separate supplies to drive avdd ommended that avdd and lvdd be powered up and lvdd, as well as separate ground planes for simultaneously. avss and lvss. after the supplies have stabilized, it is required to the use of lvds buffers reduces the injected noise give the device an active reset pulse. this results considerably, compared to cmos buffers. the cur- in all internal registers getting reset to their default rent in the lvds buffer is independent of the direction value of 0 (inactive). without reset, it is possible of switching. also, the low output swing as well as the that some registers might be in their non-default state differential nature of the lvds buffer results in on power-up. this could cause the device to low-noise coupling. malfunction. thermally-enhanced packages the adS5240 has a power-down pin, pd. pulling pd high causes the device to enter the power-down the adS5240 is housed in an 64-lead powerpad mode. in this mode, the reference and clock circuitry thermally-enhanced package. to make optimum use as well as all the channels are powered down. device of the thermal efficiencies designed into the power consumption drops to less than 100mw in this powerpad package, the printed circuit board (pcb) mode. individual channels can also be selectively must be designed with this technology in mind. powered down by programming registers. please refer to powerpad brief slma004 powerpad made easy (refer to our web site at www.ti.com), the adS5240 also has an internal circuit that moni- which addresses the specific considerations required tors the state of stopped clocks. if adclk is stopped when integrating a powerpad package into a pcb (or if it runs at a speed < 3mhz), this monitoring design. for more detailed information, including ther- circuit generates a logic signal that puts the device in mal modeling and repair procedures, please see a power-down state. as a result, the power consump- technical brief slma002, powerpad ther- tion of the device is reduced when adclk is mally-enhanced package (available for download at stopped. this circuit can also be disabled using www.ti.com). register options. multi-channel adcs to xilinx fpgas the following supply sequence is recommended for a separate application note (xapp774) describing powering up the device: how to connect ti's high-speed, multi-channel adcs 1. avdd is powered up. with serial lvds outputs to xilinx fpgas can be downloaded directly from the xilinx website 2. lvdd is powered up. (http://www.xilinx.com). during the power-up ramp, the avdd and lvdd supplies should track each other to within 0.6v. 20 www .ti.com
www.ti.com powerpad is a trademark of texas instruments pap (s-pqfp-g64) thermal information thermal pad me chanical data 32 17 49 64 48 33 116 this powerpad? package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. when the thermal pad is soldered direct ly to the printed circuit board (pcb), the pcb can be used as a heatsink. in addition, through the use of therma l vias, the thermal pad can be attached directly to a ground plane or special heatsink structur e designed into the pcb. this design optimizes the heat transfer from the integrated circuit (ic). the exposed thermal pad dimensions for this package are shown in the following illustration. for additional information on the powerpad package and how to take advantage of its heat dissipating abilities, refer to technical brief, powerpad thermally enhanced package , texas instruments literature no. slma002 and application brief, powerpad made easy , texas instruments literature no. slma004. both documents are available at www.ti.com. exposed thermal pad dimensions note: all linear dimensions are in millimeters top view pptd012 exposed thermal pad 6,50 5,29 6,50 5,29
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) adS5240ipap active htqfp pap 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr adS5240ipapg4 active htqfp pap 64 160 tbd call ti call ti adS5240ipapt active htqfp pap 64 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr adS5240ipaptg4 active htqfp pap 64 250 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 12-may-2005 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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