View K7D161871M-HC30_6610158.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev 2.0 512kx36 & 1mx18 sram - 1 - jan. 2002 k7d161871m k7d163671m document title 16m ddr synchronous sram revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any questions, please contact the samsung branch office near your office, call or cortact headquart ers. rev no. rev. 0.0 rev. 0.1 rev. 0.2 rev. 0.3 rev. 0.5 rev. 0.6 rev. 0.7 rev. 1.0 rev. 2.0 remark advance advance advance advance preliminary preliminary preliminary final final history initial document. addition of new speed bin -25 new part number from km736fs16017 to k7d163671m package height changed. leakage current test condition changed from v dd to v ddq package height changed.(from 2.4 to 2.5) zq tolerance changed from 10% to 15% deleted -hc25 part(part number, idd, ac characterisctics) add-hc37 part(part number, idd, ac characteristics) clarification on the features and the timing waveforms regarding the burst controllability. package thermal characteristics add i dd37 x36 changed from 800ma to 850ma i dd37 x18 changed from 750ma to 800ma add-hc40 part(part number, idd, ac characteristics) final specification release. absolute maximum rating vddq changed from 3.13v to 2.3v draft data march. 1999 april. 2000 may. 2000 aug. 2000 jan. 2001 april. 2001 may. 2001 sep. 2001 jan. 2002
rev 2.0 512kx36 & 1mx18 sram - 2 - jan. 2002 k7d161871m k7d163671m features ? 512kx36 or 1mx18 organizations. ? maximum frequency : 400mhz (data rate : 800mbps) ? 2.5v v dd /1.5v v ddq (1.9v max v ddq ). ? hstl input and outputs. ? single differential hstl clock. ? synchronous pipeline mode of operation with self-timed late write. ? free running active high and active low echo clock output pin. ? asynchronous output enable. ? registered addresses, burst control and data inputs. ? registered outputs. ? single and double data rate burst read and write. ? burst count controllable with max burst length of 4 ? interleved and linear burst mode support ? bypass operation support ? programmable impedance output drivers. note : *access time equals t kxch/ t kxcl organization part number maximum frequency access time 512kx36 k7d163671m-hc40 400mhz 1.6* k7d163671m-hc37 370mhz 1.7* k7d163671m-hc33 333mhz 1.7* k7d163671m-hc30 300mhz 1.9* 1mx18 k7d161871m-hc40 400mhz 1.6* k7d161871m-hc37 370mhz 1.7* k7d161871m-hc33 333mhz 1.7* K7D161871M-HC30 300mhz 1.9* functional block diagram k, k b 1 b 3 b 2 g register ce memory array 512kx36 data out data in advance control sd/ dd co clock synchronous buffer internal clock generator ce r/ w ld data output strobe data output enable state machine strobe_out s/a array 2 : 1 mux data in register write buffer w/d array echo clock output 36(or 18)x2 36(or 18)x2 36(or18)x2 36(or18)x2 xdin cq, cq dq 36(or 18) select & r/ w control output buffer write ce burst counter register address address comparator 2:1 mux dec. 19(or 20) 17(or 18) 17(or 18) 19(or 20) (burst write sa[0:18]( or sa[0:19]) or (1mx18) (2 stage) (2 stage) (burst address) address) ? jtag boundary scan (subset of ieee std. 1149.1) ? 153(9x17) flip chip ball grid array package(14mmx22mm) pin description pin name pin description pin name pin description k, k differential clocks zq output driver impedance control input sa synchronous address input tck jtag test clock sa 0 , sa 1 synchronous burst address input (sa 0 = lsb) tms jtag test mode select dq synchronous data i/o tdi jtag test data input cq, cq differential output echo clocks tdo jtag test data output b 1 load external address v ref hstl input reference voltage b 2 burst r/ w enable v dd power supply b 3 single/double data selection v ddq output power supply g asynchronous output enable v ss gnd lbo linear burst order nc no connection
rev 2.0 512kx36 & 1mx18 sram - 3 - jan. 2002 k7d161871m k7d163671m package pin configurations (top view) k7d163671m(512kx36) * mode pin(6l) is a internally nc. 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b dq c8 dq c9 sa v ss b 1 v ss sa dq b9 dq b8 c v ss v ddq sa sa g sa sa v ddq v ss d dq c4 dq c7 sa v ss v dd v ss sa dq b7 dq b6 e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f dq c3 cq 1 dq c5 v dd v dd v dd dq b5 cq 2 dq b4 g v ss v ddq v ss v ss k v ss v ss v ddq v ss h dq c1 dq c2 dq c6 v dd k v dd dq b3 dq b2 dq b1 j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k dq d1 dq d2 dq d6 v ss b 2 v ss dq a3 dq a2 dq a1 l v ss v ddq v ss lbo b 3 mode v ss v ddq v ss m dq d3 cq 1 dq d5 v dd v dd v dd dq a5 cq 2 dq a4 n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p dq d4 dq d7 nc v ss v dd v ss sa dq a7 dq a6 r v ss v ddq v dd sa sa 1 sa v dd v ddq v ss t dq d8 dq d9 sa v ss sa 0 v ss sa dq a9 dq a8 u v ss v ddq tms tdi tck tdo nc v ddq v ss k7d161871m(1mx18) * mode pin(6l)is a internally nc. 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b nc dq b9 sa v ss b 1 v ss sa nc dq a8 c v ss v ddq sa sa g sa sa v ddq v ss d dq b4 nc sa v ss v dd v ss sa dq a7 nc e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f nc cq 1 nc v dd v dd v dd dq a5 nc dq a4 g v ss v ddq v ss v ss k v ss v ss v ddq v ss h dq b1 nc dq b6 v dd k v dd nc dq a2 nc j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k nc dq b2 nc v ss b 2 v ss dq a3 nc dq a1 l v ss v ddq v ss lbo b 3 mode v ss v ddq v ss m dq b3 nc dq b5 v dd v dd v dd nc cq 1 nc n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p nc dq b7 sa v ss v dd v ss sa nc dq 6 r v ss v ddq v dd sa sa 1 sa v dd v ddq v ss t dq b8 nc sa v ss sa 0 v ss sa dq a9 nc u v ss v ddq tms tdi tck tdo nc v ddq v ss
rev 2.0 512kx36 & 1mx18 sram - 4 - jan. 2002 k7d161871m k7d163671m function description the k7d163671m and k7d161871m are 18,874,368 bit synchronous pipeline burst mode sram devices. they are organized as 524,288 words by 36 bits for k7d163671m and 1,048,576 words by 18 bits for k7d161871m, fabricated using samsung's advanced cmos technology. single differential hstl level clock, k and k are used to initiate the read/write operation and all internal operations are self-timed. at the rising edge of k clock, all addresses and burst control inputs are registered internally. data inputs are registered one cy cle after write addresses are asserted(late write), at the rising edge of k clock for single data rate (sdr) write operations and at risin g and falling edge of k clock for a double data rate (ddr) write operations. data outputs are updated from output registers off the rising edges of k clock for sdr read operations and off the rising and fa lling edges of k clock for ddr read operations. free running echo clocks are supported which are representive of data output access time for all sdr and ddr operations. the chip is operated with a single +2.5v power supply and is compatible with extended hstl input and output. the package is 9x17(153) ball grid array balls on a 1.27mm pitch. read operation(single and double) during sdr read operations, addresses and controls are registered at the first rising edge of k clock and then the internal arra y is read between first and second rising edges of k clock. data outputs are updated from output registers off the second rising edge of k clock. during ddr read operations, addresses and controls are registered at the first rising edge of k clock, and then the int ernal array is read twice between first and second rising edges of k clock. data outputs are updated from output registers sequential ly by burst order off the second rising and falling edge of k clock. interleave and linear burst operation is controlled by lbo pin and the burst count is controllable with the maximum burst length of 4. to avoid data contention,at least one nop operations are required between the last read and the first write operation. write operation(late write) during sdr write operations, addresses and controls are registered at the first rising edge of k clock and data inputs are regis tered at the following rising edge of k clock. during ddr write operations, addresses and controls are registered at the first rising edge of k clock and data inputs are registered twice at the following rising and falling edge of k clock. write addresses and data input s are stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully writte n into sram array. e cho clock operation free running type of echo clocks are generated from k clock regardless of read, write and nop operations. they will stop operati on only when k clock is in the stop mode. echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture data outputs outputs. bypass read operation bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are identical. for this case, data outputs are from the data in registers instead of sram array. programmable impedance output driver the data output and echo clock driver impedance are adjusted by an external resistor, rq, connected between zq pin and v ss , and are equal to rq/5. for example, 250 w resistor will give an output impedance of 50 w . output driver impedance tolerance is 15% by test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. they may also occur in cycles initiated with g high. in all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the sram. impedance updates occur no more often than every 32 clock cycles. clock cycles are counted whether the sram is selected or not and proceed regardless of the type of cycle being executed. therefore, the user can be assured that after 33 con tin- uous read cycles have occurred, an impedance update will occur the next time g are high at a rising edge of the k clock. there are no power up requirements for the sram. however, to guarantee optimum output driver impedance after power up, the sram needs 1024 non-read cycles.
rev 2.0 512kx36 & 1mx18 sram - 5 - jan. 2002 k7d161871m k7d163671m truth table note : - b(both) is din in write cycle and dout in read cycle. byte write function is not supported. x means "don't care". - k & k are complementary. k g b1 b2 b3 dq operation l x x x x hi-z clock stop - x h l x hi-z no operation, pipeline high-z - l l h h dout load address, single read - l l h l dout load address, double read - x l l h din load address, single write - x l l l din load address, double write - x h h x b increment address, continue 4 burst operation for interleaved burst ( lbo = v ddq ) note : - for interleave burst lbo = v ddq is recommended. if lbo = v dd , it must not exceed 2.63v. interleaved burst case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 burst sequence table 4 burst operation for linear burst ( lbo = v ss ) linear burst mode case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0
rev 2.0 512kx36 & 1mx18 sram - 6 - jan. 2002 k7d161871m k7d163671m note : 1. state transitions ; b 1 =(load address), b 1 =(increment address, continue) b 2 =(read), b 2 =(write) b 3 =(single data rate), b 3 =(double data rate) bus cycle state diagram load new address increment address increment address increment address increment address read sdr write sdr read ddr write ddr b 2 , b 3 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 no op power up b 2 , b 3 b 1 b 2 , b 3 b 1 b 2 , b 3 b 1 b 1 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2
rev 2.0 512kx36 & 1mx18 sram - 7 - jan. 2002 k7d161871m k7d163671m recommended dc operating conditions note :1. these are dc test criteria. dc design criteria is v ref 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 2. v ih (max)dc= v ddq +0.3, v ih (max)ac= 2.6 v (2.1v for dqs) (pulse width 20% of cycle time). 3. v il (min)dc= - 0.3v, v il (min)ac=-1.0v (-0.5v for dqs) (pulse width 20% of cycle time). parameter symbol min typ max unit note core power supply voltage v dd 2.37 2.5 2.63 v output power supply voltage v ddq 1.4 1.5 1.9 v input high level voltage v ih v ref +0.1 - v ddq +0.3 v 1, 2 input low level voltage v il -0.3 - v ref -0.1 v 1, 3 input reference voltage v ref 0.68 0.75 1.0 v absolute maximum ratings note : power dissipation capability will be dependent upon package characteristics and use environment. see enclosed thermal impedan ce data. stresses greater than those listed under " absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol value unit core supply voltage relative to v ss v dd -0.5 to 3.13 v output supply voltage relative to v ss v ddq -0.5 to 2.3 v voltage on any pin relative to v ss v in -0.5 to v ddq +0.5 (2.3v max ) v output short-circuit current(per i/o) i out 25 ma storage temperature t str -55 to 125 c dc characteristics note :1. minimum cycle. i out =0ma. 2. 50% read cycles. 3. |i oh |=(v ddq /2)/(rq/5) 15% @v oh =v ddq /2 for 175 w rq 350 w . 4. |i ol |=(v ddq /2)/(rq/5) 15% @v ol =v ddq /2 for 175 w rq 350 w . 5. minimum impedance mode when zq pin is connected to v ss . parameter symbol min max unit note average power supply operating current(x36) (cycle time = t khkh min) i dd40 i dd37 i dd33 i dd30 - 950 850 750 670 ma 1,2 average power supply operating current(x18) (cycle time = t khkh min) i dd40 i dd37 i dd33 i dd30 - 900 800 700 620 ma 1,2 stop clock standby current (v in =v dd -0.2v or 0.2v fixed, k=low, k =high) i sb1 - 150 ma 1 input leakage current (v in =v ss or v ddq ) i li -1 1 m a output leakage current (v out =v ss or v ddq ) i lo -1 1 m a output high voltage(programmable impedance mode) v oh1 v ddq /2 v ddq v 3 output low voltage(programmable impedance mode) v ol1 v ss v ddq /2 v 4 output high voltage(i oh =-0.1ma) v oh2 v ddq -0.2 v ddq v 5 output low voltage(i ol =0.1ma) v ol2 v ss 0.2 v 5
rev 2.0 512kx36 & 1mx18 sram - 8 - jan. 2002 k7d161871m k7d163671m pin capacitance note : periodically sampled and not 100% tested.(t a =25 c , f=1mhz) parameter symbol test condition min max unit input capacitance c in v in =0v - 4 pf data output capacitance c out v out =0v - 5 pf ac test conditions (t a =0 to 70 c , v dd =2.37 -2.63v, v ddq =1.5v) parameter symbol value unit note input high/low level v ih /v il 1.25/0.25 v - input reference level v ref 0.75 v - input rise/fall time t r /t f 0.5/0.5 ns - output timing reference level 0.75 v - clock input timing reference level cross point v - output load see below - ac characteristics (t a =0 to 70 c , v dd =2.37 -2.63v, v ddq =1.5v) note : 1. see ac test output load figure 2. design target is 0ns parameter symbol -40 -37 -33 -30 unit note min max min max min max min max clock cycle time t khkh 2.5 - 2.7 - 3.0 - 3.3 - ns clock high pulse width t khkl 1.1 - 1.3 - 1.3 - 1.5 - ns clock low pulse width t klkh 1.1 - 1.3 - 1.3 - 1.5 - ns cq high pulse width t chcl t khkl -0.1 t khkl +0.1 t khkl -0.1 t khkl +0.1 t khkl -0.1 t khkl +0.1 t khkl -0.2 t khkl +0.2 ns cq low pulse width t clch t klkh -0.1 t klkh +0.1 t klkh -0.1 t klkh +0.1 t klkh -0.1 t klkh +0.1 t klkh -0.2 t klkh +0.2 ns clock to echo clock(cq) high t kxch 0.5 1.6 0.5 1.7 0.5 1.7 0.5 1.9 ns 1 clock to echo clock(cq) low t kxcl 0.5 1.6 0.5 1.7 0.5 1.7 0.5 1.9 ns echo clock to output valid t chqv/ t clqv - 0.1 - 0.1 - 0.1 - 0.1 ns 1,2 echo clock to output hold t chqx/ t clqx -0.15 - -0.2 - -0.25 - -0.3 - ns 1 echo clock to output high-z t chqz/ t chlz 0.1 0.1 0.1 0.1 ns 1 g low to output low-z t glqx 0.5 - 0.5 - 0.5 - 0.5 - ns 1 g high to output high-z t ghqz - 1.6 - 1.7 - 1.7 - 1.9 ns 1 g low to output valid t glqv - 1.6 - 1.7 - 1.7 - 1.9 ns 1 address setup time t avkh 0.4 - 0.4 - 0.4 - 0.4 - ns address hold time t khax 0.4 - 0.4 - 0.4 - 0.4 - ns burst control setup time t bvkh 0.4 - 0.4 - 0.4 - 0.4 - ns burst control hold time t khbx 0.3 - 0.3 - 0.3 - 0.3 - ns data setup time t dvkh 0.25 - 0.25 - 0.25 - 0.3 - ns data hold time t khdx 0.25 - 0.25 - 0.25 - 0.3 - ns 50 w 50 w ac test output load 25 w 5 pf dq 0.75v 5 pf 0.75v 50 w 50 w 0.75v
rev 2.0 512kx36 & 1mx18 sram - 9 - jan. 2002 k7d161871m k7d163671m nop continue k k b1 g sa t avkh t khax cq nop 1 2 3 4 5 6 7 8 10 12 11 b2 b3 cq dq read (burst of 4) read (burst of 2) read (burst of 4) nop write continue write (burst of 4) read 9 continue read read (burst of 4) continue read a 0 a 1 a 2 a 3 q x2 q 01 q 02 q 03 q 04 q 51 q 52 q 53 q 54 q 11 q 12 d 21 d 23 d 24 d 22 q 31 t bvkh t khbx t chqz t kxch t chlz t chqv t chqx t ghqz t dvkh t khdx t glqx t glqv t khkh t ghqx undefined don ? t care a 5 note 1. q 01 refers to output from address a. q 02 refers to output from the next internal burst address following a, etc. 2. outputs are disabled(high-z) one clock cycle after nop detected or after no pending data requests are present. 3. doing more than one read continue or write continue will cause the address to wrap around. timing waveforms for double data rate cycles (burst length=4, 2)
rev 2.0 512kx36 & 1mx18 sram - 10 jan. 2002 k7d161871m k7d163671m timing waveforms for single data rate cycles note : 1. q 01 refers to output from address a 0 . q 02 refers to output from the next internal burst address following a 0 , etc. 2. outputs are disabled(high-z) one clock cycle after nop detected or after no pending data requests are present. 3. this devices supports cycle lengths of 1, 2, 4. continue(b1=high, b2=high, b3=x) up to three times following a b1 operation. any further continue assertions constitute invalid operations. 4. this device will have an address wraparound if further continues are applied. nop continue t khkh t avkh t khax nop 1 2 3 4 5 6 7 8 10 12 11 read (burst of 2) read read (burst of 4) nop write continue write (burst of 2) read 9 continue read continue read continue read a 0 a 1 a 2 a 3 q x1 d 22 d 21 t bvkh t khbx t chqz t kxch t chlz t chqv t chqx t ghqz t ghqx t dvkh t khdx t glqx t glqv t klkh q 31 q 01 q 02 q 03 q 04 q 11 undefined don ? t care t khkl k k b1 g sa b2 b3 dq cq cq (burst length=4, 2, 1) (burst of 1)
rev 2.0 512kx36 & 1mx18 sram - 11 jan. 2002 k7d161871m k7d163671m ieee 1149.1 test access port and boundary scan-jtag tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo sa sa tdi tms tck test logic reset run test idle 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction dose not places dqs in hi-z. ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 1 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 bypass bypass register 3 1 0 0 sample boundary scan register 4 1 0 1 bypass bypass register 3 1 1 0 bypass bypass register 3 1 1 1 bypass bypass register 3 the sram provides a limited set of ieee standard 1149.1 jtag functions. this is to test the connectivity during manufacturing between sram, printed circuit board and other components. internal data is not driven out of sram under jtag control. in conform - ance with ieee 1149.1, the sram contains a tap controller, instruction register, bypass register and id register. the tap contro l- ler has a standard 16-state machine that resets internally upon power-up, therefore, trst signal is not required. it is possible to use this device without utilizing the tap. to disable the tap controller without interfacing with normal operation of the sram. tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left uncon- nected.
rev 2.0 512kx36 & 1mx18 sram - 12 jan. 2002 k7d161871m k7d163671m boundary scan exit order(x36) * reserved for mode pin 36 4a sa sa 6a 35 37 4c sa sa 6c 34 38 3a sa sa 7a 33 39 3b sa sa 7b 32 40 3c sa sa 7c 31 41 3d sa sa 7d 30 42 2b dq dq 8b 29 43 1b dq dq 9b 28 44 2d dq dq 8d 27 45 3f dq dq 7f 26 46 1d dq dq 9d 25 47 2f cq cq 8f 24 48 1f dq dq 9f 23 49 3h dq dq 7h 22 50 2h dq dq 8h 21 51 1h dq dq 9h 20 52 5a zq g 5c 19 53 5b b 1 k 5g 18 54 5k b 2 k 5h 17 55 5l b 3 mode 6l 16 56 4l lbo dq 9k 15 57 1k dq dq 8k 14 58 2k dq dq 7k 13 59 3k dq dq 9m 12 60 1m dq cq 8m 11 61 2m cq dq 9p 10 62 1p dq dq 7m 9 63 3m dq dq 8p 8 64 2p dq dq 9t 7 65 1t dq dq 8t 6 66 2t dq sa 7p 5 67 3t sa sa 7t 4 68 4r sa sa 6r 3 sa 5t 2 sa 5r 1 boundary scan exit order(x18) * reserved for mode pin 26 4a sa sa 6a 25 27 4c sa sa 6c 24 28 3a sa sa 7a 23 29 3b sa sa 7b 22 30 3c sa sa 7c 21 31 3d sa sa 7d 20 32 2b dq dq 9b 19 dq 8d 18 dq 7f 17 33 1d dq 34 2f cq dq 9f 16 35 3h dq dq 8h 15 36 1h dq 37 5a zq g 5c 14 38 5b b 1 k 5g 13 39 5k b 2 k 5h 12 40 5l b 3 mode 6l 11 41 4l lbo dq 9k 10 42 2k dq dq 7k 9 43 1m dq cq 8m 8 dq 9p 7 44 3m dq 45 2p dq 46 1t dq dq 8t 6 sa 7p 5 47 3p sa sa 7t 4 48 3t sa sa 6r 3 49 4r sa sa 5t 2 sa 5r 1 id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit (0) 512kx36 0000 00111 00100 xxxxxx 00001001110 1 1m x 18 0000 01000 00011 xxxxxx 00001001110 1 scan register definition part instruction register bypass register id register boundary scan 512kx36 3 bits 1 bits 32 bits 68 bits 1m x 18 3 bits 1 bits 32 bits 49 bits
rev 2.0 512kx36 & 1mx18 sram - 13 jan. 2002 k7d161871m k7d163671m jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification. parameter symbol min typ max unit note power supply voltage v dd 2.37 2.5 2.63 v input high level v ih 1.7 - v dd +0.3 v input low level v il -0.3 - 0.7 v output high voltage(i oh =-2ma) v oh 2.1 - v dd v output low voltage(i ol =2ma) v ol v ss - 0.2 v jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5 - ns tms input hold time t chmx 5 - ns tdi input setup time t dvch 5 - ns tdi input hold time t chdx 5 - ns clock low to output valid t clqv 0 10 ns jtag ac test conditions note : 1. see sram ac test output load on page 5. parameter symbol min unit note input high/low level v ih /v il 2.5/0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 1.25 v 1 jtag timing diagram tck tms tdi tdo t chch t chcl t clch t mvch t chmx t dvch t chdx t clqv
rev 2.0 512kx36 & 1mx18 sram - 14 jan. 2002 k7d161871m k7d163671m package dimensions 153-fcbga-1422 units:millimeters/inches 7 6 5 4 3 2 1 1 . 2 7 0 ? bottom view 0.300 max m 153- ? 0.750 0.150 14.000 2 2 . 0 0 0 1.27x8=10.160 c h i p a r e a top view 0.200 max 9 8 1 . 2 7 x 1 6 = 2 0 . 3 2 0 1.270 b c d e f g h j k l m n p r t u a chip area 9 . 7 5 0 5.750 r1.250 #a1 index chip back side 0 . 6 0 0 2 . 5 0 0 0 . 6 0 0 0 . 0 5 0 1 . 2 0 0 0 . 1 0 0 underfill 153 bga package thermal characteristics note : 1. junction temperature can be calculated by : t j = t a + p d x theta_ja. parameter symbol thermal resistance unit note junction to ambient(at still air) theta_ja 22.8 c /w 1w heating junction to case theta_jc 0.6 c /w junction to board theta_jb 4.2 c /w 2w heating

▲Up To Search▲

Price & Availability of K7D161871M-HC30

	To Download K7D161871M-HC30 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .