View LSM330DLC_6501558.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. september 2012 doc id 022162 rev 2 1/66 66 LSM330DLC inemo inertial module: 3d accelerometer and 3d gyroscope datasheet ? production data features analog supply voltage: 2.4 v to 3.6 v digital supply voltage ios: 1.8 v low power mode power-down mode 3 independent acceleration channels and 3 angular rate channels 2 g /4 g /8 g /16 g dynamically selectable full scale 250/500/2000 dps dynamically selectable full scale spi/i 2 c serial interface (16-bit data output) programmable interrupt generator for free-fall and motion detection ecopack ? rohs and ?green? compliant application gps navigation systems impact recognition and logging gaming and virtual reality input devices motion activated functions intelligent power saving for handheld devices vibration monitoring and compensation free-fall detection 6d orientation detection description the LSM330DLC is a system-in-package featuring a 3d digital accelerometer and a 3d digital gyroscope. st?s family of mems sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers. the various sensing elements are manufactured using specialized micromachining processes, while the ic interfaces are developed using a cmos technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. the LSM330DLC has dynamically user- selectable full scale acceleration range of 2 g /4 g /8 g /16 g and angular rate of 250/500/2000 deg/sec. the accelerometer and gyroscope sensors can be either activated or separately put in low power/power-down mode for applications optimized for power saving. the LSM330DLC is available in a plastic land grid array (lga) package. table 1. device summary part number temperature range [c] package packing LSM330DLC -40 to +85 lga-28l (4x5x1.1 mm) tr ay LSM330DLCtr -40 to +85 tape and reel lga-28l (4x5x1.1 mm) www.st.com
contents LSM330DLC 2/66 doc id 022162 rev 2 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.2 i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 normal mode, low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.2 6d/4d orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.3 ?sleep-to-wake? and ?return to sleep? . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 linear acceleration digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.1 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.2 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.3 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.4 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.5 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.6 retrieve data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 gyroscope digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LSM330DLC contents doc id 022162 rev 2 3/66 4.4.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.4 bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.5 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.6 retrieve data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 level-sensitive / edge-sensitive data enable . . . . . . . . . . . . . . . . . . . . . . 24 4.5.1 level-sensitive trigger stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5.2 edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.1 ctrl_reg1_a (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.2 ctrl_reg2_a (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3 ctrl_reg3_a (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.4 ctrl_reg4_a (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.5 ctrl_reg5_a (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.6 ctrl_reg6_a (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.7 reference/datacapture_a (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.8 status_reg_a (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.9 out_x_l_a, out_x_h_a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.10 out_y_l_a, out_y_h_a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.11 out_z_l _a, out_z_h_a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
contents LSM330DLC 4/66 doc id 022162 rev 2 8.12 fifo_ctrl_reg_a (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.13 fifo_src_reg_a (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.14 int1_cfg_a (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.15 int1_src_a (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.16 int1_ths_a (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.17 int1_duration_a (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.18 click_cfg _a (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.19 click_src_a (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.20 click_ths_a (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.21 time_limit_a (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.22 time_latency_a (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.23 time window_a (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.24 act_ths (3eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.25 act_dur (3fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.26 who_am_i_g (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.27 ctrl_reg1_g (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.28 ctrl_reg2_g (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.29 ctrl_reg3_g (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.30 ctrl_reg4_g (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.31 ctrl_reg5_g (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.32 reference_g (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.33 out_temp_g (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.34 status_reg_g (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.35 out_x_l_g, out_x_h_g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.36 out_y_l_g, out_y_h_g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.37 out_z_l_g, out_z_h_g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.38 fifo_ctrl_reg_g (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.39 fifo_src_reg_g (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.40 int1_cfg_g (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.41 int1_src_g (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.42 int1_ths_xh_g (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.43 int1_ths_xl_g (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.44 int1_ths_yh _g (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
LSM330DLC contents doc id 022162 rev 2 5/66 8.45 int1_ths_yl_g (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.46 int1_ths_zh_g (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.47 int1_ths_zl_g (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.48 int1_duration_g (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
list of tables LSM330DLC 6/66 doc id 022162 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. i2c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 28 table 15. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 28 table 16. linear acceleration sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17. angular rate sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 18. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 19. ctrl_reg1_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 20. ctrl_reg1_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 21. data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 22. ctrl_reg2_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 23. ctrl_reg2_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 24. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 25. ctrl_reg3_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 26. ctrl_reg3_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 27. ctrl_reg4_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 28. ctrl_reg4_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 29. ctrl_reg5_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 30. ctrl_reg5_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 31. ctrl_reg6_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 32. ctrl_reg6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 33. reference_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 34. reference register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 table 35. status_reg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 36. status_reg_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 37. fifo_ctrl_reg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 38. fifo_ctrl_reg_a register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 39. fifo mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 40. fifo_src_reg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 41. fifo_src_reg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 42. int1_cfg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 43. int1_cfg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 44. interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 45. int1_src_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 46. int1_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 47. int1_ths_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 48. int1_ths_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
LSM330DLC list of tables doc id 022162 rev 2 7/66 table 49. int1_duration_aregister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 50. int1_duration_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 51. click_cfg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 52. click_cfg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 53. click_src_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 54. click_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 55. click_ths_a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 56. click_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 57. time_limit_a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 58. time_limit_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 59. time_latency_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 60. time_latency_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 table 61. time_window_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 62. time_window_a description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 table 63. act_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 64. act_ths description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 65. act_dur register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 66. act_dur description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 67. who_am_i_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 68. ctrl_reg1_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 69. ctrl_reg1_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 70. dr and bw configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 71. power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 72. ctrl_reg2_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 73. ctrl_reg2_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 74. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 75. high-pass filter cut-off frequency configuration [hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 76. ctrl_reg3_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 77. ctrl_reg3_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 78. ctrl_reg4_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 79. ctrl_reg4_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 80. ctrl_reg5_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 81. ctrl_reg5_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 82. reference_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 83. reference_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 84. out_temp_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 85. out_temp_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 86. status_reg_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 87. status_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 88. fifo_ctrl_reg_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 89. fifo_ctrl_reg_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 90. fifo mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 91. fifo_src_reg_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 92. fifo_src_reg_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 93. int1_cfg_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 94. int1_cfg_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 95. int1_src_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 96. int1_src_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 97. int1_ths_xh_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 98. int1_ths_xh_g description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 99. int1_ths_xl_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 100. int1_ths_xl_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
list of tables LSM330DLC 8/66 doc id 022162 rev 2 table 101. int1_ths_yh_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 102. int1_ths_yh_g description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 103. int1_ths_yl_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 104. int1_ths_yl_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 105. int1_ths_zh_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 106. int1_ths_zh_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 107. int1_ths_zl_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 108. int1_ths_zl_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 109. int1_duration_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 110. int1_duration_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 table 111. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
LSM330DLC list of figures doc id 022162 rev 2 9/66 list of figures figure 1. LSM330DLC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. i2c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. gyroscope block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. level-sensitive trigger stamping (lvlen = 1; extren = 0) . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. LSM330DLC electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16. multiple-byte spi read protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 18. multiple bytes spi write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 19. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 20. int1_sel and out_sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 21. wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 22. wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 23. lga-28 (4x5x1.1 mm): mechanical data and package dimensions . . . . . . . . . . . . . . . . . . 60
block diagram and pin description LSM330DLC 10/66 doc id 022162 rev 2 1 block diagram and pin description 1.1 block diagram figure 1. LSM330DLC block diagram y+ z+ y- z- x+ x- mux c s _a/g s da/ s di_a/g s do_a/g i (a) + - charge amplifier s en s ing block s en s ing interf a ce a/d control logic converter i2c/spi int1_a int2_a i ( ) drive+ drive- feedback+ feedback- demodulator voltage automatic gain control low - pass filter gain amplifier analog conditioning control logic & interrupt gen. clock trimming circuits reference generator phase + - charge amplifier y+ z+ y- z- x+ x- mux int1_g drdy_g\int2_g s cl_a/g am10160v1
LSM330DLC block diagram and pin description doc id 022162 rev 2 11/66 1.2 pin description figure 2. pin connection x 1 y z direction of detectable acceleration s z direction of detectable angular rate s 1 + y + z + x x x den_g filtvdd re s c s _g gnd filtin y filtout y/ out y re s (bottom view) vdd 1 6 7 14 21 2 8 vdd_io c s _a s cl_a/g vdd_io s do_g s do_a s da_a/g vdd re s re s re s re s vdd re s int1_g int1_a int2_a re s cap gnd drdy_g/int2_g re s 20 15 am10161v1 table 2. pin description pin# name function 1gnd0 v supply 2 res reserved. connect to gnd 3 res reserved. connect to gnd 4 res reserved. connect to gnd 5 res reserved. connect to gnd 6gnd0 v supply 7 vdd power supply 8 vdd power supply 9 vdd power supply 10 res reserved. connect to vdd 11 res reserved. connect to vdd 12 res reserved. connect to vdd 13 res reserved. connect to vdd 14 res reserved. connect to vdd 15 cap connect to gnd with ceramic capacitor, 10 nf (+/-10%), 25 v 16 den_g gyroscope data enable 17 drdy_g/ int2_g gyroscope data ready/interrupt signal 2 18 int1_g gyroscope interrupt signal
block diagram and pin description LSM330DLC 12/66 doc id 022162 rev 2 19 int2_a accelerometer interrupt signal 20 int1_a accelerometer interrupt signal 21 vdd_io power supply for io pins 22 cs_g gyroscope: spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 23 cs_a accelerometer: spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 24 scl_a/g i 2 c serial clock (scl)/spi serial port clock (spc) 25 vdd_io power supply for io pins 26 sdo_g gyroscope: spi serial data output (sdo) i 2 c least significant bit of the device address (sa0) 27 sdo_a accelerometer: spi serial data output (sdo) i 2 c least significant bit of the device address (sa0) 28 sda_a/g i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) table 2. pin description (continued) pin# name function
LSM330DLC module specifications doc id 022162 rev 2 13/66 2 module specifications 2.1 mechanical characteristics @ vdd = 3v, t = 25 c unless otherwise noted (a) a. the product is factory calibrated at 3.0 v. the operational power supply range is from 2.4 v to 3.6 v. table 3. mechanical characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range (2) user-selectable 2 g 4 8 16 g_fs angular rate measurement range (3) user-selectable 250 dps 500 2000 la_so linear acceleration sensitivity fs = 2 g 1 m g /digit fs = 4 g 2 fs = 8 g 4 fs = 16 g 12 g_so angular rate sensitivity fs = 250 dps 8.75 mdps/ digit fs = 500 dps 17.50 fs = 2000 dps 70 la_so linear acceleration sensitivity change vs. temperature fs = 2 g 0.05 %/c g_sodr angular rate sensitivity change vs. temperature from -40 c to +85 c 2 % la_tyoff linear acceleration typical zero- g level offset accuracy (3) fs bit set to 00 60 m g g_tyoff angular rate typical zero-rate level (4) fs = 250 dps 10 dps fs = 500 dps 15 fs = 2000 dps 25 la_tcoff linear acceleration zero- g level change vs. temperature max delta from 25 c 0.5 m g /c g_tcoff zero-rate level change vs. temperature 0.05 dps/c an acceleration noise density fs = 2 g, normal mode ta bl e 9 , odr bit set to 1001 ta b l e 1 9 220 g / hz
module specifications LSM330DLC 14/66 doc id 022162 rev 2 2.2 electrical characteristics @ vdd = 3 v, t = 25 c unless otherwise noted rn rate noise density fs = 250 dps, bw = 50 hz 0.03 dps/ top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. verified by wafer level test and measurement of initial offset and sensitivity. 3. typical zero- g level offset value after msl3 preconditioning. 4. offset can be eliminated by enabling the built-in high-pass filter. table 3. mechanical characteristics (continued) symbol parameter test conditions min. typ. (1) max. unit hz table 4. electrical characteristics symbol parameter test conditions min. typ. (1) max. unit vdd supply voltage 2.4 3.6 v vdd_io power supply for i/o 1.71 vdd+0.1 v la_idd accelerometer current consumption in normal mode odr = 50 hz 11 a odr = 1 hz 2 la_iddlowp accelerometer current consumption in low power mode odr = 50 hz 6 a la_iddpdn accelerometer current consumption in power-down mode 0.5 a g_idd gyroscope current consumption in normal mode 6.1 ma g_iddlowp gyroscope supply current in sleep mode (2) 2ma g_iddpdn gyroscope current consumption in power-down mode 5a vih digital high level input voltage 0.8*vdd_io v vil digital low level input voltage 0.2*vdd_io v voh high level output voltage 0.9*vdd_io v vol low level output voltage 0.1*vdd_io v top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. sleep mode introduces a faster turn-on time compared to power-down mode.
LSM330DLC module specifications doc id 022162 rev 2 15/66 2.3 temperature sensor characteristics @ vdd = 3v, t = 25 c unless otherwise noted (b) b. the product is factory calibrated at 3.0 v. table 5. electrical characteristics symbol parameter test condition min. typ. (1) max. unit tsdr temperature sensor output change vs. temperature - -1 c/digit todr temperature refresh rate 1 hz top operating temperature range -40 +85 c 1. typical specifications are not guaranteed.
module specifications LSM330DLC 16/66 doc id 022162 rev 2 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and t op . figure 3. spi slave timing diagram (c)(d) 3. data on cs, spc, sdi and sdo refer to pins: cs_a, cs_g, scl_a/g, sda_a/g, sdo_a / sdo_g. table 6. spi slave timing values symbol parameter value (1) unit min max tc(spc) spi clock cycle 100 ns fc(spc) spi clock frequency 10 mhz tsu(cs) cs setup time 6 ns th(cs) cs hold time 8 tsu(si) sdi input setup time 5 th(si) sdi input hold time 15 tv(so) sdo valid output time 50 th(so) sdo output hold time 9 tdis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results. not tested in production. c. the sdo output line features an internal pull-up. d. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output ports. spc cs sdi sdo t su(cs) t v(so) t h(so) t h(si) t su(si) t h(cs) t dis(so) t c(spc) msb in msb out lsb out lsb in (3) (3) (3) (3) (3) (3) (3) (3)
LSM330DLC module specifications doc id 022162 rev 2 17/66 2.4.2 i 2 c - inter ic control interface subject to general operating conditions for vdd and t op . figure 4. i 2 c slave timing diagram (e) table 7. i 2 c slave timing values symbol parameter (1) i 2 c standard mode (1) i 2 c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b ( 2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. scl (scl_a/g pin), sda (sda_a/g pin) 2. cb = total capacitance of one bus line, in pf e. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports 6'$ 6&/ w i6'$ w vx63 w z6&// w vx6'$ w u6'$ w vx65 w k67 w z6&/+ w k6'$ w u6&/ w i6&/ w z6365 67$57 5(3($7(' 67$57 6723 67$57 !-v
module specifications LSM330DLC 18/66 doc id 022162 rev 2 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 8. absolute maximum ratings (1) 1. supply voltage on any pin should never exceed 4.8 v. symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin (scl_a/g, sda_a/g, sdo_a, sdo_g, cs_a, cs_g, den_g) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 3 v) 3000 g for 0.5 ms 10000 g for 0.1 ms a unp acceleration (any axis, unpowered) 3000 g for 0.5 ms 10000 g for 0.1 ms t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 2 (hbm) kv this is a mechanical shock sensitive device, improper handling can cause permanent damage to the part. this is an esd sensitive device, improper handling can cause permanent damage to the part.
LSM330DLC terminology doc id 022162 rev 2 19/66 3 terminology 3.1 sensitivity linear acceleration sensitivity can be determined e.g. by applying 1 g acceleration to the device. because the sensor can measure dc accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and over time. the sensitivity tolerance describes the range of sensitivities of a large number of sensors. angular rate sensitivity describes the angular rate gain of the sensor and can be determined by applying a defined angular velocity to it. this value changes very little over temperature and also very little over time. 3.2 zero- g level linear acceleration zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady state on a horizontal surface will measure 0 g on both the x axis and y axes, whereas the z axis will measure 1 g . ideally, the output is in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is to some extent a result of stress to mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?linear acceleration zero- g level change vs. temperature? in ta b l e 3 . the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a group of sensors. angular rate zero-rate level describes the actual output value if there is no angular rate present. zero-rate level of precise mems sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. this value changes very little over temperature and over time.
functionality LSM330DLC 20/66 doc id 022162 rev 2 4 functionality the LSM330DLC is a system-in-package featuring a 3d digital accelerometer and a 3d digital gyroscope. the device includes specific sensing elements and two ic interfaces capable to measuring both the acceleration and angular rate applied to the module and to provide a signal to external applications through an spi/i 2 c serial interface. the various sensing elements are manufactured using specialized micromachining processes, while the ic interfaces are developed using a cmos technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. the LSM330DLC may also be configured to generate an inertial wakeup and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. 4.1 normal mode, low power mode the LSM330DLC provides two different operating modes: normal mode and low power mode . normal mode guarantees high resolution, while low power mode further reduces current consumption. the table below summarizes how to select the operating mode and the corresponding characteristics. 4.1.1 self-test self-test allows the checking of sensor functionality without moving it. the self-test function is off when the self-test bit (st) is programmed to ?0?. when the self-test bit is programmed to ?1? an actuation force is applied to the sensor, simulating a definite input acceleration. in this case, the sensor outputs exhibit a change in their dc levels which are related to the selected full scale through the device sensitivity. when self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified in ta b l e 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 4.1.2 6d/4d orient ation detection the LSM330DLC includes 6d/4d orientation detection. in this configuration the interrupt is generated when the device is stable in a known direction. in 4d configuration, z axis position detection is disabled. table 9. operating mode selection operating mode ctrl_reg1[3] (lpen bit) ctrl_reg4[3] (hr bit) bw [hz] turn-on time [ms] low power mode (8-bit) 1 0 odr/2 1 normal mode (12-bit) 0 1 odr/9 7/odr(khz)
LSM330DLC functionality doc id 022162 rev 2 21/66 4.1.3 ?sleep-to-wake? and ?return to sleep? the LSM330DLC can be programmed to automatically switch to low power mode upon recognition of a determined event. once the event condition is over, the device returns to the preset normal mode. to enable this function, the desired threshold value must be stored in the act_ths register , while the duration value is written in the act_dur register . when the internally high-pass filtered acceleration becomes lower than the threshold value on all the three axes, the device automatically switches to low power mode (10hz odr). during this condition, the odrx bits and lpen bit in the ctrl_reg1_g register and the hr bit in the ctrl_reg3_g register are not considered. when the acceleration goes back over the threshold (on at least one axis), the system restores the operating mode and odrs as per the ctrl_reg1_g register and ctrl_reg3_g register settings. 4.2 linear acceleration digital main blocks 4.2.1 fifo the LSM330DLC embeds 32 slots of data fifo for each of the three output channels: x, y and z. this allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. this buffer can work accordingly in four different modes: bypass mode, fifo mode, stream mode and stream-to-fifo mode. each mode is selected by the fifo_mode bits in the fifo_ctrl_reg_a register . programmable watermark level, fifo_empty or fifo_full events can be enabled to generate dedicated interrupts on the int1_a/int2_a pin (configured through the fifo_ctrl_reg_a register ). 4.2.2 bypass mode in bypass mode, the fifo is not operational and for this reason it remains empty. for each channel only the first address is used. the remaining fifo slots are empty. 4.2.3 fifo mode in fifo mode, data from the x, y and z channels are stored into the fifo. a watermark interrupt can be enabled (fifo_wtmk_en bit in the fifo_ctrl_reg_a register in order to be raised when the fifo is filled to the level specified into the fifo_wtmk_level bits of the fifo_ctrl_reg_a register . the fifo continues filling until it is full (32 slots of data for x, y and z). when full, the fifo stops collecting data from the input channels. 4.2.4 stream mode in stream mode, data from x, y and z measurement are stored into the fifo. a watermark interrupt can be enabled and set as in fifo mode.the fifo continues filling until it is full (32 slots of data for x, y and z). when full, the fifo discards the older data as the new data arrives.
functionality LSM330DLC 22/66 doc id 022162 rev 2 4.2.5 stream-to-fifo mode in stream-to-fifo mode, data from x, y and z measurement is stored in the fifo. a watermark interrupt can be enabled (fifo_wtmk_en bit in the fifo_ctrl_reg_a register ) in order to be raised when the fifo is filled to the level specified in the fifo_wtmk_level bits of the fifo_ctrl_reg_a register . the fifo continues filling until it is full (32 slots of 8 -bit data for x, y and z). when full, the fifo discards the older data as the data new arrives. once trigger event occurs, the fifo starts operating in fifo mode. 4.2.6 retrieve data from fifo fifo data is read through out_x_l_a, out_x_h_a , out_y_l_a, out_y_h_a and out_z_l _a, out_z_h_a . when the fifo is in stream, trigger or fifo mode, a read operation to the out_x_l_a, out_x_h_a , out_y_l_a, out_y_h_a or out_z_l _a, out_z_h_a registers provides the data stored in the fifo. each time data is read from the fifo, the oldest x, y and z data are placed in the out_x_l_a, out_x_h_a , out_y_l_a, out_y_h_a and out_z_l _a, out_z_h_a registers and both single read and read_burst operations can be used. 4.3 gyroscope digital main blocks figure 5. gyroscope block diagram adc lpf1 hpf 0 1 hpen lpf2 10 11 01 00 o u t_ s el d a t a reg 00 11 10 01 interr u pt gener a tor int_ s el i 2 c s pi int1 s cr reg conf reg fifo 3 2x16x 3 am072 3 0v1
LSM330DLC functionality doc id 022162 rev 2 23/66 4.4 fifo the LSM330DLC embeds 32 slots of 16-bit data fifo for each of the three output channels: yaw, pitch and roll. this allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but can wake up only when needed and burst the significant data out from the fifo. this buffer can work accordingly in five different modes: bypass mode, fifo mode, stream mode, bypass-to- stream mode and stream-to-fifo mode. each mode is selected by the fifo_mode bits in the fifo_ctrl_reg_g register . programmable watermark level, fifo_empty or fifo_full events can be enabled to generate dedicated interrupts on the drdy_g/int2_g pin (configured through the ctrl_reg3_g register and event detection information is available in the fifo_src_reg_g register . watermark level can be configured to wtm4:0 in the fifo_ctrl_reg_g register . 4.4.1 bypass mode in bypass mode, the fifo is not operational and for this reason it remains empty. as described in figure 6 below, for each channel only the first address is used. the remaining fifo slots are empty. when new data is available the old data is overwritten. figure 6. bypass mode 4.4.2 fifo mode in fifo mode, data from the yaw, pitch and roll channels is stored in the fifo. a watermark interrupt can be enabled (i2_wmk bit in the ctrl_reg3_g register ) in order to be raised when the fifo is filled to the level specified in the wtm 4:0 bits of the fifo_ctrl_reg_g register . the fifo continues filling until it is full (32 slots of 16-bit data for yaw, pitch and roll). when full, the fifo stops collecting data from the input channels. to restart data collection, the fifo_ctrl_reg_g register must be written back to bypass mode. fifo mode is represented in figure 7: fifo mode . l x 0 y z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 3 1 y 3 1 z 3 1 x i ,y i ,z i empty am072 3 1v1
functionality LSM330DLC 24/66 doc id 022162 rev 2 figure 7. fifo mode 4.4.3 stream mode in stream mode, data from yaw, pitch and roll measurement is stored in the fifo. a watermark interrupt can be enabled and set as in fifo mode.the fifo continues filling until it is full (32 slots of 16-bit data for yaw, pitch and roll). when full, the fifo discards the older data as the new data arrives. programmable watermark level events can be enabled to generate dedicated interrupts on the drdy_g/int2_g pin (configured through the ctrl_reg3_g register . stream mode is represented in figure 8: stream mode . x 0 y z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 3 1 y 3 1 z 3 1 x i ,y i ,z i am072 3 2v1
LSM330DLC functionality doc id 022162 rev 2 25/66 figure 8. stream mode x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 3 1 y 3 1 z 3 1 x i ,y i ,z i x 3 0 y 3 0 z 3 0 am072 3 4v1
functionality LSM330DLC 26/66 doc id 022162 rev 2 4.4.4 bypass-to-stream mode in bypass-to-stream mode, the fifo starts operating in bypass mode and once a trigger event occurs (related to int1_cfg_g register events) the fifo starts operating in stream mode. refer to figure 9 below. figure 9. bypass-to-stream mode 4.4.5 stream-to-fifo mode in stream-to-fifo mode, data from yaw, pitch and roll measurement is stored in the fifo. a watermark interrupt can be enabled on pin drdy/int2 by setting the i2_wtm bit in ctrl_reg3_g register to be raised when the fifo is filled to the level specified in the wtm4:0 bits of the fifo_ctrl_reg_g register . the fifo continues filling until it is full (32 slots of 16-bit data for yaw, pitch and roll). when full, the fifo discards the older data as the new data arrives. once a trigger event occurs (related to int1_cfg_g register events), the fifo starts operating in fifo mode. refer to figure 10: trigger stream mode . x 0 y i z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 3 1 y 3 1 z 3 1 x i ,y i ,z i empty byp ass mode s tre a m mode trigger event x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 3 1 y 3 1 z 3 1 x i ,y i ,z i x 3 0 y 3 0 z 3 0 am072 3 5v1
LSM330DLC functionality doc id 022162 rev 2 27/66 figure 10. trigger stream mode 4.4.6 retrieve data from fifo fifo data is read through out_x_l_g, out_x_h_g , out_y_l_g, out_y_h_g and out_z_l_g, out_z_h_g . when the fifo is in stream, trigger or fifo mode, a read operation to the out_x_l_g, out_x_h_g , out_y_l_g, out_y_h_g or out_z_l_g, out_z_h_g registers provides the data stored in the fifo. each time data is read from the fifo, the oldest pitch, roll and yaw data are placed in the out_x_l_g, out_x_h_g , out_y_l_g, out_y_h_g and out_z_l_g, out_z_h_g registers and both single read and read_burst (x,y & z with autoincremental address) operations can be used. when data included in out_z_h_g is read, the system again starts to read information from addr out_x_l _g. 4.5 level-sensitive / edge-sensitive data enable the LSM330DLC allows external trigger level recognition through the enabling of the extren and lvlen bits in the ctrl_reg2_g register . two different modes can be used: level-sensitive or edge-sensitive trigger. x 0 y i z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 3 1 y 3 1 z 3 1 x i ,y i ,z i s tre a m mode fifo mode trigger event x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 3 1 y 3 1 z 3 1 x i ,y i ,z i x 3 0 y 3 0 z 3 0 am072 3 6v1
functionality LSM330DLC 28/66 doc id 022162 rev 2 figure 11. level-sensitive trigger stamping (lvlen = 1; extren = 0) 4.5.1 level-sensitive trigger stamping once enabled, den level replaces the lsb of the x, y or z axes, configurable through the xen, yen, zen bits in the ctrl_reg1_g register . data is stored in the fifo with the internally-selected odr. 4.5.2 edge-sensitive trigger once enabled by setting extren = 1, fifo is filled with the pitch, roll and yaw data on the rising edge of the den input signal. when selected odr is 800 hz, the maximum den sample frequency is f den = 1/t den = 400 hz. x i (15-1) x i ,y i ,z i d e n y i (15-0) z i (15-0) x i-n+1 d e n (15-1) y i-n+1 (15-0) z i-n+1 (15-0) x i (15-0) x i ,y i ,z i d e n y i (15-1) z i (15-0) x i (15-0) x i ,y i ,z i d e n y i (15-0) z i (15-1) x i-n+1 d e n (15-0) y i-n+1 (15-0) z i-n+1 (15-1) x i-n+1 d e n y i-n+1 z i-n+1 (15-0) (15-1) (15-0) level- s en s itive trigger en ab led on x-axi s level- s en s itive trigger en ab led on y- a xi s level- s en s itive trigger en ab led on z- a xi s xen=1,yen=zen=0 yen=1, xen=zen=0 zen=1, xen=yen=0 am10162v1
LSM330DLC functionality doc id 022162 rev 2 29/66 figure 12. edge-sensitive trigger 4.6 factory calibration the ic interface is factory calibrated for sensitivity and zero level. the trimming values are stored in the device in non volatile memory. any time the device is turned on, the trimming parameters are downloaded to the registers to be used during normal operation. this allows use of the device without further calibration.
application hints LSM330DLC 30/66 doc id 022162 rev 2 5 application hints figure 13. LSM330DLC electrical connection 5.1 external capacitors the device core is supplied through the vdd line. power supply decoupling capacitors (c2, c3=100 nf ceramic, c4=10 f al) should be placed as near as possible to the supply pin of the device (common design practice). all voltage and ground supplies must be present at the same time to achieve proper behavior of the ic (refer to figure 13 ). the functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the spi/i 2 c interface. the functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the spi/i 2 c interface. digit a l s ign a l from/to s ign a l controller. s ign a l s level s a re defined b y proper s election of vdd direction of detectable acceleration s direction of detectable angular rate den_g filtvdd re s c s _g gnd filtin y filtout y/ out y re s (bottom view) vdd 1 6 7 14 8 2 1 2 vdd_io c s _a s cl_a/g vdd_io s do_g s do_a s da_a/g vdd re s re s re s re s vdd re s int1_g int1_a int2_a re s cap gnd drdy_g re s 20 15 vdd c1 10nf(25v) gnd 100 nf gnd gnd 10 f gnd vdd_io gnd 100 nf c 3 c4 c2 x 1 y z z 1 + y + z + x x x * c1 must guarantee 1 nf value under 11 v bias condition am1016 3 v1
LSM330DLC application hints doc id 022162 rev 2 31/66 5.2 soldering information the lga package is compliant with ecopack ? , rohs and ?green? standards. it is qualified for soldering heat resistance according to jedec j-std-020d. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com/mems .
digital interfaces LSM330DLC 32/66 doc id 022162 rev 2 6 digital interfaces the registers embedded in the LSM330DLC may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. to select/exploit the i 2 c interface, the cs line must be tied high (i.e. connected to vdd_io). 6.1 i 2 c serial interface the LSM330DLC i 2 c is a bus slave. the i 2 c is employed to write the data to the registers, whose content can also be read back. the relevant i 2 c terminology is provided in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. table 10. serial interface pin description pin name pin description cs_a linear acceleration spi enable linear acceleration i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) cs_g angular rate spi enable angular rate i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl_a/g i 2 c serial clock (scl) spi serial port clock (spc) sda_a/g i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo_a sdo_g i 2 c least significant bit of the device address (sa0) spi serial data output (sdo) table 11. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
LSM330DLC digital interfaces doc id 022162 rev 2 33/66 6.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits, and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded in the LSM330DLC behaves like a slave device and the following protocol must be adhered to. after the start condition (st), a slave address is sent. once a slave acknowledge (sak) has been returned, an 8-bit sub-address (sub) is transmitted: the 7 lsb represent the actual register address while the msb enables address auto increment. if the msb of the sub field is ?1?, the sub (register address) will be automatically increased to allow multiple data read/write. data is transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes sent per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line, scl, low to force the transmitter into a wait state. table 12. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 13. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 14. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 15. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data
digital interfaces LSM330DLC 34/66 doc id 022162 rev 2 data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of first register to be read. in the communication format presented, mak is master acknowledge and nmak is no master acknowledge. default address: the sdo / sa0 pin (sdo_a / sdo_g) can be used to modify the least significant bit of the device address. if the sa0 pad is connected to voltage supply, the lsb is ?1? (ex. address 0011001b), otherwise if the sa0 pad is connected to ground, the lsb value is ?0? (ex address 0011000b). the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition will have to be issued after the two sub-address bytes; if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. ta b l e 1 6 and 17 explain how the sad+read/write bit pattern is composed, listing all the possible configurations. linear acceleration address: the default (factory) 7-bit slave address is 001100xb. angular rate sensor: the default (factory) 7-bit slave address is 110101xb. table 16. linear acceleration sad+read/write patterns command sad[6:1] sad[0] = sdo_a pin r/w sad+r/w read 001100 0 1 00110001 (31h) write 001100 0 0 00110000 (30h) read 001100 1 1 00110011 (33h) write 001100 1 0 00110010 (32h) table 17. angular rate sad+read/write patterns command sad[6:1] sad[0] = sdo_g pin r/w sad+r/w read 110101 0 1 11010101 (d5h) write 110101 0 0 11010100 (d4h) read 110101 1 1 11010111 (d7h) write 110101 1 0 11010110 (d6h)
LSM330DLC digital interfaces doc id 022162 rev 2 35/66 6.2 spi bus interface the LSM330DLC spi is a bus slave. the spi allows writing and reading the registers of the device. the serial interface interacts with the outside world through 4 wires: cs , spc , sdi and sdo (spc, sdi, sd0 are common). figure 14. read and write protocol cs is the serial port enable and is controlled by the spi master. it goes low at the start of the transmission and returns high at the end. spc is the serial port clock and is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. these lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple-byte read/write. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs , while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written to the device. when 1, the data do(7:0) from the device is read. in the latter case, the chip drives sdo at the start of bit 8. bit 1 : ms bit. when 0, the address remains unchanged in multiple read/write commands. when 1, the address is auto-incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that will be written to the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). in multiple read/write commands, further blocks of 8 clock periods will be added. when the ms bit is ?0?, the address used to read/write data remains the same for every block. when the ms bit is ?1?, the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. c s s pc s di s do rw ad5 ad4 ad 3 ad2 ad1 ad0 di7 di6 di5 di4 di 3 di2 di1 di0 do7 do6 do5 do4 do 3 do2 do1 do0 m s am10129v1
digital interfaces LSM330DLC 36/66 doc id 022162 rev 2 6.2.1 spi read figure 15. spi read protocol the spi read command is performed with 16 clock pulses. a multiple-byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, do not increment address; when 1, increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). bit 16-... : data do(...-8). further data in multiple-byte reading. figure 16. multiple-byte spi read protocol (2-byte example) c s s pc s di s do rw do7 do6 do5 do4 do 3 do2 do1 do0 ad5 ad4 ad 3 ad2 ad1 ad0 m s am101 3 0v1 c s s pc s di s do rw do7do6do5do4do 3 do 2 do 1 do 0 ad5 ad4 ad 3 ad2 ad1 ad0 do 15 do 14 do 1 3 do 12 do 11 do 10 d o9 d o 8 m s am101 3 1v1
LSM330DLC digital interfaces doc id 022162 rev 2 37/66 6.2.2 spi write figure 17. spi write protocol the spi write command is performed with 16 clock pulses. a multiple-byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0, do not increment address; when 1, increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that will be written to the device (msb first). bit 16-... : data di(...-8). further data in multiple-byte writing. figure 18. multiple bytes spi write protocol (2 bytes example) 6.2.3 spi read in 3-wire mode 3-wire mode is entered by setting the sim bit to ?1? (spi serial interface mode selection) in the ctrl_reg4_g register . c s s pc s di rw di7 di6 di5 di4 di 3 di 2 di 1 di 0 ad5 ad 4 ad 3 ad2 ad 1 ad0 m s am101 3 2v1 c s s pc s di rw ad5 ad4 ad 3 ad2 ad1 ad 0 di 7 d i6 di 5 d i4 di 3 di 2 di 1 di 0 di 15 d i1 4 di 1 3 di12 di 11 di 10 di 9 di 8 m s am101 33 v1
digital interfaces LSM330DLC 38/66 doc id 022162 rev 2 figure 19. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, do not increment address; when 1, increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). multiple read command is also available in 3-wire mode. c s s pc s di/o rw do7 do6 do5 do4 do 3 do 2 do 1 do 0 ad5 ad 4 ad 3 ad2 ad1 ad 0 m s am101 3 4v1
LSM330DLC register mapping doc id 022162 rev 2 39/66 7 register mapping the table below provides a listing of the 8-bit registers embedded in the device, and their related addresses: table 18. register address map name slave address type register address default comment hex binary reserved (do not modify) ta b l e 1 6 00 - 1f reserved ctrl_reg1_a ta b l e 1 6 rw 20 010 0000 00000111 ctrl_reg2_a ta b l e 1 6 rw 21 010 0001 00000000 ctrl_reg3_a ta b l e 1 6 rw 22 010 0010 00000000 ctrl_reg4_a ta b l e 1 6 rw 23 010 0011 00000000 ctrl_reg5_a ta b l e 1 6 rw 24 010 0100 00000000 ctrl_reg6_a ta b l e 1 6 rw 25 010 0101 00000000 reference_a ta b l e 1 6 rw 26 010 0110 00000000 status_reg_a ta b l e 1 6 r 27 010 0111 00000000 out_x_l_a ta b l e 1 6 r 28 010 1000 output out_x_h_a ta b l e 1 6 r 29 010 1001 output out_y_l_a ta b l e 1 6 r 2a 010 1010 output out_y_h_a ta b l e 1 6 r 2b 010 1011 output out_z_l_a ta b l e 1 6 r 2c 010 1100 output out_z_h_a ta b l e 1 6 r 2d 010 1101 output fifo_ctrl_reg ta b l e 1 6 rw 2e 010 1110 00000000 fifo_src_reg ta b l e 1 6 r 2f 010 1111 int1_cfg_a ta b l e 1 6 rw 30 011 0000 00000000 int1_source_a ta b l e 1 6 r 31 011 0001 00000000 int1_ths_a ta b l e 1 6 rw 32 011 0010 00000000 int1_duration_a ta b l e 1 6 rw 33 011 0011 00000000 int2_cfg_a ta b l e 1 6 rw 34 011 0100 00000000 int2_source_a ta b l e 1 6 r 35 011 0101 00000000 int2_ths_a ta b l e 1 6 rw 36 011 0110 00000000 int2_duration_a ta b l e 1 6 rw 37 011 0111 00000000 click_cfg_a ta b l e 1 6 rw 38 011 1000 00000000 click_src_a ta b l e 1 6 rw 39 011 1001 00000000 click_ths_a ta b l e 1 6 rw 3a 011 1010 00000000 time_limit_a ta b l e 1 6 rw 3b 011 1011 00000000
register mapping LSM330DLC 40/66 doc id 022162 rev 2 time_latency_a ta b l e 1 6 rw 3c 011 1100 00000000 time_window_a ta b l e 1 6 rw 3d 011 1101 00000000 act_ths ta b l e 1 6 rw 3e 011 1110 00000000 act_dur ta b l e 1 6 rw 3f 011 1111 00000000 reserved ta b l e 1 7 - 00-1e - - reserved who_am_i_g ta b l e 1 7 rw 0f 0001111 11010100 reserved ta b l e 1 7 rw 10-1f - - ctrl_reg1_g ta b l e 1 7 rw 20 010 0000 00000111 ctrl_reg2_g ta b l e 1 7 rw 21 010 0001 00000000 ctrl_reg3_g ta b l e 1 7 rw 22 010 0010 00000000 ctrl_reg4_g ta b l e 1 7 rw 23 010 0011 00000000 ctrl_reg5_g ta b l e 1 7 r 24 010 0100 00000000 reference_g ta b l e 1 7 r 25 010 0101 00000000 out_temp_g ta b l e 1 7 r 26 010 0110 output status_reg_g ta b l e 1 7 r 27 010 0111 output out_x_l_g ta b l e 1 7 r 28 010 1000 output out_x_h_g ta b l e 1 7 r 29 010 1001 output out_y_l_g ta b l e 1 7 r 2a 010 1010 output out_y_h_g ta b l e 1 7 r 2b 010 1011 output out_z_l_g ta b l e 1 7 rw 2c 010 1100 output out_z_h_g ta b l e 1 7 r 2d 010 1101 output fifo_ctrl_reg_g ta b l e 1 7 rw 2e 010 1110 00000000 fifo_src_reg_g ta b l e 1 7 r 2f 010 1111 output int1_cfg_g ta b l e 1 7 rw 30 011 0001 output int1_src_g ta b l e 1 7 rw 31 011 0001 output int1_tsh_xh_g ta b l e 1 7 rw 32 011 0010 00000000 int1_tsh_xl_g ta b l e 1 7 rw 33 011 0011 00000000 int1_tsh_yh_g ta b l e 1 7 rw 34 011 0100 00000000 int1_tsh_yl_g ta b l e 1 7 rw 35 011 0101 00000000 int1_tsh_zh_g ta b l e 1 7 rw 36 011 0110 00000000 int1_tsh_zl_g ta b l e 1 7 rw 37 011 0111 00000000 int1_duration_g ta b l e 1 7 rw 38 011 1000 00000000 table 18. register address map (continued) name slave address type register address default comment hex binary
LSM330DLC register mapping doc id 022162 rev 2 41/66 registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up.
register descriptions LSM330DLC 42/66 doc id 022162 rev 2 8 register descriptions the device contains a set of registers which are used to control its behavior and to retrieve acceleration, angular rate and temperature data. the register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface. 8.1 ctrl_reg1_a (20h) odr<3:0> is used to set the power mode and odr selection. ta b l e 2 1 below provides all the frequencies resulting from the odr<3:0> combinations. table 19. ctrl_reg1_a register odr3 odr2 odr1 odr0 lpen zen yen xen table 20. ctrl_reg1_a description odr3-0 data rate selection. default value: 0 (0000: power-down; others: refer to ta bl e 2 1 , ?data rate configuration?) lpen low power mode enable. default value: 0 (0: normal mode, 1: low power mode) zen z axis enable. default value: 1 (0: z axis disabled; 1: z axis enabled) ye n y axis enable. default value: 1 (0: y axis disabled; 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled; 1: x axis enabled) table 21. data rate configuration odr3 odr2 odr1 odr0 power mode selection 0000power-down mode 0001normal / low power mode (1 hz) 0010normal / low power mode (10 hz) 0011normal / low power mode (25 hz) 0100normal / low power mode (50 hz) 0101normal / low power mode (100 hz) 0110normal / low power mode (200 hz) 0111normal / low power mode (400 hz) 1000low power mode (1.620 khz) 1001normal (1.344 khz) / low power mode (5.376 khz)
LSM330DLC register descriptions doc id 022162 rev 2 43/66 8.2 ctrl_reg2_a (21h) 8.3 ctrl_reg3_a (22h) table 22. ctrl_reg2_a register hpm1 hpm0 hpcf2 hpcf1 fds hpclick hpis2 hpis1 table 23. ctrl_reg2_a description hpm1 -hpm0 high-pass filter mode selection. default value: 00 refer to ta bl e 2 4 , ? high pass filter mode configuration? hpcf2 - hpcf1 high-pass filter cut-off frequency selection fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register and fifo) hpclick high-pass filter enabled for click function. (0: filter bypassed; 1: filter enabled) hpis2 high-pass filter enabled for aoi function on interrupt 2, (0: filter bypassed; 1: filter enabled) hpis1 high-pass filter enabled for aoi function on interrupt 1, (0: filter bypassed; 1: filter enabled) table 24. high-pass filter mode configuration hpm1 hpm0 high-pass filter mode 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference signal for filtering 1 0 normal mode 1 1 autoreset on interrupt event table 25. ctrl_reg3_a register i1_click i1_aoi1 0 (1) 1. this bit has to be set ?0? for correct operation i1_drdy1 i1_drdy2 i1_wtm i1_overrun -- table 26. ctrl_reg3_a description i1_click click interrupt on int1_a. default value 0. (0: disable; 1: enable) i1_aoi1 aoi1 interrupt on int1_a. default value 0. (0: disable; 1: enable)
register descriptions LSM330DLC 44/66 doc id 022162 rev 2 8.4 ctrl_reg4_a (23h) 8.5 ctrl_reg5_a (24h) i1_drdy1 drdy1 interrupt on int1_a. default value 0. (0: disable; 1: enable) i1_drdy2 drdy2 interrupt on int1_a. default value 0. (0: disable; 1: enable) i1_wtm fifo watermark interrupt on int1_a. default value 0. (0: disable; 1: enable) i1_overrun fifo overrun interrupt on int1_a. default value 0. (0: disable; 1: enable) table 26. ctrl_reg3_a description (continued) table 27. ctrl_reg4_a register 0 (1) 1. this bit must be set to ?0? for correct operation. ble fs1 fs0 hr 0 (1) 0 (1) sim table 28. ctrl_reg4_a description ble big/little endian data selection. default value 0. (0: data lsb @ lower address; 1: data msb @ lower address) fs1-fs0 full scale selection. default value: 00 (00: +/- 2g; 01: +/- 4g; 10: +/- 8g; 11: +/- 16g) hr high resolution output mode: default value: 0 (0: high resolution disable; 1: high resolution enable) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface). table 29. ctrl_reg5_a register boot fifo_en -- -- lir_int1 d4d_int1 0 (1) 1. this bit must be set to ?0? for correct operation. 0 (1) table 30. ctrl_reg5_a description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) fifo_en fifo enable. default value: 0 (0: fifo disable; 1: fifo enable)
LSM330DLC register descriptions doc id 022162 rev 2 45/66 8.6 ctrl_reg6_a (25h) 8.7 reference/datacapture_a (26h) 8.8 status_reg_a (27h) lir_int1 latch interrupt request on int1_src register, with int1_src register cleared by reading int1_src itself. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) d4d_int1 4d enable: 4d detection is enabled on int1 when 6d bit on int1_cfg is set to 1. table 30. ctrl_reg5_a description (continued) table 31. ctrl_reg6_a register i2_clicken i2_int1 0 (1) 1. this bit must be set to ?0? for correct operation. boot_i2 0 (1) -- h_lactive -- table 32. ctrl_reg6 description i2_clicken click interrupt on int2_a. default value 0. i2_int1 interrupt 1 function enabled on int2_a. default 0. boot_i2 boot on int2_a. h_lactive 0: interrupt active high; 1: interrupt active low. table 33. reference_a register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 34. reference register description ref 7-ref0 reference value for interrupt generation. default value: 0 table 35. status_reg_a register zyxor zor yor xor zyxda zda yda xda table 36. status_reg_a register description zyxor x, y and z axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous data) zor z axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis has overwritten the previous data)
register descriptions LSM330DLC 46/66 doc id 022162 rev 2 8.9 out_x_l_a, out_x_h_a x-axis acceleration data. the value is expressed in two?s complement. 8.10 out_y_l_a, out_y_h_a y-axis acceleration data. the value is expressed in two?s complement. 8.11 out_z_l _a, out_z_h_a z-axis acceleration data. the value is expressed in two?s complement. 8.12 fifo_ctrl_reg_a (2eh) yor y axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xor x axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x, y and z axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) table 36. status_reg_a register description (continued) table 37. fifo_ctrl_reg_a register fm1 fm0 tr fth4 fth3 fth2 fth1 fth0 table 38. fifo_ctrl_reg_a register description fm1-fm0 fifo mode selection. default value: 00 (see table 39: fifo mode configuration ) tr trigger selection. default value: 0 0: trigger event linked to trigger signal on int1_a 1: trigger event linked to trigger signal on int2_a fth4:0 default value: 0
LSM330DLC register descriptions doc id 022162 rev 2 47/66 8.13 fifo_src_reg_a (2fh) 8.14 int1_cfg_a (30h) table 39. fifo mode configuration fm1 fm0 fifo mode 0 0 bypass mode 01fifo mode 1 0 stream mode 1 1 trigger mode table 40. fifo_src_reg_a register wtm ovrn_fifo empty fss4 fss3 fss2 fss1 fss0 table 41. fifo_src_reg_a description wtm wtm bit is set high when fifo content exceeds watermark level ovrn_fifo ovrn bit is set high when fifo buffer is full, this means that the fifo buffer contains 32 unread samples. at the following odr a new sample set replaces the oldest fifo value. the ovrn bit is reset when the first sample set has been read empty empty flag is set high when all fifo samples have been read and fifo is empty fss4-0 fss[4:0] field always contains the current number of unread samples stored in the fifo buffer. when fifo is enabled, this value increases at odr frequency until the buffer is full, whereas, it decreases every time that one sample set is retrieved from fifo table 42. int1_cfg_a register aoi 6d zhie/ zupe zlie/ zdowne yhie/ yupe ylie/ ydowne xhie/ xupe xlie/ xdowne table 43. int1_cfg_a description aoi and/or combination of interrupt events. default value: 0. refer to table 44: inter- rupt mode , ?interrupt mode? 6d 6 direction detection function enabled. default value: 0. refer to table 44: interrupt mode zhie/ zupe enable interrupt generation on z high event or on direction recognition. default value: 0 (0: disable interrupt request;1: enable interrupt request) zlie/ zdowne enable interrupt generation on z low event or on direction recognition. default value: 0 (0: disable interrupt request;1: enable interrupt request)
register descriptions LSM330DLC 48/66 doc id 022162 rev 2 the content of this register is loaded at boot. a write operation at this address is possible only after system boot. . the difference between aoi-6d = ?01? and aoi-6d = ?11?. aoi-6d = ?01? is movement recognition. an interrupt is generated when the orientation moves from ?unknown zone? to ?known zone?. the interrupt signal remains for an odr duration. aoi-6d = ?11? is direction recognition. an interrupt is generated when the orientation is inside a ?known zone?. the interrupt signal remains until orientation is within the zone. 8.15 int1_src_a (31h) yhie/ yupe enable interrupt generation on y high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) ylie/ ydowne enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) xhie/ xupe enable interrupt generation on x high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) xlie/xdowne enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) table 44. interrupt mode aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6 direction movement recognition 1 0 and combination of interrupt events 1 1 6 direction position recognition table 43. int1_cfg_a description (continued) table 45. int1_src_a register 0 (1) 1. this bit must be set to ?0? for correct operation. ia zh zl yh yl xh xl table 46. int1_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred)
LSM330DLC register descriptions doc id 022162 rev 2 49/66 interrupt 1 source register. read only register. reading at this address clears int1_src_a ia bit (and the interrupt signal on int 1 pin) and allows the refreshing of the data in the int1_src_a register if the latched option was chosen. 8.16 int1_ths_a (32h) 8.17 int1_duration_a (33h) d6 - d0 bits set the minimum duration of the interrupt 1 event to be recognized. duration steps and maximum values depend on the odr chosen. yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 46. int1_src_a description (continued) table 47. int1_ths_a register 0 (1) 1. this bit has to be set ?0? for correct operation. ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 48. int1_ths_a description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 49. int1_duration_aregister 0 (1) 1. this bit must be set ?0? for correct operation. d6 d5 d4 d3 d2 d1 d0 table 50. int1_duration_a description d6 - d0 duration value. default value: 000 0000
register descriptions LSM330DLC 50/66 doc id 022162 rev 2 8.18 click_cfg _a (38h) 8.19 click_src_a (39h) table 51. click_cfg_a register -- -- zd zs yd ys xd xs table 52. click_cfg_a description zd enable interrupt double click on z axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zs enable interrupt single click on z axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) yd enable interrupt double click on y axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ys enable interrupt single click on y axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xd enable interrupt double click on x axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xs enable interrupt single click on x axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) table 53. click_src_a register -- ia dclick sclick sign z y x table 54. click_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) dclick double click-click enable. default value: 0 (0:double click-click detection dis- able, 1: double click-click detection enable) sclick single click-click enable. default value: 0 (0:single click-click detection dis- able, 1: single click-click detection enable) sign click-click sign. 0: positive detection, 1: negative detection z z click-click detection. default value: 0 (0: no interrupt, 1: z high event has occurred)
LSM330DLC register descriptions doc id 022162 rev 2 51/66 8.20 click_ths_a (3ah) 8.21 time_limit_a (3bh) 8.22 time_latency_a (3ch) 8.23 time window_a (3dh) y y click-click detection. default value: 0 (0: no interrupt, 1: y high event has occurred) x x click-click detection. default value: 0 (0: no interrupt, 1: x high event has occurred) table 54. click_src_a description table 55. click_ths_a register -- ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 56. click_src_a description ths6-ths0 click-click threshold. default value: 000 0000 table 57. time_limit_a register -- tli6 tli5 tli4 tli3 tli2 tli1 tli0 table 58. time_limit_a description tli7-tli0 click-click time limit. default value: 000 0000 table 59. time_latency_a register tla7 tla6 tla5 tla4 tla3 tla2 tla1 tla0 table 60. time_latency_a description tla7-tla0 click-click time latency. default value: 000 0000 table 61. time_window_a register tw7 tw6 tw5 tw4 tw3 tw2 tw1 tw0
register descriptions LSM330DLC 52/66 doc id 022162 rev 2 8.24 act_ths (3eh) 8.25 act_dur (3fh) 8.26 who_am_i_g (0fh) device identification register. 8.27 ctrl_reg1_g (20h) table 62. time_window_a description tw7-tw0 click-click time window table 63. act_ths register -- acth6 acth5 acth4 acth3 acth2 acth1 acth0 table 64. act_ths description acth[6-0] sleep-to-wake, return to sleep activation threshold 1lsb = 16m g table 65. act_dur register actd7 actd6 actd5 actd4 actd3 actd2 actd1 actd0 table 66. act_dur description actd[7-0] sleep-to-wake, return to sleep duration dur = (act_dur + 1)*8/odr table 67. who_am_i_g register 11010100 table 68. ctrl_reg1_g register dr1 dr0 bw1 bw0 pd zen xen yen table 69. ctrl_reg1_g description dr1-dr0 output data rate selection. refer to ta bl e 7 0 bw1-bw0 bandwidth selection. refer to ta bl e 7 0
LSM330DLC register descriptions doc id 022162 rev 2 53/66 dr<1:0> is used to set odr selection. bw <1:0> is used to set bandwidth selection. ta b l e 7 0 below provides all the frequencies resulting from the dr / bw bit combinations. the combination of pd, zen, yen, xen is used to set the device in different modes (power- down / normal / sleep mode) according to the following table: pd power-down mode enable. default value: 0 (0: power-down mode, 1: normal mode or sleep mode) zen z axis enable. default value: 1 (0: z axis disabled; 1: z axis enabled) yen y axis enable. default value: 1 (0: y axis disabled; 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled; 1: x axis enabled) table 70. dr and bw configuration setting dr <1:0> bw <1:0> odr [hz] cut-off 00 00 95 12.5 00 01 95 25 00 10 95 25 00 11 95 25 01 00 190 12.5 01 01 190 25 01 10 190 50 01 11 190 70 10 00 380 20 10 01 380 25 10 10 380 50 10 11 380 100 11 00 760 30 11 01 760 35 11 10 760 50 11 11 760 100 table 71. power mode selection configuration mode pd zen yen xen power-down 0 - - - table 69. ctrl_reg1_g description
register descriptions LSM330DLC 54/66 doc id 022162 rev 2 8.28 ctrl_reg2_g (21h) sleep1000 normal1--- table 71. power mode selection configuration table 72. ctrl_reg2_g register extren lvlen hpm1 hpm1 hpcf3 hpcf2 hpcf1 hpcf0 table 73. ctrl_reg2_g description extren edge-sensitive trigger enable: default value: 0 (0: external trigger disabled; 1: external trigger enabled) lv le n level-sensitive trigger enable: default value: 0 (0: level sensitive trigger disabled; 1: level sensitive trigger enabled) hpm1- hpm0 high-pass filter mode selection. default value: 00 refer to ta bl e 7 4 hpcf3- hpcf0 high-pass filter cut-off frequency selection refer to ta bl e 7 5 table 74. high-pass filter mode configuration hpm1 hpm0 high-pass filter mode 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference signal for filtering 1 0 normal mode 1 1 autoreset on interrupt event table 75. high-pass filter cut-off frequency configuration [hz] hpcf3-0 odr=95 hz odr=190 hz odr=380 hz odr=760 hz 0000 7.2 13.5 27 51.4 0001 3.5 7.2 13.5 27 0010 1.8 3.5 7.2 13.5 0011 0.9 1.8 3.5 7.2 0100 0.45 0.9 1.8 3.5 0101 0.18 0.45 0.9 1.8 0110 0.09 0.18 0.45 0.9 0111 0.045 0.09 0.18 0.45
LSM330DLC register descriptions doc id 022162 rev 2 55/66 8.29 ctrl_reg3_g (22h) 8.30 ctrl_reg4_g (23h) 1000 0.018 0.045 0.09 0.18 1001 0.009 0.018 0.045 0.09 table 75. high-pass filter cut-off frequency configuration [hz] (continued) table 76. ctrl_reg3_g register i1_int1 i1_boot h_lactive pp_od i2_drdy i2_wtm i2_orun i2_empty table 77. ctrl_reg3_g description i1_int1 interrupt enable on int1_g pin. default value 0. (0: disable; 1: enable) i1_boot boot status available on int1_g. default value 0. (0: disable; 1: enable) h_lactive interrupt active configuration on int1_g. default value 0. (0: high; 1:low) pp_od push-pull / open drain. default value: 0. (0: push-pull; 1: open drain) i2_drdy date ready on drdy_g/int2_g. default value 0. (0: disable; 1: enable) i2_wtm fifo watermark interrupt on drdy_g/int2_g. default value: 0. (0: disable; 1: ena- ble) i2_orun fifo overrun interrupt on drdy_g/int2_g default value: 0. (0: disable; 1: enable) i2_empty fifo empty interrupt on drdy_g/int2_g. default value: 0. (0: disable; 1: enable) table 78. ctrl_reg4_g register bdu ble fs1 fs0 - 0 0 sim table 79. ctrl_reg4_g description bdu block data update. default value: 0 (0: continuous update; 1: output registers not updated until msb and lsb reading) ble big/little endian data selection. default value 0. (0: data lsb @ lower address; 1: data msb @ lower address) fs1-fs0 full scale selection. default value: 00 (00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps) sim 3-wire spi serial interface read mode enable. default value: 0 (0: 3-wire read mode disabled; 1: 3-wire read enabled).
register descriptions LSM330DLC 56/66 doc id 022162 rev 2 8.31 ctrl_reg5_g (24h) figure 20. int1_sel and out_sel configuration block diagram 8.32 reference_g (25h) table 80. ctrl_reg5_g register boot fifo_en -- hpen int1_sel1 int1_sel0 out_sel1 out_sel0 table 81. ctrl_reg5_g description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) fifo_en fifo enable. default value: 0 (0: fifo disable; 1: fifo enable) hpen high-pass filter enable. default value: 0 (0: hpf disabled; 1: hpf enabled, see figure 20 ) int1_sel1- int1_sel0 int1 selection configuration. default value: 0 (see figure 20 ) out_sel1- out_sel1 out selection configuration. default value: 0 (see figure 20 ) adc lpf1 hpf 0 1 hpen lpf2 10 11 01 00 o u t_ s el <1:0> d a t a reg fifo 3 2x16x 3 00 11 10 01 interr u pt gener a tor int1_ s el <1:0> am07949v2 table 82. reference_g register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 83. reference_g register description ref 7-ref0 reference value for interrupt generation. default value: 0
LSM330DLC register descriptions doc id 022162 rev 2 57/66 8.33 out_temp_g (26h) 8.34 status_reg_g (27h) 8.35 out_x_l_g, out_x_h_g x-axis angular rate data. the value is expressed as two?s complement. 8.36 out_y_l_g, out_y_h_g y-axis angular rate data. the value is expressed as two?s complement. table 84. out_temp_g register temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0 table 85. out_temp_g register description temp7-temp0 temperature data (1lsb/deg - 8-bit resolution). the value is expressed as two?s complement. table 86. status_reg_g register zyxor zor yor xor zyxda zda yda xda table 87. status_reg description zyxor x, y, z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data has overwritten the previous data before it was read) zor z axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis has overwritten the previous data) yor y axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xor x axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x, y, z -axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y axis new data available. default value: 0 (0: new data for the y-axis is not yet available;1: new data for the y-axis is available) xda x axis new data available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available)
register descriptions LSM330DLC 58/66 doc id 022162 rev 2 8.37 out_z_l_g, out_z_h_g z-axis angular rate data. the value is expressed as two?s complement. 8.38 fifo_ctrl_reg_g (2eh) 8.39 fifo_src_reg_g (2fh) table 88. fifo_ctrl_reg_g register fm2 fm1 fm0 wtm4 wtm3 wtm2 wtm1 wtm0 table 89. fifo_ctrl_reg_g description fm2-fm0 fifo mode selection. default value: 00 (see ta b l e 9 0 ) wtm4-wtm0 fifo threshold. watermark level setting table 90. fifo mode configuration fm2 fm1 fm0 fifo mode 000bypass mode 001fifo mode 010stream mode 011stream-to-fifo mode 100bypass-to-stream mode table 91. fifo_src_reg_g register wtm ovrn empty fss4 fss3 fss2 fss1 fss0 table 92. fifo_src_reg_g description wtm watermark status. (0: fifo filling is lower than wtm level; 1: fifo filling is equal or higher than wtm level) ovrn overrun bit status. (0: fifo is not completely filled; 1:fifo is completely filled) empty fifo empty bit. (0: fifo not empty; 1: fifo empty) fss4-fss1 fifo stored data level
LSM330DLC register descriptions doc id 022162 rev 2 59/66 8.40 int1_cfg_g (30h) configuration register for interrupt source. 8.41 int1_src_g (31h) table 93. int1_cfg_g register and/or lir zhie zlie yhie ylie xhie xlie table 94. int1_cfg_g description and/or and/or combination of interrupt events. default value: 0 (0: or combination of interrupt events 1: and combination of interrupt events lir latch interrupt request. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) cleared by reading int1_src_g reg. zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured value lower than preset threshold) table 95. int1_src_g register 0 ia zhzlyhylxhxl table 96. int1_src_g description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred)
register descriptions LSM330DLC 60/66 doc id 022162 rev 2 interrupt source register. read only register. reading at this address clears the int1_src_g ia bit (and eventually the interrupt signal on the int1_g pin) and allows the refreshing of data in the int1_src_g register if the latched option was chosen. 8.42 int1_ths_xh_g (32h) 8.43 int1_ths_xl_g (33h) 8.44 int1_ths_yh _g (34h) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 96. int1_src_g description table 97. int1_ths_xh_g register - thsx14 thsx13 thsx12 thsx11 thsx10 thsx9 thsx8 table 98. int1_ths_xh_g description thsx14 - thsx9 interrupt threshold. default value: 0000 0000 table 99. int1_ths_xl_g register thsx7 thsx6 thsx5 thsx4 thsx3 thsx2 thsx1 thsx0 table 100. int1_ths_xl_g description thsx7 - thsx0 interrupt threshold. default value: 0000 0000 table 101. int1_ths_yh_g register - thsy14 thsy13 thsy12 thsy11 thsy10 thsy9 thsy8 table 102. int1_ths_yh_g description thsy14 - thsy9 interrupt threshold. default value: 0000 0000
LSM330DLC register descriptions doc id 022162 rev 2 61/66 8.45 int1_ths_yl_g (35h) 8.46 int1_ths_zh_g (36h) 8.47 int1_ths_zl_g (37h) 8.48 int1_duration_g (38h) d6 - d0 bits set the minimum duration of the interrupt event to be recognized. duration steps and maximum values depend on the odr chosen. table 103. int1_ths_yl_g register thsr7 thsy6 thsy5 thsy4 thsy3 thsy2 thsy1 thsy0 table 104. int1_ths_yl_g description thsy7 - thsy0 interrupt threshold. default value: 0000 0000 table 105. int1_ths_zh_g register - thsz14 thsz13 thsz12 thsz11 thsz10 thsz9 thsz8 table 106. int1_ths_zh_g description thsz14 - thsz9 interrupt threshold. default value: 0000 0000 table 107. int1_ths_zl_g register thsz7 thsz6 thsz5 thsz4 thsz3 thsz2 thsz1 thsz0 table 108. int1_ths_zl_g description thsz7 - thsz0 interrupt threshold. default value: 0000 0000 table 109. int1_duration_g register wait d6 d5 d4 d3 d2 d1 d0 table 110. int1_duration_g description wait wait enable. default value: 0 (0: disable; 1: enable) d6 - d0 duration value. default value: 000 0000
register descriptions LSM330DLC 62/66 doc id 022162 rev 2 wait bit has the following meaning: wait =?0?: the interrupt falls immediately if signal crosses the selected threshold wait =?1?: if the signal crosses the selected threshold, the interrupt falls only after the duration has counted the number of samples at the selected data rate, written into the duration counter register. figure 21. wait disabled
LSM330DLC register descriptions doc id 022162 rev 2 63/66 figure 22. wait enabled
package information LSM330DLC 64/66 doc id 022162 rev 2 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. figure 23. lga-28 (4x5x1.1 mm): mechanical data and package dimensions dimensions ref. mm min. typ. max. a1 1.1 a2 0. 8 55 a 3 0.200 d1 3 . 8 50 4.000 4.150 e1 4. 8 50 5.000 5.150 l1 3 .75 l2 2.75 n1 0.500 m0.075 p1 2.200 p2 1.700 t1 0.265 0. 3 25 0. 38 5 t2 0.1 9 0.250 0. 3 10 d0.200 k0.050 h0.100 lga-2 8 (4x5x1.1mm) land grid array packa g e outline and 8 1 8 1 393 a mechanical data
LSM330DLC revision history doc id 022162 rev 2 65/66 10 revision history table 111. document revision history date revision changes 02-sep-2011 1 initial release. 17-sep-2012 2 updated table 3: mechanical characteristics : zero-rate level change vs. temperature. document status promoted from preliminary data to datasheet.
LSM330DLC 66/66 doc id 022162 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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