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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xrt83d10 single channel ds1/cept line interface unit july 2004 rev. 1.0.3 general description the xrt83d10 is a fully integrated, single channel, line interface unit (transceiver) for 75 ? or 120 ? e1 (2.048 mbps) and 100 ? ds1 (1.544 mbps) applications. the liu consists of a receiver with adaptive data slicer for accurate data and clock recovery and a transmitter which accepts dual-rail digital inputs for signal transmission to the line using a low- impedance differential line driver. the liu also includes a crystal-less jitter attenuator for clock and data smoothing which, depending on system requirements, can be selected in either the transmit or receive path. the xrt83d10 uses the transformer coupling on both the receiver and transmitter sides, and supports both 120 ? balanced,75 ? unbalanced and 100 ? interfaces. features ? complete e1 (cept) and ds1 line interface unit ? generates transmit output pulses that are compli- ant with the itu-t g.703 pulse template for 2.048mbps (e1) rates ? on-chip pulse shaping for both 75 ? , 120 ? and 100 ? line drivers ? clock recovery and select able crystal-less jitter attenuator ? compliant with ets3 00166 return loss ? compliant with the itu-t g.823 jitter tolerance requirements ? remote, local and digital loop backs ? declares and clears los per itu-t g.775 ? - 40 c to 85 c temperature range ? l ow power dissipation ? +5v or +3.3v supply operation ? pin compatible with agere t7290a and t5290a applications ? pdh multiplexers ? sdh multiplexers ? digital cross-connect systems ? dect (digital european co rdless telephone) base stations ? csu/dsu equipment f igure 1. b lock d iagram of the xrt83d10 exclk taos ec1 ec2 ec3 mode1 mode2 loopa loopb cs v dda , gnd a v ddd , gnd d peak detector data slicer data & timing recovery timing generator dlos jitter attenuator digital loopback lp3 local loopback lp1 transmit monitor loss of clock pulse equalizer remote looback lp2 taos tx line driver mode2 taos + clklos 2 exclk ja clock tsc 2 2 2 2 2 2 2 2 exclk local remote digital taos ec1 ec2 ec3 mode1 mode2 4 decode rlos exclk rpdata rndata rclk fofs tpdata tndata tclk transmit data receive data alos sclk dlos ict p interface mode1 mode2 rtip rring ttip tring
xrt83d10 xr rev. 1.0.3 single channel ds1/cept line interface unit 2 product ordering information p roduct n umber p ackage t ype o perating t emperature r ange XRT83D10IW 28 lead 300 mil jedec soj -40c to +85c f igure 2. p in o ut of the xrt83d10 ec1 ict avdd agnd rring rtip mode2 mode1 loopb loopa taos rlos fofs clklos ec2 ec3 dgnd tring dvdd ttip rndata rpdata rclk tndata tpdata tclk exclk cs 1 2 9 13 12 11 10 8 7 6 5 4 3 14 28 27 20 16 17 18 19 21 22 23 24 25 26 15
xr xrt83d10 single channel ds1/cept line interface unit rev. 1.0.3 3 pin descriptions microprocessor p in #n ame t ype d escription 15 cs i microprocessor interface select (active low) cs loads the data into the device on its falling edge and latches the data on its rising edge. for hardware mode, cs is left open or connected to gnd. n ote : internally pulled down 1ec1 i transmit equalization control. the three inputs, ec1,ec2 and ec3 are used for selecting transmit equaliza- tion. n ote : internally pulled down. 27 ec3 i transmit equalization control n ote : internally pulled down. 28 ec2 i transmit equalization control n ote : internally pulled down. 7mode2 i mode select mode 1 and mode 2 select the clock and data paths through the jitter attenua- tor. n ote : internally pulled down. 8mode1 i mode select n ote : internally pulled down. 9loopb i loopback control. loopb along with loopa are used for selecting different loopbacks. n ote : internally pulled down. 10 loopa i loopback control. loopb along with loopa are used for selecting different loopbacks. n ote : internally pulled down. loopa 0 0 loopback mode normal operation digital loopb 0 1 1 1 remote local 0 1
xrt83d10 xr rev. 1.0.3 single channel ds1/cept line interface unit 4 receiver section p in #n ame t ype d escription 6rtip i receive positive bipolar data input 5rring i receive negative bipolar data input 20 rclk o receive clock output recovered receive clock for the terminal equipment. 21 rpdata o receive positive nrz data: recovered positive data ds1 (1.544mbi ts/s) or cept (2.048 mbits/s) 22 rndata o receive negative data recovered negative nrz data ds1 (1.544m bits/s) or cept (2.048 mbits/s) 12 rlos o receive loss of signal: this pin is set "high" if analog loss-of-sig nal at the receiver input is detected or if digital loss-of-signal of the recovered data is detected.rlos will remain "high" until the loss of signal condition clears. transmitter section p in #n ame t ype d escription 17 tclk i transmit clock ds1 clock signal. (1.544 mhz 130 ppm) or cept clock signal (2.048 mhz 80 ppm). 18 tpdata i transmit positive data ds1 (1.544 mbits/s) or cept (2 .048 mbits/s) positive bipolar data 19 tndata i transmit negative data ds1 (1.544 mbits/s) or cept (2.048 mbits/s) negative bipolar data 23 ttip o transmit tip output positive bipolar transmit data 25 tring o transmit differential ring output negative bipolar transmit data 14 clklos o loss of clock signal: this pin is set "high" when either the transmit clock (tclk) or the clock output from the jitter at tenuator is absent.
xr xrt83d10 single channel ds1/cept line interface unit rev. 1.0.3 5 control function p in #n ame t ype d escription 2ict i in circuit testing when this pin is tied "low" all output pi ns are forced to high-impedance state for in-circuit testing. n ote : internally pulled up. 16 exclk i external clock input: ds1 (1.544 mhz 130 ppm) or cept e1 (2.048 mhz 80 ppm) clock signal is provided. exclk must be an independent clock to guarantee device perfor- mance for all specifications. this clo ck must be continuously active (ungapped or unswitched) and void of jitter for the device to operate properly. 11 taos i transmit all ones: with this pin tied "high", an ami encoded all "1?s" signal sent to the transmit output using exclk as the timing reference. a remote loop back has higher priority over taos request. n ote : internally pulled down. 9loopb i loopback control. loopb along with loopa is used fo r selecting different loopbacks. n ote : internally pulled down. 10 loopa i loopback control. loopb along with loopa is used fo r selecting different loopbacks. n ote : internally pulled down. 13 fofs o fifo overflow signal: this pin is set "high" if the phase jitter of the incoming signal exceeds the toler- ance of the jitter attenuator?s buffer. this may result in loss of data and jitter attenuator is no lon ger attenuating jitter. power and ground p in #n ame t ype d escription 3 avdd **** analog supply: 5v 5% or 3.3v 5% 4 agnd **** analog gnd. 24 dvdd **** digital supply: 5v 5% or 3.3v 5% 26 dgnd **** digital gnd loopa 0 0 loopback mode normal operation digital loopb 0 1 1 1 remote local 0 1
xrt83d10 xr rev. 1.0.3 single channel ds1/cept line interface unit 6 n ote : power consumption measurement conditions wi th 50% 1s on the transmit and receive, ta = 25 0 c, vdd = 5v n otes : 1. measured at 772 khz. 0db is the reference to 3.0vp. 2. measured at 1024 khz (both for 75 ? and 120 ? ). 0db is the reference to 2.37vp (75 ? ) and 3.0vp (120 ? ) t able 1: dc e lectrical c haracteristics ta = -40c to 85c, vdd = 5v 5% or 3.3v 5% unless otherwise specified p arameter s ymbol m in t yp m ax u nit input high voltage v ih 2.0 5.0 5.5 v input low voltage v il 0.5 0 0.8 v output high voltage @ioh=5ma (see note) vdd=5.0v vdd=3.3v v oh 2.4 - vdd v output low voltage @ iol=5ma (see note) vdd=5.0v vdd=3.3v v ol 0 - 0.4 v input leakage current (except input pins with pull-up resistors) i l - 0 10 ua input capacitance c i - 5 20 pf output load capacitance c o - - 20 pf e lectrical c haracteristics - p ower s pecifications p arameter s ymbol min typ max unit power dissipation: with jitter attenuator ds1 (ec1=0,ec2=1,ec3=1) cept (75 ? ) cept (120 ? ) pd 275 275 275 350 350 350 mw mw mw t able 2: r eceiver c haracteristics ta = -40c to 85c, vdd = 5v 5% or 3.3v 5% unless otherwise specified p arameter m in .t yp .m ax u nit receiver sensitivity ds1 1 cept 2 10 9 db recovered clock jitter transfer corner frequency - 20 khz jitter attenuator corner frequency (-3db curve) - 3 hz return loss in e1 (cept) mode 51khz-102khz 102khz-2048khz 2048khz-3072khz 12 18 14 db db db
xr xrt83d10 single channel ds1/cept line interface unit rev. 1.0.3 7 n ote : 1. tolerance of 130 ppm 2. tolerance of 80 ppm. t able 3: t ransmitter c haracteristics ta = -40c to 85c, vdd = 5v 5% or 3.3v 5% unless otherwise specified p arameter m in .t yp .m ax u nit ami output pulse amplitude ds1 (at dsx) 75 ? application 120 ? application 2.4 2.13 2.70 3.0 2.37 3.00 3.6 2.60 3.30 v v v output pulse width ds1 cept 330 224 350 244 370 264 ns ns output power levels: ds1 (2khz band at 772 khz) ds1 (2 khz band at 1544 khz) 12 -29 16.7 -35 17.9 - dbm db output return loss:( cept only) 51khz -102khz 102khz-2048khz 2048khz-3072khz 8 8 8 - - - db db db t able 4: i nterface d ata t iming ( see f igures 3 and 4) ta = -40 to +85 c, vdd = 5v 5% or 3.3v 5% unless otherwise specified p arameter s ymbol m in .t yp m ax u nits transmit clock period ds1 1 cept 2 tclk - 647.7 488 - ns ns tclk duty cycle t clk 40 50 60 % transmit data setup time t tsu 50 - - ns transmit data hold time t tho 40 - - ns tclk rise time (10% /90%) t r -- 40 ns tclk fall time (90% / 10%) t f - - 40 ns receive data setup time t rsu 140 - ns receive data hold time t rho 180 - ns receive propagation delay t pd 40 ns
xrt83d10 xr rev. 1.0.3 single channel ds1/cept line interface unit 8 f igure 3. i nterface t iming d iagram - t ransmit f igure 4. i nterface t iming d iagram - r eceive t f t r t clk tpdata or tndata tclk . t tho t tsu t rho t rsu rpdata or rndata rclk t pd
xr xrt83d10 single channel ds1/cept line interface unit rev. 1.0.3 9 f igure 5. m icroprocessor i nterface t iming t able 5: m icroprocessor i nterface t iming s ymbol p arameter m in m ax u nit t 1 control signal rise time (10% - 90%) 40 ns t 2 control signal rise time (10% - 90%) 40 ns t 3 control signal pulse width time 40 ns t 4 control signal setup time 50 ns t 5 control signal hold time 40 ns t 2 t 4 t 3 cs mode 1 mode 2 ec1 ec2 ec3 loopa llopb t 1 t 5
xrt83d10 xr single channel ds1/cept line interface unit rev. 1.0.3 10 1.0 system description: 1.1 receiver: the xrt83d10, a single channel ds1/cept line interface unit is a fully integrated transceiver that provides an electrical interface for ds1 carrier rate (1.544 mbits/s) or cept rate (2.048 mbits/s) applications.the bipolar input signals at rtip and rring are applied to the peak detector and slicer.timing recovery is performed by the clock and data recovery block. ec1,ec2 and ec3 rate control inputs must be set appropriately for ds1 or cept operation. the digital representation of the ami signals goes to the clock recovery circuit for timing re- covery before being output to the rpdata and rndata pins. clock timing recovery of the line interface is ac- complished by means of a digital pll scheme which has high input jitter tolerance. a continuously active (ungapped or unswitched) reference clock must be present at exclk to enable the timing generator block. exclk must be an independent reference such as an oscillator or system clock for proper operation. the exclk frequency must be 1.544 mhz 130 ppm for ds1 operation or 2.048 mhz 80 ppm for cept operation. any data pattern with a minimum long-term 1s density of 12.5% with 15 or fewer consecutive 0s is allowed. 1.1.1 loss of signal: both digital (dlos) and analog (alos) loss-of-signal de tection are used. the analog signal detector uses the output of the peak detector to determine if a signal is present at rtip and rring. if the input amplitude drops below approximately 0.4 vp, the analog detector becomes active.hysteresis is provided in the analog detector to eliminate alos chattering. either the analog or digital detector sets rlos "high". 1.2 transmitter: the transmitter accepts a clock with positive and negative data (dual-rail nrz format) and converts the signal to a balanced bipolar data signal (ami format). positive 1s are produced by a positive pulse on device pin ttip and negative 1s are produced by a positive pulse on device pin tring. binary 0s are converted to null pulses. all pulse shapes are controlled on-chip according to equalizer control inputs as defined in table 6 below. n otes : 1. * distance to dsx in feet for 22-ga. use maximum loss figures for other cable types. 2. ** db at 772 khz. transmitter specifications are shown in figure 6. the ds1 pulse shape template is specified at the dsx and is illustrated in figure 6.cept transmit waveforms at th e device output conform to the template shown in figure 7. t able 6: e qualizer /r ate c ontrol o peration c lock r ate t ransmitter e qualization * m aximum c able l oss ** ec1 ec2 ec3 ds1 1.544 mhz 0 ft -131 ft 0.6 0 0 1 131 ft - 262 ft 1.2 0 1 0 262 ft - 393 ft 1.8 0 1 1 393 ft - 524 ft 2.4 1 0 0 524 ft - 655 ft 3.0 1 0 1 cept 2.048 mhz 75 ? -110 120 ? -111
xr xrt83d10 single channel ds1/cept line interface unit rev. 1.0.3 11 f igure 6. dsx-1 p ulse t emplate ( normalized amplitude ) t able 7: dsx1 i nterface i solated p ulse m ask per ansi t1.102-1993 and c orner p oint s pecifications m inimum c urve m aximum c urve time (ui) normalized amplitude (v) time (ui) normalized amplitude (v) -0.77 -0.05 -0.77 0.05 -0.23 -0.05 -0.39 0.05 -0.23 0.5 -0.27 0.8 -0.15 0.95 -0.27 1.15 0.0 0.95 -0.12 1.15 0.15 0.9 0.0 1.05 0.23 0.5 0.27 1.05 0.23 -0.45 0.35 -0.07 0.46 -0.45 0.93 0.05 0.66 -0.2 1.16 0.05 0.93 -0.05 1.16 -0.05
xrt83d10 xr single channel ds1/cept line interface unit rev. 1.0.3 12 1.3 jitter attenuator to reduce frequency jitter in the transmit clock or receive clock, a crystal-less jitter attenuator is provided. the jitter attenuator can be selected either in the transmit or receive path or it can be disabled as shown in table 8. 1.3.1 fifo overflow signal (fofs): a fifo overflow signal (fofs = 1) is indicated if the phase jitter exceeds the tolerance of the jitter attenuator. when fofs is "high", jitter attenuator bandwidth is increased to track the short term jitter an d no data error will f igure 7. itu g.703 p ulse t emplate t able 8: j itter a ttenuator s election j itter a ttenuator connectivity m ode 1m ode 2 bypass (disabled) 0 0 tr a n s m i t pa t h 0 1 receive path 1 0 test mode 1 1 10% 10% 10% 10% 10% 10% 269 ns (244 + 25) 194 ns (244?50) 244 ns 219 ns (244 ? 25) 488 ns (244 + 244) 0% 50% 20% v = 100% nominal pulse note ? v corresponds to the nominal peak value. 20% 20%
xr xrt83d10 single channel ds1/cept line interface unit rev. 1.0.3 13 occur.jitter attenuator is no longer attenuating input jitter.(this signal is asserted until normal operation resumes.) 1.4 alarms and maintenance: 1.4.1 loss of signal: a digital loss of signal (dlos =1) is indicated if 17575 or more consecutive 0s occur in the receive data stream during ds1 operation.during cept operation, a dlos is indicated when 32 or more consecutive 0s occur in the receive data stream.dlos is the deactivated when the ones density exceeds 12.5% and there are no more than 100 consecutive 0s for ds1 and 16 consecutive 0s for cept, signifying the return of good signal.dlos deactivation monitors the data in a fixed 32-bit window.each window must have at least four 1s with no more than 15 consecutive 0s. upon dlos detection, rclk is phase-locked to the external clock (exclk) so that other system devices slaved to the line clock continue to operate without instantaneous phase hits or discontinuities. either an analog loss of signal (alos) or a digital loss of signal (dlos) activates the rlos output pin. 1.4.2 loss of clock signal (clklos): a loss of clock signal (clklos =1) is indicated if either the transmit clock (tclk) or the smoothing clock (sclk) output of the jitter attenuator is absent.if the jitter attenuator is placed in the transmit path, the sclk is monitored.if the jitter attenuator is not placed in the transmit path, tclk or remote loopback clock is monitored.for every ten clock periods of the exclk osc illator clock, a strobe is gen erated.if a single transmit clock period occurs between strobes, then clklos = 0. if no transmit clock period occurs between strobes, then clklos = 1 and the output drivers ((ttip and tring) are placed into a high-impedance state and no data is transmitted. 1.4.3 ais (taos) generator: when the transmit all ones (taos = 1) signal is set, a continuous stream of bipolar 1s is transmitted onto the line synchronous with exclk. the tpdata and tndata inputs are ignored during this mode. if the rlos output is externally connected to the taos input, an rlos error initiates a transmit all 1s signal as long as rlos = 1.also, taos input is ignored when a remote loopback is selected. there is no microprocessor input for the taos input, i.e., any change on the taos pin is fed directly into the device and is not impeded by the cs function. 1.5 loopbacks: the xrt83d10 has three independent loopback paths, which are activated as shown in figure 9. n ote : during remote loopback, taos is ignored. a local loopback (lp1) connects the jitter attenuator?s output clock and data to the receive clock and data output pins. mode1:2 = 01 must be selected for this loopback to operate (jitter attenuator in the transmit path). valid transmit output data continues to be sent to the network. however, if the transmit all 1s (taos =1) is t able 9: l oopback c ontrol o peration s ymbol loopa loopb normal - 0 0 digital local loopback lp3 0 1 remote loopback lp2* 1 0 local loopback lp1 1 1
xrt83d10 xr single channel ds1/cept line interface unit rev. 1.0.3 14 initiated, an all 1s signal is sent to the network and does not corrupt the looped data. the rlos alarm still monitors the entire receive function. a remote loopback (lp2) loops the recovered clock and re-timed data into the transmitter and back onto the line. the receive front end, receive pll, jitter attenuator (if enabled), and transmit driver circuitry are all exercised. the transmit clock, transmit data, and taos inputs are ignored. valid receive output data continues to be sent to rpdata and rndata. this loop can be used to isolate failures between systems. a digital local loopback (lp3) directly loops the transmit clock and data to the receive clock and data output pins. the transmit all 1s signal can be transmitted when in this loopback. lp3 (rather than lp1) must be selected if mode2 = 0. 1.6 microprocessor interface: a chip select input (cs ) configures the device in either hardware mode or microprocessor mode. the chip- select function, applies to the following inputs: mode1, mode2,ec1,ec2,ec3,loopa and loopb. in the hardware mode, any change on these asynchronous input pins fed directly into the device.to maintain hardware mode, set cs = 0. in the microprocessor mode, new digital control inputs are loaded into the xrt83d10 on the falling edge of cs and are latched on the rising edge of cs . 1.7 in-circuit testing: the xrt83d10 has the ability to allow for in-circuit testing by activating the high-impedance mode (ict = 0).during this mode, all output buffers (ttip,tr ing,rclk,rpdata,rndata,rlos,fofs and clklos) are 3-stated. during the 3-stated condition, the absolute maximum voltage ratings must not be exceeded on any pin. 1.8 absolute maximum ratings: stresses in excess of absolute maximum ratings can cause permanent or latent damage to the device. these are absolute stress ratings only.functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. n ote : stresses in excess of the absolute maximum ratings can cause permanent damage to the device.the above values are absolute stress ratings only. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. 2.0 applications: 2.1 line termination: for the following applications, the tolerance of all transf ormer turns ratios is a maximum of 2%. the tolerance of all resistors in the transmit path is a maximum of 1%. e lectrical c haracteristics - a bsolute m aximum r atings p arameter s ymbol min max unit dc supply voltage range vdd -0.5 6.5 v storage temperature sto -65 125 degc maximum voltage (any pin) with respect to vdd 0.5 v minimum voltage (any pin) with respect to gnd -0.5 v maximum voltage allowed (rtip,rring) with respect to gnd -5.0 5.0 v esd (human-body model) 2000 v
xr xrt83d10 single channel ds1/cept line interface unit rev. 1.0.3 15 f igure 8. cept a pplication for t wisted - pair i nterface - 5 v or 3.3 v operation . f igure 9. ds1 a pplication for t wisted - pair i nterface - 5 v or 3.3 v operation . 866 ? 866 ? 1 : 2 2.42:1 rtip rring ttip tring +5 v 0.1 f dvdd avdd tpdata tndata tclk rpdata rndata rclk agnd dgnd receive input transmit output 200 ? 120 ? 10 f 9.1 ? 9.1 ? 500 ? 500 ? 1 : 2 2 : 1 rtip rring ttip tring +5 v 1 f dvdd avdd tpdata tndata tclk rpdata rndata rclk agnd dgnd receive input transmit output 200 ? 100 ? 10 f 0.68 f
xrt83d10 xr single channel ds1/cept line interface unit rev. 1.0.3 16 f igure 10. cept a pplication for c oaxial i nterface - 5 v or 3.3 v operation . f igure 11. ds1 a pplication for t wisted - pair interface 5 v or 3.3 v operation 270 ? 270 ? 1 : 2 2.42:1 rtip rring ttip tring +5 v 0.1 f dvdd avdd tpdata tndata tclk rpdata rndata rclk agnd dgnd receive input transmit output 200 ? 75 ? 10 f 6.2 ? 6.2 ? 500 ? 500 ? 1 : 2 2.42:1 rtip rring ttip tring +5 v 1 f dvdd avdd tpdata tndata tclk rpdata rndata rclk agnd dgnd receive input transmit output 200 ? 100 ? 10 f 2 ? 2 ?
xr xrt83d10 single channel ds1/t1/cept line interface unit rev. 1.0.3 17 ordering information package dimensions p roduct n umber p ackage o perating t emperature r ange XRT83D10IW 28 lead 300 mil jedec soj -40 0 c to +85 0 c
xr xrt83d10 single channel ds1/t1/cept line interface unit rev. 1.0.3 18 notice exar corporation reserves the right to make changes to th e products contained in th is publicatio n in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corpor ation is adequately protected under the circumstances. copyright 2003 exar corporation datasheet july 2004. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. revision history r evision #d ate d escription p1.0.0 06/17/03 1st release of the xrt83d10 mkll.0 preliminary data sheet. p1.0.1 7/28/2003 modified the block diagram. added application circuits.corrected the timinga dn elec- trical characteristics. p1.0.2 8/11/2003 for receiver sensitivity, added a note stating that ds1 measured at 772 khz and cept measured at 1024 khz. p1.0.3 8/29/2003 cleaned up the description for the los condition. p1.0.4 12/16/2003 transformer information and resistor values included.rearranged and added informa- tion in the tables. 1.0.0 2/16/2004 the tbd numbers filled in. "preliminary" removed. 1.0.1 3/12/2004 included table 7 1.0.2 5/3/2004 included the power levels for ds1 1.0.3 7/23/2004 included the max power numbers.included figure 11 for ds1 interface

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