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? 2013 microchip technology inc. preliminary ds25002b-page 1 features ? organized as 4m x16 ? single voltage read and write operations - 2.7-3.6v ? superior reliability - endurance: 100,000 cycles minimum - greater than 100 years data retention ? low power consumption (typical values at 5 mhz) - active current: 25 ma (typical) - standby current: 5 a (typical) - auto low power mode: 5 a (typical) ? 128-bit unique id ? security-id feature - 248 word, user one-time-programmable ? protection and security features - hardware boot block protection/wp# input pin, uniform (32 kword), and non-uniform (8 kword) options available - user-controlled individual block (32 kword) pro- tection, using software only methods - password protection ? hardware reset pin (rst#) ? fast read and page read access times: - 70 ns read access time - 25 ns page read access times - 8-word page read buffer ? latched address and data ? fast erase times: - block-erase time: 18 ms (typical) - chip-erase time: 40 ms (typical) ? erase-suspend/-resume capabilities ? fast word and write-buffer programming times: - word-program time: 7 s (typical) - write buffer programming time: 1.75 s / word (typical) - 16-word write buffer ? automatic write timing - internal v pp generation ? end-of-write detection - toggle bits - data# polling - ry/by# output ? cmos i/o compatibility ? jedec standard - flash eeprom pinouts and command sets ?cfi compliant ? packages available - 48-lead tsop - 48-ball tfbga ? all non-pb (lead-free) devices are rohs compliant description the sst38vf6401b, sst38vf6402b, sst38vf6403b, and sst38vf6404b devices are 4m x16 cmos advanced multi-purpose flash plus (advanced mpf+) manufactured with microchip proprietary, high-perfor- mance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reli- ability and manufacturability compared with alternate approaches. the sst38vf6401b/6402b/6403b/6404b write (program or erase) with a 2.7-3.6v power supply. these devices conform to jedec standard pin assign- ments for x16 memories. featuring high performance word-program, the sst38vf6401b/6402b/6403b/6404b provide a typical word-program time of 7 sec. for faster word-pro- gramming performance, the write-buffer programming feature, has a typical word-p rogram time of 1.75 sec. these devices use toggle bit, data# polling, or the ry/ by# pin to indicate program operation completion. in addition to single-word read, advanced mpf+ devices provide a page-read featur e that enables a faster word read time of 25 ns, eight words on the same page. to protect against inadvertent write, the sst38vf6401b/6402b/6403b/6404b have on-chip hardware and software data protection schemes. designed, manufactured, and tested for a wide spec- trum of applications, these devices are available with 100,000 cycles mini mum endurance. da ta retention is rated at greater than 100 years. the sst38vf6401b/6402b/6403b/6404b are suited for applications that require the convenient and economi- cal updating of program, conf iguration, or data mem- ory. for all system applications, advanced mpf+ significantly improve perfor mance and reliability, while lowering power consumption. these devices inherently use less energy during erase and program than alter- native flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. for any given voltage range, the super- flash technology uses less current to program and has sst38vf6401b / sst38vf6402b sst38vf6403b / sst38vf6404b 64 mbit (x16) advanced multi-purpose flash plus
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 2 preliminary ? 2013 microchip technology inc. a shorter erase time; therefore, the total energy con- sumed during any erase or program operation is less than alternative flash technologies. these devices also improve flexibility while lowering the cost for program, data , and configuration storage applications. the superflash technology provides fixed erase and program times, independent of the number of erase/program cycl es that have occurred. therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and pro- gram times increase with accumulated erase/program cycles. the sst38vf6401b/6402b/6403b/6404b also offer flexible data protection features. applications that require memory protection from program and erase operations can use the boot block, individual block protection, and advanced protection features. for applications that require a permanent solution, the irre- versible block locking feature provides permanent protection for memory blocks. to meet high-density, surface mount requirements, the sst38vf6401b/6402b/6403b/6404b devices are offered in 48-lead tsop and 48-ball tfbga packages. see figures 2-1 and 2-2 for pin assignments and ta b l e 2-1 for pin descriptions. 1.0 functional block diagram figure 1-1: functional block diagram y-decoder i/o buffers and data latches 1309 b1.1 address buffer & latches x-decoder dq 15 - dq 0 memory address oe# ce# we# superflash memory control logic wp# rst# ry/by#
? 2013 microchip technology inc. preliminary ds25002b-page 3 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b 2.0 pin assignments figure 2-1: pin assign ments for 48-lead tsop figure 2-2: pin assignments for 48-ball tfbga a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rst# a21 wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 25002 48-tsop p1.0 standard pinout top view die up 25002 48-tfbga p1.0 a b c d e f g h 6 5 4 3 2 1 top view (balls facing down) a13 a9 we# ry/by# a7 a3 a12 a8 rst# wp# a17 a4 a14 a10 a21 a18 a6 a2 a15 a11 a19 a20 a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 4 preliminary ? 2013 microchip technology inc. table 2-1: pin description symbol pin name functions a ms 1 -a 0 address inputs to provide memory addresses. during block-erase a ms -a 15 address lines will select the block. dq 15 -dq 0 data input/output to output data during read cycl es and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-stat e when oe# or ce# is high. wp# write protect to protect th e top/bottom boot block from erase/program operation when grounded. ry/by# ready/busy to indicate when the device is actively programming or erasing. rst# reset to reset and return the device to read mode. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 2.7-3.6v v ss ground nc no connection unconnected pins. 1. a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b
? 2013 microchip technology inc. preliminary ds25002b-page 5 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b 3.0 memory maps table 3-1: sst38vf6401b and sst38vf6402b memory maps sst38vf6401b block 1 1. each block, b0-b127 is 32kword. size address a 21 -a 15 2 2. x = 0 or 1. block address (ba) = a 21 - a 15 vpb 3 3. each block has an associated vpb and nvpb. nvpb 3 wp# 4 4. block b0 is the boot block. b0 4 32 kword 0000000 yes yes yes b1 32 kword 0000001 yes yes no b2 32 kword 0000010 yes yes no b3 32 kword 0000011 yes yes no b4 32 kword 0000100 yes yes no b5 32 kword 0000101 yes yes no b6 32 kword 0000110 yes yes no b7 32 kword 0000111 yes yes no b8 - b119 follow the same pattern b120 32 kword 1111000 yes yes no b121 32 kword 1111001 yes yes no b122 32 kword 1111010 yes yes no b123 32 kword 1111011 yes yes no b124 32 kword 1111100 yes yes no b125 32 kword 1111101 yes yes no b126 32 kword 1111110 yes yes no b127 32 kword 1111111 yes yes no sst38vf6402b block 1 size address a 21 -a 15 2 vpb 3 nvpb 3 wp# 5 5. block b127 is the boot block. b0 32 kword 0000000 yes yes no b1 32 kword 0000001 yes yes no b2 32 kword 0000010 yes yes no b3 32 kword 0000011 yes yes no b4 32 kword 0000100 yes yes no b5 32 kword 0000101 yes yes no b6 32 kword 0000110 yes yes no b7 32 kword 0000111 yes yes no b8 - b119 follow the same pattern b120 32 kword 1111000 yes yes no b121 32 kword 1111001 yes yes no b122 32 kword 1111010 yes yes no b123 32 kword 1111011 yes yes no b124 32 kword 1111100 yes yes no b125 32 kword 1111101 yes yes no b126 32 kword 1111110 yes yes no b127 5 32 kword 1111111 yes yes yes
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 6 preliminary ? 2013 microchip technology inc. table 3-2: sst38vf6403b and sst38vf6404b memory maps (sheet 1 of 2) sst38vf6403b block 1 size address a 21 -a 15 2 vpb 3 nvpb 3 wp# 4 b0 3 , 4 4 kword 0000000000 yes yes yes b1 4 kword 0000000001 yes yes yes b2 4 kword 0000000010 yes yes no b3 4 kword 0000000011 yes yes no b4 4 kword 0000000100 yes yes no b5 4 kword 0000000101 yes yes no b6 4 kword 0000000110 yes yes no b7 4 kword 0000000111 yes yes no b8 32 kword 0000001xxx yes yes no b9 32 kword 0000010xxx yes yes no b10 32 kword 0000011xxx yes yes no b11 32 kword 0000100xxx yes yes no b12 32 kword 0000101xxx yes yes no b13 32 kword 0000110xxx yes yes no b14 32 kword 0000111xxx yes yes no b15 32 kword 0001000xxx yes yes no b16 - b126 follow the same pattern b127 32 kword 1111000xxx yes yes no b128 32 kword 1111001xxx yes yes no b129 32 kword 1111010xxx yes yes no b1230 32 kword 1111011xxx yes yes no b1231 32 kword 1111100xxx yes yes no b1232 32 kword 1111101xxx yes yes no b133 32 kword 1111110xxx yes yes no b134 32 kword 1111111xxx yes yes no sst38vf6404b block 1 size address a 21 -a 15 2 vpb 3 nvpb 3 wp# 5 b0 32 kword 0000000xxx yes yes no b1 32 kword 0000001xxx yes yes no b2 32 kword 0000010xxx yes yes no b3 32 kword 0000011xxx yes yes no b4 32 kword 0000100xxx yes yes no b5 32 kword 0000101xxx yes yes no b6 32 kword 0000110xxx yes yes no b7 32 kword 0000111xxx yes yes no b8 - b119 follow the same pattern b120 32 kword 1111000xxx yes yes no b121 32 kword 1111001xxx yes yes no b122 32 kword 1111010xxx yes yes no b123 32 kword 1111011xxx yes yes no b124 32 kword 1111100xxx yes yes no b125 32 kword 1111101xxx yes yes no b126 32 kword 1111110xxx yes yes no b127 3 , 5 4 kword 1111111000 yes yes no
? 2013 microchip technology inc. preliminary ds25002b-page 7 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b b128 4 kword 1111111001 yes yes no b129 4 kword 1111111010 yes yes no b130 4 kword 1111111011 yes yes no b131 4 kword 1111111100 yes yes no b132 4 kword 1111111101 yes yes no b133 4 kword 1111111110 yes yes yes b134 4 kword 1111111111 yes yes yes 1. each block, b0-b127 is 32kword. 2. x = 0 or 1. block address (ba) = a 21 - a 15 3. each block has an associated vpb and nvpb, except for some blocks in sst38vf6403b and sst38vf6404b. in sst38vf6403b, block b0 does not have a single vpb or nvpb for all 32 kwords. instead, each block (4 kword) in block b0 has its own vpb and nvpb. in sst38vf6404b, block b127 does not have a single vpb or nvpb for all 32 kwords. instead, each block (4 kword) in block b127 has its own vpb and nvpb. 4. the 8kword boot block consists of s0 and s1 in block b0. 5. the 8kword boot block consists of s1022 and s1023 in block b127. table 3-2: sst38vf6403b and sst38vf6404b memory maps (continued) (sheet 2 of 2)
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 8 preliminary ? 2013 microchip technology inc. 4.0 device operation the memory operations functions of these devices are initiated using commands written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. the sst38vf6401b/6402b/6403b/6404b also have the auto low power mode which puts the device in a near- standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 6 ma to typically 5 a. the device requires no access time to exit the auto low power mode after any address transition or control signal tran- sition used to initiate an other read cycle. the device does not enter auto-low power mode after power-up with ce# held steadily low, until the first address tran- sition or ce# is driven high. 4.1 read the read operation of the sst38vf6401b/6402b/ 6403b/6404b is controlled by ce# and oe#, both of which have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to figure 6-1 , the read cycle timing dia- gram, for further details. 4.2 page read the page read operation utilizes an asynchronous method that enables the system to read data from the sst38vf6401b/6402b/6403b/6404b at a faster rate. this operation allows users to read an eight-word page of data at an average speed of 33 ns per word. in page read, the initial word read from the page requires t acc to be valid, while the remaining seven words in the page require only t pacc . all eight words in the page have the same address bits, a 21 -a 3 , which are used to select the page. address bits a 2 -a 0 are tog- gled, in any order, to read the words within the page. the page read operation of the sst38vf6401b/ 6402b/6403b/6404b is controlled by ce# and oe#. both ce# and oe# must be low for the system to obtain data from the output pins. ce# controls device selec- tion. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to figure 6-2 , the page read cycle timing diagram, for further details. 4.3 word-program operation the sst38vf6401b/6402b/6403b/6404b can be pro- grammed on a word-by-word basis. before program- ming, the block where the word exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, which- ever occurs first. the program operation, once initi- ated, will be completed within 7 s. see figures 6-3 and 6-4 for we# and ce# controlled program opera- tion timing diagrams and figure 6-19 for flowcharts. during the program operation, the only valid reads are data# polling, toggle bits, and ry/by#. during the internal program operation, the host is free to perform additional tasks. any co mmands issued during the internal program operation are ignored. during the command sequence, wp# should be statically held high or low. when programming more than a few words, microchip recommends write-buffer programming. 4.4 write-buffer programming the sst38vf6401b/6402b/6403b/6404b offer write- buffer programming, a feat ure that enables faster effective word programming. to use this feature, write up to 16 words with the write-to-buffer command, then use the program buffer-to-flash command to program the write-buffer to memory. the write-to-buffer command consists of between 5 and 20 write cycles. the total number of write cycles in the write-to-buffer command sequence is equal to the number of words to be written to the buffer plus four. the first three cycles in the command sequence tell the device that a write-to-buffer operation will begin. the fourth cycle tells the device the number of words to be written into the buffer and the block address of these words. specifically, the writ e cycle consists of a block address and a data value called the word count (wc), which is the number of words to be written to the buffer minus one. if the wc is greater than 15, the maximum buffer size minus 1, then the operation aborts. for the fifth cycle, and all subsequent cycles of the write-to-buffer command, the command sequence consists of the addresses and data of the words to be written into the buffer. all of these cycles must have the same a 21 - a 4 address, otherwise the operation aborts. the number of write cycles required is equal to the number of words to be writ ten into the write-buffer, which is equal to wc plus one. the correct number of
? 2013 microchip technology inc. preliminary ds25002b-page 9 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b write cycles must be issued or the operation will abort. each write cycle decrements the write-buffer counter, even if two or more of th e write cycles have identical address values. only the final data loaded for each buf- fer location is held in the write-buffer. once the write-to-buffer command sequence is com- pleted, the program buffer-to-flash command should be issued to program the write-buffer contents to the specified block in memory. the block address (i.e. a 21 - a 15 ) in this command must match the block address in the 4th write cycle of th e write-to-buffer command or the operation aborts. see table 5-2 for details on write- to-buffer and program-buffer-to-flash commands. while issuing these command sequences, the write- buffer programming abort detection bit (dq1) indi- cates if the operation has aborted. there are several cases in which the device can abort: ? in the fourth write cycle of the write-to-buffer command, if the wc is gr eater than 15, the opera- tion aborts. ? in the fifth and all subsequent cycles of the write- to-buffer command, if the address values, a 21 - a 4 , are not identical, the operation aborts. ? if the number of write cycl es between the fifth to the last cycle of the write-to-buffer command is greater than wc +1, the operation aborts. ? after completing the write-to-buffer command sequence, issuing any command other than the program buffer-to-flash command, aborts the operation. ? loading a block address, i.e. a 21 -a 15, in the pro- gram buffer-to-flash command that does not match the block address used in the write-to-buf- fer command aborts the operation. if the write-to-buffer or program buffer-to-flash opera- tion aborts, then dq 1 = 1 and the device enters write- buffer-abort mode. to exec ute another operation, a write-to-buffer abort-reset command must be issued to clear dq 1 and return the device to standard read mode. after the write-to-buffer an d program buffer-to-flash commands are successfully issued, the programming operation can be monitored using data# polling, tog- gle bits, and ry/by#. 4.5 block-erase operations the block-erase o peration allows the system to erase the device on a block-by-block basis. the block-erase architecture is based on block size of 32 kwords. in sst38vf6401b and sst38vf6402b devices, the block-erase command can erase any 32kword block (b0-b127). for the non-uniform boot block devices, sst38vf6403b and sst38vf6404b, the block-erase command can erase any 32 kword block except the block that contains the boot area. in the boot area, block-erase only erases a 4kword block. the block-erase operation is initiated by executing a six-byte command sequence with block-erase com- mand (30h) and block address (ba) in the last bus cycle. the block address is latched on th e falling edge of the sixth we# pulse, while the command (30h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. the ry/by# pin can also be used to monitor the erase operation. for more information, see figure 6-10 for timing waveforms and figure 6-24 for the flowchart. any commands, other than erase-suspend, issued during the block-erase operation are ignored. any attempt to block-erase memory inside a block pro- tected by volatile block protection, non-volatile block protection, or wp# (low) will be ignored. during the command sequence, wp# should be statically held high or low. 4.6 erase-suspend/erase-resume commands the erase-suspend operation temporarily suspends a block-erase operation thus allowing data to be read or programmed into any block that is not engaged in an erase operation. the operat ion is executed with a one- byte command sequence with erase-suspend com- mand (b0h). the device automatically enters read mode within 20 s (max) after the erase-suspend com- mand had been issued. valid data can be read, using a read or page read operation, from any block that is not being erased. reading at an address location within erase-suspended blocks will output dq 2 tog- gling and dq 6 at ?1?. while in erase-suspend, a word- program or write-buffer programming operation is allowed anywhere except the block selected for erase- suspend. to resume a suspended block-erase operation, the system must issue the erase-resume command. the operation is executed by issuing one byte command sequence with erase-resume command (30h) at any address in the last byte sequence. when an erase operation is suspended, or re-sus- pended, after resume the cumulative time needed for the erase operation to complete is greater than the erase time of a non-suspended erase operation. if the hold time from erase-resume to the next erase- sus- pend operation is less than 200s, the accumulative erase time can become very l ong therefore, after issu- ing an erase-resume comm and, the system must wait at least 200s before issuing another erase-suspend command. the erase-resume command will be ignored until any program operations initiated during erase-suspend are complete.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 10 preliminary ? 2013 microchip technology inc. bypass mode can be entered while in erase-suspend, but only bypass word-program is available for those blocks that are not susp ended. bypass block-erase, bypass chip-erase, erase-suspend, and erase- resume are not available. in order to resume an erase operation, the bypass mo de must be exited before issuing erase-resume. fo r more information about bypass mode, see ?bypass mode? on page 13 . 4.7 chip-erase operation the sst38vf6401b/6402b/6403b/6404b devices provide a chip-erase operation, which erases the entire memory array to the ?1? state. this operation is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six-byte command sequence with chip-erase com- mand (10h) at address 555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid reads are toggle bit, data# polling, or ry/by#. see table 5-2 for the com- mand sequence, figure 6-9 for timing diagram, and figure 6-24 for the flowchart. any commands issued during the chip-erase operatio n are ignored. if wp# is low, or any vpbs or nvpbs ar e in the protect state, any attempt to execute a chip-e rase operation is ignored. during the command sequence, wp# should be stati- cally held high or low. 4.8 write operation status detection to optimize the system write cycle time, the sst38vf6401b/6402b/6403b/6404b provide two soft- ware means to detect the completion of a write (pro- gram or erase) cycle the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asyn- chronous with the system. th erefore, data# polling or toggle bit maybe be read concurrent with the comple- tion of the write cycle. if this occurs, the system may possibly get an incorrect result from the status detec- tion process. for example, valid data may appear to conflict with either dq 7 or dq 6 . to prevent false results, upon detection of failures, the software routine should loop to read the accessed location an additional two times. if both reads are valid, then the device has completed the write cycle, otherwise the failure is valid. for the write-buffer programming feature, dq 1 informs the user if either th e write-to-buffer or program buffer-to-flash operation aborts. if either operation aborts, then dq 1 = 1. dq 1 must be cleared to '0' by issuing the write-to-buffer abort reset command. the sst38vf6401b/6402b/6403b/6404b also pro- vide a ry/by# signal. this signal indicates the status of a program or erase operation. if a program or erase operat ion is attempted on a pro- tected block, the operation will abort. after the device initiates an abort, the corresponding write operation status detection bits will stay active for approximately 200ns (program or erase) before the device returns to read mode. for the status of these bits during a write operation, see table 4-1 . 4.8.1 data# polling (dq 7 ) when the sst38vf6401b/6402b/6403b/6404b are in an internal program opera tion, any attempt to read dq 7 will produce the complement of true data. for a program buffer-to-flash operation, dq7 is the comple- ment of the last word loaded in the write-buffer using the write-to-buffer command. once the program oper- ation is completed, dq 7 will produce valid data. note that even though dq 7 may have valid data immediately fol- lowing the completion of an internal write operation, the remaining data outputs may still be invalid. valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during an internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase opera- tion is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for block- or chip- erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 6-7 for data# polling timing diagram and figure 6-21 for a flowchart. 4.8.2 toggle bits (dq 6 and dq 2 ) during the internal program or erase operation, any consecutive attempts to read dq 6 will produce alternat- ing ?1?s and ?0?s, i.e., toggling between ?1? and ?0?. when the internal program or er ase operation is completed, the dq 6 bit will stop toggling, and the device is then ready for the next operation. for block- or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or ce#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-suspended block. if program operation is initiated in a block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular block is being actively erased or erase-sus- pended. table 4-1 shows detailed bit status informa- tion. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or ce#) pul se of write operation. see figure 6-8 for toggle bit timing diagram and figure 6- 21 for a flowchart.
? 2013 microchip technology inc. preliminary ds25002b-page 11 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b 4.8.3 dq 1 if an operation aborts during a write-to-buffer or pro- gram buffer-to-flash operation, dq 1 is set to ?1?. to reset dq 1 to ?0?, issue the write-to-buffer abort reset command to exit the abort state. a power-off/power-on cycle or a hardware reset (rst# = 0) will also clear dq 1 . 4.8.4 ry/by# the ry/by# pin can be used to determine the status of a program or erase operation. the ry/by# pin is valid after the rising edge of the final we# pulse in the com- mand sequence. if ry/by# = 0, then the device is actively programming or erasing. if ry/by# = 1, the device is in read mode. the ry/by# pin is an open drain output pin. this means several ry/by# can be tied together with a pull-up resistor to v dd.. 4.9 data protection the sst38vf6401b/6402b/6403b/6404b provide both hardware and software features to protect nonvolatile data from inadvertent writes. 4.9.1 hardware data protection 4.9.1.1 noise/glitch protection a we# or ce# pulse of less than 5 ns will not initiate a write cycle. 4.9.1.2 v dd power up/down detection the write operation is inhibited when v dd is less than 1.5v. 4.9.1.3 write inhibit mode forcing oe# low, ce# high, or we# high will inhibit the write operation. this prev ents inadvertent writes dur- ing power-up or power-down. 4.9.2 hardware block protection the sst38vf6402b and sst38vf6404b devices support top hardware block protection, which protects the top boot block of the device. for sst38vf6402b, the boot block consists of the top 32 kword block, and for sst38vf6404b the boot block consists of the top two 4 kword blocks (8 kword total). the sst38vf6401b and sst38vf6403b devices support bottom hardware block protection, which pro- tects the bottom boot block of the device. for sst38vf6401b, the boot block consists of the bottom 32 kword block, and for sst38vf6403b the boot block consists of the bo ttom two 4 kword blocks (8 kword total). the boot block addresses are described in table 4-2 . table 4-1: write operation status status dq 7 1 dq 6 dq 2 1 dq 1 ry/by# 2 normal operation standard program dq 7 # toggle no toggle 0 0 standard erase 0 toggle toggle n/a 0 erase-suspend mode read from erase-suspended block 1 no toggle to g g l e n / a 1 read from non- erase-suspended block data data data data 1 program dq 7 # toggle n/a n/a 0 program buffer- to-flash busy dq 7 # 3 toggle n/a 0 0 abort dq 7 # 3 toggle n/a 1 0 1. dq 7 and dq 2 require a valid address when reading status information. 2. ry/by# is an open drain pin. ry/by# is high in read mode, and read in erase-suspend mode. 3. during a program buffer-to-flash operation, the datum on the dq 7 pin is the complement of dq 7 of the last word loaded in the write-buffer using the write-to-buffer command.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 12 preliminary ? 2013 microchip technology inc. program and erase operations are prevented on the boot block when wp# is low. if wp# is left floating, it is internally held high via a pull-up resistor. when wp# is high, the boot block is unprotected, which allows pro- gram and erase operations on that area. 4.9.3 hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operation will terminate and return to read mode. when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place. see figure 6-15 for more information. the interrupted erase or program operation must be re-initiated after the device resumes normal operation mode to ensure data integrity. 4.9.4 software data protection (sdp) the sst38vf6401b/64 02b/6403b/6404b devices implement the jedec approved software data protec- tion (sdp) scheme for all data alteration operations, such as program and erase. these devices are shipped with the software data protection permanently enabled. see table 5-2 for the specific software com- mand codes. all program operations require the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing opti- mal protection from inadvertent write operations. sdp for erase operations is similar to program, but a six- byte load sequence is required for erase operations. during sdp command sequence, invalid commands will abort the device to read mode within t rc. the con- tents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp command sequence. the sst38vf6401b/6402b/6403b/6404b devices provide bypass mode, which allows for reduced pro- gram and erase command sequence lengths. in this mode, the sdp portion of program and erase com- mand sequences are omitted. see ?bypass mode? on page 13 for further details. 4.10 common flash memory interface (cfi) the sst38vf6401b/6402b /6403b/6404b contain com- mon flash memory interfac e (cfi) information that describes the characteristics of the device. in order to enter the cfi query mode, the system can write a one- byte sequence using a standard cfi query entry com- mand. once the device enter s the cfi query mode, the system can read cfi data at the addresses given in tables 5-4 through 5-7 . the system must write the cf i exit command to return to read mode. note that the cfi exit command is ignored during an internal pr ogram or erase operation. see table 5-2 for software command codes, figures 6- 12 and 6-13 for timing waveform, and figures 6-22 and 6-23 for flowcharts. 4.11 product identification the product identification mode identifies the devices as the sst38vf6401b, sst38vf6402b, sst38vf6403b, or sst38vf6404b, and the manu- facturer as microchip. see table 4-3 for specific address and data informatio n. product identification mode is accessed through software operations. the software product identificat ion operations identify the part, and can be useful when using multiple manufac- turers in the same so cket. for details, see table 5-2 for software operation, figure 6-11 for the software id entry and read timing diagram, and figure 6-22 for the software id entry command sequence flowchart. while in product identific ation mode, the read block protection status command determines if a block is protected. the status return ed indicates if the block has been protected, but does not differentiate between vol- atile block protection and non-volatile block protec- tion. see table 5-2 for further details. table 4-2: boot block address ranges product size address range bottom boot uniform sst38vf6401b 32 kw 000000h- 007fffh top boot uniform sst38vf6402b 32 kw 3f8000h- 3fffffh bottom boot non- uniform sst38vf6403b 8 kw 000000h- 001fffh top boot non- uniform sst38vf6404b 8 kw 3fe000h- 3fffffh table 4-3: product identification add data add data add data manufacturer?s id 00h bfh device id sst38vf6401b 01h 227eh 0eh 220ch 0fh 2200h sst38vf6402b 01h 227eh 0eh 220ch 0fh 2201h sst38vf6403b 01h 227eh 0eh 2210h 0fh 2200h sst38vf6404b 01h 227eh 0eh 2210h 0fh 2201h
? 2013 microchip technology inc. preliminary ds25002b-page 13 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b the read-irreversible block-lock status command indicates if the irreversible block command has been issued. if dq 0 = 0, then the irreve rsible lock command has been previously issued. in order to return to the standard read mode, the soft- ware product identification mode must be exited. the exit is accomplished by issuing the software id exit command sequence, which returns the device to the read mode. see table 5-2 for software command codes, figure 6-13 for timing waveform, and figures 6- 22 and 6-23 for flowcharts. 4.12 security id the sst38vf6401b/6402b/6403b/6404b devices offer a security id feature. the secure id space is divided into two segments ? one factory programmed 128 bit segment and one user programmable 248 word seg- ment. see table 4-4 for address information. the first segment is programmed and locked at microchip and contains a 128 bit unique id which uniquely identifies the device. the user segment is left un-programmed for the customer to program as desired. the user segment of the security id can be pro- grammed by first using the sec id entry command to enter the secure id space. once in the secure id space, for smaller data sets, use the word-program command to program data. to program larger sets of data more quickly, use the write-buffer programming feature. note that bypass mode is not available. to detect end-of-write for the sec id, read the toggle bits. do not use data# polling to detect end of write. once the programming is complete, lock the sec id by programming bit ?0? in the psr with the psr program command. locking the sec id disables any corruption of this space. note that regardless of whether or not the sec id is locked, the sec id segments can not be erased. the secure id space can be queried by executing a three-byte command sequence with enter sec id com- mand (88h) at address 555h in the last byte sequence. to exit this mode, the exit sec id command should be executed. refer to table 5-2 for software commands and figures 6-22 and 6-23 for flow charts. 4.13 bypass mode bypass mode shortens the time needed to issue pro- gram and erase commands by reducing these com- mands to two write cycles each. after using the bypass entry command to enter the bypass mode, only the bypass word-program, bypass block erase, bypass chip erase, erase-suspend, and erase-resume com- mands are available. the bypass exit command exits bypass mode. see table 5-2 for further details. entering bypass mode while already in erase-suspend limits the available commands. see ?erase-suspend/ erase-resume commands? on page 9 for more infor- mation. 4.14 protection settings register (psr) the protection settings register (psr) is a user-pro- grammable register that allows for further customiza- tion of the sst38vf6401b/6402b/6403b/6404b protection features. the 16-bit psr provides four one time programmable (otp) bits for users, each of which can be programmed individually. however, once an otp bit is programmed to ?0?, the value cannot be changed back to a ?1?. the other 12 bits of the psr are reserved. see table 4-5 for the definition of all 16-bits of the psr. note that dq 4 , dq 2 , dq 1 , dq 0 do not have to be pro- grammed at the same time. in addition, dq2 and dq1 cannot both be programmed to ?0?. the valid combina- tions of states of dq 2 and dq 1 are shown in table 4-6 . table 4-4: address range for sec id size address microchip unique id 128 bits 000h ? 007h user 248 w 008h ? 0ffh table 4-5: psr bit definitions bit default from factory definition dq 15 - dq 5 fffh reserved dq 4 1 vpb power-up / hardware reset state 0 = all protected 1 = all unprotected dq 3 1 reserved dq 2 1 password mode 0 = password only mode 1 = pass-through mode dq 1 1 pass-through mode 0 = pass-through only mode 1 = pass-through mode dq 0 1 sec id lock out bit 0 = locked 1 = unlocked table 4-6: valid dq 2 and dq 1 combinations combination definition dq 2 , dq 1 = 11 pass-through mode (factory default) dq 2, dq 1 = 10 pass-through only mode dq 2 , dq 1 = 01 password only mode dq 2 , dq 1 = 00 not allowed
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 14 preliminary ? 2013 microchip technology inc. the psr can be accessed by issuing the psr entry command. users can then use the psr program and psr read commands. the psr exit command must be issued to leave this mode. see table 5-2 for further details. 4.15 individual block protection the sst38vf6401b/6402b/6403b/6404b provide two methods for individual block protection: volatile block protection and non-volatile block protection. data in protected blocks cannot be altered. 4.15.1 volatile block protection the volatile block protecti on feature provides a faster method than non-volatile protection to protect and unprotect 32 kword blocks. each block has it?s own volatile protection bit (v pb). in the sst38vf6401b/ 6402b, the 32 kword boot bloc k also has a vpb. in the sst38vf6403b/6404b devices, each of the two 4 kword blocks in the 8 kword boot area has it's own vpb. after using the volatile block protection mode entry command to enter the volatile block protection mode, individual vpbs can be set or reset with vpb set/clear, or be read with vpb status re ad. if the vpb is ?0?, then the block is protected from program and erase. if the vpb is ?1?, then the block is unprotected. the volatile block protection exit command must be issued to exit volatile block pr otection mode. see table 5-2 for fur- ther details on the commands and figure 6-26 for a flow chart. if the device experiences a hardware reset or a power cycle, all the vpbs return to their default st ate as deter- mined by user-programmable bit dq 4 in the psr. if dq 4 is ?0?, then all vpbs def ault to ?0? (protected). if dq 4 is ?1?, then all vpbs def ault to ?1? ( unprotected). 4.15.2 non-volatile block protection the non-volatile block protec tion feature provides pro- tection to individual blocks using non-volatile protec- tion bits (nvpbs). each blo ck has it?s own non-volatile protection bit. in the sst38vf6401b/2, the 32 kword boot block also has a it's own nvpb. in the sst38vf6403b/6404b, each 4 kword block in the 8kword boot area has it's own nvpb. all nvpbs come from the factory set to ?1 ?, the unprotected state. use the non-volatile block protection mode entry com- mand to enter the non-volatile block protection mode. once in this mode, the nvpb program command can be used to protect individual blocks by setting individual nvpbs to ?0?. the time n eeded to program an nvpb is two times t bp, which is a maximum of 20s. the nvpb status read command can be used to check the pro- tection state of an individual nvpb. to change an nvpb to ?1?, the unprotected state, the nvpb must be erased using nvpbs erase command. this command erases all nvpbs to ?1? and can take up to 25 ms to complete. n vpb program should be used to set the nvpbs of any blo cks that are to be protected before exiting the non-volatile block protection mode. see table 5-2 and figure 6-27 for further details. upon a power cycle or ha rdware reset, the nvpbs retain their states. memory areas that are protected using non-volatile block pr otection remain protected. the nvpb program and n vpbs erase commands are permanently disabled once the irreversible block lock command is issued. see ?irreversible block locking? on page 15 for further information. 4.16 advanced protection the sst38vf6401b/6402b/6403b/6404b provide advanced protection features that allow users to imple- ment conditional access to the nvpbs. specifically, advanced protection uses the global lock bit to pro- tect the nvpbs. if the global lock bit is ?0? then all the nvpbs states are frozen an d cannot be modified in any mode. if the global lock bit is ?1?, then all the nvpbs can be modified in non-volatile block protection mode. after using the global lock of nvpbs entry command to enter the global lock of nvpbs mode, the global lock bit can be activated by issuing a set global lock bit command, which sets the global lock bit to ?0?. the global lock bit cannot be set to ?1? with this command. the status of the bit can be read with the global lock bit status command. use the global lock of nvpbs exit command to ex it global lock of nvpbs mode. see table 5-2 and figure 6-28 for further details. the steps used to change the global lock bit from '0' to'1,' to allow access to the nvpbs, depe nd on whether the device has been set to use pass-through or pass- word mode. when using advanced protection, select either pass-through only mode or password only mode by programming the dq 2 and dq 1 bits in the psr. although the factory default is pass-through mode (dq 2 = 1, dq 1 = 1), the user should explicitly chose either pass-through only mode (dq 2 = 1, dq 1 = 0), or password only mode (dq 2 = 0, dq 1 = 1). keep- ing the sst38vf6401b/6402b/6403b/6404b in the factory default pass-through mode leaves the device open to unauthorized changes of dq 2 and dq 1 in the psr. see ?protection settings register (psr)? on page 13 . for more information about the psr. 4.16.1 pass-through mode (dq 2 , dq 1 = 1,0) the pass-through mode allows the global lock bit state to be cleared to ?1? by a power-down power-up sequence or a hardware reset (rst# pin = 0). no pass- word is required in pass-through mode. to set the global lock bit to ?0?, use the set global lock bit command while in the global lock of nvpbs mode. select the pass-through only mode by pro- gramming psr bit dq 2 = 1 and dq 1 = 0.
? 2013 microchip technology inc. preliminary ds25002b-page 15 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b 4.16.2 password mode (dq 2 , dq 1 = 0,1) in the password mode, the global lock bit is set to ?0? by the set global lock bit command, a power-down power-up sequence, or a hardware reset (rst# pin = 0). select the password only mode by programming psr bit dq 2 = 0 and dq 1 = 1. note that when the psr program command is issued in password mode, the global lock bit is automatically set to ?0?. in contrast to the pass-through mode, in the password mode, the only way to clear the global lock bit to ?1? is to submit the correct 64-bit password using the submit password command in password commands mode. the words of the password can be submitted in any order as long as each 16 bit section of the password is matched with its correct address. after the entire 64 bit password is submitted, the device takes approximately 1 s to verify the passw ord. a subsequent submit password command cannot be issued until this verifi- cation time has elapsed. the 64-bit password must be chosen by the user before programming the dq 2 and dq 1 otp bits of the psr to choose password mode. the default 64 bit password on the device from the factory is ffffffffffffffffh. enter the password commands mode by issuing the password commands entry co mmand. then, use the password program command to program the desired password. use caution when programming the pass- word because there is no method to reset the password to ffffffffffffffffh. once a password bit has been set to ?0?, it cannot be changed back to ?1?. see table 5-2 for further details about password-related commands. the password can be read using the password read command to verify the desired password has been pro- grammed. microchip recommends testing the pass- word before permanently choosing password mode. to test the password, do the following: 1. enter the global lock of nvpbs mode. 2. set the global lock bit to ?0?, and verify the value. 3. exit the global lo ck of nvpbs mode. 4. enter the password commands mode. 5. submit the 64-bit pa ssword with the submit password command. 6. wait 2 s for the device to verify the password. 7. exit the password commands mode. 8. re-enter the global lock of nvpbs mode 9. read the global lock bit with the global lock bit status read command. the global lock bit should now be ?1?. after verifying the password, program the dq 2 and dq 1 otp bits of the psr to explicitly choose password mode. once the password mode has been selected, the password read and password program com- mands are permanently disabled. there is no longer any method for reading or modifying the password. in addition, microchip is unable to read or modify the password. if a password read command is issued while in password mode, the data presented for each word of the password is ffffh. if the password mode is not explicitly chosen in the psr, then the password can still be read and modified. therefore, microchip strong ly recommends that users explicitly choose password mode in the psr. 4.17 irreversible block locking the sst38vf6401b/6402b/6403b/6404b provides irreversible block locking, a feature that allows users to customize the size of read-only memory (rom) on the device and provides more flexibility than one-time programmable (otp) memory. applying irreversible block locking turns user-selected memory areas into rom by permanently disabling pro- gram and erase operations to these chosen areas. any area that becomes rom cannot be changed back to flash. any memory blocks in the main memory, including boot blocks, can be irreversibly locked. in non-uniform boot block devices (sst38vf6403b and sst38vf6404b) each 4 kw block in the boot area can be irreversibly locked. if desired, all blocks in the main memory can be irreversibly locked. to use irreversible block locking do the following: 1. global lock bit should be ?1?. the irreversible block lock command is disabled when global lock bit is ?0?. 2. enter the non-volatile block protection mode. 3. use the nvpb program command to protect only the blocks that are to be changed into rom. 4. exit the non-volatile block protection mode. 5. issue the irreversible block lock command (see table 5-2 for details). the irreversible block lock command can only be used once. issuing the command after the first time has no effect on the device. important: once the irreversible block lock command is used, the state of the nvpbs can no longer be changed or overridden. therefore, the following fea- tures no longer have any effect on the device: ? global lock of nvpbs feature ? password feature ? nvpb program command ? nvpb erase command ? dq2 and dq1 of psr in addition, wp# has no effect on any memory in the boot block area that has been irreversibly locked.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 16 preliminary ? 2013 microchip technology inc. to verify whether the irreversible block lock command has already been issued, ent er the product id mode and read address 5feh. if dq 0 = 0, then irreversible block lock has already been executed. when using this feature to determine if a specific block is rom, use the nvpb status read.
? 2013 microchip technology inc. preliminary ds25002b-page 17 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b 5.0 operations table 5-1: operation modes selection mode ce# oe# we# rst# wp# dq address read v il v il v ih hxd out a in program v il v ih v il hv il /v ih 1 1. wp# can be v il when programming or erasing outside of the bootblock. wp# must be v ih when programming or erasing inside the bootblock area. d in a in erase v il v ih v il hv il /v ih 1 x 2 2. x can be v il or v ih , but no other value. block address, xxh for chip-erase standby v ih xxv ih x high z x write inhibit x v il x x x high z/ d out x product identification x x v ih h x high z/ d out x reset x x x l x high z x software mode v il v ih v il h x see table 5-2 see table 5-2 table 5-2: software command sequence (sheet 1 of 3) command sequence 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle 7th bus cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 read 3 wa data page read 3 wa 0 data 0 wa 1 data 1 wa 2 data 2 wa 3 data 3 word-program 555h aah 2aah 55h 555h a0h wa data reset xxh f0h write-buffer programming write-to-buffer 4 555h aah 2aah 55h ba 25h ba wc wa x data wa x data wa x data program buf- fer-to- flash ba x 29h write-to-buffer abort-reset 555h aah 2aah 55h 555h f0h bypass mode 5 bypass mode entry 555h aah 2aah 55h 555h 20h bypass word- program xxxh a0h wa data bypass block erase xxxh 80h ba 30h bypass chip erase xxxh 80h 555h 10h bypass mode exit xxxh 90h xxxh 00h erase related block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h bax 30h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase sus- pend xxxh b0h erase resume xxxh 30h
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 18 preliminary ? 2013 microchip technology inc. security id sec id entry 6 555h aah 2aah 55h 555h 88h sec id read 3, 7 wa x data sec id exit 555h aah 2aah 55h 555h 90h xxh 00h product identification software id entry 8 555h aah 2aah 55h 555h 90h manufac- turer id 3, 9 x00 bfh device id 3, 9 x01 data read block protection status 3 bax02 10 data 11 read irre- versible block lock status 3 5feh data 12 read global lock bit status 3 9ffh data 13 software id exit /cfi exit 14 xxh f0h volatile block protection volatile block protection mode entry 555h aah 2aah 55h 555h e0h volatile pro- tection bit (vpb) set/ clear xxh a0h ba x 15 data 16 vpb status read 3 ba x data 16 volatile block protection mode exit xxh 90h xxh 00h non-volatile block protection non-volatile block protec- tion mode entry 555h aah 2aah 55h 555h c0h non-volatile protect bit (nvpb) program xxh a0h ba x 15 00h non-volatile protect bits (nvpb) erase 17 xxh 80h 00h 30h nvpb status read 3 ba x 15 data 16 non-volatile block protec- tion mode exit xxh 90h xxh 00h table 5-2: software command sequence (continued) (sheet 2 of 3) command sequence 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle 7th bus cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2
? 2013 microchip technology inc. preliminary ds25002b-page 19 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b global lock of nvpbs global lock of nvpbs entry 555h aah 2aah 55h 555h 50h set global lock bit xxh a0h xxh 00h global lock bit status read 3 xxxh data 13 global lock of nvpbs exit xxh 90h xxh 00h password commands password commands mode entry 555h aah 2aah 55h 555h 60h password pro- gram 18 xxh a0h pwa x pwd x password read 3 pwa x pwd x submit pass- word 19 00h 25h 00h 03h 00h pwd 0 01h pwd 1 02h pwd 2 03h pwd 3 00h 29h password commands mode exit xxh 90h xxh 00h program and settings register (psr) psr entry 555h aah 2aah 55h 555h 40h psr program xxh a0h xxxh data psr read 3 xxh data psr exit xxh 90h xxh 00h cfi cfi query entry 55h 98h software id exit/cfi exit 14 xxh f0h irreversible block lock irreversible block lock 20 555h aah 2aah 55h 555h 87h xxh 00h 1. address format a 10 -a 0 (hex). addresses a 11 - a 21 can be v il or v ih, but no other value, for the sst38vf6401b/6402b/ 6403b/6404b command sequence. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence 3. all read commands are in bold italics . 4. total number of cycles in this command sequence depends on the number of words to be written to the buffer. additional words are written by repeating write cycle 5. address (wa x ) values for write cycle 6 and later must have the same a21-a4 values as wa x in write cycle 5. wc = word count. the value of wc is the number of words to be written into the buffer, minus 1. maximum wc value is 15 (i.e. f hex) 5. erase-suspend and erase-resume commands are also available in bypass mode. 6. once in sec id mode, the word-program, write-buffer programming, and bypass word-progr am features can be used to program the sec id area. 7. lock-out status is read with a 7 -a 0 = ffh. unlocked: dq 3 = 1 / locked: dq 3 = 0. lock status can also be checked by reading bit ?0? in the psr. 8. the device does not remain in software product id mode if powered down. 9. with a ms -a 1 =0; microchip manufacturer id = 00bfh, is read with a 0 = 0, sst38vf6401b/6402b/6403b/6404b device ids are read with the results shown in table 4-3 on page 12 . 10. ba x02 : a ms -a 15 = block address; a 14 -a 8 = xxxxxx; a 7 -a 0 = 02 table 5-2: software command sequence (continued) (sheet 3 of 3) command sequence 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle 7th bus cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 20 preliminary ? 2013 microchip technology inc. note: ta b l e 5 - 2 uses the following abbreviations: x = don?t care (v il or v ih , but no other value. ba x = block address; uses a ms -a 15 address lines wa = word address wc = word count pwa x = password address; pwa x = pwa 0 , pwa 1 , pwa 2 or pwa 3; a1 and a0 are used to select each 16-bit portion of the password pwd x = password data; pwd x = pswd 0 , pwd 1 , pwd 2 , or pwd 3 a ms = most significant address 11. data = 00h unprotected block; data = 01h protected block. 12. dq 0 = 0 means the irreversible block loc k command has been previously used. dq 0 = 1 means the irreversible block lock command has not yet been used. 13. dq 0 = 0 means that the global lock bit is locked. dq 0 = 1 means that the global lock bit is unlocked. 14. both software id exit operations are equivalent. 15. for non-uniform boot block devices (i.e. 8 kword size), in the boot area, use ba x = block address. 16. dq 0 = 0 means protected; dq 0 = 1 means unprotected 17. erases all nvpbs to ?1? (unprotected) 18. entire two-bus cycle sequence must be entered for each portion of the password. 19. entire password sequence requi red for validation. the word order doesn?t matter as long as the address and data pair match. 20. global lock bit must be ?1? before executing this command. table 5-3: protection priority for main array nvpb 1 1. x = protect or unprotect vpb 1 protection state of block protect x protected x protect protected unprotect unprotect unprotected table 5-4: cfi query identification string 1 for sst38vf6401b/6402b/6403b/6404b 1. refer to cfi publication 100 for more details. address data description 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0002h primary oem command set 14h 0000h 15h 0040h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h
? 2013 microchip technology inc. preliminary ds25002b-page 21 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b table 5-5: system interface informatio n for sst38vf6401b/ 6402b/640 3b/6404b address data description 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min. (00h = no v pp pin) 1eh 0000h v pp max. (00h = no v pp pin) 1fh 0003h typical time out for word-program 2 n s (2 3 = 8 s) 20h 0003h typical time out for min. size buffer program 2 n s (00h = not supported) 21h 0004h typical time out for individual block-erase 2 n ms (2 4 = 16 ms) 22h 0005h typical time out for chip-erase 2 n ms (2 5 = 32 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 3 = 16 s) 24h 0003h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 5 = 64 ms) table 5-6: device geometry informatio n for sst38vf6401b/6402b/6403b/6404b address data description 27h 0017h device size = 2 n bytes (17h = 23; 2 23 = 8 mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0005h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 000xh number of erase block regions in the devi ce (01h = uniform boot device, 02h = non-uniform boot device. 2dh 00xxh erase block region 1 information 007fh, 0000h, 0000h, 0001h, for sst38vf6401b/6402b 0007h, 0000h, 0020h, 0000h for sst38vf6403b/6404b 2eh 000xh 2fh 00x0h 30h 000xh 31h erase block region 2 information 0000h, 0000h, 0000h, 0000h, for sst38vf6401b/6402b 007eh, 0000h, 0000h, 0001h for sst38vf6403b/6404b 32h 33h 34h
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 22 preliminary ? 2013 microchip technology inc. table 5-7: primary vendor-specific ext ended information for sst38vf6401b/ 6402b/6403b/6404b address data description 40h 0050h query-unique ascii string ?pri? 41h 0052h 42h 0049h 43h ffffh reserved 44h ffffh reserved 45h 0000h reserved 46h 0002h erase suspend 0 = not supported 1 = only read during erase suspend, 2 = read and program during erase suspend. 47h 0001h individual block protection 0 = not supported 1 = supported 48h 0000h reserved 49h 0008h protection 0008h = advanced 4ah 0000h simultaneous operation 00 = not supported 4bh 0000h burst mode 00 = not supported 4ch 0002h page mode 00 = not supported 02 = 8 word page. 4dh 0000h acceleration supply minimum 00 = not supported 4eh 0000h acceleration supply maximum 00 = not supported 4fh 00xxh top / bottom boot block 02h = 8 kword bottom boot 03h = 8 kword top boot 04h = uniform (32 kword) bottom boot 05h = uniform (32 kword) top boot 50h 0000h program suspend 00h = not supported 01h = supported
? 2013 microchip technology inc. preliminary ds25002b-page 23 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maxi- mum stress ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . .-2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 12.5v voltage on rst# pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 12 .5v voltage on wp# pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 1 2.5v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. table 5-8: operating range range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v table 5-9: ac conditions of test 1 1. see figures 6-17 and 6-18 input rise/fall time output load 5ns c l = 30 pf
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 24 preliminary ? 2013 microchip technology inc. 5.1 power-up specifications all functionalities and dc sp ecifications are specified for a v dd ramp rate faster than 1v per 100 ms (0v to 3v in less than 300 ms). if the v dd ramp rate is slower than 1v per 100 ms, a hardware reset is required. the recommended v dd power-up to reset# high time should be greater than 100 s to ensure a proper reset. see table 5-10 and figure 5-1 for more information. figure 5-1: power-up diagram table 5-10: recommended syst em power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or process change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to erase/program operation 100 s 25002 f37.0 v dd reset# ce# t pu-read > 100 s v dd min 0v v ih t rhr > 50ns
? 2013 microchip technology inc. preliminary ds25002b-page 25 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b 5.2 dc characteristics table 5-11: dc operating characteristics v dd = 2.7-3.6v 1 1. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperature), and v dd = 3v. not 100% tested. symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht 2 , v dd =v dd max 2. see figure 6-22 read 3 3. the i dd current listed is typically less than 2ma/mhz, with oe# at v ih. ty p i c a l v dd is 3v. 30 ma ce#=v il , oe#=we#=v ih at f= 5 mhz intra-page read @5 mhz 2.5 ma ce#=v il , oe#=we#=v ih intra-page read @40 mhz 20 ma ce#=v il , oe#=we#=v ih program and erase 35 ma ce#=we#=v il , oe#=v ih program-write-buffer- to-flash 50 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 40 a ce#=v ihc , v dd =v dd max i alp auto low power 40 a ce#=v ilc , v dd =v dd max all inputs=v ss or v dd, we#=v ihc i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i liw input leakage current on wp# pin and rst# 10 a wp#=gnd to v dd or rst#=gnd to v dd i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min table 5-12: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for initial qualification and a fter a design or process change th at could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf table 5-13: reliability characteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for initial qualification and a fter a design or process change th at could affect this paramet er. 2. n end endurance rating is qualified as 100,000 cycles minimum per block. endurance 100,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lth 1 latch up 100 + i dd ma jedec standard 78
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 26 preliminary ? 2013 microchip technology inc. 6.0 ac characteristics table 6-1: read cycle timing parameters v dd = 2.7-3.6v symbol parameter min max units t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t pacc page access time 25 ns t oe output enable access time 25 ns t clz 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t rye 1,2 2. this parameter applies to block-erase and program operations. this parameter does not apply to chip-erase operations. rst# pin low to read mode 20 s t ry 1 rst# pin low to read mode ? not during program or erase algorithms. 500 ns t rpd 1 rst# input low to standby mode 20 s t rb 1 ry / by# output high to ce# / oe# pin low 0 ns t pwd delay for each password check 1 s
? 2013 microchip technology inc. preliminary ds25002b-page 27 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b table 6-2: program/erase cycle timing parameters symbol parameter min max units t bp word-program time 10 s t wbp 1 program buffer-to-flash time 40 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 2 we# pulse width high 30 ns t cph 2 ce# pulse width high 30 ns t ds data setup time 30 ns t ceph ce# pulse width high during toggle bit polling 20 ns t oeph oe# pulse width high during toggle bit polling 20 ns t dh 2 data hold time 0 ns t ida 2 software id, volatile protect, non-volatile protect, global lock bit, password mode, lock bit, bypass entry, and exit times 150 ns t be block-erase 25 ms t sce chip-erase 50 ms t busy 2 ce# high or we# high to ry / by# low 90 ns 1. effective programming time is 2.5 s per word if 16-words are programmed during this operation. 2. this parameter is measured on ly for initial qualification and after a design or process change that could affect this paramet er.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 28 preliminary ? 2013 microchip technology inc. figure 6-1: read cycle timing diagram figure 6-2: page read timing diagram 25002 f03.1 address a ms-0 dq 15-0 we# oe# ce# data valid data valid ry/by# high-z v ih high-z t chz t ohz t olz t clz t oh t oe t ce t rc t aa t rb note: a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b address a ms-3 a 2 - a 0 dq 15-0 ce# oe# ax ax ax data v alid same page ry/by# data v alid ax t aa t pac c t pac c t pac c 25002 f24.3 data v alid note: a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b a x = either 000, 001,... 111
? 2013 microchip technology inc. preliminary ds25002b-page 29 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-3: we# controlled program cycle timing diagram t dh t wph t ds t wp t ah t as t ch t cs t busy 25002 f04.1 address a ms-0 dq 15-0 ce# sw0 sw1 sw2 555 2aa 555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp ry/by# note: a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 30 preliminary ? 2013 microchip technology inc. figure 6-4: ce# controlled program cycle timing diagram figure 6-5: we# controlled write-buffer cycle timing diagram t dh t cph t ds t cp t ah t as t ch t cs t busy 25002 f05.1 address a ms-0 dq 15-0 we# sw0 sw1 sw2 555 2aa 555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp ry/by# note: a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 25002 f34.2 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 swn 555 2aa wa x ba ba data data n xx55 xxaa xx25 wc wa x oe# ce# ry/by# fill write buffer with data t wp note: ba= block address wa x = word address wc = word count datan = nth data x can be v il or v ih, but no other value.
? 2013 microchip technology inc. preliminary ds25002b-page 31 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-6: we# controlled program-write-buffer-to-flash cycle timing diagram figure 6-7: data# polling timing diagram 25002 f35.1 address a ms-0 dq 15-0 we# ba 29h oe# ce# t busy ry/by# t dh t as t wbp t wp note: ba= block address 25002 f06.1 address a ms-0 dq 7 data data # data # data we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 32 preliminary ? 2013 microchip technology inc. figure 6-8: toggle bits timing diagram figure 6-9: we# controlled chip-erase timing diagram 25002 f07.0 address a ms-0 dq 6 and dq 2 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs t ceph t oeph note: a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b 25002 f08.1 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx10 xx55 xxaa xx80 xxaa 555 oe# ce# ry/by# t wp six-byte code for chip-erase t sce t busy note: this device also supports ce# controlled chip-erase operation the we# and ce# signals are interchangeable as long as mini mum timings are met. (see table 6-2 ) a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
? 2013 microchip technology inc. preliminary ds25002b-page 33 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-10: we# controlled block-erase timing diagram 25002 f09.1 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 555 2aa 2aa 555 555 xx55 xx30 xx55 xxaa xx80 xxaa ba x oe# ce# t busy ry/by# t be six-byte code for block-erase t wp note: this device also supports ce# controlled block-er ase operation the we# and ce# signals are inter- changeable as long as minimum timings are met. (see table 6-2 ) ba x = block address a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 34 preliminary ? 2013 microchip technology inc. figure 6-11: software id entry and read figure 6-12: cfi query entry and read 25002 f11.0 address a ms-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 note: device id = 536b for sst38vf6401b, 536a for sst38vf6402b, 536d for sst38vf6403b, 536c for sst38vf6404b a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 25002 f12.2 address a ms-0 t ida dq 15-0 we# 55h oe# ce# t wp t aa 98h note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b x can be v il or v ih, but no other value.
? 2013 microchip technology inc. preliminary ds25002b-page 35 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-13: software id exit/cfi exit figure 6-14: sec id entry 25002 f13.1 address a ms-0 dq 15-0 t ida t wp t whp we# sw0 one-byte sequence for software id exit and reset oe# ce# xxf0 note: wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b x can be v il or v ih, but no other value. 25002 f14.1 address a ms-0 t ida dq 15-0 we# sw0 sw1 sw2 555 2aa 555 oe# ce# three-byte sequence for sec id entry t wp t wph t aa xx55 xxaa xx88 note: a ms = most significant address a ms = a 21 for sst38vf6401b/6402b/6403b/6404b wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 36 preliminary ? 2013 microchip technology inc. figure 6-15: rst# timing diagram (when no internal operation is in progress) figure 6-16: rst# timing diagram ( during program or erase operation) figure 6-17: ac input/output reference waveforms 25002 f15.2 rst# ce#/oe# t rp t rhr t ry ry/by# 25002 f16.2 rst# ce#/oe# t rp t rye ry/by# t rb 25002 f17.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test
? 2013 microchip technology inc. preliminary ds25002b-page 37 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-18: a test load example 25002 f18.1 to tester to dut c l v dd 25k 25k
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 38 preliminary ? 2013 microchip technology inc. figure 6-19: word-program algorithm 25002 f19.1 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load word address word data wait for end of program program complete note: x can be v il or v ih, but no other value.
? 2013 microchip technology inc. preliminary ds25002b-page 39 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-20: write-buffer programming 25002 f25.2 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xx25h address: ba wait for end of program program complete load data: wc address: ba load data: data address: wa program buffer to flash load data: xx29h address: ba is data load complete? ye s no keep writing to buffer note: ba= block address wc = word count wa = address of word to program all subsequent address values (wa x ) in write cycle 6 and later must have the same a 21 -a 4 as wa x in write cycle 5. x can be v il or v ih, but no other value
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 40 preliminary ? 2013 microchip technology inc. figure 6-21: wait options 25002 f20.1 wait t bp , t wbp , t sce, or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated ye s no ry/by# program/erase completed is ry/by# = 1? read ry/by# program/erase initiated note: for a program buffer-to-flash operation, the valid dq 7 is from the last word loaded in the buffer using the write- to-program buffer command.
? 2013 microchip technology inc. preliminary ds25002b-page 41 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-22: cfi/sec id/software id entry command flowcharts 25002 f21.0 load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555h wait t ida read software id cfi query entry command sequence load data: xx98h address: 555h wait t ida read cfi data load data: xxaah address: 555h sec id entry command sequence load data: xx55h address: 2aah load data: xx88h address: 555h wait t ida read sec id note: x can be v il or v ih, but no other value.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 42 preliminary ? 2013 microchip technology inc. figure 6-23: software id/cfi/sec id exit command flowcharts 25002 f26.2 sec id exit command sequence cfi exit command sequence load data: xxf0h address: xxh wait t ida load data: xxaah address: 555h load data: xx55h address: 2aah load data: xx90h address: 555h load data: xx00h address: xxxh wait t ida return to normal operation return to normal operation note: x can be v il or v ih, but no other value.
? 2013 microchip technology inc. preliminary ds25002b-page 43 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-24: erase command sequence 25002 f23.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value. ba= block address
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 44 preliminary ? 2013 microchip technology inc. figure 6-25: erase suspend/resume 25002 f27.0 start erase operation load data: xxb0h address: xxxh wait time (20 s max ) erase suspend active execute valid operations while in erase suspend mode load data: xx30h address: xxxh resume erase operation note: x can be v il or v ih, but no other value.
? 2013 microchip technology inc. preliminary ds25002b-page 45 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-26: volatile block protection 25003 f28.3 load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxe0h address: 555h wait t ida load data: xxa0h address: 555h load data: data address: ba load data: xx90h address: xxxh load data: xx00h address: xxxh read data: data address: ba more blocks to protect/unprotect or read status? ye s no read protect status protect / unprotect note: data = 00h (unprotect); data = 01h (protect). ba = block address x can be v il or v ih, but no other value.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 46 preliminary ? 2013 microchip technology inc. figure 6-27: non-volatile block protect mode program (protect block) load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxc0h address: 555h wait t ida load data: xx80h address: xxh read data: data address: ba load data: xxa0h address: xxh load data: xx30h address: 00h wait for end of program, erase, or read load data: xx90h address: xxh load data: xx00h address: xxh load data: xx00h address: ba more to program,erase, or read? erase read protect status ye s no 25002 f30.1 program, erase or read note: data = 00h (unprotect); data = 01h (protect). x can be v il or v ih, but no other value. programming nvpb requires 2x t bp , which results in a 20 s maximum programming time
? 2013 microchip technology inc. preliminary ds25002b-page 47 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-28: global lock of nvpbs set load data: xxaah address: 555h load data: xx55h address: 2aah load data: xx50h address: 555h wait t ida read data: status data address: xxxh load data: xxa0h address: xxh load data: xx90h address: xxh load data: xx00h address: xxh load data: xx00h address: xxh read status 25002 f31.0 note: status data: dq0 = 0 (locked); dq0 = 1 (unlocked). x can be v il or v ih, but no other value.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 48 preliminary ? 2013 microchip technology inc. figure 6-29: password operations (program, read, submit) program load data: xxaah address: 555h load data: xx55h address: 2aah load data: xx60h address: 555h wait t ida read data: status data address: pwa x load data: xxa0h address: xxh load data: xx90h address: xxh load data: xx00h address: xxh load data: pwd x address: pwa x read 25002 f32.0 more to program or read? ye s no load data: xxaah address: 555h load data: xx55h address: 2aah load data: xx60h address: 555h load data: xx25h address: 00h load data: xx03h address: 00h load data: pwd0 address: pwa0 load data: xx29h address: 00h wait t pwd wait t ida load data: pwd1 address: pwa1 load data: pwd2 address: pwa2 load data: pwd3 address: pwa3 load data: xx90h address: xxh load data: xx00h address: xxh exit password command mode submit password program / read password note: the pwdx and pwax data and address pairs can be submitted in any order. pwd x = pwd 0 , pwd 1 , pwd 2 , pwd 3 pwa x = pwa 0 , pwa 1 ,pwa 2 , pwa 3 x can be v il or v ih, but no other value.
? 2013 microchip technology inc. preliminary ds25002b-page 49 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b figure 6-30: irrever sible block lock in main array load data: aah address: 555h load data: 55h address: 2aah load data: 87h address: 555h load data: 00h address: xxh 25002 f33.0 note: global lock bit must be ?1? before executing this command. x can be v il or v ih, but no other value.
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 50 preliminary ? 2013 microchip technology inc. 7.0 product iden tification system to order or obtain information, e.g., on pricing or deli very, refer to the factory or the listed sales office. table 7-1: part marking ordering number marking on part sst38vf6401b-70-5i-tv 38vf6401b-70-i/tv SST38VF6401B-70-5I-CD 38vf6401b-70-i/cd sst38vf6402b-70-5i-tv 38vf6402b-70-i/tv sst38vf6402b-70-5i-cd 38vf6402b-70-i/cd sst38vf6403b-70-5i-tv 38vf6403b-70-i/tv sst38vf6403b-70-5i-cd 38vf6403b-70-i/cd sst38vf6404b-70-5i-tv 38vf6404b-70-i/tv sst38vf6404b-70-5i-cd 38vf6404b-70-i/cd part no. xx xxx package endurance/ device device: sst38vf6401b = 64 mbit, 2.7-3.6v, advanced multi- purpose flash plus bottom boot-block uniform (32 kword) sst38vf6402b = 64 mbit, 2.7-3.6v, advanced multi- purpose flash plus top boot-block uniform (32 kword) sst38vf6403b = 64 mbit, 2.7-3.6v, advanced multi- purpose flash plus bottom boot-block non- uniform (8 kword) sst38vf6403b = 64 mbit, 2.7-3.6v, advanced multi- purpose flash plus top boot-block non- uniform (8 kword) tape and reel flag: t = tape and reel read access speed: 70 = 70 ns endurance: 5 = 100,000 cycles minimum temperature: i = -40c to +85c package: tv = tsop (12mm x 20mm), 48-lead cd = tfbga (6mm x 8mm), 48-lead valid combinations: sst38vf6401b-70-5i-tv sst38vf6401bt-70-5i-tv SST38VF6401B-70-5I-CD sst38vf6401bt-70-5i-cd sst38vf6402b-70-5i-tv sst38vf6402bt-70-5i-tv sst38vf6402b-70-5i-cd sst38vf6402bt-70-5i-cd sst38vf6403b-70-5i-tv sst38vf6403bt-70-5i-tv sst38vf6403b-70-5i-cd sst38vf6403bt-70-5i-cd sst38vf6404b-70-5i-tv sst38vf6404bt-70-5i-tv sst38vf6404b-70-5i-cd sst38vf6404bt-70-5i-cd xxx read temperature x tape/reel indicator access speed
? 2013 microchip technology inc. preliminary ds25002b-page 51 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b 8.0 packaging diagrams
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 52 preliminary ? 2013 microchip technology inc.
? 2013 microchip technology inc. preliminary ds25002b-page 53 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 54 preliminary ? 2013 microchip technology inc.
? 2013 microchip technology inc. preliminary ds25002b-page 55 sst38vf6401b / sst38v f6402b / sst38vf6 403b / sst38vf6404b table 8-1: revision history number description date a ? initial release aug 2011 b ? applied new document format ? revised ta b l e 5 - 7 and table 6-2 ? updated ?product identification system? on page 50 ? migrated to new package drawing style jan 2013
sst38vf6401b / sst38vf6402b / sst38vf6403b / sst38vf6404b ds25002b-page 56 preliminary ? 2013 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
? 2013 microchip technology inc. preliminary ds25002b-page 57 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, a pplication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-905-8 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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