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M48T86 5v pc real time clock november 1998 1/22 drop-in replacement for pc computer clock/calendar counts seconds, minutes, hours, days, day of the week, date, month and year with leap year compensation interfaced with software as 128 ram locations: C 14 bytes of clock and control registers C 114 bytes of general purpose ram selectable bus timing (intel/motorola) three interrupts are separately software-maskable and testable C time-of-day alarm (once/second to once/day) C periodic rates from 122 m s to 500ms C end-of-clock update cycle programmable square wave output self-contained battery and crystal in the caphat dip package packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) soic package provides direct connection for a snaphat top contains the battery and crystal pin and function compatible with bq3285/7a and ds128887 ai01640 e v cc M48T86 rcl rst v ss 8 ad0-ad7 mot r/w ds as irq sqw figure 1. logic diagram ad0-ad7 multiplexed address/data bus e chip enable input r/ w write enable input ds data strobe input as address strobe input rst reset input rcl ram clear input mot bus type select input sqw square wave output irq interrupt request output v cc supply voltage v ss ground table 1. signal names 24 1 pcdip24 (pc) battery/crystal caphat snaphat (sh) battery/crystal 28 1 soh28 (mh)
symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) C40 to 85 c t sld (2) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to 7.0 v v cc supply voltage C0.3 to 7.0 v p d power dissipation 1 w notes: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal section of this specification is not implied. exposure to the absolute maximum rating conditions for extended periods of time m ay affect reliability. 2. soldering temperature not to exceed 260 c for 10 seconds (total thermal budget not to exceed 150 c for longer than 30 seconds). caution: negative undershoots below C0.3 volts are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. table 2. absolute maximum ratings (1) ad4 ad5 ad6 nc ad1 ad2 ad3 nc ad0 sqw rst nc rcl nc nc irq ds as ad7 v ss e r/w mot v cc ai01641 M48T86 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 24 23 22 21 20 19 18 17 figure 2a. dip pin connections ai01642 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 24 23 1 ad4 ad5 ad6 nc ad1 ad2 ad3 ad0 sqw rst nc rcl nc nc irq ds as ad7 v ss e r/w mot v cc M48T86 nc nc nc nc 26 25 28 27 v ss figure 2b. soic pin connections description the M48T86 is an industry standard real time clock (rtc). the M48T86 is composed of a lithium en- ergy source, quartz crystal, write-protection cir- cuitry, and a 128 byte ram array. this provides the user with a complete subsystem packaged in either a 24-pin dip caphat or 28-pin snaphat soic. functions available to the user include a non-volatile time-of-day clock, alarm interrupts, a one-hundred-year clock with programmable inter- rupts, square wave output, and 128 bytes of non- volatile static ram. the 24 pin 600mil dip caphat ? houses the M48T86 silicon with a quartz crystal and a long life lithium button cell in a single package. the 28 pin 330mil soic provides sockets with gold plated contacts at both ends for direct connection to a separate snaphat housing containing the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. the snaphat housing is keyed to prevent reverse insertion. the soic and battery packages are shipped sepa- rately in plastic anti-static tubes or in tape & reel form. warning: nc = not connected. warning: nc = not connected. 2/22 M48T86
ai01643 oscillator bcd/binary increment e / 8 / 64 / 64 periodic interrupt/square wave selector square wave output power switch and write protect ad0-ad7 registers a,b,c,d clock calendar, and alarm ram storage registers (114 bytes) clock/ calendar update bus interface v cc v bat v cc pok ds r/w as sqw rst irq double buffered rcl figure 3. block diagram for the 28 lead soic, the battery/crystal package part number is "m4t28-br12sh1". automatic deselection of the device provides insur- ance that data integrity is not compromised should v cc fall below specified power-fail deselect volt- age (v pfd ) levels. the automatic deselection of the device remains in effect upon power up for a period of 200ms (max) after v cc rises above v pfd , provided that the real time clock is running and the count down chain is not reset. this allows sufficient time for v cc to stabilize and gives the system clock a wake up period so that a valid system reset can be established. the block diagram in figure 3 shows the pin connections and the major internal functions of the M48T86. signal description v cc , v ss . dc power is provided to the device on these pins. the M48T86 utilizes a 5v v cc . sqw (square wave output). during normal op- eration (i.e. valid v cc ), the sqw pin can output a signal from one of 13 taps. the frequency of the sqw pin can be changed by programming regis- ter a as shown in table 10. the sqw signal can be turned on and off using the sqwe bit (register b; bit 3). the sqw signal is not available when v cc is less than v pfd . 3/22 M48T86
ad0-ad7 (multiplexed bi-directional ad- dress/data bus). the M48T86 provides a multi- plexed bus in which address and data information share the same signal path. the bus cycle consists of two stages; first the address is latched, followed by the data. address/data multiplexing does not slow the access time of the M48T86, since the bus change from address to data occurs during the internal ram access time. addresses must be valid prior to the falling edge of as, at which time the M48T86 latches the address present on ad0-ad7. valid write data must be present and held stable during the latter portion of the r/ w pulse. in a read cycle, the M48T86 outputs 8 bits of data during the latter portion of the ds pulse. the read cycle is terminated and the bus returns to a high impedance state upon a high transition on r/ w. as (address strobe input). a positive going pulse on the address strobe (as) input serves to demultiplex the bus. the falling edge of as causes the address present on ad0-ad7 to be latched within the M48T86. mot (mode select). the mot pin offers the flexi- bility to choose between two bus types. when connected to vcc, motorola bus timing is selected. when connected to v ss or left disconnected, intel bus timing is selected. the pin has an internal pull-down resistance of approximately 20k ohms. ds (data strobe input). the ds pin is also re- ferred to as read (rd). a falling edge transition on the data strobe (ds) input enables the output during a a read cycle. this is very similar to an output enable ( g) signal on other memory devices. e (chip enable input). the chip enable pin must be asserted low for a bus cycle in the M48T86 to be accessed. bus cycles which take place without asserting e will latch the addresses present, but no data access will occur. irq (interrupt request output). the irq pin is an open drain output that can be used as an interrupt input to a processor. the irq output remains low as long as the status bit causing the interrupt is present and the corresponding inter- rupt-enable bit is set. irq returns to a high imped- ance state whenever register c is read. the rst pin can also be used to clear pending interrupts. because the irq bus is an open drain output, it requires an external pull-up resistor to v cc. rst (reset input). the M48T86 is reset when the rst input is pulled low. with a valid v cc applied and a low on rst, the following events occur: 1. periodic interrupt enable (pie) bit is cleared to a zero. (register b; bit 6) 2. alarm interrupt enable (aie) bit is cleared to a zero. (register b; bit 5) 3. update ended interrupt request (uf) bit is cleared to a zero. (register c; bit 4) 4. interrupt request (irqf) bit is cleared to a zero. (register c bit 7) 5. periodic interrupt flag (pf) bit is cleared to a zero. (register c; bit 6) 6. the device is not accessible until rst is re- turned high. 7. alarm interrupt flag (af) bit is cleared to a zero. (register c; bit 5) 8. the irq pin is in the high impedance state. 9. square wave output enable (sqwe) bit is cleared to zero. (register b; bit 3). 10.update ended interrupt enable (uie) is cleared to a zero. (register b; bit 4) rcl (ram clear). the rcl pin is used to clear all 114 storage bytes, excluding clock and control registers, of the array to ff(hex) value. the array will be cleared when the rcl pin is held low for at least 100ms with the oscillator running. usage of this pin does not affect battery load. this function is applicable only when v cc is applied. r/ w (read/write input). the r/ w pin is utilized to latch data into the M48T86 and provides function- ality similar to w in other memory systems. address map the address map of the M48T86 is shown in figure 9. it consists of 114 bytes of user ram, 10 bytes of ram that contain the rtc time, calendar and alarm data, and 4 bytes which are used for control and status. all bytes can be read or written to except for the following: 1. registers c & d are read-only. 2. bit 7 of register a is read-only. the contents of the four registers a, b, c, and d are described in the "registers" section. 4/22 M48T86
address rtc bytes range decimal binary bcd 0 seconds 0-59 00-3b 00-59 1 seconds alarm 0-59 00-3b 00-59 2 minutes 0-59 00-3b 00-59 3 minutes alarm 0-59 00-3b 00-59 4 hours, 12-hrs 1-12 01-0c am 81-8c pm 01-12 am 81-92 pm hours, 24-hrs 0-23 00-17 00-23 5 hours alarm, 12-hrs 1-12 01-0c am 81-8c pm 01-12 am 81-92 pm hours alarm, 24-hrs 0-23 00-17 00-23 6 day of week (1=sun) 1-7 01-07 01-07 7 day of month 1-31 01-1f 01-31 8 month 1-12 01-0c 01-12 9 year 0-99 00-63 00-99 table 3. time, calendar and alarm formats time, calendar, and alarm locations the time and calendar information is obtained by reading the appropriate memory bytes. the time, calendar, and alarm registers are set or initialized by writing the appropriate ram bytes. the contents of the time, calendar, and alarm bytes can be either binary or binary-coded decimal (bcd) format. before writing the internal time, calendar,and alarm register, the set bit (register b; bit 7) should be written to a logic "1". this will prevent updates from occurring while access is being attempted. in ad- dition to writing the time, calendar, and alarm reg- isters in a selected format (binary or bcd), the data mode (dm) bit (register b; bit 2), must be set to the appropriate logic level ("1" signifies binary data; "0" signifies binary coded decimal (bcd data). all time, calendar, and alarm bytes must use the same data mode. the set bit should be cleared after the data mode bit has been written to allow the real time clock to update the time and calendar bytes. once initialized, the real time clock makes all updates in the selected mode. the data mode cannot be changed without reinitializing the ten data bytes. table 3 shows the binary and bcd formats of the time, calendar, and alarm locations. the 24/12 bit (register b; bit 1) cannot be changed without reinitializing the hour locations. when the 12-hour format is selected, a logic one in the high order bit of the hours byte represents pm. the time, calendar, and alarm bytes are always acces- sible because they are double buffered. once per second the ten bytes are advanced by one second and checked for an alarm condition. if a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc. may not correlate. however, the probability of reading incorrect time and calendar data is low. methods of avoiding possible incorrect time and calendar reads are reviewed later in this text. non-volatile ram the 114 general purpose non-volatile ram bytes are not dedicated to any special function within the M48T86. they can be used by the processor pro- gram as non-volatile memory and are fully acces- sible during the update cycle. 5/22 M48T86
ai01644 5v 50pf 960 w for all outputs except irq 510 w figure 4a. ac testing load circuit input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v note that output hi-z is defined as the point where data is no longer driven. table 4. ac measurement conditions ai01645 5v 130pf 1.15k w irq figure 4b. ac testing load circuit symbol parameter test condition min max unit i li (1) input leakage current 0v v in v cc 1 m a i lo (1) output leakage current 0v v out v cc 1 m a i cc supply current outputs open 15 ma v il input low voltage C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 4ma 0.4 v output low voltage ( irq) i ol = 0.5ma 0.4 v v oh output high voltage i oh = C1ma 2.4 v note: 1. output deselected. table 6. dc characteristics (1) (t a = 0 to 70 c; v cc = 4.5v to 5.5v) symbol parameter test condition min max unit c in input capacitance v in = 0v 7 pf c io (3) input / output capacitance v out = 0v 5 pf notes: 1. effective capacitance measured with power supply at 5v. 2. sampled only, not 100% tested. 3. outputs deselected table 5. capacitance (1, 2) (t a = 25 c, f = 1 mhz ) 6/22 M48T86
symbol parameter min typ max unit v pfd power-fail deselect voltage (M48T86) 4.0 4.35 v v so battery back-up switchover voltage 3.0 v t dr (2) expected data retention time 10 years notes: 1. all voltages referenced to v ss . 2. at 25c table 7. power down/up trip points dc characteristics (1) (t a = 0 to 70 c) symbol parameter min max unit t f (1) v cc fall time 300 m s t r v cc rise time 100 m s t rec v pfd to e high 20 200 ms note :1.v cc fall time of less than t f may result in deselection/write protection not occurring until 200 m s after v cc passes v pfd . table 8. power down/up mode ac characteristics (t a = 0 to 70 c) ai01646 v cc e tf tr trec 4.5v v pfd v so figure 5. power down/up mode ac waveforms interrupts the rtc plus ram includes three separate, fully automatic sources of interrupt (alarm, periodic, up- date-in-progress) available to a processor. the alarm interrupt can be programmed to occur at rates from once per second to once per day. the periodic interrupt can be selected from rates of 500ms to 122 m s. the update-ended interrupt can be used to indicate that an update cycle has com- pleted. the processor program can select which interrupts, if any, are going to be used. three bits in register b enable the interrupts. writing a logic "1" to an interrupt-enable bit (register b; bit 6=pie; bit 5=aie; bit 4=uie) permits an interrupt to be initial- ized when the event occurs. a zero in an interrupt- enable bit prohibits the irq pin from being asserted from that interrupt condition. if an interrupt flag is already set when an interrupt is enabled, irq is immediately set at an active level, although the 7/22 M48T86
interrupts (contd) interrupt initiating the event may have occurred much earlier. as a result, there are cases where the program should clear such earlier initiated inter- rupts before first enabling new interrupts. when an interrupt event occurs, the related flag bit (register c; bit 6=pf; bit 5=af; bit 4=uf) is set to a logic "1". these flag bits are set independent of the state of the corresponding enable bit in register b and can be used in a polling mode without enabling the corresponding enable bits. the inter- rupt flag bits are status bits which software can interrogate as necessary. when a flag is set, an indication is given to software that an interrupt event has occurred since the flag bit was last read; however, care should be taken when using the flag bits as all are cleared each time register c is read. double latching is included with register c so that bits which are set, remain stable throughout the read cycle. all bits which are set high are cleared when read. any new interrupts which are pending during the read cycle are held until after the cycle is completed. one, two, or three bits can be set when reading register c. each utilized flag bit should be examined when read to ensure that no interrupts are lost. the second flag bit usage method is with fully enabled interrupts. when an interrupt flag bit is set and the corresponding enable bit is also set, the irq pin is asserted low. irq is asserted as long as at least one of the three interrupt sources has its flag and enable bits both set. the irqf bit (register c; bit 7) is a "1" whenever the irq pin is being driven low. determination that the rtc initi- ated an interrupt is accomplished by reading reg- ister c. a logic "1" in the irqf bit indicates that one or more interrupts have been initiated by the M48T86. the act of reading register c clears all active flag bits and the irqf bit. symbol parameter M48T86 unit min typ max t cyc cycle time 160 ns t dsl pulse width, data strobe low or r/ w high 80 ns t dsh pulse width, data strobe high or r/ w low 55 ns t rwh r/ w hold time 0 ns t rws r/ w setup time 10 ns t cs chip select setup time 5 ns t ch chip select hold time 0 ns t dhr read data hold time 0 25 ns t dhw write data hold time 0 ns t as address setup time 20 ns t ah address hold time 5 ns t das delay time, data strobe to address strobe rise 10 ns t asw pulse width address strobe high 30 ns t asd delay time, address strobe to data strobe rise 35 ns t od output data delay time from data strobe rise 50 ns t dw write setup time 30 ns t buc delay time before update cycle 244 m s t pi (1) periodic interrupt time interval C C C t uc time of update cycle 1 m s note: 1. see table 10. table 9. ac characteristics (t a = 0 to 70 c; v cc = 4.5v to 5.5v) 8/22 M48T86
ai01647 tcyc tasd tasw as e ad0-ad7 tdsl tdsh tdas tcs tod tch tas tah tdhr ds r/w figure 6. intel bus read mode ac waveforms ai01648 tcyc tasd tasw as e ad0-ad7 tdsl tdsh tdas tcs tdw tch tas tah tdhw ds r/w figure 7. intel bus write enable ac waveforms 9/22 M48T86
ai01649 tasd tasw as e ad0-ad7 (write) tcyc tdsh tdas tcs trwh tas tdhw ds r/w tdsl trws tch ad0-ad7 (read) tdw tah tah tas tod tdhr figure 8. motorola bus read/write mode ac waveforms periodic interrupt the periodic interrupt will cause the irq pin to go to an active state from once every 500 ms to once every 122 m s. this function is separate from the alarm interrupt which can be output from once per second to once per day. the periodic interrupt rate is selected using the same register a bits which select the square wave frequency (see table 10). changing the register a bits affects both the square wave frequency and the periodic interrupt output. however, each function has a separate enable bit in register b. the periodic interrupt is enabled by the pie bit (register b; bit 6). the periodic interrupt can be used with software count- ers to measure inputs, create output intervals, or await the next needed software function. alarm interrupt the alarm interrupt provides the system processor with an interrupt when a match is made between the rtcs hours, minutes, and seconds bytes and the corresponding alarm bytes. the three alarm bytes can be used in two ways. first, when the alarm time is written in the appro- priate hours, minutes, and seconds alarm loca- tions, the alarm interrupt is initiated at the specified time each day if the alarm interrupt enable bit (register b; bit 5) is high. the second use is to insert a "dont care" state in one or more of the three alarm bytes. the "dont care" code is any hexa- decimal value from c0 to ff. the two most signifi- cant bits of each byte set the "dont care" condition when at logic "1". an alarm will be generated each hour when the "dont care" is are set in the hours byte. similarly, an alarm is generated every minute with "dont care" codes in the hour and minute alarm bytes. the "dont care" codes in all three alarm bytes create an interrupt every second. 10/22 M48T86
ai01650 seconds seconds alarm minutes minutes alarm hours hours alarm day of week date of month month year register a register b register c register d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 bcd or binary format 00 0d 0e 7f 0 13 14 127 114 bytes 14 bytes clock and control status registers storage registers figure 9. address map update cycle interrupt after each update cycle, the update cycle ended flag bit (uf) (register c; bit 4) is set to a "1". if the update interrupt enable bit (uie) (register b; bit 4) is set to a "1", and the set bit (register b; bit 7) is a "0", then an interrupt request is generated at the end of each update cycle. square wave output selection thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block diagram of figure 3. the purpose of selecting a divider tap is to generate a square wave output signal on the sqw pin. the rs3-rs0 bits in register a estab- lish the square wave output frequency. these frequencies are listed in table 10. the sqw fre- quency selection shares the 1-of-15 selector with the periodic interrupt generator. once the fre- quency is selected, the output of the sqw pin can be turned on and off under program control with the square wave enabled (sqwe). oscillator control bits when the M48T86 is shipped from the factory the internal oscillator is turned off. this feature pre- vents the lithium energy cell from being discharged until it is installed in a system. a pattern of "010" in bits 4-6 of register a will turn the oscillator on and enable the countdown chain. a pattern of "11x" will turn the oscillator on, but holds the countdown chain of the oscillator in reset. all other combina- tions of bits 4-6 keep the oscillator off. 11/22 M48T86
register a bits square wave periodic interrupt rs3 rs2 rs1 rs0 frequency units period units 0000none none 0001256hz3. 90625 ms 0010128hz7. 8125 ms 00118.192khz 122.070 us 01004.096khz 244.141 us 01012.048khz 488.281 us 01101.024khz 976.5625 us 0111512hz1. 953125 ms 1000256hz3. 90625 ms 1001128hz7. 8125 ms 101064hz15.625ms 101132hz31.25ms 110016hz62.5ms 11018hz125ms 11104hz250ms 11112hz500ms table 10. square wave frequency/periodic interrupt rate update cycle the M48T86 executes an update cycle once per second regardless of the set bit (register b; bit 7). when the set bit is asserted, the user copy of the double buffered time, calendar, and alarm bytes is frozen and will not update as the time increments. however, the time countdown chain continues to update the internal copy of the buffer. this feature allows accurate time to be maintained, inde- pendent of reading and writing the time, calendar, and alarm buffers. this also guarantees that the time and calendar information will be consistent. the update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a "dont care" code is present in all three positions. there are three methods of accessing the real time clock that will avoid any possibility of obtaining inconsistent time and calendar data. the first method uses the update-ended interrupt. if en- abled, an interrupt occurs after every update cycle which indicates that over 999ms are available to read valid time and date information. if this inter- rupt is used, the irqf bit (register c; bit 7) should be cleared before leaving the interrupt routine. a second method uses the update-in-progress (uip) bit (register a; bit 7) to determine if the update cycle is in progress. the uip bit will pulse once per second. after the uip bit goes high, the update transfer occurs 244 m s later. if a low is read on the uip bit, the user has at least 244 m s before the time/calendar data will be changed. therefore, the user should avoid interrupt service routines that would cause the time needed to read valid time/cal- endar data to exceed 244 m s. the third method uses a periodic interrupt to de- termine if an update cycle is in progress. the uip bit is set high between the setting of the pf bit (register c; bit 6). periodic interrupts that occur at a rate greater than t buc allow valid time and date information to be reached at each occurrence of the periodic interrupt. the reads should be com- pleted within 1/(t pl/2 + t buc ) to ensure that data is not read during the update cycle. 12/22 M48T86
ai01651 uip update period (1sec) tbuc tuc figure 10. update period timing and uip ai01652 uip update period (1sec) pf uf tpl/2 tpl/2 tpl tbuc tuc figure 11. update-ended/periodic interrupt relationship 13/22 M48T86
uip. update in progress the update in progress (uip) bit is a status flag that can be monitored. when the uip bit is one, the update transfer will not occur for at least 244 m s. the time, calendar, and alarm information in ram is fully available for access when the uip bit is zero. the uip bit is read only and is not affected by rst. writing the set bit in register b to a "1" inhibits any update transfer and clears the uip status bit. osc0, osc1, osc2. oscillator control these three bits are used to control the oscillator and reset the countdown chain. a pattern of "010" enables operation by turning on the oscillator and enabling the divider chain. a pattern of 11x turns the oscillator on, but keeps the frequency divider disabled. when "010" is written, the first update begins after 500ms. rs3, rs2, rs1, rs0 these four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. the tap selected may be used to generate an output square wave (sqw pin) and/or a periodic interrupt. the user may do one of the following: 1. enable the interrupt with the pie bit; or 2. enable the sqw output with the sqwe bit; or 3. enable both at the same time and same rate; or 4. enable neither. table 10 lists the periodic interrupt rates and the square wave frequencies that may be chosen with the rs bits. these four read/write bits are not affected by rst. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uip osc2 osc1 osc0 rs3 rs2 rs1 rs0 register a msb 14/22 M48T86
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set pie aie uie sqwe dm 24/12 dse register b msb set when the set bit is a zero, the update transfer functions normally by advancing the counts once per second. when the set bit is written to a one, any update transfer is inhibited and the program may initialize the time and calendar bytes without an update occurring. read cycles can be executed in a similar manner. set is a read/write bit which is not modified by rst or internal functions of the M48T86. pie. periodic interrupt enable the periodic interrupt enable bit (pie) is a read/write bit which allows the periodic interrupt flag (pf) bit register c to cause the irq pin to be driven low. when the pie bit is set to one, periodic interrupts are generated by driving the irq pin low at a rate specified by the rs3-rs0 bits of register a. a zero in the pie bit blocks the irq output from being driven by a periodic interrupt, but the periodic flag (pf) bit is still set at the periodic rate. pie is not modified by any internal M48T86 functions, but is cleared to zero on rst. aie. alarm interrupt enable the alarm interrupt enable (aie) bit is a read/write bit which, when set to a one, permits the alarm flag (af) bit in register c to assert irq. an alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes including a "dont care" alarm code of binary 1xxxxxxx. when the aie bit is set to zero, the af bit does not initate the irq signal. the rst pin clears aie to zero. the internal functions of the M48T86 do not affect the aie bit. uie. update ended interrupt enable the update ended interrupt enable (uie) bit is a read/write bit which enables the update end flag (uf) bit in register c to assert irq. a transition low on the rst pin or the set bit going high clears the uie bit. sqwe. square wave enable when the square wave enable (sqwe) bit is set to a one, a square wave signal is driven out on the sqw pin. the frequency is determined by the rate-selection bits rs3-rs0. when the sqwe bit is set to zero, the sqw pin is held low. the sqwe bit is cleared by the rst pin. sqwe is a read/write bit. dm. data mode the data mode (dm) bit indicates whether time and calendar information are in binary or bcd format. the dm bit is set by the program to the appropriate format and can be read as required. this bit is not modified by internal function or rst. a one in dm signifies binary data and a zero specifies binary coded decimal (bcd) data. 24/12 the 24/12 control bit establishes the format of the hours byte. a one indicates the 24-hour mode and a zero indicates the 12-hour mode. this bit is read/write and is not affected by internal functions or rst. dse. daylight savings enable the daylight savings enable (dse) bit is a read/write bit which enables two special updates when set to a one. on the first sunday in april, the time increments from 1:59:59am to 3:00:00 am. on the last sunday in october, when the time reaches 1:59:59 am, it changes to 1:00:00 am. these special updates do not occur when the dse bit is a zero. this bit is not affected by internal functions or rst. 15/22 M48T86
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irqf pf af uf 0 0 0 0 register c msb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vrt0000000 register d msb irqf. interrupt request flag the interrupt request flag (irqf) bit is set to a one when one or more of the following are true: pf=pie=1 af=aie=1 uf=uie=1 (i.e. irqf=pf*pie+af*aie+uf*uie) pf. periodic interrupt flag the periodic interrupt flag (pf) is a read-only bit which is set to a one when an edge is detected on the selected tap of the divider chain. the rs3-rs0 bits establish the periodic rate. pf is set to a one independent of the state of the pie bit. the irq signal is active and will set the irqf bit. the pf bit is cleared by a rst or a software read of register c. af. alarm flag a one in the af (alarm interrupt flag) bit indicates that the current time has matched the alarm time. if the aie bit is also a one, the irq pin will go low and a one will appear in the irqf bit. a rst or a read of register c will clear af. uf. update ended interrupt flag the update ended interrupt flag (uf) bit is set after each update cycle. when the uie bit is set to a one, the one in the uf bit causes the irqf bit to be a one. this will assert the irq pin. uf is cleared by reading register c or an rst. bit 0 through 3. unused bits bit 3-bit 0 are unused. these bits always read zero and cannot be written. vrt. valid ram and time the valid ram and time (vrt) bit is set to the one state by stmicroelectronics prior to shipment. this bit is not writable and should always be a one when read. if a zero is ever present, an exhausted inter- nal lithium cell is indicated and both the contents of the rtc data and ram data are questionable. this bit is unaffected by rst. bit 0 through 6. unused bits the remaining bits of register d are not usable. they cannot be written and when read, they will always read zero. 16/22 M48T86
ai02169 v cc 0.1 m f device v cc v ss figure 14. supply voltage protection power supply decoupling and under- shoot protection i cc transients, including those produced by output switching, can produce voltage fluctuations, result- ing in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy, which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic bypass capaci- tor value of 0.1 m f (as shown in figure 14) is recommended in order to provide the needed filter- ing. in addition to transients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommeded to connect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. 17/22 M48T86
ordering information scheme package pc pcdip24 mh (1) soh28 temp. range 1 0 to 70 c shipping method for soic blank tubes tr tape &reel example: M48T86 mh 1 tr note: 1. the soic package (soh28) requires the battery/crystal package (snaphat) which is ordered separately under the part number "m4t28-br12sh1" in plastic tube or "m4t28-br12sh1tr" in tape & reel form. caution: do not place the snaphat battery/crystal package "m4t28-br12sh1" in conductive foam since this will drain the lithium button-cell battery. for a list of available options (package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. 18/22 M48T86
pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3 symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.36 8.89 0.329 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 34.29 34.80 1.350 1.370 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 25.15 30.73 0.990 1.210 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n24 24 drawing is not to scale. pcdip24 - 24 pin plastic dip, battery caphat 19/22 M48T86
soh e n d c l a1 a 1 h a cp be a2 eb symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e1.27C C0.050C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n28 28 cp 0.10 0.004 drawing is not to scale. soh28 - 28 lead plastic small outline, battery snaphat 20/22 M48T86
sh a1 a d e ea eb a2 b l a3 symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 sh - snaphat housing for 28 lead plastic small outline drawing is not to scale. 21/22 M48T86
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics product s are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved ? timekeeper and snaphat are registered trademarks of stmicroelectronics ? caphat is a trademark of stmicroelectronics stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 22/22 M48T86

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