1. general description the CBTL05023 is a multiplexer/demultiplexer switch chip for displayport v1.2 signals and the control signals of a 10 gbit/s channel. the 10 gbit/s channel does not pass through this switch. this chip provides biasout output control signal, and the dc-biasing pull-down resistors to fac ilitate an external 10 gbit/s channel. the aux mux is a 2 : 1 switch with ca_det ect pin selecting between aux and ddc (direct display control) signals. the dp mux is a 2 : 1 switch that selects between dpml (displayport main link) and lstx/lsrx signals. this chip also includes three control signal buffers: hpdout, ca_detout and biasout. CBTL05023 is powered by a 3.3 v supply and it is available in 3 mm 3 mm hvqfn24 package with 0.4 mm pitch. 2. features and benefits 2.1 aux mux 2 : 1 switch ? this 2 : 1 switch is controlled by ca_d et signal multiplexing of the 1 mbit/s differential aux and ddc (direc t display control) signals ? when ca_det is high, ddc path is selected ? differential aux channel: ? low insertion loss: ? 0.5 db at 5 mhz ? low return loss: ? 19 db at 5 mhz ? low on-state resistance: 7.5 ? bandwidth: 5 ghz ? low off-state isolation: ? 75 db at 5 mhz ? low crosstalk: ? 40 db at 5 mhz ? common-mode input voltage v ic : 0 v to 3.3 v ? differential input voltage v id : 1.4 v (maximum) ? ddc channel has ddc_clk and ddc_dat i 2 c signals ? 100 khz 3.3 v voltage swing ? both auxio+ and auxio ? outputs have 900 ( 20 %) pull-down resistor that is enabled by the status of the biasout output pin ? these pull-down resistors provide dc bias for the 10 gbit/s channel CBTL05023 multiplexer/demultiplexer swit ch for thunderbol t applications rev. 2 ? 15 august 2012 product brief
CBTL05023 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product brief rev. 2 ? 15 august 2012 2 of 4 nxp semiconductors CBTL05023 multiplexer/de-multiplexer switch for thunderbolt applications 2.2 dp mux 2 : 1 switch the dp mux is a 2:1 switch that is controlled by dp_pd pin mu ltiplexing of a differential dpml signal and lstx/lsrx signals ? the dpml (displayport main link) runs up to hbr2 data rate of 5.4 gbit/s ? the low speed dc coupled signals lstx an d lsrx are 3.3 v single-ended signals that operated at 1 mbit/s ? 5.4 gbit/s dpml channel: ? low insertion loss for dp-dpmlo path: ? 2.0 db at 2.5 ghz ? low insertion loss for ls-dpmlo path: ? 2.0 db at 2.5 ghz ? low return loss fo r dp-dpmlo path: ? 15 db at 2.5 ghz ? low return loss fo r ls-dpmlo path: ? 14 db at 2.5 ghz ? low on-state resistance for dp-dpmlo path: 9 ? low on-state resistance for ls-dpmlo path: 13 ? high bandwidth: 7 ghz ? low off-state isolation: ? 20 db at 2.5 ghz ? low crosstalk: ? 25 db at 2.5 ghz ? common-mode input voltage v ic : 0 v to 3.3 v ? differential input voltage v id : 1.4 v (maximum) 2.3 general ? the input of the hpdout (hug plug detect output) buffer is 5 v tolerant ? hpdout, ca_detout and biasout buffers ? ca_det input leakage current < 0.1 a to prevent driving the 1 m pull-down to a high level ? biasout buffer is able to provide enough cu rrent to drive the bias circuit for the pin diode path ? biasout buffer can drive up to six sets of bias circuits for the 10 gbit/s paths ? when auxio_en is low or (biasin = 0 and dp_pd = 1), this chip is in sleep mode ? auxio+ and auxio ? of aux mux are disabled ? ca_detout and hpdout buffers are on ? when the chip is in sleep m ode, CBTL05023 will consume < 3.5 mw ? patent-pending high-bandwidth analog pass-gate technology ? very low intra-pair differ ential skew (5 ps typical) ? all channels have back current protection ? all channels support rail-to-rail input voltage ? cmos input buffe r with hysteresis ? single 3.3 v 10 % power supply ? hvqfn24 3 mm 3 mm package, 0.4 mm pitch, with exposed center pad for thermal relief and electrical ground ? esd: 2500 v hbm, 1250 v cdm ? operating temperature range: 0 c to 85 c
CBTL05023 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product brief rev. 2 ? 15 august 2012 3 of 4 nxp semiconductors CBTL05023 multiplexer/de-multiplexer switch for thunderbolt applications 3. ordering information [1] maximum package height is 1 mm. 4. pinning information 4.1 pinning table 1. ordering information type number package name description version CBTL05023bs hvqfn24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3 3 0.85 mm [1] sot905-1 center pad is connected to printed-circui t board ground plane for electrical grounding and thermal relief. fig 1. pin configuration for hvqfn24 002aag230 17 transparent top view v dd hpd 24 biasout 23 auxio? 22 auxio+ 20 dpmlo? 19 dpmlo+ 18 ca_det 21 gnd terminal 1 index area CBTL05023bs 15 lstx 14 lsrx 13 ca_detout 16 biasin 3 1 v dd 4 ddc_dat 5 ddc_clk 2 auxio_en dp_pd 6 aux? 7 aux+ 8 dp? 10 dp+ 11 hpdout 12 gnd 9
CBTL05023 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product brief rev. 2 ? 15 august 2012 4 of 4 nxp semiconductors CBTL05023 multiplexer/de-multiplexer switch for thunderbolt applications 5. package outline fig 2. package outline sot905-1 (hvqfn24) references outline version european projection issue date iec jedec jeita - - - sot905-1 06-03-13 06-03-31 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included unit a (1) max mm 1 0.05 0.00 0.25 0.15 0.45 0.35 0.2 3.1 2.9 2.05 1.75 0.35 0.15 a 1 dimensions (mm are the original dimensions) hvqfn24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3 x 3 x 0.85 mm 0 1.5 3 mm scale b b 1 c d (1) d h 3.1 2.9 2.05 1.75 e (1) e h e 0.4 e 2 1.8 e 1 1.8 l 0.1 0.0 l 1 0.3 0.2 lc v 0.1 w 0.05 y 0.05 y 1 0.1 - - - - - - sot905-1 c y c y 1 x terminal 1 index area b a d e detail x a a 1 c e 2 e b e 1 e a c b v m c w m terminal 1 index area b 1 b 1 lc lc l e h d h l 1 6 5 1 13 17 71112 24 23 19 18 ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 15 august 2012 document identifier: CBTL05023
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