1 ? fn3690.10 ha5351 64ns sample and hold amplifier the ha5351 is a fast acquisition, wide bandwidth sample and hold amplifier, built with the intersil hbc-10 bicmos process. this sample and hold amplifier offers a combination of desirable features; fast acquisition time (70ns to 0.01% maximum), excellent dc precision and extremely low power dissipation, making it ideal fo r use in systems that sample multiple signals and require low power. the ha5351 is in an open loop configuration with fully differential inputs providing flexibility for user defined feedback. in unity gain the ha5351 is completely self-contained and requires no external components. the on-chip 15pf hold capacitor is completely isolated to minimizing droop rate and reducing sensitivity to pedestal error. the ha5351 is available in 8 lead soic package for minimizing board space and ease of layout. functional diagram features ? fast acquisition to 0.01%. . . . . . . . . . . . . . . . . 70ns (max) ? low offset error . . . . . . . . . . . . . . . . . . . . . . . 2mv (max) ? low pedestal error. . . . . . . . . . . . . . . . . . . . 10mv (max) ? low droop rate . . . . . . . . . . . . . . . . . . . . . . 2 v/ s (max) ? wide unity gain bandwidth . . . . . . . . . . . . . . . . . . 40mhz ? low power dissipation . . . . . . . . . . . . . . . .220mw (max) ? total harmonic distortion (hol d mode) . . . . . . . . . -72dbc -(v in = 5v p-p at 1mhz) ? fully differential inputs ? on chip hold capacitor ? pb-free plus anneal available (rohs compliant) applications ? synchronous sampling ? wide bandwidth a/d conversion ? deglitching ? peak detection ? high speed dc restore pinout ha5351 (8 ld soic) top view ordering information part number part marking temp. range (c) package pkg. dwg. # ha5351ib 5351 i -40 to +85 8 ld soic m8.15 HA5351IBZ (note) 5351 ibz -40 to +85 8 ld soic (pb-free) m8.15 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-fr ee soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ha5351 g m buffer a v + 8 1 5 -in +in s /h out 15pf 4 63 v+ v- 7 gnd - - + +in nc v- out 1 2 3 4 8 7 6 5 -in gnd v+ s /h ctrl data sheet april 12, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003, 2006, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn3690.10 april 12, 2007 absolute maximum rati ngs thermal information voltage between v+ and v- terminals. . . . . . . . . . . . . . . . . . . .+11v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v voltage between sample and hold control and ground. . . . . +5.5v output current, continuous . . . . . . . . . . . . . . . . . . . . . . . . . . 37ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, note 1) ja (c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 maximum junction temperature (plastic package) . . . . . . . +150c maximum storage temperature range . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications test conditions: v supply = 5v; c h = internal = 15pf, digital input: v il = 0v (sample), v ih = 4.0v (hold). non-inverting unity gain configuration (output tied to -input), c l = 5pf, unless otherwise specified parameter test conditions temp. (c) min typ max units input characteristics input voltage range full -2.5 - +2.5 v input resistance (note 2) 25 100 500 - k input capacitance 25 - - 5 pf input offset voltage 25 -2 - 2 mv full -3.0 - 3.0 mv offset voltage temperature coefficient full - 15 - v/c bias current full - 2.5 5 a offset current full -1.5 - +1.5 a common mode range full -2.5 - +2.5 v common mode rejection ratio 2.5v, note 3 full 60 80 - db transfer characteristics large signal voltage gain v out = 2.5v 25 95 108 - db full 85 - - db unity gain -3db bandwidth 25 - 40 - mhz transient response rise time 200mv step 25 - 8.5 - ns overshoot 200mv step 25 0 - 30 % slew rate 5v step full 88 105 - v/ s digital input characteristics input voltage v ih 25, 85 2.1 - 5.0 v -40 2.4 - 5.0 v v il full 0 - 0.8 v input current v il = 0v full -1.0 - 1.0 a v ih = 5v full -1.0 - 1.0 a output characteristics output voltage r l = 510 full -3.0 - +3.0 v output current r l = 100 25, 85 20 25 - ma -40 15 - - ma full power bandwidth 5v p-p , a v = +1, -3db full - 13 - mhz output resistance hold mode 25 - 0.02 - total output noise (dc to 10mhz) sample mode 25 - 325 - v rms hold mode 25 - 325 - v rms ha5351
3 fn3690.10 april 12, 2007 distortion characteristics sample mode total harmonic distortion v in = 4.5v p-p , f in = 100khz 25 - -80 - dbc v in = 5v p-p , f in = 1mhz 25 - -74 - dbc v in = 1v p-p , f in = 10mhz 25 - -57 - dbc signal to noise ratio (rms signal to rms noise) v in = 4.5v p-p , f in = 100khz 25 - 73 - db hold mode (50% duty cycle s/h) total harmonic distortion v in = 4.5v p-p , f in = 100khz, f s ? 100khz 25 - -78 - dbc v in = 5v p-p , f in = 1mhz, f s ? 1mhz 25 - -72 - dbc v in = 1v p-p , f in = 10mhz, f s ? 1mhz 25 - -51 - dbc signal to noise ratio (rms signal to rms noise) v in = 4.5v p-p , f in = 100khz, f s ? 100khz 25 - 70 - db sample and hold characteristics acquisition time 0v to 2.0v step to 1mv 25 - 53 - ns 0v to 2.0v step to 0.01% ( 200 v) 25 - 64 70 ns -2.5v to +2.5v step to 0.01% ( 500 v) 25 - 90 100 ns droop rate 25 - 0.3 - v/ s full -2 - 2 v/ s hold step error v il = 0v, v ih = 4.0v, t r = 5ns full -10 - + 10 mv hold mode settling time to 1mv 25 - 50 - ns hold mode feedthrough 5v p-p , 500khz, sine 25 - 72 - db eadt (effective aperture delay time) 25 - +1 - ns aperture time (note 2) 25 - 10 - ns aperture uncertainty 25 - 10 20 ps power supply characteristics positive supply current full - 20 22 ma negative supply current full - 20 22 ma psrr 10% delta full 60 74 - db notes: 2. derived from computer simulation only, not tested. 3. +cmrr is measured from 0v to +2.5v, -cmrr is measured from 0v to -2.5v. electrical specifications test conditions: v supply = 5v; c h = internal = 15pf, digital input: v il = 0v (sample), v ih = 4.0v (hold). non-inverting unity gain configuration (output tied to -input), c l = 5pf, unless otherwise specified (continued) parameter test conditions temp. (c) min typ max units ha5351
4 fn3690.10 april 12, 2007 typical performance curves figure 1. large signal response figure 2. small signal response figure 3. unity gain frequency respons e figure 4. closed loop gain/phase a v = +1000 figure 5. 5v p-p full power frequency response figure 6. -3db bandwidth vs supply voltage 2 0 -2 0 100 200 300 400 500 time (ns) output (v) 0.1 0.0 -0.1 200 400 600 time (ns) output (v) 100k 1m 10m 100m 2 0 -2 -4 -6 -8 frequency (hz) gain (db) 40.163156mhz -3db 1k 10k 100k 1m 10m 100m frequency (hz) 60 40 20 0 -20 0 -30 -60 -90 -120 -150 -180 phase () gain (db) 2 2 0db at 21.34mhz gain phase -119.86 10k 100k 1m 10m 100m 2 0 -2 -4 -6 -8 2 frequency (hz) gain (db) 13.241189mhz -3db 3.5 4 4.5 5 5.5 6 0 10 20 30 40 50 60 supply voltage (v) -3db bandwidth (mhz) 4 typical units 200mv p-p ha5351
5 fn3690.10 april 12, 2007 figure 7. droop rate vs temperature figure 8. slew rate vs temperature figure 9. rise time vs temperature figure 10. hold mode settling vs temperature figure 11. pedestal vs s/h control rise time fig ure 12. acquisition time (0.01%, 0v to 2v step) typical performance curves (continued) -50 0 50 100 0 0.1 0.2 0.3 0.4 0.5 temperature (c) droop rate ( v/ s) 3 typical units -50 0 50 100 80 90 100 110 120 130 140 150 160 temperature (c) slew rate (v/ s) unit #2 unit #3 unit #1 3 typical units -slew rate +slew rate -50 0 50 100 4 5 6 7 8 9 temperature (c) rise time (ns) 4 typical units -50 0 50 100 30 35 40 45 50 55 60 65 temperature (c) hold mode settling time (ns) 4 typical units 0 1020304050 -2 -1 0 1 2 3 s /h control rise time (ns) pedestal error (mv) 0v to 4v s /h ctrl 0.01 0.00 -0.01 3.0e-7 0 5 10 time (ns) output (v) s /h control (v) 67.25ns output s /h control ha5351
6 fn3690.10 april 12, 2007 die characteristics substrate potential: v- transistor count: 156 metallization mask layout ha5351 figure 13. hold mode settling time ( 200 v) typical performance curves (continued) 0.02 0.00 -0.02 -0.04 0 20406080 0 5 10 time (ns) 51.4 ns output (v) s /h control (v) output +in -in v- v- v- v out v out s /h control v+ v+ v+ gnd gnd gnd ha5351
7 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn3690.10 april 12, 2007 ha5351 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05
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